1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Christian König. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Christian König 25 */ 26 #include <linux/hdmi.h> 27 #include <linux/gcd.h> 28 #include <drm/drmP.h> 29 #include <drm/radeon_drm.h> 30 #include "radeon.h" 31 #include "radeon_asic.h" 32 #include "radeon_audio.h" 33 #include "r600d.h" 34 #include "atom.h" 35 36 /* 37 * HDMI color format 38 */ 39 enum r600_hdmi_color_format { 40 RGB = 0, 41 YCC_422 = 1, 42 YCC_444 = 2 43 }; 44 45 /* 46 * IEC60958 status bits 47 */ 48 enum r600_hdmi_iec_status_bits { 49 AUDIO_STATUS_DIG_ENABLE = 0x01, 50 AUDIO_STATUS_V = 0x02, 51 AUDIO_STATUS_VCFG = 0x04, 52 AUDIO_STATUS_EMPHASIS = 0x08, 53 AUDIO_STATUS_COPYRIGHT = 0x10, 54 AUDIO_STATUS_NONAUDIO = 0x20, 55 AUDIO_STATUS_PROFESSIONAL = 0x40, 56 AUDIO_STATUS_LEVEL = 0x80 57 }; 58 59 static struct r600_audio_pin r600_audio_status(struct radeon_device *rdev) 60 { 61 struct r600_audio_pin status = {}; 62 uint32_t value; 63 64 value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL); 65 66 /* number of channels */ 67 status.channels = (value & 0x7) + 1; 68 69 /* bits per sample */ 70 switch ((value & 0xF0) >> 4) { 71 case 0x0: 72 status.bits_per_sample = 8; 73 break; 74 case 0x1: 75 status.bits_per_sample = 16; 76 break; 77 case 0x2: 78 status.bits_per_sample = 20; 79 break; 80 case 0x3: 81 status.bits_per_sample = 24; 82 break; 83 case 0x4: 84 status.bits_per_sample = 32; 85 break; 86 default: 87 dev_err(rdev->dev, "Unknown bits per sample 0x%x, using 16\n", 88 (int)value); 89 status.bits_per_sample = 16; 90 } 91 92 /* current sampling rate in HZ */ 93 if (value & 0x4000) 94 status.rate = 44100; 95 else 96 status.rate = 48000; 97 status.rate *= ((value >> 11) & 0x7) + 1; 98 status.rate /= ((value >> 8) & 0x7) + 1; 99 100 value = RREG32(R600_AUDIO_STATUS_BITS); 101 102 /* iec 60958 status bits */ 103 status.status_bits = value & 0xff; 104 105 /* iec 60958 category code */ 106 status.category_code = (value >> 8) & 0xff; 107 108 return status; 109 } 110 111 /* 112 * update all hdmi interfaces with current audio parameters 113 */ 114 void r600_audio_update_hdmi(struct work_struct *work) 115 { 116 struct radeon_device *rdev = container_of(work, struct radeon_device, 117 audio_work); 118 struct drm_device *dev = rdev->ddev; 119 struct r600_audio_pin audio_status = r600_audio_status(rdev); 120 struct drm_encoder *encoder; 121 bool changed = false; 122 123 if (rdev->audio.pin[0].channels != audio_status.channels || 124 rdev->audio.pin[0].rate != audio_status.rate || 125 rdev->audio.pin[0].bits_per_sample != audio_status.bits_per_sample || 126 rdev->audio.pin[0].status_bits != audio_status.status_bits || 127 rdev->audio.pin[0].category_code != audio_status.category_code) { 128 rdev->audio.pin[0] = audio_status; 129 changed = true; 130 } 131 132 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 133 if (!radeon_encoder_is_digital(encoder)) 134 continue; 135 if (changed || r600_hdmi_buffer_status_changed(encoder)) 136 r600_hdmi_update_audio_settings(encoder); 137 } 138 } 139 140 /* enable the audio stream */ 141 void r600_audio_enable(struct radeon_device *rdev, 142 struct r600_audio_pin *pin, 143 u8 enable_mask) 144 { 145 u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL); 146 147 if (!pin) 148 return; 149 150 if (enable_mask) { 151 tmp |= AUDIO_ENABLED; 152 if (enable_mask & 1) 153 tmp |= PIN0_AUDIO_ENABLED; 154 if (enable_mask & 2) 155 tmp |= PIN1_AUDIO_ENABLED; 156 if (enable_mask & 4) 157 tmp |= PIN2_AUDIO_ENABLED; 158 if (enable_mask & 8) 159 tmp |= PIN3_AUDIO_ENABLED; 160 } else { 161 tmp &= ~(AUDIO_ENABLED | 162 PIN0_AUDIO_ENABLED | 163 PIN1_AUDIO_ENABLED | 164 PIN2_AUDIO_ENABLED | 165 PIN3_AUDIO_ENABLED); 166 } 167 168 WREG32(AZ_HOT_PLUG_CONTROL, tmp); 169 } 170 171 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev) 172 { 173 /* only one pin on 6xx-NI */ 174 return &rdev->audio.pin[0]; 175 } 176 177 void r600_hdmi_update_acr(struct drm_encoder *encoder, long offset, 178 const struct radeon_hdmi_acr *acr); 179 void r600_hdmi_update_acr(struct drm_encoder *encoder, long offset, 180 const struct radeon_hdmi_acr *acr) 181 { 182 struct drm_device *dev = encoder->dev; 183 struct radeon_device *rdev = dev->dev_private; 184 185 /* DCE 3.0 uses register that's normally for CRC_CONTROL */ 186 uint32_t acr_ctl = ASIC_IS_DCE3(rdev) ? DCE3_HDMI0_ACR_PACKET_CONTROL : 187 HDMI0_ACR_PACKET_CONTROL; 188 WREG32_P(acr_ctl + offset, 189 HDMI0_ACR_SOURCE | /* select SW CTS value */ 190 HDMI0_ACR_AUTO_SEND, /* allow hw to sent ACR packets when required */ 191 ~(HDMI0_ACR_SOURCE | 192 HDMI0_ACR_AUTO_SEND)); 193 194 WREG32_P(HDMI0_ACR_32_0 + offset, 195 HDMI0_ACR_CTS_32(acr->cts_32khz), 196 ~HDMI0_ACR_CTS_32_MASK); 197 WREG32_P(HDMI0_ACR_32_1 + offset, 198 HDMI0_ACR_N_32(acr->n_32khz), 199 ~HDMI0_ACR_N_32_MASK); 200 201 WREG32_P(HDMI0_ACR_44_0 + offset, 202 HDMI0_ACR_CTS_44(acr->cts_44_1khz), 203 ~HDMI0_ACR_CTS_44_MASK); 204 WREG32_P(HDMI0_ACR_44_1 + offset, 205 HDMI0_ACR_N_44(acr->n_44_1khz), 206 ~HDMI0_ACR_N_44_MASK); 207 208 WREG32_P(HDMI0_ACR_48_0 + offset, 209 HDMI0_ACR_CTS_48(acr->cts_48khz), 210 ~HDMI0_ACR_CTS_48_MASK); 211 WREG32_P(HDMI0_ACR_48_1 + offset, 212 HDMI0_ACR_N_48(acr->n_48khz), 213 ~HDMI0_ACR_N_48_MASK); 214 } 215 216 /* 217 * build a HDMI Video Info Frame 218 */ 219 void r600_set_avi_packet(struct radeon_device *rdev, u32 offset, 220 unsigned char *buffer, size_t size); 221 void r600_set_avi_packet(struct radeon_device *rdev, u32 offset, 222 unsigned char *buffer, size_t size) 223 { 224 uint8_t *frame = buffer + 3; 225 226 WREG32(HDMI0_AVI_INFO0 + offset, 227 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 228 WREG32(HDMI0_AVI_INFO1 + offset, 229 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 230 WREG32(HDMI0_AVI_INFO2 + offset, 231 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 232 WREG32(HDMI0_AVI_INFO3 + offset, 233 frame[0xC] | (frame[0xD] << 8) | (buffer[1] << 24)); 234 235 WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset, 236 HDMI0_AVI_INFO_LINE(2)); /* anything other than 0 */ 237 238 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, 239 HDMI0_AVI_INFO_SEND | /* enable AVI info frames */ 240 HDMI0_AVI_INFO_CONT); /* send AVI info frames every frame/field */ 241 242 } 243 244 /* 245 * build a Audio Info Frame 246 */ 247 static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder, 248 const void *buffer, size_t size) 249 { 250 struct drm_device *dev = encoder->dev; 251 struct radeon_device *rdev = dev->dev_private; 252 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 253 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 254 uint32_t offset = dig->afmt->offset; 255 const u8 *frame = (const u8*)buffer + 3; 256 257 WREG32(HDMI0_AUDIO_INFO0 + offset, 258 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 259 WREG32(HDMI0_AUDIO_INFO1 + offset, 260 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24)); 261 } 262 263 /* 264 * test if audio buffer is filled enough to start playing 265 */ 266 static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder) 267 { 268 struct drm_device *dev = encoder->dev; 269 struct radeon_device *rdev = dev->dev_private; 270 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 271 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 272 uint32_t offset = dig->afmt->offset; 273 274 return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0; 275 } 276 277 /* 278 * have buffer status changed since last call? 279 */ 280 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder) 281 { 282 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 283 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 284 int status, result; 285 286 if (!dig->afmt || !dig->afmt->enabled) 287 return 0; 288 289 status = r600_hdmi_is_audio_buffer_filled(encoder); 290 result = dig->afmt->last_buffer_filled_status != status; 291 dig->afmt->last_buffer_filled_status = status; 292 293 return result; 294 } 295 296 /* 297 * write the audio workaround status to the hardware 298 */ 299 void r600_hdmi_audio_workaround(struct drm_encoder *encoder) 300 { 301 struct drm_device *dev = encoder->dev; 302 struct radeon_device *rdev = dev->dev_private; 303 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 304 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 305 uint32_t offset = dig->afmt->offset; 306 bool hdmi_audio_workaround = false; /* FIXME */ 307 u32 value; 308 309 if (!hdmi_audio_workaround || 310 r600_hdmi_is_audio_buffer_filled(encoder)) 311 value = 0; /* disable workaround */ 312 else 313 value = HDMI0_AUDIO_TEST_EN; /* enable workaround */ 314 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, 315 value, ~HDMI0_AUDIO_TEST_EN); 316 } 317 318 void r600_hdmi_audio_set_dto(struct radeon_device *rdev, 319 struct radeon_crtc *crtc, unsigned int clock); 320 void r600_hdmi_audio_set_dto(struct radeon_device *rdev, 321 struct radeon_crtc *crtc, unsigned int clock) 322 { 323 struct radeon_encoder *radeon_encoder; 324 struct radeon_encoder_atom_dig *dig; 325 326 if (!crtc) 327 return; 328 329 radeon_encoder = to_radeon_encoder(crtc->encoder); 330 dig = radeon_encoder->enc_priv; 331 332 if (!dig) 333 return; 334 335 if (dig->dig_encoder == 0) { 336 WREG32(DCCG_AUDIO_DTO0_PHASE, 24000 * 100); 337 WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); 338 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ 339 } else { 340 WREG32(DCCG_AUDIO_DTO1_PHASE, 24000 * 100); 341 WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100); 342 WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */ 343 } 344 } 345 346 void r600_set_vbi_packet(struct drm_encoder *encoder, u32 offset); 347 void r600_set_vbi_packet(struct drm_encoder *encoder, u32 offset) 348 { 349 struct drm_device *dev = encoder->dev; 350 struct radeon_device *rdev = dev->dev_private; 351 352 WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset, 353 HDMI0_NULL_SEND | /* send null packets when required */ 354 HDMI0_GC_SEND | /* send general control packets */ 355 HDMI0_GC_CONT); /* send general control packets every frame */ 356 } 357 358 void r600_set_audio_packet(struct drm_encoder *encoder, u32 offset); 359 void r600_set_audio_packet(struct drm_encoder *encoder, u32 offset) 360 { 361 struct drm_device *dev = encoder->dev; 362 struct radeon_device *rdev = dev->dev_private; 363 364 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, 365 HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */ 366 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ 367 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */ 368 HDMI0_60958_CS_UPDATE, /* allow 60958 channel status fields to be updated */ 369 ~(HDMI0_AUDIO_SAMPLE_SEND | 370 HDMI0_AUDIO_DELAY_EN_MASK | 371 HDMI0_AUDIO_PACKETS_PER_LINE_MASK | 372 HDMI0_60958_CS_UPDATE)); 373 374 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, 375 HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ 376 HDMI0_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ 377 378 WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset, 379 HDMI0_AUDIO_INFO_LINE(2), /* anything other than 0 */ 380 ~HDMI0_AUDIO_INFO_LINE_MASK); 381 382 WREG32_AND(HDMI0_GENERIC_PACKET_CONTROL + offset, 383 ~(HDMI0_GENERIC0_SEND | 384 HDMI0_GENERIC0_CONT | 385 HDMI0_GENERIC0_UPDATE | 386 HDMI0_GENERIC1_SEND | 387 HDMI0_GENERIC1_CONT | 388 HDMI0_GENERIC0_LINE_MASK | 389 HDMI0_GENERIC1_LINE_MASK)); 390 391 WREG32_P(HDMI0_60958_0 + offset, 392 HDMI0_60958_CS_CHANNEL_NUMBER_L(1), 393 ~(HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK | 394 HDMI0_60958_CS_CLOCK_ACCURACY_MASK)); 395 396 WREG32_P(HDMI0_60958_1 + offset, 397 HDMI0_60958_CS_CHANNEL_NUMBER_R(2), 398 ~HDMI0_60958_CS_CHANNEL_NUMBER_R_MASK); 399 } 400 401 void r600_set_mute(struct drm_encoder *encoder, u32 offset, bool mute); 402 void r600_set_mute(struct drm_encoder *encoder, u32 offset, bool mute) 403 { 404 struct drm_device *dev = encoder->dev; 405 struct radeon_device *rdev = dev->dev_private; 406 407 if (mute) 408 WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE); 409 else 410 WREG32_AND(HDMI0_GC + offset, ~HDMI0_GC_AVMUTE); 411 } 412 413 /** 414 * r600_hdmi_update_audio_settings - Update audio infoframe 415 * 416 * @encoder: drm encoder 417 * 418 * Gets info about current audio stream and updates audio infoframe. 419 */ 420 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder) 421 { 422 struct drm_device *dev = encoder->dev; 423 struct radeon_device *rdev = dev->dev_private; 424 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 425 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 426 struct r600_audio_pin audio = r600_audio_status(rdev); 427 uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE]; 428 struct hdmi_audio_infoframe frame; 429 uint32_t offset; 430 uint32_t value; 431 ssize_t err; 432 433 if (!dig->afmt || !dig->afmt->enabled) 434 return; 435 offset = dig->afmt->offset; 436 437 DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n", 438 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped", 439 audio.channels, audio.rate, audio.bits_per_sample); 440 DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n", 441 (int)audio.status_bits, (int)audio.category_code); 442 443 err = hdmi_audio_infoframe_init(&frame); 444 if (err < 0) { 445 DRM_ERROR("failed to setup audio infoframe\n"); 446 return; 447 } 448 449 frame.channels = audio.channels; 450 451 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); 452 if (err < 0) { 453 DRM_ERROR("failed to pack audio infoframe\n"); 454 return; 455 } 456 457 value = RREG32(HDMI0_AUDIO_PACKET_CONTROL + offset); 458 if (value & HDMI0_AUDIO_TEST_EN) 459 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, 460 value & ~HDMI0_AUDIO_TEST_EN); 461 462 WREG32_OR(HDMI0_CONTROL + offset, 463 HDMI0_ERROR_ACK); 464 465 WREG32_AND(HDMI0_INFOFRAME_CONTROL0 + offset, 466 ~HDMI0_AUDIO_INFO_SOURCE); 467 468 r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer)); 469 470 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, 471 HDMI0_AUDIO_INFO_CONT | 472 HDMI0_AUDIO_INFO_UPDATE); 473 } 474 475 /* 476 * enable the HDMI engine 477 */ 478 void r600_hdmi_enable(struct drm_encoder *encoder, bool enable); 479 void r600_hdmi_enable(struct drm_encoder *encoder, bool enable) 480 { 481 struct drm_device *dev = encoder->dev; 482 struct radeon_device *rdev = dev->dev_private; 483 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 484 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 485 u32 hdmi = HDMI0_ERROR_ACK; 486 487 if (!dig || !dig->afmt) 488 return; 489 490 /* Older chipsets require setting HDMI and routing manually */ 491 if (!ASIC_IS_DCE3(rdev)) { 492 if (enable) 493 hdmi |= HDMI0_ENABLE; 494 switch (radeon_encoder->encoder_id) { 495 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 496 if (enable) { 497 WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN); 498 hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA); 499 } else { 500 WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN); 501 } 502 break; 503 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 504 if (enable) { 505 WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN); 506 hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA); 507 } else { 508 WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN); 509 } 510 break; 511 case ENCODER_OBJECT_ID_INTERNAL_DDI: 512 if (enable) { 513 WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN); 514 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA); 515 } else { 516 WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN); 517 } 518 break; 519 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 520 if (enable) 521 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA); 522 break; 523 default: 524 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n", 525 radeon_encoder->encoder_id); 526 break; 527 } 528 WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi); 529 } 530 531 if (rdev->irq.installed) { 532 /* if irq is available use it */ 533 /* XXX: shouldn't need this on any asics. Double check DCE2/3 */ 534 if (enable) 535 radeon_irq_kms_enable_afmt(rdev, dig->afmt->id); 536 else 537 radeon_irq_kms_disable_afmt(rdev, dig->afmt->id); 538 } 539 540 dig->afmt->enabled = enable; 541 542 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", 543 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); 544 } 545