1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Christian König. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Christian König 25 */ 26 #include <linux/hdmi.h> 27 #include <drm/drmP.h> 28 #include <uapi_drm/radeon_drm.h> 29 #include "radeon.h" 30 #include "radeon_asic.h" 31 #include "r600d.h" 32 #include "atom.h" 33 34 /* 35 * HDMI color format 36 */ 37 enum r600_hdmi_color_format { 38 RGB = 0, 39 YCC_422 = 1, 40 YCC_444 = 2 41 }; 42 43 /* 44 * IEC60958 status bits 45 */ 46 enum r600_hdmi_iec_status_bits { 47 AUDIO_STATUS_DIG_ENABLE = 0x01, 48 AUDIO_STATUS_V = 0x02, 49 AUDIO_STATUS_VCFG = 0x04, 50 AUDIO_STATUS_EMPHASIS = 0x08, 51 AUDIO_STATUS_COPYRIGHT = 0x10, 52 AUDIO_STATUS_NONAUDIO = 0x20, 53 AUDIO_STATUS_PROFESSIONAL = 0x40, 54 AUDIO_STATUS_LEVEL = 0x80 55 }; 56 57 static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = { 58 /* 32kHz 44.1kHz 48kHz */ 59 /* Clock N CTS N CTS N CTS */ 60 { 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */ 61 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ 62 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ 63 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ 64 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ 65 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ 66 { 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */ 67 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ 68 { 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */ 69 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ 70 { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */ 71 }; 72 73 /* 74 * calculate CTS value if it's not found in the table 75 */ 76 static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq) 77 { 78 if (*CTS == 0) 79 *CTS = clock * N / (128 * freq) * 1000; 80 DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n", 81 N, *CTS, freq); 82 } 83 84 struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock) 85 { 86 struct radeon_hdmi_acr res; 87 u8 i; 88 89 for (i = 0; r600_hdmi_predefined_acr[i].clock != clock && 90 r600_hdmi_predefined_acr[i].clock != 0; i++) 91 ; 92 res = r600_hdmi_predefined_acr[i]; 93 94 /* In case some CTS are missing */ 95 r600_hdmi_calc_cts(clock, &res.cts_32khz, res.n_32khz, 32000); 96 r600_hdmi_calc_cts(clock, &res.cts_44_1khz, res.n_44_1khz, 44100); 97 r600_hdmi_calc_cts(clock, &res.cts_48khz, res.n_48khz, 48000); 98 99 return res; 100 } 101 102 /* 103 * update the N and CTS parameters for a given pixel clock rate 104 */ 105 static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) 106 { 107 struct drm_device *dev = encoder->dev; 108 struct radeon_device *rdev = dev->dev_private; 109 struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); 110 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 111 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 112 uint32_t offset = dig->afmt->offset; 113 114 WREG32(HDMI0_ACR_32_0 + offset, HDMI0_ACR_CTS_32(acr.cts_32khz)); 115 WREG32(HDMI0_ACR_32_1 + offset, acr.n_32khz); 116 117 WREG32(HDMI0_ACR_44_0 + offset, HDMI0_ACR_CTS_44(acr.cts_44_1khz)); 118 WREG32(HDMI0_ACR_44_1 + offset, acr.n_44_1khz); 119 120 WREG32(HDMI0_ACR_48_0 + offset, HDMI0_ACR_CTS_48(acr.cts_48khz)); 121 WREG32(HDMI0_ACR_48_1 + offset, acr.n_48khz); 122 } 123 124 /* 125 * build a HDMI Video Info Frame 126 */ 127 static void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, 128 void *buffer, size_t size) 129 { 130 struct drm_device *dev = encoder->dev; 131 struct radeon_device *rdev = dev->dev_private; 132 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 133 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 134 uint32_t offset = dig->afmt->offset; 135 uint8_t *frame = (uint8_t*)buffer + 3; 136 uint8_t *header = buffer; 137 138 WREG32(HDMI0_AVI_INFO0 + offset, 139 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 140 WREG32(HDMI0_AVI_INFO1 + offset, 141 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 142 WREG32(HDMI0_AVI_INFO2 + offset, 143 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 144 WREG32(HDMI0_AVI_INFO3 + offset, 145 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); 146 } 147 148 /* 149 * build a Audio Info Frame 150 */ 151 static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder, 152 const void *buffer, size_t size) 153 { 154 struct drm_device *dev = encoder->dev; 155 struct radeon_device *rdev = dev->dev_private; 156 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 157 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 158 uint32_t offset = dig->afmt->offset; 159 const u8 *frame = (const u8*)buffer + 3; 160 161 WREG32(HDMI0_AUDIO_INFO0 + offset, 162 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 163 WREG32(HDMI0_AUDIO_INFO1 + offset, 164 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24)); 165 } 166 167 /* 168 * test if audio buffer is filled enough to start playing 169 */ 170 static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder) 171 { 172 struct drm_device *dev = encoder->dev; 173 struct radeon_device *rdev = dev->dev_private; 174 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 175 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 176 uint32_t offset = dig->afmt->offset; 177 178 return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0; 179 } 180 181 /* 182 * have buffer status changed since last call? 183 */ 184 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder) 185 { 186 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 187 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 188 int status, result; 189 190 if (!dig->afmt || !dig->afmt->enabled) 191 return 0; 192 193 status = r600_hdmi_is_audio_buffer_filled(encoder); 194 result = dig->afmt->last_buffer_filled_status != status; 195 dig->afmt->last_buffer_filled_status = status; 196 197 return result; 198 } 199 200 /* 201 * write the audio workaround status to the hardware 202 */ 203 static void r600_hdmi_audio_workaround(struct drm_encoder *encoder) 204 { 205 struct drm_device *dev = encoder->dev; 206 struct radeon_device *rdev = dev->dev_private; 207 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 208 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 209 uint32_t offset = dig->afmt->offset; 210 bool hdmi_audio_workaround = false; /* FIXME */ 211 u32 value; 212 213 if (!hdmi_audio_workaround || 214 r600_hdmi_is_audio_buffer_filled(encoder)) 215 value = 0; /* disable workaround */ 216 else 217 value = HDMI0_AUDIO_TEST_EN; /* enable workaround */ 218 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, 219 value, ~HDMI0_AUDIO_TEST_EN); 220 } 221 222 void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock) 223 { 224 struct drm_device *dev = encoder->dev; 225 struct radeon_device *rdev = dev->dev_private; 226 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 227 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 228 u32 base_rate = 24000; 229 u32 max_ratio = clock / base_rate; 230 u32 dto_phase; 231 u32 dto_modulo = clock; 232 u32 wallclock_ratio; 233 u32 dto_cntl; 234 235 if (!dig || !dig->afmt) 236 return; 237 238 if (max_ratio >= 8) { 239 dto_phase = 192 * 1000; 240 wallclock_ratio = 3; 241 } else if (max_ratio >= 4) { 242 dto_phase = 96 * 1000; 243 wallclock_ratio = 2; 244 } else if (max_ratio >= 2) { 245 dto_phase = 48 * 1000; 246 wallclock_ratio = 1; 247 } else { 248 dto_phase = 24 * 1000; 249 wallclock_ratio = 0; 250 } 251 252 /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT. 253 * doesn't matter which one you use. Just use the first one. 254 */ 255 /* XXX two dtos; generally use dto0 for hdmi */ 256 /* Express [24MHz / target pixel clock] as an exact rational 257 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 258 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 259 */ 260 if (ASIC_IS_DCE3(rdev)) { 261 /* according to the reg specs, this should DCE3.2 only, but in 262 * practice it seems to cover DCE3.0 as well. 263 */ 264 if (dig->dig_encoder == 0) { 265 dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; 266 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); 267 WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl); 268 WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); 269 WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo); 270 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ 271 } else { 272 dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; 273 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); 274 WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl); 275 WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase); 276 WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo); 277 WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */ 278 } 279 } else { 280 /* according to the reg specs, this should be DCE2.0 and DCE3.0 */ 281 WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate / 10) | 282 AUDIO_DTO_MODULE(clock / 10)); 283 } 284 } 285 286 /* 287 * update the info frames with the data from the current display mode 288 */ 289 void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) 290 { 291 struct drm_device *dev = encoder->dev; 292 struct radeon_device *rdev = dev->dev_private; 293 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 294 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 295 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 296 struct hdmi_avi_infoframe frame; 297 uint32_t offset; 298 ssize_t err; 299 300 if (!dig || !dig->afmt) 301 return; 302 303 /* Silent, r600_hdmi_enable will raise WARN for us */ 304 if (!dig->afmt->enabled) 305 return; 306 offset = dig->afmt->offset; 307 308 r600_audio_set_dto(encoder, mode->clock); 309 310 WREG32(HDMI0_VBI_PACKET_CONTROL + offset, 311 HDMI0_NULL_SEND); /* send null packets when required */ 312 313 WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000); 314 315 if (ASIC_IS_DCE32(rdev)) { 316 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, 317 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ 318 HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ 319 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, 320 AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */ 321 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ 322 } else { 323 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, 324 HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */ 325 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ 326 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */ 327 HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ 328 } 329 330 WREG32(HDMI0_ACR_PACKET_CONTROL + offset, 331 HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */ 332 HDMI0_ACR_SOURCE); /* select SW CTS value */ 333 334 WREG32(HDMI0_VBI_PACKET_CONTROL + offset, 335 HDMI0_NULL_SEND | /* send null packets when required */ 336 HDMI0_GC_SEND | /* send general control packets */ 337 HDMI0_GC_CONT); /* send general control packets every frame */ 338 339 /* TODO: HDMI0_AUDIO_INFO_UPDATE */ 340 WREG32(HDMI0_INFOFRAME_CONTROL0 + offset, 341 HDMI0_AVI_INFO_SEND | /* enable AVI info frames */ 342 HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */ 343 HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ 344 HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */ 345 346 WREG32(HDMI0_INFOFRAME_CONTROL1 + offset, 347 HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */ 348 HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */ 349 350 WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */ 351 352 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 353 if (err < 0) { 354 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 355 return; 356 } 357 358 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 359 if (err < 0) { 360 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 361 return; 362 } 363 364 r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 365 r600_hdmi_update_ACR(encoder, mode->clock); 366 367 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ 368 WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF); 369 WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF); 370 WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001); 371 WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001); 372 373 r600_hdmi_audio_workaround(encoder); 374 } 375 376 /* 377 * update settings with current parameters from audio engine 378 */ 379 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder) 380 { 381 struct drm_device *dev = encoder->dev; 382 struct radeon_device *rdev = dev->dev_private; 383 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 384 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 385 struct r600_audio audio = r600_audio_status(rdev); 386 uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE]; 387 struct hdmi_audio_infoframe frame; 388 uint32_t offset; 389 uint32_t iec; 390 ssize_t err; 391 392 if (!dig->afmt || !dig->afmt->enabled) 393 return; 394 offset = dig->afmt->offset; 395 396 DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n", 397 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped", 398 audio.channels, audio.rate, audio.bits_per_sample); 399 DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n", 400 (int)audio.status_bits, (int)audio.category_code); 401 402 iec = 0; 403 if (audio.status_bits & AUDIO_STATUS_PROFESSIONAL) 404 iec |= 1 << 0; 405 if (audio.status_bits & AUDIO_STATUS_NONAUDIO) 406 iec |= 1 << 1; 407 if (audio.status_bits & AUDIO_STATUS_COPYRIGHT) 408 iec |= 1 << 2; 409 if (audio.status_bits & AUDIO_STATUS_EMPHASIS) 410 iec |= 1 << 3; 411 412 iec |= HDMI0_60958_CS_CATEGORY_CODE(audio.category_code); 413 414 switch (audio.rate) { 415 case 32000: 416 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x3); 417 break; 418 case 44100: 419 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x0); 420 break; 421 case 48000: 422 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x2); 423 break; 424 case 88200: 425 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x8); 426 break; 427 case 96000: 428 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xa); 429 break; 430 case 176400: 431 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xc); 432 break; 433 case 192000: 434 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xe); 435 break; 436 } 437 438 WREG32(HDMI0_60958_0 + offset, iec); 439 440 iec = 0; 441 switch (audio.bits_per_sample) { 442 case 16: 443 iec |= HDMI0_60958_CS_WORD_LENGTH(0x2); 444 break; 445 case 20: 446 iec |= HDMI0_60958_CS_WORD_LENGTH(0x3); 447 break; 448 case 24: 449 iec |= HDMI0_60958_CS_WORD_LENGTH(0xb); 450 break; 451 } 452 if (audio.status_bits & AUDIO_STATUS_V) 453 iec |= 0x5 << 16; 454 WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f); 455 456 err = hdmi_audio_infoframe_init(&frame); 457 if (err < 0) { 458 DRM_ERROR("failed to setup audio infoframe\n"); 459 return; 460 } 461 462 frame.channels = audio.channels; 463 464 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); 465 if (err < 0) { 466 DRM_ERROR("failed to pack audio infoframe\n"); 467 return; 468 } 469 470 r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer)); 471 r600_hdmi_audio_workaround(encoder); 472 } 473 474 /* 475 * enable the HDMI engine 476 */ 477 void r600_hdmi_enable(struct drm_encoder *encoder, bool enable) 478 { 479 struct drm_device *dev = encoder->dev; 480 struct radeon_device *rdev = dev->dev_private; 481 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 482 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 483 u32 hdmi = HDMI0_ERROR_ACK; 484 485 if (!dig || !dig->afmt) 486 return; 487 488 /* Silent, r600_hdmi_enable will raise WARN for us */ 489 if (enable && dig->afmt->enabled) 490 return; 491 if (!enable && !dig->afmt->enabled) 492 return; 493 494 /* Older chipsets require setting HDMI and routing manually */ 495 if (!ASIC_IS_DCE3(rdev)) { 496 if (enable) 497 hdmi |= HDMI0_ENABLE; 498 switch (radeon_encoder->encoder_id) { 499 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 500 if (enable) { 501 WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN); 502 hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA); 503 } else { 504 WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN); 505 } 506 break; 507 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 508 if (enable) { 509 WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN); 510 hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA); 511 } else { 512 WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN); 513 } 514 break; 515 case ENCODER_OBJECT_ID_INTERNAL_DDI: 516 if (enable) { 517 WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN); 518 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA); 519 } else { 520 WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN); 521 } 522 break; 523 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 524 if (enable) 525 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA); 526 break; 527 default: 528 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n", 529 radeon_encoder->encoder_id); 530 break; 531 } 532 WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi); 533 } 534 535 if (rdev->irq.installed) { 536 /* if irq is available use it */ 537 /* XXX: shouldn't need this on any asics. Double check DCE2/3 */ 538 if (enable) 539 radeon_irq_kms_enable_afmt(rdev, dig->afmt->id); 540 else 541 radeon_irq_kms_disable_afmt(rdev, dig->afmt->id); 542 } 543 544 dig->afmt->enabled = enable; 545 546 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", 547 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); 548 } 549