1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Christian König. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Christian König 25 * 26 * $FreeBSD: head/sys/dev/drm2/radeon/r600_hdmi.c 254885 2013-08-25 19:37:15Z dumbbell $ 27 */ 28 29 #include <drm/drmP.h> 30 #include <uapi_drm/radeon_drm.h> 31 #include "radeon.h" 32 #include "radeon_asic.h" 33 #include "r600d.h" 34 #include "atom.h" 35 36 /* 37 * HDMI color format 38 */ 39 enum r600_hdmi_color_format { 40 RGB = 0, 41 YCC_422 = 1, 42 YCC_444 = 2 43 }; 44 45 /* 46 * IEC60958 status bits 47 */ 48 enum r600_hdmi_iec_status_bits { 49 AUDIO_STATUS_DIG_ENABLE = 0x01, 50 AUDIO_STATUS_V = 0x02, 51 AUDIO_STATUS_VCFG = 0x04, 52 AUDIO_STATUS_EMPHASIS = 0x08, 53 AUDIO_STATUS_COPYRIGHT = 0x10, 54 AUDIO_STATUS_NONAUDIO = 0x20, 55 AUDIO_STATUS_PROFESSIONAL = 0x40, 56 AUDIO_STATUS_LEVEL = 0x80 57 }; 58 59 static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = { 60 /* 32kHz 44.1kHz 48kHz */ 61 /* Clock N CTS N CTS N CTS */ 62 { 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */ 63 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ 64 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ 65 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ 66 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ 67 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ 68 { 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */ 69 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ 70 { 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */ 71 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ 72 { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */ 73 }; 74 75 /* 76 * calculate CTS value if it's not found in the table 77 */ 78 static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq) 79 { 80 if (*CTS == 0) 81 *CTS = clock * N / (128 * freq) * 1000; 82 DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n", 83 N, *CTS, freq); 84 } 85 86 struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock) 87 { 88 struct radeon_hdmi_acr res; 89 u8 i; 90 91 for (i = 0; r600_hdmi_predefined_acr[i].clock != clock && 92 r600_hdmi_predefined_acr[i].clock != 0; i++) 93 ; 94 res = r600_hdmi_predefined_acr[i]; 95 96 /* In case some CTS are missing */ 97 r600_hdmi_calc_cts(clock, &res.cts_32khz, res.n_32khz, 32000); 98 r600_hdmi_calc_cts(clock, &res.cts_44_1khz, res.n_44_1khz, 44100); 99 r600_hdmi_calc_cts(clock, &res.cts_48khz, res.n_48khz, 48000); 100 101 return res; 102 } 103 104 /* 105 * update the N and CTS parameters for a given pixel clock rate 106 */ 107 static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) 108 { 109 struct drm_device *dev = encoder->dev; 110 struct radeon_device *rdev = dev->dev_private; 111 struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); 112 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 113 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 114 uint32_t offset = dig->afmt->offset; 115 116 WREG32(HDMI0_ACR_32_0 + offset, HDMI0_ACR_CTS_32(acr.cts_32khz)); 117 WREG32(HDMI0_ACR_32_1 + offset, acr.n_32khz); 118 119 WREG32(HDMI0_ACR_44_0 + offset, HDMI0_ACR_CTS_44(acr.cts_44_1khz)); 120 WREG32(HDMI0_ACR_44_1 + offset, acr.n_44_1khz); 121 122 WREG32(HDMI0_ACR_48_0 + offset, HDMI0_ACR_CTS_48(acr.cts_48khz)); 123 WREG32(HDMI0_ACR_48_1 + offset, acr.n_48khz); 124 } 125 126 /* 127 * calculate the crc for a given info frame 128 */ 129 static void r600_hdmi_infoframe_checksum(uint8_t packetType, 130 uint8_t versionNumber, 131 uint8_t length, 132 uint8_t *frame) 133 { 134 int i; 135 frame[0] = packetType + versionNumber + length; 136 for (i = 1; i <= length; i++) 137 frame[0] += frame[i]; 138 frame[0] = 0x100 - frame[0]; 139 } 140 141 /* 142 * build a HDMI Video Info Frame 143 */ 144 static void r600_hdmi_videoinfoframe( 145 struct drm_encoder *encoder, 146 enum r600_hdmi_color_format color_format, 147 int active_information_present, 148 uint8_t active_format_aspect_ratio, 149 uint8_t scan_information, 150 uint8_t colorimetry, 151 uint8_t ex_colorimetry, 152 uint8_t quantization, 153 int ITC, 154 uint8_t picture_aspect_ratio, 155 uint8_t video_format_identification, 156 uint8_t pixel_repetition, 157 uint8_t non_uniform_picture_scaling, 158 uint8_t bar_info_data_valid, 159 uint16_t top_bar, 160 uint16_t bottom_bar, 161 uint16_t left_bar, 162 uint16_t right_bar 163 ) 164 { 165 struct drm_device *dev = encoder->dev; 166 struct radeon_device *rdev = dev->dev_private; 167 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 168 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 169 uint32_t offset = dig->afmt->offset; 170 171 uint8_t frame[14]; 172 173 frame[0x0] = 0; 174 frame[0x1] = 175 (scan_information & 0x3) | 176 ((bar_info_data_valid & 0x3) << 2) | 177 ((active_information_present & 0x1) << 4) | 178 ((color_format & 0x3) << 5); 179 frame[0x2] = 180 (active_format_aspect_ratio & 0xF) | 181 ((picture_aspect_ratio & 0x3) << 4) | 182 ((colorimetry & 0x3) << 6); 183 frame[0x3] = 184 (non_uniform_picture_scaling & 0x3) | 185 ((quantization & 0x3) << 2) | 186 ((ex_colorimetry & 0x7) << 4) | 187 ((ITC & 0x1) << 7); 188 frame[0x4] = (video_format_identification & 0x7F); 189 frame[0x5] = (pixel_repetition & 0xF); 190 frame[0x6] = (top_bar & 0xFF); 191 frame[0x7] = (top_bar >> 8); 192 frame[0x8] = (bottom_bar & 0xFF); 193 frame[0x9] = (bottom_bar >> 8); 194 frame[0xA] = (left_bar & 0xFF); 195 frame[0xB] = (left_bar >> 8); 196 frame[0xC] = (right_bar & 0xFF); 197 frame[0xD] = (right_bar >> 8); 198 199 r600_hdmi_infoframe_checksum(0x82, 0x02, 0x0D, frame); 200 /* Our header values (type, version, length) should be alright, Intel 201 * is using the same. Checksum function also seems to be OK, it works 202 * fine for audio infoframe. However calculated value is always lower 203 * by 2 in comparison to fglrx. It breaks displaying anything in case 204 * of TVs that strictly check the checksum. Hack it manually here to 205 * workaround this issue. */ 206 frame[0x0] += 2; 207 208 WREG32(HDMI0_AVI_INFO0 + offset, 209 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 210 WREG32(HDMI0_AVI_INFO1 + offset, 211 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 212 WREG32(HDMI0_AVI_INFO2 + offset, 213 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 214 WREG32(HDMI0_AVI_INFO3 + offset, 215 frame[0xC] | (frame[0xD] << 8)); 216 } 217 218 /* 219 * build a Audio Info Frame 220 */ 221 static void r600_hdmi_audioinfoframe( 222 struct drm_encoder *encoder, 223 uint8_t channel_count, 224 uint8_t coding_type, 225 uint8_t sample_size, 226 uint8_t sample_frequency, 227 uint8_t format, 228 uint8_t channel_allocation, 229 uint8_t level_shift, 230 int downmix_inhibit 231 ) 232 { 233 struct drm_device *dev = encoder->dev; 234 struct radeon_device *rdev = dev->dev_private; 235 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 236 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 237 uint32_t offset = dig->afmt->offset; 238 239 uint8_t frame[11]; 240 241 frame[0x0] = 0; 242 frame[0x1] = (channel_count & 0x7) | ((coding_type & 0xF) << 4); 243 frame[0x2] = (sample_size & 0x3) | ((sample_frequency & 0x7) << 2); 244 frame[0x3] = format; 245 frame[0x4] = channel_allocation; 246 frame[0x5] = ((level_shift & 0xF) << 3) | ((downmix_inhibit & 0x1) << 7); 247 frame[0x6] = 0; 248 frame[0x7] = 0; 249 frame[0x8] = 0; 250 frame[0x9] = 0; 251 frame[0xA] = 0; 252 253 r600_hdmi_infoframe_checksum(0x84, 0x01, 0x0A, frame); 254 255 WREG32(HDMI0_AUDIO_INFO0 + offset, 256 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 257 WREG32(HDMI0_AUDIO_INFO1 + offset, 258 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24)); 259 } 260 261 /* 262 * test if audio buffer is filled enough to start playing 263 */ 264 static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder) 265 { 266 struct drm_device *dev = encoder->dev; 267 struct radeon_device *rdev = dev->dev_private; 268 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 269 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 270 uint32_t offset = dig->afmt->offset; 271 272 return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0; 273 } 274 275 /* 276 * have buffer status changed since last call? 277 */ 278 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder) 279 { 280 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 281 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 282 int status, result; 283 284 if (!dig->afmt || !dig->afmt->enabled) 285 return 0; 286 287 status = r600_hdmi_is_audio_buffer_filled(encoder); 288 result = dig->afmt->last_buffer_filled_status != status; 289 dig->afmt->last_buffer_filled_status = status; 290 291 return result; 292 } 293 294 /* 295 * write the audio workaround status to the hardware 296 */ 297 static void r600_hdmi_audio_workaround(struct drm_encoder *encoder) 298 { 299 struct drm_device *dev = encoder->dev; 300 struct radeon_device *rdev = dev->dev_private; 301 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 302 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 303 uint32_t offset = dig->afmt->offset; 304 bool hdmi_audio_workaround = false; /* FIXME */ 305 u32 value; 306 307 if (!hdmi_audio_workaround || 308 r600_hdmi_is_audio_buffer_filled(encoder)) 309 value = 0; /* disable workaround */ 310 else 311 value = HDMI0_AUDIO_TEST_EN; /* enable workaround */ 312 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, 313 value, ~HDMI0_AUDIO_TEST_EN); 314 } 315 316 317 /* 318 * update the info frames with the data from the current display mode 319 */ 320 void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) 321 { 322 struct drm_device *dev = encoder->dev; 323 struct radeon_device *rdev = dev->dev_private; 324 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 325 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 326 uint32_t offset; 327 328 /* Silent, r600_hdmi_enable will raise WARN for us */ 329 if (!dig->afmt->enabled) 330 return; 331 offset = dig->afmt->offset; 332 333 r600_audio_set_clock(encoder, mode->clock); 334 335 WREG32(HDMI0_VBI_PACKET_CONTROL + offset, 336 HDMI0_NULL_SEND); /* send null packets when required */ 337 338 WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000); 339 340 if (ASIC_IS_DCE32(rdev)) { 341 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, 342 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ 343 HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ 344 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, 345 AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */ 346 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ 347 } else { 348 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, 349 HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */ 350 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ 351 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */ 352 HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ 353 } 354 355 WREG32(HDMI0_ACR_PACKET_CONTROL + offset, 356 HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */ 357 HDMI0_ACR_SOURCE); /* select SW CTS value */ 358 359 WREG32(HDMI0_VBI_PACKET_CONTROL + offset, 360 HDMI0_NULL_SEND | /* send null packets when required */ 361 HDMI0_GC_SEND | /* send general control packets */ 362 HDMI0_GC_CONT); /* send general control packets every frame */ 363 364 /* TODO: HDMI0_AUDIO_INFO_UPDATE */ 365 WREG32(HDMI0_INFOFRAME_CONTROL0 + offset, 366 HDMI0_AVI_INFO_SEND | /* enable AVI info frames */ 367 HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */ 368 HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ 369 HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */ 370 371 WREG32(HDMI0_INFOFRAME_CONTROL1 + offset, 372 HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */ 373 HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */ 374 375 WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */ 376 377 r600_hdmi_videoinfoframe(encoder, RGB, 0, 0, 0, 0, 378 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); 379 380 r600_hdmi_update_ACR(encoder, mode->clock); 381 382 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ 383 WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF); 384 WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF); 385 WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001); 386 WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001); 387 388 r600_hdmi_audio_workaround(encoder); 389 } 390 391 /* 392 * update settings with current parameters from audio engine 393 */ 394 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder) 395 { 396 struct drm_device *dev = encoder->dev; 397 struct radeon_device *rdev = dev->dev_private; 398 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 399 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 400 struct r600_audio audio = r600_audio_status(rdev); 401 uint32_t offset; 402 uint32_t iec; 403 404 if (!dig->afmt || !dig->afmt->enabled) 405 return; 406 offset = dig->afmt->offset; 407 408 DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n", 409 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped", 410 audio.channels, audio.rate, audio.bits_per_sample); 411 DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n", 412 (int)audio.status_bits, (int)audio.category_code); 413 414 iec = 0; 415 if (audio.status_bits & AUDIO_STATUS_PROFESSIONAL) 416 iec |= 1 << 0; 417 if (audio.status_bits & AUDIO_STATUS_NONAUDIO) 418 iec |= 1 << 1; 419 if (audio.status_bits & AUDIO_STATUS_COPYRIGHT) 420 iec |= 1 << 2; 421 if (audio.status_bits & AUDIO_STATUS_EMPHASIS) 422 iec |= 1 << 3; 423 424 iec |= HDMI0_60958_CS_CATEGORY_CODE(audio.category_code); 425 426 switch (audio.rate) { 427 case 32000: 428 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x3); 429 break; 430 case 44100: 431 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x0); 432 break; 433 case 48000: 434 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x2); 435 break; 436 case 88200: 437 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x8); 438 break; 439 case 96000: 440 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xa); 441 break; 442 case 176400: 443 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xc); 444 break; 445 case 192000: 446 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xe); 447 break; 448 } 449 450 WREG32(HDMI0_60958_0 + offset, iec); 451 452 iec = 0; 453 switch (audio.bits_per_sample) { 454 case 16: 455 iec |= HDMI0_60958_CS_WORD_LENGTH(0x2); 456 break; 457 case 20: 458 iec |= HDMI0_60958_CS_WORD_LENGTH(0x3); 459 break; 460 case 24: 461 iec |= HDMI0_60958_CS_WORD_LENGTH(0xb); 462 break; 463 } 464 if (audio.status_bits & AUDIO_STATUS_V) 465 iec |= 0x5 << 16; 466 WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f); 467 468 r600_hdmi_audioinfoframe(encoder, audio.channels - 1, 0, 0, 0, 0, 0, 0, 469 0); 470 471 r600_hdmi_audio_workaround(encoder); 472 } 473 474 /* 475 * enable the HDMI engine 476 */ 477 void r600_hdmi_enable(struct drm_encoder *encoder) 478 { 479 struct drm_device *dev = encoder->dev; 480 struct radeon_device *rdev = dev->dev_private; 481 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 482 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 483 uint32_t offset; 484 u32 hdmi; 485 486 if (ASIC_IS_DCE6(rdev)) 487 return; 488 489 /* Silent, r600_hdmi_enable will raise WARN for us */ 490 if (dig->afmt->enabled) 491 return; 492 offset = dig->afmt->offset; 493 494 /* Older chipsets require setting HDMI and routing manually */ 495 if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) { 496 hdmi = HDMI0_ERROR_ACK | HDMI0_ENABLE; 497 switch (radeon_encoder->encoder_id) { 498 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 499 WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN, 500 ~AVIVO_TMDSA_CNTL_HDMI_EN); 501 hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA); 502 break; 503 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 504 WREG32_P(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN, 505 ~AVIVO_LVTMA_CNTL_HDMI_EN); 506 hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA); 507 break; 508 case ENCODER_OBJECT_ID_INTERNAL_DDI: 509 WREG32_P(DDIA_CNTL, DDIA_HDMI_EN, ~DDIA_HDMI_EN); 510 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA); 511 break; 512 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 513 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA); 514 break; 515 default: 516 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n", 517 radeon_encoder->encoder_id); 518 break; 519 } 520 WREG32(HDMI0_CONTROL + offset, hdmi); 521 } 522 523 if (rdev->irq.installed) { 524 /* if irq is available use it */ 525 radeon_irq_kms_enable_afmt(rdev, dig->afmt->id); 526 } 527 528 dig->afmt->enabled = true; 529 530 DRM_DEBUG("Enabling HDMI interface @ 0x%04X for encoder 0x%x\n", 531 offset, radeon_encoder->encoder_id); 532 } 533 534 /* 535 * disable the HDMI engine 536 */ 537 void r600_hdmi_disable(struct drm_encoder *encoder) 538 { 539 struct drm_device *dev = encoder->dev; 540 struct radeon_device *rdev = dev->dev_private; 541 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 542 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 543 uint32_t offset; 544 545 if (ASIC_IS_DCE6(rdev)) 546 return; 547 548 /* Called for ATOM_ENCODER_MODE_HDMI only */ 549 if (!dig || !dig->afmt) { 550 DRM_ERROR("%s: !dig || !dig->afmt", __func__); 551 return; 552 } 553 if (!dig->afmt->enabled) 554 return; 555 offset = dig->afmt->offset; 556 557 DRM_DEBUG("Disabling HDMI interface @ 0x%04X for encoder 0x%x\n", 558 offset, radeon_encoder->encoder_id); 559 560 /* disable irq */ 561 radeon_irq_kms_disable_afmt(rdev, dig->afmt->id); 562 563 /* Older chipsets not handled by AtomBIOS */ 564 if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) { 565 switch (radeon_encoder->encoder_id) { 566 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 567 WREG32_P(AVIVO_TMDSA_CNTL, 0, 568 ~AVIVO_TMDSA_CNTL_HDMI_EN); 569 break; 570 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 571 WREG32_P(AVIVO_LVTMA_CNTL, 0, 572 ~AVIVO_LVTMA_CNTL_HDMI_EN); 573 break; 574 case ENCODER_OBJECT_ID_INTERNAL_DDI: 575 WREG32_P(DDIA_CNTL, 0, ~DDIA_HDMI_EN); 576 break; 577 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 578 break; 579 default: 580 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n", 581 radeon_encoder->encoder_id); 582 break; 583 } 584 WREG32(HDMI0_CONTROL + offset, HDMI0_ERROR_ACK); 585 } 586 587 dig->afmt->enabled = false; 588 } 589