1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * 28 * $FreeBSD: head/sys/dev/drm2/radeon/radeon.h 254885 2013-08-25 19:37:15Z dumbbell $ 29 */ 30 31 #ifndef __RADEON_H__ 32 #define __RADEON_H__ 33 34 /* TODO: Here are things that needs to be done : 35 * - surface allocator & initializer : (bit like scratch reg) should 36 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 37 * related to surface 38 * - WB : write back stuff (do it bit like scratch reg things) 39 * - Vblank : look at Jesse's rework and what we should do 40 * - r600/r700: gart & cp 41 * - cs : clean cs ioctl use bitmap & things like that. 42 * - power management stuff 43 * - Barrier in gart code 44 * - Unmappabled vram ? 45 * - TESTING, TESTING, TESTING 46 */ 47 48 /* Initialization path: 49 * We expect that acceleration initialization might fail for various 50 * reasons even thought we work hard to make it works on most 51 * configurations. In order to still have a working userspace in such 52 * situation the init path must succeed up to the memory controller 53 * initialization point. Failure before this point are considered as 54 * fatal error. Here is the init callchain : 55 * radeon_device_init perform common structure, mutex initialization 56 * asic_init setup the GPU memory layout and perform all 57 * one time initialization (failure in this 58 * function are considered fatal) 59 * asic_startup setup the GPU acceleration, in order to 60 * follow guideline the first thing this 61 * function should do is setting the GPU 62 * memory controller (only MC setup failure 63 * are considered as fatal) 64 */ 65 66 #include <sys/condvar.h> 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/linker.h> 70 #include <linux/firmware.h> 71 #include <linux/seq_file.h> 72 73 #include <contrib/dev/acpica/source/include/acpi.h> 74 #include <dev/acpica/acpivar.h> 75 76 #include <drm/ttm/ttm_bo_api.h> 77 #include <drm/ttm/ttm_bo_driver.h> 78 #include <drm/ttm/ttm_placement.h> 79 #include <drm/ttm/ttm_module.h> 80 #include <drm/ttm/ttm_execbuf_util.h> 81 82 #define CONFIG_ACPI 1 83 84 #include "radeon_family.h" 85 #include "radeon_mode.h" 86 #include "radeon_reg.h" 87 88 /* 89 * Modules parameters. 90 */ 91 extern int radeon_no_wb; 92 extern int radeon_modeset; 93 extern int radeon_dynclks; 94 extern int radeon_r4xx_atom; 95 extern int radeon_agpmode; 96 extern int radeon_vram_limit; 97 extern int radeon_gart_size; 98 extern int radeon_benchmarking; 99 extern int radeon_testing; 100 extern int radeon_connector_table; 101 extern int radeon_tv; 102 extern int radeon_audio; 103 extern int radeon_disp_priority; 104 extern int radeon_hw_i2c; 105 extern int radeon_pcie_gen2; 106 extern int radeon_msi; 107 extern int radeon_lockup_timeout; 108 extern int radeon_fastfb; 109 extern int radeon_dpm; 110 extern int radeon_aspm; 111 extern int radeon_runtime_pm; 112 extern int radeon_hard_reset; 113 extern int radeon_vm_size; 114 extern int radeon_vm_block_size; 115 extern int radeon_deep_color; 116 extern int radeon_use_pflipirq; 117 extern int radeon_bapm; 118 extern int radeon_backlight; 119 120 /* 121 * Copy from radeon_drv.h so we don't have to include both and have conflicting 122 * symbol; 123 */ 124 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 125 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 126 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 127 #define RADEON_IB_POOL_SIZE 16 128 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 129 #define RADEONFB_CONN_LIMIT 4 130 #define RADEON_BIOS_NUM_SCRATCH 8 131 132 /* fence seq are set to this number when signaled */ 133 #define RADEON_FENCE_SIGNALED_SEQ 0LL 134 135 /* internal ring indices */ 136 /* r1xx+ has gfx CP ring */ 137 #define RADEON_RING_TYPE_GFX_INDEX 0 138 139 /* cayman has 2 compute CP rings */ 140 #define CAYMAN_RING_TYPE_CP1_INDEX 1 141 #define CAYMAN_RING_TYPE_CP2_INDEX 2 142 143 /* R600+ has an async dma ring */ 144 #define R600_RING_TYPE_DMA_INDEX 3 145 /* cayman add a second async dma ring */ 146 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 147 148 /* R600+ */ 149 #define R600_RING_TYPE_UVD_INDEX 5 150 151 /* TN+ */ 152 #define TN_RING_TYPE_VCE1_INDEX 6 153 #define TN_RING_TYPE_VCE2_INDEX 7 154 155 /* max number of rings */ 156 #define RADEON_NUM_RINGS 8 157 158 /* number of hw syncs before falling back on blocking */ 159 #define RADEON_NUM_SYNCS 4 160 161 /* hardcode those limit for now */ 162 #define RADEON_VA_IB_OFFSET (1 << 20) 163 #define RADEON_VA_RESERVED_SIZE (8 << 20) 164 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 165 166 /* hard reset data */ 167 #define RADEON_ASIC_RESET_DATA 0x39d5e86b 168 169 /* reset flags */ 170 #define RADEON_RESET_GFX (1 << 0) 171 #define RADEON_RESET_COMPUTE (1 << 1) 172 #define RADEON_RESET_DMA (1 << 2) 173 #define RADEON_RESET_CP (1 << 3) 174 #define RADEON_RESET_GRBM (1 << 4) 175 #define RADEON_RESET_DMA1 (1 << 5) 176 #define RADEON_RESET_RLC (1 << 6) 177 #define RADEON_RESET_SEM (1 << 7) 178 #define RADEON_RESET_IH (1 << 8) 179 #define RADEON_RESET_VMC (1 << 9) 180 #define RADEON_RESET_MC (1 << 10) 181 #define RADEON_RESET_DISPLAY (1 << 11) 182 183 /* CG block flags */ 184 #define RADEON_CG_BLOCK_GFX (1 << 0) 185 #define RADEON_CG_BLOCK_MC (1 << 1) 186 #define RADEON_CG_BLOCK_SDMA (1 << 2) 187 #define RADEON_CG_BLOCK_UVD (1 << 3) 188 #define RADEON_CG_BLOCK_VCE (1 << 4) 189 #define RADEON_CG_BLOCK_HDP (1 << 5) 190 #define RADEON_CG_BLOCK_BIF (1 << 6) 191 192 /* CG flags */ 193 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 194 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 195 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 196 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 197 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 198 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 199 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 200 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 201 #define RADEON_CG_SUPPORT_MC_LS (1 << 8) 202 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 203 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 204 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 205 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 206 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 207 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 208 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 209 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 210 211 /* PG flags */ 212 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 213 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 214 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 215 #define RADEON_PG_SUPPORT_UVD (1 << 3) 216 #define RADEON_PG_SUPPORT_VCE (1 << 4) 217 #define RADEON_PG_SUPPORT_CP (1 << 5) 218 #define RADEON_PG_SUPPORT_GDS (1 << 6) 219 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 220 #define RADEON_PG_SUPPORT_SDMA (1 << 8) 221 #define RADEON_PG_SUPPORT_ACP (1 << 9) 222 #define RADEON_PG_SUPPORT_SAMU (1 << 10) 223 224 /* max cursor sizes (in pixels) */ 225 #define CURSOR_WIDTH 64 226 #define CURSOR_HEIGHT 64 227 228 #define CIK_CURSOR_WIDTH 128 229 #define CIK_CURSOR_HEIGHT 128 230 231 /* 232 * Errata workarounds. 233 */ 234 enum radeon_pll_errata { 235 CHIP_ERRATA_R300_CG = 0x00000001, 236 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 237 CHIP_ERRATA_PLL_DELAY = 0x00000004 238 }; 239 240 241 struct radeon_device; 242 243 244 /* 245 * BIOS. 246 */ 247 bool radeon_get_bios(struct radeon_device *rdev); 248 249 /* 250 * Dummy page 251 */ 252 struct radeon_dummy_page { 253 drm_dma_handle_t *dmah; 254 dma_addr_t addr; 255 }; 256 int radeon_dummy_page_init(struct radeon_device *rdev); 257 void radeon_dummy_page_fini(struct radeon_device *rdev); 258 259 260 /* 261 * Clocks 262 */ 263 struct radeon_clock { 264 struct radeon_pll p1pll; 265 struct radeon_pll p2pll; 266 struct radeon_pll dcpll; 267 struct radeon_pll spll; 268 struct radeon_pll mpll; 269 /* 10 Khz units */ 270 uint32_t default_mclk; 271 uint32_t default_sclk; 272 uint32_t default_dispclk; 273 uint32_t current_dispclk; 274 uint32_t dp_extclk; 275 uint32_t max_pixel_clock; 276 }; 277 278 /* 279 * Power management 280 */ 281 int radeon_pm_init(struct radeon_device *rdev); 282 int radeon_pm_late_init(struct radeon_device *rdev); 283 void radeon_pm_fini(struct radeon_device *rdev); 284 void radeon_pm_compute_clocks(struct radeon_device *rdev); 285 void radeon_pm_suspend(struct radeon_device *rdev); 286 void radeon_pm_resume(struct radeon_device *rdev); 287 void radeon_combios_get_power_modes(struct radeon_device *rdev); 288 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 289 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 290 u8 clock_type, 291 u32 clock, 292 bool strobe_mode, 293 struct atom_clock_dividers *dividers); 294 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 295 u32 clock, 296 bool strobe_mode, 297 struct atom_mpll_param *mpll_param); 298 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 299 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 300 u16 voltage_level, u8 voltage_type, 301 u32 *gpio_value, u32 *gpio_mask); 302 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 303 u32 eng_clock, u32 mem_clock); 304 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 305 u8 voltage_type, u16 *voltage_step); 306 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 307 u16 voltage_id, u16 *voltage); 308 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 309 u16 *voltage, 310 u16 leakage_idx); 311 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 312 u16 *leakage_id); 313 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 314 u16 *vddc, u16 *vddci, 315 u16 virtual_voltage_id, 316 u16 vbios_voltage_id); 317 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 318 u16 virtual_voltage_id, 319 u16 *voltage); 320 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 321 u8 voltage_type, 322 u16 nominal_voltage, 323 u16 *true_voltage); 324 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 325 u8 voltage_type, u16 *min_voltage); 326 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 327 u8 voltage_type, u16 *max_voltage); 328 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 329 u8 voltage_type, u8 voltage_mode, 330 struct atom_voltage_table *voltage_table); 331 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 332 u8 voltage_type, u8 voltage_mode); 333 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 334 u8 voltage_type, 335 u8 *svd_gpio_id, u8 *svc_gpio_id); 336 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 337 u32 mem_clock); 338 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 339 u32 mem_clock); 340 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 341 u8 module_index, 342 struct atom_mc_reg_table *reg_table); 343 int radeon_atom_get_memory_info(struct radeon_device *rdev, 344 u8 module_index, struct atom_memory_info *mem_info); 345 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 346 bool gddr5, u8 module_index, 347 struct atom_memory_clock_range_table *mclk_range_table); 348 void rs690_pm_info(struct radeon_device *rdev); 349 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 350 unsigned *bankh, unsigned *mtaspect, 351 unsigned *tile_split); 352 353 /* 354 * Fences. 355 */ 356 struct radeon_fence_driver { 357 uint32_t scratch_reg; 358 uint64_t gpu_addr; 359 volatile uint32_t *cpu_addr; 360 /* sync_seq is protected by ring emission lock */ 361 uint64_t sync_seq[RADEON_NUM_RINGS]; 362 atomic64_t last_seq; 363 bool initialized; 364 }; 365 366 struct radeon_fence { 367 struct radeon_device *rdev; 368 unsigned int kref; 369 /* protected by radeon_fence.lock */ 370 uint64_t seq; 371 /* RB, DMA, etc. */ 372 unsigned ring; 373 }; 374 375 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 376 int radeon_fence_driver_init(struct radeon_device *rdev); 377 void radeon_fence_driver_fini(struct radeon_device *rdev); 378 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); 379 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 380 void radeon_fence_process(struct radeon_device *rdev, int ring); 381 bool radeon_fence_signaled(struct radeon_fence *fence); 382 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 383 int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 384 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 385 int radeon_fence_wait_any(struct radeon_device *rdev, 386 struct radeon_fence **fences, 387 bool intr); 388 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 389 void radeon_fence_unref(struct radeon_fence **fence); 390 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 391 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 392 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 393 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 394 struct radeon_fence *b) 395 { 396 if (!a) { 397 return b; 398 } 399 400 if (!b) { 401 return a; 402 } 403 404 BUG_ON(a->ring != b->ring); 405 406 if (a->seq > b->seq) { 407 return a; 408 } else { 409 return b; 410 } 411 } 412 413 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 414 struct radeon_fence *b) 415 { 416 if (!a) { 417 return false; 418 } 419 420 if (!b) { 421 return true; 422 } 423 424 BUG_ON(a->ring != b->ring); 425 426 return a->seq < b->seq; 427 } 428 429 /* 430 * Tiling registers 431 */ 432 struct radeon_surface_reg { 433 struct radeon_bo *bo; 434 }; 435 436 #define RADEON_GEM_MAX_SURFACES 8 437 438 /* 439 * TTM. 440 */ 441 struct radeon_mman { 442 struct ttm_bo_global_ref bo_global_ref; 443 struct drm_global_reference mem_global_ref; 444 struct ttm_bo_device bdev; 445 bool mem_global_referenced; 446 bool initialized; 447 448 #if defined(CONFIG_DEBUG_FS) 449 struct dentry *vram; 450 struct dentry *gtt; 451 #endif 452 }; 453 454 /* bo virtual address in a specific vm */ 455 struct radeon_bo_va { 456 /* protected by bo being reserved */ 457 struct list_head bo_list; 458 uint64_t soffset; 459 uint64_t eoffset; 460 uint32_t flags; 461 uint64_t addr; 462 unsigned ref_count; 463 464 /* protected by vm mutex */ 465 struct list_head vm_list; 466 struct list_head vm_status; 467 468 /* constant after initialization */ 469 struct radeon_vm *vm; 470 struct radeon_bo *bo; 471 }; 472 473 struct radeon_bo { 474 /* Protected by gem.mutex */ 475 struct list_head list; 476 /* Protected by tbo.reserved */ 477 u32 initial_domain; 478 u32 placements[3]; 479 struct ttm_placement placement; 480 struct ttm_buffer_object tbo; 481 struct ttm_bo_kmap_obj kmap; 482 u32 flags; 483 unsigned pin_count; 484 void *kptr; 485 u32 tiling_flags; 486 u32 pitch; 487 int surface_reg; 488 /* list of all virtual address to which this bo 489 * is associated to 490 */ 491 struct list_head va; 492 /* Constant after initialization */ 493 struct radeon_device *rdev; 494 struct drm_gem_object gem_base; 495 496 struct ttm_bo_kmap_obj dma_buf_vmap; 497 pid_t pid; 498 }; 499 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 500 501 int radeon_gem_debugfs_init(struct radeon_device *rdev); 502 503 /* sub-allocation manager, it has to be protected by another lock. 504 * By conception this is an helper for other part of the driver 505 * like the indirect buffer or semaphore, which both have their 506 * locking. 507 * 508 * Principe is simple, we keep a list of sub allocation in offset 509 * order (first entry has offset == 0, last entry has the highest 510 * offset). 511 * 512 * When allocating new object we first check if there is room at 513 * the end total_size - (last_object_offset + last_object_size) >= 514 * alloc_size. If so we allocate new object there. 515 * 516 * When there is not enough room at the end, we start waiting for 517 * each sub object until we reach object_offset+object_size >= 518 * alloc_size, this object then become the sub object we return. 519 * 520 * Alignment can't be bigger than page size. 521 * 522 * Hole are not considered for allocation to keep things simple. 523 * Assumption is that there won't be hole (all object on same 524 * alignment). 525 */ 526 struct radeon_sa_manager { 527 struct cv wq; 528 struct lock wq_lock; 529 struct radeon_bo *bo; 530 struct list_head *hole; 531 struct list_head flist[RADEON_NUM_RINGS]; 532 struct list_head olist; 533 unsigned size; 534 uint64_t gpu_addr; 535 void *cpu_ptr; 536 uint32_t domain; 537 uint32_t align; 538 }; 539 540 struct radeon_sa_bo; 541 542 /* sub-allocation buffer */ 543 struct radeon_sa_bo { 544 struct list_head olist; 545 struct list_head flist; 546 struct radeon_sa_manager *manager; 547 unsigned soffset; 548 unsigned eoffset; 549 struct radeon_fence *fence; 550 }; 551 552 /* 553 * GEM objects. 554 */ 555 struct radeon_gem { 556 struct spinlock mutex; 557 struct list_head objects; 558 }; 559 560 int radeon_gem_init(struct radeon_device *rdev); 561 void radeon_gem_fini(struct radeon_device *rdev); 562 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, 563 int alignment, int initial_domain, 564 u32 flags, bool kernel, 565 struct drm_gem_object **obj); 566 567 int radeon_mode_dumb_create(struct drm_file *file_priv, 568 struct drm_device *dev, 569 struct drm_mode_create_dumb *args); 570 int radeon_mode_dumb_mmap(struct drm_file *filp, 571 struct drm_device *dev, 572 uint32_t handle, uint64_t *offset_p); 573 574 /* 575 * Semaphores. 576 */ 577 struct radeon_semaphore { 578 struct radeon_sa_bo *sa_bo; 579 signed waiters; 580 uint64_t gpu_addr; 581 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 582 }; 583 584 int radeon_semaphore_create(struct radeon_device *rdev, 585 struct radeon_semaphore **semaphore); 586 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 587 struct radeon_semaphore *semaphore); 588 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 589 struct radeon_semaphore *semaphore); 590 void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore, 591 struct radeon_fence *fence); 592 int radeon_semaphore_sync_rings(struct radeon_device *rdev, 593 struct radeon_semaphore *semaphore, 594 int waiting_ring); 595 void radeon_semaphore_free(struct radeon_device *rdev, 596 struct radeon_semaphore **semaphore, 597 struct radeon_fence *fence); 598 599 /* 600 * GART structures, functions & helpers 601 */ 602 struct radeon_mc; 603 604 #define RADEON_GPU_PAGE_SIZE 4096 605 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 606 #define RADEON_GPU_PAGE_SHIFT 12 607 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 608 609 #define RADEON_GART_PAGE_DUMMY 0 610 #define RADEON_GART_PAGE_VALID (1 << 0) 611 #define RADEON_GART_PAGE_READ (1 << 1) 612 #define RADEON_GART_PAGE_WRITE (1 << 2) 613 #define RADEON_GART_PAGE_SNOOP (1 << 3) 614 615 struct radeon_gart { 616 drm_dma_handle_t *dmah; 617 dma_addr_t table_addr; 618 struct radeon_bo *robj; 619 void *ptr; 620 unsigned num_gpu_pages; 621 unsigned num_cpu_pages; 622 unsigned table_size; 623 vm_page_t *pages; 624 dma_addr_t *pages_addr; 625 bool ready; 626 }; 627 628 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 629 void radeon_gart_table_ram_free(struct radeon_device *rdev); 630 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 631 void radeon_gart_table_vram_free(struct radeon_device *rdev); 632 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 633 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 634 int radeon_gart_init(struct radeon_device *rdev); 635 void radeon_gart_fini(struct radeon_device *rdev); 636 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 637 int pages); 638 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 639 int pages, vm_page_t *pagelist, 640 dma_addr_t *dma_addr, uint32_t flags); 641 642 643 /* 644 * GPU MC structures, functions & helpers 645 */ 646 struct radeon_mc { 647 resource_size_t aper_size; 648 resource_size_t aper_base; 649 resource_size_t agp_base; 650 /* for some chips with <= 32MB we need to lie 651 * about vram size near mc fb location */ 652 u64 mc_vram_size; 653 u64 visible_vram_size; 654 u64 gtt_size; 655 u64 gtt_start; 656 u64 gtt_end; 657 u64 vram_start; 658 u64 vram_end; 659 unsigned vram_width; 660 u64 real_vram_size; 661 int vram_mtrr; 662 bool vram_is_ddr; 663 bool igp_sideport_enabled; 664 u64 gtt_base_align; 665 u64 mc_mask; 666 }; 667 668 bool radeon_combios_sideport_present(struct radeon_device *rdev); 669 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 670 671 /* 672 * GPU scratch registers structures, functions & helpers 673 */ 674 struct radeon_scratch { 675 unsigned num_reg; 676 uint32_t reg_base; 677 bool free[32]; 678 uint32_t reg[32]; 679 }; 680 681 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 682 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 683 684 /* 685 * GPU doorbell structures, functions & helpers 686 */ 687 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 688 689 struct radeon_doorbell { 690 /* doorbell mmio */ 691 resource_size_t base; 692 resource_size_t size; 693 u32 __iomem *ptr; 694 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 695 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)]; 696 }; 697 698 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 699 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 700 701 /* 702 * IRQS. 703 */ 704 705 struct radeon_flip_work { 706 struct work_struct flip_work; 707 struct work_struct unpin_work; 708 struct radeon_device *rdev; 709 int crtc_id; 710 uint64_t base; 711 struct drm_pending_vblank_event *event; 712 struct radeon_bo *old_rbo; 713 struct radeon_fence *fence; 714 }; 715 716 struct r500_irq_stat_regs { 717 u32 disp_int; 718 u32 hdmi0_status; 719 }; 720 721 struct r600_irq_stat_regs { 722 u32 disp_int; 723 u32 disp_int_cont; 724 u32 disp_int_cont2; 725 u32 d1grph_int; 726 u32 d2grph_int; 727 u32 hdmi0_status; 728 u32 hdmi1_status; 729 }; 730 731 struct evergreen_irq_stat_regs { 732 u32 disp_int; 733 u32 disp_int_cont; 734 u32 disp_int_cont2; 735 u32 disp_int_cont3; 736 u32 disp_int_cont4; 737 u32 disp_int_cont5; 738 u32 d1grph_int; 739 u32 d2grph_int; 740 u32 d3grph_int; 741 u32 d4grph_int; 742 u32 d5grph_int; 743 u32 d6grph_int; 744 u32 afmt_status1; 745 u32 afmt_status2; 746 u32 afmt_status3; 747 u32 afmt_status4; 748 u32 afmt_status5; 749 u32 afmt_status6; 750 }; 751 752 struct cik_irq_stat_regs { 753 u32 disp_int; 754 u32 disp_int_cont; 755 u32 disp_int_cont2; 756 u32 disp_int_cont3; 757 u32 disp_int_cont4; 758 u32 disp_int_cont5; 759 u32 disp_int_cont6; 760 u32 d1grph_int; 761 u32 d2grph_int; 762 u32 d3grph_int; 763 u32 d4grph_int; 764 u32 d5grph_int; 765 u32 d6grph_int; 766 }; 767 768 union radeon_irq_stat_regs { 769 struct r500_irq_stat_regs r500; 770 struct r600_irq_stat_regs r600; 771 struct evergreen_irq_stat_regs evergreen; 772 struct cik_irq_stat_regs cik; 773 }; 774 775 struct radeon_irq { 776 bool installed; 777 struct lock lock; 778 atomic_t ring_int[RADEON_NUM_RINGS]; 779 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 780 atomic_t pflip[RADEON_MAX_CRTCS]; 781 wait_queue_head_t vblank_queue; 782 bool hpd[RADEON_MAX_HPD_PINS]; 783 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 784 union radeon_irq_stat_regs stat_regs; 785 bool dpm_thermal; 786 }; 787 788 int radeon_irq_kms_init(struct radeon_device *rdev); 789 void radeon_irq_kms_fini(struct radeon_device *rdev); 790 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 791 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 792 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 793 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 794 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 795 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 796 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 797 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 798 799 /* 800 * CP & rings. 801 */ 802 803 struct radeon_ib { 804 struct radeon_sa_bo *sa_bo; 805 uint32_t length_dw; 806 uint64_t gpu_addr; 807 uint32_t *ptr; 808 int ring; 809 struct radeon_fence *fence; 810 struct radeon_vm *vm; 811 bool is_const_ib; 812 struct radeon_semaphore *semaphore; 813 }; 814 815 struct radeon_ring { 816 struct radeon_bo *ring_obj; 817 volatile uint32_t *ring; 818 unsigned rptr_offs; 819 unsigned rptr_save_reg; 820 u64 next_rptr_gpu_addr; 821 volatile u32 *next_rptr_cpu_addr; 822 unsigned wptr; 823 unsigned wptr_old; 824 unsigned ring_size; 825 unsigned ring_free_dw; 826 int count_dw; 827 atomic_t last_rptr; 828 atomic64_t last_activity; 829 uint64_t gpu_addr; 830 uint32_t align_mask; 831 uint32_t ptr_mask; 832 bool ready; 833 u32 nop; 834 u32 idx; 835 u64 last_semaphore_signal_addr; 836 u64 last_semaphore_wait_addr; 837 /* for CIK queues */ 838 u32 me; 839 u32 pipe; 840 u32 queue; 841 struct radeon_bo *mqd_obj; 842 u32 doorbell_index; 843 unsigned wptr_offs; 844 }; 845 846 struct radeon_mec { 847 struct radeon_bo *hpd_eop_obj; 848 u64 hpd_eop_gpu_addr; 849 u32 num_pipe; 850 u32 num_mec; 851 u32 num_queue; 852 }; 853 854 /* 855 * VM 856 */ 857 858 /* maximum number of VMIDs */ 859 #define RADEON_NUM_VM 16 860 861 /* number of entries in page table */ 862 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) 863 864 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 865 #define RADEON_VM_PTB_ALIGN_SIZE 32768 866 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 867 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 868 869 #define R600_PTE_VALID (1 << 0) 870 #define R600_PTE_SYSTEM (1 << 1) 871 #define R600_PTE_SNOOPED (1 << 2) 872 #define R600_PTE_READABLE (1 << 5) 873 #define R600_PTE_WRITEABLE (1 << 6) 874 875 /* PTE (Page Table Entry) fragment field for different page sizes */ 876 #define R600_PTE_FRAG_4KB (0 << 7) 877 #define R600_PTE_FRAG_64KB (4 << 7) 878 #define R600_PTE_FRAG_256KB (6 << 7) 879 880 /* flags needed to be set so we can copy directly from the GART table */ 881 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ 882 R600_PTE_SYSTEM | R600_PTE_VALID ) 883 884 struct radeon_vm_pt { 885 struct radeon_bo *bo; 886 uint64_t addr; 887 }; 888 889 struct radeon_vm { 890 struct list_head va; 891 unsigned id; 892 893 /* BOs moved, but not yet updated in the PT */ 894 struct list_head invalidated; 895 896 /* BOs freed, but not yet updated in the PT */ 897 struct list_head freed; 898 899 /* contains the page directory */ 900 struct radeon_bo *page_directory; 901 uint64_t pd_gpu_addr; 902 unsigned max_pde_used; 903 904 /* array of page tables, one for each page directory entry */ 905 struct radeon_vm_pt *page_tables; 906 907 struct radeon_bo_va *ib_bo_va; 908 909 struct lock mutex; 910 /* last fence for cs using this vm */ 911 struct radeon_fence *fence; 912 /* last flush or NULL if we still need to flush */ 913 struct radeon_fence *last_flush; 914 /* last use of vmid */ 915 struct radeon_fence *last_id_use; 916 }; 917 918 struct radeon_vm_manager { 919 struct radeon_fence *active[RADEON_NUM_VM]; 920 uint32_t max_pfn; 921 /* number of VMIDs */ 922 unsigned nvm; 923 /* vram base address for page table entry */ 924 u64 vram_base_offset; 925 /* is vm enabled? */ 926 bool enabled; 927 /* for hw to save the PD addr on suspend/resume */ 928 uint32_t saved_table_addr[RADEON_NUM_VM]; 929 }; 930 931 /* 932 * file private structure 933 */ 934 struct radeon_fpriv { 935 struct radeon_vm vm; 936 }; 937 938 /* 939 * R6xx+ IH ring 940 */ 941 struct r600_ih { 942 struct radeon_bo *ring_obj; 943 volatile uint32_t *ring; 944 unsigned rptr; 945 unsigned ring_size; 946 uint64_t gpu_addr; 947 uint32_t ptr_mask; 948 atomic_t lock; 949 bool enabled; 950 }; 951 952 /* 953 * RLC stuff 954 */ 955 #include "clearstate_defs.h" 956 957 struct radeon_rlc { 958 /* for power gating */ 959 struct radeon_bo *save_restore_obj; 960 uint64_t save_restore_gpu_addr; 961 volatile uint32_t *sr_ptr; 962 const u32 *reg_list; 963 u32 reg_list_size; 964 /* for clear state */ 965 struct radeon_bo *clear_state_obj; 966 uint64_t clear_state_gpu_addr; 967 volatile uint32_t *cs_ptr; 968 const struct cs_section_def *cs_data; 969 u32 clear_state_size; 970 /* for cp tables */ 971 struct radeon_bo *cp_table_obj; 972 uint64_t cp_table_gpu_addr; 973 volatile uint32_t *cp_table_ptr; 974 u32 cp_table_size; 975 }; 976 977 int radeon_ib_get(struct radeon_device *rdev, int ring, 978 struct radeon_ib *ib, struct radeon_vm *vm, 979 unsigned size); 980 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 981 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 982 struct radeon_ib *const_ib, bool hdp_flush); 983 int radeon_ib_pool_init(struct radeon_device *rdev); 984 void radeon_ib_pool_fini(struct radeon_device *rdev); 985 int radeon_ib_ring_tests(struct radeon_device *rdev); 986 /* Ring access between begin & end cannot sleep */ 987 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 988 struct radeon_ring *ring); 989 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 990 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 991 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 992 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, 993 bool hdp_flush); 994 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, 995 bool hdp_flush); 996 void radeon_ring_undo(struct radeon_ring *ring); 997 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 998 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 999 void radeon_ring_lockup_update(struct radeon_device *rdev, 1000 struct radeon_ring *ring); 1001 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 1002 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 1003 uint32_t **data); 1004 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 1005 unsigned size, uint32_t *data); 1006 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 1007 unsigned rptr_offs, u32 nop); 1008 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 1009 1010 1011 /* r600 async dma */ 1012 void r600_dma_stop(struct radeon_device *rdev); 1013 int r600_dma_resume(struct radeon_device *rdev); 1014 void r600_dma_fini(struct radeon_device *rdev); 1015 1016 void cayman_dma_stop(struct radeon_device *rdev); 1017 int cayman_dma_resume(struct radeon_device *rdev); 1018 void cayman_dma_fini(struct radeon_device *rdev); 1019 1020 /* 1021 * CS. 1022 */ 1023 struct radeon_cs_reloc { 1024 struct drm_gem_object *gobj; 1025 struct radeon_bo *robj; 1026 struct ttm_validate_buffer tv; 1027 uint64_t gpu_offset; 1028 unsigned prefered_domains; 1029 unsigned allowed_domains; 1030 uint32_t tiling_flags; 1031 uint32_t handle; 1032 }; 1033 1034 struct radeon_cs_chunk { 1035 uint32_t chunk_id; 1036 uint32_t length_dw; 1037 uint32_t *kdata; 1038 void __user *user_ptr; 1039 }; 1040 1041 struct radeon_cs_parser { 1042 device_t dev; 1043 struct radeon_device *rdev; 1044 struct drm_file *filp; 1045 /* chunks */ 1046 unsigned nchunks; 1047 struct radeon_cs_chunk *chunks; 1048 uint64_t *chunks_array; 1049 /* IB */ 1050 unsigned idx; 1051 /* relocations */ 1052 unsigned nrelocs; 1053 struct radeon_cs_reloc *relocs; 1054 struct radeon_cs_reloc **relocs_ptr; 1055 struct radeon_cs_reloc *vm_bos; 1056 struct list_head validated; 1057 unsigned dma_reloc_idx; 1058 /* indices of various chunks */ 1059 int chunk_ib_idx; 1060 int chunk_relocs_idx; 1061 int chunk_flags_idx; 1062 int chunk_const_ib_idx; 1063 struct radeon_ib ib; 1064 struct radeon_ib const_ib; 1065 void *track; 1066 unsigned family; 1067 int parser_error; 1068 u32 cs_flags; 1069 u32 ring; 1070 s32 priority; 1071 struct ww_acquire_ctx ticket; 1072 }; 1073 1074 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1075 { 1076 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 1077 1078 if (ibc->kdata) 1079 return ibc->kdata[idx]; 1080 return p->ib.ptr[idx]; 1081 } 1082 1083 1084 struct radeon_cs_packet { 1085 unsigned idx; 1086 unsigned type; 1087 unsigned reg; 1088 unsigned opcode; 1089 int count; 1090 unsigned one_reg_wr; 1091 }; 1092 1093 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1094 struct radeon_cs_packet *pkt, 1095 unsigned idx, unsigned reg); 1096 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 1097 struct radeon_cs_packet *pkt); 1098 1099 1100 /* 1101 * AGP 1102 */ 1103 int radeon_agp_init(struct radeon_device *rdev); 1104 void radeon_agp_resume(struct radeon_device *rdev); 1105 void radeon_agp_suspend(struct radeon_device *rdev); 1106 void radeon_agp_fini(struct radeon_device *rdev); 1107 1108 1109 /* 1110 * Writeback 1111 */ 1112 struct radeon_wb { 1113 struct radeon_bo *wb_obj; 1114 volatile uint32_t *wb; 1115 uint64_t gpu_addr; 1116 bool enabled; 1117 bool use_event; 1118 }; 1119 1120 #define RADEON_WB_SCRATCH_OFFSET 0 1121 #define RADEON_WB_RING0_NEXT_RPTR 256 1122 #define RADEON_WB_CP_RPTR_OFFSET 1024 1123 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1124 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1125 #define R600_WB_DMA_RPTR_OFFSET 1792 1126 #define R600_WB_IH_WPTR_OFFSET 2048 1127 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1128 #define R600_WB_EVENT_OFFSET 3072 1129 #define CIK_WB_CP1_WPTR_OFFSET 3328 1130 #define CIK_WB_CP2_WPTR_OFFSET 3584 1131 1132 /** 1133 * struct radeon_pm - power management datas 1134 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1135 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1136 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1137 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1138 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1139 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1140 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1141 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1142 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1143 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1144 * @needed_bandwidth: current bandwidth needs 1145 * 1146 * It keeps track of various data needed to take powermanagement decision. 1147 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1148 * Equation between gpu/memory clock and available bandwidth is hw dependent 1149 * (type of memory, bus size, efficiency, ...) 1150 */ 1151 1152 enum radeon_pm_method { 1153 PM_METHOD_PROFILE, 1154 PM_METHOD_DYNPM, 1155 PM_METHOD_DPM, 1156 }; 1157 1158 enum radeon_dynpm_state { 1159 DYNPM_STATE_DISABLED, 1160 DYNPM_STATE_MINIMUM, 1161 DYNPM_STATE_PAUSED, 1162 DYNPM_STATE_ACTIVE, 1163 DYNPM_STATE_SUSPENDED, 1164 }; 1165 enum radeon_dynpm_action { 1166 DYNPM_ACTION_NONE, 1167 DYNPM_ACTION_MINIMUM, 1168 DYNPM_ACTION_DOWNCLOCK, 1169 DYNPM_ACTION_UPCLOCK, 1170 DYNPM_ACTION_DEFAULT 1171 }; 1172 1173 enum radeon_voltage_type { 1174 VOLTAGE_NONE = 0, 1175 VOLTAGE_GPIO, 1176 VOLTAGE_VDDC, 1177 VOLTAGE_SW 1178 }; 1179 1180 enum radeon_pm_state_type { 1181 /* not used for dpm */ 1182 POWER_STATE_TYPE_DEFAULT, 1183 POWER_STATE_TYPE_POWERSAVE, 1184 /* user selectable states */ 1185 POWER_STATE_TYPE_BATTERY, 1186 POWER_STATE_TYPE_BALANCED, 1187 POWER_STATE_TYPE_PERFORMANCE, 1188 /* internal states */ 1189 POWER_STATE_TYPE_INTERNAL_UVD, 1190 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1191 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1192 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1193 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1194 POWER_STATE_TYPE_INTERNAL_BOOT, 1195 POWER_STATE_TYPE_INTERNAL_THERMAL, 1196 POWER_STATE_TYPE_INTERNAL_ACPI, 1197 POWER_STATE_TYPE_INTERNAL_ULV, 1198 POWER_STATE_TYPE_INTERNAL_3DPERF, 1199 }; 1200 1201 enum radeon_pm_profile_type { 1202 PM_PROFILE_DEFAULT, 1203 PM_PROFILE_AUTO, 1204 PM_PROFILE_LOW, 1205 PM_PROFILE_MID, 1206 PM_PROFILE_HIGH, 1207 }; 1208 1209 #define PM_PROFILE_DEFAULT_IDX 0 1210 #define PM_PROFILE_LOW_SH_IDX 1 1211 #define PM_PROFILE_MID_SH_IDX 2 1212 #define PM_PROFILE_HIGH_SH_IDX 3 1213 #define PM_PROFILE_LOW_MH_IDX 4 1214 #define PM_PROFILE_MID_MH_IDX 5 1215 #define PM_PROFILE_HIGH_MH_IDX 6 1216 #define PM_PROFILE_MAX 7 1217 1218 struct radeon_pm_profile { 1219 int dpms_off_ps_idx; 1220 int dpms_on_ps_idx; 1221 int dpms_off_cm_idx; 1222 int dpms_on_cm_idx; 1223 }; 1224 1225 enum radeon_int_thermal_type { 1226 THERMAL_TYPE_NONE, 1227 THERMAL_TYPE_EXTERNAL, 1228 THERMAL_TYPE_EXTERNAL_GPIO, 1229 THERMAL_TYPE_RV6XX, 1230 THERMAL_TYPE_RV770, 1231 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1232 THERMAL_TYPE_EVERGREEN, 1233 THERMAL_TYPE_SUMO, 1234 THERMAL_TYPE_NI, 1235 THERMAL_TYPE_SI, 1236 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1237 THERMAL_TYPE_CI, 1238 THERMAL_TYPE_KV, 1239 }; 1240 1241 struct radeon_voltage { 1242 enum radeon_voltage_type type; 1243 /* gpio voltage */ 1244 struct radeon_gpio_rec gpio; 1245 u32 delay; /* delay in usec from voltage drop to sclk change */ 1246 bool active_high; /* voltage drop is active when bit is high */ 1247 /* VDDC voltage */ 1248 u8 vddc_id; /* index into vddc voltage table */ 1249 u8 vddci_id; /* index into vddci voltage table */ 1250 bool vddci_enabled; 1251 /* r6xx+ sw */ 1252 u16 voltage; 1253 /* evergreen+ vddci */ 1254 u16 vddci; 1255 }; 1256 1257 /* clock mode flags */ 1258 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1259 1260 struct radeon_pm_clock_info { 1261 /* memory clock */ 1262 u32 mclk; 1263 /* engine clock */ 1264 u32 sclk; 1265 /* voltage info */ 1266 struct radeon_voltage voltage; 1267 /* standardized clock flags */ 1268 u32 flags; 1269 }; 1270 1271 /* state flags */ 1272 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1273 1274 struct radeon_power_state { 1275 enum radeon_pm_state_type type; 1276 struct radeon_pm_clock_info *clock_info; 1277 /* number of valid clock modes in this power state */ 1278 int num_clock_modes; 1279 struct radeon_pm_clock_info *default_clock_mode; 1280 /* standardized state flags */ 1281 u32 flags; 1282 u32 misc; /* vbios specific flags */ 1283 u32 misc2; /* vbios specific flags */ 1284 int pcie_lanes; /* pcie lanes */ 1285 }; 1286 1287 /* 1288 * Some modes are overclocked by very low value, accept them 1289 */ 1290 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1291 1292 enum radeon_dpm_auto_throttle_src { 1293 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1294 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1295 }; 1296 1297 enum radeon_dpm_event_src { 1298 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1299 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1300 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1301 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1302 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1303 }; 1304 1305 #define RADEON_MAX_VCE_LEVELS 6 1306 1307 enum radeon_vce_level { 1308 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1309 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1310 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1311 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1312 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1313 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1314 }; 1315 1316 struct radeon_ps { 1317 u32 caps; /* vbios flags */ 1318 u32 class; /* vbios flags */ 1319 u32 class2; /* vbios flags */ 1320 /* UVD clocks */ 1321 u32 vclk; 1322 u32 dclk; 1323 /* VCE clocks */ 1324 u32 evclk; 1325 u32 ecclk; 1326 bool vce_active; 1327 enum radeon_vce_level vce_level; 1328 /* asic priv */ 1329 void *ps_priv; 1330 }; 1331 1332 struct radeon_dpm_thermal { 1333 /* thermal interrupt work */ 1334 struct task work; 1335 /* low temperature threshold */ 1336 int min_temp; 1337 /* high temperature threshold */ 1338 int max_temp; 1339 /* was interrupt low to high or high to low */ 1340 bool high_to_low; 1341 }; 1342 1343 enum radeon_clk_action 1344 { 1345 RADEON_SCLK_UP = 1, 1346 RADEON_SCLK_DOWN 1347 }; 1348 1349 struct radeon_blacklist_clocks 1350 { 1351 u32 sclk; 1352 u32 mclk; 1353 enum radeon_clk_action action; 1354 }; 1355 1356 struct radeon_clock_and_voltage_limits { 1357 u32 sclk; 1358 u32 mclk; 1359 u16 vddc; 1360 u16 vddci; 1361 }; 1362 1363 struct radeon_clock_array { 1364 u32 count; 1365 u32 *values; 1366 }; 1367 1368 struct radeon_clock_voltage_dependency_entry { 1369 u32 clk; 1370 u16 v; 1371 }; 1372 1373 struct radeon_clock_voltage_dependency_table { 1374 u32 count; 1375 struct radeon_clock_voltage_dependency_entry *entries; 1376 }; 1377 1378 union radeon_cac_leakage_entry { 1379 struct { 1380 u16 vddc; 1381 u32 leakage; 1382 }; 1383 struct { 1384 u16 vddc1; 1385 u16 vddc2; 1386 u16 vddc3; 1387 }; 1388 }; 1389 1390 struct radeon_cac_leakage_table { 1391 u32 count; 1392 union radeon_cac_leakage_entry *entries; 1393 }; 1394 1395 struct radeon_phase_shedding_limits_entry { 1396 u16 voltage; 1397 u32 sclk; 1398 u32 mclk; 1399 }; 1400 1401 struct radeon_phase_shedding_limits_table { 1402 u32 count; 1403 struct radeon_phase_shedding_limits_entry *entries; 1404 }; 1405 1406 struct radeon_uvd_clock_voltage_dependency_entry { 1407 u32 vclk; 1408 u32 dclk; 1409 u16 v; 1410 }; 1411 1412 struct radeon_uvd_clock_voltage_dependency_table { 1413 u8 count; 1414 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1415 }; 1416 1417 struct radeon_vce_clock_voltage_dependency_entry { 1418 u32 ecclk; 1419 u32 evclk; 1420 u16 v; 1421 }; 1422 1423 struct radeon_vce_clock_voltage_dependency_table { 1424 u8 count; 1425 struct radeon_vce_clock_voltage_dependency_entry *entries; 1426 }; 1427 1428 struct radeon_ppm_table { 1429 u8 ppm_design; 1430 u16 cpu_core_number; 1431 u32 platform_tdp; 1432 u32 small_ac_platform_tdp; 1433 u32 platform_tdc; 1434 u32 small_ac_platform_tdc; 1435 u32 apu_tdp; 1436 u32 dgpu_tdp; 1437 u32 dgpu_ulv_power; 1438 u32 tj_max; 1439 }; 1440 1441 struct radeon_cac_tdp_table { 1442 u16 tdp; 1443 u16 configurable_tdp; 1444 u16 tdc; 1445 u16 battery_power_limit; 1446 u16 small_power_limit; 1447 u16 low_cac_leakage; 1448 u16 high_cac_leakage; 1449 u16 maximum_power_delivery_limit; 1450 }; 1451 1452 struct radeon_dpm_dynamic_state { 1453 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1454 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1455 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1456 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1457 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1458 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1459 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1460 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1461 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1462 struct radeon_clock_array valid_sclk_values; 1463 struct radeon_clock_array valid_mclk_values; 1464 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1465 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1466 u32 mclk_sclk_ratio; 1467 u32 sclk_mclk_delta; 1468 u16 vddc_vddci_delta; 1469 u16 min_vddc_for_pcie_gen2; 1470 struct radeon_cac_leakage_table cac_leakage_table; 1471 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1472 struct radeon_ppm_table *ppm_table; 1473 struct radeon_cac_tdp_table *cac_tdp_table; 1474 }; 1475 1476 struct radeon_dpm_fan { 1477 u16 t_min; 1478 u16 t_med; 1479 u16 t_high; 1480 u16 pwm_min; 1481 u16 pwm_med; 1482 u16 pwm_high; 1483 u8 t_hyst; 1484 u32 cycle_delay; 1485 u16 t_max; 1486 bool ucode_fan_control; 1487 }; 1488 1489 enum radeon_pcie_gen { 1490 RADEON_PCIE_GEN1 = 0, 1491 RADEON_PCIE_GEN2 = 1, 1492 RADEON_PCIE_GEN3 = 2, 1493 RADEON_PCIE_GEN_INVALID = 0xffff 1494 }; 1495 1496 enum radeon_dpm_forced_level { 1497 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1498 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1499 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1500 }; 1501 1502 struct radeon_vce_state { 1503 /* vce clocks */ 1504 u32 evclk; 1505 u32 ecclk; 1506 /* gpu clocks */ 1507 u32 sclk; 1508 u32 mclk; 1509 u8 clk_idx; 1510 u8 pstate; 1511 }; 1512 1513 struct radeon_dpm { 1514 struct radeon_ps *ps; 1515 /* number of valid power states */ 1516 int num_ps; 1517 /* current power state that is active */ 1518 struct radeon_ps *current_ps; 1519 /* requested power state */ 1520 struct radeon_ps *requested_ps; 1521 /* boot up power state */ 1522 struct radeon_ps *boot_ps; 1523 /* default uvd power state */ 1524 struct radeon_ps *uvd_ps; 1525 /* vce requirements */ 1526 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1527 enum radeon_vce_level vce_level; 1528 enum radeon_pm_state_type state; 1529 enum radeon_pm_state_type user_state; 1530 u32 platform_caps; 1531 u32 voltage_response_time; 1532 u32 backbias_response_time; 1533 void *priv; 1534 u32 new_active_crtcs; 1535 int new_active_crtc_count; 1536 u32 current_active_crtcs; 1537 int current_active_crtc_count; 1538 struct radeon_dpm_dynamic_state dyn_state; 1539 struct radeon_dpm_fan fan; 1540 u32 tdp_limit; 1541 u32 near_tdp_limit; 1542 u32 near_tdp_limit_adjusted; 1543 u32 sq_ramping_threshold; 1544 u32 cac_leakage; 1545 u16 tdp_od_limit; 1546 u32 tdp_adjustment; 1547 u16 load_line_slope; 1548 bool power_control; 1549 bool ac_power; 1550 /* special states active */ 1551 bool thermal_active; 1552 bool uvd_active; 1553 bool vce_active; 1554 /* thermal handling */ 1555 struct radeon_dpm_thermal thermal; 1556 /* forced levels */ 1557 enum radeon_dpm_forced_level forced_level; 1558 /* track UVD streams */ 1559 unsigned sd; 1560 unsigned hd; 1561 }; 1562 1563 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1564 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1565 1566 struct radeon_pm { 1567 struct lock mutex; 1568 /* write locked while reprogramming mclk */ 1569 struct lock mclk_lock; 1570 u32 active_crtcs; 1571 int active_crtc_count; 1572 int req_vblank; 1573 bool vblank_sync; 1574 fixed20_12 max_bandwidth; 1575 fixed20_12 igp_sideport_mclk; 1576 fixed20_12 igp_system_mclk; 1577 fixed20_12 igp_ht_link_clk; 1578 fixed20_12 igp_ht_link_width; 1579 fixed20_12 k8_bandwidth; 1580 fixed20_12 sideport_bandwidth; 1581 fixed20_12 ht_bandwidth; 1582 fixed20_12 core_bandwidth; 1583 fixed20_12 sclk; 1584 fixed20_12 mclk; 1585 fixed20_12 needed_bandwidth; 1586 struct radeon_power_state *power_state; 1587 /* number of valid power states */ 1588 int num_power_states; 1589 int current_power_state_index; 1590 int current_clock_mode_index; 1591 int requested_power_state_index; 1592 int requested_clock_mode_index; 1593 int default_power_state_index; 1594 u32 current_sclk; 1595 u32 current_mclk; 1596 u16 current_vddc; 1597 u16 current_vddci; 1598 u32 default_sclk; 1599 u32 default_mclk; 1600 u16 default_vddc; 1601 u16 default_vddci; 1602 struct radeon_i2c_chan *i2c_bus; 1603 /* selected pm method */ 1604 enum radeon_pm_method pm_method; 1605 /* dynpm power management */ 1606 #ifdef DUMBBELL_WIP 1607 struct delayed_work dynpm_idle_work; 1608 #endif /* DUMBBELL_WIP */ 1609 enum radeon_dynpm_state dynpm_state; 1610 enum radeon_dynpm_action dynpm_planned_action; 1611 unsigned long dynpm_action_timeout; 1612 bool dynpm_can_upclock; 1613 bool dynpm_can_downclock; 1614 /* profile-based power management */ 1615 enum radeon_pm_profile_type profile; 1616 int profile_index; 1617 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1618 /* internal thermal controller on rv6xx+ */ 1619 enum radeon_int_thermal_type int_thermal_type; 1620 struct ksensor *int_sensor; 1621 struct ksensordev *int_sensordev; 1622 /* dpm */ 1623 bool dpm_enabled; 1624 struct radeon_dpm dpm; 1625 }; 1626 1627 int radeon_pm_get_type_index(struct radeon_device *rdev, 1628 enum radeon_pm_state_type ps_type, 1629 int instance); 1630 /* 1631 * UVD 1632 */ 1633 #define RADEON_MAX_UVD_HANDLES 10 1634 #define RADEON_UVD_STACK_SIZE (1024*1024) 1635 #define RADEON_UVD_HEAP_SIZE (1024*1024) 1636 1637 struct radeon_uvd { 1638 struct radeon_bo *vcpu_bo; 1639 void *cpu_addr; 1640 uint64_t gpu_addr; 1641 void *saved_bo; 1642 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1643 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1644 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1645 struct delayed_work idle_work; 1646 }; 1647 1648 int radeon_uvd_init(struct radeon_device *rdev); 1649 void radeon_uvd_fini(struct radeon_device *rdev); 1650 int radeon_uvd_suspend(struct radeon_device *rdev); 1651 int radeon_uvd_resume(struct radeon_device *rdev); 1652 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1653 uint32_t handle, struct radeon_fence **fence); 1654 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1655 uint32_t handle, struct radeon_fence **fence); 1656 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo); 1657 void radeon_uvd_free_handles(struct radeon_device *rdev, 1658 struct drm_file *filp); 1659 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1660 void radeon_uvd_note_usage(struct radeon_device *rdev); 1661 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1662 unsigned vclk, unsigned dclk, 1663 unsigned vco_min, unsigned vco_max, 1664 unsigned fb_factor, unsigned fb_mask, 1665 unsigned pd_min, unsigned pd_max, 1666 unsigned pd_even, 1667 unsigned *optimal_fb_div, 1668 unsigned *optimal_vclk_div, 1669 unsigned *optimal_dclk_div); 1670 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1671 unsigned cg_upll_func_cntl); 1672 1673 /* 1674 * VCE 1675 */ 1676 #define RADEON_MAX_VCE_HANDLES 16 1677 #define RADEON_VCE_STACK_SIZE (1024*1024) 1678 #define RADEON_VCE_HEAP_SIZE (4*1024*1024) 1679 1680 struct radeon_vce { 1681 struct radeon_bo *vcpu_bo; 1682 uint64_t gpu_addr; 1683 unsigned fw_version; 1684 unsigned fb_version; 1685 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1686 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1687 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1688 struct delayed_work idle_work; 1689 }; 1690 1691 int radeon_vce_init(struct radeon_device *rdev); 1692 void radeon_vce_fini(struct radeon_device *rdev); 1693 int radeon_vce_suspend(struct radeon_device *rdev); 1694 int radeon_vce_resume(struct radeon_device *rdev); 1695 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1696 uint32_t handle, struct radeon_fence **fence); 1697 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1698 uint32_t handle, struct radeon_fence **fence); 1699 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1700 void radeon_vce_note_usage(struct radeon_device *rdev); 1701 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1702 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1703 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1704 struct radeon_ring *ring, 1705 struct radeon_semaphore *semaphore, 1706 bool emit_wait); 1707 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1708 void radeon_vce_fence_emit(struct radeon_device *rdev, 1709 struct radeon_fence *fence); 1710 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1711 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1712 1713 struct r600_audio_pin { 1714 int channels; 1715 int rate; 1716 int bits_per_sample; 1717 u8 status_bits; 1718 u8 category_code; 1719 u32 offset; 1720 bool connected; 1721 u32 id; 1722 }; 1723 1724 struct r600_audio { 1725 bool enabled; 1726 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1727 int num_pins; 1728 }; 1729 1730 /* 1731 * Benchmarking 1732 */ 1733 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1734 1735 1736 /* 1737 * Testing 1738 */ 1739 void radeon_test_moves(struct radeon_device *rdev); 1740 void radeon_test_ring_sync(struct radeon_device *rdev, 1741 struct radeon_ring *cpA, 1742 struct radeon_ring *cpB); 1743 void radeon_test_syncing(struct radeon_device *rdev); 1744 1745 1746 /* 1747 * Debugfs 1748 */ 1749 struct radeon_debugfs { 1750 struct drm_info_list *files; 1751 unsigned num_files; 1752 }; 1753 1754 int radeon_debugfs_add_files(struct radeon_device *rdev, 1755 struct drm_info_list *files, 1756 unsigned nfiles); 1757 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1758 1759 /* 1760 * ASIC ring specific functions. 1761 */ 1762 struct radeon_asic_ring { 1763 /* ring read/write ptr handling */ 1764 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1765 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1766 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1767 1768 /* validating and patching of IBs */ 1769 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1770 int (*cs_parse)(struct radeon_cs_parser *p); 1771 1772 /* command emmit functions */ 1773 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1774 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1775 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); 1776 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1777 struct radeon_semaphore *semaphore, bool emit_wait); 1778 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 1779 1780 /* testing functions */ 1781 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1782 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1783 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1784 1785 /* deprecated */ 1786 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1787 }; 1788 1789 /* 1790 * ASIC specific functions. 1791 */ 1792 struct radeon_asic { 1793 int (*init)(struct radeon_device *rdev); 1794 void (*fini)(struct radeon_device *rdev); 1795 int (*resume)(struct radeon_device *rdev); 1796 int (*suspend)(struct radeon_device *rdev); 1797 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1798 int (*asic_reset)(struct radeon_device *rdev); 1799 /* Flush the HDP cache via MMIO */ 1800 void (*mmio_hdp_flush)(struct radeon_device *rdev); 1801 /* check if 3D engine is idle */ 1802 bool (*gui_idle)(struct radeon_device *rdev); 1803 /* wait for mc_idle */ 1804 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1805 /* get the reference clock */ 1806 u32 (*get_xclk)(struct radeon_device *rdev); 1807 /* get the gpu clock counter */ 1808 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1809 /* gart */ 1810 struct { 1811 void (*tlb_flush)(struct radeon_device *rdev); 1812 void (*set_page)(struct radeon_device *rdev, unsigned i, 1813 uint64_t addr, uint32_t flags); 1814 } gart; 1815 struct { 1816 int (*init)(struct radeon_device *rdev); 1817 void (*fini)(struct radeon_device *rdev); 1818 void (*copy_pages)(struct radeon_device *rdev, 1819 struct radeon_ib *ib, 1820 uint64_t pe, uint64_t src, 1821 unsigned count); 1822 void (*write_pages)(struct radeon_device *rdev, 1823 struct radeon_ib *ib, 1824 uint64_t pe, 1825 uint64_t addr, unsigned count, 1826 uint32_t incr, uint32_t flags); 1827 void (*set_pages)(struct radeon_device *rdev, 1828 struct radeon_ib *ib, 1829 uint64_t pe, 1830 uint64_t addr, unsigned count, 1831 uint32_t incr, uint32_t flags); 1832 void (*pad_ib)(struct radeon_ib *ib); 1833 } vm; 1834 /* ring specific callbacks */ 1835 struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1836 /* irqs */ 1837 struct { 1838 int (*set)(struct radeon_device *rdev); 1839 irqreturn_t (*process)(struct radeon_device *rdev); 1840 } irq; 1841 /* displays */ 1842 struct { 1843 /* display watermarks */ 1844 void (*bandwidth_update)(struct radeon_device *rdev); 1845 /* get frame count */ 1846 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1847 /* wait for vblank */ 1848 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1849 /* set backlight level */ 1850 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1851 /* get backlight level */ 1852 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1853 /* audio callbacks */ 1854 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1855 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1856 } display; 1857 /* copy functions for bo handling */ 1858 struct { 1859 int (*blit)(struct radeon_device *rdev, 1860 uint64_t src_offset, 1861 uint64_t dst_offset, 1862 unsigned num_gpu_pages, 1863 struct radeon_fence **fence); 1864 u32 blit_ring_index; 1865 int (*dma)(struct radeon_device *rdev, 1866 uint64_t src_offset, 1867 uint64_t dst_offset, 1868 unsigned num_gpu_pages, 1869 struct radeon_fence **fence); 1870 u32 dma_ring_index; 1871 /* method used for bo copy */ 1872 int (*copy)(struct radeon_device *rdev, 1873 uint64_t src_offset, 1874 uint64_t dst_offset, 1875 unsigned num_gpu_pages, 1876 struct radeon_fence **fence); 1877 /* ring used for bo copies */ 1878 u32 copy_ring_index; 1879 } copy; 1880 /* surfaces */ 1881 struct { 1882 int (*set_reg)(struct radeon_device *rdev, int reg, 1883 uint32_t tiling_flags, uint32_t pitch, 1884 uint32_t offset, uint32_t obj_size); 1885 void (*clear_reg)(struct radeon_device *rdev, int reg); 1886 } surface; 1887 /* hotplug detect */ 1888 struct { 1889 void (*init)(struct radeon_device *rdev); 1890 void (*fini)(struct radeon_device *rdev); 1891 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1892 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1893 } hpd; 1894 /* static power management */ 1895 struct { 1896 void (*misc)(struct radeon_device *rdev); 1897 void (*prepare)(struct radeon_device *rdev); 1898 void (*finish)(struct radeon_device *rdev); 1899 void (*init_profile)(struct radeon_device *rdev); 1900 void (*get_dynpm_state)(struct radeon_device *rdev); 1901 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1902 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1903 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1904 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1905 int (*get_pcie_lanes)(struct radeon_device *rdev); 1906 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1907 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1908 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 1909 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 1910 int (*get_temperature)(struct radeon_device *rdev); 1911 } pm; 1912 /* dynamic power management */ 1913 struct { 1914 int (*init)(struct radeon_device *rdev); 1915 void (*setup_asic)(struct radeon_device *rdev); 1916 int (*enable)(struct radeon_device *rdev); 1917 int (*late_enable)(struct radeon_device *rdev); 1918 void (*disable)(struct radeon_device *rdev); 1919 int (*pre_set_power_state)(struct radeon_device *rdev); 1920 int (*set_power_state)(struct radeon_device *rdev); 1921 void (*post_set_power_state)(struct radeon_device *rdev); 1922 void (*display_configuration_changed)(struct radeon_device *rdev); 1923 void (*fini)(struct radeon_device *rdev); 1924 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 1925 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 1926 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 1927 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 1928 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 1929 bool (*vblank_too_short)(struct radeon_device *rdev); 1930 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 1931 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 1932 } dpm; 1933 /* pageflipping */ 1934 struct { 1935 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 1936 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); 1937 } pflip; 1938 }; 1939 1940 /* 1941 * Asic structures 1942 */ 1943 struct r100_asic { 1944 const unsigned *reg_safe_bm; 1945 unsigned reg_safe_bm_size; 1946 u32 hdp_cntl; 1947 }; 1948 1949 struct r300_asic { 1950 const unsigned *reg_safe_bm; 1951 unsigned reg_safe_bm_size; 1952 u32 resync_scratch; 1953 u32 hdp_cntl; 1954 }; 1955 1956 struct r600_asic { 1957 unsigned max_pipes; 1958 unsigned max_tile_pipes; 1959 unsigned max_simds; 1960 unsigned max_backends; 1961 unsigned max_gprs; 1962 unsigned max_threads; 1963 unsigned max_stack_entries; 1964 unsigned max_hw_contexts; 1965 unsigned max_gs_threads; 1966 unsigned sx_max_export_size; 1967 unsigned sx_max_export_pos_size; 1968 unsigned sx_max_export_smx_size; 1969 unsigned sq_num_cf_insts; 1970 unsigned tiling_nbanks; 1971 unsigned tiling_npipes; 1972 unsigned tiling_group_size; 1973 unsigned tile_config; 1974 unsigned backend_map; 1975 unsigned active_simds; 1976 }; 1977 1978 struct rv770_asic { 1979 unsigned max_pipes; 1980 unsigned max_tile_pipes; 1981 unsigned max_simds; 1982 unsigned max_backends; 1983 unsigned max_gprs; 1984 unsigned max_threads; 1985 unsigned max_stack_entries; 1986 unsigned max_hw_contexts; 1987 unsigned max_gs_threads; 1988 unsigned sx_max_export_size; 1989 unsigned sx_max_export_pos_size; 1990 unsigned sx_max_export_smx_size; 1991 unsigned sq_num_cf_insts; 1992 unsigned sx_num_of_sets; 1993 unsigned sc_prim_fifo_size; 1994 unsigned sc_hiz_tile_fifo_size; 1995 unsigned sc_earlyz_tile_fifo_fize; 1996 unsigned tiling_nbanks; 1997 unsigned tiling_npipes; 1998 unsigned tiling_group_size; 1999 unsigned tile_config; 2000 unsigned backend_map; 2001 unsigned active_simds; 2002 }; 2003 2004 struct evergreen_asic { 2005 unsigned num_ses; 2006 unsigned max_pipes; 2007 unsigned max_tile_pipes; 2008 unsigned max_simds; 2009 unsigned max_backends; 2010 unsigned max_gprs; 2011 unsigned max_threads; 2012 unsigned max_stack_entries; 2013 unsigned max_hw_contexts; 2014 unsigned max_gs_threads; 2015 unsigned sx_max_export_size; 2016 unsigned sx_max_export_pos_size; 2017 unsigned sx_max_export_smx_size; 2018 unsigned sq_num_cf_insts; 2019 unsigned sx_num_of_sets; 2020 unsigned sc_prim_fifo_size; 2021 unsigned sc_hiz_tile_fifo_size; 2022 unsigned sc_earlyz_tile_fifo_size; 2023 unsigned tiling_nbanks; 2024 unsigned tiling_npipes; 2025 unsigned tiling_group_size; 2026 unsigned tile_config; 2027 unsigned backend_map; 2028 unsigned active_simds; 2029 }; 2030 2031 struct cayman_asic { 2032 unsigned max_shader_engines; 2033 unsigned max_pipes_per_simd; 2034 unsigned max_tile_pipes; 2035 unsigned max_simds_per_se; 2036 unsigned max_backends_per_se; 2037 unsigned max_texture_channel_caches; 2038 unsigned max_gprs; 2039 unsigned max_threads; 2040 unsigned max_gs_threads; 2041 unsigned max_stack_entries; 2042 unsigned sx_num_of_sets; 2043 unsigned sx_max_export_size; 2044 unsigned sx_max_export_pos_size; 2045 unsigned sx_max_export_smx_size; 2046 unsigned max_hw_contexts; 2047 unsigned sq_num_cf_insts; 2048 unsigned sc_prim_fifo_size; 2049 unsigned sc_hiz_tile_fifo_size; 2050 unsigned sc_earlyz_tile_fifo_size; 2051 2052 unsigned num_shader_engines; 2053 unsigned num_shader_pipes_per_simd; 2054 unsigned num_tile_pipes; 2055 unsigned num_simds_per_se; 2056 unsigned num_backends_per_se; 2057 unsigned backend_disable_mask_per_asic; 2058 unsigned backend_map; 2059 unsigned num_texture_channel_caches; 2060 unsigned mem_max_burst_length_bytes; 2061 unsigned mem_row_size_in_kb; 2062 unsigned shader_engine_tile_size; 2063 unsigned num_gpus; 2064 unsigned multi_gpu_tile_size; 2065 2066 unsigned tile_config; 2067 unsigned active_simds; 2068 }; 2069 2070 struct si_asic { 2071 unsigned max_shader_engines; 2072 unsigned max_tile_pipes; 2073 unsigned max_cu_per_sh; 2074 unsigned max_sh_per_se; 2075 unsigned max_backends_per_se; 2076 unsigned max_texture_channel_caches; 2077 unsigned max_gprs; 2078 unsigned max_gs_threads; 2079 unsigned max_hw_contexts; 2080 unsigned sc_prim_fifo_size_frontend; 2081 unsigned sc_prim_fifo_size_backend; 2082 unsigned sc_hiz_tile_fifo_size; 2083 unsigned sc_earlyz_tile_fifo_size; 2084 2085 unsigned num_tile_pipes; 2086 unsigned backend_enable_mask; 2087 unsigned backend_disable_mask_per_asic; 2088 unsigned backend_map; 2089 unsigned num_texture_channel_caches; 2090 unsigned mem_max_burst_length_bytes; 2091 unsigned mem_row_size_in_kb; 2092 unsigned shader_engine_tile_size; 2093 unsigned num_gpus; 2094 unsigned multi_gpu_tile_size; 2095 2096 unsigned tile_config; 2097 uint32_t tile_mode_array[32]; 2098 uint32_t active_cus; 2099 }; 2100 2101 struct cik_asic { 2102 unsigned max_shader_engines; 2103 unsigned max_tile_pipes; 2104 unsigned max_cu_per_sh; 2105 unsigned max_sh_per_se; 2106 unsigned max_backends_per_se; 2107 unsigned max_texture_channel_caches; 2108 unsigned max_gprs; 2109 unsigned max_gs_threads; 2110 unsigned max_hw_contexts; 2111 unsigned sc_prim_fifo_size_frontend; 2112 unsigned sc_prim_fifo_size_backend; 2113 unsigned sc_hiz_tile_fifo_size; 2114 unsigned sc_earlyz_tile_fifo_size; 2115 2116 unsigned num_tile_pipes; 2117 unsigned backend_enable_mask; 2118 unsigned backend_disable_mask_per_asic; 2119 unsigned backend_map; 2120 unsigned num_texture_channel_caches; 2121 unsigned mem_max_burst_length_bytes; 2122 unsigned mem_row_size_in_kb; 2123 unsigned shader_engine_tile_size; 2124 unsigned num_gpus; 2125 unsigned multi_gpu_tile_size; 2126 2127 unsigned tile_config; 2128 uint32_t tile_mode_array[32]; 2129 uint32_t macrotile_mode_array[16]; 2130 uint32_t active_cus; 2131 }; 2132 2133 union radeon_asic_config { 2134 struct r300_asic r300; 2135 struct r100_asic r100; 2136 struct r600_asic r600; 2137 struct rv770_asic rv770; 2138 struct evergreen_asic evergreen; 2139 struct cayman_asic cayman; 2140 struct si_asic si; 2141 struct cik_asic cik; 2142 }; 2143 2144 /* 2145 * asic initizalization from radeon_asic.c 2146 */ 2147 int radeon_asic_init(struct radeon_device *rdev); 2148 2149 2150 /* 2151 * IOCTL. 2152 */ 2153 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2154 struct drm_file *filp); 2155 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2156 struct drm_file *filp); 2157 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2158 struct drm_file *file_priv); 2159 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2160 struct drm_file *file_priv); 2161 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2162 struct drm_file *file_priv); 2163 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 2164 struct drm_file *file_priv); 2165 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2166 struct drm_file *filp); 2167 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2168 struct drm_file *filp); 2169 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2170 struct drm_file *filp); 2171 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2172 struct drm_file *filp); 2173 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2174 struct drm_file *filp); 2175 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2176 struct drm_file *filp); 2177 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2178 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2179 struct drm_file *filp); 2180 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2181 struct drm_file *filp); 2182 2183 /* VRAM scratch page for HDP bug, default vram page */ 2184 struct r600_vram_scratch { 2185 struct radeon_bo *robj; 2186 volatile uint32_t *ptr; 2187 u64 gpu_addr; 2188 }; 2189 2190 /* 2191 * ACPI 2192 */ 2193 struct radeon_atif_notification_cfg { 2194 bool enabled; 2195 int command_code; 2196 }; 2197 2198 struct radeon_atif_notifications { 2199 bool display_switch; 2200 bool expansion_mode_change; 2201 bool thermal_state; 2202 bool forced_power_state; 2203 bool system_power_state; 2204 bool display_conf_change; 2205 bool px_gfx_switch; 2206 bool brightness_change; 2207 bool dgpu_display_event; 2208 }; 2209 2210 struct radeon_atif_functions { 2211 bool system_params; 2212 bool sbios_requests; 2213 bool select_active_disp; 2214 bool lid_state; 2215 bool get_tv_standard; 2216 bool set_tv_standard; 2217 bool get_panel_expansion_mode; 2218 bool set_panel_expansion_mode; 2219 bool temperature_change; 2220 bool graphics_device_types; 2221 }; 2222 2223 struct radeon_atif { 2224 struct radeon_atif_notifications notifications; 2225 struct radeon_atif_functions functions; 2226 struct radeon_atif_notification_cfg notification_cfg; 2227 struct radeon_encoder *encoder_for_bl; 2228 }; 2229 2230 struct radeon_atcs_functions { 2231 bool get_ext_state; 2232 bool pcie_perf_req; 2233 bool pcie_dev_rdy; 2234 bool pcie_bus_width; 2235 }; 2236 2237 struct radeon_atcs { 2238 struct radeon_atcs_functions functions; 2239 }; 2240 2241 /* 2242 * Core structure, functions and helpers. 2243 */ 2244 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2245 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2246 2247 struct radeon_device { 2248 device_t dev; 2249 struct drm_device *ddev; 2250 struct pci_dev *pdev; 2251 struct lock exclusive_lock; 2252 /* ASIC */ 2253 union radeon_asic_config config; 2254 enum radeon_family family; 2255 unsigned long flags; 2256 int usec_timeout; 2257 enum radeon_pll_errata pll_errata; 2258 int num_gb_pipes; 2259 int num_z_pipes; 2260 int disp_priority; 2261 /* BIOS */ 2262 uint8_t *bios; 2263 bool is_atom_bios; 2264 uint16_t bios_header_start; 2265 struct radeon_bo *stollen_vga_memory; 2266 /* Register mmio */ 2267 resource_size_t rmmio_base; 2268 resource_size_t rmmio_size; 2269 /* protects concurrent MM_INDEX/DATA based register access */ 2270 struct spinlock mmio_idx_lock; 2271 /* protects concurrent SMC based register access */ 2272 struct spinlock smc_idx_lock; 2273 /* protects concurrent PLL register access */ 2274 struct spinlock pll_idx_lock; 2275 /* protects concurrent MC register access */ 2276 struct spinlock mc_idx_lock; 2277 /* protects concurrent PCIE register access */ 2278 struct spinlock pcie_idx_lock; 2279 /* protects concurrent PCIE_PORT register access */ 2280 struct spinlock pciep_idx_lock; 2281 /* protects concurrent PIF register access */ 2282 struct spinlock pif_idx_lock; 2283 /* protects concurrent CG register access */ 2284 struct spinlock cg_idx_lock; 2285 /* protects concurrent UVD register access */ 2286 struct spinlock uvd_idx_lock; 2287 /* protects concurrent RCU register access */ 2288 struct spinlock rcu_idx_lock; 2289 /* protects concurrent DIDT register access */ 2290 struct spinlock didt_idx_lock; 2291 /* protects concurrent ENDPOINT (audio) register access */ 2292 struct spinlock end_idx_lock; 2293 int rmmio_rid; 2294 struct resource *rmmio; 2295 radeon_rreg_t mc_rreg; 2296 radeon_wreg_t mc_wreg; 2297 radeon_rreg_t pll_rreg; 2298 radeon_wreg_t pll_wreg; 2299 uint32_t pcie_reg_mask; 2300 radeon_rreg_t pciep_rreg; 2301 radeon_wreg_t pciep_wreg; 2302 /* io port */ 2303 int rio_rid; 2304 struct resource *rio_mem; 2305 resource_size_t rio_mem_size; 2306 struct radeon_clock clock; 2307 struct radeon_mc mc; 2308 struct radeon_gart gart; 2309 struct radeon_mode_info mode_info; 2310 struct radeon_scratch scratch; 2311 struct radeon_doorbell doorbell; 2312 struct radeon_mman mman; 2313 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2314 wait_queue_head_t fence_queue; 2315 struct lock ring_lock; 2316 struct radeon_ring ring[RADEON_NUM_RINGS]; 2317 bool ib_pool_ready; 2318 struct radeon_sa_manager ring_tmp_bo; 2319 struct radeon_irq irq; 2320 struct radeon_asic *asic; 2321 struct radeon_gem gem; 2322 struct radeon_pm pm; 2323 struct radeon_uvd uvd; 2324 struct radeon_vce vce; 2325 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2326 struct radeon_wb wb; 2327 struct radeon_dummy_page dummy_page; 2328 bool shutdown; 2329 bool suspend; 2330 bool need_dma32; 2331 bool accel_working; 2332 bool fastfb_working; /* IGP feature*/ 2333 bool needs_reset; 2334 bool fictitious_range_registered; 2335 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2336 const struct firmware *me_fw; /* all family ME firmware */ 2337 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2338 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2339 const struct firmware *mc_fw; /* NI MC firmware */ 2340 const struct firmware *ce_fw; /* SI CE firmware */ 2341 const struct firmware *mec_fw; /* CIK MEC firmware */ 2342 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2343 const struct firmware *smc_fw; /* SMC firmware */ 2344 const struct firmware *uvd_fw; /* UVD firmware */ 2345 const struct firmware *vce_fw; /* VCE firmware */ 2346 struct r600_vram_scratch vram_scratch; 2347 int msi_enabled; /* msi enabled */ 2348 struct r600_ih ih; /* r6/700 interrupt ring */ 2349 struct radeon_rlc rlc; 2350 struct radeon_mec mec; 2351 struct taskqueue *tq; 2352 struct task hotplug_work; 2353 struct task audio_work; 2354 struct task reset_work; 2355 int num_crtc; /* number of crtcs */ 2356 struct lock dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2357 bool has_uvd; 2358 struct r600_audio audio; /* audio stuff */ 2359 struct { 2360 ACPI_HANDLE handle; 2361 ACPI_NOTIFY_HANDLER notifier_call; 2362 } acpi; 2363 /* only one userspace can use Hyperz features or CMASK at a time */ 2364 struct drm_file *hyperz_filp; 2365 struct drm_file *cmask_filp; 2366 /* i2c buses */ 2367 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2368 /* debugfs */ 2369 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 2370 unsigned debugfs_count; 2371 /* virtual memory */ 2372 struct radeon_vm_manager vm_manager; 2373 struct spinlock gpu_clock_mutex; 2374 /* memory stats */ 2375 atomic64_t vram_usage; 2376 atomic64_t gtt_usage; 2377 atomic64_t num_bytes_moved; 2378 /* ACPI interface */ 2379 struct radeon_atif atif; 2380 struct radeon_atcs atcs; 2381 /* srbm instance registers */ 2382 struct spinlock srbm_mutex; 2383 /* clock, powergating flags */ 2384 u32 cg_flags; 2385 u32 pg_flags; 2386 2387 #ifdef PM_TODO 2388 struct dev_pm_domain vga_pm_domain; 2389 #endif 2390 bool have_disp_power_ref; 2391 u32 px_quirk_flags; 2392 2393 /* tracking pinned memory */ 2394 u64 vram_pin_size; 2395 u64 gart_pin_size; 2396 }; 2397 2398 bool radeon_is_px(struct drm_device *dev); 2399 int radeon_device_init(struct radeon_device *rdev, 2400 struct drm_device *ddev, 2401 struct pci_dev *pdev, 2402 uint32_t flags); 2403 void radeon_device_fini(struct radeon_device *rdev); 2404 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2405 2406 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2407 bool always_indirect); 2408 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2409 bool always_indirect); 2410 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2411 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2412 2413 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2414 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2415 2416 /* 2417 * Cast helper 2418 */ 2419 #define to_radeon_fence(p) ((struct radeon_fence *)(p)) 2420 2421 /* 2422 * Registers read & write functions. 2423 */ 2424 #define RREG8(reg) bus_read_1((rdev->rmmio), (reg)) 2425 #define WREG8(reg, v) bus_write_1((rdev->rmmio), (reg), v) 2426 #define RREG16(reg) bus_read_2((rdev->rmmio), (reg)) 2427 #define WREG16(reg, v) bus_write_2((rdev->rmmio), (reg), v) 2428 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2429 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2430 #define DREG32(reg) DRM_INFO("REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) 2431 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2432 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2433 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2434 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2435 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2436 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2437 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2438 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2439 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2440 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2441 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2442 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2443 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2444 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2445 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2446 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2447 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2448 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2449 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2450 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2451 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2452 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2453 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2454 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2455 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2456 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2457 #define WREG32_P(reg, val, mask) \ 2458 do { \ 2459 uint32_t tmp_ = RREG32(reg); \ 2460 tmp_ &= (mask); \ 2461 tmp_ |= ((val) & ~(mask)); \ 2462 WREG32(reg, tmp_); \ 2463 } while (0) 2464 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2465 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2466 #define WREG32_PLL_P(reg, val, mask) \ 2467 do { \ 2468 uint32_t tmp_ = RREG32_PLL(reg); \ 2469 tmp_ &= (mask); \ 2470 tmp_ |= ((val) & ~(mask)); \ 2471 WREG32_PLL(reg, tmp_); \ 2472 } while (0) 2473 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2474 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2475 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2476 2477 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2478 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2479 2480 /* 2481 * Indirect registers accessor 2482 */ 2483 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 2484 { 2485 uint32_t r; 2486 2487 spin_lock(&rdev->pcie_idx_lock); 2488 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2489 r = RREG32(RADEON_PCIE_DATA); 2490 spin_unlock(&rdev->pcie_idx_lock); 2491 return r; 2492 } 2493 2494 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2495 { 2496 spin_lock(&rdev->pcie_idx_lock); 2497 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2498 WREG32(RADEON_PCIE_DATA, (v)); 2499 spin_unlock(&rdev->pcie_idx_lock); 2500 } 2501 2502 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) 2503 { 2504 u32 r; 2505 2506 spin_lock(&rdev->smc_idx_lock); 2507 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2508 r = RREG32(TN_SMC_IND_DATA_0); 2509 spin_unlock(&rdev->smc_idx_lock); 2510 return r; 2511 } 2512 2513 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2514 { 2515 spin_lock(&rdev->smc_idx_lock); 2516 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2517 WREG32(TN_SMC_IND_DATA_0, (v)); 2518 spin_unlock(&rdev->smc_idx_lock); 2519 } 2520 2521 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) 2522 { 2523 u32 r; 2524 2525 spin_lock(&rdev->rcu_idx_lock); 2526 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2527 r = RREG32(R600_RCU_DATA); 2528 spin_unlock(&rdev->rcu_idx_lock); 2529 return r; 2530 } 2531 2532 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2533 { 2534 spin_lock(&rdev->rcu_idx_lock); 2535 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2536 WREG32(R600_RCU_DATA, (v)); 2537 spin_unlock(&rdev->rcu_idx_lock); 2538 } 2539 2540 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) 2541 { 2542 u32 r; 2543 2544 spin_lock(&rdev->cg_idx_lock); 2545 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2546 r = RREG32(EVERGREEN_CG_IND_DATA); 2547 spin_unlock(&rdev->cg_idx_lock); 2548 return r; 2549 } 2550 2551 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2552 { 2553 spin_lock(&rdev->cg_idx_lock); 2554 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2555 WREG32(EVERGREEN_CG_IND_DATA, (v)); 2556 spin_unlock(&rdev->cg_idx_lock); 2557 } 2558 2559 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg) 2560 { 2561 u32 r; 2562 2563 spin_lock(&rdev->pif_idx_lock); 2564 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2565 r = RREG32(EVERGREEN_PIF_PHY0_DATA); 2566 spin_unlock(&rdev->pif_idx_lock); 2567 return r; 2568 } 2569 2570 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2571 { 2572 spin_lock(&rdev->pif_idx_lock); 2573 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2574 WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); 2575 spin_unlock(&rdev->pif_idx_lock); 2576 } 2577 2578 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg) 2579 { 2580 u32 r; 2581 2582 spin_lock(&rdev->pif_idx_lock); 2583 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2584 r = RREG32(EVERGREEN_PIF_PHY1_DATA); 2585 spin_unlock(&rdev->pif_idx_lock); 2586 return r; 2587 } 2588 2589 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2590 { 2591 spin_lock(&rdev->pif_idx_lock); 2592 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2593 WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); 2594 spin_unlock(&rdev->pif_idx_lock); 2595 } 2596 2597 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) 2598 { 2599 u32 r; 2600 2601 spin_lock(&rdev->uvd_idx_lock); 2602 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2603 r = RREG32(R600_UVD_CTX_DATA); 2604 spin_unlock(&rdev->uvd_idx_lock); 2605 return r; 2606 } 2607 2608 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2609 { 2610 spin_lock(&rdev->uvd_idx_lock); 2611 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2612 WREG32(R600_UVD_CTX_DATA, (v)); 2613 spin_unlock(&rdev->uvd_idx_lock); 2614 } 2615 2616 2617 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg) 2618 { 2619 u32 r; 2620 2621 spin_lock(&rdev->didt_idx_lock); 2622 WREG32(CIK_DIDT_IND_INDEX, (reg)); 2623 r = RREG32(CIK_DIDT_IND_DATA); 2624 spin_unlock(&rdev->didt_idx_lock); 2625 return r; 2626 } 2627 2628 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2629 { 2630 spin_lock(&rdev->didt_idx_lock); 2631 WREG32(CIK_DIDT_IND_INDEX, (reg)); 2632 WREG32(CIK_DIDT_IND_DATA, (v)); 2633 spin_unlock(&rdev->didt_idx_lock); 2634 } 2635 2636 void r100_pll_errata_after_index(struct radeon_device *rdev); 2637 2638 2639 /* 2640 * ASICs helpers. 2641 */ 2642 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2643 (rdev->pdev->device == 0x5969)) 2644 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2645 (rdev->family == CHIP_RV200) || \ 2646 (rdev->family == CHIP_RS100) || \ 2647 (rdev->family == CHIP_RS200) || \ 2648 (rdev->family == CHIP_RV250) || \ 2649 (rdev->family == CHIP_RV280) || \ 2650 (rdev->family == CHIP_RS300)) 2651 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2652 (rdev->family == CHIP_RV350) || \ 2653 (rdev->family == CHIP_R350) || \ 2654 (rdev->family == CHIP_RV380) || \ 2655 (rdev->family == CHIP_R420) || \ 2656 (rdev->family == CHIP_R423) || \ 2657 (rdev->family == CHIP_RV410) || \ 2658 (rdev->family == CHIP_RS400) || \ 2659 (rdev->family == CHIP_RS480)) 2660 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 2661 (rdev->ddev->pdev->device == 0x9443) || \ 2662 (rdev->ddev->pdev->device == 0x944B) || \ 2663 (rdev->ddev->pdev->device == 0x9506) || \ 2664 (rdev->ddev->pdev->device == 0x9509) || \ 2665 (rdev->ddev->pdev->device == 0x950F) || \ 2666 (rdev->ddev->pdev->device == 0x689C) || \ 2667 (rdev->ddev->pdev->device == 0x689D)) 2668 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2669 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2670 (rdev->family == CHIP_RS690) || \ 2671 (rdev->family == CHIP_RS740) || \ 2672 (rdev->family >= CHIP_R600)) 2673 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2674 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2675 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2676 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2677 (rdev->flags & RADEON_IS_IGP)) 2678 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2679 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2680 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2681 (rdev->flags & RADEON_IS_IGP)) 2682 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2683 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2684 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2685 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2686 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2687 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2688 (rdev->family == CHIP_MULLINS)) 2689 2690 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ 2691 (rdev->ddev->pdev->device == 0x6850) || \ 2692 (rdev->ddev->pdev->device == 0x6858) || \ 2693 (rdev->ddev->pdev->device == 0x6859) || \ 2694 (rdev->ddev->pdev->device == 0x6840) || \ 2695 (rdev->ddev->pdev->device == 0x6841) || \ 2696 (rdev->ddev->pdev->device == 0x6842) || \ 2697 (rdev->ddev->pdev->device == 0x6843)) 2698 2699 /* 2700 * BIOS helpers. 2701 */ 2702 #define RBIOS8(i) (rdev->bios[i]) 2703 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2704 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2705 2706 int radeon_combios_init(struct radeon_device *rdev); 2707 void radeon_combios_fini(struct radeon_device *rdev); 2708 int radeon_atombios_init(struct radeon_device *rdev); 2709 void radeon_atombios_fini(struct radeon_device *rdev); 2710 2711 2712 /* 2713 * RING helpers. 2714 */ 2715 #if !defined(DRM_DEBUG_CODE) || DRM_DEBUG_CODE == 0 2716 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2717 { 2718 ring->ring[ring->wptr++] = v; 2719 ring->wptr &= ring->ptr_mask; 2720 ring->count_dw--; 2721 ring->ring_free_dw--; 2722 } 2723 #else 2724 /* With debugging this is just too big to inline */ 2725 void radeon_ring_write(struct radeon_ring *ring, uint32_t v); 2726 #endif 2727 2728 /* 2729 * ASICs macro. 2730 */ 2731 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2732 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2733 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2734 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2735 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2736 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2737 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 2738 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2739 #define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f)) 2740 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2741 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2742 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) 2743 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2744 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2745 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) 2746 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2747 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2748 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2749 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2750 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2751 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2752 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm)) 2753 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2754 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2755 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2756 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2757 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2758 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2759 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2760 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2761 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2762 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2763 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2764 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2765 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) 2766 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) 2767 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) 2768 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2769 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2770 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2771 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2772 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2773 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2774 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2775 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2776 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2777 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2778 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2779 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2780 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2781 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2782 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2783 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2784 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2785 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2786 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2787 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2788 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2789 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2790 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2791 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2792 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2793 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2794 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) 2795 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) 2796 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2797 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2798 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2799 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2800 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2801 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2802 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2803 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2804 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2805 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2806 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2807 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2808 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2809 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2810 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2811 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2812 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2813 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2814 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2815 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2816 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2817 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2818 2819 /* Common functions */ 2820 /* AGP */ 2821 extern int radeon_gpu_reset(struct radeon_device *rdev); 2822 extern void radeon_pci_config_reset(struct radeon_device *rdev); 2823 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2824 extern void radeon_agp_disable(struct radeon_device *rdev); 2825 extern int radeon_modeset_init(struct radeon_device *rdev); 2826 extern void radeon_modeset_fini(struct radeon_device *rdev); 2827 extern bool radeon_card_posted(struct radeon_device *rdev); 2828 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2829 extern void radeon_update_display_priority(struct radeon_device *rdev); 2830 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2831 extern void radeon_scratch_init(struct radeon_device *rdev); 2832 extern void radeon_wb_fini(struct radeon_device *rdev); 2833 extern int radeon_wb_init(struct radeon_device *rdev); 2834 extern void radeon_wb_disable(struct radeon_device *rdev); 2835 extern void radeon_surface_init(struct radeon_device *rdev); 2836 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2837 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2838 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2839 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2840 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2841 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2842 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2843 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2844 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2845 const u32 *registers, 2846 const u32 array_size); 2847 2848 /* 2849 * vm 2850 */ 2851 int radeon_vm_manager_init(struct radeon_device *rdev); 2852 void radeon_vm_manager_fini(struct radeon_device *rdev); 2853 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2854 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2855 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev, 2856 struct radeon_vm *vm, 2857 struct list_head *head); 2858 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2859 struct radeon_vm *vm, int ring); 2860 void radeon_vm_flush(struct radeon_device *rdev, 2861 struct radeon_vm *vm, 2862 int ring); 2863 void radeon_vm_fence(struct radeon_device *rdev, 2864 struct radeon_vm *vm, 2865 struct radeon_fence *fence); 2866 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2867 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2868 struct radeon_vm *vm); 2869 int radeon_vm_clear_freed(struct radeon_device *rdev, 2870 struct radeon_vm *vm); 2871 int radeon_vm_clear_invalids(struct radeon_device *rdev, 2872 struct radeon_vm *vm); 2873 int radeon_vm_bo_update(struct radeon_device *rdev, 2874 struct radeon_bo_va *bo_va, 2875 struct ttm_mem_reg *mem); 2876 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2877 struct radeon_bo *bo); 2878 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2879 struct radeon_bo *bo); 2880 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2881 struct radeon_vm *vm, 2882 struct radeon_bo *bo); 2883 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2884 struct radeon_bo_va *bo_va, 2885 uint64_t offset, 2886 uint32_t flags); 2887 void radeon_vm_bo_rmv(struct radeon_device *rdev, 2888 struct radeon_bo_va *bo_va); 2889 2890 /* audio */ 2891 void r600_audio_update_hdmi(void *arg, int pending); 2892 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2893 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2894 void r600_audio_enable(struct radeon_device *rdev, 2895 struct r600_audio_pin *pin, 2896 bool enable); 2897 void dce6_audio_enable(struct radeon_device *rdev, 2898 struct r600_audio_pin *pin, 2899 bool enable); 2900 2901 /* 2902 * R600 vram scratch functions 2903 */ 2904 int r600_vram_scratch_init(struct radeon_device *rdev); 2905 void r600_vram_scratch_fini(struct radeon_device *rdev); 2906 2907 /* 2908 * r600 cs checking helper 2909 */ 2910 unsigned r600_mip_minify(unsigned size, unsigned level); 2911 bool r600_fmt_is_valid_color(u32 format); 2912 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2913 int r600_fmt_get_blocksize(u32 format); 2914 int r600_fmt_get_nblocksx(u32 format, u32 w); 2915 int r600_fmt_get_nblocksy(u32 format, u32 h); 2916 2917 /* 2918 * r600 functions used by radeon_encoder.c 2919 */ 2920 struct radeon_hdmi_acr { 2921 u32 clock; 2922 2923 int n_32khz; 2924 int cts_32khz; 2925 2926 int n_44_1khz; 2927 int cts_44_1khz; 2928 2929 int n_48khz; 2930 int cts_48khz; 2931 2932 }; 2933 2934 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 2935 2936 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 2937 u32 tiling_pipe_num, 2938 u32 max_rb_num, 2939 u32 total_max_rb_num, 2940 u32 enabled_rb_mask); 2941 2942 /* 2943 * evergreen functions used by radeon_encoder.c 2944 */ 2945 2946 extern int ni_init_microcode(struct radeon_device *rdev); 2947 extern int ni_mc_load_microcode(struct radeon_device *rdev); 2948 extern void ni_fini_microcode(struct radeon_device *rdev); 2949 2950 /* radeon_acpi.c */ 2951 extern int radeon_acpi_init(struct radeon_device *rdev); 2952 extern void radeon_acpi_fini(struct radeon_device *rdev); 2953 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 2954 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 2955 u8 perf_req, bool advertise); 2956 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 2957 2958 /* Prototypes added by @dumbbell. */ 2959 2960 /* atombios_encoders.c */ 2961 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 2962 struct drm_connector *drm_connector); 2963 void radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, 2964 uint32_t supported_device, u16 caps); 2965 2966 /* radeon_atombios.c */ 2967 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 2968 struct drm_display_mode *mode); 2969 2970 /* radeon_legacy_encoders.c */ 2971 void radeon_add_legacy_encoder(struct drm_device *dev, 2972 uint32_t encoder_enum, uint32_t supported_device); 2973 void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder, 2974 struct drm_connector *drm_connector); 2975 2976 /* radeon_pm.c */ 2977 void radeon_pm_acpi_event_handler(struct radeon_device *rdev); 2978 2979 /* radeon_ttm.c */ 2980 int radeon_ttm_init(struct radeon_device *rdev); 2981 void radeon_ttm_fini(struct radeon_device *rdev); 2982 2983 /* r600.c */ 2984 int r600_ih_ring_alloc(struct radeon_device *rdev); 2985 void r600_ih_ring_fini(struct radeon_device *rdev); 2986 2987 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 2988 struct radeon_cs_packet *pkt, 2989 unsigned idx); 2990 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 2991 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 2992 struct radeon_cs_packet *pkt); 2993 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 2994 struct radeon_cs_reloc **cs_reloc, 2995 int nomm); 2996 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 2997 uint32_t *vline_start_end, 2998 uint32_t *vline_status); 2999 3000 #include "radeon_object.h" 3001 3002 #endif 3003