1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * 28 * $FreeBSD: head/sys/dev/drm2/radeon/radeon.h 254885 2013-08-25 19:37:15Z dumbbell $ 29 */ 30 31 #ifndef __RADEON_H__ 32 #define __RADEON_H__ 33 34 /* TODO: Here are things that needs to be done : 35 * - surface allocator & initializer : (bit like scratch reg) should 36 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 37 * related to surface 38 * - WB : write back stuff (do it bit like scratch reg things) 39 * - Vblank : look at Jesse's rework and what we should do 40 * - r600/r700: gart & cp 41 * - cs : clean cs ioctl use bitmap & things like that. 42 * - power management stuff 43 * - Barrier in gart code 44 * - Unmappabled vram ? 45 * - TESTING, TESTING, TESTING 46 */ 47 48 /* Initialization path: 49 * We expect that acceleration initialization might fail for various 50 * reasons even thought we work hard to make it works on most 51 * configurations. In order to still have a working userspace in such 52 * situation the init path must succeed up to the memory controller 53 * initialization point. Failure before this point are considered as 54 * fatal error. Here is the init callchain : 55 * radeon_device_init perform common structure, mutex initialization 56 * asic_init setup the GPU memory layout and perform all 57 * one time initialization (failure in this 58 * function are considered fatal) 59 * asic_startup setup the GPU acceleration, in order to 60 * follow guideline the first thing this 61 * function should do is setting the GPU 62 * memory controller (only MC setup failure 63 * are considered as fatal) 64 */ 65 66 #include <sys/condvar.h> 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/linker.h> 70 #include <linux/firmware.h> 71 #include <linux/seq_file.h> 72 73 #include <contrib/dev/acpica/source/include/acpi.h> 74 #include <dev/acpica/acpivar.h> 75 76 #include <drm/ttm/ttm_bo_api.h> 77 #include <drm/ttm/ttm_bo_driver.h> 78 #include <drm/ttm/ttm_placement.h> 79 #include <drm/ttm/ttm_module.h> 80 #include <drm/ttm/ttm_execbuf_util.h> 81 82 #define CONFIG_ACPI 1 83 84 #include "radeon_family.h" 85 #include "radeon_mode.h" 86 #include "radeon_reg.h" 87 88 /* 89 * Modules parameters. 90 */ 91 extern int radeon_no_wb; 92 extern int radeon_modeset; 93 extern int radeon_dynclks; 94 extern int radeon_r4xx_atom; 95 extern int radeon_agpmode; 96 extern int radeon_vram_limit; 97 extern int radeon_gart_size; 98 extern int radeon_benchmarking; 99 extern int radeon_testing; 100 extern int radeon_connector_table; 101 extern int radeon_tv; 102 extern int radeon_audio; 103 extern int radeon_disp_priority; 104 extern int radeon_hw_i2c; 105 extern int radeon_pcie_gen2; 106 extern int radeon_msi; 107 extern int radeon_lockup_timeout; 108 extern int radeon_fastfb; 109 extern int radeon_dpm; 110 extern int radeon_aspm; 111 112 /* 113 * Copy from radeon_drv.h so we don't have to include both and have conflicting 114 * symbol; 115 */ 116 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 117 #define RADEON_FENCE_JIFFIES_TIMEOUT (DRM_HZ / 2) 118 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 119 #define RADEON_IB_POOL_SIZE 16 120 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 121 #define RADEONFB_CONN_LIMIT 4 122 #define RADEON_BIOS_NUM_SCRATCH 8 123 124 /* max number of rings */ 125 #define RADEON_NUM_RINGS 6 126 127 /* fence seq are set to this number when signaled */ 128 #define RADEON_FENCE_SIGNALED_SEQ 0LL 129 130 /* internal ring indices */ 131 /* r1xx+ has gfx CP ring */ 132 #define RADEON_RING_TYPE_GFX_INDEX 0 133 134 /* cayman has 2 compute CP rings */ 135 #define CAYMAN_RING_TYPE_CP1_INDEX 1 136 #define CAYMAN_RING_TYPE_CP2_INDEX 2 137 138 /* R600+ has an async dma ring */ 139 #define R600_RING_TYPE_DMA_INDEX 3 140 /* cayman add a second async dma ring */ 141 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 142 143 /* R600+ */ 144 #define R600_RING_TYPE_UVD_INDEX 5 145 146 /* hardcode those limit for now */ 147 #define RADEON_VA_IB_OFFSET (1 << 20) 148 #define RADEON_VA_RESERVED_SIZE (8 << 20) 149 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 150 151 /* reset flags */ 152 #define RADEON_RESET_GFX (1 << 0) 153 #define RADEON_RESET_COMPUTE (1 << 1) 154 #define RADEON_RESET_DMA (1 << 2) 155 #define RADEON_RESET_CP (1 << 3) 156 #define RADEON_RESET_GRBM (1 << 4) 157 #define RADEON_RESET_DMA1 (1 << 5) 158 #define RADEON_RESET_RLC (1 << 6) 159 #define RADEON_RESET_SEM (1 << 7) 160 #define RADEON_RESET_IH (1 << 8) 161 #define RADEON_RESET_VMC (1 << 9) 162 #define RADEON_RESET_MC (1 << 10) 163 #define RADEON_RESET_DISPLAY (1 << 11) 164 165 /* max cursor sizes (in pixels) */ 166 #define CURSOR_WIDTH 64 167 #define CURSOR_HEIGHT 64 168 169 #define CIK_CURSOR_WIDTH 128 170 #define CIK_CURSOR_HEIGHT 128 171 172 /* 173 * Errata workarounds. 174 */ 175 enum radeon_pll_errata { 176 CHIP_ERRATA_R300_CG = 0x00000001, 177 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 178 CHIP_ERRATA_PLL_DELAY = 0x00000004 179 }; 180 181 182 struct radeon_device; 183 184 185 /* 186 * BIOS. 187 */ 188 bool radeon_get_bios(struct radeon_device *rdev); 189 190 /* 191 * Dummy page 192 */ 193 struct radeon_dummy_page { 194 drm_dma_handle_t *dmah; 195 dma_addr_t addr; 196 }; 197 int radeon_dummy_page_init(struct radeon_device *rdev); 198 void radeon_dummy_page_fini(struct radeon_device *rdev); 199 200 201 /* 202 * Clocks 203 */ 204 struct radeon_clock { 205 struct radeon_pll p1pll; 206 struct radeon_pll p2pll; 207 struct radeon_pll dcpll; 208 struct radeon_pll spll; 209 struct radeon_pll mpll; 210 /* 10 Khz units */ 211 uint32_t default_mclk; 212 uint32_t default_sclk; 213 uint32_t default_dispclk; 214 uint32_t current_dispclk; 215 uint32_t dp_extclk; 216 uint32_t max_pixel_clock; 217 }; 218 219 /* 220 * Power management 221 */ 222 int radeon_pm_init(struct radeon_device *rdev); 223 void radeon_pm_fini(struct radeon_device *rdev); 224 void radeon_pm_compute_clocks(struct radeon_device *rdev); 225 void radeon_pm_suspend(struct radeon_device *rdev); 226 void radeon_pm_resume(struct radeon_device *rdev); 227 void radeon_combios_get_power_modes(struct radeon_device *rdev); 228 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 229 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 230 u8 clock_type, 231 u32 clock, 232 bool strobe_mode, 233 struct atom_clock_dividers *dividers); 234 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 235 u32 clock, 236 bool strobe_mode, 237 struct atom_mpll_param *mpll_param); 238 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 239 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 240 u16 voltage_level, u8 voltage_type, 241 u32 *gpio_value, u32 *gpio_mask); 242 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 243 u32 eng_clock, u32 mem_clock); 244 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 245 u8 voltage_type, u16 *voltage_step); 246 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 247 u16 voltage_id, u16 *voltage); 248 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 249 u16 *voltage, 250 u16 leakage_idx); 251 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 252 u8 voltage_type, 253 u16 nominal_voltage, 254 u16 *true_voltage); 255 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 256 u8 voltage_type, u16 *min_voltage); 257 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 258 u8 voltage_type, u16 *max_voltage); 259 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 260 u8 voltage_type, u8 voltage_mode, 261 struct atom_voltage_table *voltage_table); 262 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 263 u8 voltage_type, u8 voltage_mode); 264 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 265 u32 mem_clock); 266 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 267 u32 mem_clock); 268 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 269 u8 module_index, 270 struct atom_mc_reg_table *reg_table); 271 int radeon_atom_get_memory_info(struct radeon_device *rdev, 272 u8 module_index, struct atom_memory_info *mem_info); 273 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 274 bool gddr5, u8 module_index, 275 struct atom_memory_clock_range_table *mclk_range_table); 276 void rs690_pm_info(struct radeon_device *rdev); 277 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 278 unsigned *bankh, unsigned *mtaspect, 279 unsigned *tile_split); 280 281 /* 282 * Fences. 283 */ 284 struct radeon_fence_driver { 285 uint32_t scratch_reg; 286 uint64_t gpu_addr; 287 volatile uint32_t *cpu_addr; 288 /* sync_seq is protected by ring emission lock */ 289 uint64_t sync_seq[RADEON_NUM_RINGS]; 290 atomic64_t last_seq; 291 unsigned long last_activity; 292 bool initialized; 293 }; 294 295 struct radeon_fence { 296 struct radeon_device *rdev; 297 unsigned int kref; 298 /* protected by radeon_fence.lock */ 299 uint64_t seq; 300 /* RB, DMA, etc. */ 301 unsigned ring; 302 }; 303 304 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 305 int radeon_fence_driver_init(struct radeon_device *rdev); 306 void radeon_fence_driver_fini(struct radeon_device *rdev); 307 void radeon_fence_driver_force_completion(struct radeon_device *rdev); 308 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 309 void radeon_fence_process(struct radeon_device *rdev, int ring); 310 bool radeon_fence_signaled(struct radeon_fence *fence); 311 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 312 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring); 313 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring); 314 int radeon_fence_wait_any(struct radeon_device *rdev, 315 struct radeon_fence **fences, 316 bool intr); 317 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 318 void radeon_fence_unref(struct radeon_fence **fence); 319 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 320 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 321 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 322 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 323 struct radeon_fence *b) 324 { 325 if (!a) { 326 return b; 327 } 328 329 if (!b) { 330 return a; 331 } 332 333 BUG_ON(a->ring != b->ring); 334 335 if (a->seq > b->seq) { 336 return a; 337 } else { 338 return b; 339 } 340 } 341 342 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 343 struct radeon_fence *b) 344 { 345 if (!a) { 346 return false; 347 } 348 349 if (!b) { 350 return true; 351 } 352 353 BUG_ON(a->ring != b->ring); 354 355 return a->seq < b->seq; 356 } 357 358 /* 359 * Tiling registers 360 */ 361 struct radeon_surface_reg { 362 struct radeon_bo *bo; 363 }; 364 365 #define RADEON_GEM_MAX_SURFACES 8 366 367 /* 368 * TTM. 369 */ 370 struct radeon_mman { 371 struct ttm_bo_global_ref bo_global_ref; 372 struct drm_global_reference mem_global_ref; 373 struct ttm_bo_device bdev; 374 bool mem_global_referenced; 375 bool initialized; 376 }; 377 378 /* bo virtual address in a specific vm */ 379 struct radeon_bo_va { 380 /* protected by bo being reserved */ 381 struct list_head bo_list; 382 uint64_t soffset; 383 uint64_t eoffset; 384 uint32_t flags; 385 bool valid; 386 unsigned ref_count; 387 388 /* protected by vm mutex */ 389 struct list_head vm_list; 390 391 /* constant after initialization */ 392 struct radeon_vm *vm; 393 struct radeon_bo *bo; 394 }; 395 396 struct radeon_bo { 397 /* Protected by gem.mutex */ 398 struct list_head list; 399 /* Protected by tbo.reserved */ 400 u32 placements[3]; 401 struct ttm_placement placement; 402 struct ttm_buffer_object tbo; 403 struct ttm_bo_kmap_obj kmap; 404 unsigned pin_count; 405 void *kptr; 406 u32 tiling_flags; 407 u32 pitch; 408 int surface_reg; 409 /* list of all virtual address to which this bo 410 * is associated to 411 */ 412 struct list_head va; 413 /* Constant after initialization */ 414 struct radeon_device *rdev; 415 struct drm_gem_object gem_base; 416 417 struct ttm_bo_kmap_obj dma_buf_vmap; 418 pid_t pid; 419 }; 420 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 421 422 struct radeon_bo_list { 423 struct ttm_validate_buffer tv; 424 struct radeon_bo *bo; 425 uint64_t gpu_offset; 426 bool written; 427 unsigned domain; 428 unsigned alt_domain; 429 u32 tiling_flags; 430 }; 431 432 int radeon_gem_debugfs_init(struct radeon_device *rdev); 433 434 /* sub-allocation manager, it has to be protected by another lock. 435 * By conception this is an helper for other part of the driver 436 * like the indirect buffer or semaphore, which both have their 437 * locking. 438 * 439 * Principe is simple, we keep a list of sub allocation in offset 440 * order (first entry has offset == 0, last entry has the highest 441 * offset). 442 * 443 * When allocating new object we first check if there is room at 444 * the end total_size - (last_object_offset + last_object_size) >= 445 * alloc_size. If so we allocate new object there. 446 * 447 * When there is not enough room at the end, we start waiting for 448 * each sub object until we reach object_offset+object_size >= 449 * alloc_size, this object then become the sub object we return. 450 * 451 * Alignment can't be bigger than page size. 452 * 453 * Hole are not considered for allocation to keep things simple. 454 * Assumption is that there won't be hole (all object on same 455 * alignment). 456 */ 457 struct radeon_sa_manager { 458 struct cv wq; 459 struct lock wq_lock; 460 struct radeon_bo *bo; 461 struct list_head *hole; 462 struct list_head flist[RADEON_NUM_RINGS]; 463 struct list_head olist; 464 unsigned size; 465 uint64_t gpu_addr; 466 void *cpu_ptr; 467 uint32_t domain; 468 uint32_t align; 469 }; 470 471 struct radeon_sa_bo; 472 473 /* sub-allocation buffer */ 474 struct radeon_sa_bo { 475 struct list_head olist; 476 struct list_head flist; 477 struct radeon_sa_manager *manager; 478 unsigned soffset; 479 unsigned eoffset; 480 struct radeon_fence *fence; 481 }; 482 483 /* 484 * GEM objects. 485 */ 486 struct radeon_gem { 487 struct spinlock mutex; 488 struct list_head objects; 489 }; 490 491 int radeon_gem_init(struct radeon_device *rdev); 492 void radeon_gem_fini(struct radeon_device *rdev); 493 int radeon_gem_object_create(struct radeon_device *rdev, int size, 494 int alignment, int initial_domain, 495 bool discardable, bool kernel, 496 struct drm_gem_object **obj); 497 498 int radeon_mode_dumb_create(struct drm_file *file_priv, 499 struct drm_device *dev, 500 struct drm_mode_create_dumb *args); 501 int radeon_mode_dumb_mmap(struct drm_file *filp, 502 struct drm_device *dev, 503 uint32_t handle, uint64_t *offset_p); 504 int radeon_mode_dumb_destroy(struct drm_file *file_priv, 505 struct drm_device *dev, 506 uint32_t handle); 507 508 /* 509 * Semaphores. 510 */ 511 /* everything here is constant */ 512 struct radeon_semaphore { 513 struct radeon_sa_bo *sa_bo; 514 signed waiters; 515 uint64_t gpu_addr; 516 }; 517 518 int radeon_semaphore_create(struct radeon_device *rdev, 519 struct radeon_semaphore **semaphore); 520 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 521 struct radeon_semaphore *semaphore); 522 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 523 struct radeon_semaphore *semaphore); 524 int radeon_semaphore_sync_rings(struct radeon_device *rdev, 525 struct radeon_semaphore *semaphore, 526 int signaler, int waiter); 527 void radeon_semaphore_free(struct radeon_device *rdev, 528 struct radeon_semaphore **semaphore, 529 struct radeon_fence *fence); 530 531 /* 532 * GART structures, functions & helpers 533 */ 534 struct radeon_mc; 535 536 #define RADEON_GPU_PAGE_SIZE 4096 537 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 538 #define RADEON_GPU_PAGE_SHIFT 12 539 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 540 541 struct radeon_gart { 542 drm_dma_handle_t *dmah; 543 dma_addr_t table_addr; 544 struct radeon_bo *robj; 545 void *ptr; 546 unsigned num_gpu_pages; 547 unsigned num_cpu_pages; 548 unsigned table_size; 549 vm_page_t *pages; 550 dma_addr_t *pages_addr; 551 bool ready; 552 }; 553 554 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 555 void radeon_gart_table_ram_free(struct radeon_device *rdev); 556 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 557 void radeon_gart_table_vram_free(struct radeon_device *rdev); 558 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 559 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 560 int radeon_gart_init(struct radeon_device *rdev); 561 void radeon_gart_fini(struct radeon_device *rdev); 562 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 563 int pages); 564 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 565 int pages, vm_page_t *pagelist, 566 dma_addr_t *dma_addr); 567 void radeon_gart_restore(struct radeon_device *rdev); 568 569 570 /* 571 * GPU MC structures, functions & helpers 572 */ 573 struct radeon_mc { 574 resource_size_t aper_size; 575 resource_size_t aper_base; 576 resource_size_t agp_base; 577 /* for some chips with <= 32MB we need to lie 578 * about vram size near mc fb location */ 579 u64 mc_vram_size; 580 u64 visible_vram_size; 581 u64 gtt_size; 582 u64 gtt_start; 583 u64 gtt_end; 584 u64 vram_start; 585 u64 vram_end; 586 unsigned vram_width; 587 u64 real_vram_size; 588 int vram_mtrr; 589 bool vram_is_ddr; 590 bool igp_sideport_enabled; 591 u64 gtt_base_align; 592 u64 mc_mask; 593 }; 594 595 bool radeon_combios_sideport_present(struct radeon_device *rdev); 596 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 597 598 /* 599 * GPU scratch registers structures, functions & helpers 600 */ 601 struct radeon_scratch { 602 unsigned num_reg; 603 uint32_t reg_base; 604 bool free[32]; 605 uint32_t reg[32]; 606 }; 607 608 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 609 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 610 611 /* 612 * GPU doorbell structures, functions & helpers 613 */ 614 struct radeon_doorbell { 615 u32 num_pages; 616 bool free[1024]; 617 /* doorbell mmio */ 618 resource_size_t base; 619 resource_size_t size; 620 void __iomem *ptr; 621 }; 622 623 int radeon_doorbell_init(struct radeon_device *rdev); 624 void radeon_doorbell_fini(struct radeon_device *rdev); 625 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 626 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 627 628 /* 629 * IRQS. 630 */ 631 632 struct radeon_unpin_work { 633 struct task work; 634 struct radeon_device *rdev; 635 int crtc_id; 636 struct radeon_fence *fence; 637 struct drm_pending_vblank_event *event; 638 struct radeon_bo *old_rbo; 639 u64 new_crtc_base; 640 }; 641 642 struct r500_irq_stat_regs { 643 u32 disp_int; 644 u32 hdmi0_status; 645 }; 646 647 struct r600_irq_stat_regs { 648 u32 disp_int; 649 u32 disp_int_cont; 650 u32 disp_int_cont2; 651 u32 d1grph_int; 652 u32 d2grph_int; 653 u32 hdmi0_status; 654 u32 hdmi1_status; 655 }; 656 657 struct evergreen_irq_stat_regs { 658 u32 disp_int; 659 u32 disp_int_cont; 660 u32 disp_int_cont2; 661 u32 disp_int_cont3; 662 u32 disp_int_cont4; 663 u32 disp_int_cont5; 664 u32 d1grph_int; 665 u32 d2grph_int; 666 u32 d3grph_int; 667 u32 d4grph_int; 668 u32 d5grph_int; 669 u32 d6grph_int; 670 u32 afmt_status1; 671 u32 afmt_status2; 672 u32 afmt_status3; 673 u32 afmt_status4; 674 u32 afmt_status5; 675 u32 afmt_status6; 676 }; 677 678 struct cik_irq_stat_regs { 679 u32 disp_int; 680 u32 disp_int_cont; 681 u32 disp_int_cont2; 682 u32 disp_int_cont3; 683 u32 disp_int_cont4; 684 u32 disp_int_cont5; 685 u32 disp_int_cont6; 686 }; 687 688 union radeon_irq_stat_regs { 689 struct r500_irq_stat_regs r500; 690 struct r600_irq_stat_regs r600; 691 struct evergreen_irq_stat_regs evergreen; 692 struct cik_irq_stat_regs cik; 693 }; 694 695 #define RADEON_MAX_HPD_PINS 6 696 #define RADEON_MAX_CRTCS 6 697 #define RADEON_MAX_AFMT_BLOCKS 6 698 699 struct radeon_irq { 700 bool installed; 701 struct lock lock; 702 atomic_t ring_int[RADEON_NUM_RINGS]; 703 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 704 atomic_t pflip[RADEON_MAX_CRTCS]; 705 wait_queue_head_t vblank_queue; 706 bool hpd[RADEON_MAX_HPD_PINS]; 707 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 708 union radeon_irq_stat_regs stat_regs; 709 bool dpm_thermal; 710 }; 711 712 int radeon_irq_kms_init(struct radeon_device *rdev); 713 void radeon_irq_kms_fini(struct radeon_device *rdev); 714 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 715 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 716 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 717 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 718 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 719 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 720 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 721 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 722 723 /* 724 * CP & rings. 725 */ 726 727 struct radeon_ib { 728 struct radeon_sa_bo *sa_bo; 729 uint32_t length_dw; 730 uint64_t gpu_addr; 731 uint32_t *ptr; 732 int ring; 733 struct radeon_fence *fence; 734 struct radeon_vm *vm; 735 bool is_const_ib; 736 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 737 struct radeon_semaphore *semaphore; 738 }; 739 740 struct radeon_ring { 741 struct radeon_bo *ring_obj; 742 volatile uint32_t *ring; 743 unsigned rptr; 744 unsigned rptr_offs; 745 unsigned rptr_reg; 746 unsigned rptr_save_reg; 747 u64 next_rptr_gpu_addr; 748 volatile u32 *next_rptr_cpu_addr; 749 unsigned wptr; 750 unsigned wptr_old; 751 unsigned wptr_reg; 752 unsigned ring_size; 753 unsigned ring_free_dw; 754 int count_dw; 755 unsigned long last_activity; 756 unsigned last_rptr; 757 uint64_t gpu_addr; 758 uint32_t align_mask; 759 uint32_t ptr_mask; 760 bool ready; 761 u32 ptr_reg_shift; 762 u32 ptr_reg_mask; 763 u32 nop; 764 u32 idx; 765 u64 last_semaphore_signal_addr; 766 u64 last_semaphore_wait_addr; 767 /* for CIK queues */ 768 u32 me; 769 u32 pipe; 770 u32 queue; 771 struct radeon_bo *mqd_obj; 772 u32 doorbell_page_num; 773 u32 doorbell_offset; 774 unsigned wptr_offs; 775 }; 776 777 struct radeon_mec { 778 struct radeon_bo *hpd_eop_obj; 779 u64 hpd_eop_gpu_addr; 780 u32 num_pipe; 781 u32 num_mec; 782 u32 num_queue; 783 }; 784 785 /* 786 * VM 787 */ 788 789 /* maximum number of VMIDs */ 790 #define RADEON_NUM_VM 16 791 792 /* defines number of bits in page table versus page directory, 793 * a page is 4KB so we have 12 bits offset, 9 bits in the page 794 * table and the remaining 19 bits are in the page directory */ 795 #define RADEON_VM_BLOCK_SIZE 9 796 797 /* number of entries in page table */ 798 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE) 799 800 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 801 #define RADEON_VM_PTB_ALIGN_SIZE 32768 802 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 803 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 804 805 struct radeon_vm { 806 struct list_head list; 807 struct list_head va; 808 unsigned id; 809 810 /* contains the page directory */ 811 struct radeon_sa_bo *page_directory; 812 uint64_t pd_gpu_addr; 813 814 /* array of page tables, one for each page directory entry */ 815 struct radeon_sa_bo **page_tables; 816 817 struct lock mutex; 818 /* last fence for cs using this vm */ 819 struct radeon_fence *fence; 820 /* last flush or NULL if we still need to flush */ 821 struct radeon_fence *last_flush; 822 }; 823 824 struct radeon_vm_manager { 825 struct lock lock; 826 struct list_head lru_vm; 827 struct radeon_fence *active[RADEON_NUM_VM]; 828 struct radeon_sa_manager sa_manager; 829 uint32_t max_pfn; 830 /* number of VMIDs */ 831 unsigned nvm; 832 /* vram base address for page table entry */ 833 u64 vram_base_offset; 834 /* is vm enabled? */ 835 bool enabled; 836 }; 837 838 /* 839 * file private structure 840 */ 841 struct radeon_fpriv { 842 struct radeon_vm vm; 843 }; 844 845 /* 846 * R6xx+ IH ring 847 */ 848 struct r600_ih { 849 struct radeon_bo *ring_obj; 850 volatile uint32_t *ring; 851 unsigned rptr; 852 unsigned ring_size; 853 uint64_t gpu_addr; 854 uint32_t ptr_mask; 855 atomic_t lock; 856 bool enabled; 857 }; 858 859 struct r600_blit_cp_primitives { 860 void (*set_render_target)(struct radeon_device *rdev, int format, 861 int w, int h, u64 gpu_addr); 862 void (*cp_set_surface_sync)(struct radeon_device *rdev, 863 u32 sync_type, u32 size, 864 u64 mc_addr); 865 void (*set_shaders)(struct radeon_device *rdev); 866 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr); 867 void (*set_tex_resource)(struct radeon_device *rdev, 868 int format, int w, int h, int pitch, 869 u64 gpu_addr, u32 size); 870 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1, 871 int x2, int y2); 872 void (*draw_auto)(struct radeon_device *rdev); 873 void (*set_default_state)(struct radeon_device *rdev); 874 }; 875 876 struct r600_blit { 877 struct radeon_bo *shader_obj; 878 struct r600_blit_cp_primitives primitives; 879 int max_dim; 880 int ring_size_common; 881 int ring_size_per_loop; 882 u64 shader_gpu_addr; 883 u32 vs_offset, ps_offset; 884 u32 state_offset; 885 u32 state_len; 886 }; 887 888 /* 889 * RLC stuff 890 */ 891 #include "clearstate_defs.h" 892 893 struct radeon_rlc { 894 /* for power gating */ 895 struct radeon_bo *save_restore_obj; 896 uint64_t save_restore_gpu_addr; 897 volatile uint32_t *sr_ptr; 898 u32 *reg_list; 899 u32 reg_list_size; 900 /* for clear state */ 901 struct radeon_bo *clear_state_obj; 902 uint64_t clear_state_gpu_addr; 903 volatile uint32_t *cs_ptr; 904 struct cs_section_def *cs_data; 905 }; 906 907 int radeon_ib_get(struct radeon_device *rdev, int ring, 908 struct radeon_ib *ib, struct radeon_vm *vm, 909 unsigned size); 910 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 911 void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence); 912 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 913 struct radeon_ib *const_ib); 914 int radeon_ib_pool_init(struct radeon_device *rdev); 915 void radeon_ib_pool_fini(struct radeon_device *rdev); 916 int radeon_ib_ring_tests(struct radeon_device *rdev); 917 /* Ring access between begin & end cannot sleep */ 918 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 919 struct radeon_ring *ring); 920 u32 radeon_ring_generic_get_rptr(struct radeon_device *rdev, 921 struct radeon_ring *ring); 922 u32 radeon_ring_generic_get_wptr(struct radeon_device *rdev, 923 struct radeon_ring *ring); 924 void radeon_ring_generic_set_wptr(struct radeon_device *rdev, 925 struct radeon_ring *ring); 926 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 927 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 928 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 929 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); 930 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); 931 void radeon_ring_undo(struct radeon_ring *ring); 932 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 933 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 934 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring); 935 void radeon_ring_lockup_update(struct radeon_ring *ring); 936 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 937 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 938 uint32_t **data); 939 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 940 unsigned size, uint32_t *data); 941 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 942 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, 943 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop); 944 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 945 946 947 /* r600 async dma */ 948 void r600_dma_stop(struct radeon_device *rdev); 949 int r600_dma_resume(struct radeon_device *rdev); 950 void r600_dma_fini(struct radeon_device *rdev); 951 952 void cayman_dma_stop(struct radeon_device *rdev); 953 int cayman_dma_resume(struct radeon_device *rdev); 954 void cayman_dma_fini(struct radeon_device *rdev); 955 956 /* 957 * CS. 958 */ 959 struct radeon_cs_reloc { 960 struct drm_gem_object *gobj; 961 struct radeon_bo *robj; 962 struct radeon_bo_list lobj; 963 uint32_t handle; 964 uint32_t flags; 965 }; 966 967 struct radeon_cs_chunk { 968 uint32_t chunk_id; 969 uint32_t length_dw; 970 int kpage_idx[2]; 971 uint32_t *kpage[2]; 972 uint32_t *kdata; 973 void __user *user_ptr; 974 int last_copied_page; 975 int last_page_index; 976 }; 977 978 struct radeon_cs_parser { 979 device_t dev; 980 struct radeon_device *rdev; 981 struct drm_file *filp; 982 /* chunks */ 983 unsigned nchunks; 984 struct radeon_cs_chunk *chunks; 985 uint64_t *chunks_array; 986 /* IB */ 987 unsigned idx; 988 /* relocations */ 989 unsigned nrelocs; 990 struct radeon_cs_reloc *relocs; 991 struct radeon_cs_reloc **relocs_ptr; 992 struct list_head validated; 993 unsigned dma_reloc_idx; 994 /* indices of various chunks */ 995 int chunk_ib_idx; 996 int chunk_relocs_idx; 997 int chunk_flags_idx; 998 int chunk_const_ib_idx; 999 struct radeon_ib ib; 1000 struct radeon_ib const_ib; 1001 void *track; 1002 unsigned family; 1003 int parser_error; 1004 u32 cs_flags; 1005 u32 ring; 1006 s32 priority; 1007 }; 1008 1009 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); 1010 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx); 1011 1012 struct radeon_cs_packet { 1013 unsigned idx; 1014 unsigned type; 1015 unsigned reg; 1016 unsigned opcode; 1017 int count; 1018 unsigned one_reg_wr; 1019 }; 1020 1021 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1022 struct radeon_cs_packet *pkt, 1023 unsigned idx, unsigned reg); 1024 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 1025 struct radeon_cs_packet *pkt); 1026 1027 1028 /* 1029 * AGP 1030 */ 1031 int radeon_agp_init(struct radeon_device *rdev); 1032 void radeon_agp_resume(struct radeon_device *rdev); 1033 void radeon_agp_suspend(struct radeon_device *rdev); 1034 void radeon_agp_fini(struct radeon_device *rdev); 1035 1036 1037 /* 1038 * Writeback 1039 */ 1040 struct radeon_wb { 1041 struct radeon_bo *wb_obj; 1042 volatile uint32_t *wb; 1043 uint64_t gpu_addr; 1044 bool enabled; 1045 bool use_event; 1046 }; 1047 1048 #define RADEON_WB_SCRATCH_OFFSET 0 1049 #define RADEON_WB_RING0_NEXT_RPTR 256 1050 #define RADEON_WB_CP_RPTR_OFFSET 1024 1051 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1052 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1053 #define R600_WB_DMA_RPTR_OFFSET 1792 1054 #define R600_WB_IH_WPTR_OFFSET 2048 1055 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1056 #define R600_WB_UVD_RPTR_OFFSET 2560 1057 #define R600_WB_EVENT_OFFSET 3072 1058 #define CIK_WB_CP1_WPTR_OFFSET 3328 1059 #define CIK_WB_CP2_WPTR_OFFSET 3584 1060 1061 /** 1062 * struct radeon_pm - power management datas 1063 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1064 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1065 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1066 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1067 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1068 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1069 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1070 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1071 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1072 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1073 * @needed_bandwidth: current bandwidth needs 1074 * 1075 * It keeps track of various data needed to take powermanagement decision. 1076 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1077 * Equation between gpu/memory clock and available bandwidth is hw dependent 1078 * (type of memory, bus size, efficiency, ...) 1079 */ 1080 1081 enum radeon_pm_method { 1082 PM_METHOD_PROFILE, 1083 PM_METHOD_DYNPM, 1084 PM_METHOD_DPM, 1085 }; 1086 1087 enum radeon_dynpm_state { 1088 DYNPM_STATE_DISABLED, 1089 DYNPM_STATE_MINIMUM, 1090 DYNPM_STATE_PAUSED, 1091 DYNPM_STATE_ACTIVE, 1092 DYNPM_STATE_SUSPENDED, 1093 }; 1094 enum radeon_dynpm_action { 1095 DYNPM_ACTION_NONE, 1096 DYNPM_ACTION_MINIMUM, 1097 DYNPM_ACTION_DOWNCLOCK, 1098 DYNPM_ACTION_UPCLOCK, 1099 DYNPM_ACTION_DEFAULT 1100 }; 1101 1102 enum radeon_voltage_type { 1103 VOLTAGE_NONE = 0, 1104 VOLTAGE_GPIO, 1105 VOLTAGE_VDDC, 1106 VOLTAGE_SW 1107 }; 1108 1109 enum radeon_pm_state_type { 1110 /* not used for dpm */ 1111 POWER_STATE_TYPE_DEFAULT, 1112 POWER_STATE_TYPE_POWERSAVE, 1113 /* user selectable states */ 1114 POWER_STATE_TYPE_BATTERY, 1115 POWER_STATE_TYPE_BALANCED, 1116 POWER_STATE_TYPE_PERFORMANCE, 1117 /* internal states */ 1118 POWER_STATE_TYPE_INTERNAL_UVD, 1119 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1120 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1121 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1122 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1123 POWER_STATE_TYPE_INTERNAL_BOOT, 1124 POWER_STATE_TYPE_INTERNAL_THERMAL, 1125 POWER_STATE_TYPE_INTERNAL_ACPI, 1126 POWER_STATE_TYPE_INTERNAL_ULV, 1127 POWER_STATE_TYPE_INTERNAL_3DPERF, 1128 }; 1129 1130 enum radeon_pm_profile_type { 1131 PM_PROFILE_DEFAULT, 1132 PM_PROFILE_AUTO, 1133 PM_PROFILE_LOW, 1134 PM_PROFILE_MID, 1135 PM_PROFILE_HIGH, 1136 }; 1137 1138 #define PM_PROFILE_DEFAULT_IDX 0 1139 #define PM_PROFILE_LOW_SH_IDX 1 1140 #define PM_PROFILE_MID_SH_IDX 2 1141 #define PM_PROFILE_HIGH_SH_IDX 3 1142 #define PM_PROFILE_LOW_MH_IDX 4 1143 #define PM_PROFILE_MID_MH_IDX 5 1144 #define PM_PROFILE_HIGH_MH_IDX 6 1145 #define PM_PROFILE_MAX 7 1146 1147 struct radeon_pm_profile { 1148 int dpms_off_ps_idx; 1149 int dpms_on_ps_idx; 1150 int dpms_off_cm_idx; 1151 int dpms_on_cm_idx; 1152 }; 1153 1154 enum radeon_int_thermal_type { 1155 THERMAL_TYPE_NONE, 1156 THERMAL_TYPE_EXTERNAL, 1157 THERMAL_TYPE_EXTERNAL_GPIO, 1158 THERMAL_TYPE_RV6XX, 1159 THERMAL_TYPE_RV770, 1160 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1161 THERMAL_TYPE_EVERGREEN, 1162 THERMAL_TYPE_SUMO, 1163 THERMAL_TYPE_NI, 1164 THERMAL_TYPE_SI, 1165 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1166 THERMAL_TYPE_CI, 1167 }; 1168 1169 struct radeon_voltage { 1170 enum radeon_voltage_type type; 1171 /* gpio voltage */ 1172 struct radeon_gpio_rec gpio; 1173 u32 delay; /* delay in usec from voltage drop to sclk change */ 1174 bool active_high; /* voltage drop is active when bit is high */ 1175 /* VDDC voltage */ 1176 u8 vddc_id; /* index into vddc voltage table */ 1177 u8 vddci_id; /* index into vddci voltage table */ 1178 bool vddci_enabled; 1179 /* r6xx+ sw */ 1180 u16 voltage; 1181 /* evergreen+ vddci */ 1182 u16 vddci; 1183 }; 1184 1185 /* clock mode flags */ 1186 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1187 1188 struct radeon_pm_clock_info { 1189 /* memory clock */ 1190 u32 mclk; 1191 /* engine clock */ 1192 u32 sclk; 1193 /* voltage info */ 1194 struct radeon_voltage voltage; 1195 /* standardized clock flags */ 1196 u32 flags; 1197 }; 1198 1199 /* state flags */ 1200 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1201 1202 struct radeon_power_state { 1203 enum radeon_pm_state_type type; 1204 struct radeon_pm_clock_info *clock_info; 1205 /* number of valid clock modes in this power state */ 1206 int num_clock_modes; 1207 struct radeon_pm_clock_info *default_clock_mode; 1208 /* standardized state flags */ 1209 u32 flags; 1210 u32 misc; /* vbios specific flags */ 1211 u32 misc2; /* vbios specific flags */ 1212 int pcie_lanes; /* pcie lanes */ 1213 }; 1214 1215 /* 1216 * Some modes are overclocked by very low value, accept them 1217 */ 1218 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1219 1220 enum radeon_dpm_auto_throttle_src { 1221 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1222 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1223 }; 1224 1225 enum radeon_dpm_event_src { 1226 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1227 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1228 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1229 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1230 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1231 }; 1232 1233 struct radeon_ps { 1234 u32 caps; /* vbios flags */ 1235 u32 class; /* vbios flags */ 1236 u32 class2; /* vbios flags */ 1237 /* UVD clocks */ 1238 u32 vclk; 1239 u32 dclk; 1240 /* asic priv */ 1241 void *ps_priv; 1242 }; 1243 1244 struct radeon_dpm_thermal { 1245 /* thermal interrupt work */ 1246 struct task work; 1247 /* low temperature threshold */ 1248 int min_temp; 1249 /* high temperature threshold */ 1250 int max_temp; 1251 /* was interrupt low to high or high to low */ 1252 bool high_to_low; 1253 }; 1254 1255 enum radeon_clk_action 1256 { 1257 RADEON_SCLK_UP = 1, 1258 RADEON_SCLK_DOWN 1259 }; 1260 1261 struct radeon_blacklist_clocks 1262 { 1263 u32 sclk; 1264 u32 mclk; 1265 enum radeon_clk_action action; 1266 }; 1267 1268 struct radeon_clock_and_voltage_limits { 1269 u32 sclk; 1270 u32 mclk; 1271 u32 vddc; 1272 u32 vddci; 1273 }; 1274 1275 struct radeon_clock_array { 1276 u32 count; 1277 u32 *values; 1278 }; 1279 1280 struct radeon_clock_voltage_dependency_entry { 1281 u32 clk; 1282 u16 v; 1283 }; 1284 1285 struct radeon_clock_voltage_dependency_table { 1286 u32 count; 1287 struct radeon_clock_voltage_dependency_entry *entries; 1288 }; 1289 1290 struct radeon_cac_leakage_entry { 1291 u16 vddc; 1292 u32 leakage; 1293 }; 1294 1295 struct radeon_cac_leakage_table { 1296 u32 count; 1297 struct radeon_cac_leakage_entry *entries; 1298 }; 1299 1300 struct radeon_phase_shedding_limits_entry { 1301 u16 voltage; 1302 u32 sclk; 1303 u32 mclk; 1304 }; 1305 1306 struct radeon_phase_shedding_limits_table { 1307 u32 count; 1308 struct radeon_phase_shedding_limits_entry *entries; 1309 }; 1310 1311 struct radeon_ppm_table { 1312 u8 ppm_design; 1313 u16 cpu_core_number; 1314 u32 platform_tdp; 1315 u32 small_ac_platform_tdp; 1316 u32 platform_tdc; 1317 u32 small_ac_platform_tdc; 1318 u32 apu_tdp; 1319 u32 dgpu_tdp; 1320 u32 dgpu_ulv_power; 1321 u32 tj_max; 1322 }; 1323 1324 struct radeon_dpm_dynamic_state { 1325 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1326 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1327 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1328 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1329 struct radeon_clock_array valid_sclk_values; 1330 struct radeon_clock_array valid_mclk_values; 1331 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1332 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1333 u32 mclk_sclk_ratio; 1334 u32 sclk_mclk_delta; 1335 u16 vddc_vddci_delta; 1336 u16 min_vddc_for_pcie_gen2; 1337 struct radeon_cac_leakage_table cac_leakage_table; 1338 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1339 struct radeon_ppm_table *ppm_table; 1340 }; 1341 1342 struct radeon_dpm_fan { 1343 u16 t_min; 1344 u16 t_med; 1345 u16 t_high; 1346 u16 pwm_min; 1347 u16 pwm_med; 1348 u16 pwm_high; 1349 u8 t_hyst; 1350 u32 cycle_delay; 1351 u16 t_max; 1352 bool ucode_fan_control; 1353 }; 1354 1355 enum radeon_pcie_gen { 1356 RADEON_PCIE_GEN1 = 0, 1357 RADEON_PCIE_GEN2 = 1, 1358 RADEON_PCIE_GEN3 = 2, 1359 RADEON_PCIE_GEN_INVALID = 0xffff 1360 }; 1361 1362 enum radeon_dpm_forced_level { 1363 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1364 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1365 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1366 }; 1367 1368 struct radeon_dpm { 1369 struct radeon_ps *ps; 1370 /* number of valid power states */ 1371 int num_ps; 1372 /* current power state that is active */ 1373 struct radeon_ps *current_ps; 1374 /* requested power state */ 1375 struct radeon_ps *requested_ps; 1376 /* boot up power state */ 1377 struct radeon_ps *boot_ps; 1378 /* default uvd power state */ 1379 struct radeon_ps *uvd_ps; 1380 enum radeon_pm_state_type state; 1381 enum radeon_pm_state_type user_state; 1382 u32 platform_caps; 1383 u32 voltage_response_time; 1384 u32 backbias_response_time; 1385 void *priv; 1386 u32 new_active_crtcs; 1387 int new_active_crtc_count; 1388 u32 current_active_crtcs; 1389 int current_active_crtc_count; 1390 struct radeon_dpm_dynamic_state dyn_state; 1391 struct radeon_dpm_fan fan; 1392 u32 tdp_limit; 1393 u32 near_tdp_limit; 1394 u32 near_tdp_limit_adjusted; 1395 u32 sq_ramping_threshold; 1396 u32 cac_leakage; 1397 u16 tdp_od_limit; 1398 u32 tdp_adjustment; 1399 u16 load_line_slope; 1400 bool power_control; 1401 bool ac_power; 1402 /* special states active */ 1403 bool thermal_active; 1404 bool uvd_active; 1405 /* thermal handling */ 1406 struct radeon_dpm_thermal thermal; 1407 /* forced levels */ 1408 enum radeon_dpm_forced_level forced_level; 1409 }; 1410 1411 void radeon_dpm_enable_power_state(struct radeon_device *rdev, 1412 enum radeon_pm_state_type dpm_state); 1413 1414 1415 struct radeon_pm { 1416 struct lock mutex; 1417 /* write locked while reprogramming mclk */ 1418 struct lock mclk_lock; 1419 u32 active_crtcs; 1420 int active_crtc_count; 1421 int req_vblank; 1422 bool vblank_sync; 1423 fixed20_12 max_bandwidth; 1424 fixed20_12 igp_sideport_mclk; 1425 fixed20_12 igp_system_mclk; 1426 fixed20_12 igp_ht_link_clk; 1427 fixed20_12 igp_ht_link_width; 1428 fixed20_12 k8_bandwidth; 1429 fixed20_12 sideport_bandwidth; 1430 fixed20_12 ht_bandwidth; 1431 fixed20_12 core_bandwidth; 1432 fixed20_12 sclk; 1433 fixed20_12 mclk; 1434 fixed20_12 needed_bandwidth; 1435 struct radeon_power_state *power_state; 1436 /* number of valid power states */ 1437 int num_power_states; 1438 int current_power_state_index; 1439 int current_clock_mode_index; 1440 int requested_power_state_index; 1441 int requested_clock_mode_index; 1442 int default_power_state_index; 1443 u32 current_sclk; 1444 u32 current_mclk; 1445 u16 current_vddc; 1446 u16 current_vddci; 1447 u32 default_sclk; 1448 u32 default_mclk; 1449 u16 default_vddc; 1450 u16 default_vddci; 1451 struct radeon_i2c_chan *i2c_bus; 1452 /* selected pm method */ 1453 enum radeon_pm_method pm_method; 1454 /* dynpm power management */ 1455 #ifdef DUMBBELL_WIP 1456 struct delayed_work dynpm_idle_work; 1457 #endif /* DUMBBELL_WIP */ 1458 enum radeon_dynpm_state dynpm_state; 1459 enum radeon_dynpm_action dynpm_planned_action; 1460 unsigned long dynpm_action_timeout; 1461 bool dynpm_can_upclock; 1462 bool dynpm_can_downclock; 1463 /* profile-based power management */ 1464 enum radeon_pm_profile_type profile; 1465 int profile_index; 1466 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1467 /* internal thermal controller on rv6xx+ */ 1468 enum radeon_int_thermal_type int_thermal_type; 1469 struct ksensor *int_sensor; 1470 struct ksensordev *int_sensordev; 1471 /* dpm */ 1472 bool dpm_enabled; 1473 struct radeon_dpm dpm; 1474 }; 1475 1476 int radeon_pm_get_type_index(struct radeon_device *rdev, 1477 enum radeon_pm_state_type ps_type, 1478 int instance); 1479 /* 1480 * UVD 1481 */ 1482 #define RADEON_MAX_UVD_HANDLES 10 1483 #define RADEON_UVD_STACK_SIZE (1024*1024) 1484 #define RADEON_UVD_HEAP_SIZE (1024*1024) 1485 1486 struct radeon_uvd { 1487 struct radeon_bo *vcpu_bo; 1488 void *cpu_addr; 1489 uint64_t gpu_addr; 1490 void *saved_bo; 1491 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1492 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1493 struct delayed_work idle_work; 1494 }; 1495 1496 int radeon_uvd_init(struct radeon_device *rdev); 1497 void radeon_uvd_fini(struct radeon_device *rdev); 1498 int radeon_uvd_suspend(struct radeon_device *rdev); 1499 int radeon_uvd_resume(struct radeon_device *rdev); 1500 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1501 uint32_t handle, struct radeon_fence **fence); 1502 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1503 uint32_t handle, struct radeon_fence **fence); 1504 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo); 1505 void radeon_uvd_free_handles(struct radeon_device *rdev, 1506 struct drm_file *filp); 1507 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1508 void radeon_uvd_note_usage(struct radeon_device *rdev); 1509 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1510 unsigned vclk, unsigned dclk, 1511 unsigned vco_min, unsigned vco_max, 1512 unsigned fb_factor, unsigned fb_mask, 1513 unsigned pd_min, unsigned pd_max, 1514 unsigned pd_even, 1515 unsigned *optimal_fb_div, 1516 unsigned *optimal_vclk_div, 1517 unsigned *optimal_dclk_div); 1518 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1519 unsigned cg_upll_func_cntl); 1520 1521 struct r600_audio { 1522 int channels; 1523 int rate; 1524 int bits_per_sample; 1525 u8 status_bits; 1526 u8 category_code; 1527 }; 1528 1529 /* 1530 * Benchmarking 1531 */ 1532 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1533 1534 1535 /* 1536 * Testing 1537 */ 1538 void radeon_test_moves(struct radeon_device *rdev); 1539 void radeon_test_ring_sync(struct radeon_device *rdev, 1540 struct radeon_ring *cpA, 1541 struct radeon_ring *cpB); 1542 void radeon_test_syncing(struct radeon_device *rdev); 1543 1544 1545 /* 1546 * Debugfs 1547 */ 1548 struct radeon_debugfs { 1549 struct drm_info_list *files; 1550 unsigned num_files; 1551 }; 1552 1553 int radeon_debugfs_add_files(struct radeon_device *rdev, 1554 struct drm_info_list *files, 1555 unsigned nfiles); 1556 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1557 1558 1559 /* 1560 * ASIC specific functions. 1561 */ 1562 struct radeon_asic { 1563 int (*init)(struct radeon_device *rdev); 1564 void (*fini)(struct radeon_device *rdev); 1565 int (*resume)(struct radeon_device *rdev); 1566 int (*suspend)(struct radeon_device *rdev); 1567 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1568 int (*asic_reset)(struct radeon_device *rdev); 1569 /* ioctl hw specific callback. Some hw might want to perform special 1570 * operation on specific ioctl. For instance on wait idle some hw 1571 * might want to perform and HDP flush through MMIO as it seems that 1572 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed 1573 * through ring. 1574 */ 1575 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); 1576 /* check if 3D engine is idle */ 1577 bool (*gui_idle)(struct radeon_device *rdev); 1578 /* wait for mc_idle */ 1579 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1580 /* get the reference clock */ 1581 u32 (*get_xclk)(struct radeon_device *rdev); 1582 /* get the gpu clock counter */ 1583 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1584 /* gart */ 1585 struct { 1586 void (*tlb_flush)(struct radeon_device *rdev); 1587 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr); 1588 } gart; 1589 struct { 1590 int (*init)(struct radeon_device *rdev); 1591 void (*fini)(struct radeon_device *rdev); 1592 1593 u32 pt_ring_index; 1594 void (*set_page)(struct radeon_device *rdev, 1595 struct radeon_ib *ib, 1596 uint64_t pe, 1597 uint64_t addr, unsigned count, 1598 uint32_t incr, uint32_t flags); 1599 } vm; 1600 /* ring specific callbacks */ 1601 struct { 1602 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1603 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1604 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1605 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1606 struct radeon_semaphore *semaphore, bool emit_wait); 1607 int (*cs_parse)(struct radeon_cs_parser *p); 1608 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1609 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1610 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1611 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1612 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 1613 1614 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1615 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1616 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1617 } ring[RADEON_NUM_RINGS]; 1618 /* irqs */ 1619 struct { 1620 int (*set)(struct radeon_device *rdev); 1621 irqreturn_t (*process)(struct radeon_device *rdev); 1622 } irq; 1623 /* displays */ 1624 struct { 1625 /* display watermarks */ 1626 void (*bandwidth_update)(struct radeon_device *rdev); 1627 /* get frame count */ 1628 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1629 /* wait for vblank */ 1630 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1631 /* set backlight level */ 1632 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1633 /* get backlight level */ 1634 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1635 /* audio callbacks */ 1636 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1637 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1638 } display; 1639 /* copy functions for bo handling */ 1640 struct { 1641 int (*blit)(struct radeon_device *rdev, 1642 uint64_t src_offset, 1643 uint64_t dst_offset, 1644 unsigned num_gpu_pages, 1645 struct radeon_fence **fence); 1646 u32 blit_ring_index; 1647 int (*dma)(struct radeon_device *rdev, 1648 uint64_t src_offset, 1649 uint64_t dst_offset, 1650 unsigned num_gpu_pages, 1651 struct radeon_fence **fence); 1652 u32 dma_ring_index; 1653 /* method used for bo copy */ 1654 int (*copy)(struct radeon_device *rdev, 1655 uint64_t src_offset, 1656 uint64_t dst_offset, 1657 unsigned num_gpu_pages, 1658 struct radeon_fence **fence); 1659 /* ring used for bo copies */ 1660 u32 copy_ring_index; 1661 } copy; 1662 /* surfaces */ 1663 struct { 1664 int (*set_reg)(struct radeon_device *rdev, int reg, 1665 uint32_t tiling_flags, uint32_t pitch, 1666 uint32_t offset, uint32_t obj_size); 1667 void (*clear_reg)(struct radeon_device *rdev, int reg); 1668 } surface; 1669 /* hotplug detect */ 1670 struct { 1671 void (*init)(struct radeon_device *rdev); 1672 void (*fini)(struct radeon_device *rdev); 1673 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1674 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1675 } hpd; 1676 /* static power management */ 1677 struct { 1678 void (*misc)(struct radeon_device *rdev); 1679 void (*prepare)(struct radeon_device *rdev); 1680 void (*finish)(struct radeon_device *rdev); 1681 void (*init_profile)(struct radeon_device *rdev); 1682 void (*get_dynpm_state)(struct radeon_device *rdev); 1683 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1684 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1685 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1686 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1687 int (*get_pcie_lanes)(struct radeon_device *rdev); 1688 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1689 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1690 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 1691 int (*get_temperature)(struct radeon_device *rdev); 1692 } pm; 1693 /* dynamic power management */ 1694 struct { 1695 int (*init)(struct radeon_device *rdev); 1696 void (*setup_asic)(struct radeon_device *rdev); 1697 int (*enable)(struct radeon_device *rdev); 1698 void (*disable)(struct radeon_device *rdev); 1699 int (*pre_set_power_state)(struct radeon_device *rdev); 1700 int (*set_power_state)(struct radeon_device *rdev); 1701 void (*post_set_power_state)(struct radeon_device *rdev); 1702 void (*display_configuration_changed)(struct radeon_device *rdev); 1703 void (*fini)(struct radeon_device *rdev); 1704 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 1705 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 1706 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 1707 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 1708 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 1709 bool (*vblank_too_short)(struct radeon_device *rdev); 1710 } dpm; 1711 /* pageflipping */ 1712 struct { 1713 void (*pre_page_flip)(struct radeon_device *rdev, int crtc); 1714 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 1715 void (*post_page_flip)(struct radeon_device *rdev, int crtc); 1716 } pflip; 1717 }; 1718 1719 /* 1720 * Asic structures 1721 */ 1722 struct r100_asic { 1723 const unsigned *reg_safe_bm; 1724 unsigned reg_safe_bm_size; 1725 u32 hdp_cntl; 1726 }; 1727 1728 struct r300_asic { 1729 const unsigned *reg_safe_bm; 1730 unsigned reg_safe_bm_size; 1731 u32 resync_scratch; 1732 u32 hdp_cntl; 1733 }; 1734 1735 struct r600_asic { 1736 unsigned max_pipes; 1737 unsigned max_tile_pipes; 1738 unsigned max_simds; 1739 unsigned max_backends; 1740 unsigned max_gprs; 1741 unsigned max_threads; 1742 unsigned max_stack_entries; 1743 unsigned max_hw_contexts; 1744 unsigned max_gs_threads; 1745 unsigned sx_max_export_size; 1746 unsigned sx_max_export_pos_size; 1747 unsigned sx_max_export_smx_size; 1748 unsigned sq_num_cf_insts; 1749 unsigned tiling_nbanks; 1750 unsigned tiling_npipes; 1751 unsigned tiling_group_size; 1752 unsigned tile_config; 1753 unsigned backend_map; 1754 }; 1755 1756 struct rv770_asic { 1757 unsigned max_pipes; 1758 unsigned max_tile_pipes; 1759 unsigned max_simds; 1760 unsigned max_backends; 1761 unsigned max_gprs; 1762 unsigned max_threads; 1763 unsigned max_stack_entries; 1764 unsigned max_hw_contexts; 1765 unsigned max_gs_threads; 1766 unsigned sx_max_export_size; 1767 unsigned sx_max_export_pos_size; 1768 unsigned sx_max_export_smx_size; 1769 unsigned sq_num_cf_insts; 1770 unsigned sx_num_of_sets; 1771 unsigned sc_prim_fifo_size; 1772 unsigned sc_hiz_tile_fifo_size; 1773 unsigned sc_earlyz_tile_fifo_fize; 1774 unsigned tiling_nbanks; 1775 unsigned tiling_npipes; 1776 unsigned tiling_group_size; 1777 unsigned tile_config; 1778 unsigned backend_map; 1779 }; 1780 1781 struct evergreen_asic { 1782 unsigned num_ses; 1783 unsigned max_pipes; 1784 unsigned max_tile_pipes; 1785 unsigned max_simds; 1786 unsigned max_backends; 1787 unsigned max_gprs; 1788 unsigned max_threads; 1789 unsigned max_stack_entries; 1790 unsigned max_hw_contexts; 1791 unsigned max_gs_threads; 1792 unsigned sx_max_export_size; 1793 unsigned sx_max_export_pos_size; 1794 unsigned sx_max_export_smx_size; 1795 unsigned sq_num_cf_insts; 1796 unsigned sx_num_of_sets; 1797 unsigned sc_prim_fifo_size; 1798 unsigned sc_hiz_tile_fifo_size; 1799 unsigned sc_earlyz_tile_fifo_size; 1800 unsigned tiling_nbanks; 1801 unsigned tiling_npipes; 1802 unsigned tiling_group_size; 1803 unsigned tile_config; 1804 unsigned backend_map; 1805 }; 1806 1807 struct cayman_asic { 1808 unsigned max_shader_engines; 1809 unsigned max_pipes_per_simd; 1810 unsigned max_tile_pipes; 1811 unsigned max_simds_per_se; 1812 unsigned max_backends_per_se; 1813 unsigned max_texture_channel_caches; 1814 unsigned max_gprs; 1815 unsigned max_threads; 1816 unsigned max_gs_threads; 1817 unsigned max_stack_entries; 1818 unsigned sx_num_of_sets; 1819 unsigned sx_max_export_size; 1820 unsigned sx_max_export_pos_size; 1821 unsigned sx_max_export_smx_size; 1822 unsigned max_hw_contexts; 1823 unsigned sq_num_cf_insts; 1824 unsigned sc_prim_fifo_size; 1825 unsigned sc_hiz_tile_fifo_size; 1826 unsigned sc_earlyz_tile_fifo_size; 1827 1828 unsigned num_shader_engines; 1829 unsigned num_shader_pipes_per_simd; 1830 unsigned num_tile_pipes; 1831 unsigned num_simds_per_se; 1832 unsigned num_backends_per_se; 1833 unsigned backend_disable_mask_per_asic; 1834 unsigned backend_map; 1835 unsigned num_texture_channel_caches; 1836 unsigned mem_max_burst_length_bytes; 1837 unsigned mem_row_size_in_kb; 1838 unsigned shader_engine_tile_size; 1839 unsigned num_gpus; 1840 unsigned multi_gpu_tile_size; 1841 1842 unsigned tile_config; 1843 }; 1844 1845 struct si_asic { 1846 unsigned max_shader_engines; 1847 unsigned max_tile_pipes; 1848 unsigned max_cu_per_sh; 1849 unsigned max_sh_per_se; 1850 unsigned max_backends_per_se; 1851 unsigned max_texture_channel_caches; 1852 unsigned max_gprs; 1853 unsigned max_gs_threads; 1854 unsigned max_hw_contexts; 1855 unsigned sc_prim_fifo_size_frontend; 1856 unsigned sc_prim_fifo_size_backend; 1857 unsigned sc_hiz_tile_fifo_size; 1858 unsigned sc_earlyz_tile_fifo_size; 1859 1860 unsigned num_tile_pipes; 1861 unsigned num_backends_per_se; 1862 unsigned backend_disable_mask_per_asic; 1863 unsigned backend_map; 1864 unsigned num_texture_channel_caches; 1865 unsigned mem_max_burst_length_bytes; 1866 unsigned mem_row_size_in_kb; 1867 unsigned shader_engine_tile_size; 1868 unsigned num_gpus; 1869 unsigned multi_gpu_tile_size; 1870 1871 unsigned tile_config; 1872 uint32_t tile_mode_array[32]; 1873 }; 1874 1875 struct cik_asic { 1876 unsigned max_shader_engines; 1877 unsigned max_tile_pipes; 1878 unsigned max_cu_per_sh; 1879 unsigned max_sh_per_se; 1880 unsigned max_backends_per_se; 1881 unsigned max_texture_channel_caches; 1882 unsigned max_gprs; 1883 unsigned max_gs_threads; 1884 unsigned max_hw_contexts; 1885 unsigned sc_prim_fifo_size_frontend; 1886 unsigned sc_prim_fifo_size_backend; 1887 unsigned sc_hiz_tile_fifo_size; 1888 unsigned sc_earlyz_tile_fifo_size; 1889 1890 unsigned num_tile_pipes; 1891 unsigned num_backends_per_se; 1892 unsigned backend_disable_mask_per_asic; 1893 unsigned backend_map; 1894 unsigned num_texture_channel_caches; 1895 unsigned mem_max_burst_length_bytes; 1896 unsigned mem_row_size_in_kb; 1897 unsigned shader_engine_tile_size; 1898 unsigned num_gpus; 1899 unsigned multi_gpu_tile_size; 1900 1901 unsigned tile_config; 1902 uint32_t tile_mode_array[32]; 1903 }; 1904 1905 union radeon_asic_config { 1906 struct r300_asic r300; 1907 struct r100_asic r100; 1908 struct r600_asic r600; 1909 struct rv770_asic rv770; 1910 struct evergreen_asic evergreen; 1911 struct cayman_asic cayman; 1912 struct si_asic si; 1913 struct cik_asic cik; 1914 }; 1915 1916 /* 1917 * asic initizalization from radeon_asic.c 1918 */ 1919 int radeon_asic_init(struct radeon_device *rdev); 1920 1921 1922 /* 1923 * IOCTL. 1924 */ 1925 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 1926 struct drm_file *filp); 1927 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 1928 struct drm_file *filp); 1929 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 1930 struct drm_file *file_priv); 1931 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 1932 struct drm_file *file_priv); 1933 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1934 struct drm_file *file_priv); 1935 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 1936 struct drm_file *file_priv); 1937 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1938 struct drm_file *filp); 1939 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 1940 struct drm_file *filp); 1941 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 1942 struct drm_file *filp); 1943 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1944 struct drm_file *filp); 1945 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 1946 struct drm_file *filp); 1947 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1948 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 1949 struct drm_file *filp); 1950 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 1951 struct drm_file *filp); 1952 1953 /* VRAM scratch page for HDP bug, default vram page */ 1954 struct r600_vram_scratch { 1955 struct radeon_bo *robj; 1956 volatile uint32_t *ptr; 1957 u64 gpu_addr; 1958 }; 1959 1960 /* 1961 * ACPI 1962 */ 1963 struct radeon_atif_notification_cfg { 1964 bool enabled; 1965 int command_code; 1966 }; 1967 1968 struct radeon_atif_notifications { 1969 bool display_switch; 1970 bool expansion_mode_change; 1971 bool thermal_state; 1972 bool forced_power_state; 1973 bool system_power_state; 1974 bool display_conf_change; 1975 bool px_gfx_switch; 1976 bool brightness_change; 1977 bool dgpu_display_event; 1978 }; 1979 1980 struct radeon_atif_functions { 1981 bool system_params; 1982 bool sbios_requests; 1983 bool select_active_disp; 1984 bool lid_state; 1985 bool get_tv_standard; 1986 bool set_tv_standard; 1987 bool get_panel_expansion_mode; 1988 bool set_panel_expansion_mode; 1989 bool temperature_change; 1990 bool graphics_device_types; 1991 }; 1992 1993 struct radeon_atif { 1994 struct radeon_atif_notifications notifications; 1995 struct radeon_atif_functions functions; 1996 struct radeon_atif_notification_cfg notification_cfg; 1997 struct radeon_encoder *encoder_for_bl; 1998 }; 1999 2000 struct radeon_atcs_functions { 2001 bool get_ext_state; 2002 bool pcie_perf_req; 2003 bool pcie_dev_rdy; 2004 bool pcie_bus_width; 2005 }; 2006 2007 struct radeon_atcs { 2008 struct radeon_atcs_functions functions; 2009 }; 2010 2011 /* 2012 * Core structure, functions and helpers. 2013 */ 2014 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2015 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2016 2017 struct radeon_device { 2018 device_t dev; 2019 struct drm_device *ddev; 2020 struct lock exclusive_lock; 2021 /* ASIC */ 2022 union radeon_asic_config config; 2023 enum radeon_family family; 2024 unsigned long flags; 2025 int usec_timeout; 2026 enum radeon_pll_errata pll_errata; 2027 int num_gb_pipes; 2028 int num_z_pipes; 2029 int disp_priority; 2030 /* BIOS */ 2031 uint8_t *bios; 2032 bool is_atom_bios; 2033 uint16_t bios_header_start; 2034 struct radeon_bo *stollen_vga_memory; 2035 /* Register mmio */ 2036 resource_size_t rmmio_base; 2037 resource_size_t rmmio_size; 2038 /* protects concurrent MM_INDEX/DATA based register access */ 2039 struct spinlock mmio_idx_lock; 2040 int rmmio_rid; 2041 struct resource *rmmio; 2042 radeon_rreg_t mc_rreg; 2043 radeon_wreg_t mc_wreg; 2044 radeon_rreg_t pll_rreg; 2045 radeon_wreg_t pll_wreg; 2046 uint32_t pcie_reg_mask; 2047 radeon_rreg_t pciep_rreg; 2048 radeon_wreg_t pciep_wreg; 2049 /* io port */ 2050 int rio_rid; 2051 struct resource *rio_mem; 2052 resource_size_t rio_mem_size; 2053 struct radeon_clock clock; 2054 struct radeon_mc mc; 2055 struct radeon_gart gart; 2056 struct radeon_mode_info mode_info; 2057 struct radeon_scratch scratch; 2058 struct radeon_doorbell doorbell; 2059 struct radeon_mman mman; 2060 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2061 wait_queue_head_t fence_queue; 2062 struct lock ring_lock; 2063 struct radeon_ring ring[RADEON_NUM_RINGS]; 2064 bool ib_pool_ready; 2065 struct radeon_sa_manager ring_tmp_bo; 2066 struct radeon_irq irq; 2067 struct radeon_asic *asic; 2068 struct radeon_gem gem; 2069 struct radeon_pm pm; 2070 struct radeon_uvd uvd; 2071 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2072 struct radeon_wb wb; 2073 struct radeon_dummy_page dummy_page; 2074 bool shutdown; 2075 bool suspend; 2076 bool need_dma32; 2077 bool accel_working; 2078 bool fastfb_working; /* IGP feature*/ 2079 bool fictitious_range_registered; 2080 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2081 const struct firmware *me_fw; /* all family ME firmware */ 2082 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2083 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2084 const struct firmware *mc_fw; /* NI MC firmware */ 2085 const struct firmware *ce_fw; /* SI CE firmware */ 2086 const struct firmware *mec_fw; /* CIK MEC firmware */ 2087 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2088 const struct firmware *smc_fw; /* SMC firmware */ 2089 const struct firmware *uvd_fw; /* UVD firmware */ 2090 struct r600_blit r600_blit; 2091 struct r600_vram_scratch vram_scratch; 2092 int msi_enabled; /* msi enabled */ 2093 struct r600_ih ih; /* r6/700 interrupt ring */ 2094 struct radeon_rlc rlc; 2095 struct radeon_mec mec; 2096 struct taskqueue *tq; 2097 struct task hotplug_work; 2098 struct task audio_work; 2099 struct task reset_work; 2100 int num_crtc; /* number of crtcs */ 2101 struct lock dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2102 bool audio_enabled; 2103 bool has_uvd; 2104 struct r600_audio audio_status; /* audio stuff */ 2105 struct { 2106 ACPI_HANDLE handle; 2107 ACPI_NOTIFY_HANDLER notifier_call; 2108 } acpi; 2109 /* only one userspace can use Hyperz features or CMASK at a time */ 2110 struct drm_file *hyperz_filp; 2111 struct drm_file *cmask_filp; 2112 /* i2c buses */ 2113 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2114 /* debugfs */ 2115 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 2116 unsigned debugfs_count; 2117 /* virtual memory */ 2118 struct radeon_vm_manager vm_manager; 2119 struct spinlock gpu_clock_mutex; 2120 /* ACPI interface */ 2121 struct radeon_atif atif; 2122 struct radeon_atcs atcs; 2123 /* srbm instance registers */ 2124 struct spinlock srbm_mutex; 2125 }; 2126 2127 int radeon_device_init(struct radeon_device *rdev, 2128 struct drm_device *ddev, 2129 uint32_t flags); 2130 void radeon_device_fini(struct radeon_device *rdev); 2131 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2132 2133 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2134 bool always_indirect); 2135 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2136 bool always_indirect); 2137 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2138 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2139 2140 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 offset); 2141 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v); 2142 2143 /* 2144 * Cast helper 2145 */ 2146 #define to_radeon_fence(p) ((struct radeon_fence *)(p)) 2147 2148 /* 2149 * Registers read & write functions. 2150 */ 2151 #define RREG8(reg) bus_read_1((rdev->rmmio), (reg)) 2152 #define WREG8(reg, v) bus_write_1((rdev->rmmio), (reg), v) 2153 #define RREG16(reg) bus_read_2((rdev->rmmio), (reg)) 2154 #define WREG16(reg, v) bus_write_2((rdev->rmmio), (reg), v) 2155 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2156 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2157 #define DREG32(reg) DRM_INFO("REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) 2158 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2159 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2160 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2161 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2162 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2163 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2164 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2165 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2166 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2167 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2168 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2169 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2170 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2171 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2172 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2173 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2174 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2175 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2176 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2177 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2178 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2179 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2180 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2181 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2182 #define WREG32_P(reg, val, mask) \ 2183 do { \ 2184 uint32_t tmp_ = RREG32(reg); \ 2185 tmp_ &= (mask); \ 2186 tmp_ |= ((val) & ~(mask)); \ 2187 WREG32(reg, tmp_); \ 2188 } while (0) 2189 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2190 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2191 #define WREG32_PLL_P(reg, val, mask) \ 2192 do { \ 2193 uint32_t tmp_ = RREG32_PLL(reg); \ 2194 tmp_ &= (mask); \ 2195 tmp_ |= ((val) & ~(mask)); \ 2196 WREG32_PLL(reg, tmp_); \ 2197 } while (0) 2198 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2199 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2200 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2201 2202 #define RDOORBELL32(offset) cik_mm_rdoorbell(rdev, (offset)) 2203 #define WDOORBELL32(offset, v) cik_mm_wdoorbell(rdev, (offset), (v)) 2204 2205 /* 2206 * Indirect registers accessor 2207 */ 2208 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 2209 { 2210 uint32_t r; 2211 2212 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2213 r = RREG32(RADEON_PCIE_DATA); 2214 return r; 2215 } 2216 2217 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2218 { 2219 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2220 WREG32(RADEON_PCIE_DATA, (v)); 2221 } 2222 2223 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) 2224 { 2225 u32 r; 2226 2227 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2228 r = RREG32(TN_SMC_IND_DATA_0); 2229 return r; 2230 } 2231 2232 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2233 { 2234 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2235 WREG32(TN_SMC_IND_DATA_0, (v)); 2236 } 2237 2238 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) 2239 { 2240 u32 r; 2241 2242 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2243 r = RREG32(R600_RCU_DATA); 2244 return r; 2245 } 2246 2247 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2248 { 2249 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2250 WREG32(R600_RCU_DATA, (v)); 2251 } 2252 2253 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) 2254 { 2255 u32 r; 2256 2257 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2258 r = RREG32(EVERGREEN_CG_IND_DATA); 2259 return r; 2260 } 2261 2262 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2263 { 2264 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2265 WREG32(EVERGREEN_CG_IND_DATA, (v)); 2266 } 2267 2268 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg) 2269 { 2270 u32 r; 2271 2272 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2273 r = RREG32(EVERGREEN_PIF_PHY0_DATA); 2274 return r; 2275 } 2276 2277 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2278 { 2279 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2280 WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); 2281 } 2282 2283 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg) 2284 { 2285 u32 r; 2286 2287 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2288 r = RREG32(EVERGREEN_PIF_PHY1_DATA); 2289 return r; 2290 } 2291 2292 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2293 { 2294 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2295 WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); 2296 } 2297 2298 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) 2299 { 2300 u32 r; 2301 2302 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2303 r = RREG32(R600_UVD_CTX_DATA); 2304 return r; 2305 } 2306 2307 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2308 { 2309 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2310 WREG32(R600_UVD_CTX_DATA, (v)); 2311 } 2312 2313 void r100_pll_errata_after_index(struct radeon_device *rdev); 2314 2315 2316 /* 2317 * ASICs helpers. 2318 */ 2319 #define ASIC_IS_RN50(rdev) ((rdev->ddev->pci_device == 0x515e) || \ 2320 (rdev->ddev->pci_device == 0x5969)) 2321 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2322 (rdev->family == CHIP_RV200) || \ 2323 (rdev->family == CHIP_RS100) || \ 2324 (rdev->family == CHIP_RS200) || \ 2325 (rdev->family == CHIP_RV250) || \ 2326 (rdev->family == CHIP_RV280) || \ 2327 (rdev->family == CHIP_RS300)) 2328 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2329 (rdev->family == CHIP_RV350) || \ 2330 (rdev->family == CHIP_R350) || \ 2331 (rdev->family == CHIP_RV380) || \ 2332 (rdev->family == CHIP_R420) || \ 2333 (rdev->family == CHIP_R423) || \ 2334 (rdev->family == CHIP_RV410) || \ 2335 (rdev->family == CHIP_RS400) || \ 2336 (rdev->family == CHIP_RS480)) 2337 #define ASIC_IS_X2(rdev) ((rdev->ddev->pci_device == 0x9441) || \ 2338 (rdev->ddev->pci_device == 0x9443) || \ 2339 (rdev->ddev->pci_device == 0x944B) || \ 2340 (rdev->ddev->pci_device == 0x9506) || \ 2341 (rdev->ddev->pci_device == 0x9509) || \ 2342 (rdev->ddev->pci_device == 0x950F) || \ 2343 (rdev->ddev->pci_device == 0x689C) || \ 2344 (rdev->ddev->pci_device == 0x689D)) 2345 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2346 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2347 (rdev->family == CHIP_RS690) || \ 2348 (rdev->family == CHIP_RS740) || \ 2349 (rdev->family >= CHIP_R600)) 2350 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2351 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2352 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2353 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2354 (rdev->flags & RADEON_IS_IGP)) 2355 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2356 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2357 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2358 (rdev->flags & RADEON_IS_IGP)) 2359 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2360 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2361 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2362 2363 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pci_device == 0x6849) || \ 2364 (rdev->ddev->pci_device == 0x6850) || \ 2365 (rdev->ddev->pci_device == 0x6858) || \ 2366 (rdev->ddev->pci_device == 0x6859) || \ 2367 (rdev->ddev->pci_device == 0x6840) || \ 2368 (rdev->ddev->pci_device == 0x6841) || \ 2369 (rdev->ddev->pci_device == 0x6842) || \ 2370 (rdev->ddev->pci_device == 0x6843)) 2371 2372 /* 2373 * BIOS helpers. 2374 */ 2375 #define RBIOS8(i) (rdev->bios[i]) 2376 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2377 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2378 2379 int radeon_combios_init(struct radeon_device *rdev); 2380 void radeon_combios_fini(struct radeon_device *rdev); 2381 int radeon_atombios_init(struct radeon_device *rdev); 2382 void radeon_atombios_fini(struct radeon_device *rdev); 2383 2384 2385 /* 2386 * RING helpers. 2387 */ 2388 #if !defined(DRM_DEBUG_CODE) || DRM_DEBUG_CODE == 0 2389 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2390 { 2391 ring->ring[ring->wptr++] = v; 2392 ring->wptr &= ring->ptr_mask; 2393 ring->count_dw--; 2394 ring->ring_free_dw--; 2395 } 2396 #else 2397 /* With debugging this is just too big to inline */ 2398 void radeon_ring_write(struct radeon_ring *ring, uint32_t v); 2399 #endif 2400 2401 /* 2402 * ASICs macro. 2403 */ 2404 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2405 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2406 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2407 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2408 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p)) 2409 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2410 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 2411 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2412 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) 2413 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2414 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2415 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2416 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp)) 2417 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp)) 2418 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp)) 2419 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib)) 2420 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib)) 2421 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp)) 2422 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm)) 2423 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_rptr((rdev), (r)) 2424 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_wptr((rdev), (r)) 2425 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].set_wptr((rdev), (r)) 2426 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2427 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2428 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2429 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2430 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2431 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2432 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2433 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence)) 2434 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2435 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) 2436 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) 2437 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) 2438 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2439 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2440 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2441 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2442 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2443 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2444 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2445 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2446 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2447 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2448 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2449 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2450 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2451 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2452 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2453 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2454 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2455 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2456 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2457 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2458 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2459 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2460 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2461 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2462 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2463 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc)) 2464 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) 2465 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc)) 2466 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2467 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2468 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2469 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2470 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2471 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2472 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2473 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2474 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2475 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2476 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2477 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2478 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2479 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2480 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2481 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2482 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2483 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2484 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2485 2486 /* Common functions */ 2487 /* AGP */ 2488 extern int radeon_gpu_reset(struct radeon_device *rdev); 2489 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2490 extern void radeon_agp_disable(struct radeon_device *rdev); 2491 extern int radeon_modeset_init(struct radeon_device *rdev); 2492 extern void radeon_modeset_fini(struct radeon_device *rdev); 2493 extern bool radeon_card_posted(struct radeon_device *rdev); 2494 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2495 extern void radeon_update_display_priority(struct radeon_device *rdev); 2496 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2497 extern void radeon_scratch_init(struct radeon_device *rdev); 2498 extern void radeon_wb_fini(struct radeon_device *rdev); 2499 extern int radeon_wb_init(struct radeon_device *rdev); 2500 extern void radeon_wb_disable(struct radeon_device *rdev); 2501 extern void radeon_surface_init(struct radeon_device *rdev); 2502 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2503 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2504 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2505 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2506 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2507 extern int radeon_resume_kms(struct drm_device *dev); 2508 extern int radeon_suspend_kms(struct drm_device *dev); 2509 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2510 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2511 const u32 *registers, 2512 const u32 array_size); 2513 2514 /* 2515 * vm 2516 */ 2517 int radeon_vm_manager_init(struct radeon_device *rdev); 2518 void radeon_vm_manager_fini(struct radeon_device *rdev); 2519 void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2520 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2521 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm); 2522 void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm); 2523 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2524 struct radeon_vm *vm, int ring); 2525 void radeon_vm_fence(struct radeon_device *rdev, 2526 struct radeon_vm *vm, 2527 struct radeon_fence *fence); 2528 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2529 int radeon_vm_bo_update_pte(struct radeon_device *rdev, 2530 struct radeon_vm *vm, 2531 struct radeon_bo *bo, 2532 struct ttm_mem_reg *mem); 2533 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2534 struct radeon_bo *bo); 2535 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2536 struct radeon_bo *bo); 2537 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2538 struct radeon_vm *vm, 2539 struct radeon_bo *bo); 2540 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2541 struct radeon_bo_va *bo_va, 2542 uint64_t offset, 2543 uint32_t flags); 2544 int radeon_vm_bo_rmv(struct radeon_device *rdev, 2545 struct radeon_bo_va *bo_va); 2546 2547 /* audio */ 2548 void r600_audio_update_hdmi(void *arg, int pending); 2549 2550 /* 2551 * R600 vram scratch functions 2552 */ 2553 int r600_vram_scratch_init(struct radeon_device *rdev); 2554 void r600_vram_scratch_fini(struct radeon_device *rdev); 2555 2556 /* 2557 * r600 cs checking helper 2558 */ 2559 unsigned r600_mip_minify(unsigned size, unsigned level); 2560 bool r600_fmt_is_valid_color(u32 format); 2561 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2562 int r600_fmt_get_blocksize(u32 format); 2563 int r600_fmt_get_nblocksx(u32 format, u32 w); 2564 int r600_fmt_get_nblocksy(u32 format, u32 h); 2565 2566 /* 2567 * r600 functions used by radeon_encoder.c 2568 */ 2569 struct radeon_hdmi_acr { 2570 u32 clock; 2571 2572 int n_32khz; 2573 int cts_32khz; 2574 2575 int n_44_1khz; 2576 int cts_44_1khz; 2577 2578 int n_48khz; 2579 int cts_48khz; 2580 2581 }; 2582 2583 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 2584 2585 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 2586 u32 tiling_pipe_num, 2587 u32 max_rb_num, 2588 u32 total_max_rb_num, 2589 u32 enabled_rb_mask); 2590 2591 /* 2592 * evergreen functions used by radeon_encoder.c 2593 */ 2594 2595 extern int ni_init_microcode(struct radeon_device *rdev); 2596 extern int ni_mc_load_microcode(struct radeon_device *rdev); 2597 extern void ni_fini_microcode(struct radeon_device *rdev); 2598 2599 /* radeon_acpi.c */ 2600 extern int radeon_acpi_init(struct radeon_device *rdev); 2601 extern void radeon_acpi_fini(struct radeon_device *rdev); 2602 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 2603 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 2604 u8 perf_req, bool advertise); 2605 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 2606 2607 /* Prototypes added by @dumbbell. */ 2608 2609 /* atombios_encoders.c */ 2610 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 2611 struct drm_connector *drm_connector); 2612 void radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, 2613 uint32_t supported_device, u16 caps); 2614 2615 /* radeon_atombios.c */ 2616 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 2617 struct drm_display_mode *mode); 2618 2619 /* radeon_combios.c */ 2620 void radeon_combios_connected_scratch_regs(struct drm_connector *connector, 2621 struct drm_encoder *encoder, bool connected); 2622 2623 /* radeon_connectors.c */ 2624 void radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 2625 struct drm_encoder *encoder, bool connected); 2626 void radeon_add_legacy_connector(struct drm_device *dev, 2627 uint32_t connector_id, 2628 uint32_t supported_device, 2629 int connector_type, 2630 struct radeon_i2c_bus_rec *i2c_bus, 2631 uint16_t connector_object_id, 2632 struct radeon_hpd *hpd); 2633 void radeon_add_atom_connector(struct drm_device *dev, 2634 uint32_t connector_id, 2635 uint32_t supported_device, 2636 int connector_type, 2637 struct radeon_i2c_bus_rec *i2c_bus, 2638 uint32_t igp_lane_info, 2639 uint16_t connector_object_id, 2640 struct radeon_hpd *hpd, 2641 struct radeon_router *router); 2642 2643 /* radeon_encoders.c */ 2644 uint32_t radeon_get_encoder_enum(struct drm_device *dev, 2645 uint32_t supported_device, uint8_t dac); 2646 void radeon_link_encoder_connector(struct drm_device *dev); 2647 2648 /* radeon_legacy_encoders.c */ 2649 void radeon_add_legacy_encoder(struct drm_device *dev, 2650 uint32_t encoder_enum, uint32_t supported_device); 2651 void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder, 2652 struct drm_connector *drm_connector); 2653 2654 /* radeon_pm.c */ 2655 void radeon_pm_acpi_event_handler(struct radeon_device *rdev); 2656 2657 /* radeon_ttm.c */ 2658 int radeon_ttm_init(struct radeon_device *rdev); 2659 void radeon_ttm_fini(struct radeon_device *rdev); 2660 2661 /* r600.c */ 2662 int r600_ih_ring_alloc(struct radeon_device *rdev); 2663 void r600_ih_ring_fini(struct radeon_device *rdev); 2664 2665 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 2666 struct radeon_cs_packet *pkt, 2667 unsigned idx); 2668 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 2669 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 2670 struct radeon_cs_packet *pkt); 2671 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 2672 struct radeon_cs_reloc **cs_reloc, 2673 int nomm); 2674 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 2675 uint32_t *vline_start_end, 2676 uint32_t *vline_status); 2677 2678 #include "radeon_object.h" 2679 2680 #endif 2681