1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #ifndef __RADEON_H__ 30 #define __RADEON_H__ 31 32 /* TODO: Here are things that needs to be done : 33 * - surface allocator & initializer : (bit like scratch reg) should 34 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 35 * related to surface 36 * - WB : write back stuff (do it bit like scratch reg things) 37 * - Vblank : look at Jesse's rework and what we should do 38 * - r600/r700: gart & cp 39 * - cs : clean cs ioctl use bitmap & things like that. 40 * - power management stuff 41 * - Barrier in gart code 42 * - Unmappabled vram ? 43 * - TESTING, TESTING, TESTING 44 */ 45 46 /* Initialization path: 47 * We expect that acceleration initialization might fail for various 48 * reasons even thought we work hard to make it works on most 49 * configurations. In order to still have a working userspace in such 50 * situation the init path must succeed up to the memory controller 51 * initialization point. Failure before this point are considered as 52 * fatal error. Here is the init callchain : 53 * radeon_device_init perform common structure, mutex initialization 54 * asic_init setup the GPU memory layout and perform all 55 * one time initialization (failure in this 56 * function are considered fatal) 57 * asic_startup setup the GPU acceleration, in order to 58 * follow guideline the first thing this 59 * function should do is setting the GPU 60 * memory controller (only MC setup failure 61 * are considered as fatal) 62 */ 63 64 #include <contrib/dev/acpica/source/include/acpi.h> 65 #include <dev/acpica/acpivar.h> 66 67 #include <linux/atomic.h> 68 #include <linux/wait.h> 69 #include <linux/list.h> 70 #include <linux/kref.h> 71 #include <linux/interval_tree.h> 72 #include <linux/hashtable.h> 73 #include <linux/fence.h> 74 75 #include <ttm/ttm_bo_api.h> 76 #include <ttm/ttm_bo_driver.h> 77 #include <ttm/ttm_placement.h> 78 #include <ttm/ttm_module.h> 79 #include <ttm/ttm_execbuf_util.h> 80 81 #include <drm/drm_gem.h> 82 83 #include "radeon_family.h" 84 #include "radeon_mode.h" 85 #include "radeon_reg.h" 86 87 /* 88 * Modules parameters. 89 */ 90 extern int radeon_no_wb; 91 extern int radeon_modeset; 92 extern int radeon_dynclks; 93 extern int radeon_r4xx_atom; 94 extern int radeon_agpmode; 95 extern int radeon_vram_limit; 96 extern int radeon_gart_size; 97 extern int radeon_benchmarking; 98 extern int radeon_testing; 99 extern int radeon_connector_table; 100 extern int radeon_tv; 101 extern int radeon_audio; 102 extern int radeon_disp_priority; 103 extern int radeon_hw_i2c; 104 extern int radeon_pcie_gen2; 105 extern int radeon_msi; 106 extern int radeon_lockup_timeout; 107 extern int radeon_fastfb; 108 extern int radeon_dpm; 109 extern int radeon_aspm; 110 extern int radeon_runtime_pm; 111 extern int radeon_hard_reset; 112 extern int radeon_vm_size; 113 extern int radeon_vm_block_size; 114 extern int radeon_deep_color; 115 extern int radeon_use_pflipirq; 116 extern int radeon_bapm; 117 extern int radeon_backlight; 118 extern int radeon_auxch; 119 extern int radeon_mst; 120 extern int radeon_uvd; 121 extern int radeon_vce; 122 123 /* 124 * Copy from radeon_drv.h so we don't have to include both and have conflicting 125 * symbol; 126 */ 127 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 128 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 129 #define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */ 130 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 131 #define RADEON_IB_POOL_SIZE 16 132 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 133 #define RADEONFB_CONN_LIMIT 4 134 #define RADEON_BIOS_NUM_SCRATCH 8 135 136 /* internal ring indices */ 137 /* r1xx+ has gfx CP ring */ 138 #define RADEON_RING_TYPE_GFX_INDEX 0 139 140 /* cayman has 2 compute CP rings */ 141 #define CAYMAN_RING_TYPE_CP1_INDEX 1 142 #define CAYMAN_RING_TYPE_CP2_INDEX 2 143 144 /* R600+ has an async dma ring */ 145 #define R600_RING_TYPE_DMA_INDEX 3 146 /* cayman add a second async dma ring */ 147 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 148 149 /* R600+ */ 150 #define R600_RING_TYPE_UVD_INDEX 5 151 152 /* TN+ */ 153 #define TN_RING_TYPE_VCE1_INDEX 6 154 #define TN_RING_TYPE_VCE2_INDEX 7 155 156 /* max number of rings */ 157 #define RADEON_NUM_RINGS 8 158 159 /* number of hw syncs before falling back on blocking */ 160 #define RADEON_NUM_SYNCS 4 161 162 /* hardcode those limit for now */ 163 #define RADEON_VA_IB_OFFSET (1 << 20) 164 #define RADEON_VA_RESERVED_SIZE (8 << 20) 165 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 166 167 /* hard reset data */ 168 #define RADEON_ASIC_RESET_DATA 0x39d5e86b 169 170 /* reset flags */ 171 #define RADEON_RESET_GFX (1 << 0) 172 #define RADEON_RESET_COMPUTE (1 << 1) 173 #define RADEON_RESET_DMA (1 << 2) 174 #define RADEON_RESET_CP (1 << 3) 175 #define RADEON_RESET_GRBM (1 << 4) 176 #define RADEON_RESET_DMA1 (1 << 5) 177 #define RADEON_RESET_RLC (1 << 6) 178 #define RADEON_RESET_SEM (1 << 7) 179 #define RADEON_RESET_IH (1 << 8) 180 #define RADEON_RESET_VMC (1 << 9) 181 #define RADEON_RESET_MC (1 << 10) 182 #define RADEON_RESET_DISPLAY (1 << 11) 183 184 /* CG block flags */ 185 #define RADEON_CG_BLOCK_GFX (1 << 0) 186 #define RADEON_CG_BLOCK_MC (1 << 1) 187 #define RADEON_CG_BLOCK_SDMA (1 << 2) 188 #define RADEON_CG_BLOCK_UVD (1 << 3) 189 #define RADEON_CG_BLOCK_VCE (1 << 4) 190 #define RADEON_CG_BLOCK_HDP (1 << 5) 191 #define RADEON_CG_BLOCK_BIF (1 << 6) 192 193 /* CG flags */ 194 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 195 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 196 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 197 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 198 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 199 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 200 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 201 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 202 #define RADEON_CG_SUPPORT_MC_LS (1 << 8) 203 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 204 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 205 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 206 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 207 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 208 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 209 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 210 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 211 212 /* PG flags */ 213 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 214 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 215 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 216 #define RADEON_PG_SUPPORT_UVD (1 << 3) 217 #define RADEON_PG_SUPPORT_VCE (1 << 4) 218 #define RADEON_PG_SUPPORT_CP (1 << 5) 219 #define RADEON_PG_SUPPORT_GDS (1 << 6) 220 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 221 #define RADEON_PG_SUPPORT_SDMA (1 << 8) 222 #define RADEON_PG_SUPPORT_ACP (1 << 9) 223 #define RADEON_PG_SUPPORT_SAMU (1 << 10) 224 225 /* max cursor sizes (in pixels) */ 226 #define CURSOR_WIDTH 64 227 #define CURSOR_HEIGHT 64 228 229 #define CIK_CURSOR_WIDTH 128 230 #define CIK_CURSOR_HEIGHT 128 231 232 /* 233 * Errata workarounds. 234 */ 235 enum radeon_pll_errata { 236 CHIP_ERRATA_R300_CG = 0x00000001, 237 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 238 CHIP_ERRATA_PLL_DELAY = 0x00000004 239 }; 240 241 242 struct radeon_device; 243 244 245 /* 246 * BIOS. 247 */ 248 bool radeon_get_bios(struct radeon_device *rdev); 249 250 /* 251 * Dummy page 252 */ 253 struct radeon_dummy_page { 254 uint64_t entry; 255 struct drm_dma_handle *dmah; 256 dma_addr_t addr; 257 }; 258 int radeon_dummy_page_init(struct radeon_device *rdev); 259 void radeon_dummy_page_fini(struct radeon_device *rdev); 260 261 262 /* 263 * Clocks 264 */ 265 struct radeon_clock { 266 struct radeon_pll p1pll; 267 struct radeon_pll p2pll; 268 struct radeon_pll dcpll; 269 struct radeon_pll spll; 270 struct radeon_pll mpll; 271 /* 10 Khz units */ 272 uint32_t default_mclk; 273 uint32_t default_sclk; 274 uint32_t default_dispclk; 275 uint32_t current_dispclk; 276 uint32_t dp_extclk; 277 uint32_t max_pixel_clock; 278 uint32_t vco_freq; 279 }; 280 281 /* 282 * Power management 283 */ 284 int radeon_pm_init(struct radeon_device *rdev); 285 int radeon_pm_late_init(struct radeon_device *rdev); 286 void radeon_pm_fini(struct radeon_device *rdev); 287 void radeon_pm_compute_clocks(struct radeon_device *rdev); 288 void radeon_pm_suspend(struct radeon_device *rdev); 289 void radeon_pm_resume(struct radeon_device *rdev); 290 void radeon_combios_get_power_modes(struct radeon_device *rdev); 291 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 292 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 293 u8 clock_type, 294 u32 clock, 295 bool strobe_mode, 296 struct atom_clock_dividers *dividers); 297 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 298 u32 clock, 299 bool strobe_mode, 300 struct atom_mpll_param *mpll_param); 301 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 302 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 303 u16 voltage_level, u8 voltage_type, 304 u32 *gpio_value, u32 *gpio_mask); 305 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 306 u32 eng_clock, u32 mem_clock); 307 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 308 u8 voltage_type, u16 *voltage_step); 309 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 310 u16 voltage_id, u16 *voltage); 311 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 312 u16 *voltage, 313 u16 leakage_idx); 314 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 315 u16 *leakage_id); 316 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 317 u16 *vddc, u16 *vddci, 318 u16 virtual_voltage_id, 319 u16 vbios_voltage_id); 320 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 321 u16 virtual_voltage_id, 322 u16 *voltage); 323 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 324 u8 voltage_type, 325 u16 nominal_voltage, 326 u16 *true_voltage); 327 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 328 u8 voltage_type, u16 *min_voltage); 329 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 330 u8 voltage_type, u16 *max_voltage); 331 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 332 u8 voltage_type, u8 voltage_mode, 333 struct atom_voltage_table *voltage_table); 334 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 335 u8 voltage_type, u8 voltage_mode); 336 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 337 u8 voltage_type, 338 u8 *svd_gpio_id, u8 *svc_gpio_id); 339 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 340 u32 mem_clock); 341 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 342 u32 mem_clock); 343 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 344 u8 module_index, 345 struct atom_mc_reg_table *reg_table); 346 int radeon_atom_get_memory_info(struct radeon_device *rdev, 347 u8 module_index, struct atom_memory_info *mem_info); 348 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 349 bool gddr5, u8 module_index, 350 struct atom_memory_clock_range_table *mclk_range_table); 351 void rs690_pm_info(struct radeon_device *rdev); 352 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 353 unsigned *bankh, unsigned *mtaspect, 354 unsigned *tile_split); 355 356 /* 357 * Fences. 358 */ 359 struct radeon_fence_driver { 360 struct radeon_device *rdev; 361 uint32_t scratch_reg; 362 uint64_t gpu_addr; 363 volatile uint32_t *cpu_addr; 364 /* sync_seq is protected by ring emission lock */ 365 uint64_t sync_seq[RADEON_NUM_RINGS]; 366 atomic64_t last_seq; 367 bool initialized, delayed_irq; 368 struct delayed_work lockup_work; 369 }; 370 371 struct radeon_fence { 372 struct fence base; 373 374 struct radeon_device *rdev; 375 uint64_t seq; 376 /* RB, DMA, etc. */ 377 unsigned ring; 378 bool is_vm_update; 379 380 wait_queue_t fence_wake; 381 }; 382 383 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 384 int radeon_fence_driver_init(struct radeon_device *rdev); 385 void radeon_fence_driver_fini(struct radeon_device *rdev); 386 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); 387 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 388 void radeon_fence_process(struct radeon_device *rdev, int ring); 389 bool radeon_fence_signaled(struct radeon_fence *fence); 390 long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout); 391 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 392 int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 393 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 394 int radeon_fence_wait_any(struct radeon_device *rdev, 395 struct radeon_fence **fences, 396 bool intr); 397 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 398 void radeon_fence_unref(struct radeon_fence **fence); 399 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 400 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 401 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 402 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 403 struct radeon_fence *b) 404 { 405 if (!a) { 406 return b; 407 } 408 409 if (!b) { 410 return a; 411 } 412 413 BUG_ON(a->ring != b->ring); 414 415 if (a->seq > b->seq) { 416 return a; 417 } else { 418 return b; 419 } 420 } 421 422 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 423 struct radeon_fence *b) 424 { 425 if (!a) { 426 return false; 427 } 428 429 if (!b) { 430 return true; 431 } 432 433 BUG_ON(a->ring != b->ring); 434 435 return a->seq < b->seq; 436 } 437 438 /* 439 * Tiling registers 440 */ 441 struct radeon_surface_reg { 442 struct radeon_bo *bo; 443 }; 444 445 #define RADEON_GEM_MAX_SURFACES 8 446 447 /* 448 * TTM. 449 */ 450 struct radeon_mman { 451 struct ttm_bo_global_ref bo_global_ref; 452 struct drm_global_reference mem_global_ref; 453 struct ttm_bo_device bdev; 454 bool mem_global_referenced; 455 bool initialized; 456 457 #if defined(CONFIG_DEBUG_FS) 458 struct dentry *vram; 459 struct dentry *gtt; 460 #endif 461 }; 462 463 struct radeon_bo_list { 464 struct radeon_bo *robj; 465 struct ttm_validate_buffer tv; 466 uint64_t gpu_offset; 467 unsigned prefered_domains; 468 unsigned allowed_domains; 469 uint32_t tiling_flags; 470 }; 471 472 /* bo virtual address in a specific vm */ 473 struct radeon_bo_va { 474 /* protected by bo being reserved */ 475 struct list_head bo_list; 476 uint32_t flags; 477 struct radeon_fence *last_pt_update; 478 unsigned ref_count; 479 480 /* protected by vm mutex */ 481 struct interval_tree_node it; 482 struct list_head vm_status; 483 484 /* constant after initialization */ 485 struct radeon_vm *vm; 486 struct radeon_bo *bo; 487 }; 488 489 struct radeon_bo { 490 /* Protected by gem.mutex */ 491 struct list_head list; 492 /* Protected by tbo.reserved */ 493 u32 initial_domain; 494 struct ttm_place placements[4]; 495 struct ttm_placement placement; 496 struct ttm_buffer_object tbo; 497 struct ttm_bo_kmap_obj kmap; 498 u32 flags; 499 unsigned pin_count; 500 void *kptr; 501 u32 tiling_flags; 502 u32 pitch; 503 int surface_reg; 504 /* list of all virtual address to which this bo 505 * is associated to 506 */ 507 struct list_head va; 508 /* Constant after initialization */ 509 struct radeon_device *rdev; 510 struct drm_gem_object gem_base; 511 512 struct ttm_bo_kmap_obj dma_buf_vmap; 513 pid_t pid; 514 515 struct radeon_mn *mn; 516 struct interval_tree_node mn_it; 517 }; 518 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 519 520 int radeon_gem_debugfs_init(struct radeon_device *rdev); 521 522 /* sub-allocation manager, it has to be protected by another lock. 523 * By conception this is an helper for other part of the driver 524 * like the indirect buffer or semaphore, which both have their 525 * locking. 526 * 527 * Principe is simple, we keep a list of sub allocation in offset 528 * order (first entry has offset == 0, last entry has the highest 529 * offset). 530 * 531 * When allocating new object we first check if there is room at 532 * the end total_size - (last_object_offset + last_object_size) >= 533 * alloc_size. If so we allocate new object there. 534 * 535 * When there is not enough room at the end, we start waiting for 536 * each sub object until we reach object_offset+object_size >= 537 * alloc_size, this object then become the sub object we return. 538 * 539 * Alignment can't be bigger than page size. 540 * 541 * Hole are not considered for allocation to keep things simple. 542 * Assumption is that there won't be hole (all object on same 543 * alignment). 544 */ 545 struct radeon_sa_manager { 546 wait_queue_head_t wq; 547 struct radeon_bo *bo; 548 struct list_head *hole; 549 struct list_head flist[RADEON_NUM_RINGS]; 550 struct list_head olist; 551 unsigned size; 552 u64 gpu_addr; 553 void *cpu_ptr; 554 uint32_t domain; 555 uint32_t align; 556 }; 557 558 struct radeon_sa_bo; 559 560 /* sub-allocation buffer */ 561 struct radeon_sa_bo { 562 struct list_head olist; 563 struct list_head flist; 564 struct radeon_sa_manager *manager; 565 unsigned soffset; 566 unsigned eoffset; 567 struct radeon_fence *fence; 568 }; 569 570 /* 571 * GEM objects. 572 */ 573 struct radeon_gem { 574 struct lock mutex; 575 struct list_head objects; 576 }; 577 578 int radeon_gem_init(struct radeon_device *rdev); 579 void radeon_gem_fini(struct radeon_device *rdev); 580 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, 581 int alignment, int initial_domain, 582 u32 flags, bool kernel, 583 struct drm_gem_object **obj); 584 585 int radeon_mode_dumb_create(struct drm_file *file_priv, 586 struct drm_device *dev, 587 struct drm_mode_create_dumb *args); 588 int radeon_mode_dumb_mmap(struct drm_file *filp, 589 struct drm_device *dev, 590 uint32_t handle, uint64_t *offset_p); 591 592 /* 593 * Semaphores. 594 */ 595 struct radeon_semaphore { 596 struct radeon_sa_bo *sa_bo; 597 signed waiters; 598 uint64_t gpu_addr; 599 }; 600 601 int radeon_semaphore_create(struct radeon_device *rdev, 602 struct radeon_semaphore **semaphore); 603 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 604 struct radeon_semaphore *semaphore); 605 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 606 struct radeon_semaphore *semaphore); 607 void radeon_semaphore_free(struct radeon_device *rdev, 608 struct radeon_semaphore **semaphore, 609 struct radeon_fence *fence); 610 611 /* 612 * Synchronization 613 */ 614 struct radeon_sync { 615 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS]; 616 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 617 struct radeon_fence *last_vm_update; 618 }; 619 620 void radeon_sync_create(struct radeon_sync *sync); 621 void radeon_sync_fence(struct radeon_sync *sync, 622 struct radeon_fence *fence); 623 int radeon_sync_resv(struct radeon_device *rdev, 624 struct radeon_sync *sync, 625 struct reservation_object *resv, 626 bool shared); 627 int radeon_sync_rings(struct radeon_device *rdev, 628 struct radeon_sync *sync, 629 int waiting_ring); 630 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync, 631 struct radeon_fence *fence); 632 633 /* 634 * GART structures, functions & helpers 635 */ 636 struct radeon_mc; 637 638 #define RADEON_GPU_PAGE_SIZE 4096 639 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 640 #define RADEON_GPU_PAGE_SHIFT 12 641 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 642 643 #define RADEON_GART_PAGE_DUMMY 0 644 #define RADEON_GART_PAGE_VALID (1 << 0) 645 #define RADEON_GART_PAGE_READ (1 << 1) 646 #define RADEON_GART_PAGE_WRITE (1 << 2) 647 #define RADEON_GART_PAGE_SNOOP (1 << 3) 648 649 struct radeon_gart { 650 struct drm_dma_handle *dmah; 651 dma_addr_t table_addr; 652 struct radeon_bo *robj; 653 void *ptr; 654 unsigned num_gpu_pages; 655 unsigned num_cpu_pages; 656 unsigned table_size; 657 struct page **pages; 658 uint64_t *pages_entry; 659 bool ready; 660 }; 661 662 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 663 void radeon_gart_table_ram_free(struct radeon_device *rdev); 664 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 665 void radeon_gart_table_vram_free(struct radeon_device *rdev); 666 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 667 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 668 int radeon_gart_init(struct radeon_device *rdev); 669 void radeon_gart_fini(struct radeon_device *rdev); 670 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 671 int pages); 672 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 673 int pages, struct page **pagelist, 674 dma_addr_t *dma_addr, uint32_t flags); 675 676 677 /* 678 * GPU MC structures, functions & helpers 679 */ 680 struct radeon_mc { 681 resource_size_t aper_size; 682 resource_size_t aper_base; 683 resource_size_t agp_base; 684 /* for some chips with <= 32MB we need to lie 685 * about vram size near mc fb location */ 686 u64 mc_vram_size; 687 u64 visible_vram_size; 688 u64 gtt_size; 689 u64 gtt_start; 690 u64 gtt_end; 691 u64 vram_start; 692 u64 vram_end; 693 unsigned vram_width; 694 u64 real_vram_size; 695 int vram_mtrr; 696 bool vram_is_ddr; 697 bool igp_sideport_enabled; 698 u64 gtt_base_align; 699 u64 mc_mask; 700 }; 701 702 bool radeon_combios_sideport_present(struct radeon_device *rdev); 703 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 704 705 /* 706 * GPU scratch registers structures, functions & helpers 707 */ 708 struct radeon_scratch { 709 unsigned num_reg; 710 uint32_t reg_base; 711 bool free[32]; 712 uint32_t reg[32]; 713 }; 714 715 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 716 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 717 718 /* 719 * GPU doorbell structures, functions & helpers 720 */ 721 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 722 723 struct radeon_doorbell { 724 /* doorbell mmio */ 725 resource_size_t base; 726 resource_size_t size; 727 u32 __iomem *ptr; 728 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 729 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS); 730 }; 731 732 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 733 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 734 void radeon_doorbell_get_kfd_info(struct radeon_device *rdev, 735 phys_addr_t *aperture_base, 736 size_t *aperture_size, 737 size_t *start_offset); 738 739 /* 740 * IRQS. 741 */ 742 743 struct radeon_flip_work { 744 struct work_struct flip_work; 745 struct work_struct unpin_work; 746 struct radeon_device *rdev; 747 int crtc_id; 748 u32 target_vblank; 749 uint64_t base; 750 struct drm_pending_vblank_event *event; 751 struct radeon_bo *old_rbo; 752 struct fence *fence; 753 bool async; 754 }; 755 756 struct r500_irq_stat_regs { 757 u32 disp_int; 758 u32 hdmi0_status; 759 }; 760 761 struct r600_irq_stat_regs { 762 u32 disp_int; 763 u32 disp_int_cont; 764 u32 disp_int_cont2; 765 u32 d1grph_int; 766 u32 d2grph_int; 767 u32 hdmi0_status; 768 u32 hdmi1_status; 769 }; 770 771 struct evergreen_irq_stat_regs { 772 u32 disp_int; 773 u32 disp_int_cont; 774 u32 disp_int_cont2; 775 u32 disp_int_cont3; 776 u32 disp_int_cont4; 777 u32 disp_int_cont5; 778 u32 d1grph_int; 779 u32 d2grph_int; 780 u32 d3grph_int; 781 u32 d4grph_int; 782 u32 d5grph_int; 783 u32 d6grph_int; 784 u32 afmt_status1; 785 u32 afmt_status2; 786 u32 afmt_status3; 787 u32 afmt_status4; 788 u32 afmt_status5; 789 u32 afmt_status6; 790 }; 791 792 struct cik_irq_stat_regs { 793 u32 disp_int; 794 u32 disp_int_cont; 795 u32 disp_int_cont2; 796 u32 disp_int_cont3; 797 u32 disp_int_cont4; 798 u32 disp_int_cont5; 799 u32 disp_int_cont6; 800 u32 d1grph_int; 801 u32 d2grph_int; 802 u32 d3grph_int; 803 u32 d4grph_int; 804 u32 d5grph_int; 805 u32 d6grph_int; 806 }; 807 808 union radeon_irq_stat_regs { 809 struct r500_irq_stat_regs r500; 810 struct r600_irq_stat_regs r600; 811 struct evergreen_irq_stat_regs evergreen; 812 struct cik_irq_stat_regs cik; 813 }; 814 815 struct radeon_irq { 816 bool installed; 817 struct lock lock; 818 atomic_t ring_int[RADEON_NUM_RINGS]; 819 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 820 atomic_t pflip[RADEON_MAX_CRTCS]; 821 wait_queue_head_t vblank_queue; 822 bool hpd[RADEON_MAX_HPD_PINS]; 823 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 824 union radeon_irq_stat_regs stat_regs; 825 bool dpm_thermal; 826 }; 827 828 int radeon_irq_kms_init(struct radeon_device *rdev); 829 void radeon_irq_kms_fini(struct radeon_device *rdev); 830 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 831 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring); 832 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 833 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 834 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 835 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 836 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 837 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 838 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 839 840 /* 841 * CP & rings. 842 */ 843 844 struct radeon_ib { 845 struct radeon_sa_bo *sa_bo; 846 uint32_t length_dw; 847 uint64_t gpu_addr; 848 uint32_t *ptr; 849 int ring; 850 struct radeon_fence *fence; 851 struct radeon_vm *vm; 852 bool is_const_ib; 853 struct radeon_sync sync; 854 }; 855 856 struct radeon_ring { 857 struct radeon_bo *ring_obj; 858 volatile uint32_t *ring; 859 unsigned rptr_offs; 860 unsigned rptr_save_reg; 861 u64 next_rptr_gpu_addr; 862 volatile u32 *next_rptr_cpu_addr; 863 unsigned wptr; 864 unsigned wptr_old; 865 unsigned ring_size; 866 unsigned ring_free_dw; 867 int count_dw; 868 atomic_t last_rptr; 869 atomic64_t last_activity; 870 uint64_t gpu_addr; 871 uint32_t align_mask; 872 uint32_t ptr_mask; 873 bool ready; 874 u32 nop; 875 u32 idx; 876 u64 last_semaphore_signal_addr; 877 u64 last_semaphore_wait_addr; 878 /* for CIK queues */ 879 u32 me; 880 u32 pipe; 881 u32 queue; 882 struct radeon_bo *mqd_obj; 883 u32 doorbell_index; 884 unsigned wptr_offs; 885 }; 886 887 struct radeon_mec { 888 struct radeon_bo *hpd_eop_obj; 889 u64 hpd_eop_gpu_addr; 890 u32 num_pipe; 891 u32 num_mec; 892 u32 num_queue; 893 }; 894 895 /* 896 * VM 897 */ 898 899 /* maximum number of VMIDs */ 900 #define RADEON_NUM_VM 16 901 902 /* number of entries in page table */ 903 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) 904 905 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 906 #define RADEON_VM_PTB_ALIGN_SIZE 32768 907 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 908 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 909 910 #define R600_PTE_VALID (1 << 0) 911 #define R600_PTE_SYSTEM (1 << 1) 912 #define R600_PTE_SNOOPED (1 << 2) 913 #define R600_PTE_READABLE (1 << 5) 914 #define R600_PTE_WRITEABLE (1 << 6) 915 916 /* PTE (Page Table Entry) fragment field for different page sizes */ 917 #define R600_PTE_FRAG_4KB (0 << 7) 918 #define R600_PTE_FRAG_64KB (4 << 7) 919 #define R600_PTE_FRAG_256KB (6 << 7) 920 921 /* flags needed to be set so we can copy directly from the GART table */ 922 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ 923 R600_PTE_SYSTEM | R600_PTE_VALID ) 924 925 struct radeon_vm_pt { 926 struct radeon_bo *bo; 927 uint64_t addr; 928 }; 929 930 struct radeon_vm_id { 931 unsigned id; 932 uint64_t pd_gpu_addr; 933 /* last flushed PD/PT update */ 934 struct radeon_fence *flushed_updates; 935 /* last use of vmid */ 936 struct radeon_fence *last_id_use; 937 }; 938 939 struct radeon_vm { 940 struct lock mutex; 941 942 struct rb_root va; 943 944 /* protecting invalidated and freed */ 945 struct spinlock status_lock; 946 947 /* BOs moved, but not yet updated in the PT */ 948 struct list_head invalidated; 949 950 /* BOs freed, but not yet updated in the PT */ 951 struct list_head freed; 952 953 /* BOs cleared in the PT */ 954 struct list_head cleared; 955 956 /* contains the page directory */ 957 struct radeon_bo *page_directory; 958 unsigned max_pde_used; 959 960 /* array of page tables, one for each page directory entry */ 961 struct radeon_vm_pt *page_tables; 962 963 struct radeon_bo_va *ib_bo_va; 964 965 /* for id and flush management per ring */ 966 struct radeon_vm_id ids[RADEON_NUM_RINGS]; 967 }; 968 969 struct radeon_vm_manager { 970 struct radeon_fence *active[RADEON_NUM_VM]; 971 uint32_t max_pfn; 972 /* number of VMIDs */ 973 unsigned nvm; 974 /* vram base address for page table entry */ 975 u64 vram_base_offset; 976 /* is vm enabled? */ 977 bool enabled; 978 /* for hw to save the PD addr on suspend/resume */ 979 uint32_t saved_table_addr[RADEON_NUM_VM]; 980 }; 981 982 /* 983 * file private structure 984 */ 985 struct radeon_fpriv { 986 struct radeon_vm vm; 987 }; 988 989 /* 990 * R6xx+ IH ring 991 */ 992 struct r600_ih { 993 struct radeon_bo *ring_obj; 994 volatile uint32_t *ring; 995 unsigned rptr; 996 unsigned ring_size; 997 uint64_t gpu_addr; 998 uint32_t ptr_mask; 999 atomic_t lock; 1000 bool enabled; 1001 }; 1002 1003 /* 1004 * RLC stuff 1005 */ 1006 #include "clearstate_defs.h" 1007 1008 struct radeon_rlc { 1009 /* for power gating */ 1010 struct radeon_bo *save_restore_obj; 1011 u64 save_restore_gpu_addr; 1012 volatile uint32_t *sr_ptr; 1013 const u32 *reg_list; 1014 u32 reg_list_size; 1015 /* for clear state */ 1016 struct radeon_bo *clear_state_obj; 1017 u64 clear_state_gpu_addr; 1018 volatile uint32_t *cs_ptr; 1019 const struct cs_section_def *cs_data; 1020 u32 clear_state_size; 1021 /* for cp tables */ 1022 struct radeon_bo *cp_table_obj; 1023 u64 cp_table_gpu_addr; 1024 volatile uint32_t *cp_table_ptr; 1025 u32 cp_table_size; 1026 }; 1027 1028 int radeon_ib_get(struct radeon_device *rdev, int ring, 1029 struct radeon_ib *ib, struct radeon_vm *vm, 1030 unsigned size); 1031 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 1032 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 1033 struct radeon_ib *const_ib, bool hdp_flush); 1034 int radeon_ib_pool_init(struct radeon_device *rdev); 1035 void radeon_ib_pool_fini(struct radeon_device *rdev); 1036 int radeon_ib_ring_tests(struct radeon_device *rdev); 1037 /* Ring access between begin & end cannot sleep */ 1038 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 1039 struct radeon_ring *ring); 1040 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 1041 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1042 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1043 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1044 bool hdp_flush); 1045 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1046 bool hdp_flush); 1047 void radeon_ring_undo(struct radeon_ring *ring); 1048 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 1049 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 1050 void radeon_ring_lockup_update(struct radeon_device *rdev, 1051 struct radeon_ring *ring); 1052 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 1053 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 1054 uint32_t **data); 1055 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 1056 unsigned size, uint32_t *data); 1057 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 1058 unsigned rptr_offs, u32 nop); 1059 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 1060 1061 1062 /* r600 async dma */ 1063 void r600_dma_stop(struct radeon_device *rdev); 1064 int r600_dma_resume(struct radeon_device *rdev); 1065 void r600_dma_fini(struct radeon_device *rdev); 1066 1067 void cayman_dma_stop(struct radeon_device *rdev); 1068 int cayman_dma_resume(struct radeon_device *rdev); 1069 void cayman_dma_fini(struct radeon_device *rdev); 1070 1071 /* 1072 * CS. 1073 */ 1074 struct radeon_cs_chunk { 1075 uint32_t length_dw; 1076 uint32_t *kdata; 1077 void __user *user_ptr; 1078 }; 1079 1080 struct radeon_cs_parser { 1081 struct device *dev; 1082 struct radeon_device *rdev; 1083 struct drm_file *filp; 1084 /* chunks */ 1085 unsigned nchunks; 1086 struct radeon_cs_chunk *chunks; 1087 uint64_t *chunks_array; 1088 /* IB */ 1089 unsigned idx; 1090 /* relocations */ 1091 unsigned nrelocs; 1092 struct radeon_bo_list *relocs; 1093 struct radeon_bo_list *vm_bos; 1094 struct list_head validated; 1095 unsigned dma_reloc_idx; 1096 /* indices of various chunks */ 1097 struct radeon_cs_chunk *chunk_ib; 1098 struct radeon_cs_chunk *chunk_relocs; 1099 struct radeon_cs_chunk *chunk_flags; 1100 struct radeon_cs_chunk *chunk_const_ib; 1101 struct radeon_ib ib; 1102 struct radeon_ib const_ib; 1103 void *track; 1104 unsigned family; 1105 int parser_error; 1106 u32 cs_flags; 1107 u32 ring; 1108 s32 priority; 1109 struct ww_acquire_ctx ticket; 1110 }; 1111 1112 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1113 { 1114 struct radeon_cs_chunk *ibc = p->chunk_ib; 1115 1116 if (ibc->kdata) 1117 return ibc->kdata[idx]; 1118 return p->ib.ptr[idx]; 1119 } 1120 1121 1122 struct radeon_cs_packet { 1123 unsigned idx; 1124 unsigned type; 1125 unsigned reg; 1126 unsigned opcode; 1127 int count; 1128 unsigned one_reg_wr; 1129 }; 1130 1131 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1132 struct radeon_cs_packet *pkt, 1133 unsigned idx, unsigned reg); 1134 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 1135 struct radeon_cs_packet *pkt); 1136 1137 1138 /* 1139 * AGP 1140 */ 1141 int radeon_agp_init(struct radeon_device *rdev); 1142 void radeon_agp_resume(struct radeon_device *rdev); 1143 void radeon_agp_suspend(struct radeon_device *rdev); 1144 void radeon_agp_fini(struct radeon_device *rdev); 1145 1146 1147 /* 1148 * Writeback 1149 */ 1150 struct radeon_wb { 1151 struct radeon_bo *wb_obj; 1152 volatile uint32_t *wb; 1153 uint64_t gpu_addr; 1154 bool enabled; 1155 bool use_event; 1156 }; 1157 1158 #define RADEON_WB_SCRATCH_OFFSET 0 1159 #define RADEON_WB_RING0_NEXT_RPTR 256 1160 #define RADEON_WB_CP_RPTR_OFFSET 1024 1161 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1162 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1163 #define R600_WB_DMA_RPTR_OFFSET 1792 1164 #define R600_WB_IH_WPTR_OFFSET 2048 1165 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1166 #define R600_WB_EVENT_OFFSET 3072 1167 #define CIK_WB_CP1_WPTR_OFFSET 3328 1168 #define CIK_WB_CP2_WPTR_OFFSET 3584 1169 #define R600_WB_DMA_RING_TEST_OFFSET 3588 1170 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 1171 1172 /** 1173 * struct radeon_pm - power management datas 1174 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1175 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1176 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1177 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1178 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1179 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1180 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1181 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1182 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1183 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1184 * @needed_bandwidth: current bandwidth needs 1185 * 1186 * It keeps track of various data needed to take powermanagement decision. 1187 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1188 * Equation between gpu/memory clock and available bandwidth is hw dependent 1189 * (type of memory, bus size, efficiency, ...) 1190 */ 1191 1192 enum radeon_pm_method { 1193 PM_METHOD_PROFILE, 1194 PM_METHOD_DYNPM, 1195 PM_METHOD_DPM, 1196 }; 1197 1198 enum radeon_dynpm_state { 1199 DYNPM_STATE_DISABLED, 1200 DYNPM_STATE_MINIMUM, 1201 DYNPM_STATE_PAUSED, 1202 DYNPM_STATE_ACTIVE, 1203 DYNPM_STATE_SUSPENDED, 1204 }; 1205 enum radeon_dynpm_action { 1206 DYNPM_ACTION_NONE, 1207 DYNPM_ACTION_MINIMUM, 1208 DYNPM_ACTION_DOWNCLOCK, 1209 DYNPM_ACTION_UPCLOCK, 1210 DYNPM_ACTION_DEFAULT 1211 }; 1212 1213 enum radeon_voltage_type { 1214 VOLTAGE_NONE = 0, 1215 VOLTAGE_GPIO, 1216 VOLTAGE_VDDC, 1217 VOLTAGE_SW 1218 }; 1219 1220 enum radeon_pm_state_type { 1221 /* not used for dpm */ 1222 POWER_STATE_TYPE_DEFAULT, 1223 POWER_STATE_TYPE_POWERSAVE, 1224 /* user selectable states */ 1225 POWER_STATE_TYPE_BATTERY, 1226 POWER_STATE_TYPE_BALANCED, 1227 POWER_STATE_TYPE_PERFORMANCE, 1228 /* internal states */ 1229 POWER_STATE_TYPE_INTERNAL_UVD, 1230 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1231 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1232 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1233 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1234 POWER_STATE_TYPE_INTERNAL_BOOT, 1235 POWER_STATE_TYPE_INTERNAL_THERMAL, 1236 POWER_STATE_TYPE_INTERNAL_ACPI, 1237 POWER_STATE_TYPE_INTERNAL_ULV, 1238 POWER_STATE_TYPE_INTERNAL_3DPERF, 1239 }; 1240 1241 enum radeon_pm_profile_type { 1242 PM_PROFILE_DEFAULT, 1243 PM_PROFILE_AUTO, 1244 PM_PROFILE_LOW, 1245 PM_PROFILE_MID, 1246 PM_PROFILE_HIGH, 1247 }; 1248 1249 #define PM_PROFILE_DEFAULT_IDX 0 1250 #define PM_PROFILE_LOW_SH_IDX 1 1251 #define PM_PROFILE_MID_SH_IDX 2 1252 #define PM_PROFILE_HIGH_SH_IDX 3 1253 #define PM_PROFILE_LOW_MH_IDX 4 1254 #define PM_PROFILE_MID_MH_IDX 5 1255 #define PM_PROFILE_HIGH_MH_IDX 6 1256 #define PM_PROFILE_MAX 7 1257 1258 struct radeon_pm_profile { 1259 int dpms_off_ps_idx; 1260 int dpms_on_ps_idx; 1261 int dpms_off_cm_idx; 1262 int dpms_on_cm_idx; 1263 }; 1264 1265 enum radeon_int_thermal_type { 1266 THERMAL_TYPE_NONE, 1267 THERMAL_TYPE_EXTERNAL, 1268 THERMAL_TYPE_EXTERNAL_GPIO, 1269 THERMAL_TYPE_RV6XX, 1270 THERMAL_TYPE_RV770, 1271 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1272 THERMAL_TYPE_EVERGREEN, 1273 THERMAL_TYPE_SUMO, 1274 THERMAL_TYPE_NI, 1275 THERMAL_TYPE_SI, 1276 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1277 THERMAL_TYPE_CI, 1278 THERMAL_TYPE_KV, 1279 }; 1280 1281 struct radeon_voltage { 1282 enum radeon_voltage_type type; 1283 /* gpio voltage */ 1284 struct radeon_gpio_rec gpio; 1285 u32 delay; /* delay in usec from voltage drop to sclk change */ 1286 bool active_high; /* voltage drop is active when bit is high */ 1287 /* VDDC voltage */ 1288 u8 vddc_id; /* index into vddc voltage table */ 1289 u8 vddci_id; /* index into vddci voltage table */ 1290 bool vddci_enabled; 1291 /* r6xx+ sw */ 1292 u16 voltage; 1293 /* evergreen+ vddci */ 1294 u16 vddci; 1295 }; 1296 1297 /* clock mode flags */ 1298 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1299 1300 struct radeon_pm_clock_info { 1301 /* memory clock */ 1302 u32 mclk; 1303 /* engine clock */ 1304 u32 sclk; 1305 /* voltage info */ 1306 struct radeon_voltage voltage; 1307 /* standardized clock flags */ 1308 u32 flags; 1309 }; 1310 1311 /* state flags */ 1312 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1313 1314 struct radeon_power_state { 1315 enum radeon_pm_state_type type; 1316 struct radeon_pm_clock_info *clock_info; 1317 /* number of valid clock modes in this power state */ 1318 int num_clock_modes; 1319 struct radeon_pm_clock_info *default_clock_mode; 1320 /* standardized state flags */ 1321 u32 flags; 1322 u32 misc; /* vbios specific flags */ 1323 u32 misc2; /* vbios specific flags */ 1324 int pcie_lanes; /* pcie lanes */ 1325 }; 1326 1327 /* 1328 * Some modes are overclocked by very low value, accept them 1329 */ 1330 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1331 1332 enum radeon_dpm_auto_throttle_src { 1333 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1334 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1335 }; 1336 1337 enum radeon_dpm_event_src { 1338 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1339 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1340 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1341 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1342 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1343 }; 1344 1345 #define RADEON_MAX_VCE_LEVELS 6 1346 1347 enum radeon_vce_level { 1348 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1349 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1350 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1351 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1352 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1353 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1354 }; 1355 1356 struct radeon_ps { 1357 u32 caps; /* vbios flags */ 1358 u32 class; /* vbios flags */ 1359 u32 class2; /* vbios flags */ 1360 /* UVD clocks */ 1361 u32 vclk; 1362 u32 dclk; 1363 /* VCE clocks */ 1364 u32 evclk; 1365 u32 ecclk; 1366 bool vce_active; 1367 enum radeon_vce_level vce_level; 1368 /* asic priv */ 1369 void *ps_priv; 1370 }; 1371 1372 struct radeon_dpm_thermal { 1373 /* thermal interrupt work */ 1374 struct work_struct work; 1375 /* low temperature threshold */ 1376 int min_temp; 1377 /* high temperature threshold */ 1378 int max_temp; 1379 /* was interrupt low to high or high to low */ 1380 bool high_to_low; 1381 }; 1382 1383 enum radeon_clk_action 1384 { 1385 RADEON_SCLK_UP = 1, 1386 RADEON_SCLK_DOWN 1387 }; 1388 1389 struct radeon_blacklist_clocks 1390 { 1391 u32 sclk; 1392 u32 mclk; 1393 enum radeon_clk_action action; 1394 }; 1395 1396 struct radeon_clock_and_voltage_limits { 1397 u32 sclk; 1398 u32 mclk; 1399 u16 vddc; 1400 u16 vddci; 1401 }; 1402 1403 struct radeon_clock_array { 1404 u32 count; 1405 u32 *values; 1406 }; 1407 1408 struct radeon_clock_voltage_dependency_entry { 1409 u32 clk; 1410 u16 v; 1411 }; 1412 1413 struct radeon_clock_voltage_dependency_table { 1414 u32 count; 1415 struct radeon_clock_voltage_dependency_entry *entries; 1416 }; 1417 1418 union radeon_cac_leakage_entry { 1419 struct { 1420 u16 vddc; 1421 u32 leakage; 1422 }; 1423 struct { 1424 u16 vddc1; 1425 u16 vddc2; 1426 u16 vddc3; 1427 }; 1428 }; 1429 1430 struct radeon_cac_leakage_table { 1431 u32 count; 1432 union radeon_cac_leakage_entry *entries; 1433 }; 1434 1435 struct radeon_phase_shedding_limits_entry { 1436 u16 voltage; 1437 u32 sclk; 1438 u32 mclk; 1439 }; 1440 1441 struct radeon_phase_shedding_limits_table { 1442 u32 count; 1443 struct radeon_phase_shedding_limits_entry *entries; 1444 }; 1445 1446 struct radeon_uvd_clock_voltage_dependency_entry { 1447 u32 vclk; 1448 u32 dclk; 1449 u16 v; 1450 }; 1451 1452 struct radeon_uvd_clock_voltage_dependency_table { 1453 u8 count; 1454 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1455 }; 1456 1457 struct radeon_vce_clock_voltage_dependency_entry { 1458 u32 ecclk; 1459 u32 evclk; 1460 u16 v; 1461 }; 1462 1463 struct radeon_vce_clock_voltage_dependency_table { 1464 u8 count; 1465 struct radeon_vce_clock_voltage_dependency_entry *entries; 1466 }; 1467 1468 struct radeon_ppm_table { 1469 u8 ppm_design; 1470 u16 cpu_core_number; 1471 u32 platform_tdp; 1472 u32 small_ac_platform_tdp; 1473 u32 platform_tdc; 1474 u32 small_ac_platform_tdc; 1475 u32 apu_tdp; 1476 u32 dgpu_tdp; 1477 u32 dgpu_ulv_power; 1478 u32 tj_max; 1479 }; 1480 1481 struct radeon_cac_tdp_table { 1482 u16 tdp; 1483 u16 configurable_tdp; 1484 u16 tdc; 1485 u16 battery_power_limit; 1486 u16 small_power_limit; 1487 u16 low_cac_leakage; 1488 u16 high_cac_leakage; 1489 u16 maximum_power_delivery_limit; 1490 }; 1491 1492 struct radeon_dpm_dynamic_state { 1493 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1494 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1495 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1496 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1497 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1498 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1499 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1500 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1501 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1502 struct radeon_clock_array valid_sclk_values; 1503 struct radeon_clock_array valid_mclk_values; 1504 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1505 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1506 u32 mclk_sclk_ratio; 1507 u32 sclk_mclk_delta; 1508 u16 vddc_vddci_delta; 1509 u16 min_vddc_for_pcie_gen2; 1510 struct radeon_cac_leakage_table cac_leakage_table; 1511 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1512 struct radeon_ppm_table *ppm_table; 1513 struct radeon_cac_tdp_table *cac_tdp_table; 1514 }; 1515 1516 struct radeon_dpm_fan { 1517 u16 t_min; 1518 u16 t_med; 1519 u16 t_high; 1520 u16 pwm_min; 1521 u16 pwm_med; 1522 u16 pwm_high; 1523 u8 t_hyst; 1524 u32 cycle_delay; 1525 u16 t_max; 1526 u8 control_mode; 1527 u16 default_max_fan_pwm; 1528 u16 default_fan_output_sensitivity; 1529 u16 fan_output_sensitivity; 1530 bool ucode_fan_control; 1531 }; 1532 1533 enum radeon_pcie_gen { 1534 RADEON_PCIE_GEN1 = 0, 1535 RADEON_PCIE_GEN2 = 1, 1536 RADEON_PCIE_GEN3 = 2, 1537 RADEON_PCIE_GEN_INVALID = 0xffff 1538 }; 1539 1540 enum radeon_dpm_forced_level { 1541 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1542 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1543 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1544 }; 1545 1546 struct radeon_vce_state { 1547 /* vce clocks */ 1548 u32 evclk; 1549 u32 ecclk; 1550 /* gpu clocks */ 1551 u32 sclk; 1552 u32 mclk; 1553 u8 clk_idx; 1554 u8 pstate; 1555 }; 1556 1557 struct radeon_dpm { 1558 struct radeon_ps *ps; 1559 /* number of valid power states */ 1560 int num_ps; 1561 /* current power state that is active */ 1562 struct radeon_ps *current_ps; 1563 /* requested power state */ 1564 struct radeon_ps *requested_ps; 1565 /* boot up power state */ 1566 struct radeon_ps *boot_ps; 1567 /* default uvd power state */ 1568 struct radeon_ps *uvd_ps; 1569 /* vce requirements */ 1570 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1571 enum radeon_vce_level vce_level; 1572 enum radeon_pm_state_type state; 1573 enum radeon_pm_state_type user_state; 1574 u32 platform_caps; 1575 u32 voltage_response_time; 1576 u32 backbias_response_time; 1577 void *priv; 1578 u32 new_active_crtcs; 1579 int new_active_crtc_count; 1580 u32 current_active_crtcs; 1581 int current_active_crtc_count; 1582 bool single_display; 1583 struct radeon_dpm_dynamic_state dyn_state; 1584 struct radeon_dpm_fan fan; 1585 u32 tdp_limit; 1586 u32 near_tdp_limit; 1587 u32 near_tdp_limit_adjusted; 1588 u32 sq_ramping_threshold; 1589 u32 cac_leakage; 1590 u16 tdp_od_limit; 1591 u32 tdp_adjustment; 1592 u16 load_line_slope; 1593 bool power_control; 1594 bool ac_power; 1595 /* special states active */ 1596 bool thermal_active; 1597 bool uvd_active; 1598 bool vce_active; 1599 /* thermal handling */ 1600 struct radeon_dpm_thermal thermal; 1601 /* forced levels */ 1602 enum radeon_dpm_forced_level forced_level; 1603 /* track UVD streams */ 1604 unsigned sd; 1605 unsigned hd; 1606 }; 1607 1608 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1609 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1610 1611 struct radeon_pm { 1612 struct lock mutex; 1613 /* write locked while reprogramming mclk */ 1614 struct lock mclk_lock; 1615 u32 active_crtcs; 1616 int active_crtc_count; 1617 int req_vblank; 1618 bool vblank_sync; 1619 fixed20_12 max_bandwidth; 1620 fixed20_12 igp_sideport_mclk; 1621 fixed20_12 igp_system_mclk; 1622 fixed20_12 igp_ht_link_clk; 1623 fixed20_12 igp_ht_link_width; 1624 fixed20_12 k8_bandwidth; 1625 fixed20_12 sideport_bandwidth; 1626 fixed20_12 ht_bandwidth; 1627 fixed20_12 core_bandwidth; 1628 fixed20_12 sclk; 1629 fixed20_12 mclk; 1630 fixed20_12 needed_bandwidth; 1631 struct radeon_power_state *power_state; 1632 /* number of valid power states */ 1633 int num_power_states; 1634 int current_power_state_index; 1635 int current_clock_mode_index; 1636 int requested_power_state_index; 1637 int requested_clock_mode_index; 1638 int default_power_state_index; 1639 u32 current_sclk; 1640 u32 current_mclk; 1641 u16 current_vddc; 1642 u16 current_vddci; 1643 u32 default_sclk; 1644 u32 default_mclk; 1645 u16 default_vddc; 1646 u16 default_vddci; 1647 struct radeon_i2c_chan *i2c_bus; 1648 /* selected pm method */ 1649 enum radeon_pm_method pm_method; 1650 /* dynpm power management */ 1651 struct delayed_work dynpm_idle_work; 1652 enum radeon_dynpm_state dynpm_state; 1653 enum radeon_dynpm_action dynpm_planned_action; 1654 unsigned long dynpm_action_timeout; 1655 bool dynpm_can_upclock; 1656 bool dynpm_can_downclock; 1657 /* profile-based power management */ 1658 enum radeon_pm_profile_type profile; 1659 int profile_index; 1660 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1661 /* internal thermal controller on rv6xx+ */ 1662 enum radeon_int_thermal_type int_thermal_type; 1663 struct ksensor *int_sensor; 1664 struct ksensordev *int_sensordev; 1665 /* fan control parameters */ 1666 bool no_fan; 1667 u8 fan_pulses_per_revolution; 1668 u8 fan_min_rpm; 1669 u8 fan_max_rpm; 1670 /* dpm */ 1671 bool dpm_enabled; 1672 bool sysfs_initialized; 1673 struct radeon_dpm dpm; 1674 }; 1675 1676 int radeon_pm_get_type_index(struct radeon_device *rdev, 1677 enum radeon_pm_state_type ps_type, 1678 int instance); 1679 /* 1680 * UVD 1681 */ 1682 #define RADEON_DEFAULT_UVD_HANDLES 10 1683 #define RADEON_MAX_UVD_HANDLES 30 1684 #define RADEON_UVD_STACK_SIZE (200*1024) 1685 #define RADEON_UVD_HEAP_SIZE (256*1024) 1686 #define RADEON_UVD_SESSION_SIZE (50*1024) 1687 1688 struct radeon_uvd { 1689 bool fw_header_present; 1690 struct radeon_bo *vcpu_bo; 1691 void *cpu_addr; 1692 u64 gpu_addr; 1693 unsigned max_handles; 1694 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1695 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1696 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1697 struct delayed_work idle_work; 1698 }; 1699 1700 int radeon_uvd_init(struct radeon_device *rdev); 1701 void radeon_uvd_fini(struct radeon_device *rdev); 1702 int radeon_uvd_suspend(struct radeon_device *rdev); 1703 int radeon_uvd_resume(struct radeon_device *rdev); 1704 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1705 uint32_t handle, struct radeon_fence **fence); 1706 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1707 uint32_t handle, struct radeon_fence **fence); 1708 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, 1709 uint32_t allowed_domains); 1710 void radeon_uvd_free_handles(struct radeon_device *rdev, 1711 struct drm_file *filp); 1712 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1713 void radeon_uvd_note_usage(struct radeon_device *rdev); 1714 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1715 unsigned vclk, unsigned dclk, 1716 unsigned vco_min, unsigned vco_max, 1717 unsigned fb_factor, unsigned fb_mask, 1718 unsigned pd_min, unsigned pd_max, 1719 unsigned pd_even, 1720 unsigned *optimal_fb_div, 1721 unsigned *optimal_vclk_div, 1722 unsigned *optimal_dclk_div); 1723 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1724 unsigned cg_upll_func_cntl); 1725 1726 /* 1727 * VCE 1728 */ 1729 #define RADEON_MAX_VCE_HANDLES 16 1730 1731 struct radeon_vce { 1732 struct radeon_bo *vcpu_bo; 1733 u64 gpu_addr; 1734 unsigned fw_version; 1735 unsigned fb_version; 1736 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1737 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1738 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1739 struct delayed_work idle_work; 1740 uint32_t keyselect; 1741 }; 1742 1743 int radeon_vce_init(struct radeon_device *rdev); 1744 void radeon_vce_fini(struct radeon_device *rdev); 1745 int radeon_vce_suspend(struct radeon_device *rdev); 1746 int radeon_vce_resume(struct radeon_device *rdev); 1747 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1748 uint32_t handle, struct radeon_fence **fence); 1749 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1750 uint32_t handle, struct radeon_fence **fence); 1751 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1752 void radeon_vce_note_usage(struct radeon_device *rdev); 1753 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1754 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1755 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1756 struct radeon_ring *ring, 1757 struct radeon_semaphore *semaphore, 1758 bool emit_wait); 1759 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1760 void radeon_vce_fence_emit(struct radeon_device *rdev, 1761 struct radeon_fence *fence); 1762 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1763 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1764 1765 struct r600_audio_pin { 1766 int channels; 1767 int rate; 1768 int bits_per_sample; 1769 u8 status_bits; 1770 u8 category_code; 1771 u32 offset; 1772 bool connected; 1773 u32 id; 1774 }; 1775 1776 struct r600_audio { 1777 bool enabled; 1778 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1779 int num_pins; 1780 struct radeon_audio_funcs *hdmi_funcs; 1781 struct radeon_audio_funcs *dp_funcs; 1782 struct radeon_audio_basic_funcs *funcs; 1783 }; 1784 1785 /* 1786 * Benchmarking 1787 */ 1788 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1789 1790 1791 /* 1792 * Testing 1793 */ 1794 void radeon_test_moves(struct radeon_device *rdev); 1795 void radeon_test_ring_sync(struct radeon_device *rdev, 1796 struct radeon_ring *cpA, 1797 struct radeon_ring *cpB); 1798 void radeon_test_syncing(struct radeon_device *rdev); 1799 1800 /* 1801 * MMU Notifier 1802 */ 1803 #if defined(CONFIG_MMU_NOTIFIER) 1804 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr); 1805 void radeon_mn_unregister(struct radeon_bo *bo); 1806 #else 1807 static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr) 1808 { 1809 return -ENODEV; 1810 } 1811 static inline void radeon_mn_unregister(struct radeon_bo *bo) {} 1812 #endif 1813 1814 /* 1815 * Debugfs 1816 */ 1817 struct radeon_debugfs { 1818 struct drm_info_list *files; 1819 unsigned num_files; 1820 }; 1821 1822 int radeon_debugfs_add_files(struct radeon_device *rdev, 1823 struct drm_info_list *files, 1824 unsigned nfiles); 1825 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1826 1827 /* 1828 * ASIC ring specific functions. 1829 */ 1830 struct radeon_asic_ring { 1831 /* ring read/write ptr handling */ 1832 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1833 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1834 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1835 1836 /* validating and patching of IBs */ 1837 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1838 int (*cs_parse)(struct radeon_cs_parser *p); 1839 1840 /* command emmit functions */ 1841 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1842 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1843 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); 1844 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1845 struct radeon_semaphore *semaphore, bool emit_wait); 1846 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring, 1847 unsigned vm_id, uint64_t pd_addr); 1848 1849 /* testing functions */ 1850 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1851 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1852 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1853 1854 /* deprecated */ 1855 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1856 }; 1857 1858 /* 1859 * ASIC specific functions. 1860 */ 1861 struct radeon_asic { 1862 int (*init)(struct radeon_device *rdev); 1863 void (*fini)(struct radeon_device *rdev); 1864 int (*resume)(struct radeon_device *rdev); 1865 int (*suspend)(struct radeon_device *rdev); 1866 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1867 int (*asic_reset)(struct radeon_device *rdev, bool hard); 1868 /* Flush the HDP cache via MMIO */ 1869 void (*mmio_hdp_flush)(struct radeon_device *rdev); 1870 /* check if 3D engine is idle */ 1871 bool (*gui_idle)(struct radeon_device *rdev); 1872 /* wait for mc_idle */ 1873 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1874 /* get the reference clock */ 1875 u32 (*get_xclk)(struct radeon_device *rdev); 1876 /* get the gpu clock counter */ 1877 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1878 /* get register for info ioctl */ 1879 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val); 1880 /* gart */ 1881 struct { 1882 void (*tlb_flush)(struct radeon_device *rdev); 1883 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags); 1884 void (*set_page)(struct radeon_device *rdev, unsigned i, 1885 uint64_t entry); 1886 } gart; 1887 struct { 1888 int (*init)(struct radeon_device *rdev); 1889 void (*fini)(struct radeon_device *rdev); 1890 void (*copy_pages)(struct radeon_device *rdev, 1891 struct radeon_ib *ib, 1892 uint64_t pe, uint64_t src, 1893 unsigned count); 1894 void (*write_pages)(struct radeon_device *rdev, 1895 struct radeon_ib *ib, 1896 uint64_t pe, 1897 uint64_t addr, unsigned count, 1898 uint32_t incr, uint32_t flags); 1899 void (*set_pages)(struct radeon_device *rdev, 1900 struct radeon_ib *ib, 1901 uint64_t pe, 1902 uint64_t addr, unsigned count, 1903 uint32_t incr, uint32_t flags); 1904 void (*pad_ib)(struct radeon_ib *ib); 1905 } vm; 1906 /* ring specific callbacks */ 1907 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1908 /* irqs */ 1909 struct { 1910 int (*set)(struct radeon_device *rdev); 1911 irqreturn_t (*process)(struct radeon_device *rdev); 1912 } irq; 1913 /* displays */ 1914 struct { 1915 /* display watermarks */ 1916 void (*bandwidth_update)(struct radeon_device *rdev); 1917 /* get frame count */ 1918 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1919 /* wait for vblank */ 1920 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1921 /* set backlight level */ 1922 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1923 /* get backlight level */ 1924 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1925 /* audio callbacks */ 1926 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1927 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1928 } display; 1929 /* copy functions for bo handling */ 1930 struct { 1931 struct radeon_fence *(*blit)(struct radeon_device *rdev, 1932 uint64_t src_offset, 1933 uint64_t dst_offset, 1934 unsigned num_gpu_pages, 1935 struct reservation_object *resv); 1936 u32 blit_ring_index; 1937 struct radeon_fence *(*dma)(struct radeon_device *rdev, 1938 uint64_t src_offset, 1939 uint64_t dst_offset, 1940 unsigned num_gpu_pages, 1941 struct reservation_object *resv); 1942 u32 dma_ring_index; 1943 /* method used for bo copy */ 1944 struct radeon_fence *(*copy)(struct radeon_device *rdev, 1945 uint64_t src_offset, 1946 uint64_t dst_offset, 1947 unsigned num_gpu_pages, 1948 struct reservation_object *resv); 1949 /* ring used for bo copies */ 1950 u32 copy_ring_index; 1951 } copy; 1952 /* surfaces */ 1953 struct { 1954 int (*set_reg)(struct radeon_device *rdev, int reg, 1955 uint32_t tiling_flags, uint32_t pitch, 1956 uint32_t offset, uint32_t obj_size); 1957 void (*clear_reg)(struct radeon_device *rdev, int reg); 1958 } surface; 1959 /* hotplug detect */ 1960 struct { 1961 void (*init)(struct radeon_device *rdev); 1962 void (*fini)(struct radeon_device *rdev); 1963 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1964 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1965 } hpd; 1966 /* static power management */ 1967 struct { 1968 void (*misc)(struct radeon_device *rdev); 1969 void (*prepare)(struct radeon_device *rdev); 1970 void (*finish)(struct radeon_device *rdev); 1971 void (*init_profile)(struct radeon_device *rdev); 1972 void (*get_dynpm_state)(struct radeon_device *rdev); 1973 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1974 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1975 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1976 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1977 int (*get_pcie_lanes)(struct radeon_device *rdev); 1978 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1979 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1980 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 1981 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 1982 int (*get_temperature)(struct radeon_device *rdev); 1983 } pm; 1984 /* dynamic power management */ 1985 struct { 1986 int (*init)(struct radeon_device *rdev); 1987 void (*setup_asic)(struct radeon_device *rdev); 1988 int (*enable)(struct radeon_device *rdev); 1989 int (*late_enable)(struct radeon_device *rdev); 1990 void (*disable)(struct radeon_device *rdev); 1991 int (*pre_set_power_state)(struct radeon_device *rdev); 1992 int (*set_power_state)(struct radeon_device *rdev); 1993 void (*post_set_power_state)(struct radeon_device *rdev); 1994 void (*display_configuration_changed)(struct radeon_device *rdev); 1995 void (*fini)(struct radeon_device *rdev); 1996 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 1997 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 1998 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 1999 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 2000 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 2001 bool (*vblank_too_short)(struct radeon_device *rdev); 2002 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 2003 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 2004 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode); 2005 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev); 2006 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed); 2007 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed); 2008 u32 (*get_current_sclk)(struct radeon_device *rdev); 2009 u32 (*get_current_mclk)(struct radeon_device *rdev); 2010 } dpm; 2011 /* pageflipping */ 2012 struct { 2013 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async); 2014 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); 2015 } pflip; 2016 }; 2017 2018 /* 2019 * Asic structures 2020 */ 2021 struct r100_asic { 2022 const unsigned *reg_safe_bm; 2023 unsigned reg_safe_bm_size; 2024 u32 hdp_cntl; 2025 }; 2026 2027 struct r300_asic { 2028 const unsigned *reg_safe_bm; 2029 unsigned reg_safe_bm_size; 2030 u32 resync_scratch; 2031 u32 hdp_cntl; 2032 }; 2033 2034 struct r600_asic { 2035 unsigned max_pipes; 2036 unsigned max_tile_pipes; 2037 unsigned max_simds; 2038 unsigned max_backends; 2039 unsigned max_gprs; 2040 unsigned max_threads; 2041 unsigned max_stack_entries; 2042 unsigned max_hw_contexts; 2043 unsigned max_gs_threads; 2044 unsigned sx_max_export_size; 2045 unsigned sx_max_export_pos_size; 2046 unsigned sx_max_export_smx_size; 2047 unsigned sq_num_cf_insts; 2048 unsigned tiling_nbanks; 2049 unsigned tiling_npipes; 2050 unsigned tiling_group_size; 2051 unsigned tile_config; 2052 unsigned backend_map; 2053 unsigned active_simds; 2054 }; 2055 2056 struct rv770_asic { 2057 unsigned max_pipes; 2058 unsigned max_tile_pipes; 2059 unsigned max_simds; 2060 unsigned max_backends; 2061 unsigned max_gprs; 2062 unsigned max_threads; 2063 unsigned max_stack_entries; 2064 unsigned max_hw_contexts; 2065 unsigned max_gs_threads; 2066 unsigned sx_max_export_size; 2067 unsigned sx_max_export_pos_size; 2068 unsigned sx_max_export_smx_size; 2069 unsigned sq_num_cf_insts; 2070 unsigned sx_num_of_sets; 2071 unsigned sc_prim_fifo_size; 2072 unsigned sc_hiz_tile_fifo_size; 2073 unsigned sc_earlyz_tile_fifo_fize; 2074 unsigned tiling_nbanks; 2075 unsigned tiling_npipes; 2076 unsigned tiling_group_size; 2077 unsigned tile_config; 2078 unsigned backend_map; 2079 unsigned active_simds; 2080 }; 2081 2082 struct evergreen_asic { 2083 unsigned num_ses; 2084 unsigned max_pipes; 2085 unsigned max_tile_pipes; 2086 unsigned max_simds; 2087 unsigned max_backends; 2088 unsigned max_gprs; 2089 unsigned max_threads; 2090 unsigned max_stack_entries; 2091 unsigned max_hw_contexts; 2092 unsigned max_gs_threads; 2093 unsigned sx_max_export_size; 2094 unsigned sx_max_export_pos_size; 2095 unsigned sx_max_export_smx_size; 2096 unsigned sq_num_cf_insts; 2097 unsigned sx_num_of_sets; 2098 unsigned sc_prim_fifo_size; 2099 unsigned sc_hiz_tile_fifo_size; 2100 unsigned sc_earlyz_tile_fifo_size; 2101 unsigned tiling_nbanks; 2102 unsigned tiling_npipes; 2103 unsigned tiling_group_size; 2104 unsigned tile_config; 2105 unsigned backend_map; 2106 unsigned active_simds; 2107 }; 2108 2109 struct cayman_asic { 2110 unsigned max_shader_engines; 2111 unsigned max_pipes_per_simd; 2112 unsigned max_tile_pipes; 2113 unsigned max_simds_per_se; 2114 unsigned max_backends_per_se; 2115 unsigned max_texture_channel_caches; 2116 unsigned max_gprs; 2117 unsigned max_threads; 2118 unsigned max_gs_threads; 2119 unsigned max_stack_entries; 2120 unsigned sx_num_of_sets; 2121 unsigned sx_max_export_size; 2122 unsigned sx_max_export_pos_size; 2123 unsigned sx_max_export_smx_size; 2124 unsigned max_hw_contexts; 2125 unsigned sq_num_cf_insts; 2126 unsigned sc_prim_fifo_size; 2127 unsigned sc_hiz_tile_fifo_size; 2128 unsigned sc_earlyz_tile_fifo_size; 2129 2130 unsigned num_shader_engines; 2131 unsigned num_shader_pipes_per_simd; 2132 unsigned num_tile_pipes; 2133 unsigned num_simds_per_se; 2134 unsigned num_backends_per_se; 2135 unsigned backend_disable_mask_per_asic; 2136 unsigned backend_map; 2137 unsigned num_texture_channel_caches; 2138 unsigned mem_max_burst_length_bytes; 2139 unsigned mem_row_size_in_kb; 2140 unsigned shader_engine_tile_size; 2141 unsigned num_gpus; 2142 unsigned multi_gpu_tile_size; 2143 2144 unsigned tile_config; 2145 unsigned active_simds; 2146 }; 2147 2148 struct si_asic { 2149 unsigned max_shader_engines; 2150 unsigned max_tile_pipes; 2151 unsigned max_cu_per_sh; 2152 unsigned max_sh_per_se; 2153 unsigned max_backends_per_se; 2154 unsigned max_texture_channel_caches; 2155 unsigned max_gprs; 2156 unsigned max_gs_threads; 2157 unsigned max_hw_contexts; 2158 unsigned sc_prim_fifo_size_frontend; 2159 unsigned sc_prim_fifo_size_backend; 2160 unsigned sc_hiz_tile_fifo_size; 2161 unsigned sc_earlyz_tile_fifo_size; 2162 2163 unsigned num_tile_pipes; 2164 unsigned backend_enable_mask; 2165 unsigned backend_disable_mask_per_asic; 2166 unsigned backend_map; 2167 unsigned num_texture_channel_caches; 2168 unsigned mem_max_burst_length_bytes; 2169 unsigned mem_row_size_in_kb; 2170 unsigned shader_engine_tile_size; 2171 unsigned num_gpus; 2172 unsigned multi_gpu_tile_size; 2173 2174 unsigned tile_config; 2175 uint32_t tile_mode_array[32]; 2176 uint32_t active_cus; 2177 }; 2178 2179 struct cik_asic { 2180 unsigned max_shader_engines; 2181 unsigned max_tile_pipes; 2182 unsigned max_cu_per_sh; 2183 unsigned max_sh_per_se; 2184 unsigned max_backends_per_se; 2185 unsigned max_texture_channel_caches; 2186 unsigned max_gprs; 2187 unsigned max_gs_threads; 2188 unsigned max_hw_contexts; 2189 unsigned sc_prim_fifo_size_frontend; 2190 unsigned sc_prim_fifo_size_backend; 2191 unsigned sc_hiz_tile_fifo_size; 2192 unsigned sc_earlyz_tile_fifo_size; 2193 2194 unsigned num_tile_pipes; 2195 unsigned backend_enable_mask; 2196 unsigned backend_disable_mask_per_asic; 2197 unsigned backend_map; 2198 unsigned num_texture_channel_caches; 2199 unsigned mem_max_burst_length_bytes; 2200 unsigned mem_row_size_in_kb; 2201 unsigned shader_engine_tile_size; 2202 unsigned num_gpus; 2203 unsigned multi_gpu_tile_size; 2204 2205 unsigned tile_config; 2206 uint32_t tile_mode_array[32]; 2207 uint32_t macrotile_mode_array[16]; 2208 uint32_t active_cus; 2209 }; 2210 2211 union radeon_asic_config { 2212 struct r300_asic r300; 2213 struct r100_asic r100; 2214 struct r600_asic r600; 2215 struct rv770_asic rv770; 2216 struct evergreen_asic evergreen; 2217 struct cayman_asic cayman; 2218 struct si_asic si; 2219 struct cik_asic cik; 2220 }; 2221 2222 /* 2223 * asic initizalization from radeon_asic.c 2224 */ 2225 int radeon_asic_init(struct radeon_device *rdev); 2226 2227 2228 /* 2229 * IOCTL. 2230 */ 2231 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2232 struct drm_file *filp); 2233 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2234 struct drm_file *filp); 2235 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, 2236 struct drm_file *filp); 2237 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2238 struct drm_file *file_priv); 2239 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2240 struct drm_file *file_priv); 2241 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2242 struct drm_file *file_priv); 2243 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 2244 struct drm_file *file_priv); 2245 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2246 struct drm_file *filp); 2247 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2248 struct drm_file *filp); 2249 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2250 struct drm_file *filp); 2251 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2252 struct drm_file *filp); 2253 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2254 struct drm_file *filp); 2255 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2256 struct drm_file *filp); 2257 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2258 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2259 struct drm_file *filp); 2260 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2261 struct drm_file *filp); 2262 2263 /* VRAM scratch page for HDP bug, default vram page */ 2264 struct r600_vram_scratch { 2265 struct radeon_bo *robj; 2266 volatile uint32_t *ptr; 2267 u64 gpu_addr; 2268 }; 2269 2270 /* 2271 * ACPI 2272 */ 2273 struct radeon_atif_notification_cfg { 2274 bool enabled; 2275 int command_code; 2276 }; 2277 2278 struct radeon_atif_notifications { 2279 bool display_switch; 2280 bool expansion_mode_change; 2281 bool thermal_state; 2282 bool forced_power_state; 2283 bool system_power_state; 2284 bool display_conf_change; 2285 bool px_gfx_switch; 2286 bool brightness_change; 2287 bool dgpu_display_event; 2288 }; 2289 2290 struct radeon_atif_functions { 2291 bool system_params; 2292 bool sbios_requests; 2293 bool select_active_disp; 2294 bool lid_state; 2295 bool get_tv_standard; 2296 bool set_tv_standard; 2297 bool get_panel_expansion_mode; 2298 bool set_panel_expansion_mode; 2299 bool temperature_change; 2300 bool graphics_device_types; 2301 }; 2302 2303 struct radeon_atif { 2304 struct radeon_atif_notifications notifications; 2305 struct radeon_atif_functions functions; 2306 struct radeon_atif_notification_cfg notification_cfg; 2307 struct radeon_encoder *encoder_for_bl; 2308 }; 2309 2310 struct radeon_atcs_functions { 2311 bool get_ext_state; 2312 bool pcie_perf_req; 2313 bool pcie_dev_rdy; 2314 bool pcie_bus_width; 2315 }; 2316 2317 struct radeon_atcs { 2318 struct radeon_atcs_functions functions; 2319 }; 2320 2321 /* 2322 * Core structure, functions and helpers. 2323 */ 2324 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2325 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2326 2327 struct radeon_device { 2328 struct device *dev; 2329 struct drm_device *ddev; 2330 struct pci_dev *pdev; 2331 struct lock exclusive_lock; 2332 /* ASIC */ 2333 union radeon_asic_config config; 2334 enum radeon_family family; 2335 unsigned long flags; 2336 int usec_timeout; 2337 enum radeon_pll_errata pll_errata; 2338 int num_gb_pipes; 2339 int num_z_pipes; 2340 int disp_priority; 2341 /* BIOS */ 2342 uint8_t *bios; 2343 bool is_atom_bios; 2344 uint16_t bios_header_start; 2345 struct radeon_bo *stollen_vga_memory; 2346 /* Register mmio */ 2347 resource_size_t rmmio_base; 2348 resource_size_t rmmio_size; 2349 /* protects concurrent MM_INDEX/DATA based register access */ 2350 struct spinlock mmio_idx_lock; 2351 /* protects concurrent SMC based register access */ 2352 struct spinlock smc_idx_lock; 2353 /* protects concurrent PLL register access */ 2354 struct spinlock pll_idx_lock; 2355 /* protects concurrent MC register access */ 2356 struct spinlock mc_idx_lock; 2357 /* protects concurrent PCIE register access */ 2358 struct spinlock pcie_idx_lock; 2359 /* protects concurrent PCIE_PORT register access */ 2360 struct spinlock pciep_idx_lock; 2361 /* protects concurrent PIF register access */ 2362 struct spinlock pif_idx_lock; 2363 /* protects concurrent CG register access */ 2364 struct spinlock cg_idx_lock; 2365 /* protects concurrent UVD register access */ 2366 struct spinlock uvd_idx_lock; 2367 /* protects concurrent RCU register access */ 2368 struct spinlock rcu_idx_lock; 2369 /* protects concurrent DIDT register access */ 2370 struct spinlock didt_idx_lock; 2371 /* protects concurrent ENDPOINT (audio) register access */ 2372 struct spinlock end_idx_lock; 2373 int rmmio_rid; 2374 struct resource *rmmio; 2375 radeon_rreg_t mc_rreg; 2376 radeon_wreg_t mc_wreg; 2377 radeon_rreg_t pll_rreg; 2378 radeon_wreg_t pll_wreg; 2379 uint32_t pcie_reg_mask; 2380 radeon_rreg_t pciep_rreg; 2381 radeon_wreg_t pciep_wreg; 2382 /* io port */ 2383 int rio_rid; 2384 struct resource *rio_mem; 2385 resource_size_t rio_mem_size; 2386 struct radeon_clock clock; 2387 struct radeon_mc mc; 2388 struct radeon_gart gart; 2389 struct radeon_mode_info mode_info; 2390 struct radeon_scratch scratch; 2391 struct radeon_doorbell doorbell; 2392 struct radeon_mman mman; 2393 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2394 wait_queue_head_t fence_queue; 2395 u64 fence_context; 2396 struct lock ring_lock; 2397 struct radeon_ring ring[RADEON_NUM_RINGS]; 2398 bool ib_pool_ready; 2399 struct radeon_sa_manager ring_tmp_bo; 2400 struct radeon_irq irq; 2401 struct radeon_asic *asic; 2402 struct radeon_gem gem; 2403 struct radeon_pm pm; 2404 struct radeon_uvd uvd; 2405 struct radeon_vce vce; 2406 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2407 struct radeon_wb wb; 2408 struct radeon_dummy_page dummy_page; 2409 bool shutdown; 2410 bool need_dma32; 2411 bool accel_working; 2412 bool fastfb_working; /* IGP feature*/ 2413 bool needs_reset, in_reset; 2414 bool fictitious_range_registered; 2415 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2416 const struct firmware *me_fw; /* all family ME firmware */ 2417 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2418 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2419 const struct firmware *mc_fw; /* NI MC firmware */ 2420 const struct firmware *ce_fw; /* SI CE firmware */ 2421 const struct firmware *mec_fw; /* CIK MEC firmware */ 2422 const struct firmware *mec2_fw; /* KV MEC2 firmware */ 2423 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2424 const struct firmware *smc_fw; /* SMC firmware */ 2425 const struct firmware *uvd_fw; /* UVD firmware */ 2426 const struct firmware *vce_fw; /* VCE firmware */ 2427 bool new_fw; 2428 struct r600_vram_scratch vram_scratch; 2429 int msi_enabled; /* msi enabled */ 2430 struct r600_ih ih; /* r6/700 interrupt ring */ 2431 struct radeon_rlc rlc; 2432 struct radeon_mec mec; 2433 struct delayed_work hotplug_work; 2434 struct work_struct dp_work; 2435 struct work_struct audio_work; 2436 int num_crtc; /* number of crtcs */ 2437 struct lock dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2438 bool has_uvd; 2439 bool has_vce; 2440 struct r600_audio audio; /* audio stuff */ 2441 struct { 2442 ACPI_HANDLE handle; 2443 ACPI_NOTIFY_HANDLER notifier_call; 2444 } acpi; 2445 /* only one userspace can use Hyperz features or CMASK at a time */ 2446 struct drm_file *hyperz_filp; 2447 struct drm_file *cmask_filp; 2448 /* i2c buses */ 2449 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2450 /* debugfs */ 2451 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 2452 unsigned debugfs_count; 2453 /* virtual memory */ 2454 struct radeon_vm_manager vm_manager; 2455 struct lock gpu_clock_mutex; 2456 /* memory stats */ 2457 atomic64_t vram_usage; 2458 atomic64_t gtt_usage; 2459 atomic64_t num_bytes_moved; 2460 atomic_t gpu_reset_counter; 2461 /* ACPI interface */ 2462 struct radeon_atif atif; 2463 struct radeon_atcs atcs; 2464 /* srbm instance registers */ 2465 struct lock srbm_mutex; 2466 /* GRBM index mutex. Protects concurrents access to GRBM index */ 2467 struct lock grbm_idx_mutex; 2468 /* clock, powergating flags */ 2469 u32 cg_flags; 2470 u32 pg_flags; 2471 2472 #ifdef PM_TODO 2473 struct dev_pm_domain vga_pm_domain; 2474 #endif 2475 bool have_disp_power_ref; 2476 u32 px_quirk_flags; 2477 2478 /* tracking pinned memory */ 2479 u64 vram_pin_size; 2480 u64 gart_pin_size; 2481 2482 /* amdkfd interface */ 2483 struct kfd_dev *kfd; 2484 2485 struct lock mn_lock; 2486 DECLARE_HASHTABLE(mn_hash, 7); 2487 }; 2488 2489 bool radeon_is_px(struct drm_device *dev); 2490 int radeon_device_init(struct radeon_device *rdev, 2491 struct drm_device *ddev, 2492 struct pci_dev *pdev, 2493 uint32_t flags); 2494 void radeon_device_fini(struct radeon_device *rdev); 2495 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2496 2497 #define RADEON_MIN_MMIO_SIZE 0x10000 2498 2499 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg); 2500 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2501 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2502 bool always_indirect) 2503 { 2504 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ 2505 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2506 return bus_read_4(rdev->rmmio, reg); 2507 else 2508 return r100_mm_rreg_slow(rdev, reg); 2509 } 2510 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2511 bool always_indirect) 2512 { 2513 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2514 bus_write_4(rdev->rmmio, reg, v); 2515 else 2516 r100_mm_wreg_slow(rdev, reg, v); 2517 } 2518 2519 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2520 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2521 2522 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2523 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2524 2525 /* 2526 * Cast helper 2527 */ 2528 extern const struct fence_ops radeon_fence_ops; 2529 2530 static inline struct radeon_fence *to_radeon_fence(struct fence *f) 2531 { 2532 struct radeon_fence *__f = container_of(f, struct radeon_fence, base); 2533 2534 if (__f->base.ops == &radeon_fence_ops) 2535 return __f; 2536 2537 return NULL; 2538 } 2539 2540 /* 2541 * Registers read & write functions. 2542 */ 2543 #define RREG8(reg) bus_read_1((rdev->rmmio), (reg)) 2544 #define WREG8(reg, v) bus_write_1((rdev->rmmio), (reg), v) 2545 #define RREG16(reg) bus_read_2((rdev->rmmio), (reg)) 2546 #define WREG16(reg, v) bus_write_2((rdev->rmmio), (reg), v) 2547 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2548 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2549 #define DREG32(reg) DRM_INFO("REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) 2550 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2551 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2552 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2553 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2554 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2555 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2556 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2557 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2558 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2559 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2560 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2561 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2562 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2563 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2564 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2565 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2566 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2567 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2568 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2569 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2570 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2571 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2572 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2573 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2574 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2575 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2576 #define WREG32_P(reg, val, mask) \ 2577 do { \ 2578 uint32_t tmp_ = RREG32(reg); \ 2579 tmp_ &= (mask); \ 2580 tmp_ |= ((val) & ~(mask)); \ 2581 WREG32(reg, tmp_); \ 2582 } while (0) 2583 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2584 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2585 #define WREG32_PLL_P(reg, val, mask) \ 2586 do { \ 2587 uint32_t tmp_ = RREG32_PLL(reg); \ 2588 tmp_ &= (mask); \ 2589 tmp_ |= ((val) & ~(mask)); \ 2590 WREG32_PLL(reg, tmp_); \ 2591 } while (0) 2592 #define WREG32_SMC_P(reg, val, mask) \ 2593 do { \ 2594 uint32_t tmp_ = RREG32_SMC(reg); \ 2595 tmp_ &= (mask); \ 2596 tmp_ |= ((val) & ~(mask)); \ 2597 WREG32_SMC(reg, tmp_); \ 2598 } while (0) 2599 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2600 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2601 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2602 2603 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2604 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2605 2606 /* 2607 * Indirect registers accessors. 2608 * They used to be inlined, but this increases code size by ~65 kbytes. 2609 * Since each performs a pair of MMIO ops 2610 * within a spin_lock_irqsave/spin_unlock_irqrestore region, 2611 * the cost of call+ret is almost negligible. MMIO and locking 2612 * costs several dozens of cycles each at best, call+ret is ~5 cycles. 2613 */ 2614 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); 2615 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2616 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg); 2617 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2618 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg); 2619 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2620 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg); 2621 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2622 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg); 2623 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2624 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg); 2625 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2626 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg); 2627 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2628 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg); 2629 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2630 2631 void r100_pll_errata_after_index(struct radeon_device *rdev); 2632 2633 2634 /* 2635 * ASICs helpers. 2636 */ 2637 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2638 (rdev->pdev->device == 0x5969)) 2639 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2640 (rdev->family == CHIP_RV200) || \ 2641 (rdev->family == CHIP_RS100) || \ 2642 (rdev->family == CHIP_RS200) || \ 2643 (rdev->family == CHIP_RV250) || \ 2644 (rdev->family == CHIP_RV280) || \ 2645 (rdev->family == CHIP_RS300)) 2646 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2647 (rdev->family == CHIP_RV350) || \ 2648 (rdev->family == CHIP_R350) || \ 2649 (rdev->family == CHIP_RV380) || \ 2650 (rdev->family == CHIP_R420) || \ 2651 (rdev->family == CHIP_R423) || \ 2652 (rdev->family == CHIP_RV410) || \ 2653 (rdev->family == CHIP_RS400) || \ 2654 (rdev->family == CHIP_RS480)) 2655 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 2656 (rdev->ddev->pdev->device == 0x9443) || \ 2657 (rdev->ddev->pdev->device == 0x944B) || \ 2658 (rdev->ddev->pdev->device == 0x9506) || \ 2659 (rdev->ddev->pdev->device == 0x9509) || \ 2660 (rdev->ddev->pdev->device == 0x950F) || \ 2661 (rdev->ddev->pdev->device == 0x689C) || \ 2662 (rdev->ddev->pdev->device == 0x689D)) 2663 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2664 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2665 (rdev->family == CHIP_RS690) || \ 2666 (rdev->family == CHIP_RS740) || \ 2667 (rdev->family >= CHIP_R600)) 2668 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2669 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2670 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2671 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2672 (rdev->flags & RADEON_IS_IGP)) 2673 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2674 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2675 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2676 (rdev->flags & RADEON_IS_IGP)) 2677 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2678 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2679 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2680 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2681 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2682 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2683 (rdev->family == CHIP_MULLINS)) 2684 2685 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ 2686 (rdev->ddev->pdev->device == 0x6850) || \ 2687 (rdev->ddev->pdev->device == 0x6858) || \ 2688 (rdev->ddev->pdev->device == 0x6859) || \ 2689 (rdev->ddev->pdev->device == 0x6840) || \ 2690 (rdev->ddev->pdev->device == 0x6841) || \ 2691 (rdev->ddev->pdev->device == 0x6842) || \ 2692 (rdev->ddev->pdev->device == 0x6843)) 2693 2694 /* 2695 * BIOS helpers. 2696 */ 2697 #define RBIOS8(i) (rdev->bios[i]) 2698 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2699 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2700 2701 int radeon_combios_init(struct radeon_device *rdev); 2702 void radeon_combios_fini(struct radeon_device *rdev); 2703 int radeon_atombios_init(struct radeon_device *rdev); 2704 void radeon_atombios_fini(struct radeon_device *rdev); 2705 2706 2707 /* 2708 * RING helpers. 2709 */ 2710 2711 /** 2712 * radeon_ring_write - write a value to the ring 2713 * 2714 * @ring: radeon_ring structure holding ring information 2715 * @v: dword (dw) value to write 2716 * 2717 * Write a value to the requested ring buffer (all asics). 2718 */ 2719 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2720 { 2721 if (ring->count_dw <= 0) 2722 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); 2723 2724 ring->ring[ring->wptr++] = v; 2725 ring->wptr &= ring->ptr_mask; 2726 ring->count_dw--; 2727 ring->ring_free_dw--; 2728 } 2729 2730 /* 2731 * ASICs macro. 2732 */ 2733 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2734 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2735 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2736 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2737 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2738 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2739 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false) 2740 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2741 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f)) 2742 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e)) 2743 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2744 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2745 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) 2746 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2747 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2748 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) 2749 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2750 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2751 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2752 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2753 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2754 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2755 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr)) 2756 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2757 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2758 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2759 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2760 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2761 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2762 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2763 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2764 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2765 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2766 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2767 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2768 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv)) 2769 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv)) 2770 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv)) 2771 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2772 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2773 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2774 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2775 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2776 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2777 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2778 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2779 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2780 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2781 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2782 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2783 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2784 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2785 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2786 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2787 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2788 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2789 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2790 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2791 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2792 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2793 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2794 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2795 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2796 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2797 #define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async)) 2798 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) 2799 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2800 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2801 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2802 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2803 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v)) 2804 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2805 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2806 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2807 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2808 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2809 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2810 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2811 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2812 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2813 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2814 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2815 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2816 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2817 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2818 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2819 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2820 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2821 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2822 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev)) 2823 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev)) 2824 2825 /* Common functions */ 2826 /* AGP */ 2827 extern int radeon_gpu_reset(struct radeon_device *rdev); 2828 extern void radeon_pci_config_reset(struct radeon_device *rdev); 2829 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2830 extern void radeon_agp_disable(struct radeon_device *rdev); 2831 extern int radeon_modeset_init(struct radeon_device *rdev); 2832 extern void radeon_modeset_fini(struct radeon_device *rdev); 2833 extern bool radeon_card_posted(struct radeon_device *rdev); 2834 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2835 extern void radeon_update_display_priority(struct radeon_device *rdev); 2836 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2837 extern void radeon_scratch_init(struct radeon_device *rdev); 2838 extern void radeon_wb_fini(struct radeon_device *rdev); 2839 extern int radeon_wb_init(struct radeon_device *rdev); 2840 extern void radeon_wb_disable(struct radeon_device *rdev); 2841 extern void radeon_surface_init(struct radeon_device *rdev); 2842 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2843 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2844 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2845 extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2846 uint32_t flags); 2847 extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm); 2848 extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm); 2849 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2850 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2851 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2852 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, 2853 bool fbcon, bool freeze); 2854 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2855 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2856 const u32 *registers, 2857 const u32 array_size); 2858 2859 /* 2860 * vm 2861 */ 2862 int radeon_vm_manager_init(struct radeon_device *rdev); 2863 void radeon_vm_manager_fini(struct radeon_device *rdev); 2864 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2865 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2866 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, 2867 struct radeon_vm *vm, 2868 struct list_head *head); 2869 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2870 struct radeon_vm *vm, int ring); 2871 void radeon_vm_flush(struct radeon_device *rdev, 2872 struct radeon_vm *vm, 2873 int ring, struct radeon_fence *fence); 2874 void radeon_vm_fence(struct radeon_device *rdev, 2875 struct radeon_vm *vm, 2876 struct radeon_fence *fence); 2877 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2878 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2879 struct radeon_vm *vm); 2880 int radeon_vm_clear_freed(struct radeon_device *rdev, 2881 struct radeon_vm *vm); 2882 int radeon_vm_clear_invalids(struct radeon_device *rdev, 2883 struct radeon_vm *vm); 2884 int radeon_vm_bo_update(struct radeon_device *rdev, 2885 struct radeon_bo_va *bo_va, 2886 struct ttm_mem_reg *mem); 2887 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2888 struct radeon_bo *bo); 2889 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2890 struct radeon_bo *bo); 2891 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2892 struct radeon_vm *vm, 2893 struct radeon_bo *bo); 2894 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2895 struct radeon_bo_va *bo_va, 2896 uint64_t offset, 2897 uint32_t flags); 2898 void radeon_vm_bo_rmv(struct radeon_device *rdev, 2899 struct radeon_bo_va *bo_va); 2900 2901 /* audio */ 2902 void r600_audio_update_hdmi(struct work_struct *work); 2903 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2904 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2905 void r600_audio_enable(struct radeon_device *rdev, 2906 struct r600_audio_pin *pin, 2907 u8 enable_mask); 2908 void dce6_audio_enable(struct radeon_device *rdev, 2909 struct r600_audio_pin *pin, 2910 u8 enable_mask); 2911 2912 /* 2913 * R600 vram scratch functions 2914 */ 2915 int r600_vram_scratch_init(struct radeon_device *rdev); 2916 void r600_vram_scratch_fini(struct radeon_device *rdev); 2917 2918 /* 2919 * r600 cs checking helper 2920 */ 2921 unsigned r600_mip_minify(unsigned size, unsigned level); 2922 bool r600_fmt_is_valid_color(u32 format); 2923 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2924 int r600_fmt_get_blocksize(u32 format); 2925 int r600_fmt_get_nblocksx(u32 format, u32 w); 2926 int r600_fmt_get_nblocksy(u32 format, u32 h); 2927 2928 /* 2929 * r600 functions used by radeon_encoder.c 2930 */ 2931 struct radeon_hdmi_acr { 2932 u32 clock; 2933 2934 int n_32khz; 2935 int cts_32khz; 2936 2937 int n_44_1khz; 2938 int cts_44_1khz; 2939 2940 int n_48khz; 2941 int cts_48khz; 2942 2943 }; 2944 2945 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 2946 2947 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 2948 u32 tiling_pipe_num, 2949 u32 max_rb_num, 2950 u32 total_max_rb_num, 2951 u32 enabled_rb_mask); 2952 2953 /* 2954 * evergreen functions used by radeon_encoder.c 2955 */ 2956 2957 extern int ni_init_microcode(struct radeon_device *rdev); 2958 extern int ni_mc_load_microcode(struct radeon_device *rdev); 2959 extern void ni_fini_microcode(struct radeon_device *rdev); 2960 2961 /* radeon_acpi.c */ 2962 extern int radeon_acpi_init(struct radeon_device *rdev); 2963 extern void radeon_acpi_fini(struct radeon_device *rdev); 2964 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 2965 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 2966 u8 perf_req, bool advertise); 2967 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 2968 2969 /* Prototypes added by @dumbbell. */ 2970 2971 /* atombios_encoders.c */ 2972 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 2973 struct drm_connector *drm_connector); 2974 void radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, 2975 uint32_t supported_device, u16 caps); 2976 2977 /* radeon_atombios.c */ 2978 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 2979 struct drm_display_mode *mode); 2980 2981 /* radeon_legacy_encoders.c */ 2982 void radeon_add_legacy_encoder(struct drm_device *dev, 2983 uint32_t encoder_enum, uint32_t supported_device); 2984 void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder, 2985 struct drm_connector *drm_connector); 2986 2987 /* radeon_pm.c */ 2988 void radeon_pm_acpi_event_handler(struct radeon_device *rdev); 2989 2990 /* radeon_ttm.c */ 2991 int radeon_ttm_init(struct radeon_device *rdev); 2992 void radeon_ttm_fini(struct radeon_device *rdev); 2993 2994 /* r600.c */ 2995 int r600_ih_ring_alloc(struct radeon_device *rdev); 2996 void r600_ih_ring_fini(struct radeon_device *rdev); 2997 2998 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 2999 struct radeon_cs_packet *pkt, 3000 unsigned idx); 3001 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 3002 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 3003 struct radeon_cs_packet *pkt); 3004 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 3005 struct radeon_bo_list **cs_reloc, 3006 int nomm); 3007 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 3008 uint32_t *vline_start_end, 3009 uint32_t *vline_status); 3010 3011 #include "radeon_object.h" 3012 3013 #endif 3014