1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #ifndef __RADEON_H__ 30 #define __RADEON_H__ 31 32 /* TODO: Here are things that needs to be done : 33 * - surface allocator & initializer : (bit like scratch reg) should 34 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 35 * related to surface 36 * - WB : write back stuff (do it bit like scratch reg things) 37 * - Vblank : look at Jesse's rework and what we should do 38 * - r600/r700: gart & cp 39 * - cs : clean cs ioctl use bitmap & things like that. 40 * - power management stuff 41 * - Barrier in gart code 42 * - Unmappabled vram ? 43 * - TESTING, TESTING, TESTING 44 */ 45 46 /* Initialization path: 47 * We expect that acceleration initialization might fail for various 48 * reasons even thought we work hard to make it works on most 49 * configurations. In order to still have a working userspace in such 50 * situation the init path must succeed up to the memory controller 51 * initialization point. Failure before this point are considered as 52 * fatal error. Here is the init callchain : 53 * radeon_device_init perform common structure, mutex initialization 54 * asic_init setup the GPU memory layout and perform all 55 * one time initialization (failure in this 56 * function are considered fatal) 57 * asic_startup setup the GPU acceleration, in order to 58 * follow guideline the first thing this 59 * function should do is setting the GPU 60 * memory controller (only MC setup failure 61 * are considered as fatal) 62 */ 63 64 #include <sys/condvar.h> 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/linker.h> 68 #include <linux/firmware.h> 69 #include <linux/seq_file.h> 70 71 #include <contrib/dev/acpica/source/include/acpi.h> 72 #include <dev/acpica/acpivar.h> 73 74 #include <linux/atomic.h> 75 #include <linux/wait.h> 76 #include <linux/list.h> 77 #include <linux/kref.h> 78 #include <linux/hashtable.h> 79 #include <linux/fence.h> 80 81 #include <drm/ttm/ttm_bo_api.h> 82 #include <drm/ttm/ttm_bo_driver.h> 83 #include <drm/ttm/ttm_placement.h> 84 #include <drm/ttm/ttm_module.h> 85 #include <drm/ttm/ttm_execbuf_util.h> 86 87 #include <drm/drm_gem.h> 88 #define CONFIG_ACPI 1 89 #define __OS_HAS_AGP 0 90 91 #include "radeon_family.h" 92 #include "radeon_mode.h" 93 #include "radeon_reg.h" 94 95 /* 96 * Modules parameters. 97 */ 98 extern int radeon_no_wb; 99 extern int radeon_modeset; 100 extern int radeon_dynclks; 101 extern int radeon_r4xx_atom; 102 extern int radeon_agpmode; 103 extern int radeon_vram_limit; 104 extern int radeon_gart_size; 105 extern int radeon_benchmarking; 106 extern int radeon_testing; 107 extern int radeon_connector_table; 108 extern int radeon_tv; 109 extern int radeon_audio; 110 extern int radeon_disp_priority; 111 extern int radeon_hw_i2c; 112 extern int radeon_pcie_gen2; 113 extern int radeon_msi; 114 extern int radeon_lockup_timeout; 115 extern int radeon_fastfb; 116 extern int radeon_dpm; 117 extern int radeon_aspm; 118 extern int radeon_runtime_pm; 119 extern int radeon_hard_reset; 120 extern int radeon_vm_size; 121 extern int radeon_vm_block_size; 122 extern int radeon_deep_color; 123 extern int radeon_use_pflipirq; 124 extern int radeon_bapm; 125 extern int radeon_backlight; 126 127 /* 128 * Copy from radeon_drv.h so we don't have to include both and have conflicting 129 * symbol; 130 */ 131 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 132 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 133 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 134 #define RADEON_IB_POOL_SIZE 16 135 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 136 #define RADEONFB_CONN_LIMIT 4 137 #define RADEON_BIOS_NUM_SCRATCH 8 138 139 /* internal ring indices */ 140 /* r1xx+ has gfx CP ring */ 141 #define RADEON_RING_TYPE_GFX_INDEX 0 142 143 /* cayman has 2 compute CP rings */ 144 #define CAYMAN_RING_TYPE_CP1_INDEX 1 145 #define CAYMAN_RING_TYPE_CP2_INDEX 2 146 147 /* R600+ has an async dma ring */ 148 #define R600_RING_TYPE_DMA_INDEX 3 149 /* cayman add a second async dma ring */ 150 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 151 152 /* R600+ */ 153 #define R600_RING_TYPE_UVD_INDEX 5 154 155 /* TN+ */ 156 #define TN_RING_TYPE_VCE1_INDEX 6 157 #define TN_RING_TYPE_VCE2_INDEX 7 158 159 /* max number of rings */ 160 #define RADEON_NUM_RINGS 8 161 162 /* number of hw syncs before falling back on blocking */ 163 #define RADEON_NUM_SYNCS 4 164 165 /* hardcode those limit for now */ 166 #define RADEON_VA_IB_OFFSET (1 << 20) 167 #define RADEON_VA_RESERVED_SIZE (8 << 20) 168 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 169 170 /* hard reset data */ 171 #define RADEON_ASIC_RESET_DATA 0x39d5e86b 172 173 /* reset flags */ 174 #define RADEON_RESET_GFX (1 << 0) 175 #define RADEON_RESET_COMPUTE (1 << 1) 176 #define RADEON_RESET_DMA (1 << 2) 177 #define RADEON_RESET_CP (1 << 3) 178 #define RADEON_RESET_GRBM (1 << 4) 179 #define RADEON_RESET_DMA1 (1 << 5) 180 #define RADEON_RESET_RLC (1 << 6) 181 #define RADEON_RESET_SEM (1 << 7) 182 #define RADEON_RESET_IH (1 << 8) 183 #define RADEON_RESET_VMC (1 << 9) 184 #define RADEON_RESET_MC (1 << 10) 185 #define RADEON_RESET_DISPLAY (1 << 11) 186 187 /* CG block flags */ 188 #define RADEON_CG_BLOCK_GFX (1 << 0) 189 #define RADEON_CG_BLOCK_MC (1 << 1) 190 #define RADEON_CG_BLOCK_SDMA (1 << 2) 191 #define RADEON_CG_BLOCK_UVD (1 << 3) 192 #define RADEON_CG_BLOCK_VCE (1 << 4) 193 #define RADEON_CG_BLOCK_HDP (1 << 5) 194 #define RADEON_CG_BLOCK_BIF (1 << 6) 195 196 /* CG flags */ 197 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 198 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 199 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 200 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 201 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 202 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 203 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 204 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 205 #define RADEON_CG_SUPPORT_MC_LS (1 << 8) 206 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 207 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 208 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 209 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 210 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 211 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 212 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 213 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 214 215 /* PG flags */ 216 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 217 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 218 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 219 #define RADEON_PG_SUPPORT_UVD (1 << 3) 220 #define RADEON_PG_SUPPORT_VCE (1 << 4) 221 #define RADEON_PG_SUPPORT_CP (1 << 5) 222 #define RADEON_PG_SUPPORT_GDS (1 << 6) 223 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 224 #define RADEON_PG_SUPPORT_SDMA (1 << 8) 225 #define RADEON_PG_SUPPORT_ACP (1 << 9) 226 #define RADEON_PG_SUPPORT_SAMU (1 << 10) 227 228 /* max cursor sizes (in pixels) */ 229 #define CURSOR_WIDTH 64 230 #define CURSOR_HEIGHT 64 231 232 #define CIK_CURSOR_WIDTH 128 233 #define CIK_CURSOR_HEIGHT 128 234 235 /* 236 * Errata workarounds. 237 */ 238 enum radeon_pll_errata { 239 CHIP_ERRATA_R300_CG = 0x00000001, 240 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 241 CHIP_ERRATA_PLL_DELAY = 0x00000004 242 }; 243 244 245 struct radeon_device; 246 247 248 /* 249 * BIOS. 250 */ 251 bool radeon_get_bios(struct radeon_device *rdev); 252 253 /* 254 * Dummy page 255 */ 256 struct radeon_dummy_page { 257 struct drm_dma_handle *dmah; 258 dma_addr_t addr; 259 }; 260 int radeon_dummy_page_init(struct radeon_device *rdev); 261 void radeon_dummy_page_fini(struct radeon_device *rdev); 262 263 264 /* 265 * Clocks 266 */ 267 struct radeon_clock { 268 struct radeon_pll p1pll; 269 struct radeon_pll p2pll; 270 struct radeon_pll dcpll; 271 struct radeon_pll spll; 272 struct radeon_pll mpll; 273 /* 10 Khz units */ 274 uint32_t default_mclk; 275 uint32_t default_sclk; 276 uint32_t default_dispclk; 277 uint32_t current_dispclk; 278 uint32_t dp_extclk; 279 uint32_t max_pixel_clock; 280 }; 281 282 /* 283 * Power management 284 */ 285 int radeon_pm_init(struct radeon_device *rdev); 286 int radeon_pm_late_init(struct radeon_device *rdev); 287 void radeon_pm_fini(struct radeon_device *rdev); 288 void radeon_pm_compute_clocks(struct radeon_device *rdev); 289 void radeon_pm_suspend(struct radeon_device *rdev); 290 void radeon_pm_resume(struct radeon_device *rdev); 291 void radeon_combios_get_power_modes(struct radeon_device *rdev); 292 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 293 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 294 u8 clock_type, 295 u32 clock, 296 bool strobe_mode, 297 struct atom_clock_dividers *dividers); 298 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 299 u32 clock, 300 bool strobe_mode, 301 struct atom_mpll_param *mpll_param); 302 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 303 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 304 u16 voltage_level, u8 voltage_type, 305 u32 *gpio_value, u32 *gpio_mask); 306 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 307 u32 eng_clock, u32 mem_clock); 308 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 309 u8 voltage_type, u16 *voltage_step); 310 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 311 u16 voltage_id, u16 *voltage); 312 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 313 u16 *voltage, 314 u16 leakage_idx); 315 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 316 u16 *leakage_id); 317 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 318 u16 *vddc, u16 *vddci, 319 u16 virtual_voltage_id, 320 u16 vbios_voltage_id); 321 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 322 u16 virtual_voltage_id, 323 u16 *voltage); 324 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 325 u8 voltage_type, 326 u16 nominal_voltage, 327 u16 *true_voltage); 328 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 329 u8 voltage_type, u16 *min_voltage); 330 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 331 u8 voltage_type, u16 *max_voltage); 332 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 333 u8 voltage_type, u8 voltage_mode, 334 struct atom_voltage_table *voltage_table); 335 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 336 u8 voltage_type, u8 voltage_mode); 337 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 338 u8 voltage_type, 339 u8 *svd_gpio_id, u8 *svc_gpio_id); 340 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 341 u32 mem_clock); 342 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 343 u32 mem_clock); 344 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 345 u8 module_index, 346 struct atom_mc_reg_table *reg_table); 347 int radeon_atom_get_memory_info(struct radeon_device *rdev, 348 u8 module_index, struct atom_memory_info *mem_info); 349 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 350 bool gddr5, u8 module_index, 351 struct atom_memory_clock_range_table *mclk_range_table); 352 void rs690_pm_info(struct radeon_device *rdev); 353 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 354 unsigned *bankh, unsigned *mtaspect, 355 unsigned *tile_split); 356 357 /* 358 * Fences. 359 */ 360 struct radeon_fence_driver { 361 struct radeon_device *rdev; 362 uint32_t scratch_reg; 363 uint64_t gpu_addr; 364 volatile uint32_t *cpu_addr; 365 /* sync_seq is protected by ring emission lock */ 366 uint64_t sync_seq[RADEON_NUM_RINGS]; 367 atomic64_t last_seq; 368 bool initialized; 369 struct delayed_work lockup_work; 370 }; 371 372 struct radeon_fence { 373 struct radeon_device *rdev; 374 unsigned int kref; 375 /* protected by radeon_fence.lock */ 376 uint64_t seq; 377 /* RB, DMA, etc. */ 378 unsigned ring; 379 }; 380 381 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 382 int radeon_fence_driver_init(struct radeon_device *rdev); 383 void radeon_fence_driver_fini(struct radeon_device *rdev); 384 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); 385 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 386 void radeon_fence_process(struct radeon_device *rdev, int ring); 387 bool radeon_fence_signaled(struct radeon_fence *fence); 388 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 389 int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 390 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 391 int radeon_fence_wait_any(struct radeon_device *rdev, 392 struct radeon_fence **fences, 393 bool intr); 394 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 395 void radeon_fence_unref(struct radeon_fence **fence); 396 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 397 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 398 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 399 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 400 struct radeon_fence *b) 401 { 402 if (!a) { 403 return b; 404 } 405 406 if (!b) { 407 return a; 408 } 409 410 BUG_ON(a->ring != b->ring); 411 412 if (a->seq > b->seq) { 413 return a; 414 } else { 415 return b; 416 } 417 } 418 419 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 420 struct radeon_fence *b) 421 { 422 if (!a) { 423 return false; 424 } 425 426 if (!b) { 427 return true; 428 } 429 430 BUG_ON(a->ring != b->ring); 431 432 return a->seq < b->seq; 433 } 434 435 /* 436 * Tiling registers 437 */ 438 struct radeon_surface_reg { 439 struct radeon_bo *bo; 440 }; 441 442 #define RADEON_GEM_MAX_SURFACES 8 443 444 /* 445 * TTM. 446 */ 447 struct radeon_mman { 448 struct ttm_bo_global_ref bo_global_ref; 449 struct drm_global_reference mem_global_ref; 450 struct ttm_bo_device bdev; 451 bool mem_global_referenced; 452 bool initialized; 453 454 #if defined(CONFIG_DEBUG_FS) 455 struct dentry *vram; 456 struct dentry *gtt; 457 #endif 458 }; 459 460 /* bo virtual address in a specific vm */ 461 struct radeon_bo_va { 462 /* protected by bo being reserved */ 463 struct list_head bo_list; 464 uint64_t soffset; 465 uint64_t eoffset; 466 uint32_t flags; 467 uint64_t addr; 468 unsigned ref_count; 469 470 /* protected by vm mutex */ 471 struct list_head vm_list; 472 struct list_head vm_status; 473 474 /* constant after initialization */ 475 struct radeon_vm *vm; 476 struct radeon_bo *bo; 477 }; 478 479 struct radeon_bo { 480 /* Protected by gem.mutex */ 481 struct list_head list; 482 /* Protected by tbo.reserved */ 483 u32 initial_domain; 484 struct ttm_place placements[3]; 485 struct ttm_placement placement; 486 struct ttm_buffer_object tbo; 487 struct ttm_bo_kmap_obj kmap; 488 u32 flags; 489 unsigned pin_count; 490 void *kptr; 491 u32 tiling_flags; 492 u32 pitch; 493 int surface_reg; 494 /* list of all virtual address to which this bo 495 * is associated to 496 */ 497 struct list_head va; 498 /* Constant after initialization */ 499 struct radeon_device *rdev; 500 struct drm_gem_object gem_base; 501 502 struct ttm_bo_kmap_obj dma_buf_vmap; 503 pid_t pid; 504 }; 505 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 506 507 int radeon_gem_debugfs_init(struct radeon_device *rdev); 508 509 /* sub-allocation manager, it has to be protected by another lock. 510 * By conception this is an helper for other part of the driver 511 * like the indirect buffer or semaphore, which both have their 512 * locking. 513 * 514 * Principe is simple, we keep a list of sub allocation in offset 515 * order (first entry has offset == 0, last entry has the highest 516 * offset). 517 * 518 * When allocating new object we first check if there is room at 519 * the end total_size - (last_object_offset + last_object_size) >= 520 * alloc_size. If so we allocate new object there. 521 * 522 * When there is not enough room at the end, we start waiting for 523 * each sub object until we reach object_offset+object_size >= 524 * alloc_size, this object then become the sub object we return. 525 * 526 * Alignment can't be bigger than page size. 527 * 528 * Hole are not considered for allocation to keep things simple. 529 * Assumption is that there won't be hole (all object on same 530 * alignment). 531 */ 532 struct radeon_sa_manager { 533 struct cv wq; 534 struct lock wq_lock; 535 struct radeon_bo *bo; 536 struct list_head *hole; 537 struct list_head flist[RADEON_NUM_RINGS]; 538 struct list_head olist; 539 unsigned size; 540 u64 gpu_addr; 541 void *cpu_ptr; 542 uint32_t domain; 543 uint32_t align; 544 }; 545 546 struct radeon_sa_bo; 547 548 /* sub-allocation buffer */ 549 struct radeon_sa_bo { 550 struct list_head olist; 551 struct list_head flist; 552 struct radeon_sa_manager *manager; 553 unsigned soffset; 554 unsigned eoffset; 555 struct radeon_fence *fence; 556 }; 557 558 /* 559 * GEM objects. 560 */ 561 struct radeon_gem { 562 struct lock mutex; 563 struct list_head objects; 564 }; 565 566 int radeon_gem_init(struct radeon_device *rdev); 567 void radeon_gem_fini(struct radeon_device *rdev); 568 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, 569 int alignment, int initial_domain, 570 u32 flags, bool kernel, 571 struct drm_gem_object **obj); 572 573 int radeon_mode_dumb_create(struct drm_file *file_priv, 574 struct drm_device *dev, 575 struct drm_mode_create_dumb *args); 576 int radeon_mode_dumb_mmap(struct drm_file *filp, 577 struct drm_device *dev, 578 uint32_t handle, uint64_t *offset_p); 579 580 /* 581 * Semaphores. 582 */ 583 struct radeon_semaphore { 584 struct radeon_sa_bo *sa_bo; 585 signed waiters; 586 uint64_t gpu_addr; 587 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 588 }; 589 590 int radeon_semaphore_create(struct radeon_device *rdev, 591 struct radeon_semaphore **semaphore); 592 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 593 struct radeon_semaphore *semaphore); 594 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 595 struct radeon_semaphore *semaphore); 596 void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore, 597 struct radeon_fence *fence); 598 int radeon_semaphore_sync_rings(struct radeon_device *rdev, 599 struct radeon_semaphore *semaphore, 600 int waiting_ring); 601 void radeon_semaphore_free(struct radeon_device *rdev, 602 struct radeon_semaphore **semaphore, 603 struct radeon_fence *fence); 604 605 /* 606 * GART structures, functions & helpers 607 */ 608 struct radeon_mc; 609 610 #define RADEON_GPU_PAGE_SIZE 4096 611 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 612 #define RADEON_GPU_PAGE_SHIFT 12 613 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 614 615 #define RADEON_GART_PAGE_DUMMY 0 616 #define RADEON_GART_PAGE_VALID (1 << 0) 617 #define RADEON_GART_PAGE_READ (1 << 1) 618 #define RADEON_GART_PAGE_WRITE (1 << 2) 619 #define RADEON_GART_PAGE_SNOOP (1 << 3) 620 621 struct radeon_gart { 622 struct drm_dma_handle *dmah; 623 dma_addr_t table_addr; 624 struct radeon_bo *robj; 625 void *ptr; 626 unsigned num_gpu_pages; 627 unsigned num_cpu_pages; 628 unsigned table_size; 629 vm_page_t *pages; 630 dma_addr_t *pages_addr; 631 bool ready; 632 }; 633 634 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 635 void radeon_gart_table_ram_free(struct radeon_device *rdev); 636 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 637 void radeon_gart_table_vram_free(struct radeon_device *rdev); 638 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 639 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 640 int radeon_gart_init(struct radeon_device *rdev); 641 void radeon_gart_fini(struct radeon_device *rdev); 642 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 643 int pages); 644 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 645 int pages, vm_page_t *pagelist, 646 dma_addr_t *dma_addr, uint32_t flags); 647 648 649 /* 650 * GPU MC structures, functions & helpers 651 */ 652 struct radeon_mc { 653 resource_size_t aper_size; 654 resource_size_t aper_base; 655 resource_size_t agp_base; 656 /* for some chips with <= 32MB we need to lie 657 * about vram size near mc fb location */ 658 u64 mc_vram_size; 659 u64 visible_vram_size; 660 u64 gtt_size; 661 u64 gtt_start; 662 u64 gtt_end; 663 u64 vram_start; 664 u64 vram_end; 665 unsigned vram_width; 666 u64 real_vram_size; 667 int vram_mtrr; 668 bool vram_is_ddr; 669 bool igp_sideport_enabled; 670 u64 gtt_base_align; 671 u64 mc_mask; 672 }; 673 674 bool radeon_combios_sideport_present(struct radeon_device *rdev); 675 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 676 677 /* 678 * GPU scratch registers structures, functions & helpers 679 */ 680 struct radeon_scratch { 681 unsigned num_reg; 682 uint32_t reg_base; 683 bool free[32]; 684 uint32_t reg[32]; 685 }; 686 687 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 688 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 689 690 /* 691 * GPU doorbell structures, functions & helpers 692 */ 693 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 694 695 struct radeon_doorbell { 696 /* doorbell mmio */ 697 resource_size_t base; 698 resource_size_t size; 699 u32 __iomem *ptr; 700 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 701 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)]; 702 }; 703 704 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 705 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 706 707 /* 708 * IRQS. 709 */ 710 711 struct radeon_flip_work { 712 struct work_struct flip_work; 713 struct work_struct unpin_work; 714 struct radeon_device *rdev; 715 int crtc_id; 716 uint64_t base; 717 struct drm_pending_vblank_event *event; 718 struct radeon_bo *old_rbo; 719 struct radeon_fence *fence; 720 }; 721 722 struct r500_irq_stat_regs { 723 u32 disp_int; 724 u32 hdmi0_status; 725 }; 726 727 struct r600_irq_stat_regs { 728 u32 disp_int; 729 u32 disp_int_cont; 730 u32 disp_int_cont2; 731 u32 d1grph_int; 732 u32 d2grph_int; 733 u32 hdmi0_status; 734 u32 hdmi1_status; 735 }; 736 737 struct evergreen_irq_stat_regs { 738 u32 disp_int; 739 u32 disp_int_cont; 740 u32 disp_int_cont2; 741 u32 disp_int_cont3; 742 u32 disp_int_cont4; 743 u32 disp_int_cont5; 744 u32 d1grph_int; 745 u32 d2grph_int; 746 u32 d3grph_int; 747 u32 d4grph_int; 748 u32 d5grph_int; 749 u32 d6grph_int; 750 u32 afmt_status1; 751 u32 afmt_status2; 752 u32 afmt_status3; 753 u32 afmt_status4; 754 u32 afmt_status5; 755 u32 afmt_status6; 756 }; 757 758 struct cik_irq_stat_regs { 759 u32 disp_int; 760 u32 disp_int_cont; 761 u32 disp_int_cont2; 762 u32 disp_int_cont3; 763 u32 disp_int_cont4; 764 u32 disp_int_cont5; 765 u32 disp_int_cont6; 766 u32 d1grph_int; 767 u32 d2grph_int; 768 u32 d3grph_int; 769 u32 d4grph_int; 770 u32 d5grph_int; 771 u32 d6grph_int; 772 }; 773 774 union radeon_irq_stat_regs { 775 struct r500_irq_stat_regs r500; 776 struct r600_irq_stat_regs r600; 777 struct evergreen_irq_stat_regs evergreen; 778 struct cik_irq_stat_regs cik; 779 }; 780 781 struct radeon_irq { 782 bool installed; 783 struct lock lock; 784 atomic_t ring_int[RADEON_NUM_RINGS]; 785 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 786 atomic_t pflip[RADEON_MAX_CRTCS]; 787 wait_queue_head_t vblank_queue; 788 bool hpd[RADEON_MAX_HPD_PINS]; 789 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 790 union radeon_irq_stat_regs stat_regs; 791 bool dpm_thermal; 792 }; 793 794 int radeon_irq_kms_init(struct radeon_device *rdev); 795 void radeon_irq_kms_fini(struct radeon_device *rdev); 796 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 797 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 798 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 799 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 800 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 801 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 802 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 803 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 804 805 /* 806 * CP & rings. 807 */ 808 809 struct radeon_ib { 810 struct radeon_sa_bo *sa_bo; 811 uint32_t length_dw; 812 uint64_t gpu_addr; 813 uint32_t *ptr; 814 int ring; 815 struct radeon_fence *fence; 816 struct radeon_vm *vm; 817 bool is_const_ib; 818 struct radeon_semaphore *semaphore; 819 }; 820 821 struct radeon_ring { 822 struct radeon_bo *ring_obj; 823 volatile uint32_t *ring; 824 unsigned rptr_offs; 825 unsigned rptr_save_reg; 826 u64 next_rptr_gpu_addr; 827 volatile u32 *next_rptr_cpu_addr; 828 unsigned wptr; 829 unsigned wptr_old; 830 unsigned ring_size; 831 unsigned ring_free_dw; 832 int count_dw; 833 atomic_t last_rptr; 834 atomic64_t last_activity; 835 uint64_t gpu_addr; 836 uint32_t align_mask; 837 uint32_t ptr_mask; 838 bool ready; 839 u32 nop; 840 u32 idx; 841 u64 last_semaphore_signal_addr; 842 u64 last_semaphore_wait_addr; 843 /* for CIK queues */ 844 u32 me; 845 u32 pipe; 846 u32 queue; 847 struct radeon_bo *mqd_obj; 848 u32 doorbell_index; 849 unsigned wptr_offs; 850 }; 851 852 struct radeon_mec { 853 struct radeon_bo *hpd_eop_obj; 854 u64 hpd_eop_gpu_addr; 855 u32 num_pipe; 856 u32 num_mec; 857 u32 num_queue; 858 }; 859 860 /* 861 * VM 862 */ 863 864 /* maximum number of VMIDs */ 865 #define RADEON_NUM_VM 16 866 867 /* number of entries in page table */ 868 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) 869 870 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 871 #define RADEON_VM_PTB_ALIGN_SIZE 32768 872 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 873 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 874 875 #define R600_PTE_VALID (1 << 0) 876 #define R600_PTE_SYSTEM (1 << 1) 877 #define R600_PTE_SNOOPED (1 << 2) 878 #define R600_PTE_READABLE (1 << 5) 879 #define R600_PTE_WRITEABLE (1 << 6) 880 881 /* PTE (Page Table Entry) fragment field for different page sizes */ 882 #define R600_PTE_FRAG_4KB (0 << 7) 883 #define R600_PTE_FRAG_64KB (4 << 7) 884 #define R600_PTE_FRAG_256KB (6 << 7) 885 886 /* flags needed to be set so we can copy directly from the GART table */ 887 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ 888 R600_PTE_SYSTEM | R600_PTE_VALID ) 889 890 struct radeon_vm_pt { 891 struct radeon_bo *bo; 892 uint64_t addr; 893 }; 894 895 struct radeon_vm { 896 struct list_head va; 897 unsigned id; 898 899 /* BOs moved, but not yet updated in the PT */ 900 struct list_head invalidated; 901 902 /* BOs freed, but not yet updated in the PT */ 903 struct list_head freed; 904 905 /* contains the page directory */ 906 struct radeon_bo *page_directory; 907 uint64_t pd_gpu_addr; 908 unsigned max_pde_used; 909 910 /* array of page tables, one for each page directory entry */ 911 struct radeon_vm_pt *page_tables; 912 913 struct radeon_bo_va *ib_bo_va; 914 915 struct lock mutex; 916 /* last fence for cs using this vm */ 917 struct radeon_fence *fence; 918 /* last flush or NULL if we still need to flush */ 919 struct radeon_fence *last_flush; 920 /* last use of vmid */ 921 struct radeon_fence *last_id_use; 922 }; 923 924 struct radeon_vm_manager { 925 struct radeon_fence *active[RADEON_NUM_VM]; 926 uint32_t max_pfn; 927 /* number of VMIDs */ 928 unsigned nvm; 929 /* vram base address for page table entry */ 930 u64 vram_base_offset; 931 /* is vm enabled? */ 932 bool enabled; 933 /* for hw to save the PD addr on suspend/resume */ 934 uint32_t saved_table_addr[RADEON_NUM_VM]; 935 }; 936 937 /* 938 * file private structure 939 */ 940 struct radeon_fpriv { 941 struct radeon_vm vm; 942 }; 943 944 /* 945 * R6xx+ IH ring 946 */ 947 struct r600_ih { 948 struct radeon_bo *ring_obj; 949 volatile uint32_t *ring; 950 unsigned rptr; 951 unsigned ring_size; 952 uint64_t gpu_addr; 953 uint32_t ptr_mask; 954 atomic_t lock; 955 bool enabled; 956 }; 957 958 /* 959 * RLC stuff 960 */ 961 #include "clearstate_defs.h" 962 963 struct radeon_rlc { 964 /* for power gating */ 965 struct radeon_bo *save_restore_obj; 966 u64 save_restore_gpu_addr; 967 volatile uint32_t *sr_ptr; 968 const u32 *reg_list; 969 u32 reg_list_size; 970 /* for clear state */ 971 struct radeon_bo *clear_state_obj; 972 u64 clear_state_gpu_addr; 973 volatile uint32_t *cs_ptr; 974 const struct cs_section_def *cs_data; 975 u32 clear_state_size; 976 /* for cp tables */ 977 struct radeon_bo *cp_table_obj; 978 u64 cp_table_gpu_addr; 979 volatile uint32_t *cp_table_ptr; 980 u32 cp_table_size; 981 }; 982 983 int radeon_ib_get(struct radeon_device *rdev, int ring, 984 struct radeon_ib *ib, struct radeon_vm *vm, 985 unsigned size); 986 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 987 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 988 struct radeon_ib *const_ib, bool hdp_flush); 989 int radeon_ib_pool_init(struct radeon_device *rdev); 990 void radeon_ib_pool_fini(struct radeon_device *rdev); 991 int radeon_ib_ring_tests(struct radeon_device *rdev); 992 /* Ring access between begin & end cannot sleep */ 993 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 994 struct radeon_ring *ring); 995 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 996 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 997 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 998 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, 999 bool hdp_flush); 1000 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1001 bool hdp_flush); 1002 void radeon_ring_undo(struct radeon_ring *ring); 1003 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 1004 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 1005 void radeon_ring_lockup_update(struct radeon_device *rdev, 1006 struct radeon_ring *ring); 1007 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 1008 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 1009 uint32_t **data); 1010 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 1011 unsigned size, uint32_t *data); 1012 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 1013 unsigned rptr_offs, u32 nop); 1014 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 1015 1016 1017 /* r600 async dma */ 1018 void r600_dma_stop(struct radeon_device *rdev); 1019 int r600_dma_resume(struct radeon_device *rdev); 1020 void r600_dma_fini(struct radeon_device *rdev); 1021 1022 void cayman_dma_stop(struct radeon_device *rdev); 1023 int cayman_dma_resume(struct radeon_device *rdev); 1024 void cayman_dma_fini(struct radeon_device *rdev); 1025 1026 /* 1027 * CS. 1028 */ 1029 struct radeon_cs_reloc { 1030 struct drm_gem_object *gobj; 1031 struct radeon_bo *robj; 1032 struct ttm_validate_buffer tv; 1033 uint64_t gpu_offset; 1034 unsigned prefered_domains; 1035 unsigned allowed_domains; 1036 uint32_t tiling_flags; 1037 uint32_t handle; 1038 }; 1039 1040 struct radeon_cs_chunk { 1041 uint32_t chunk_id; 1042 uint32_t length_dw; 1043 uint32_t *kdata; 1044 void __user *user_ptr; 1045 }; 1046 1047 struct radeon_cs_parser { 1048 struct device *dev; 1049 struct radeon_device *rdev; 1050 struct drm_file *filp; 1051 /* chunks */ 1052 unsigned nchunks; 1053 struct radeon_cs_chunk *chunks; 1054 uint64_t *chunks_array; 1055 /* IB */ 1056 unsigned idx; 1057 /* relocations */ 1058 unsigned nrelocs; 1059 struct radeon_cs_reloc *relocs; 1060 struct radeon_cs_reloc **relocs_ptr; 1061 struct radeon_cs_reloc *vm_bos; 1062 struct list_head validated; 1063 unsigned dma_reloc_idx; 1064 /* indices of various chunks */ 1065 int chunk_ib_idx; 1066 int chunk_relocs_idx; 1067 int chunk_flags_idx; 1068 int chunk_const_ib_idx; 1069 struct radeon_ib ib; 1070 struct radeon_ib const_ib; 1071 void *track; 1072 unsigned family; 1073 int parser_error; 1074 u32 cs_flags; 1075 u32 ring; 1076 s32 priority; 1077 struct ww_acquire_ctx ticket; 1078 }; 1079 1080 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1081 { 1082 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 1083 1084 if (ibc->kdata) 1085 return ibc->kdata[idx]; 1086 return p->ib.ptr[idx]; 1087 } 1088 1089 1090 struct radeon_cs_packet { 1091 unsigned idx; 1092 unsigned type; 1093 unsigned reg; 1094 unsigned opcode; 1095 int count; 1096 unsigned one_reg_wr; 1097 }; 1098 1099 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1100 struct radeon_cs_packet *pkt, 1101 unsigned idx, unsigned reg); 1102 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 1103 struct radeon_cs_packet *pkt); 1104 1105 1106 /* 1107 * AGP 1108 */ 1109 int radeon_agp_init(struct radeon_device *rdev); 1110 void radeon_agp_resume(struct radeon_device *rdev); 1111 void radeon_agp_suspend(struct radeon_device *rdev); 1112 void radeon_agp_fini(struct radeon_device *rdev); 1113 1114 1115 /* 1116 * Writeback 1117 */ 1118 struct radeon_wb { 1119 struct radeon_bo *wb_obj; 1120 volatile uint32_t *wb; 1121 uint64_t gpu_addr; 1122 bool enabled; 1123 bool use_event; 1124 }; 1125 1126 #define RADEON_WB_SCRATCH_OFFSET 0 1127 #define RADEON_WB_RING0_NEXT_RPTR 256 1128 #define RADEON_WB_CP_RPTR_OFFSET 1024 1129 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1130 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1131 #define R600_WB_DMA_RPTR_OFFSET 1792 1132 #define R600_WB_IH_WPTR_OFFSET 2048 1133 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1134 #define R600_WB_EVENT_OFFSET 3072 1135 #define CIK_WB_CP1_WPTR_OFFSET 3328 1136 #define CIK_WB_CP2_WPTR_OFFSET 3584 1137 #define R600_WB_DMA_RING_TEST_OFFSET 3588 1138 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 1139 1140 /** 1141 * struct radeon_pm - power management datas 1142 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1143 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1144 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1145 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1146 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1147 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1148 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1149 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1150 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1151 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1152 * @needed_bandwidth: current bandwidth needs 1153 * 1154 * It keeps track of various data needed to take powermanagement decision. 1155 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1156 * Equation between gpu/memory clock and available bandwidth is hw dependent 1157 * (type of memory, bus size, efficiency, ...) 1158 */ 1159 1160 enum radeon_pm_method { 1161 PM_METHOD_PROFILE, 1162 PM_METHOD_DYNPM, 1163 PM_METHOD_DPM, 1164 }; 1165 1166 enum radeon_dynpm_state { 1167 DYNPM_STATE_DISABLED, 1168 DYNPM_STATE_MINIMUM, 1169 DYNPM_STATE_PAUSED, 1170 DYNPM_STATE_ACTIVE, 1171 DYNPM_STATE_SUSPENDED, 1172 }; 1173 enum radeon_dynpm_action { 1174 DYNPM_ACTION_NONE, 1175 DYNPM_ACTION_MINIMUM, 1176 DYNPM_ACTION_DOWNCLOCK, 1177 DYNPM_ACTION_UPCLOCK, 1178 DYNPM_ACTION_DEFAULT 1179 }; 1180 1181 enum radeon_voltage_type { 1182 VOLTAGE_NONE = 0, 1183 VOLTAGE_GPIO, 1184 VOLTAGE_VDDC, 1185 VOLTAGE_SW 1186 }; 1187 1188 enum radeon_pm_state_type { 1189 /* not used for dpm */ 1190 POWER_STATE_TYPE_DEFAULT, 1191 POWER_STATE_TYPE_POWERSAVE, 1192 /* user selectable states */ 1193 POWER_STATE_TYPE_BATTERY, 1194 POWER_STATE_TYPE_BALANCED, 1195 POWER_STATE_TYPE_PERFORMANCE, 1196 /* internal states */ 1197 POWER_STATE_TYPE_INTERNAL_UVD, 1198 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1199 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1200 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1201 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1202 POWER_STATE_TYPE_INTERNAL_BOOT, 1203 POWER_STATE_TYPE_INTERNAL_THERMAL, 1204 POWER_STATE_TYPE_INTERNAL_ACPI, 1205 POWER_STATE_TYPE_INTERNAL_ULV, 1206 POWER_STATE_TYPE_INTERNAL_3DPERF, 1207 }; 1208 1209 enum radeon_pm_profile_type { 1210 PM_PROFILE_DEFAULT, 1211 PM_PROFILE_AUTO, 1212 PM_PROFILE_LOW, 1213 PM_PROFILE_MID, 1214 PM_PROFILE_HIGH, 1215 }; 1216 1217 #define PM_PROFILE_DEFAULT_IDX 0 1218 #define PM_PROFILE_LOW_SH_IDX 1 1219 #define PM_PROFILE_MID_SH_IDX 2 1220 #define PM_PROFILE_HIGH_SH_IDX 3 1221 #define PM_PROFILE_LOW_MH_IDX 4 1222 #define PM_PROFILE_MID_MH_IDX 5 1223 #define PM_PROFILE_HIGH_MH_IDX 6 1224 #define PM_PROFILE_MAX 7 1225 1226 struct radeon_pm_profile { 1227 int dpms_off_ps_idx; 1228 int dpms_on_ps_idx; 1229 int dpms_off_cm_idx; 1230 int dpms_on_cm_idx; 1231 }; 1232 1233 enum radeon_int_thermal_type { 1234 THERMAL_TYPE_NONE, 1235 THERMAL_TYPE_EXTERNAL, 1236 THERMAL_TYPE_EXTERNAL_GPIO, 1237 THERMAL_TYPE_RV6XX, 1238 THERMAL_TYPE_RV770, 1239 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1240 THERMAL_TYPE_EVERGREEN, 1241 THERMAL_TYPE_SUMO, 1242 THERMAL_TYPE_NI, 1243 THERMAL_TYPE_SI, 1244 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1245 THERMAL_TYPE_CI, 1246 THERMAL_TYPE_KV, 1247 }; 1248 1249 struct radeon_voltage { 1250 enum radeon_voltage_type type; 1251 /* gpio voltage */ 1252 struct radeon_gpio_rec gpio; 1253 u32 delay; /* delay in usec from voltage drop to sclk change */ 1254 bool active_high; /* voltage drop is active when bit is high */ 1255 /* VDDC voltage */ 1256 u8 vddc_id; /* index into vddc voltage table */ 1257 u8 vddci_id; /* index into vddci voltage table */ 1258 bool vddci_enabled; 1259 /* r6xx+ sw */ 1260 u16 voltage; 1261 /* evergreen+ vddci */ 1262 u16 vddci; 1263 }; 1264 1265 /* clock mode flags */ 1266 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1267 1268 struct radeon_pm_clock_info { 1269 /* memory clock */ 1270 u32 mclk; 1271 /* engine clock */ 1272 u32 sclk; 1273 /* voltage info */ 1274 struct radeon_voltage voltage; 1275 /* standardized clock flags */ 1276 u32 flags; 1277 }; 1278 1279 /* state flags */ 1280 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1281 1282 struct radeon_power_state { 1283 enum radeon_pm_state_type type; 1284 struct radeon_pm_clock_info *clock_info; 1285 /* number of valid clock modes in this power state */ 1286 int num_clock_modes; 1287 struct radeon_pm_clock_info *default_clock_mode; 1288 /* standardized state flags */ 1289 u32 flags; 1290 u32 misc; /* vbios specific flags */ 1291 u32 misc2; /* vbios specific flags */ 1292 int pcie_lanes; /* pcie lanes */ 1293 }; 1294 1295 /* 1296 * Some modes are overclocked by very low value, accept them 1297 */ 1298 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1299 1300 enum radeon_dpm_auto_throttle_src { 1301 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1302 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1303 }; 1304 1305 enum radeon_dpm_event_src { 1306 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1307 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1308 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1309 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1310 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1311 }; 1312 1313 #define RADEON_MAX_VCE_LEVELS 6 1314 1315 enum radeon_vce_level { 1316 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1317 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1318 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1319 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1320 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1321 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1322 }; 1323 1324 struct radeon_ps { 1325 u32 caps; /* vbios flags */ 1326 u32 class; /* vbios flags */ 1327 u32 class2; /* vbios flags */ 1328 /* UVD clocks */ 1329 u32 vclk; 1330 u32 dclk; 1331 /* VCE clocks */ 1332 u32 evclk; 1333 u32 ecclk; 1334 bool vce_active; 1335 enum radeon_vce_level vce_level; 1336 /* asic priv */ 1337 void *ps_priv; 1338 }; 1339 1340 struct radeon_dpm_thermal { 1341 /* thermal interrupt work */ 1342 struct task work; 1343 /* low temperature threshold */ 1344 int min_temp; 1345 /* high temperature threshold */ 1346 int max_temp; 1347 /* was interrupt low to high or high to low */ 1348 bool high_to_low; 1349 }; 1350 1351 enum radeon_clk_action 1352 { 1353 RADEON_SCLK_UP = 1, 1354 RADEON_SCLK_DOWN 1355 }; 1356 1357 struct radeon_blacklist_clocks 1358 { 1359 u32 sclk; 1360 u32 mclk; 1361 enum radeon_clk_action action; 1362 }; 1363 1364 struct radeon_clock_and_voltage_limits { 1365 u32 sclk; 1366 u32 mclk; 1367 u16 vddc; 1368 u16 vddci; 1369 }; 1370 1371 struct radeon_clock_array { 1372 u32 count; 1373 u32 *values; 1374 }; 1375 1376 struct radeon_clock_voltage_dependency_entry { 1377 u32 clk; 1378 u16 v; 1379 }; 1380 1381 struct radeon_clock_voltage_dependency_table { 1382 u32 count; 1383 struct radeon_clock_voltage_dependency_entry *entries; 1384 }; 1385 1386 union radeon_cac_leakage_entry { 1387 struct { 1388 u16 vddc; 1389 u32 leakage; 1390 }; 1391 struct { 1392 u16 vddc1; 1393 u16 vddc2; 1394 u16 vddc3; 1395 }; 1396 }; 1397 1398 struct radeon_cac_leakage_table { 1399 u32 count; 1400 union radeon_cac_leakage_entry *entries; 1401 }; 1402 1403 struct radeon_phase_shedding_limits_entry { 1404 u16 voltage; 1405 u32 sclk; 1406 u32 mclk; 1407 }; 1408 1409 struct radeon_phase_shedding_limits_table { 1410 u32 count; 1411 struct radeon_phase_shedding_limits_entry *entries; 1412 }; 1413 1414 struct radeon_uvd_clock_voltage_dependency_entry { 1415 u32 vclk; 1416 u32 dclk; 1417 u16 v; 1418 }; 1419 1420 struct radeon_uvd_clock_voltage_dependency_table { 1421 u8 count; 1422 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1423 }; 1424 1425 struct radeon_vce_clock_voltage_dependency_entry { 1426 u32 ecclk; 1427 u32 evclk; 1428 u16 v; 1429 }; 1430 1431 struct radeon_vce_clock_voltage_dependency_table { 1432 u8 count; 1433 struct radeon_vce_clock_voltage_dependency_entry *entries; 1434 }; 1435 1436 struct radeon_ppm_table { 1437 u8 ppm_design; 1438 u16 cpu_core_number; 1439 u32 platform_tdp; 1440 u32 small_ac_platform_tdp; 1441 u32 platform_tdc; 1442 u32 small_ac_platform_tdc; 1443 u32 apu_tdp; 1444 u32 dgpu_tdp; 1445 u32 dgpu_ulv_power; 1446 u32 tj_max; 1447 }; 1448 1449 struct radeon_cac_tdp_table { 1450 u16 tdp; 1451 u16 configurable_tdp; 1452 u16 tdc; 1453 u16 battery_power_limit; 1454 u16 small_power_limit; 1455 u16 low_cac_leakage; 1456 u16 high_cac_leakage; 1457 u16 maximum_power_delivery_limit; 1458 }; 1459 1460 struct radeon_dpm_dynamic_state { 1461 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1462 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1463 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1464 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1465 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1466 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1467 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1468 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1469 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1470 struct radeon_clock_array valid_sclk_values; 1471 struct radeon_clock_array valid_mclk_values; 1472 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1473 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1474 u32 mclk_sclk_ratio; 1475 u32 sclk_mclk_delta; 1476 u16 vddc_vddci_delta; 1477 u16 min_vddc_for_pcie_gen2; 1478 struct radeon_cac_leakage_table cac_leakage_table; 1479 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1480 struct radeon_ppm_table *ppm_table; 1481 struct radeon_cac_tdp_table *cac_tdp_table; 1482 }; 1483 1484 struct radeon_dpm_fan { 1485 u16 t_min; 1486 u16 t_med; 1487 u16 t_high; 1488 u16 pwm_min; 1489 u16 pwm_med; 1490 u16 pwm_high; 1491 u8 t_hyst; 1492 u32 cycle_delay; 1493 u16 t_max; 1494 bool ucode_fan_control; 1495 }; 1496 1497 enum radeon_pcie_gen { 1498 RADEON_PCIE_GEN1 = 0, 1499 RADEON_PCIE_GEN2 = 1, 1500 RADEON_PCIE_GEN3 = 2, 1501 RADEON_PCIE_GEN_INVALID = 0xffff 1502 }; 1503 1504 enum radeon_dpm_forced_level { 1505 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1506 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1507 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1508 }; 1509 1510 struct radeon_vce_state { 1511 /* vce clocks */ 1512 u32 evclk; 1513 u32 ecclk; 1514 /* gpu clocks */ 1515 u32 sclk; 1516 u32 mclk; 1517 u8 clk_idx; 1518 u8 pstate; 1519 }; 1520 1521 struct radeon_dpm { 1522 struct radeon_ps *ps; 1523 /* number of valid power states */ 1524 int num_ps; 1525 /* current power state that is active */ 1526 struct radeon_ps *current_ps; 1527 /* requested power state */ 1528 struct radeon_ps *requested_ps; 1529 /* boot up power state */ 1530 struct radeon_ps *boot_ps; 1531 /* default uvd power state */ 1532 struct radeon_ps *uvd_ps; 1533 /* vce requirements */ 1534 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1535 enum radeon_vce_level vce_level; 1536 enum radeon_pm_state_type state; 1537 enum radeon_pm_state_type user_state; 1538 u32 platform_caps; 1539 u32 voltage_response_time; 1540 u32 backbias_response_time; 1541 void *priv; 1542 u32 new_active_crtcs; 1543 int new_active_crtc_count; 1544 u32 current_active_crtcs; 1545 int current_active_crtc_count; 1546 struct radeon_dpm_dynamic_state dyn_state; 1547 struct radeon_dpm_fan fan; 1548 u32 tdp_limit; 1549 u32 near_tdp_limit; 1550 u32 near_tdp_limit_adjusted; 1551 u32 sq_ramping_threshold; 1552 u32 cac_leakage; 1553 u16 tdp_od_limit; 1554 u32 tdp_adjustment; 1555 u16 load_line_slope; 1556 bool power_control; 1557 bool ac_power; 1558 /* special states active */ 1559 bool thermal_active; 1560 bool uvd_active; 1561 bool vce_active; 1562 /* thermal handling */ 1563 struct radeon_dpm_thermal thermal; 1564 /* forced levels */ 1565 enum radeon_dpm_forced_level forced_level; 1566 /* track UVD streams */ 1567 unsigned sd; 1568 unsigned hd; 1569 }; 1570 1571 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1572 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1573 1574 struct radeon_pm { 1575 struct lock mutex; 1576 /* write locked while reprogramming mclk */ 1577 struct lock mclk_lock; 1578 u32 active_crtcs; 1579 int active_crtc_count; 1580 int req_vblank; 1581 bool vblank_sync; 1582 fixed20_12 max_bandwidth; 1583 fixed20_12 igp_sideport_mclk; 1584 fixed20_12 igp_system_mclk; 1585 fixed20_12 igp_ht_link_clk; 1586 fixed20_12 igp_ht_link_width; 1587 fixed20_12 k8_bandwidth; 1588 fixed20_12 sideport_bandwidth; 1589 fixed20_12 ht_bandwidth; 1590 fixed20_12 core_bandwidth; 1591 fixed20_12 sclk; 1592 fixed20_12 mclk; 1593 fixed20_12 needed_bandwidth; 1594 struct radeon_power_state *power_state; 1595 /* number of valid power states */ 1596 int num_power_states; 1597 int current_power_state_index; 1598 int current_clock_mode_index; 1599 int requested_power_state_index; 1600 int requested_clock_mode_index; 1601 int default_power_state_index; 1602 u32 current_sclk; 1603 u32 current_mclk; 1604 u16 current_vddc; 1605 u16 current_vddci; 1606 u32 default_sclk; 1607 u32 default_mclk; 1608 u16 default_vddc; 1609 u16 default_vddci; 1610 struct radeon_i2c_chan *i2c_bus; 1611 /* selected pm method */ 1612 enum radeon_pm_method pm_method; 1613 /* dynpm power management */ 1614 #ifdef DUMBBELL_WIP 1615 struct delayed_work dynpm_idle_work; 1616 #endif /* DUMBBELL_WIP */ 1617 enum radeon_dynpm_state dynpm_state; 1618 enum radeon_dynpm_action dynpm_planned_action; 1619 unsigned long dynpm_action_timeout; 1620 bool dynpm_can_upclock; 1621 bool dynpm_can_downclock; 1622 /* profile-based power management */ 1623 enum radeon_pm_profile_type profile; 1624 int profile_index; 1625 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1626 /* internal thermal controller on rv6xx+ */ 1627 enum radeon_int_thermal_type int_thermal_type; 1628 struct ksensor *int_sensor; 1629 struct ksensordev *int_sensordev; 1630 /* dpm */ 1631 bool dpm_enabled; 1632 struct radeon_dpm dpm; 1633 }; 1634 1635 int radeon_pm_get_type_index(struct radeon_device *rdev, 1636 enum radeon_pm_state_type ps_type, 1637 int instance); 1638 /* 1639 * UVD 1640 */ 1641 #define RADEON_MAX_UVD_HANDLES 10 1642 #define RADEON_UVD_STACK_SIZE (1024*1024) 1643 #define RADEON_UVD_HEAP_SIZE (1024*1024) 1644 1645 struct radeon_uvd { 1646 struct radeon_bo *vcpu_bo; 1647 void *cpu_addr; 1648 u64 gpu_addr; 1649 void *saved_bo; 1650 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1651 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1652 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1653 struct delayed_work idle_work; 1654 }; 1655 1656 int radeon_uvd_init(struct radeon_device *rdev); 1657 void radeon_uvd_fini(struct radeon_device *rdev); 1658 int radeon_uvd_suspend(struct radeon_device *rdev); 1659 int radeon_uvd_resume(struct radeon_device *rdev); 1660 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1661 uint32_t handle, struct radeon_fence **fence); 1662 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1663 uint32_t handle, struct radeon_fence **fence); 1664 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, 1665 uint32_t allowed_domains); 1666 void radeon_uvd_free_handles(struct radeon_device *rdev, 1667 struct drm_file *filp); 1668 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1669 void radeon_uvd_note_usage(struct radeon_device *rdev); 1670 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1671 unsigned vclk, unsigned dclk, 1672 unsigned vco_min, unsigned vco_max, 1673 unsigned fb_factor, unsigned fb_mask, 1674 unsigned pd_min, unsigned pd_max, 1675 unsigned pd_even, 1676 unsigned *optimal_fb_div, 1677 unsigned *optimal_vclk_div, 1678 unsigned *optimal_dclk_div); 1679 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1680 unsigned cg_upll_func_cntl); 1681 1682 /* 1683 * VCE 1684 */ 1685 #define RADEON_MAX_VCE_HANDLES 16 1686 #define RADEON_VCE_STACK_SIZE (1024*1024) 1687 #define RADEON_VCE_HEAP_SIZE (4*1024*1024) 1688 1689 struct radeon_vce { 1690 struct radeon_bo *vcpu_bo; 1691 u64 gpu_addr; 1692 unsigned fw_version; 1693 unsigned fb_version; 1694 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1695 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1696 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1697 struct delayed_work idle_work; 1698 }; 1699 1700 int radeon_vce_init(struct radeon_device *rdev); 1701 void radeon_vce_fini(struct radeon_device *rdev); 1702 int radeon_vce_suspend(struct radeon_device *rdev); 1703 int radeon_vce_resume(struct radeon_device *rdev); 1704 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1705 uint32_t handle, struct radeon_fence **fence); 1706 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1707 uint32_t handle, struct radeon_fence **fence); 1708 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1709 void radeon_vce_note_usage(struct radeon_device *rdev); 1710 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1711 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1712 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1713 struct radeon_ring *ring, 1714 struct radeon_semaphore *semaphore, 1715 bool emit_wait); 1716 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1717 void radeon_vce_fence_emit(struct radeon_device *rdev, 1718 struct radeon_fence *fence); 1719 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1720 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1721 1722 struct r600_audio_pin { 1723 int channels; 1724 int rate; 1725 int bits_per_sample; 1726 u8 status_bits; 1727 u8 category_code; 1728 u32 offset; 1729 bool connected; 1730 u32 id; 1731 }; 1732 1733 struct r600_audio { 1734 bool enabled; 1735 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1736 int num_pins; 1737 }; 1738 1739 /* 1740 * Benchmarking 1741 */ 1742 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1743 1744 1745 /* 1746 * Testing 1747 */ 1748 void radeon_test_moves(struct radeon_device *rdev); 1749 void radeon_test_ring_sync(struct radeon_device *rdev, 1750 struct radeon_ring *cpA, 1751 struct radeon_ring *cpB); 1752 void radeon_test_syncing(struct radeon_device *rdev); 1753 1754 1755 /* 1756 * Debugfs 1757 */ 1758 struct radeon_debugfs { 1759 struct drm_info_list *files; 1760 unsigned num_files; 1761 }; 1762 1763 int radeon_debugfs_add_files(struct radeon_device *rdev, 1764 struct drm_info_list *files, 1765 unsigned nfiles); 1766 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1767 1768 /* 1769 * ASIC ring specific functions. 1770 */ 1771 struct radeon_asic_ring { 1772 /* ring read/write ptr handling */ 1773 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1774 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1775 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1776 1777 /* validating and patching of IBs */ 1778 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1779 int (*cs_parse)(struct radeon_cs_parser *p); 1780 1781 /* command emmit functions */ 1782 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1783 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1784 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); 1785 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1786 struct radeon_semaphore *semaphore, bool emit_wait); 1787 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 1788 1789 /* testing functions */ 1790 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1791 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1792 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1793 1794 /* deprecated */ 1795 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1796 }; 1797 1798 /* 1799 * ASIC specific functions. 1800 */ 1801 struct radeon_asic { 1802 int (*init)(struct radeon_device *rdev); 1803 void (*fini)(struct radeon_device *rdev); 1804 int (*resume)(struct radeon_device *rdev); 1805 int (*suspend)(struct radeon_device *rdev); 1806 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1807 int (*asic_reset)(struct radeon_device *rdev); 1808 /* Flush the HDP cache via MMIO */ 1809 void (*mmio_hdp_flush)(struct radeon_device *rdev); 1810 /* check if 3D engine is idle */ 1811 bool (*gui_idle)(struct radeon_device *rdev); 1812 /* wait for mc_idle */ 1813 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1814 /* get the reference clock */ 1815 u32 (*get_xclk)(struct radeon_device *rdev); 1816 /* get the gpu clock counter */ 1817 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1818 /* gart */ 1819 struct { 1820 void (*tlb_flush)(struct radeon_device *rdev); 1821 void (*set_page)(struct radeon_device *rdev, unsigned i, 1822 uint64_t addr, uint32_t flags); 1823 } gart; 1824 struct { 1825 int (*init)(struct radeon_device *rdev); 1826 void (*fini)(struct radeon_device *rdev); 1827 void (*copy_pages)(struct radeon_device *rdev, 1828 struct radeon_ib *ib, 1829 uint64_t pe, uint64_t src, 1830 unsigned count); 1831 void (*write_pages)(struct radeon_device *rdev, 1832 struct radeon_ib *ib, 1833 uint64_t pe, 1834 uint64_t addr, unsigned count, 1835 uint32_t incr, uint32_t flags); 1836 void (*set_pages)(struct radeon_device *rdev, 1837 struct radeon_ib *ib, 1838 uint64_t pe, 1839 uint64_t addr, unsigned count, 1840 uint32_t incr, uint32_t flags); 1841 void (*pad_ib)(struct radeon_ib *ib); 1842 } vm; 1843 /* ring specific callbacks */ 1844 struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1845 /* irqs */ 1846 struct { 1847 int (*set)(struct radeon_device *rdev); 1848 irqreturn_t (*process)(struct radeon_device *rdev); 1849 } irq; 1850 /* displays */ 1851 struct { 1852 /* display watermarks */ 1853 void (*bandwidth_update)(struct radeon_device *rdev); 1854 /* get frame count */ 1855 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1856 /* wait for vblank */ 1857 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1858 /* set backlight level */ 1859 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1860 /* get backlight level */ 1861 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1862 /* audio callbacks */ 1863 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1864 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1865 } display; 1866 /* copy functions for bo handling */ 1867 struct { 1868 int (*blit)(struct radeon_device *rdev, 1869 uint64_t src_offset, 1870 uint64_t dst_offset, 1871 unsigned num_gpu_pages, 1872 struct radeon_fence **fence); 1873 u32 blit_ring_index; 1874 int (*dma)(struct radeon_device *rdev, 1875 uint64_t src_offset, 1876 uint64_t dst_offset, 1877 unsigned num_gpu_pages, 1878 struct radeon_fence **fence); 1879 u32 dma_ring_index; 1880 /* method used for bo copy */ 1881 int (*copy)(struct radeon_device *rdev, 1882 uint64_t src_offset, 1883 uint64_t dst_offset, 1884 unsigned num_gpu_pages, 1885 struct radeon_fence **fence); 1886 /* ring used for bo copies */ 1887 u32 copy_ring_index; 1888 } copy; 1889 /* surfaces */ 1890 struct { 1891 int (*set_reg)(struct radeon_device *rdev, int reg, 1892 uint32_t tiling_flags, uint32_t pitch, 1893 uint32_t offset, uint32_t obj_size); 1894 void (*clear_reg)(struct radeon_device *rdev, int reg); 1895 } surface; 1896 /* hotplug detect */ 1897 struct { 1898 void (*init)(struct radeon_device *rdev); 1899 void (*fini)(struct radeon_device *rdev); 1900 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1901 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1902 } hpd; 1903 /* static power management */ 1904 struct { 1905 void (*misc)(struct radeon_device *rdev); 1906 void (*prepare)(struct radeon_device *rdev); 1907 void (*finish)(struct radeon_device *rdev); 1908 void (*init_profile)(struct radeon_device *rdev); 1909 void (*get_dynpm_state)(struct radeon_device *rdev); 1910 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1911 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1912 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1913 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1914 int (*get_pcie_lanes)(struct radeon_device *rdev); 1915 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1916 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1917 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 1918 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 1919 int (*get_temperature)(struct radeon_device *rdev); 1920 } pm; 1921 /* dynamic power management */ 1922 struct { 1923 int (*init)(struct radeon_device *rdev); 1924 void (*setup_asic)(struct radeon_device *rdev); 1925 int (*enable)(struct radeon_device *rdev); 1926 int (*late_enable)(struct radeon_device *rdev); 1927 void (*disable)(struct radeon_device *rdev); 1928 int (*pre_set_power_state)(struct radeon_device *rdev); 1929 int (*set_power_state)(struct radeon_device *rdev); 1930 void (*post_set_power_state)(struct radeon_device *rdev); 1931 void (*display_configuration_changed)(struct radeon_device *rdev); 1932 void (*fini)(struct radeon_device *rdev); 1933 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 1934 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 1935 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 1936 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 1937 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 1938 bool (*vblank_too_short)(struct radeon_device *rdev); 1939 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 1940 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 1941 } dpm; 1942 /* pageflipping */ 1943 struct { 1944 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 1945 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); 1946 } pflip; 1947 }; 1948 1949 /* 1950 * Asic structures 1951 */ 1952 struct r100_asic { 1953 const unsigned *reg_safe_bm; 1954 unsigned reg_safe_bm_size; 1955 u32 hdp_cntl; 1956 }; 1957 1958 struct r300_asic { 1959 const unsigned *reg_safe_bm; 1960 unsigned reg_safe_bm_size; 1961 u32 resync_scratch; 1962 u32 hdp_cntl; 1963 }; 1964 1965 struct r600_asic { 1966 unsigned max_pipes; 1967 unsigned max_tile_pipes; 1968 unsigned max_simds; 1969 unsigned max_backends; 1970 unsigned max_gprs; 1971 unsigned max_threads; 1972 unsigned max_stack_entries; 1973 unsigned max_hw_contexts; 1974 unsigned max_gs_threads; 1975 unsigned sx_max_export_size; 1976 unsigned sx_max_export_pos_size; 1977 unsigned sx_max_export_smx_size; 1978 unsigned sq_num_cf_insts; 1979 unsigned tiling_nbanks; 1980 unsigned tiling_npipes; 1981 unsigned tiling_group_size; 1982 unsigned tile_config; 1983 unsigned backend_map; 1984 unsigned active_simds; 1985 }; 1986 1987 struct rv770_asic { 1988 unsigned max_pipes; 1989 unsigned max_tile_pipes; 1990 unsigned max_simds; 1991 unsigned max_backends; 1992 unsigned max_gprs; 1993 unsigned max_threads; 1994 unsigned max_stack_entries; 1995 unsigned max_hw_contexts; 1996 unsigned max_gs_threads; 1997 unsigned sx_max_export_size; 1998 unsigned sx_max_export_pos_size; 1999 unsigned sx_max_export_smx_size; 2000 unsigned sq_num_cf_insts; 2001 unsigned sx_num_of_sets; 2002 unsigned sc_prim_fifo_size; 2003 unsigned sc_hiz_tile_fifo_size; 2004 unsigned sc_earlyz_tile_fifo_fize; 2005 unsigned tiling_nbanks; 2006 unsigned tiling_npipes; 2007 unsigned tiling_group_size; 2008 unsigned tile_config; 2009 unsigned backend_map; 2010 unsigned active_simds; 2011 }; 2012 2013 struct evergreen_asic { 2014 unsigned num_ses; 2015 unsigned max_pipes; 2016 unsigned max_tile_pipes; 2017 unsigned max_simds; 2018 unsigned max_backends; 2019 unsigned max_gprs; 2020 unsigned max_threads; 2021 unsigned max_stack_entries; 2022 unsigned max_hw_contexts; 2023 unsigned max_gs_threads; 2024 unsigned sx_max_export_size; 2025 unsigned sx_max_export_pos_size; 2026 unsigned sx_max_export_smx_size; 2027 unsigned sq_num_cf_insts; 2028 unsigned sx_num_of_sets; 2029 unsigned sc_prim_fifo_size; 2030 unsigned sc_hiz_tile_fifo_size; 2031 unsigned sc_earlyz_tile_fifo_size; 2032 unsigned tiling_nbanks; 2033 unsigned tiling_npipes; 2034 unsigned tiling_group_size; 2035 unsigned tile_config; 2036 unsigned backend_map; 2037 unsigned active_simds; 2038 }; 2039 2040 struct cayman_asic { 2041 unsigned max_shader_engines; 2042 unsigned max_pipes_per_simd; 2043 unsigned max_tile_pipes; 2044 unsigned max_simds_per_se; 2045 unsigned max_backends_per_se; 2046 unsigned max_texture_channel_caches; 2047 unsigned max_gprs; 2048 unsigned max_threads; 2049 unsigned max_gs_threads; 2050 unsigned max_stack_entries; 2051 unsigned sx_num_of_sets; 2052 unsigned sx_max_export_size; 2053 unsigned sx_max_export_pos_size; 2054 unsigned sx_max_export_smx_size; 2055 unsigned max_hw_contexts; 2056 unsigned sq_num_cf_insts; 2057 unsigned sc_prim_fifo_size; 2058 unsigned sc_hiz_tile_fifo_size; 2059 unsigned sc_earlyz_tile_fifo_size; 2060 2061 unsigned num_shader_engines; 2062 unsigned num_shader_pipes_per_simd; 2063 unsigned num_tile_pipes; 2064 unsigned num_simds_per_se; 2065 unsigned num_backends_per_se; 2066 unsigned backend_disable_mask_per_asic; 2067 unsigned backend_map; 2068 unsigned num_texture_channel_caches; 2069 unsigned mem_max_burst_length_bytes; 2070 unsigned mem_row_size_in_kb; 2071 unsigned shader_engine_tile_size; 2072 unsigned num_gpus; 2073 unsigned multi_gpu_tile_size; 2074 2075 unsigned tile_config; 2076 unsigned active_simds; 2077 }; 2078 2079 struct si_asic { 2080 unsigned max_shader_engines; 2081 unsigned max_tile_pipes; 2082 unsigned max_cu_per_sh; 2083 unsigned max_sh_per_se; 2084 unsigned max_backends_per_se; 2085 unsigned max_texture_channel_caches; 2086 unsigned max_gprs; 2087 unsigned max_gs_threads; 2088 unsigned max_hw_contexts; 2089 unsigned sc_prim_fifo_size_frontend; 2090 unsigned sc_prim_fifo_size_backend; 2091 unsigned sc_hiz_tile_fifo_size; 2092 unsigned sc_earlyz_tile_fifo_size; 2093 2094 unsigned num_tile_pipes; 2095 unsigned backend_enable_mask; 2096 unsigned backend_disable_mask_per_asic; 2097 unsigned backend_map; 2098 unsigned num_texture_channel_caches; 2099 unsigned mem_max_burst_length_bytes; 2100 unsigned mem_row_size_in_kb; 2101 unsigned shader_engine_tile_size; 2102 unsigned num_gpus; 2103 unsigned multi_gpu_tile_size; 2104 2105 unsigned tile_config; 2106 uint32_t tile_mode_array[32]; 2107 uint32_t active_cus; 2108 }; 2109 2110 struct cik_asic { 2111 unsigned max_shader_engines; 2112 unsigned max_tile_pipes; 2113 unsigned max_cu_per_sh; 2114 unsigned max_sh_per_se; 2115 unsigned max_backends_per_se; 2116 unsigned max_texture_channel_caches; 2117 unsigned max_gprs; 2118 unsigned max_gs_threads; 2119 unsigned max_hw_contexts; 2120 unsigned sc_prim_fifo_size_frontend; 2121 unsigned sc_prim_fifo_size_backend; 2122 unsigned sc_hiz_tile_fifo_size; 2123 unsigned sc_earlyz_tile_fifo_size; 2124 2125 unsigned num_tile_pipes; 2126 unsigned backend_enable_mask; 2127 unsigned backend_disable_mask_per_asic; 2128 unsigned backend_map; 2129 unsigned num_texture_channel_caches; 2130 unsigned mem_max_burst_length_bytes; 2131 unsigned mem_row_size_in_kb; 2132 unsigned shader_engine_tile_size; 2133 unsigned num_gpus; 2134 unsigned multi_gpu_tile_size; 2135 2136 unsigned tile_config; 2137 uint32_t tile_mode_array[32]; 2138 uint32_t macrotile_mode_array[16]; 2139 uint32_t active_cus; 2140 }; 2141 2142 union radeon_asic_config { 2143 struct r300_asic r300; 2144 struct r100_asic r100; 2145 struct r600_asic r600; 2146 struct rv770_asic rv770; 2147 struct evergreen_asic evergreen; 2148 struct cayman_asic cayman; 2149 struct si_asic si; 2150 struct cik_asic cik; 2151 }; 2152 2153 /* 2154 * asic initizalization from radeon_asic.c 2155 */ 2156 int radeon_asic_init(struct radeon_device *rdev); 2157 2158 2159 /* 2160 * IOCTL. 2161 */ 2162 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2163 struct drm_file *filp); 2164 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2165 struct drm_file *filp); 2166 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2167 struct drm_file *file_priv); 2168 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2169 struct drm_file *file_priv); 2170 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2171 struct drm_file *file_priv); 2172 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 2173 struct drm_file *file_priv); 2174 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2175 struct drm_file *filp); 2176 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2177 struct drm_file *filp); 2178 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2179 struct drm_file *filp); 2180 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2181 struct drm_file *filp); 2182 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2183 struct drm_file *filp); 2184 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2185 struct drm_file *filp); 2186 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2187 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2188 struct drm_file *filp); 2189 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2190 struct drm_file *filp); 2191 2192 /* VRAM scratch page for HDP bug, default vram page */ 2193 struct r600_vram_scratch { 2194 struct radeon_bo *robj; 2195 volatile uint32_t *ptr; 2196 u64 gpu_addr; 2197 }; 2198 2199 /* 2200 * ACPI 2201 */ 2202 struct radeon_atif_notification_cfg { 2203 bool enabled; 2204 int command_code; 2205 }; 2206 2207 struct radeon_atif_notifications { 2208 bool display_switch; 2209 bool expansion_mode_change; 2210 bool thermal_state; 2211 bool forced_power_state; 2212 bool system_power_state; 2213 bool display_conf_change; 2214 bool px_gfx_switch; 2215 bool brightness_change; 2216 bool dgpu_display_event; 2217 }; 2218 2219 struct radeon_atif_functions { 2220 bool system_params; 2221 bool sbios_requests; 2222 bool select_active_disp; 2223 bool lid_state; 2224 bool get_tv_standard; 2225 bool set_tv_standard; 2226 bool get_panel_expansion_mode; 2227 bool set_panel_expansion_mode; 2228 bool temperature_change; 2229 bool graphics_device_types; 2230 }; 2231 2232 struct radeon_atif { 2233 struct radeon_atif_notifications notifications; 2234 struct radeon_atif_functions functions; 2235 struct radeon_atif_notification_cfg notification_cfg; 2236 struct radeon_encoder *encoder_for_bl; 2237 }; 2238 2239 struct radeon_atcs_functions { 2240 bool get_ext_state; 2241 bool pcie_perf_req; 2242 bool pcie_dev_rdy; 2243 bool pcie_bus_width; 2244 }; 2245 2246 struct radeon_atcs { 2247 struct radeon_atcs_functions functions; 2248 }; 2249 2250 /* 2251 * Core structure, functions and helpers. 2252 */ 2253 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2254 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2255 2256 struct radeon_device { 2257 struct device *dev; 2258 struct drm_device *ddev; 2259 struct pci_dev *pdev; 2260 struct lock exclusive_lock; 2261 /* ASIC */ 2262 union radeon_asic_config config; 2263 enum radeon_family family; 2264 unsigned long flags; 2265 int usec_timeout; 2266 enum radeon_pll_errata pll_errata; 2267 int num_gb_pipes; 2268 int num_z_pipes; 2269 int disp_priority; 2270 /* BIOS */ 2271 uint8_t *bios; 2272 bool is_atom_bios; 2273 uint16_t bios_header_start; 2274 struct radeon_bo *stollen_vga_memory; 2275 /* Register mmio */ 2276 resource_size_t rmmio_base; 2277 resource_size_t rmmio_size; 2278 /* protects concurrent MM_INDEX/DATA based register access */ 2279 struct spinlock mmio_idx_lock; 2280 /* protects concurrent SMC based register access */ 2281 struct spinlock smc_idx_lock; 2282 /* protects concurrent PLL register access */ 2283 struct spinlock pll_idx_lock; 2284 /* protects concurrent MC register access */ 2285 struct spinlock mc_idx_lock; 2286 /* protects concurrent PCIE register access */ 2287 struct spinlock pcie_idx_lock; 2288 /* protects concurrent PCIE_PORT register access */ 2289 struct spinlock pciep_idx_lock; 2290 /* protects concurrent PIF register access */ 2291 struct spinlock pif_idx_lock; 2292 /* protects concurrent CG register access */ 2293 struct spinlock cg_idx_lock; 2294 /* protects concurrent UVD register access */ 2295 struct spinlock uvd_idx_lock; 2296 /* protects concurrent RCU register access */ 2297 struct spinlock rcu_idx_lock; 2298 /* protects concurrent DIDT register access */ 2299 struct spinlock didt_idx_lock; 2300 /* protects concurrent ENDPOINT (audio) register access */ 2301 struct spinlock end_idx_lock; 2302 int rmmio_rid; 2303 struct resource *rmmio; 2304 radeon_rreg_t mc_rreg; 2305 radeon_wreg_t mc_wreg; 2306 radeon_rreg_t pll_rreg; 2307 radeon_wreg_t pll_wreg; 2308 uint32_t pcie_reg_mask; 2309 radeon_rreg_t pciep_rreg; 2310 radeon_wreg_t pciep_wreg; 2311 /* io port */ 2312 int rio_rid; 2313 struct resource *rio_mem; 2314 resource_size_t rio_mem_size; 2315 struct radeon_clock clock; 2316 struct radeon_mc mc; 2317 struct radeon_gart gart; 2318 struct radeon_mode_info mode_info; 2319 struct radeon_scratch scratch; 2320 struct radeon_doorbell doorbell; 2321 struct radeon_mman mman; 2322 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2323 wait_queue_head_t fence_queue; 2324 struct lock ring_lock; 2325 struct radeon_ring ring[RADEON_NUM_RINGS]; 2326 bool ib_pool_ready; 2327 struct radeon_sa_manager ring_tmp_bo; 2328 struct radeon_irq irq; 2329 struct radeon_asic *asic; 2330 struct radeon_gem gem; 2331 struct radeon_pm pm; 2332 struct radeon_uvd uvd; 2333 struct radeon_vce vce; 2334 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2335 struct radeon_wb wb; 2336 struct radeon_dummy_page dummy_page; 2337 bool shutdown; 2338 bool suspend; 2339 bool need_dma32; 2340 bool accel_working; 2341 bool fastfb_working; /* IGP feature*/ 2342 bool needs_reset, in_reset; 2343 bool fictitious_range_registered; 2344 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2345 const struct firmware *me_fw; /* all family ME firmware */ 2346 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2347 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2348 const struct firmware *mc_fw; /* NI MC firmware */ 2349 const struct firmware *ce_fw; /* SI CE firmware */ 2350 const struct firmware *mec_fw; /* CIK MEC firmware */ 2351 const struct firmware *mec2_fw; /* KV MEC2 firmware */ 2352 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2353 const struct firmware *smc_fw; /* SMC firmware */ 2354 const struct firmware *uvd_fw; /* UVD firmware */ 2355 const struct firmware *vce_fw; /* VCE firmware */ 2356 bool new_fw; 2357 struct r600_vram_scratch vram_scratch; 2358 int msi_enabled; /* msi enabled */ 2359 struct r600_ih ih; /* r6/700 interrupt ring */ 2360 struct radeon_rlc rlc; 2361 struct radeon_mec mec; 2362 struct taskqueue *tq; 2363 struct task hotplug_work; 2364 struct task audio_work; 2365 int num_crtc; /* number of crtcs */ 2366 struct lock dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2367 bool has_uvd; 2368 struct r600_audio audio; /* audio stuff */ 2369 struct { 2370 ACPI_HANDLE handle; 2371 ACPI_NOTIFY_HANDLER notifier_call; 2372 } acpi; 2373 /* only one userspace can use Hyperz features or CMASK at a time */ 2374 struct drm_file *hyperz_filp; 2375 struct drm_file *cmask_filp; 2376 /* i2c buses */ 2377 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2378 /* debugfs */ 2379 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 2380 unsigned debugfs_count; 2381 /* virtual memory */ 2382 struct radeon_vm_manager vm_manager; 2383 struct lock gpu_clock_mutex; 2384 /* memory stats */ 2385 atomic64_t vram_usage; 2386 atomic64_t gtt_usage; 2387 atomic64_t num_bytes_moved; 2388 /* ACPI interface */ 2389 struct radeon_atif atif; 2390 struct radeon_atcs atcs; 2391 /* srbm instance registers */ 2392 struct lock srbm_mutex; 2393 /* clock, powergating flags */ 2394 u32 cg_flags; 2395 u32 pg_flags; 2396 2397 #ifdef PM_TODO 2398 struct dev_pm_domain vga_pm_domain; 2399 #endif 2400 bool have_disp_power_ref; 2401 u32 px_quirk_flags; 2402 2403 /* tracking pinned memory */ 2404 u64 vram_pin_size; 2405 u64 gart_pin_size; 2406 }; 2407 2408 bool radeon_is_px(struct drm_device *dev); 2409 int radeon_device_init(struct radeon_device *rdev, 2410 struct drm_device *ddev, 2411 struct pci_dev *pdev, 2412 uint32_t flags); 2413 void radeon_device_fini(struct radeon_device *rdev); 2414 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2415 2416 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2417 bool always_indirect); 2418 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2419 bool always_indirect); 2420 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2421 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2422 2423 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2424 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2425 2426 /* 2427 * Cast helper 2428 */ 2429 #define to_radeon_fence(p) ((struct radeon_fence *)(p)) 2430 2431 /* 2432 * Registers read & write functions. 2433 */ 2434 #define RREG8(reg) bus_read_1((rdev->rmmio), (reg)) 2435 #define WREG8(reg, v) bus_write_1((rdev->rmmio), (reg), v) 2436 #define RREG16(reg) bus_read_2((rdev->rmmio), (reg)) 2437 #define WREG16(reg, v) bus_write_2((rdev->rmmio), (reg), v) 2438 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2439 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2440 #define DREG32(reg) DRM_INFO("REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) 2441 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2442 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2443 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2444 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2445 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2446 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2447 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2448 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2449 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2450 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2451 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2452 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2453 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2454 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2455 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2456 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2457 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2458 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2459 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2460 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2461 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2462 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2463 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2464 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2465 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2466 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2467 #define WREG32_P(reg, val, mask) \ 2468 do { \ 2469 uint32_t tmp_ = RREG32(reg); \ 2470 tmp_ &= (mask); \ 2471 tmp_ |= ((val) & ~(mask)); \ 2472 WREG32(reg, tmp_); \ 2473 } while (0) 2474 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2475 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2476 #define WREG32_PLL_P(reg, val, mask) \ 2477 do { \ 2478 uint32_t tmp_ = RREG32_PLL(reg); \ 2479 tmp_ &= (mask); \ 2480 tmp_ |= ((val) & ~(mask)); \ 2481 WREG32_PLL(reg, tmp_); \ 2482 } while (0) 2483 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2484 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2485 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2486 2487 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2488 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2489 2490 /* 2491 * Indirect registers accessor 2492 */ 2493 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 2494 { 2495 uint32_t r; 2496 2497 spin_lock(&rdev->pcie_idx_lock); 2498 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2499 r = RREG32(RADEON_PCIE_DATA); 2500 spin_unlock(&rdev->pcie_idx_lock); 2501 return r; 2502 } 2503 2504 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2505 { 2506 spin_lock(&rdev->pcie_idx_lock); 2507 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2508 WREG32(RADEON_PCIE_DATA, (v)); 2509 spin_unlock(&rdev->pcie_idx_lock); 2510 } 2511 2512 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) 2513 { 2514 u32 r; 2515 2516 spin_lock(&rdev->smc_idx_lock); 2517 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2518 r = RREG32(TN_SMC_IND_DATA_0); 2519 spin_unlock(&rdev->smc_idx_lock); 2520 return r; 2521 } 2522 2523 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2524 { 2525 spin_lock(&rdev->smc_idx_lock); 2526 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2527 WREG32(TN_SMC_IND_DATA_0, (v)); 2528 spin_unlock(&rdev->smc_idx_lock); 2529 } 2530 2531 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) 2532 { 2533 u32 r; 2534 2535 spin_lock(&rdev->rcu_idx_lock); 2536 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2537 r = RREG32(R600_RCU_DATA); 2538 spin_unlock(&rdev->rcu_idx_lock); 2539 return r; 2540 } 2541 2542 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2543 { 2544 spin_lock(&rdev->rcu_idx_lock); 2545 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2546 WREG32(R600_RCU_DATA, (v)); 2547 spin_unlock(&rdev->rcu_idx_lock); 2548 } 2549 2550 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) 2551 { 2552 u32 r; 2553 2554 spin_lock(&rdev->cg_idx_lock); 2555 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2556 r = RREG32(EVERGREEN_CG_IND_DATA); 2557 spin_unlock(&rdev->cg_idx_lock); 2558 return r; 2559 } 2560 2561 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2562 { 2563 spin_lock(&rdev->cg_idx_lock); 2564 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2565 WREG32(EVERGREEN_CG_IND_DATA, (v)); 2566 spin_unlock(&rdev->cg_idx_lock); 2567 } 2568 2569 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg) 2570 { 2571 u32 r; 2572 2573 spin_lock(&rdev->pif_idx_lock); 2574 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2575 r = RREG32(EVERGREEN_PIF_PHY0_DATA); 2576 spin_unlock(&rdev->pif_idx_lock); 2577 return r; 2578 } 2579 2580 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2581 { 2582 spin_lock(&rdev->pif_idx_lock); 2583 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2584 WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); 2585 spin_unlock(&rdev->pif_idx_lock); 2586 } 2587 2588 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg) 2589 { 2590 u32 r; 2591 2592 spin_lock(&rdev->pif_idx_lock); 2593 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2594 r = RREG32(EVERGREEN_PIF_PHY1_DATA); 2595 spin_unlock(&rdev->pif_idx_lock); 2596 return r; 2597 } 2598 2599 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2600 { 2601 spin_lock(&rdev->pif_idx_lock); 2602 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2603 WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); 2604 spin_unlock(&rdev->pif_idx_lock); 2605 } 2606 2607 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) 2608 { 2609 u32 r; 2610 2611 spin_lock(&rdev->uvd_idx_lock); 2612 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2613 r = RREG32(R600_UVD_CTX_DATA); 2614 spin_unlock(&rdev->uvd_idx_lock); 2615 return r; 2616 } 2617 2618 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2619 { 2620 spin_lock(&rdev->uvd_idx_lock); 2621 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2622 WREG32(R600_UVD_CTX_DATA, (v)); 2623 spin_unlock(&rdev->uvd_idx_lock); 2624 } 2625 2626 2627 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg) 2628 { 2629 u32 r; 2630 2631 spin_lock(&rdev->didt_idx_lock); 2632 WREG32(CIK_DIDT_IND_INDEX, (reg)); 2633 r = RREG32(CIK_DIDT_IND_DATA); 2634 spin_unlock(&rdev->didt_idx_lock); 2635 return r; 2636 } 2637 2638 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2639 { 2640 spin_lock(&rdev->didt_idx_lock); 2641 WREG32(CIK_DIDT_IND_INDEX, (reg)); 2642 WREG32(CIK_DIDT_IND_DATA, (v)); 2643 spin_unlock(&rdev->didt_idx_lock); 2644 } 2645 2646 void r100_pll_errata_after_index(struct radeon_device *rdev); 2647 2648 2649 /* 2650 * ASICs helpers. 2651 */ 2652 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2653 (rdev->pdev->device == 0x5969)) 2654 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2655 (rdev->family == CHIP_RV200) || \ 2656 (rdev->family == CHIP_RS100) || \ 2657 (rdev->family == CHIP_RS200) || \ 2658 (rdev->family == CHIP_RV250) || \ 2659 (rdev->family == CHIP_RV280) || \ 2660 (rdev->family == CHIP_RS300)) 2661 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2662 (rdev->family == CHIP_RV350) || \ 2663 (rdev->family == CHIP_R350) || \ 2664 (rdev->family == CHIP_RV380) || \ 2665 (rdev->family == CHIP_R420) || \ 2666 (rdev->family == CHIP_R423) || \ 2667 (rdev->family == CHIP_RV410) || \ 2668 (rdev->family == CHIP_RS400) || \ 2669 (rdev->family == CHIP_RS480)) 2670 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 2671 (rdev->ddev->pdev->device == 0x9443) || \ 2672 (rdev->ddev->pdev->device == 0x944B) || \ 2673 (rdev->ddev->pdev->device == 0x9506) || \ 2674 (rdev->ddev->pdev->device == 0x9509) || \ 2675 (rdev->ddev->pdev->device == 0x950F) || \ 2676 (rdev->ddev->pdev->device == 0x689C) || \ 2677 (rdev->ddev->pdev->device == 0x689D)) 2678 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2679 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2680 (rdev->family == CHIP_RS690) || \ 2681 (rdev->family == CHIP_RS740) || \ 2682 (rdev->family >= CHIP_R600)) 2683 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2684 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2685 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2686 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2687 (rdev->flags & RADEON_IS_IGP)) 2688 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2689 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2690 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2691 (rdev->flags & RADEON_IS_IGP)) 2692 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2693 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2694 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2695 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2696 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2697 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2698 (rdev->family == CHIP_MULLINS)) 2699 2700 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ 2701 (rdev->ddev->pdev->device == 0x6850) || \ 2702 (rdev->ddev->pdev->device == 0x6858) || \ 2703 (rdev->ddev->pdev->device == 0x6859) || \ 2704 (rdev->ddev->pdev->device == 0x6840) || \ 2705 (rdev->ddev->pdev->device == 0x6841) || \ 2706 (rdev->ddev->pdev->device == 0x6842) || \ 2707 (rdev->ddev->pdev->device == 0x6843)) 2708 2709 /* 2710 * BIOS helpers. 2711 */ 2712 #define RBIOS8(i) (rdev->bios[i]) 2713 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2714 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2715 2716 int radeon_combios_init(struct radeon_device *rdev); 2717 void radeon_combios_fini(struct radeon_device *rdev); 2718 int radeon_atombios_init(struct radeon_device *rdev); 2719 void radeon_atombios_fini(struct radeon_device *rdev); 2720 2721 2722 /* 2723 * RING helpers. 2724 */ 2725 2726 /** 2727 * radeon_ring_write - write a value to the ring 2728 * 2729 * @ring: radeon_ring structure holding ring information 2730 * @v: dword (dw) value to write 2731 * 2732 * Write a value to the requested ring buffer (all asics). 2733 */ 2734 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2735 { 2736 if (ring->count_dw <= 0) 2737 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); 2738 2739 ring->ring[ring->wptr++] = v; 2740 ring->wptr &= ring->ptr_mask; 2741 ring->count_dw--; 2742 ring->ring_free_dw--; 2743 } 2744 2745 /* 2746 * ASICs macro. 2747 */ 2748 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2749 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2750 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2751 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2752 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2753 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2754 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 2755 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2756 #define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f)) 2757 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2758 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2759 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) 2760 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2761 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2762 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) 2763 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2764 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2765 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2766 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2767 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2768 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2769 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm)) 2770 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2771 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2772 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2773 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2774 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2775 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2776 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2777 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2778 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2779 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2780 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2781 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2782 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) 2783 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) 2784 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) 2785 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2786 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2787 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2788 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2789 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2790 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2791 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2792 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2793 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2794 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2795 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2796 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2797 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2798 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2799 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2800 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2801 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2802 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2803 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2804 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2805 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2806 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2807 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2808 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2809 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2810 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2811 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) 2812 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) 2813 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2814 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2815 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2816 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2817 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2818 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2819 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2820 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2821 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2822 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2823 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2824 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2825 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2826 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2827 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2828 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2829 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2830 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2831 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2832 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2833 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2834 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2835 2836 /* Common functions */ 2837 /* AGP */ 2838 extern int radeon_gpu_reset(struct radeon_device *rdev); 2839 extern void radeon_pci_config_reset(struct radeon_device *rdev); 2840 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2841 extern void radeon_agp_disable(struct radeon_device *rdev); 2842 extern int radeon_modeset_init(struct radeon_device *rdev); 2843 extern void radeon_modeset_fini(struct radeon_device *rdev); 2844 extern bool radeon_card_posted(struct radeon_device *rdev); 2845 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2846 extern void radeon_update_display_priority(struct radeon_device *rdev); 2847 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2848 extern void radeon_scratch_init(struct radeon_device *rdev); 2849 extern void radeon_wb_fini(struct radeon_device *rdev); 2850 extern int radeon_wb_init(struct radeon_device *rdev); 2851 extern void radeon_wb_disable(struct radeon_device *rdev); 2852 extern void radeon_surface_init(struct radeon_device *rdev); 2853 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2854 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2855 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2856 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2857 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2858 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2859 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2860 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2861 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2862 const u32 *registers, 2863 const u32 array_size); 2864 2865 /* 2866 * vm 2867 */ 2868 int radeon_vm_manager_init(struct radeon_device *rdev); 2869 void radeon_vm_manager_fini(struct radeon_device *rdev); 2870 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2871 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2872 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev, 2873 struct radeon_vm *vm, 2874 struct list_head *head); 2875 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2876 struct radeon_vm *vm, int ring); 2877 void radeon_vm_flush(struct radeon_device *rdev, 2878 struct radeon_vm *vm, 2879 int ring); 2880 void radeon_vm_fence(struct radeon_device *rdev, 2881 struct radeon_vm *vm, 2882 struct radeon_fence *fence); 2883 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2884 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2885 struct radeon_vm *vm); 2886 int radeon_vm_clear_freed(struct radeon_device *rdev, 2887 struct radeon_vm *vm); 2888 int radeon_vm_clear_invalids(struct radeon_device *rdev, 2889 struct radeon_vm *vm); 2890 int radeon_vm_bo_update(struct radeon_device *rdev, 2891 struct radeon_bo_va *bo_va, 2892 struct ttm_mem_reg *mem); 2893 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2894 struct radeon_bo *bo); 2895 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2896 struct radeon_bo *bo); 2897 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2898 struct radeon_vm *vm, 2899 struct radeon_bo *bo); 2900 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2901 struct radeon_bo_va *bo_va, 2902 uint64_t offset, 2903 uint32_t flags); 2904 void radeon_vm_bo_rmv(struct radeon_device *rdev, 2905 struct radeon_bo_va *bo_va); 2906 2907 /* audio */ 2908 void r600_audio_update_hdmi(void *arg, int pending); 2909 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2910 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2911 void r600_audio_enable(struct radeon_device *rdev, 2912 struct r600_audio_pin *pin, 2913 u8 enable_mask); 2914 void dce6_audio_enable(struct radeon_device *rdev, 2915 struct r600_audio_pin *pin, 2916 u8 enable_mask); 2917 2918 /* 2919 * R600 vram scratch functions 2920 */ 2921 int r600_vram_scratch_init(struct radeon_device *rdev); 2922 void r600_vram_scratch_fini(struct radeon_device *rdev); 2923 2924 /* 2925 * r600 cs checking helper 2926 */ 2927 unsigned r600_mip_minify(unsigned size, unsigned level); 2928 bool r600_fmt_is_valid_color(u32 format); 2929 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2930 int r600_fmt_get_blocksize(u32 format); 2931 int r600_fmt_get_nblocksx(u32 format, u32 w); 2932 int r600_fmt_get_nblocksy(u32 format, u32 h); 2933 2934 /* 2935 * r600 functions used by radeon_encoder.c 2936 */ 2937 struct radeon_hdmi_acr { 2938 u32 clock; 2939 2940 int n_32khz; 2941 int cts_32khz; 2942 2943 int n_44_1khz; 2944 int cts_44_1khz; 2945 2946 int n_48khz; 2947 int cts_48khz; 2948 2949 }; 2950 2951 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 2952 2953 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 2954 u32 tiling_pipe_num, 2955 u32 max_rb_num, 2956 u32 total_max_rb_num, 2957 u32 enabled_rb_mask); 2958 2959 /* 2960 * evergreen functions used by radeon_encoder.c 2961 */ 2962 2963 extern int ni_init_microcode(struct radeon_device *rdev); 2964 extern int ni_mc_load_microcode(struct radeon_device *rdev); 2965 extern void ni_fini_microcode(struct radeon_device *rdev); 2966 2967 /* radeon_acpi.c */ 2968 extern int radeon_acpi_init(struct radeon_device *rdev); 2969 extern void radeon_acpi_fini(struct radeon_device *rdev); 2970 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 2971 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 2972 u8 perf_req, bool advertise); 2973 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 2974 2975 /* Prototypes added by @dumbbell. */ 2976 2977 /* atombios_encoders.c */ 2978 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 2979 struct drm_connector *drm_connector); 2980 void radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, 2981 uint32_t supported_device, u16 caps); 2982 2983 /* radeon_atombios.c */ 2984 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 2985 struct drm_display_mode *mode); 2986 2987 /* radeon_legacy_encoders.c */ 2988 void radeon_add_legacy_encoder(struct drm_device *dev, 2989 uint32_t encoder_enum, uint32_t supported_device); 2990 void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder, 2991 struct drm_connector *drm_connector); 2992 2993 /* radeon_pm.c */ 2994 void radeon_pm_acpi_event_handler(struct radeon_device *rdev); 2995 2996 /* radeon_ttm.c */ 2997 int radeon_ttm_init(struct radeon_device *rdev); 2998 void radeon_ttm_fini(struct radeon_device *rdev); 2999 3000 /* r600.c */ 3001 int r600_ih_ring_alloc(struct radeon_device *rdev); 3002 void r600_ih_ring_fini(struct radeon_device *rdev); 3003 3004 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 3005 struct radeon_cs_packet *pkt, 3006 unsigned idx); 3007 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 3008 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 3009 struct radeon_cs_packet *pkt); 3010 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 3011 struct radeon_cs_reloc **cs_reloc, 3012 int nomm); 3013 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 3014 uint32_t *vline_start_end, 3015 uint32_t *vline_status); 3016 3017 #include "radeon_object.h" 3018 3019 #endif 3020