1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_H__ 29 #define __RADEON_H__ 30 31 /* TODO: Here are things that needs to be done : 32 * - surface allocator & initializer : (bit like scratch reg) should 33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 34 * related to surface 35 * - WB : write back stuff (do it bit like scratch reg things) 36 * - Vblank : look at Jesse's rework and what we should do 37 * - r600/r700: gart & cp 38 * - cs : clean cs ioctl use bitmap & things like that. 39 * - power management stuff 40 * - Barrier in gart code 41 * - Unmappabled vram ? 42 * - TESTING, TESTING, TESTING 43 */ 44 45 /* Initialization path: 46 * We expect that acceleration initialization might fail for various 47 * reasons even thought we work hard to make it works on most 48 * configurations. In order to still have a working userspace in such 49 * situation the init path must succeed up to the memory controller 50 * initialization point. Failure before this point are considered as 51 * fatal error. Here is the init callchain : 52 * radeon_device_init perform common structure, mutex initialization 53 * asic_init setup the GPU memory layout and perform all 54 * one time initialization (failure in this 55 * function are considered fatal) 56 * asic_startup setup the GPU acceleration, in order to 57 * follow guideline the first thing this 58 * function should do is setting the GPU 59 * memory controller (only MC setup failure 60 * are considered as fatal) 61 */ 62 63 #include <contrib/dev/acpica/source/include/acpi.h> 64 #include <dev/acpica/acpivar.h> 65 66 #include <linux/atomic.h> 67 #include <linux/wait.h> 68 #include <linux/list.h> 69 #include <linux/kref.h> 70 #include <linux/interval_tree.h> 71 #include <linux/hashtable.h> 72 #include <linux/fence.h> 73 74 #include <ttm/ttm_bo_api.h> 75 #include <ttm/ttm_bo_driver.h> 76 #include <ttm/ttm_placement.h> 77 #include <ttm/ttm_module.h> 78 #include <ttm/ttm_execbuf_util.h> 79 80 #include <drm/drm_gem.h> 81 82 #include "radeon_family.h" 83 #include "radeon_mode.h" 84 #include "radeon_reg.h" 85 86 /* 87 * Modules parameters. 88 */ 89 extern int radeon_no_wb; 90 extern int radeon_modeset; 91 extern int radeon_dynclks; 92 extern int radeon_r4xx_atom; 93 extern int radeon_agpmode; 94 extern int radeon_vram_limit; 95 extern int radeon_gart_size; 96 extern int radeon_benchmarking; 97 extern int radeon_testing; 98 extern int radeon_connector_table; 99 extern int radeon_tv; 100 extern int radeon_audio; 101 extern int radeon_disp_priority; 102 extern int radeon_hw_i2c; 103 extern int radeon_pcie_gen2; 104 extern int radeon_msi; 105 extern int radeon_lockup_timeout; 106 extern int radeon_fastfb; 107 extern int radeon_dpm; 108 extern int radeon_aspm; 109 extern int radeon_runtime_pm; 110 extern int radeon_hard_reset; 111 extern int radeon_vm_size; 112 extern int radeon_vm_block_size; 113 extern int radeon_deep_color; 114 extern int radeon_use_pflipirq; 115 extern int radeon_bapm; 116 extern int radeon_backlight; 117 extern int radeon_auxch; 118 extern int radeon_mst; 119 extern int radeon_uvd; 120 extern int radeon_vce; 121 122 /* 123 * Copy from radeon_drv.h so we don't have to include both and have conflicting 124 * symbol; 125 */ 126 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 127 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 128 #define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */ 129 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 130 #define RADEON_IB_POOL_SIZE 16 131 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 132 #define RADEONFB_CONN_LIMIT 4 133 #define RADEON_BIOS_NUM_SCRATCH 8 134 135 /* internal ring indices */ 136 /* r1xx+ has gfx CP ring */ 137 #define RADEON_RING_TYPE_GFX_INDEX 0 138 139 /* cayman has 2 compute CP rings */ 140 #define CAYMAN_RING_TYPE_CP1_INDEX 1 141 #define CAYMAN_RING_TYPE_CP2_INDEX 2 142 143 /* R600+ has an async dma ring */ 144 #define R600_RING_TYPE_DMA_INDEX 3 145 /* cayman add a second async dma ring */ 146 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 147 148 /* R600+ */ 149 #define R600_RING_TYPE_UVD_INDEX 5 150 151 /* TN+ */ 152 #define TN_RING_TYPE_VCE1_INDEX 6 153 #define TN_RING_TYPE_VCE2_INDEX 7 154 155 /* max number of rings */ 156 #define RADEON_NUM_RINGS 8 157 158 /* number of hw syncs before falling back on blocking */ 159 #define RADEON_NUM_SYNCS 4 160 161 /* hardcode those limit for now */ 162 #define RADEON_VA_IB_OFFSET (1 << 20) 163 #define RADEON_VA_RESERVED_SIZE (8 << 20) 164 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 165 166 /* hard reset data */ 167 #define RADEON_ASIC_RESET_DATA 0x39d5e86b 168 169 /* reset flags */ 170 #define RADEON_RESET_GFX (1 << 0) 171 #define RADEON_RESET_COMPUTE (1 << 1) 172 #define RADEON_RESET_DMA (1 << 2) 173 #define RADEON_RESET_CP (1 << 3) 174 #define RADEON_RESET_GRBM (1 << 4) 175 #define RADEON_RESET_DMA1 (1 << 5) 176 #define RADEON_RESET_RLC (1 << 6) 177 #define RADEON_RESET_SEM (1 << 7) 178 #define RADEON_RESET_IH (1 << 8) 179 #define RADEON_RESET_VMC (1 << 9) 180 #define RADEON_RESET_MC (1 << 10) 181 #define RADEON_RESET_DISPLAY (1 << 11) 182 183 /* CG block flags */ 184 #define RADEON_CG_BLOCK_GFX (1 << 0) 185 #define RADEON_CG_BLOCK_MC (1 << 1) 186 #define RADEON_CG_BLOCK_SDMA (1 << 2) 187 #define RADEON_CG_BLOCK_UVD (1 << 3) 188 #define RADEON_CG_BLOCK_VCE (1 << 4) 189 #define RADEON_CG_BLOCK_HDP (1 << 5) 190 #define RADEON_CG_BLOCK_BIF (1 << 6) 191 192 /* CG flags */ 193 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 194 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 195 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 196 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 197 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 198 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 199 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 200 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 201 #define RADEON_CG_SUPPORT_MC_LS (1 << 8) 202 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 203 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 204 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 205 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 206 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 207 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 208 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 209 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 210 211 /* PG flags */ 212 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 213 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 214 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 215 #define RADEON_PG_SUPPORT_UVD (1 << 3) 216 #define RADEON_PG_SUPPORT_VCE (1 << 4) 217 #define RADEON_PG_SUPPORT_CP (1 << 5) 218 #define RADEON_PG_SUPPORT_GDS (1 << 6) 219 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 220 #define RADEON_PG_SUPPORT_SDMA (1 << 8) 221 #define RADEON_PG_SUPPORT_ACP (1 << 9) 222 #define RADEON_PG_SUPPORT_SAMU (1 << 10) 223 224 /* max cursor sizes (in pixels) */ 225 #define CURSOR_WIDTH 64 226 #define CURSOR_HEIGHT 64 227 228 #define CIK_CURSOR_WIDTH 128 229 #define CIK_CURSOR_HEIGHT 128 230 231 /* 232 * Errata workarounds. 233 */ 234 enum radeon_pll_errata { 235 CHIP_ERRATA_R300_CG = 0x00000001, 236 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 237 CHIP_ERRATA_PLL_DELAY = 0x00000004 238 }; 239 240 241 struct radeon_device; 242 243 244 /* 245 * BIOS. 246 */ 247 bool radeon_get_bios(struct radeon_device *rdev); 248 249 /* 250 * Dummy page 251 */ 252 struct radeon_dummy_page { 253 uint64_t entry; 254 struct drm_dma_handle *dmah; 255 dma_addr_t addr; 256 }; 257 int radeon_dummy_page_init(struct radeon_device *rdev); 258 void radeon_dummy_page_fini(struct radeon_device *rdev); 259 260 261 /* 262 * Clocks 263 */ 264 struct radeon_clock { 265 struct radeon_pll p1pll; 266 struct radeon_pll p2pll; 267 struct radeon_pll dcpll; 268 struct radeon_pll spll; 269 struct radeon_pll mpll; 270 /* 10 Khz units */ 271 uint32_t default_mclk; 272 uint32_t default_sclk; 273 uint32_t default_dispclk; 274 uint32_t current_dispclk; 275 uint32_t dp_extclk; 276 uint32_t max_pixel_clock; 277 uint32_t vco_freq; 278 }; 279 280 /* 281 * Power management 282 */ 283 int radeon_pm_init(struct radeon_device *rdev); 284 int radeon_pm_late_init(struct radeon_device *rdev); 285 void radeon_pm_fini(struct radeon_device *rdev); 286 void radeon_pm_compute_clocks(struct radeon_device *rdev); 287 void radeon_pm_suspend(struct radeon_device *rdev); 288 void radeon_pm_resume(struct radeon_device *rdev); 289 void radeon_combios_get_power_modes(struct radeon_device *rdev); 290 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 291 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 292 u8 clock_type, 293 u32 clock, 294 bool strobe_mode, 295 struct atom_clock_dividers *dividers); 296 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 297 u32 clock, 298 bool strobe_mode, 299 struct atom_mpll_param *mpll_param); 300 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 301 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 302 u16 voltage_level, u8 voltage_type, 303 u32 *gpio_value, u32 *gpio_mask); 304 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 305 u32 eng_clock, u32 mem_clock); 306 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 307 u8 voltage_type, u16 *voltage_step); 308 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 309 u16 voltage_id, u16 *voltage); 310 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 311 u16 *voltage, 312 u16 leakage_idx); 313 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 314 u16 *leakage_id); 315 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 316 u16 *vddc, u16 *vddci, 317 u16 virtual_voltage_id, 318 u16 vbios_voltage_id); 319 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 320 u16 virtual_voltage_id, 321 u16 *voltage); 322 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 323 u8 voltage_type, 324 u16 nominal_voltage, 325 u16 *true_voltage); 326 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 327 u8 voltage_type, u16 *min_voltage); 328 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 329 u8 voltage_type, u16 *max_voltage); 330 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 331 u8 voltage_type, u8 voltage_mode, 332 struct atom_voltage_table *voltage_table); 333 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 334 u8 voltage_type, u8 voltage_mode); 335 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 336 u8 voltage_type, 337 u8 *svd_gpio_id, u8 *svc_gpio_id); 338 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 339 u32 mem_clock); 340 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 341 u32 mem_clock); 342 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 343 u8 module_index, 344 struct atom_mc_reg_table *reg_table); 345 int radeon_atom_get_memory_info(struct radeon_device *rdev, 346 u8 module_index, struct atom_memory_info *mem_info); 347 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 348 bool gddr5, u8 module_index, 349 struct atom_memory_clock_range_table *mclk_range_table); 350 void rs690_pm_info(struct radeon_device *rdev); 351 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 352 unsigned *bankh, unsigned *mtaspect, 353 unsigned *tile_split); 354 355 /* 356 * Fences. 357 */ 358 struct radeon_fence_driver { 359 struct radeon_device *rdev; 360 uint32_t scratch_reg; 361 uint64_t gpu_addr; 362 volatile uint32_t *cpu_addr; 363 /* sync_seq is protected by ring emission lock */ 364 uint64_t sync_seq[RADEON_NUM_RINGS]; 365 atomic64_t last_seq; 366 bool initialized, delayed_irq; 367 struct delayed_work lockup_work; 368 }; 369 370 struct radeon_fence { 371 struct fence base; 372 373 struct radeon_device *rdev; 374 uint64_t seq; 375 /* RB, DMA, etc. */ 376 unsigned ring; 377 bool is_vm_update; 378 379 wait_queue_t fence_wake; 380 }; 381 382 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 383 int radeon_fence_driver_init(struct radeon_device *rdev); 384 void radeon_fence_driver_fini(struct radeon_device *rdev); 385 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); 386 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 387 void radeon_fence_process(struct radeon_device *rdev, int ring); 388 bool radeon_fence_signaled(struct radeon_fence *fence); 389 long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout); 390 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 391 int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 392 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 393 int radeon_fence_wait_any(struct radeon_device *rdev, 394 struct radeon_fence **fences, 395 bool intr); 396 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 397 void radeon_fence_unref(struct radeon_fence **fence); 398 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 399 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 400 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 401 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 402 struct radeon_fence *b) 403 { 404 if (!a) { 405 return b; 406 } 407 408 if (!b) { 409 return a; 410 } 411 412 BUG_ON(a->ring != b->ring); 413 414 if (a->seq > b->seq) { 415 return a; 416 } else { 417 return b; 418 } 419 } 420 421 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 422 struct radeon_fence *b) 423 { 424 if (!a) { 425 return false; 426 } 427 428 if (!b) { 429 return true; 430 } 431 432 BUG_ON(a->ring != b->ring); 433 434 return a->seq < b->seq; 435 } 436 437 /* 438 * Tiling registers 439 */ 440 struct radeon_surface_reg { 441 struct radeon_bo *bo; 442 }; 443 444 #define RADEON_GEM_MAX_SURFACES 8 445 446 /* 447 * TTM. 448 */ 449 struct radeon_mman { 450 struct ttm_bo_global_ref bo_global_ref; 451 struct drm_global_reference mem_global_ref; 452 struct ttm_bo_device bdev; 453 bool mem_global_referenced; 454 bool initialized; 455 456 #if defined(CONFIG_DEBUG_FS) 457 struct dentry *vram; 458 struct dentry *gtt; 459 #endif 460 }; 461 462 struct radeon_bo_list { 463 struct radeon_bo *robj; 464 struct ttm_validate_buffer tv; 465 uint64_t gpu_offset; 466 unsigned prefered_domains; 467 unsigned allowed_domains; 468 uint32_t tiling_flags; 469 }; 470 471 /* bo virtual address in a specific vm */ 472 struct radeon_bo_va { 473 /* protected by bo being reserved */ 474 struct list_head bo_list; 475 uint32_t flags; 476 struct radeon_fence *last_pt_update; 477 unsigned ref_count; 478 479 /* protected by vm mutex */ 480 struct interval_tree_node it; 481 struct list_head vm_status; 482 483 /* constant after initialization */ 484 struct radeon_vm *vm; 485 struct radeon_bo *bo; 486 }; 487 488 struct radeon_bo { 489 /* Protected by gem.mutex */ 490 struct list_head list; 491 /* Protected by tbo.reserved */ 492 u32 initial_domain; 493 struct ttm_place placements[4]; 494 struct ttm_placement placement; 495 struct ttm_buffer_object tbo; 496 struct ttm_bo_kmap_obj kmap; 497 u32 flags; 498 unsigned pin_count; 499 void *kptr; 500 u32 tiling_flags; 501 u32 pitch; 502 int surface_reg; 503 /* list of all virtual address to which this bo 504 * is associated to 505 */ 506 struct list_head va; 507 /* Constant after initialization */ 508 struct radeon_device *rdev; 509 struct drm_gem_object gem_base; 510 511 struct ttm_bo_kmap_obj dma_buf_vmap; 512 pid_t pid; 513 514 struct radeon_mn *mn; 515 struct list_head mn_list; 516 }; 517 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 518 519 int radeon_gem_debugfs_init(struct radeon_device *rdev); 520 521 /* sub-allocation manager, it has to be protected by another lock. 522 * By conception this is an helper for other part of the driver 523 * like the indirect buffer or semaphore, which both have their 524 * locking. 525 * 526 * Principe is simple, we keep a list of sub allocation in offset 527 * order (first entry has offset == 0, last entry has the highest 528 * offset). 529 * 530 * When allocating new object we first check if there is room at 531 * the end total_size - (last_object_offset + last_object_size) >= 532 * alloc_size. If so we allocate new object there. 533 * 534 * When there is not enough room at the end, we start waiting for 535 * each sub object until we reach object_offset+object_size >= 536 * alloc_size, this object then become the sub object we return. 537 * 538 * Alignment can't be bigger than page size. 539 * 540 * Hole are not considered for allocation to keep things simple. 541 * Assumption is that there won't be hole (all object on same 542 * alignment). 543 */ 544 struct radeon_sa_manager { 545 wait_queue_head_t wq; 546 struct radeon_bo *bo; 547 struct list_head *hole; 548 struct list_head flist[RADEON_NUM_RINGS]; 549 struct list_head olist; 550 unsigned size; 551 u64 gpu_addr; 552 void *cpu_ptr; 553 uint32_t domain; 554 uint32_t align; 555 }; 556 557 struct radeon_sa_bo; 558 559 /* sub-allocation buffer */ 560 struct radeon_sa_bo { 561 struct list_head olist; 562 struct list_head flist; 563 struct radeon_sa_manager *manager; 564 unsigned soffset; 565 unsigned eoffset; 566 struct radeon_fence *fence; 567 }; 568 569 /* 570 * GEM objects. 571 */ 572 struct radeon_gem { 573 struct lock mutex; 574 struct list_head objects; 575 }; 576 577 int radeon_gem_init(struct radeon_device *rdev); 578 void radeon_gem_fini(struct radeon_device *rdev); 579 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, 580 int alignment, int initial_domain, 581 u32 flags, bool kernel, 582 struct drm_gem_object **obj); 583 584 int radeon_mode_dumb_create(struct drm_file *file_priv, 585 struct drm_device *dev, 586 struct drm_mode_create_dumb *args); 587 int radeon_mode_dumb_mmap(struct drm_file *filp, 588 struct drm_device *dev, 589 uint32_t handle, uint64_t *offset_p); 590 591 /* 592 * Semaphores. 593 */ 594 struct radeon_semaphore { 595 struct radeon_sa_bo *sa_bo; 596 signed waiters; 597 uint64_t gpu_addr; 598 }; 599 600 int radeon_semaphore_create(struct radeon_device *rdev, 601 struct radeon_semaphore **semaphore); 602 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 603 struct radeon_semaphore *semaphore); 604 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 605 struct radeon_semaphore *semaphore); 606 void radeon_semaphore_free(struct radeon_device *rdev, 607 struct radeon_semaphore **semaphore, 608 struct radeon_fence *fence); 609 610 /* 611 * Synchronization 612 */ 613 struct radeon_sync { 614 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS]; 615 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 616 struct radeon_fence *last_vm_update; 617 }; 618 619 void radeon_sync_create(struct radeon_sync *sync); 620 void radeon_sync_fence(struct radeon_sync *sync, 621 struct radeon_fence *fence); 622 int radeon_sync_resv(struct radeon_device *rdev, 623 struct radeon_sync *sync, 624 struct reservation_object *resv, 625 bool shared); 626 int radeon_sync_rings(struct radeon_device *rdev, 627 struct radeon_sync *sync, 628 int waiting_ring); 629 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync, 630 struct radeon_fence *fence); 631 632 /* 633 * GART structures, functions & helpers 634 */ 635 struct radeon_mc; 636 637 #define RADEON_GPU_PAGE_SIZE 4096 638 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 639 #define RADEON_GPU_PAGE_SHIFT 12 640 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 641 642 #define RADEON_GART_PAGE_DUMMY 0 643 #define RADEON_GART_PAGE_VALID (1 << 0) 644 #define RADEON_GART_PAGE_READ (1 << 1) 645 #define RADEON_GART_PAGE_WRITE (1 << 2) 646 #define RADEON_GART_PAGE_SNOOP (1 << 3) 647 648 struct radeon_gart { 649 struct drm_dma_handle *dmah; 650 dma_addr_t table_addr; 651 struct radeon_bo *robj; 652 void *ptr; 653 unsigned num_gpu_pages; 654 unsigned num_cpu_pages; 655 unsigned table_size; 656 struct page **pages; 657 uint64_t *pages_entry; 658 bool ready; 659 }; 660 661 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 662 void radeon_gart_table_ram_free(struct radeon_device *rdev); 663 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 664 void radeon_gart_table_vram_free(struct radeon_device *rdev); 665 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 666 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 667 int radeon_gart_init(struct radeon_device *rdev); 668 void radeon_gart_fini(struct radeon_device *rdev); 669 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 670 int pages); 671 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 672 int pages, struct page **pagelist, 673 dma_addr_t *dma_addr, uint32_t flags); 674 675 676 /* 677 * GPU MC structures, functions & helpers 678 */ 679 struct radeon_mc { 680 resource_size_t aper_size; 681 resource_size_t aper_base; 682 resource_size_t agp_base; 683 /* for some chips with <= 32MB we need to lie 684 * about vram size near mc fb location */ 685 u64 mc_vram_size; 686 u64 visible_vram_size; 687 u64 gtt_size; 688 u64 gtt_start; 689 u64 gtt_end; 690 u64 vram_start; 691 u64 vram_end; 692 unsigned vram_width; 693 u64 real_vram_size; 694 int vram_mtrr; 695 bool vram_is_ddr; 696 bool igp_sideport_enabled; 697 u64 gtt_base_align; 698 u64 mc_mask; 699 }; 700 701 bool radeon_combios_sideport_present(struct radeon_device *rdev); 702 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 703 704 /* 705 * GPU scratch registers structures, functions & helpers 706 */ 707 struct radeon_scratch { 708 unsigned num_reg; 709 uint32_t reg_base; 710 bool free[32]; 711 uint32_t reg[32]; 712 }; 713 714 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 715 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 716 717 /* 718 * GPU doorbell structures, functions & helpers 719 */ 720 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 721 722 struct radeon_doorbell { 723 /* doorbell mmio */ 724 resource_size_t base; 725 resource_size_t size; 726 u32 __iomem *ptr; 727 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 728 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS); 729 }; 730 731 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 732 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 733 void radeon_doorbell_get_kfd_info(struct radeon_device *rdev, 734 phys_addr_t *aperture_base, 735 size_t *aperture_size, 736 size_t *start_offset); 737 738 /* 739 * IRQS. 740 */ 741 742 struct radeon_flip_work { 743 struct work_struct flip_work; 744 struct work_struct unpin_work; 745 struct radeon_device *rdev; 746 int crtc_id; 747 u32 target_vblank; 748 uint64_t base; 749 struct drm_pending_vblank_event *event; 750 struct radeon_bo *old_rbo; 751 struct fence *fence; 752 bool async; 753 }; 754 755 struct r500_irq_stat_regs { 756 u32 disp_int; 757 u32 hdmi0_status; 758 }; 759 760 struct r600_irq_stat_regs { 761 u32 disp_int; 762 u32 disp_int_cont; 763 u32 disp_int_cont2; 764 u32 d1grph_int; 765 u32 d2grph_int; 766 u32 hdmi0_status; 767 u32 hdmi1_status; 768 }; 769 770 struct evergreen_irq_stat_regs { 771 u32 disp_int; 772 u32 disp_int_cont; 773 u32 disp_int_cont2; 774 u32 disp_int_cont3; 775 u32 disp_int_cont4; 776 u32 disp_int_cont5; 777 u32 d1grph_int; 778 u32 d2grph_int; 779 u32 d3grph_int; 780 u32 d4grph_int; 781 u32 d5grph_int; 782 u32 d6grph_int; 783 u32 afmt_status1; 784 u32 afmt_status2; 785 u32 afmt_status3; 786 u32 afmt_status4; 787 u32 afmt_status5; 788 u32 afmt_status6; 789 }; 790 791 struct cik_irq_stat_regs { 792 u32 disp_int; 793 u32 disp_int_cont; 794 u32 disp_int_cont2; 795 u32 disp_int_cont3; 796 u32 disp_int_cont4; 797 u32 disp_int_cont5; 798 u32 disp_int_cont6; 799 u32 d1grph_int; 800 u32 d2grph_int; 801 u32 d3grph_int; 802 u32 d4grph_int; 803 u32 d5grph_int; 804 u32 d6grph_int; 805 }; 806 807 union radeon_irq_stat_regs { 808 struct r500_irq_stat_regs r500; 809 struct r600_irq_stat_regs r600; 810 struct evergreen_irq_stat_regs evergreen; 811 struct cik_irq_stat_regs cik; 812 }; 813 814 struct radeon_irq { 815 bool installed; 816 struct lock lock; 817 atomic_t ring_int[RADEON_NUM_RINGS]; 818 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 819 atomic_t pflip[RADEON_MAX_CRTCS]; 820 wait_queue_head_t vblank_queue; 821 bool hpd[RADEON_MAX_HPD_PINS]; 822 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 823 union radeon_irq_stat_regs stat_regs; 824 bool dpm_thermal; 825 }; 826 827 int radeon_irq_kms_init(struct radeon_device *rdev); 828 void radeon_irq_kms_fini(struct radeon_device *rdev); 829 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 830 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring); 831 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 832 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 833 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 834 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 835 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 836 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 837 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 838 839 /* 840 * CP & rings. 841 */ 842 843 struct radeon_ib { 844 struct radeon_sa_bo *sa_bo; 845 uint32_t length_dw; 846 uint64_t gpu_addr; 847 uint32_t *ptr; 848 int ring; 849 struct radeon_fence *fence; 850 struct radeon_vm *vm; 851 bool is_const_ib; 852 struct radeon_sync sync; 853 }; 854 855 struct radeon_ring { 856 struct radeon_bo *ring_obj; 857 volatile uint32_t *ring; 858 unsigned rptr_offs; 859 unsigned rptr_save_reg; 860 u64 next_rptr_gpu_addr; 861 volatile u32 *next_rptr_cpu_addr; 862 unsigned wptr; 863 unsigned wptr_old; 864 unsigned ring_size; 865 unsigned ring_free_dw; 866 int count_dw; 867 atomic_t last_rptr; 868 atomic64_t last_activity; 869 uint64_t gpu_addr; 870 uint32_t align_mask; 871 uint32_t ptr_mask; 872 bool ready; 873 u32 nop; 874 u32 idx; 875 u64 last_semaphore_signal_addr; 876 u64 last_semaphore_wait_addr; 877 /* for CIK queues */ 878 u32 me; 879 u32 pipe; 880 u32 queue; 881 struct radeon_bo *mqd_obj; 882 u32 doorbell_index; 883 unsigned wptr_offs; 884 }; 885 886 struct radeon_mec { 887 struct radeon_bo *hpd_eop_obj; 888 u64 hpd_eop_gpu_addr; 889 u32 num_pipe; 890 u32 num_mec; 891 u32 num_queue; 892 }; 893 894 /* 895 * VM 896 */ 897 898 /* maximum number of VMIDs */ 899 #define RADEON_NUM_VM 16 900 901 /* number of entries in page table */ 902 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) 903 904 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 905 #define RADEON_VM_PTB_ALIGN_SIZE 32768 906 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 907 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 908 909 #define R600_PTE_VALID (1 << 0) 910 #define R600_PTE_SYSTEM (1 << 1) 911 #define R600_PTE_SNOOPED (1 << 2) 912 #define R600_PTE_READABLE (1 << 5) 913 #define R600_PTE_WRITEABLE (1 << 6) 914 915 /* PTE (Page Table Entry) fragment field for different page sizes */ 916 #define R600_PTE_FRAG_4KB (0 << 7) 917 #define R600_PTE_FRAG_64KB (4 << 7) 918 #define R600_PTE_FRAG_256KB (6 << 7) 919 920 /* flags needed to be set so we can copy directly from the GART table */ 921 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ 922 R600_PTE_SYSTEM | R600_PTE_VALID ) 923 924 struct radeon_vm_pt { 925 struct radeon_bo *bo; 926 uint64_t addr; 927 }; 928 929 struct radeon_vm_id { 930 unsigned id; 931 uint64_t pd_gpu_addr; 932 /* last flushed PD/PT update */ 933 struct radeon_fence *flushed_updates; 934 /* last use of vmid */ 935 struct radeon_fence *last_id_use; 936 }; 937 938 struct radeon_vm { 939 struct lock mutex; 940 941 struct rb_root va; 942 943 /* protecting invalidated and freed */ 944 spinlock_t status_lock; 945 946 /* BOs moved, but not yet updated in the PT */ 947 struct list_head invalidated; 948 949 /* BOs freed, but not yet updated in the PT */ 950 struct list_head freed; 951 952 /* BOs cleared in the PT */ 953 struct list_head cleared; 954 955 /* contains the page directory */ 956 struct radeon_bo *page_directory; 957 unsigned max_pde_used; 958 959 /* array of page tables, one for each page directory entry */ 960 struct radeon_vm_pt *page_tables; 961 962 struct radeon_bo_va *ib_bo_va; 963 964 /* for id and flush management per ring */ 965 struct radeon_vm_id ids[RADEON_NUM_RINGS]; 966 }; 967 968 struct radeon_vm_manager { 969 struct radeon_fence *active[RADEON_NUM_VM]; 970 uint32_t max_pfn; 971 /* number of VMIDs */ 972 unsigned nvm; 973 /* vram base address for page table entry */ 974 u64 vram_base_offset; 975 /* is vm enabled? */ 976 bool enabled; 977 /* for hw to save the PD addr on suspend/resume */ 978 uint32_t saved_table_addr[RADEON_NUM_VM]; 979 }; 980 981 /* 982 * file private structure 983 */ 984 struct radeon_fpriv { 985 struct radeon_vm vm; 986 }; 987 988 /* 989 * R6xx+ IH ring 990 */ 991 struct r600_ih { 992 struct radeon_bo *ring_obj; 993 volatile uint32_t *ring; 994 unsigned rptr; 995 unsigned ring_size; 996 uint64_t gpu_addr; 997 uint32_t ptr_mask; 998 atomic_t lock; 999 bool enabled; 1000 }; 1001 1002 /* 1003 * RLC stuff 1004 */ 1005 #include "clearstate_defs.h" 1006 1007 struct radeon_rlc { 1008 /* for power gating */ 1009 struct radeon_bo *save_restore_obj; 1010 u64 save_restore_gpu_addr; 1011 volatile uint32_t *sr_ptr; 1012 const u32 *reg_list; 1013 u32 reg_list_size; 1014 /* for clear state */ 1015 struct radeon_bo *clear_state_obj; 1016 u64 clear_state_gpu_addr; 1017 volatile uint32_t *cs_ptr; 1018 const struct cs_section_def *cs_data; 1019 u32 clear_state_size; 1020 /* for cp tables */ 1021 struct radeon_bo *cp_table_obj; 1022 u64 cp_table_gpu_addr; 1023 volatile uint32_t *cp_table_ptr; 1024 u32 cp_table_size; 1025 }; 1026 1027 int radeon_ib_get(struct radeon_device *rdev, int ring, 1028 struct radeon_ib *ib, struct radeon_vm *vm, 1029 unsigned size); 1030 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 1031 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 1032 struct radeon_ib *const_ib, bool hdp_flush); 1033 int radeon_ib_pool_init(struct radeon_device *rdev); 1034 void radeon_ib_pool_fini(struct radeon_device *rdev); 1035 int radeon_ib_ring_tests(struct radeon_device *rdev); 1036 /* Ring access between begin & end cannot sleep */ 1037 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 1038 struct radeon_ring *ring); 1039 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 1040 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1041 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1042 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1043 bool hdp_flush); 1044 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1045 bool hdp_flush); 1046 void radeon_ring_undo(struct radeon_ring *ring); 1047 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 1048 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 1049 void radeon_ring_lockup_update(struct radeon_device *rdev, 1050 struct radeon_ring *ring); 1051 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 1052 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 1053 uint32_t **data); 1054 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 1055 unsigned size, uint32_t *data); 1056 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 1057 unsigned rptr_offs, u32 nop); 1058 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 1059 1060 1061 /* r600 async dma */ 1062 void r600_dma_stop(struct radeon_device *rdev); 1063 int r600_dma_resume(struct radeon_device *rdev); 1064 void r600_dma_fini(struct radeon_device *rdev); 1065 1066 void cayman_dma_stop(struct radeon_device *rdev); 1067 int cayman_dma_resume(struct radeon_device *rdev); 1068 void cayman_dma_fini(struct radeon_device *rdev); 1069 1070 /* 1071 * CS. 1072 */ 1073 struct radeon_cs_chunk { 1074 uint32_t length_dw; 1075 uint32_t *kdata; 1076 void __user *user_ptr; 1077 }; 1078 1079 struct radeon_cs_parser { 1080 struct device *dev; 1081 struct radeon_device *rdev; 1082 struct drm_file *filp; 1083 /* chunks */ 1084 unsigned nchunks; 1085 struct radeon_cs_chunk *chunks; 1086 uint64_t *chunks_array; 1087 /* IB */ 1088 unsigned idx; 1089 /* relocations */ 1090 unsigned nrelocs; 1091 struct radeon_bo_list *relocs; 1092 struct radeon_bo_list *vm_bos; 1093 struct list_head validated; 1094 unsigned dma_reloc_idx; 1095 /* indices of various chunks */ 1096 struct radeon_cs_chunk *chunk_ib; 1097 struct radeon_cs_chunk *chunk_relocs; 1098 struct radeon_cs_chunk *chunk_flags; 1099 struct radeon_cs_chunk *chunk_const_ib; 1100 struct radeon_ib ib; 1101 struct radeon_ib const_ib; 1102 void *track; 1103 unsigned family; 1104 int parser_error; 1105 u32 cs_flags; 1106 u32 ring; 1107 s32 priority; 1108 struct ww_acquire_ctx ticket; 1109 }; 1110 1111 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1112 { 1113 struct radeon_cs_chunk *ibc = p->chunk_ib; 1114 1115 if (ibc->kdata) 1116 return ibc->kdata[idx]; 1117 return p->ib.ptr[idx]; 1118 } 1119 1120 1121 struct radeon_cs_packet { 1122 unsigned idx; 1123 unsigned type; 1124 unsigned reg; 1125 unsigned opcode; 1126 int count; 1127 unsigned one_reg_wr; 1128 }; 1129 1130 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1131 struct radeon_cs_packet *pkt, 1132 unsigned idx, unsigned reg); 1133 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 1134 struct radeon_cs_packet *pkt); 1135 1136 1137 /* 1138 * AGP 1139 */ 1140 int radeon_agp_init(struct radeon_device *rdev); 1141 void radeon_agp_resume(struct radeon_device *rdev); 1142 void radeon_agp_suspend(struct radeon_device *rdev); 1143 void radeon_agp_fini(struct radeon_device *rdev); 1144 1145 1146 /* 1147 * Writeback 1148 */ 1149 struct radeon_wb { 1150 struct radeon_bo *wb_obj; 1151 volatile uint32_t *wb; 1152 uint64_t gpu_addr; 1153 bool enabled; 1154 bool use_event; 1155 }; 1156 1157 #define RADEON_WB_SCRATCH_OFFSET 0 1158 #define RADEON_WB_RING0_NEXT_RPTR 256 1159 #define RADEON_WB_CP_RPTR_OFFSET 1024 1160 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1161 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1162 #define R600_WB_DMA_RPTR_OFFSET 1792 1163 #define R600_WB_IH_WPTR_OFFSET 2048 1164 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1165 #define R600_WB_EVENT_OFFSET 3072 1166 #define CIK_WB_CP1_WPTR_OFFSET 3328 1167 #define CIK_WB_CP2_WPTR_OFFSET 3584 1168 #define R600_WB_DMA_RING_TEST_OFFSET 3588 1169 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 1170 1171 /** 1172 * struct radeon_pm - power management datas 1173 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1174 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1175 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1176 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1177 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1178 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1179 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1180 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1181 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1182 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1183 * @needed_bandwidth: current bandwidth needs 1184 * 1185 * It keeps track of various data needed to take powermanagement decision. 1186 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1187 * Equation between gpu/memory clock and available bandwidth is hw dependent 1188 * (type of memory, bus size, efficiency, ...) 1189 */ 1190 1191 enum radeon_pm_method { 1192 PM_METHOD_PROFILE, 1193 PM_METHOD_DYNPM, 1194 PM_METHOD_DPM, 1195 }; 1196 1197 enum radeon_dynpm_state { 1198 DYNPM_STATE_DISABLED, 1199 DYNPM_STATE_MINIMUM, 1200 DYNPM_STATE_PAUSED, 1201 DYNPM_STATE_ACTIVE, 1202 DYNPM_STATE_SUSPENDED, 1203 }; 1204 enum radeon_dynpm_action { 1205 DYNPM_ACTION_NONE, 1206 DYNPM_ACTION_MINIMUM, 1207 DYNPM_ACTION_DOWNCLOCK, 1208 DYNPM_ACTION_UPCLOCK, 1209 DYNPM_ACTION_DEFAULT 1210 }; 1211 1212 enum radeon_voltage_type { 1213 VOLTAGE_NONE = 0, 1214 VOLTAGE_GPIO, 1215 VOLTAGE_VDDC, 1216 VOLTAGE_SW 1217 }; 1218 1219 enum radeon_pm_state_type { 1220 /* not used for dpm */ 1221 POWER_STATE_TYPE_DEFAULT, 1222 POWER_STATE_TYPE_POWERSAVE, 1223 /* user selectable states */ 1224 POWER_STATE_TYPE_BATTERY, 1225 POWER_STATE_TYPE_BALANCED, 1226 POWER_STATE_TYPE_PERFORMANCE, 1227 /* internal states */ 1228 POWER_STATE_TYPE_INTERNAL_UVD, 1229 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1230 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1231 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1232 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1233 POWER_STATE_TYPE_INTERNAL_BOOT, 1234 POWER_STATE_TYPE_INTERNAL_THERMAL, 1235 POWER_STATE_TYPE_INTERNAL_ACPI, 1236 POWER_STATE_TYPE_INTERNAL_ULV, 1237 POWER_STATE_TYPE_INTERNAL_3DPERF, 1238 }; 1239 1240 enum radeon_pm_profile_type { 1241 PM_PROFILE_DEFAULT, 1242 PM_PROFILE_AUTO, 1243 PM_PROFILE_LOW, 1244 PM_PROFILE_MID, 1245 PM_PROFILE_HIGH, 1246 }; 1247 1248 #define PM_PROFILE_DEFAULT_IDX 0 1249 #define PM_PROFILE_LOW_SH_IDX 1 1250 #define PM_PROFILE_MID_SH_IDX 2 1251 #define PM_PROFILE_HIGH_SH_IDX 3 1252 #define PM_PROFILE_LOW_MH_IDX 4 1253 #define PM_PROFILE_MID_MH_IDX 5 1254 #define PM_PROFILE_HIGH_MH_IDX 6 1255 #define PM_PROFILE_MAX 7 1256 1257 struct radeon_pm_profile { 1258 int dpms_off_ps_idx; 1259 int dpms_on_ps_idx; 1260 int dpms_off_cm_idx; 1261 int dpms_on_cm_idx; 1262 }; 1263 1264 enum radeon_int_thermal_type { 1265 THERMAL_TYPE_NONE, 1266 THERMAL_TYPE_EXTERNAL, 1267 THERMAL_TYPE_EXTERNAL_GPIO, 1268 THERMAL_TYPE_RV6XX, 1269 THERMAL_TYPE_RV770, 1270 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1271 THERMAL_TYPE_EVERGREEN, 1272 THERMAL_TYPE_SUMO, 1273 THERMAL_TYPE_NI, 1274 THERMAL_TYPE_SI, 1275 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1276 THERMAL_TYPE_CI, 1277 THERMAL_TYPE_KV, 1278 }; 1279 1280 struct radeon_voltage { 1281 enum radeon_voltage_type type; 1282 /* gpio voltage */ 1283 struct radeon_gpio_rec gpio; 1284 u32 delay; /* delay in usec from voltage drop to sclk change */ 1285 bool active_high; /* voltage drop is active when bit is high */ 1286 /* VDDC voltage */ 1287 u8 vddc_id; /* index into vddc voltage table */ 1288 u8 vddci_id; /* index into vddci voltage table */ 1289 bool vddci_enabled; 1290 /* r6xx+ sw */ 1291 u16 voltage; 1292 /* evergreen+ vddci */ 1293 u16 vddci; 1294 }; 1295 1296 /* clock mode flags */ 1297 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1298 1299 struct radeon_pm_clock_info { 1300 /* memory clock */ 1301 u32 mclk; 1302 /* engine clock */ 1303 u32 sclk; 1304 /* voltage info */ 1305 struct radeon_voltage voltage; 1306 /* standardized clock flags */ 1307 u32 flags; 1308 }; 1309 1310 /* state flags */ 1311 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1312 1313 struct radeon_power_state { 1314 enum radeon_pm_state_type type; 1315 struct radeon_pm_clock_info *clock_info; 1316 /* number of valid clock modes in this power state */ 1317 int num_clock_modes; 1318 struct radeon_pm_clock_info *default_clock_mode; 1319 /* standardized state flags */ 1320 u32 flags; 1321 u32 misc; /* vbios specific flags */ 1322 u32 misc2; /* vbios specific flags */ 1323 int pcie_lanes; /* pcie lanes */ 1324 }; 1325 1326 /* 1327 * Some modes are overclocked by very low value, accept them 1328 */ 1329 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1330 1331 enum radeon_dpm_auto_throttle_src { 1332 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1333 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1334 }; 1335 1336 enum radeon_dpm_event_src { 1337 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1338 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1339 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1340 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1341 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1342 }; 1343 1344 #define RADEON_MAX_VCE_LEVELS 6 1345 1346 enum radeon_vce_level { 1347 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1348 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1349 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1350 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1351 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1352 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1353 }; 1354 1355 struct radeon_ps { 1356 u32 caps; /* vbios flags */ 1357 u32 class; /* vbios flags */ 1358 u32 class2; /* vbios flags */ 1359 /* UVD clocks */ 1360 u32 vclk; 1361 u32 dclk; 1362 /* VCE clocks */ 1363 u32 evclk; 1364 u32 ecclk; 1365 bool vce_active; 1366 enum radeon_vce_level vce_level; 1367 /* asic priv */ 1368 void *ps_priv; 1369 }; 1370 1371 struct radeon_dpm_thermal { 1372 /* thermal interrupt work */ 1373 struct work_struct work; 1374 /* low temperature threshold */ 1375 int min_temp; 1376 /* high temperature threshold */ 1377 int max_temp; 1378 /* was interrupt low to high or high to low */ 1379 bool high_to_low; 1380 }; 1381 1382 enum radeon_clk_action 1383 { 1384 RADEON_SCLK_UP = 1, 1385 RADEON_SCLK_DOWN 1386 }; 1387 1388 struct radeon_blacklist_clocks 1389 { 1390 u32 sclk; 1391 u32 mclk; 1392 enum radeon_clk_action action; 1393 }; 1394 1395 struct radeon_clock_and_voltage_limits { 1396 u32 sclk; 1397 u32 mclk; 1398 u16 vddc; 1399 u16 vddci; 1400 }; 1401 1402 struct radeon_clock_array { 1403 u32 count; 1404 u32 *values; 1405 }; 1406 1407 struct radeon_clock_voltage_dependency_entry { 1408 u32 clk; 1409 u16 v; 1410 }; 1411 1412 struct radeon_clock_voltage_dependency_table { 1413 u32 count; 1414 struct radeon_clock_voltage_dependency_entry *entries; 1415 }; 1416 1417 union radeon_cac_leakage_entry { 1418 struct { 1419 u16 vddc; 1420 u32 leakage; 1421 }; 1422 struct { 1423 u16 vddc1; 1424 u16 vddc2; 1425 u16 vddc3; 1426 }; 1427 }; 1428 1429 struct radeon_cac_leakage_table { 1430 u32 count; 1431 union radeon_cac_leakage_entry *entries; 1432 }; 1433 1434 struct radeon_phase_shedding_limits_entry { 1435 u16 voltage; 1436 u32 sclk; 1437 u32 mclk; 1438 }; 1439 1440 struct radeon_phase_shedding_limits_table { 1441 u32 count; 1442 struct radeon_phase_shedding_limits_entry *entries; 1443 }; 1444 1445 struct radeon_uvd_clock_voltage_dependency_entry { 1446 u32 vclk; 1447 u32 dclk; 1448 u16 v; 1449 }; 1450 1451 struct radeon_uvd_clock_voltage_dependency_table { 1452 u8 count; 1453 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1454 }; 1455 1456 struct radeon_vce_clock_voltage_dependency_entry { 1457 u32 ecclk; 1458 u32 evclk; 1459 u16 v; 1460 }; 1461 1462 struct radeon_vce_clock_voltage_dependency_table { 1463 u8 count; 1464 struct radeon_vce_clock_voltage_dependency_entry *entries; 1465 }; 1466 1467 struct radeon_ppm_table { 1468 u8 ppm_design; 1469 u16 cpu_core_number; 1470 u32 platform_tdp; 1471 u32 small_ac_platform_tdp; 1472 u32 platform_tdc; 1473 u32 small_ac_platform_tdc; 1474 u32 apu_tdp; 1475 u32 dgpu_tdp; 1476 u32 dgpu_ulv_power; 1477 u32 tj_max; 1478 }; 1479 1480 struct radeon_cac_tdp_table { 1481 u16 tdp; 1482 u16 configurable_tdp; 1483 u16 tdc; 1484 u16 battery_power_limit; 1485 u16 small_power_limit; 1486 u16 low_cac_leakage; 1487 u16 high_cac_leakage; 1488 u16 maximum_power_delivery_limit; 1489 }; 1490 1491 struct radeon_dpm_dynamic_state { 1492 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1493 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1494 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1495 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1496 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1497 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1498 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1499 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1500 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1501 struct radeon_clock_array valid_sclk_values; 1502 struct radeon_clock_array valid_mclk_values; 1503 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1504 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1505 u32 mclk_sclk_ratio; 1506 u32 sclk_mclk_delta; 1507 u16 vddc_vddci_delta; 1508 u16 min_vddc_for_pcie_gen2; 1509 struct radeon_cac_leakage_table cac_leakage_table; 1510 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1511 struct radeon_ppm_table *ppm_table; 1512 struct radeon_cac_tdp_table *cac_tdp_table; 1513 }; 1514 1515 struct radeon_dpm_fan { 1516 u16 t_min; 1517 u16 t_med; 1518 u16 t_high; 1519 u16 pwm_min; 1520 u16 pwm_med; 1521 u16 pwm_high; 1522 u8 t_hyst; 1523 u32 cycle_delay; 1524 u16 t_max; 1525 u8 control_mode; 1526 u16 default_max_fan_pwm; 1527 u16 default_fan_output_sensitivity; 1528 u16 fan_output_sensitivity; 1529 bool ucode_fan_control; 1530 }; 1531 1532 enum radeon_pcie_gen { 1533 RADEON_PCIE_GEN1 = 0, 1534 RADEON_PCIE_GEN2 = 1, 1535 RADEON_PCIE_GEN3 = 2, 1536 RADEON_PCIE_GEN_INVALID = 0xffff 1537 }; 1538 1539 enum radeon_dpm_forced_level { 1540 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1541 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1542 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1543 }; 1544 1545 struct radeon_vce_state { 1546 /* vce clocks */ 1547 u32 evclk; 1548 u32 ecclk; 1549 /* gpu clocks */ 1550 u32 sclk; 1551 u32 mclk; 1552 u8 clk_idx; 1553 u8 pstate; 1554 }; 1555 1556 struct radeon_dpm { 1557 struct radeon_ps *ps; 1558 /* number of valid power states */ 1559 int num_ps; 1560 /* current power state that is active */ 1561 struct radeon_ps *current_ps; 1562 /* requested power state */ 1563 struct radeon_ps *requested_ps; 1564 /* boot up power state */ 1565 struct radeon_ps *boot_ps; 1566 /* default uvd power state */ 1567 struct radeon_ps *uvd_ps; 1568 /* vce requirements */ 1569 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1570 enum radeon_vce_level vce_level; 1571 enum radeon_pm_state_type state; 1572 enum radeon_pm_state_type user_state; 1573 u32 platform_caps; 1574 u32 voltage_response_time; 1575 u32 backbias_response_time; 1576 void *priv; 1577 u32 new_active_crtcs; 1578 int new_active_crtc_count; 1579 u32 current_active_crtcs; 1580 int current_active_crtc_count; 1581 bool single_display; 1582 struct radeon_dpm_dynamic_state dyn_state; 1583 struct radeon_dpm_fan fan; 1584 u32 tdp_limit; 1585 u32 near_tdp_limit; 1586 u32 near_tdp_limit_adjusted; 1587 u32 sq_ramping_threshold; 1588 u32 cac_leakage; 1589 u16 tdp_od_limit; 1590 u32 tdp_adjustment; 1591 u16 load_line_slope; 1592 bool power_control; 1593 bool ac_power; 1594 /* special states active */ 1595 bool thermal_active; 1596 bool uvd_active; 1597 bool vce_active; 1598 /* thermal handling */ 1599 struct radeon_dpm_thermal thermal; 1600 /* forced levels */ 1601 enum radeon_dpm_forced_level forced_level; 1602 /* track UVD streams */ 1603 unsigned sd; 1604 unsigned hd; 1605 }; 1606 1607 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1608 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1609 1610 struct radeon_pm { 1611 struct lock mutex; 1612 /* write locked while reprogramming mclk */ 1613 struct lock mclk_lock; 1614 u32 active_crtcs; 1615 int active_crtc_count; 1616 int req_vblank; 1617 bool vblank_sync; 1618 fixed20_12 max_bandwidth; 1619 fixed20_12 igp_sideport_mclk; 1620 fixed20_12 igp_system_mclk; 1621 fixed20_12 igp_ht_link_clk; 1622 fixed20_12 igp_ht_link_width; 1623 fixed20_12 k8_bandwidth; 1624 fixed20_12 sideport_bandwidth; 1625 fixed20_12 ht_bandwidth; 1626 fixed20_12 core_bandwidth; 1627 fixed20_12 sclk; 1628 fixed20_12 mclk; 1629 fixed20_12 needed_bandwidth; 1630 struct radeon_power_state *power_state; 1631 /* number of valid power states */ 1632 int num_power_states; 1633 int current_power_state_index; 1634 int current_clock_mode_index; 1635 int requested_power_state_index; 1636 int requested_clock_mode_index; 1637 int default_power_state_index; 1638 u32 current_sclk; 1639 u32 current_mclk; 1640 u16 current_vddc; 1641 u16 current_vddci; 1642 u32 default_sclk; 1643 u32 default_mclk; 1644 u16 default_vddc; 1645 u16 default_vddci; 1646 struct radeon_i2c_chan *i2c_bus; 1647 /* selected pm method */ 1648 enum radeon_pm_method pm_method; 1649 /* dynpm power management */ 1650 struct delayed_work dynpm_idle_work; 1651 enum radeon_dynpm_state dynpm_state; 1652 enum radeon_dynpm_action dynpm_planned_action; 1653 unsigned long dynpm_action_timeout; 1654 bool dynpm_can_upclock; 1655 bool dynpm_can_downclock; 1656 /* profile-based power management */ 1657 enum radeon_pm_profile_type profile; 1658 int profile_index; 1659 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1660 /* internal thermal controller on rv6xx+ */ 1661 enum radeon_int_thermal_type int_thermal_type; 1662 struct ksensor *int_sensor; 1663 struct ksensordev *int_sensordev; 1664 /* fan control parameters */ 1665 bool no_fan; 1666 u8 fan_pulses_per_revolution; 1667 u8 fan_min_rpm; 1668 u8 fan_max_rpm; 1669 /* dpm */ 1670 bool dpm_enabled; 1671 bool sysfs_initialized; 1672 struct radeon_dpm dpm; 1673 }; 1674 1675 int radeon_pm_get_type_index(struct radeon_device *rdev, 1676 enum radeon_pm_state_type ps_type, 1677 int instance); 1678 /* 1679 * UVD 1680 */ 1681 #define RADEON_DEFAULT_UVD_HANDLES 10 1682 #define RADEON_MAX_UVD_HANDLES 30 1683 #define RADEON_UVD_STACK_SIZE (200*1024) 1684 #define RADEON_UVD_HEAP_SIZE (256*1024) 1685 #define RADEON_UVD_SESSION_SIZE (50*1024) 1686 1687 struct radeon_uvd { 1688 bool fw_header_present; 1689 struct radeon_bo *vcpu_bo; 1690 void *cpu_addr; 1691 u64 gpu_addr; 1692 unsigned max_handles; 1693 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1694 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1695 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1696 struct delayed_work idle_work; 1697 }; 1698 1699 int radeon_uvd_init(struct radeon_device *rdev); 1700 void radeon_uvd_fini(struct radeon_device *rdev); 1701 int radeon_uvd_suspend(struct radeon_device *rdev); 1702 int radeon_uvd_resume(struct radeon_device *rdev); 1703 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1704 uint32_t handle, struct radeon_fence **fence); 1705 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1706 uint32_t handle, struct radeon_fence **fence); 1707 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, 1708 uint32_t allowed_domains); 1709 void radeon_uvd_free_handles(struct radeon_device *rdev, 1710 struct drm_file *filp); 1711 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1712 void radeon_uvd_note_usage(struct radeon_device *rdev); 1713 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1714 unsigned vclk, unsigned dclk, 1715 unsigned vco_min, unsigned vco_max, 1716 unsigned fb_factor, unsigned fb_mask, 1717 unsigned pd_min, unsigned pd_max, 1718 unsigned pd_even, 1719 unsigned *optimal_fb_div, 1720 unsigned *optimal_vclk_div, 1721 unsigned *optimal_dclk_div); 1722 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1723 unsigned cg_upll_func_cntl); 1724 1725 /* 1726 * VCE 1727 */ 1728 #define RADEON_MAX_VCE_HANDLES 16 1729 1730 struct radeon_vce { 1731 struct radeon_bo *vcpu_bo; 1732 u64 gpu_addr; 1733 unsigned fw_version; 1734 unsigned fb_version; 1735 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1736 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1737 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1738 struct delayed_work idle_work; 1739 uint32_t keyselect; 1740 }; 1741 1742 int radeon_vce_init(struct radeon_device *rdev); 1743 void radeon_vce_fini(struct radeon_device *rdev); 1744 int radeon_vce_suspend(struct radeon_device *rdev); 1745 int radeon_vce_resume(struct radeon_device *rdev); 1746 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1747 uint32_t handle, struct radeon_fence **fence); 1748 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1749 uint32_t handle, struct radeon_fence **fence); 1750 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1751 void radeon_vce_note_usage(struct radeon_device *rdev); 1752 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1753 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1754 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1755 struct radeon_ring *ring, 1756 struct radeon_semaphore *semaphore, 1757 bool emit_wait); 1758 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1759 void radeon_vce_fence_emit(struct radeon_device *rdev, 1760 struct radeon_fence *fence); 1761 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1762 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1763 1764 struct r600_audio_pin { 1765 int channels; 1766 int rate; 1767 int bits_per_sample; 1768 u8 status_bits; 1769 u8 category_code; 1770 u32 offset; 1771 bool connected; 1772 u32 id; 1773 }; 1774 1775 struct r600_audio { 1776 bool enabled; 1777 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1778 int num_pins; 1779 struct radeon_audio_funcs *hdmi_funcs; 1780 struct radeon_audio_funcs *dp_funcs; 1781 struct radeon_audio_basic_funcs *funcs; 1782 }; 1783 1784 /* 1785 * Benchmarking 1786 */ 1787 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1788 1789 1790 /* 1791 * Testing 1792 */ 1793 void radeon_test_moves(struct radeon_device *rdev); 1794 void radeon_test_ring_sync(struct radeon_device *rdev, 1795 struct radeon_ring *cpA, 1796 struct radeon_ring *cpB); 1797 void radeon_test_syncing(struct radeon_device *rdev); 1798 1799 /* 1800 * MMU Notifier 1801 */ 1802 #if defined(CONFIG_MMU_NOTIFIER) 1803 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr); 1804 void radeon_mn_unregister(struct radeon_bo *bo); 1805 #else 1806 static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr) 1807 { 1808 return -ENODEV; 1809 } 1810 static inline void radeon_mn_unregister(struct radeon_bo *bo) {} 1811 #endif 1812 1813 /* 1814 * Debugfs 1815 */ 1816 struct radeon_debugfs { 1817 struct drm_info_list *files; 1818 unsigned num_files; 1819 }; 1820 1821 int radeon_debugfs_add_files(struct radeon_device *rdev, 1822 struct drm_info_list *files, 1823 unsigned nfiles); 1824 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1825 1826 /* 1827 * ASIC ring specific functions. 1828 */ 1829 struct radeon_asic_ring { 1830 /* ring read/write ptr handling */ 1831 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1832 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1833 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1834 1835 /* validating and patching of IBs */ 1836 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1837 int (*cs_parse)(struct radeon_cs_parser *p); 1838 1839 /* command emmit functions */ 1840 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1841 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1842 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); 1843 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1844 struct radeon_semaphore *semaphore, bool emit_wait); 1845 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring, 1846 unsigned vm_id, uint64_t pd_addr); 1847 1848 /* testing functions */ 1849 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1850 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1851 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1852 1853 /* deprecated */ 1854 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1855 }; 1856 1857 /* 1858 * ASIC specific functions. 1859 */ 1860 struct radeon_asic { 1861 int (*init)(struct radeon_device *rdev); 1862 void (*fini)(struct radeon_device *rdev); 1863 int (*resume)(struct radeon_device *rdev); 1864 int (*suspend)(struct radeon_device *rdev); 1865 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1866 int (*asic_reset)(struct radeon_device *rdev, bool hard); 1867 /* Flush the HDP cache via MMIO */ 1868 void (*mmio_hdp_flush)(struct radeon_device *rdev); 1869 /* check if 3D engine is idle */ 1870 bool (*gui_idle)(struct radeon_device *rdev); 1871 /* wait for mc_idle */ 1872 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1873 /* get the reference clock */ 1874 u32 (*get_xclk)(struct radeon_device *rdev); 1875 /* get the gpu clock counter */ 1876 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1877 /* get register for info ioctl */ 1878 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val); 1879 /* gart */ 1880 struct { 1881 void (*tlb_flush)(struct radeon_device *rdev); 1882 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags); 1883 void (*set_page)(struct radeon_device *rdev, unsigned i, 1884 uint64_t entry); 1885 } gart; 1886 struct { 1887 int (*init)(struct radeon_device *rdev); 1888 void (*fini)(struct radeon_device *rdev); 1889 void (*copy_pages)(struct radeon_device *rdev, 1890 struct radeon_ib *ib, 1891 uint64_t pe, uint64_t src, 1892 unsigned count); 1893 void (*write_pages)(struct radeon_device *rdev, 1894 struct radeon_ib *ib, 1895 uint64_t pe, 1896 uint64_t addr, unsigned count, 1897 uint32_t incr, uint32_t flags); 1898 void (*set_pages)(struct radeon_device *rdev, 1899 struct radeon_ib *ib, 1900 uint64_t pe, 1901 uint64_t addr, unsigned count, 1902 uint32_t incr, uint32_t flags); 1903 void (*pad_ib)(struct radeon_ib *ib); 1904 } vm; 1905 /* ring specific callbacks */ 1906 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1907 /* irqs */ 1908 struct { 1909 int (*set)(struct radeon_device *rdev); 1910 irqreturn_t (*process)(struct radeon_device *rdev); 1911 } irq; 1912 /* displays */ 1913 struct { 1914 /* display watermarks */ 1915 void (*bandwidth_update)(struct radeon_device *rdev); 1916 /* get frame count */ 1917 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1918 /* wait for vblank */ 1919 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1920 /* set backlight level */ 1921 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1922 /* get backlight level */ 1923 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1924 /* audio callbacks */ 1925 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1926 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1927 } display; 1928 /* copy functions for bo handling */ 1929 struct { 1930 struct radeon_fence *(*blit)(struct radeon_device *rdev, 1931 uint64_t src_offset, 1932 uint64_t dst_offset, 1933 unsigned num_gpu_pages, 1934 struct reservation_object *resv); 1935 u32 blit_ring_index; 1936 struct radeon_fence *(*dma)(struct radeon_device *rdev, 1937 uint64_t src_offset, 1938 uint64_t dst_offset, 1939 unsigned num_gpu_pages, 1940 struct reservation_object *resv); 1941 u32 dma_ring_index; 1942 /* method used for bo copy */ 1943 struct radeon_fence *(*copy)(struct radeon_device *rdev, 1944 uint64_t src_offset, 1945 uint64_t dst_offset, 1946 unsigned num_gpu_pages, 1947 struct reservation_object *resv); 1948 /* ring used for bo copies */ 1949 u32 copy_ring_index; 1950 } copy; 1951 /* surfaces */ 1952 struct { 1953 int (*set_reg)(struct radeon_device *rdev, int reg, 1954 uint32_t tiling_flags, uint32_t pitch, 1955 uint32_t offset, uint32_t obj_size); 1956 void (*clear_reg)(struct radeon_device *rdev, int reg); 1957 } surface; 1958 /* hotplug detect */ 1959 struct { 1960 void (*init)(struct radeon_device *rdev); 1961 void (*fini)(struct radeon_device *rdev); 1962 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1963 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1964 } hpd; 1965 /* static power management */ 1966 struct { 1967 void (*misc)(struct radeon_device *rdev); 1968 void (*prepare)(struct radeon_device *rdev); 1969 void (*finish)(struct radeon_device *rdev); 1970 void (*init_profile)(struct radeon_device *rdev); 1971 void (*get_dynpm_state)(struct radeon_device *rdev); 1972 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1973 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1974 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1975 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1976 int (*get_pcie_lanes)(struct radeon_device *rdev); 1977 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1978 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1979 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 1980 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 1981 int (*get_temperature)(struct radeon_device *rdev); 1982 } pm; 1983 /* dynamic power management */ 1984 struct { 1985 int (*init)(struct radeon_device *rdev); 1986 void (*setup_asic)(struct radeon_device *rdev); 1987 int (*enable)(struct radeon_device *rdev); 1988 int (*late_enable)(struct radeon_device *rdev); 1989 void (*disable)(struct radeon_device *rdev); 1990 int (*pre_set_power_state)(struct radeon_device *rdev); 1991 int (*set_power_state)(struct radeon_device *rdev); 1992 void (*post_set_power_state)(struct radeon_device *rdev); 1993 void (*display_configuration_changed)(struct radeon_device *rdev); 1994 void (*fini)(struct radeon_device *rdev); 1995 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 1996 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 1997 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 1998 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 1999 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 2000 bool (*vblank_too_short)(struct radeon_device *rdev); 2001 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 2002 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 2003 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode); 2004 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev); 2005 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed); 2006 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed); 2007 u32 (*get_current_sclk)(struct radeon_device *rdev); 2008 u32 (*get_current_mclk)(struct radeon_device *rdev); 2009 } dpm; 2010 /* pageflipping */ 2011 struct { 2012 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async); 2013 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); 2014 } pflip; 2015 }; 2016 2017 /* 2018 * Asic structures 2019 */ 2020 struct r100_asic { 2021 const unsigned *reg_safe_bm; 2022 unsigned reg_safe_bm_size; 2023 u32 hdp_cntl; 2024 }; 2025 2026 struct r300_asic { 2027 const unsigned *reg_safe_bm; 2028 unsigned reg_safe_bm_size; 2029 u32 resync_scratch; 2030 u32 hdp_cntl; 2031 }; 2032 2033 struct r600_asic { 2034 unsigned max_pipes; 2035 unsigned max_tile_pipes; 2036 unsigned max_simds; 2037 unsigned max_backends; 2038 unsigned max_gprs; 2039 unsigned max_threads; 2040 unsigned max_stack_entries; 2041 unsigned max_hw_contexts; 2042 unsigned max_gs_threads; 2043 unsigned sx_max_export_size; 2044 unsigned sx_max_export_pos_size; 2045 unsigned sx_max_export_smx_size; 2046 unsigned sq_num_cf_insts; 2047 unsigned tiling_nbanks; 2048 unsigned tiling_npipes; 2049 unsigned tiling_group_size; 2050 unsigned tile_config; 2051 unsigned backend_map; 2052 unsigned active_simds; 2053 }; 2054 2055 struct rv770_asic { 2056 unsigned max_pipes; 2057 unsigned max_tile_pipes; 2058 unsigned max_simds; 2059 unsigned max_backends; 2060 unsigned max_gprs; 2061 unsigned max_threads; 2062 unsigned max_stack_entries; 2063 unsigned max_hw_contexts; 2064 unsigned max_gs_threads; 2065 unsigned sx_max_export_size; 2066 unsigned sx_max_export_pos_size; 2067 unsigned sx_max_export_smx_size; 2068 unsigned sq_num_cf_insts; 2069 unsigned sx_num_of_sets; 2070 unsigned sc_prim_fifo_size; 2071 unsigned sc_hiz_tile_fifo_size; 2072 unsigned sc_earlyz_tile_fifo_fize; 2073 unsigned tiling_nbanks; 2074 unsigned tiling_npipes; 2075 unsigned tiling_group_size; 2076 unsigned tile_config; 2077 unsigned backend_map; 2078 unsigned active_simds; 2079 }; 2080 2081 struct evergreen_asic { 2082 unsigned num_ses; 2083 unsigned max_pipes; 2084 unsigned max_tile_pipes; 2085 unsigned max_simds; 2086 unsigned max_backends; 2087 unsigned max_gprs; 2088 unsigned max_threads; 2089 unsigned max_stack_entries; 2090 unsigned max_hw_contexts; 2091 unsigned max_gs_threads; 2092 unsigned sx_max_export_size; 2093 unsigned sx_max_export_pos_size; 2094 unsigned sx_max_export_smx_size; 2095 unsigned sq_num_cf_insts; 2096 unsigned sx_num_of_sets; 2097 unsigned sc_prim_fifo_size; 2098 unsigned sc_hiz_tile_fifo_size; 2099 unsigned sc_earlyz_tile_fifo_size; 2100 unsigned tiling_nbanks; 2101 unsigned tiling_npipes; 2102 unsigned tiling_group_size; 2103 unsigned tile_config; 2104 unsigned backend_map; 2105 unsigned active_simds; 2106 }; 2107 2108 struct cayman_asic { 2109 unsigned max_shader_engines; 2110 unsigned max_pipes_per_simd; 2111 unsigned max_tile_pipes; 2112 unsigned max_simds_per_se; 2113 unsigned max_backends_per_se; 2114 unsigned max_texture_channel_caches; 2115 unsigned max_gprs; 2116 unsigned max_threads; 2117 unsigned max_gs_threads; 2118 unsigned max_stack_entries; 2119 unsigned sx_num_of_sets; 2120 unsigned sx_max_export_size; 2121 unsigned sx_max_export_pos_size; 2122 unsigned sx_max_export_smx_size; 2123 unsigned max_hw_contexts; 2124 unsigned sq_num_cf_insts; 2125 unsigned sc_prim_fifo_size; 2126 unsigned sc_hiz_tile_fifo_size; 2127 unsigned sc_earlyz_tile_fifo_size; 2128 2129 unsigned num_shader_engines; 2130 unsigned num_shader_pipes_per_simd; 2131 unsigned num_tile_pipes; 2132 unsigned num_simds_per_se; 2133 unsigned num_backends_per_se; 2134 unsigned backend_disable_mask_per_asic; 2135 unsigned backend_map; 2136 unsigned num_texture_channel_caches; 2137 unsigned mem_max_burst_length_bytes; 2138 unsigned mem_row_size_in_kb; 2139 unsigned shader_engine_tile_size; 2140 unsigned num_gpus; 2141 unsigned multi_gpu_tile_size; 2142 2143 unsigned tile_config; 2144 unsigned active_simds; 2145 }; 2146 2147 struct si_asic { 2148 unsigned max_shader_engines; 2149 unsigned max_tile_pipes; 2150 unsigned max_cu_per_sh; 2151 unsigned max_sh_per_se; 2152 unsigned max_backends_per_se; 2153 unsigned max_texture_channel_caches; 2154 unsigned max_gprs; 2155 unsigned max_gs_threads; 2156 unsigned max_hw_contexts; 2157 unsigned sc_prim_fifo_size_frontend; 2158 unsigned sc_prim_fifo_size_backend; 2159 unsigned sc_hiz_tile_fifo_size; 2160 unsigned sc_earlyz_tile_fifo_size; 2161 2162 unsigned num_tile_pipes; 2163 unsigned backend_enable_mask; 2164 unsigned backend_disable_mask_per_asic; 2165 unsigned backend_map; 2166 unsigned num_texture_channel_caches; 2167 unsigned mem_max_burst_length_bytes; 2168 unsigned mem_row_size_in_kb; 2169 unsigned shader_engine_tile_size; 2170 unsigned num_gpus; 2171 unsigned multi_gpu_tile_size; 2172 2173 unsigned tile_config; 2174 uint32_t tile_mode_array[32]; 2175 uint32_t active_cus; 2176 }; 2177 2178 struct cik_asic { 2179 unsigned max_shader_engines; 2180 unsigned max_tile_pipes; 2181 unsigned max_cu_per_sh; 2182 unsigned max_sh_per_se; 2183 unsigned max_backends_per_se; 2184 unsigned max_texture_channel_caches; 2185 unsigned max_gprs; 2186 unsigned max_gs_threads; 2187 unsigned max_hw_contexts; 2188 unsigned sc_prim_fifo_size_frontend; 2189 unsigned sc_prim_fifo_size_backend; 2190 unsigned sc_hiz_tile_fifo_size; 2191 unsigned sc_earlyz_tile_fifo_size; 2192 2193 unsigned num_tile_pipes; 2194 unsigned backend_enable_mask; 2195 unsigned backend_disable_mask_per_asic; 2196 unsigned backend_map; 2197 unsigned num_texture_channel_caches; 2198 unsigned mem_max_burst_length_bytes; 2199 unsigned mem_row_size_in_kb; 2200 unsigned shader_engine_tile_size; 2201 unsigned num_gpus; 2202 unsigned multi_gpu_tile_size; 2203 2204 unsigned tile_config; 2205 uint32_t tile_mode_array[32]; 2206 uint32_t macrotile_mode_array[16]; 2207 uint32_t active_cus; 2208 }; 2209 2210 union radeon_asic_config { 2211 struct r300_asic r300; 2212 struct r100_asic r100; 2213 struct r600_asic r600; 2214 struct rv770_asic rv770; 2215 struct evergreen_asic evergreen; 2216 struct cayman_asic cayman; 2217 struct si_asic si; 2218 struct cik_asic cik; 2219 }; 2220 2221 /* 2222 * asic initizalization from radeon_asic.c 2223 */ 2224 int radeon_asic_init(struct radeon_device *rdev); 2225 2226 2227 /* 2228 * IOCTL. 2229 */ 2230 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2231 struct drm_file *filp); 2232 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2233 struct drm_file *filp); 2234 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, 2235 struct drm_file *filp); 2236 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2237 struct drm_file *file_priv); 2238 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2239 struct drm_file *file_priv); 2240 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2241 struct drm_file *file_priv); 2242 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 2243 struct drm_file *file_priv); 2244 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2245 struct drm_file *filp); 2246 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2247 struct drm_file *filp); 2248 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2249 struct drm_file *filp); 2250 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2251 struct drm_file *filp); 2252 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2253 struct drm_file *filp); 2254 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2255 struct drm_file *filp); 2256 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2257 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2258 struct drm_file *filp); 2259 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2260 struct drm_file *filp); 2261 2262 /* VRAM scratch page for HDP bug, default vram page */ 2263 struct r600_vram_scratch { 2264 struct radeon_bo *robj; 2265 volatile uint32_t *ptr; 2266 u64 gpu_addr; 2267 }; 2268 2269 /* 2270 * ACPI 2271 */ 2272 struct radeon_atif_notification_cfg { 2273 bool enabled; 2274 int command_code; 2275 }; 2276 2277 struct radeon_atif_notifications { 2278 bool display_switch; 2279 bool expansion_mode_change; 2280 bool thermal_state; 2281 bool forced_power_state; 2282 bool system_power_state; 2283 bool display_conf_change; 2284 bool px_gfx_switch; 2285 bool brightness_change; 2286 bool dgpu_display_event; 2287 }; 2288 2289 struct radeon_atif_functions { 2290 bool system_params; 2291 bool sbios_requests; 2292 bool select_active_disp; 2293 bool lid_state; 2294 bool get_tv_standard; 2295 bool set_tv_standard; 2296 bool get_panel_expansion_mode; 2297 bool set_panel_expansion_mode; 2298 bool temperature_change; 2299 bool graphics_device_types; 2300 }; 2301 2302 struct radeon_atif { 2303 struct radeon_atif_notifications notifications; 2304 struct radeon_atif_functions functions; 2305 struct radeon_atif_notification_cfg notification_cfg; 2306 struct radeon_encoder *encoder_for_bl; 2307 }; 2308 2309 struct radeon_atcs_functions { 2310 bool get_ext_state; 2311 bool pcie_perf_req; 2312 bool pcie_dev_rdy; 2313 bool pcie_bus_width; 2314 }; 2315 2316 struct radeon_atcs { 2317 struct radeon_atcs_functions functions; 2318 }; 2319 2320 /* 2321 * Core structure, functions and helpers. 2322 */ 2323 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2324 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2325 2326 struct radeon_device { 2327 struct device *dev; 2328 struct drm_device *ddev; 2329 struct pci_dev *pdev; 2330 struct lock exclusive_lock; 2331 /* ASIC */ 2332 union radeon_asic_config config; 2333 enum radeon_family family; 2334 unsigned long flags; 2335 int usec_timeout; 2336 enum radeon_pll_errata pll_errata; 2337 int num_gb_pipes; 2338 int num_z_pipes; 2339 int disp_priority; 2340 /* BIOS */ 2341 uint8_t *bios; 2342 bool is_atom_bios; 2343 uint16_t bios_header_start; 2344 struct radeon_bo *stollen_vga_memory; 2345 /* Register mmio */ 2346 resource_size_t rmmio_base; 2347 resource_size_t rmmio_size; 2348 /* protects concurrent MM_INDEX/DATA based register access */ 2349 spinlock_t mmio_idx_lock; 2350 /* protects concurrent SMC based register access */ 2351 spinlock_t smc_idx_lock; 2352 /* protects concurrent PLL register access */ 2353 spinlock_t pll_idx_lock; 2354 /* protects concurrent MC register access */ 2355 spinlock_t mc_idx_lock; 2356 /* protects concurrent PCIE register access */ 2357 spinlock_t pcie_idx_lock; 2358 /* protects concurrent PCIE_PORT register access */ 2359 spinlock_t pciep_idx_lock; 2360 /* protects concurrent PIF register access */ 2361 spinlock_t pif_idx_lock; 2362 /* protects concurrent CG register access */ 2363 spinlock_t cg_idx_lock; 2364 /* protects concurrent UVD register access */ 2365 spinlock_t uvd_idx_lock; 2366 /* protects concurrent RCU register access */ 2367 spinlock_t rcu_idx_lock; 2368 /* protects concurrent DIDT register access */ 2369 spinlock_t didt_idx_lock; 2370 /* protects concurrent ENDPOINT (audio) register access */ 2371 spinlock_t end_idx_lock; 2372 void __iomem *rmmio; 2373 radeon_rreg_t mc_rreg; 2374 radeon_wreg_t mc_wreg; 2375 radeon_rreg_t pll_rreg; 2376 radeon_wreg_t pll_wreg; 2377 uint32_t pcie_reg_mask; 2378 radeon_rreg_t pciep_rreg; 2379 radeon_wreg_t pciep_wreg; 2380 /* io port */ 2381 int rio_rid; 2382 struct resource *rio_mem; 2383 resource_size_t rio_mem_size; 2384 struct radeon_clock clock; 2385 struct radeon_mc mc; 2386 struct radeon_gart gart; 2387 struct radeon_mode_info mode_info; 2388 struct radeon_scratch scratch; 2389 struct radeon_doorbell doorbell; 2390 struct radeon_mman mman; 2391 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2392 wait_queue_head_t fence_queue; 2393 u64 fence_context; 2394 struct lock ring_lock; 2395 struct radeon_ring ring[RADEON_NUM_RINGS]; 2396 bool ib_pool_ready; 2397 struct radeon_sa_manager ring_tmp_bo; 2398 struct radeon_irq irq; 2399 struct radeon_asic *asic; 2400 struct radeon_gem gem; 2401 struct radeon_pm pm; 2402 struct radeon_uvd uvd; 2403 struct radeon_vce vce; 2404 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2405 struct radeon_wb wb; 2406 struct radeon_dummy_page dummy_page; 2407 bool shutdown; 2408 bool need_dma32; 2409 bool accel_working; 2410 bool fastfb_working; /* IGP feature*/ 2411 bool needs_reset, in_reset; 2412 bool fictitious_range_registered; 2413 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2414 const struct firmware *me_fw; /* all family ME firmware */ 2415 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2416 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2417 const struct firmware *mc_fw; /* NI MC firmware */ 2418 const struct firmware *ce_fw; /* SI CE firmware */ 2419 const struct firmware *mec_fw; /* CIK MEC firmware */ 2420 const struct firmware *mec2_fw; /* KV MEC2 firmware */ 2421 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2422 const struct firmware *smc_fw; /* SMC firmware */ 2423 const struct firmware *uvd_fw; /* UVD firmware */ 2424 const struct firmware *vce_fw; /* VCE firmware */ 2425 bool new_fw; 2426 struct r600_vram_scratch vram_scratch; 2427 int msi_enabled; /* msi enabled */ 2428 struct r600_ih ih; /* r6/700 interrupt ring */ 2429 struct radeon_rlc rlc; 2430 struct radeon_mec mec; 2431 struct delayed_work hotplug_work; 2432 struct work_struct dp_work; 2433 struct work_struct audio_work; 2434 int num_crtc; /* number of crtcs */ 2435 struct lock dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2436 bool has_uvd; 2437 bool has_vce; 2438 struct r600_audio audio; /* audio stuff */ 2439 struct { 2440 ACPI_HANDLE handle; 2441 ACPI_NOTIFY_HANDLER notifier_call; 2442 } acpi; 2443 /* only one userspace can use Hyperz features or CMASK at a time */ 2444 struct drm_file *hyperz_filp; 2445 struct drm_file *cmask_filp; 2446 /* i2c buses */ 2447 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2448 /* debugfs */ 2449 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 2450 unsigned debugfs_count; 2451 /* virtual memory */ 2452 struct radeon_vm_manager vm_manager; 2453 struct lock gpu_clock_mutex; 2454 /* memory stats */ 2455 atomic64_t vram_usage; 2456 atomic64_t gtt_usage; 2457 atomic64_t num_bytes_moved; 2458 atomic_t gpu_reset_counter; 2459 /* ACPI interface */ 2460 struct radeon_atif atif; 2461 struct radeon_atcs atcs; 2462 /* srbm instance registers */ 2463 struct lock srbm_mutex; 2464 /* GRBM index mutex. Protects concurrents access to GRBM index */ 2465 struct lock grbm_idx_mutex; 2466 /* clock, powergating flags */ 2467 u32 cg_flags; 2468 u32 pg_flags; 2469 2470 #ifdef PM_TODO 2471 struct dev_pm_domain vga_pm_domain; 2472 #endif 2473 bool have_disp_power_ref; 2474 u32 px_quirk_flags; 2475 2476 /* tracking pinned memory */ 2477 u64 vram_pin_size; 2478 u64 gart_pin_size; 2479 2480 /* amdkfd interface */ 2481 struct kfd_dev *kfd; 2482 2483 struct lock mn_lock; 2484 DECLARE_HASHTABLE(mn_hash, 7); 2485 }; 2486 2487 bool radeon_is_px(struct drm_device *dev); 2488 int radeon_device_init(struct radeon_device *rdev, 2489 struct drm_device *ddev, 2490 struct pci_dev *pdev, 2491 uint32_t flags); 2492 void radeon_device_fini(struct radeon_device *rdev); 2493 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2494 2495 #define RADEON_MIN_MMIO_SIZE 0x10000 2496 2497 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg); 2498 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2499 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2500 bool always_indirect) 2501 { 2502 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ 2503 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2504 return readl(((void __iomem *)rdev->rmmio) + reg); 2505 else 2506 return r100_mm_rreg_slow(rdev, reg); 2507 } 2508 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2509 bool always_indirect) 2510 { 2511 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2512 writel(v, ((void __iomem *)rdev->rmmio) + reg); 2513 else 2514 r100_mm_wreg_slow(rdev, reg, v); 2515 } 2516 2517 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2518 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2519 2520 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2521 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2522 2523 /* 2524 * Cast helper 2525 */ 2526 extern const struct fence_ops radeon_fence_ops; 2527 2528 static inline struct radeon_fence *to_radeon_fence(struct fence *f) 2529 { 2530 struct radeon_fence *__f = container_of(f, struct radeon_fence, base); 2531 2532 if (__f->base.ops == &radeon_fence_ops) 2533 return __f; 2534 2535 return NULL; 2536 } 2537 2538 /* 2539 * Registers read & write functions. 2540 */ 2541 #define RREG8(reg) readb((rdev->rmmio) + (reg)) 2542 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) 2543 #define RREG16(reg) readw((rdev->rmmio) + (reg)) 2544 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) 2545 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2546 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2547 #define DREG32(reg) DRM_INFO("REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) 2548 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2549 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2550 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2551 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2552 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2553 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2554 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2555 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2556 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2557 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2558 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2559 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2560 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2561 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2562 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2563 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2564 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2565 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2566 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2567 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2568 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2569 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2570 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2571 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2572 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2573 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2574 #define WREG32_P(reg, val, mask) \ 2575 do { \ 2576 uint32_t tmp_ = RREG32(reg); \ 2577 tmp_ &= (mask); \ 2578 tmp_ |= ((val) & ~(mask)); \ 2579 WREG32(reg, tmp_); \ 2580 } while (0) 2581 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2582 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2583 #define WREG32_PLL_P(reg, val, mask) \ 2584 do { \ 2585 uint32_t tmp_ = RREG32_PLL(reg); \ 2586 tmp_ &= (mask); \ 2587 tmp_ |= ((val) & ~(mask)); \ 2588 WREG32_PLL(reg, tmp_); \ 2589 } while (0) 2590 #define WREG32_SMC_P(reg, val, mask) \ 2591 do { \ 2592 uint32_t tmp_ = RREG32_SMC(reg); \ 2593 tmp_ &= (mask); \ 2594 tmp_ |= ((val) & ~(mask)); \ 2595 WREG32_SMC(reg, tmp_); \ 2596 } while (0) 2597 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2598 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2599 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2600 2601 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2602 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2603 2604 /* 2605 * Indirect registers accessors. 2606 * They used to be inlined, but this increases code size by ~65 kbytes. 2607 * Since each performs a pair of MMIO ops 2608 * within a spin_lock_irqsave/spin_unlock_irqrestore region, 2609 * the cost of call+ret is almost negligible. MMIO and locking 2610 * costs several dozens of cycles each at best, call+ret is ~5 cycles. 2611 */ 2612 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); 2613 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2614 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg); 2615 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2616 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg); 2617 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2618 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg); 2619 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2620 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg); 2621 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2622 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg); 2623 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2624 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg); 2625 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2626 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg); 2627 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2628 2629 void r100_pll_errata_after_index(struct radeon_device *rdev); 2630 2631 2632 /* 2633 * ASICs helpers. 2634 */ 2635 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2636 (rdev->pdev->device == 0x5969)) 2637 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2638 (rdev->family == CHIP_RV200) || \ 2639 (rdev->family == CHIP_RS100) || \ 2640 (rdev->family == CHIP_RS200) || \ 2641 (rdev->family == CHIP_RV250) || \ 2642 (rdev->family == CHIP_RV280) || \ 2643 (rdev->family == CHIP_RS300)) 2644 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2645 (rdev->family == CHIP_RV350) || \ 2646 (rdev->family == CHIP_R350) || \ 2647 (rdev->family == CHIP_RV380) || \ 2648 (rdev->family == CHIP_R420) || \ 2649 (rdev->family == CHIP_R423) || \ 2650 (rdev->family == CHIP_RV410) || \ 2651 (rdev->family == CHIP_RS400) || \ 2652 (rdev->family == CHIP_RS480)) 2653 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 2654 (rdev->ddev->pdev->device == 0x9443) || \ 2655 (rdev->ddev->pdev->device == 0x944B) || \ 2656 (rdev->ddev->pdev->device == 0x9506) || \ 2657 (rdev->ddev->pdev->device == 0x9509) || \ 2658 (rdev->ddev->pdev->device == 0x950F) || \ 2659 (rdev->ddev->pdev->device == 0x689C) || \ 2660 (rdev->ddev->pdev->device == 0x689D)) 2661 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2662 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2663 (rdev->family == CHIP_RS690) || \ 2664 (rdev->family == CHIP_RS740) || \ 2665 (rdev->family >= CHIP_R600)) 2666 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2667 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2668 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2669 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2670 (rdev->flags & RADEON_IS_IGP)) 2671 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2672 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2673 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2674 (rdev->flags & RADEON_IS_IGP)) 2675 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2676 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2677 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2678 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2679 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2680 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2681 (rdev->family == CHIP_MULLINS)) 2682 2683 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ 2684 (rdev->ddev->pdev->device == 0x6850) || \ 2685 (rdev->ddev->pdev->device == 0x6858) || \ 2686 (rdev->ddev->pdev->device == 0x6859) || \ 2687 (rdev->ddev->pdev->device == 0x6840) || \ 2688 (rdev->ddev->pdev->device == 0x6841) || \ 2689 (rdev->ddev->pdev->device == 0x6842) || \ 2690 (rdev->ddev->pdev->device == 0x6843)) 2691 2692 /* 2693 * BIOS helpers. 2694 */ 2695 #define RBIOS8(i) (rdev->bios[i]) 2696 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2697 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2698 2699 int radeon_combios_init(struct radeon_device *rdev); 2700 void radeon_combios_fini(struct radeon_device *rdev); 2701 int radeon_atombios_init(struct radeon_device *rdev); 2702 void radeon_atombios_fini(struct radeon_device *rdev); 2703 2704 2705 /* 2706 * RING helpers. 2707 */ 2708 2709 /** 2710 * radeon_ring_write - write a value to the ring 2711 * 2712 * @ring: radeon_ring structure holding ring information 2713 * @v: dword (dw) value to write 2714 * 2715 * Write a value to the requested ring buffer (all asics). 2716 */ 2717 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2718 { 2719 if (ring->count_dw <= 0) 2720 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); 2721 2722 ring->ring[ring->wptr++] = v; 2723 ring->wptr &= ring->ptr_mask; 2724 ring->count_dw--; 2725 ring->ring_free_dw--; 2726 } 2727 2728 /* 2729 * ASICs macro. 2730 */ 2731 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2732 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2733 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2734 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2735 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2736 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2737 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false) 2738 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2739 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f)) 2740 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e)) 2741 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2742 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2743 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) 2744 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2745 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2746 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) 2747 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2748 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2749 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2750 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2751 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2752 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2753 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr)) 2754 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2755 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2756 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2757 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2758 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2759 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2760 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2761 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2762 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2763 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2764 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2765 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2766 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv)) 2767 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv)) 2768 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv)) 2769 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2770 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2771 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2772 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2773 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2774 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2775 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2776 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2777 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2778 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2779 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2780 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2781 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2782 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2783 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2784 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2785 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2786 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2787 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2788 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2789 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2790 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2791 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2792 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2793 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2794 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2795 #define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async)) 2796 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) 2797 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2798 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2799 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2800 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2801 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v)) 2802 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2803 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2804 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2805 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2806 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2807 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2808 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2809 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2810 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2811 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2812 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2813 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2814 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2815 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2816 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2817 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2818 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2819 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2820 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev)) 2821 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev)) 2822 2823 /* Common functions */ 2824 /* AGP */ 2825 extern int radeon_gpu_reset(struct radeon_device *rdev); 2826 extern void radeon_pci_config_reset(struct radeon_device *rdev); 2827 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2828 extern void radeon_agp_disable(struct radeon_device *rdev); 2829 extern int radeon_modeset_init(struct radeon_device *rdev); 2830 extern void radeon_modeset_fini(struct radeon_device *rdev); 2831 extern bool radeon_card_posted(struct radeon_device *rdev); 2832 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2833 extern void radeon_update_display_priority(struct radeon_device *rdev); 2834 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2835 extern void radeon_scratch_init(struct radeon_device *rdev); 2836 extern void radeon_wb_fini(struct radeon_device *rdev); 2837 extern int radeon_wb_init(struct radeon_device *rdev); 2838 extern void radeon_wb_disable(struct radeon_device *rdev); 2839 extern void radeon_surface_init(struct radeon_device *rdev); 2840 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2841 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2842 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2843 extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2844 uint32_t flags); 2845 extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm); 2846 extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm); 2847 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2848 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2849 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2850 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, 2851 bool fbcon, bool freeze); 2852 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2853 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2854 const u32 *registers, 2855 const u32 array_size); 2856 2857 /* 2858 * vm 2859 */ 2860 int radeon_vm_manager_init(struct radeon_device *rdev); 2861 void radeon_vm_manager_fini(struct radeon_device *rdev); 2862 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2863 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2864 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, 2865 struct radeon_vm *vm, 2866 struct list_head *head); 2867 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2868 struct radeon_vm *vm, int ring); 2869 void radeon_vm_flush(struct radeon_device *rdev, 2870 struct radeon_vm *vm, 2871 int ring, struct radeon_fence *fence); 2872 void radeon_vm_fence(struct radeon_device *rdev, 2873 struct radeon_vm *vm, 2874 struct radeon_fence *fence); 2875 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2876 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2877 struct radeon_vm *vm); 2878 int radeon_vm_clear_freed(struct radeon_device *rdev, 2879 struct radeon_vm *vm); 2880 int radeon_vm_clear_invalids(struct radeon_device *rdev, 2881 struct radeon_vm *vm); 2882 int radeon_vm_bo_update(struct radeon_device *rdev, 2883 struct radeon_bo_va *bo_va, 2884 struct ttm_mem_reg *mem); 2885 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2886 struct radeon_bo *bo); 2887 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2888 struct radeon_bo *bo); 2889 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2890 struct radeon_vm *vm, 2891 struct radeon_bo *bo); 2892 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2893 struct radeon_bo_va *bo_va, 2894 uint64_t offset, 2895 uint32_t flags); 2896 void radeon_vm_bo_rmv(struct radeon_device *rdev, 2897 struct radeon_bo_va *bo_va); 2898 2899 /* audio */ 2900 void r600_audio_update_hdmi(struct work_struct *work); 2901 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2902 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2903 void r600_audio_enable(struct radeon_device *rdev, 2904 struct r600_audio_pin *pin, 2905 u8 enable_mask); 2906 void dce6_audio_enable(struct radeon_device *rdev, 2907 struct r600_audio_pin *pin, 2908 u8 enable_mask); 2909 2910 /* 2911 * R600 vram scratch functions 2912 */ 2913 int r600_vram_scratch_init(struct radeon_device *rdev); 2914 void r600_vram_scratch_fini(struct radeon_device *rdev); 2915 2916 /* 2917 * r600 cs checking helper 2918 */ 2919 unsigned r600_mip_minify(unsigned size, unsigned level); 2920 bool r600_fmt_is_valid_color(u32 format); 2921 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2922 int r600_fmt_get_blocksize(u32 format); 2923 int r600_fmt_get_nblocksx(u32 format, u32 w); 2924 int r600_fmt_get_nblocksy(u32 format, u32 h); 2925 2926 /* 2927 * r600 functions used by radeon_encoder.c 2928 */ 2929 struct radeon_hdmi_acr { 2930 u32 clock; 2931 2932 int n_32khz; 2933 int cts_32khz; 2934 2935 int n_44_1khz; 2936 int cts_44_1khz; 2937 2938 int n_48khz; 2939 int cts_48khz; 2940 2941 }; 2942 2943 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 2944 2945 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 2946 u32 tiling_pipe_num, 2947 u32 max_rb_num, 2948 u32 total_max_rb_num, 2949 u32 enabled_rb_mask); 2950 2951 /* 2952 * evergreen functions used by radeon_encoder.c 2953 */ 2954 2955 extern int ni_init_microcode(struct radeon_device *rdev); 2956 extern int ni_mc_load_microcode(struct radeon_device *rdev); 2957 extern void ni_fini_microcode(struct radeon_device *rdev); 2958 2959 /* radeon_acpi.c */ 2960 #if defined(CONFIG_ACPI) 2961 extern int radeon_acpi_init(struct radeon_device *rdev); 2962 extern void radeon_acpi_fini(struct radeon_device *rdev); 2963 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 2964 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 2965 u8 perf_req, bool advertise); 2966 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 2967 2968 /* Prototypes added by @dumbbell. */ 2969 2970 /* atombios_encoders.c */ 2971 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 2972 struct drm_connector *drm_connector); 2973 void radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, 2974 uint32_t supported_device, u16 caps); 2975 2976 /* radeon_atombios.c */ 2977 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 2978 struct drm_display_mode *mode); 2979 2980 /* radeon_legacy_encoders.c */ 2981 void radeon_add_legacy_encoder(struct drm_device *dev, 2982 uint32_t encoder_enum, uint32_t supported_device); 2983 void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder, 2984 struct drm_connector *drm_connector); 2985 2986 /* radeon_pm.c */ 2987 void radeon_pm_acpi_event_handler(struct radeon_device *rdev); 2988 2989 /* radeon_ttm.c */ 2990 int radeon_ttm_init(struct radeon_device *rdev); 2991 void radeon_ttm_fini(struct radeon_device *rdev); 2992 2993 /* r600.c */ 2994 int r600_ih_ring_alloc(struct radeon_device *rdev); 2995 void r600_ih_ring_fini(struct radeon_device *rdev); 2996 #else 2997 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 2998 static inline void radeon_acpi_fini(struct radeon_device *rdev) { } 2999 #endif 3000 3001 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 3002 struct radeon_cs_packet *pkt, 3003 unsigned idx); 3004 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 3005 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 3006 struct radeon_cs_packet *pkt); 3007 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 3008 struct radeon_bo_list **cs_reloc, 3009 int nomm); 3010 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 3011 uint32_t *vline_start_end, 3012 uint32_t *vline_status); 3013 3014 #include "radeon_object.h" 3015 3016 #endif 3017