1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #ifndef __RADEON_H__ 30 #define __RADEON_H__ 31 32 /* TODO: Here are things that needs to be done : 33 * - surface allocator & initializer : (bit like scratch reg) should 34 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 35 * related to surface 36 * - WB : write back stuff (do it bit like scratch reg things) 37 * - Vblank : look at Jesse's rework and what we should do 38 * - r600/r700: gart & cp 39 * - cs : clean cs ioctl use bitmap & things like that. 40 * - power management stuff 41 * - Barrier in gart code 42 * - Unmappabled vram ? 43 * - TESTING, TESTING, TESTING 44 */ 45 46 /* Initialization path: 47 * We expect that acceleration initialization might fail for various 48 * reasons even thought we work hard to make it works on most 49 * configurations. In order to still have a working userspace in such 50 * situation the init path must succeed up to the memory controller 51 * initialization point. Failure before this point are considered as 52 * fatal error. Here is the init callchain : 53 * radeon_device_init perform common structure, mutex initialization 54 * asic_init setup the GPU memory layout and perform all 55 * one time initialization (failure in this 56 * function are considered fatal) 57 * asic_startup setup the GPU acceleration, in order to 58 * follow guideline the first thing this 59 * function should do is setting the GPU 60 * memory controller (only MC setup failure 61 * are considered as fatal) 62 */ 63 64 #include <sys/condvar.h> 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/linker.h> 68 #include <linux/firmware.h> 69 #include <linux/seq_file.h> 70 71 #include <contrib/dev/acpica/source/include/acpi.h> 72 #include <dev/acpica/acpivar.h> 73 74 #include <linux/atomic.h> 75 #include <linux/wait.h> 76 #include <linux/list.h> 77 #include <linux/kref.h> 78 #include <linux/hashtable.h> 79 #include <linux/fence.h> 80 81 #include <drm/ttm/ttm_bo_api.h> 82 #include <drm/ttm/ttm_bo_driver.h> 83 #include <drm/ttm/ttm_placement.h> 84 #include <drm/ttm/ttm_module.h> 85 #include <drm/ttm/ttm_execbuf_util.h> 86 87 #include <drm/drm_gem.h> 88 #define CONFIG_ACPI 1 89 90 #include "radeon_family.h" 91 #include "radeon_mode.h" 92 #include "radeon_reg.h" 93 94 /* 95 * Modules parameters. 96 */ 97 extern int radeon_no_wb; 98 extern int radeon_modeset; 99 extern int radeon_dynclks; 100 extern int radeon_r4xx_atom; 101 extern int radeon_agpmode; 102 extern int radeon_vram_limit; 103 extern int radeon_gart_size; 104 extern int radeon_benchmarking; 105 extern int radeon_testing; 106 extern int radeon_connector_table; 107 extern int radeon_tv; 108 extern int radeon_audio; 109 extern int radeon_disp_priority; 110 extern int radeon_hw_i2c; 111 extern int radeon_pcie_gen2; 112 extern int radeon_msi; 113 extern int radeon_lockup_timeout; 114 extern int radeon_fastfb; 115 extern int radeon_dpm; 116 extern int radeon_aspm; 117 extern int radeon_runtime_pm; 118 extern int radeon_hard_reset; 119 extern int radeon_vm_size; 120 extern int radeon_vm_block_size; 121 extern int radeon_deep_color; 122 extern int radeon_use_pflipirq; 123 extern int radeon_bapm; 124 extern int radeon_backlight; 125 126 /* 127 * Copy from radeon_drv.h so we don't have to include both and have conflicting 128 * symbol; 129 */ 130 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 131 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 132 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 133 #define RADEON_IB_POOL_SIZE 16 134 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 135 #define RADEONFB_CONN_LIMIT 4 136 #define RADEON_BIOS_NUM_SCRATCH 8 137 138 /* internal ring indices */ 139 /* r1xx+ has gfx CP ring */ 140 #define RADEON_RING_TYPE_GFX_INDEX 0 141 142 /* cayman has 2 compute CP rings */ 143 #define CAYMAN_RING_TYPE_CP1_INDEX 1 144 #define CAYMAN_RING_TYPE_CP2_INDEX 2 145 146 /* R600+ has an async dma ring */ 147 #define R600_RING_TYPE_DMA_INDEX 3 148 /* cayman add a second async dma ring */ 149 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 150 151 /* R600+ */ 152 #define R600_RING_TYPE_UVD_INDEX 5 153 154 /* TN+ */ 155 #define TN_RING_TYPE_VCE1_INDEX 6 156 #define TN_RING_TYPE_VCE2_INDEX 7 157 158 /* max number of rings */ 159 #define RADEON_NUM_RINGS 8 160 161 /* number of hw syncs before falling back on blocking */ 162 #define RADEON_NUM_SYNCS 4 163 164 /* hardcode those limit for now */ 165 #define RADEON_VA_IB_OFFSET (1 << 20) 166 #define RADEON_VA_RESERVED_SIZE (8 << 20) 167 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 168 169 /* hard reset data */ 170 #define RADEON_ASIC_RESET_DATA 0x39d5e86b 171 172 /* reset flags */ 173 #define RADEON_RESET_GFX (1 << 0) 174 #define RADEON_RESET_COMPUTE (1 << 1) 175 #define RADEON_RESET_DMA (1 << 2) 176 #define RADEON_RESET_CP (1 << 3) 177 #define RADEON_RESET_GRBM (1 << 4) 178 #define RADEON_RESET_DMA1 (1 << 5) 179 #define RADEON_RESET_RLC (1 << 6) 180 #define RADEON_RESET_SEM (1 << 7) 181 #define RADEON_RESET_IH (1 << 8) 182 #define RADEON_RESET_VMC (1 << 9) 183 #define RADEON_RESET_MC (1 << 10) 184 #define RADEON_RESET_DISPLAY (1 << 11) 185 186 /* CG block flags */ 187 #define RADEON_CG_BLOCK_GFX (1 << 0) 188 #define RADEON_CG_BLOCK_MC (1 << 1) 189 #define RADEON_CG_BLOCK_SDMA (1 << 2) 190 #define RADEON_CG_BLOCK_UVD (1 << 3) 191 #define RADEON_CG_BLOCK_VCE (1 << 4) 192 #define RADEON_CG_BLOCK_HDP (1 << 5) 193 #define RADEON_CG_BLOCK_BIF (1 << 6) 194 195 /* CG flags */ 196 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 197 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 198 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 199 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 200 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 201 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 202 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 203 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 204 #define RADEON_CG_SUPPORT_MC_LS (1 << 8) 205 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 206 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 207 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 208 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 209 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 210 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 211 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 212 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 213 214 /* PG flags */ 215 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 216 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 217 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 218 #define RADEON_PG_SUPPORT_UVD (1 << 3) 219 #define RADEON_PG_SUPPORT_VCE (1 << 4) 220 #define RADEON_PG_SUPPORT_CP (1 << 5) 221 #define RADEON_PG_SUPPORT_GDS (1 << 6) 222 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 223 #define RADEON_PG_SUPPORT_SDMA (1 << 8) 224 #define RADEON_PG_SUPPORT_ACP (1 << 9) 225 #define RADEON_PG_SUPPORT_SAMU (1 << 10) 226 227 /* max cursor sizes (in pixels) */ 228 #define CURSOR_WIDTH 64 229 #define CURSOR_HEIGHT 64 230 231 #define CIK_CURSOR_WIDTH 128 232 #define CIK_CURSOR_HEIGHT 128 233 234 /* 235 * Errata workarounds. 236 */ 237 enum radeon_pll_errata { 238 CHIP_ERRATA_R300_CG = 0x00000001, 239 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 240 CHIP_ERRATA_PLL_DELAY = 0x00000004 241 }; 242 243 244 struct radeon_device; 245 246 247 /* 248 * BIOS. 249 */ 250 bool radeon_get_bios(struct radeon_device *rdev); 251 252 /* 253 * Dummy page 254 */ 255 struct radeon_dummy_page { 256 struct drm_dma_handle *dmah; 257 dma_addr_t addr; 258 }; 259 int radeon_dummy_page_init(struct radeon_device *rdev); 260 void radeon_dummy_page_fini(struct radeon_device *rdev); 261 262 263 /* 264 * Clocks 265 */ 266 struct radeon_clock { 267 struct radeon_pll p1pll; 268 struct radeon_pll p2pll; 269 struct radeon_pll dcpll; 270 struct radeon_pll spll; 271 struct radeon_pll mpll; 272 /* 10 Khz units */ 273 uint32_t default_mclk; 274 uint32_t default_sclk; 275 uint32_t default_dispclk; 276 uint32_t current_dispclk; 277 uint32_t dp_extclk; 278 uint32_t max_pixel_clock; 279 }; 280 281 /* 282 * Power management 283 */ 284 int radeon_pm_init(struct radeon_device *rdev); 285 int radeon_pm_late_init(struct radeon_device *rdev); 286 void radeon_pm_fini(struct radeon_device *rdev); 287 void radeon_pm_compute_clocks(struct radeon_device *rdev); 288 void radeon_pm_suspend(struct radeon_device *rdev); 289 void radeon_pm_resume(struct radeon_device *rdev); 290 void radeon_combios_get_power_modes(struct radeon_device *rdev); 291 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 292 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 293 u8 clock_type, 294 u32 clock, 295 bool strobe_mode, 296 struct atom_clock_dividers *dividers); 297 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 298 u32 clock, 299 bool strobe_mode, 300 struct atom_mpll_param *mpll_param); 301 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 302 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 303 u16 voltage_level, u8 voltage_type, 304 u32 *gpio_value, u32 *gpio_mask); 305 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 306 u32 eng_clock, u32 mem_clock); 307 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 308 u8 voltage_type, u16 *voltage_step); 309 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 310 u16 voltage_id, u16 *voltage); 311 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 312 u16 *voltage, 313 u16 leakage_idx); 314 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 315 u16 *leakage_id); 316 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 317 u16 *vddc, u16 *vddci, 318 u16 virtual_voltage_id, 319 u16 vbios_voltage_id); 320 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 321 u16 virtual_voltage_id, 322 u16 *voltage); 323 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 324 u8 voltage_type, 325 u16 nominal_voltage, 326 u16 *true_voltage); 327 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 328 u8 voltage_type, u16 *min_voltage); 329 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 330 u8 voltage_type, u16 *max_voltage); 331 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 332 u8 voltage_type, u8 voltage_mode, 333 struct atom_voltage_table *voltage_table); 334 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 335 u8 voltage_type, u8 voltage_mode); 336 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 337 u8 voltage_type, 338 u8 *svd_gpio_id, u8 *svc_gpio_id); 339 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 340 u32 mem_clock); 341 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 342 u32 mem_clock); 343 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 344 u8 module_index, 345 struct atom_mc_reg_table *reg_table); 346 int radeon_atom_get_memory_info(struct radeon_device *rdev, 347 u8 module_index, struct atom_memory_info *mem_info); 348 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 349 bool gddr5, u8 module_index, 350 struct atom_memory_clock_range_table *mclk_range_table); 351 void rs690_pm_info(struct radeon_device *rdev); 352 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 353 unsigned *bankh, unsigned *mtaspect, 354 unsigned *tile_split); 355 356 /* 357 * Fences. 358 */ 359 struct radeon_fence_driver { 360 struct radeon_device *rdev; 361 uint32_t scratch_reg; 362 uint64_t gpu_addr; 363 volatile uint32_t *cpu_addr; 364 /* sync_seq is protected by ring emission lock */ 365 uint64_t sync_seq[RADEON_NUM_RINGS]; 366 atomic64_t last_seq; 367 bool initialized; 368 struct delayed_work lockup_work; 369 }; 370 371 struct radeon_fence { 372 struct radeon_device *rdev; 373 unsigned int kref; 374 /* protected by radeon_fence.lock */ 375 uint64_t seq; 376 /* RB, DMA, etc. */ 377 unsigned ring; 378 }; 379 380 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 381 int radeon_fence_driver_init(struct radeon_device *rdev); 382 void radeon_fence_driver_fini(struct radeon_device *rdev); 383 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); 384 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 385 void radeon_fence_process(struct radeon_device *rdev, int ring); 386 bool radeon_fence_signaled(struct radeon_fence *fence); 387 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 388 int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 389 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 390 int radeon_fence_wait_any(struct radeon_device *rdev, 391 struct radeon_fence **fences, 392 bool intr); 393 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 394 void radeon_fence_unref(struct radeon_fence **fence); 395 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 396 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 397 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 398 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 399 struct radeon_fence *b) 400 { 401 if (!a) { 402 return b; 403 } 404 405 if (!b) { 406 return a; 407 } 408 409 BUG_ON(a->ring != b->ring); 410 411 if (a->seq > b->seq) { 412 return a; 413 } else { 414 return b; 415 } 416 } 417 418 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 419 struct radeon_fence *b) 420 { 421 if (!a) { 422 return false; 423 } 424 425 if (!b) { 426 return true; 427 } 428 429 BUG_ON(a->ring != b->ring); 430 431 return a->seq < b->seq; 432 } 433 434 /* 435 * Tiling registers 436 */ 437 struct radeon_surface_reg { 438 struct radeon_bo *bo; 439 }; 440 441 #define RADEON_GEM_MAX_SURFACES 8 442 443 /* 444 * TTM. 445 */ 446 struct radeon_mman { 447 struct ttm_bo_global_ref bo_global_ref; 448 struct drm_global_reference mem_global_ref; 449 struct ttm_bo_device bdev; 450 bool mem_global_referenced; 451 bool initialized; 452 453 #if defined(CONFIG_DEBUG_FS) 454 struct dentry *vram; 455 struct dentry *gtt; 456 #endif 457 }; 458 459 /* bo virtual address in a specific vm */ 460 struct radeon_bo_va { 461 /* protected by bo being reserved */ 462 struct list_head bo_list; 463 uint64_t soffset; 464 uint64_t eoffset; 465 uint32_t flags; 466 uint64_t addr; 467 unsigned ref_count; 468 469 /* protected by vm mutex */ 470 struct list_head vm_list; 471 struct list_head vm_status; 472 473 /* constant after initialization */ 474 struct radeon_vm *vm; 475 struct radeon_bo *bo; 476 }; 477 478 struct radeon_bo { 479 /* Protected by gem.mutex */ 480 struct list_head list; 481 /* Protected by tbo.reserved */ 482 u32 initial_domain; 483 struct ttm_place placements[3]; 484 struct ttm_placement placement; 485 struct ttm_buffer_object tbo; 486 struct ttm_bo_kmap_obj kmap; 487 u32 flags; 488 unsigned pin_count; 489 void *kptr; 490 u32 tiling_flags; 491 u32 pitch; 492 int surface_reg; 493 /* list of all virtual address to which this bo 494 * is associated to 495 */ 496 struct list_head va; 497 /* Constant after initialization */ 498 struct radeon_device *rdev; 499 struct drm_gem_object gem_base; 500 501 struct ttm_bo_kmap_obj dma_buf_vmap; 502 pid_t pid; 503 }; 504 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 505 506 int radeon_gem_debugfs_init(struct radeon_device *rdev); 507 508 /* sub-allocation manager, it has to be protected by another lock. 509 * By conception this is an helper for other part of the driver 510 * like the indirect buffer or semaphore, which both have their 511 * locking. 512 * 513 * Principe is simple, we keep a list of sub allocation in offset 514 * order (first entry has offset == 0, last entry has the highest 515 * offset). 516 * 517 * When allocating new object we first check if there is room at 518 * the end total_size - (last_object_offset + last_object_size) >= 519 * alloc_size. If so we allocate new object there. 520 * 521 * When there is not enough room at the end, we start waiting for 522 * each sub object until we reach object_offset+object_size >= 523 * alloc_size, this object then become the sub object we return. 524 * 525 * Alignment can't be bigger than page size. 526 * 527 * Hole are not considered for allocation to keep things simple. 528 * Assumption is that there won't be hole (all object on same 529 * alignment). 530 */ 531 struct radeon_sa_manager { 532 struct cv wq; 533 struct lock wq_lock; 534 struct radeon_bo *bo; 535 struct list_head *hole; 536 struct list_head flist[RADEON_NUM_RINGS]; 537 struct list_head olist; 538 unsigned size; 539 uint64_t gpu_addr; 540 void *cpu_ptr; 541 uint32_t domain; 542 uint32_t align; 543 }; 544 545 struct radeon_sa_bo; 546 547 /* sub-allocation buffer */ 548 struct radeon_sa_bo { 549 struct list_head olist; 550 struct list_head flist; 551 struct radeon_sa_manager *manager; 552 unsigned soffset; 553 unsigned eoffset; 554 struct radeon_fence *fence; 555 }; 556 557 /* 558 * GEM objects. 559 */ 560 struct radeon_gem { 561 struct spinlock mutex; 562 struct list_head objects; 563 }; 564 565 int radeon_gem_init(struct radeon_device *rdev); 566 void radeon_gem_fini(struct radeon_device *rdev); 567 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, 568 int alignment, int initial_domain, 569 u32 flags, bool kernel, 570 struct drm_gem_object **obj); 571 572 int radeon_mode_dumb_create(struct drm_file *file_priv, 573 struct drm_device *dev, 574 struct drm_mode_create_dumb *args); 575 int radeon_mode_dumb_mmap(struct drm_file *filp, 576 struct drm_device *dev, 577 uint32_t handle, uint64_t *offset_p); 578 579 /* 580 * Semaphores. 581 */ 582 struct radeon_semaphore { 583 struct radeon_sa_bo *sa_bo; 584 signed waiters; 585 uint64_t gpu_addr; 586 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 587 }; 588 589 int radeon_semaphore_create(struct radeon_device *rdev, 590 struct radeon_semaphore **semaphore); 591 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 592 struct radeon_semaphore *semaphore); 593 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 594 struct radeon_semaphore *semaphore); 595 void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore, 596 struct radeon_fence *fence); 597 int radeon_semaphore_sync_rings(struct radeon_device *rdev, 598 struct radeon_semaphore *semaphore, 599 int waiting_ring); 600 void radeon_semaphore_free(struct radeon_device *rdev, 601 struct radeon_semaphore **semaphore, 602 struct radeon_fence *fence); 603 604 /* 605 * GART structures, functions & helpers 606 */ 607 struct radeon_mc; 608 609 #define RADEON_GPU_PAGE_SIZE 4096 610 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 611 #define RADEON_GPU_PAGE_SHIFT 12 612 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 613 614 #define RADEON_GART_PAGE_DUMMY 0 615 #define RADEON_GART_PAGE_VALID (1 << 0) 616 #define RADEON_GART_PAGE_READ (1 << 1) 617 #define RADEON_GART_PAGE_WRITE (1 << 2) 618 #define RADEON_GART_PAGE_SNOOP (1 << 3) 619 620 struct radeon_gart { 621 struct drm_dma_handle *dmah; 622 dma_addr_t table_addr; 623 struct radeon_bo *robj; 624 void *ptr; 625 unsigned num_gpu_pages; 626 unsigned num_cpu_pages; 627 unsigned table_size; 628 vm_page_t *pages; 629 dma_addr_t *pages_addr; 630 bool ready; 631 }; 632 633 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 634 void radeon_gart_table_ram_free(struct radeon_device *rdev); 635 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 636 void radeon_gart_table_vram_free(struct radeon_device *rdev); 637 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 638 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 639 int radeon_gart_init(struct radeon_device *rdev); 640 void radeon_gart_fini(struct radeon_device *rdev); 641 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 642 int pages); 643 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 644 int pages, vm_page_t *pagelist, 645 dma_addr_t *dma_addr, uint32_t flags); 646 647 648 /* 649 * GPU MC structures, functions & helpers 650 */ 651 struct radeon_mc { 652 resource_size_t aper_size; 653 resource_size_t aper_base; 654 resource_size_t agp_base; 655 /* for some chips with <= 32MB we need to lie 656 * about vram size near mc fb location */ 657 u64 mc_vram_size; 658 u64 visible_vram_size; 659 u64 gtt_size; 660 u64 gtt_start; 661 u64 gtt_end; 662 u64 vram_start; 663 u64 vram_end; 664 unsigned vram_width; 665 u64 real_vram_size; 666 int vram_mtrr; 667 bool vram_is_ddr; 668 bool igp_sideport_enabled; 669 u64 gtt_base_align; 670 u64 mc_mask; 671 }; 672 673 bool radeon_combios_sideport_present(struct radeon_device *rdev); 674 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 675 676 /* 677 * GPU scratch registers structures, functions & helpers 678 */ 679 struct radeon_scratch { 680 unsigned num_reg; 681 uint32_t reg_base; 682 bool free[32]; 683 uint32_t reg[32]; 684 }; 685 686 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 687 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 688 689 /* 690 * GPU doorbell structures, functions & helpers 691 */ 692 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 693 694 struct radeon_doorbell { 695 /* doorbell mmio */ 696 resource_size_t base; 697 resource_size_t size; 698 u32 __iomem *ptr; 699 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 700 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)]; 701 }; 702 703 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 704 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 705 706 /* 707 * IRQS. 708 */ 709 710 struct radeon_flip_work { 711 struct work_struct flip_work; 712 struct work_struct unpin_work; 713 struct radeon_device *rdev; 714 int crtc_id; 715 uint64_t base; 716 struct drm_pending_vblank_event *event; 717 struct radeon_bo *old_rbo; 718 struct radeon_fence *fence; 719 }; 720 721 struct r500_irq_stat_regs { 722 u32 disp_int; 723 u32 hdmi0_status; 724 }; 725 726 struct r600_irq_stat_regs { 727 u32 disp_int; 728 u32 disp_int_cont; 729 u32 disp_int_cont2; 730 u32 d1grph_int; 731 u32 d2grph_int; 732 u32 hdmi0_status; 733 u32 hdmi1_status; 734 }; 735 736 struct evergreen_irq_stat_regs { 737 u32 disp_int; 738 u32 disp_int_cont; 739 u32 disp_int_cont2; 740 u32 disp_int_cont3; 741 u32 disp_int_cont4; 742 u32 disp_int_cont5; 743 u32 d1grph_int; 744 u32 d2grph_int; 745 u32 d3grph_int; 746 u32 d4grph_int; 747 u32 d5grph_int; 748 u32 d6grph_int; 749 u32 afmt_status1; 750 u32 afmt_status2; 751 u32 afmt_status3; 752 u32 afmt_status4; 753 u32 afmt_status5; 754 u32 afmt_status6; 755 }; 756 757 struct cik_irq_stat_regs { 758 u32 disp_int; 759 u32 disp_int_cont; 760 u32 disp_int_cont2; 761 u32 disp_int_cont3; 762 u32 disp_int_cont4; 763 u32 disp_int_cont5; 764 u32 disp_int_cont6; 765 u32 d1grph_int; 766 u32 d2grph_int; 767 u32 d3grph_int; 768 u32 d4grph_int; 769 u32 d5grph_int; 770 u32 d6grph_int; 771 }; 772 773 union radeon_irq_stat_regs { 774 struct r500_irq_stat_regs r500; 775 struct r600_irq_stat_regs r600; 776 struct evergreen_irq_stat_regs evergreen; 777 struct cik_irq_stat_regs cik; 778 }; 779 780 struct radeon_irq { 781 bool installed; 782 struct lock lock; 783 atomic_t ring_int[RADEON_NUM_RINGS]; 784 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 785 atomic_t pflip[RADEON_MAX_CRTCS]; 786 wait_queue_head_t vblank_queue; 787 bool hpd[RADEON_MAX_HPD_PINS]; 788 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 789 union radeon_irq_stat_regs stat_regs; 790 bool dpm_thermal; 791 }; 792 793 int radeon_irq_kms_init(struct radeon_device *rdev); 794 void radeon_irq_kms_fini(struct radeon_device *rdev); 795 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 796 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 797 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 798 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 799 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 800 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 801 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 802 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 803 804 /* 805 * CP & rings. 806 */ 807 808 struct radeon_ib { 809 struct radeon_sa_bo *sa_bo; 810 uint32_t length_dw; 811 uint64_t gpu_addr; 812 uint32_t *ptr; 813 int ring; 814 struct radeon_fence *fence; 815 struct radeon_vm *vm; 816 bool is_const_ib; 817 struct radeon_semaphore *semaphore; 818 }; 819 820 struct radeon_ring { 821 struct radeon_bo *ring_obj; 822 volatile uint32_t *ring; 823 unsigned rptr_offs; 824 unsigned rptr_save_reg; 825 u64 next_rptr_gpu_addr; 826 volatile u32 *next_rptr_cpu_addr; 827 unsigned wptr; 828 unsigned wptr_old; 829 unsigned ring_size; 830 unsigned ring_free_dw; 831 int count_dw; 832 atomic_t last_rptr; 833 atomic64_t last_activity; 834 uint64_t gpu_addr; 835 uint32_t align_mask; 836 uint32_t ptr_mask; 837 bool ready; 838 u32 nop; 839 u32 idx; 840 u64 last_semaphore_signal_addr; 841 u64 last_semaphore_wait_addr; 842 /* for CIK queues */ 843 u32 me; 844 u32 pipe; 845 u32 queue; 846 struct radeon_bo *mqd_obj; 847 u32 doorbell_index; 848 unsigned wptr_offs; 849 }; 850 851 struct radeon_mec { 852 struct radeon_bo *hpd_eop_obj; 853 u64 hpd_eop_gpu_addr; 854 u32 num_pipe; 855 u32 num_mec; 856 u32 num_queue; 857 }; 858 859 /* 860 * VM 861 */ 862 863 /* maximum number of VMIDs */ 864 #define RADEON_NUM_VM 16 865 866 /* number of entries in page table */ 867 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) 868 869 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 870 #define RADEON_VM_PTB_ALIGN_SIZE 32768 871 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 872 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 873 874 #define R600_PTE_VALID (1 << 0) 875 #define R600_PTE_SYSTEM (1 << 1) 876 #define R600_PTE_SNOOPED (1 << 2) 877 #define R600_PTE_READABLE (1 << 5) 878 #define R600_PTE_WRITEABLE (1 << 6) 879 880 /* PTE (Page Table Entry) fragment field for different page sizes */ 881 #define R600_PTE_FRAG_4KB (0 << 7) 882 #define R600_PTE_FRAG_64KB (4 << 7) 883 #define R600_PTE_FRAG_256KB (6 << 7) 884 885 /* flags needed to be set so we can copy directly from the GART table */ 886 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ 887 R600_PTE_SYSTEM | R600_PTE_VALID ) 888 889 struct radeon_vm_pt { 890 struct radeon_bo *bo; 891 uint64_t addr; 892 }; 893 894 struct radeon_vm { 895 struct list_head va; 896 unsigned id; 897 898 /* BOs moved, but not yet updated in the PT */ 899 struct list_head invalidated; 900 901 /* BOs freed, but not yet updated in the PT */ 902 struct list_head freed; 903 904 /* contains the page directory */ 905 struct radeon_bo *page_directory; 906 uint64_t pd_gpu_addr; 907 unsigned max_pde_used; 908 909 /* array of page tables, one for each page directory entry */ 910 struct radeon_vm_pt *page_tables; 911 912 struct radeon_bo_va *ib_bo_va; 913 914 struct lock mutex; 915 /* last fence for cs using this vm */ 916 struct radeon_fence *fence; 917 /* last flush or NULL if we still need to flush */ 918 struct radeon_fence *last_flush; 919 /* last use of vmid */ 920 struct radeon_fence *last_id_use; 921 }; 922 923 struct radeon_vm_manager { 924 struct radeon_fence *active[RADEON_NUM_VM]; 925 uint32_t max_pfn; 926 /* number of VMIDs */ 927 unsigned nvm; 928 /* vram base address for page table entry */ 929 u64 vram_base_offset; 930 /* is vm enabled? */ 931 bool enabled; 932 /* for hw to save the PD addr on suspend/resume */ 933 uint32_t saved_table_addr[RADEON_NUM_VM]; 934 }; 935 936 /* 937 * file private structure 938 */ 939 struct radeon_fpriv { 940 struct radeon_vm vm; 941 }; 942 943 /* 944 * R6xx+ IH ring 945 */ 946 struct r600_ih { 947 struct radeon_bo *ring_obj; 948 volatile uint32_t *ring; 949 unsigned rptr; 950 unsigned ring_size; 951 uint64_t gpu_addr; 952 uint32_t ptr_mask; 953 atomic_t lock; 954 bool enabled; 955 }; 956 957 /* 958 * RLC stuff 959 */ 960 #include "clearstate_defs.h" 961 962 struct radeon_rlc { 963 /* for power gating */ 964 struct radeon_bo *save_restore_obj; 965 uint64_t save_restore_gpu_addr; 966 volatile uint32_t *sr_ptr; 967 const u32 *reg_list; 968 u32 reg_list_size; 969 /* for clear state */ 970 struct radeon_bo *clear_state_obj; 971 uint64_t clear_state_gpu_addr; 972 volatile uint32_t *cs_ptr; 973 const struct cs_section_def *cs_data; 974 u32 clear_state_size; 975 /* for cp tables */ 976 struct radeon_bo *cp_table_obj; 977 uint64_t cp_table_gpu_addr; 978 volatile uint32_t *cp_table_ptr; 979 u32 cp_table_size; 980 }; 981 982 int radeon_ib_get(struct radeon_device *rdev, int ring, 983 struct radeon_ib *ib, struct radeon_vm *vm, 984 unsigned size); 985 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 986 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 987 struct radeon_ib *const_ib, bool hdp_flush); 988 int radeon_ib_pool_init(struct radeon_device *rdev); 989 void radeon_ib_pool_fini(struct radeon_device *rdev); 990 int radeon_ib_ring_tests(struct radeon_device *rdev); 991 /* Ring access between begin & end cannot sleep */ 992 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 993 struct radeon_ring *ring); 994 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 995 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 996 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 997 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, 998 bool hdp_flush); 999 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1000 bool hdp_flush); 1001 void radeon_ring_undo(struct radeon_ring *ring); 1002 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 1003 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 1004 void radeon_ring_lockup_update(struct radeon_device *rdev, 1005 struct radeon_ring *ring); 1006 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 1007 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 1008 uint32_t **data); 1009 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 1010 unsigned size, uint32_t *data); 1011 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 1012 unsigned rptr_offs, u32 nop); 1013 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 1014 1015 1016 /* r600 async dma */ 1017 void r600_dma_stop(struct radeon_device *rdev); 1018 int r600_dma_resume(struct radeon_device *rdev); 1019 void r600_dma_fini(struct radeon_device *rdev); 1020 1021 void cayman_dma_stop(struct radeon_device *rdev); 1022 int cayman_dma_resume(struct radeon_device *rdev); 1023 void cayman_dma_fini(struct radeon_device *rdev); 1024 1025 /* 1026 * CS. 1027 */ 1028 struct radeon_cs_reloc { 1029 struct drm_gem_object *gobj; 1030 struct radeon_bo *robj; 1031 struct ttm_validate_buffer tv; 1032 uint64_t gpu_offset; 1033 unsigned prefered_domains; 1034 unsigned allowed_domains; 1035 uint32_t tiling_flags; 1036 uint32_t handle; 1037 }; 1038 1039 struct radeon_cs_chunk { 1040 uint32_t chunk_id; 1041 uint32_t length_dw; 1042 uint32_t *kdata; 1043 void __user *user_ptr; 1044 }; 1045 1046 struct radeon_cs_parser { 1047 struct device *dev; 1048 struct radeon_device *rdev; 1049 struct drm_file *filp; 1050 /* chunks */ 1051 unsigned nchunks; 1052 struct radeon_cs_chunk *chunks; 1053 uint64_t *chunks_array; 1054 /* IB */ 1055 unsigned idx; 1056 /* relocations */ 1057 unsigned nrelocs; 1058 struct radeon_cs_reloc *relocs; 1059 struct radeon_cs_reloc **relocs_ptr; 1060 struct radeon_cs_reloc *vm_bos; 1061 struct list_head validated; 1062 unsigned dma_reloc_idx; 1063 /* indices of various chunks */ 1064 int chunk_ib_idx; 1065 int chunk_relocs_idx; 1066 int chunk_flags_idx; 1067 int chunk_const_ib_idx; 1068 struct radeon_ib ib; 1069 struct radeon_ib const_ib; 1070 void *track; 1071 unsigned family; 1072 int parser_error; 1073 u32 cs_flags; 1074 u32 ring; 1075 s32 priority; 1076 struct ww_acquire_ctx ticket; 1077 }; 1078 1079 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1080 { 1081 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 1082 1083 if (ibc->kdata) 1084 return ibc->kdata[idx]; 1085 return p->ib.ptr[idx]; 1086 } 1087 1088 1089 struct radeon_cs_packet { 1090 unsigned idx; 1091 unsigned type; 1092 unsigned reg; 1093 unsigned opcode; 1094 int count; 1095 unsigned one_reg_wr; 1096 }; 1097 1098 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1099 struct radeon_cs_packet *pkt, 1100 unsigned idx, unsigned reg); 1101 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 1102 struct radeon_cs_packet *pkt); 1103 1104 1105 /* 1106 * AGP 1107 */ 1108 int radeon_agp_init(struct radeon_device *rdev); 1109 void radeon_agp_resume(struct radeon_device *rdev); 1110 void radeon_agp_suspend(struct radeon_device *rdev); 1111 void radeon_agp_fini(struct radeon_device *rdev); 1112 1113 1114 /* 1115 * Writeback 1116 */ 1117 struct radeon_wb { 1118 struct radeon_bo *wb_obj; 1119 volatile uint32_t *wb; 1120 uint64_t gpu_addr; 1121 bool enabled; 1122 bool use_event; 1123 }; 1124 1125 #define RADEON_WB_SCRATCH_OFFSET 0 1126 #define RADEON_WB_RING0_NEXT_RPTR 256 1127 #define RADEON_WB_CP_RPTR_OFFSET 1024 1128 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1129 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1130 #define R600_WB_DMA_RPTR_OFFSET 1792 1131 #define R600_WB_IH_WPTR_OFFSET 2048 1132 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1133 #define R600_WB_EVENT_OFFSET 3072 1134 #define CIK_WB_CP1_WPTR_OFFSET 3328 1135 #define CIK_WB_CP2_WPTR_OFFSET 3584 1136 #define R600_WB_DMA_RING_TEST_OFFSET 3588 1137 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 1138 1139 /** 1140 * struct radeon_pm - power management datas 1141 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1142 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1143 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1144 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1145 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1146 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1147 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1148 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1149 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1150 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1151 * @needed_bandwidth: current bandwidth needs 1152 * 1153 * It keeps track of various data needed to take powermanagement decision. 1154 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1155 * Equation between gpu/memory clock and available bandwidth is hw dependent 1156 * (type of memory, bus size, efficiency, ...) 1157 */ 1158 1159 enum radeon_pm_method { 1160 PM_METHOD_PROFILE, 1161 PM_METHOD_DYNPM, 1162 PM_METHOD_DPM, 1163 }; 1164 1165 enum radeon_dynpm_state { 1166 DYNPM_STATE_DISABLED, 1167 DYNPM_STATE_MINIMUM, 1168 DYNPM_STATE_PAUSED, 1169 DYNPM_STATE_ACTIVE, 1170 DYNPM_STATE_SUSPENDED, 1171 }; 1172 enum radeon_dynpm_action { 1173 DYNPM_ACTION_NONE, 1174 DYNPM_ACTION_MINIMUM, 1175 DYNPM_ACTION_DOWNCLOCK, 1176 DYNPM_ACTION_UPCLOCK, 1177 DYNPM_ACTION_DEFAULT 1178 }; 1179 1180 enum radeon_voltage_type { 1181 VOLTAGE_NONE = 0, 1182 VOLTAGE_GPIO, 1183 VOLTAGE_VDDC, 1184 VOLTAGE_SW 1185 }; 1186 1187 enum radeon_pm_state_type { 1188 /* not used for dpm */ 1189 POWER_STATE_TYPE_DEFAULT, 1190 POWER_STATE_TYPE_POWERSAVE, 1191 /* user selectable states */ 1192 POWER_STATE_TYPE_BATTERY, 1193 POWER_STATE_TYPE_BALANCED, 1194 POWER_STATE_TYPE_PERFORMANCE, 1195 /* internal states */ 1196 POWER_STATE_TYPE_INTERNAL_UVD, 1197 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1198 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1199 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1200 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1201 POWER_STATE_TYPE_INTERNAL_BOOT, 1202 POWER_STATE_TYPE_INTERNAL_THERMAL, 1203 POWER_STATE_TYPE_INTERNAL_ACPI, 1204 POWER_STATE_TYPE_INTERNAL_ULV, 1205 POWER_STATE_TYPE_INTERNAL_3DPERF, 1206 }; 1207 1208 enum radeon_pm_profile_type { 1209 PM_PROFILE_DEFAULT, 1210 PM_PROFILE_AUTO, 1211 PM_PROFILE_LOW, 1212 PM_PROFILE_MID, 1213 PM_PROFILE_HIGH, 1214 }; 1215 1216 #define PM_PROFILE_DEFAULT_IDX 0 1217 #define PM_PROFILE_LOW_SH_IDX 1 1218 #define PM_PROFILE_MID_SH_IDX 2 1219 #define PM_PROFILE_HIGH_SH_IDX 3 1220 #define PM_PROFILE_LOW_MH_IDX 4 1221 #define PM_PROFILE_MID_MH_IDX 5 1222 #define PM_PROFILE_HIGH_MH_IDX 6 1223 #define PM_PROFILE_MAX 7 1224 1225 struct radeon_pm_profile { 1226 int dpms_off_ps_idx; 1227 int dpms_on_ps_idx; 1228 int dpms_off_cm_idx; 1229 int dpms_on_cm_idx; 1230 }; 1231 1232 enum radeon_int_thermal_type { 1233 THERMAL_TYPE_NONE, 1234 THERMAL_TYPE_EXTERNAL, 1235 THERMAL_TYPE_EXTERNAL_GPIO, 1236 THERMAL_TYPE_RV6XX, 1237 THERMAL_TYPE_RV770, 1238 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1239 THERMAL_TYPE_EVERGREEN, 1240 THERMAL_TYPE_SUMO, 1241 THERMAL_TYPE_NI, 1242 THERMAL_TYPE_SI, 1243 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1244 THERMAL_TYPE_CI, 1245 THERMAL_TYPE_KV, 1246 }; 1247 1248 struct radeon_voltage { 1249 enum radeon_voltage_type type; 1250 /* gpio voltage */ 1251 struct radeon_gpio_rec gpio; 1252 u32 delay; /* delay in usec from voltage drop to sclk change */ 1253 bool active_high; /* voltage drop is active when bit is high */ 1254 /* VDDC voltage */ 1255 u8 vddc_id; /* index into vddc voltage table */ 1256 u8 vddci_id; /* index into vddci voltage table */ 1257 bool vddci_enabled; 1258 /* r6xx+ sw */ 1259 u16 voltage; 1260 /* evergreen+ vddci */ 1261 u16 vddci; 1262 }; 1263 1264 /* clock mode flags */ 1265 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1266 1267 struct radeon_pm_clock_info { 1268 /* memory clock */ 1269 u32 mclk; 1270 /* engine clock */ 1271 u32 sclk; 1272 /* voltage info */ 1273 struct radeon_voltage voltage; 1274 /* standardized clock flags */ 1275 u32 flags; 1276 }; 1277 1278 /* state flags */ 1279 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1280 1281 struct radeon_power_state { 1282 enum radeon_pm_state_type type; 1283 struct radeon_pm_clock_info *clock_info; 1284 /* number of valid clock modes in this power state */ 1285 int num_clock_modes; 1286 struct radeon_pm_clock_info *default_clock_mode; 1287 /* standardized state flags */ 1288 u32 flags; 1289 u32 misc; /* vbios specific flags */ 1290 u32 misc2; /* vbios specific flags */ 1291 int pcie_lanes; /* pcie lanes */ 1292 }; 1293 1294 /* 1295 * Some modes are overclocked by very low value, accept them 1296 */ 1297 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1298 1299 enum radeon_dpm_auto_throttle_src { 1300 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1301 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1302 }; 1303 1304 enum radeon_dpm_event_src { 1305 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1306 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1307 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1308 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1309 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1310 }; 1311 1312 #define RADEON_MAX_VCE_LEVELS 6 1313 1314 enum radeon_vce_level { 1315 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1316 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1317 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1318 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1319 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1320 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1321 }; 1322 1323 struct radeon_ps { 1324 u32 caps; /* vbios flags */ 1325 u32 class; /* vbios flags */ 1326 u32 class2; /* vbios flags */ 1327 /* UVD clocks */ 1328 u32 vclk; 1329 u32 dclk; 1330 /* VCE clocks */ 1331 u32 evclk; 1332 u32 ecclk; 1333 bool vce_active; 1334 enum radeon_vce_level vce_level; 1335 /* asic priv */ 1336 void *ps_priv; 1337 }; 1338 1339 struct radeon_dpm_thermal { 1340 /* thermal interrupt work */ 1341 struct task work; 1342 /* low temperature threshold */ 1343 int min_temp; 1344 /* high temperature threshold */ 1345 int max_temp; 1346 /* was interrupt low to high or high to low */ 1347 bool high_to_low; 1348 }; 1349 1350 enum radeon_clk_action 1351 { 1352 RADEON_SCLK_UP = 1, 1353 RADEON_SCLK_DOWN 1354 }; 1355 1356 struct radeon_blacklist_clocks 1357 { 1358 u32 sclk; 1359 u32 mclk; 1360 enum radeon_clk_action action; 1361 }; 1362 1363 struct radeon_clock_and_voltage_limits { 1364 u32 sclk; 1365 u32 mclk; 1366 u16 vddc; 1367 u16 vddci; 1368 }; 1369 1370 struct radeon_clock_array { 1371 u32 count; 1372 u32 *values; 1373 }; 1374 1375 struct radeon_clock_voltage_dependency_entry { 1376 u32 clk; 1377 u16 v; 1378 }; 1379 1380 struct radeon_clock_voltage_dependency_table { 1381 u32 count; 1382 struct radeon_clock_voltage_dependency_entry *entries; 1383 }; 1384 1385 union radeon_cac_leakage_entry { 1386 struct { 1387 u16 vddc; 1388 u32 leakage; 1389 }; 1390 struct { 1391 u16 vddc1; 1392 u16 vddc2; 1393 u16 vddc3; 1394 }; 1395 }; 1396 1397 struct radeon_cac_leakage_table { 1398 u32 count; 1399 union radeon_cac_leakage_entry *entries; 1400 }; 1401 1402 struct radeon_phase_shedding_limits_entry { 1403 u16 voltage; 1404 u32 sclk; 1405 u32 mclk; 1406 }; 1407 1408 struct radeon_phase_shedding_limits_table { 1409 u32 count; 1410 struct radeon_phase_shedding_limits_entry *entries; 1411 }; 1412 1413 struct radeon_uvd_clock_voltage_dependency_entry { 1414 u32 vclk; 1415 u32 dclk; 1416 u16 v; 1417 }; 1418 1419 struct radeon_uvd_clock_voltage_dependency_table { 1420 u8 count; 1421 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1422 }; 1423 1424 struct radeon_vce_clock_voltage_dependency_entry { 1425 u32 ecclk; 1426 u32 evclk; 1427 u16 v; 1428 }; 1429 1430 struct radeon_vce_clock_voltage_dependency_table { 1431 u8 count; 1432 struct radeon_vce_clock_voltage_dependency_entry *entries; 1433 }; 1434 1435 struct radeon_ppm_table { 1436 u8 ppm_design; 1437 u16 cpu_core_number; 1438 u32 platform_tdp; 1439 u32 small_ac_platform_tdp; 1440 u32 platform_tdc; 1441 u32 small_ac_platform_tdc; 1442 u32 apu_tdp; 1443 u32 dgpu_tdp; 1444 u32 dgpu_ulv_power; 1445 u32 tj_max; 1446 }; 1447 1448 struct radeon_cac_tdp_table { 1449 u16 tdp; 1450 u16 configurable_tdp; 1451 u16 tdc; 1452 u16 battery_power_limit; 1453 u16 small_power_limit; 1454 u16 low_cac_leakage; 1455 u16 high_cac_leakage; 1456 u16 maximum_power_delivery_limit; 1457 }; 1458 1459 struct radeon_dpm_dynamic_state { 1460 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1461 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1462 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1463 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1464 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1465 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1466 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1467 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1468 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1469 struct radeon_clock_array valid_sclk_values; 1470 struct radeon_clock_array valid_mclk_values; 1471 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1472 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1473 u32 mclk_sclk_ratio; 1474 u32 sclk_mclk_delta; 1475 u16 vddc_vddci_delta; 1476 u16 min_vddc_for_pcie_gen2; 1477 struct radeon_cac_leakage_table cac_leakage_table; 1478 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1479 struct radeon_ppm_table *ppm_table; 1480 struct radeon_cac_tdp_table *cac_tdp_table; 1481 }; 1482 1483 struct radeon_dpm_fan { 1484 u16 t_min; 1485 u16 t_med; 1486 u16 t_high; 1487 u16 pwm_min; 1488 u16 pwm_med; 1489 u16 pwm_high; 1490 u8 t_hyst; 1491 u32 cycle_delay; 1492 u16 t_max; 1493 bool ucode_fan_control; 1494 }; 1495 1496 enum radeon_pcie_gen { 1497 RADEON_PCIE_GEN1 = 0, 1498 RADEON_PCIE_GEN2 = 1, 1499 RADEON_PCIE_GEN3 = 2, 1500 RADEON_PCIE_GEN_INVALID = 0xffff 1501 }; 1502 1503 enum radeon_dpm_forced_level { 1504 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1505 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1506 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1507 }; 1508 1509 struct radeon_vce_state { 1510 /* vce clocks */ 1511 u32 evclk; 1512 u32 ecclk; 1513 /* gpu clocks */ 1514 u32 sclk; 1515 u32 mclk; 1516 u8 clk_idx; 1517 u8 pstate; 1518 }; 1519 1520 struct radeon_dpm { 1521 struct radeon_ps *ps; 1522 /* number of valid power states */ 1523 int num_ps; 1524 /* current power state that is active */ 1525 struct radeon_ps *current_ps; 1526 /* requested power state */ 1527 struct radeon_ps *requested_ps; 1528 /* boot up power state */ 1529 struct radeon_ps *boot_ps; 1530 /* default uvd power state */ 1531 struct radeon_ps *uvd_ps; 1532 /* vce requirements */ 1533 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1534 enum radeon_vce_level vce_level; 1535 enum radeon_pm_state_type state; 1536 enum radeon_pm_state_type user_state; 1537 u32 platform_caps; 1538 u32 voltage_response_time; 1539 u32 backbias_response_time; 1540 void *priv; 1541 u32 new_active_crtcs; 1542 int new_active_crtc_count; 1543 u32 current_active_crtcs; 1544 int current_active_crtc_count; 1545 struct radeon_dpm_dynamic_state dyn_state; 1546 struct radeon_dpm_fan fan; 1547 u32 tdp_limit; 1548 u32 near_tdp_limit; 1549 u32 near_tdp_limit_adjusted; 1550 u32 sq_ramping_threshold; 1551 u32 cac_leakage; 1552 u16 tdp_od_limit; 1553 u32 tdp_adjustment; 1554 u16 load_line_slope; 1555 bool power_control; 1556 bool ac_power; 1557 /* special states active */ 1558 bool thermal_active; 1559 bool uvd_active; 1560 bool vce_active; 1561 /* thermal handling */ 1562 struct radeon_dpm_thermal thermal; 1563 /* forced levels */ 1564 enum radeon_dpm_forced_level forced_level; 1565 /* track UVD streams */ 1566 unsigned sd; 1567 unsigned hd; 1568 }; 1569 1570 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1571 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1572 1573 struct radeon_pm { 1574 struct lock mutex; 1575 /* write locked while reprogramming mclk */ 1576 struct lock mclk_lock; 1577 u32 active_crtcs; 1578 int active_crtc_count; 1579 int req_vblank; 1580 bool vblank_sync; 1581 fixed20_12 max_bandwidth; 1582 fixed20_12 igp_sideport_mclk; 1583 fixed20_12 igp_system_mclk; 1584 fixed20_12 igp_ht_link_clk; 1585 fixed20_12 igp_ht_link_width; 1586 fixed20_12 k8_bandwidth; 1587 fixed20_12 sideport_bandwidth; 1588 fixed20_12 ht_bandwidth; 1589 fixed20_12 core_bandwidth; 1590 fixed20_12 sclk; 1591 fixed20_12 mclk; 1592 fixed20_12 needed_bandwidth; 1593 struct radeon_power_state *power_state; 1594 /* number of valid power states */ 1595 int num_power_states; 1596 int current_power_state_index; 1597 int current_clock_mode_index; 1598 int requested_power_state_index; 1599 int requested_clock_mode_index; 1600 int default_power_state_index; 1601 u32 current_sclk; 1602 u32 current_mclk; 1603 u16 current_vddc; 1604 u16 current_vddci; 1605 u32 default_sclk; 1606 u32 default_mclk; 1607 u16 default_vddc; 1608 u16 default_vddci; 1609 struct radeon_i2c_chan *i2c_bus; 1610 /* selected pm method */ 1611 enum radeon_pm_method pm_method; 1612 /* dynpm power management */ 1613 #ifdef DUMBBELL_WIP 1614 struct delayed_work dynpm_idle_work; 1615 #endif /* DUMBBELL_WIP */ 1616 enum radeon_dynpm_state dynpm_state; 1617 enum radeon_dynpm_action dynpm_planned_action; 1618 unsigned long dynpm_action_timeout; 1619 bool dynpm_can_upclock; 1620 bool dynpm_can_downclock; 1621 /* profile-based power management */ 1622 enum radeon_pm_profile_type profile; 1623 int profile_index; 1624 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1625 /* internal thermal controller on rv6xx+ */ 1626 enum radeon_int_thermal_type int_thermal_type; 1627 struct ksensor *int_sensor; 1628 struct ksensordev *int_sensordev; 1629 /* dpm */ 1630 bool dpm_enabled; 1631 struct radeon_dpm dpm; 1632 }; 1633 1634 int radeon_pm_get_type_index(struct radeon_device *rdev, 1635 enum radeon_pm_state_type ps_type, 1636 int instance); 1637 /* 1638 * UVD 1639 */ 1640 #define RADEON_MAX_UVD_HANDLES 10 1641 #define RADEON_UVD_STACK_SIZE (1024*1024) 1642 #define RADEON_UVD_HEAP_SIZE (1024*1024) 1643 1644 struct radeon_uvd { 1645 struct radeon_bo *vcpu_bo; 1646 void *cpu_addr; 1647 uint64_t gpu_addr; 1648 void *saved_bo; 1649 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1650 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1651 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1652 struct delayed_work idle_work; 1653 }; 1654 1655 int radeon_uvd_init(struct radeon_device *rdev); 1656 void radeon_uvd_fini(struct radeon_device *rdev); 1657 int radeon_uvd_suspend(struct radeon_device *rdev); 1658 int radeon_uvd_resume(struct radeon_device *rdev); 1659 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1660 uint32_t handle, struct radeon_fence **fence); 1661 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1662 uint32_t handle, struct radeon_fence **fence); 1663 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, 1664 uint32_t allowed_domains); 1665 void radeon_uvd_free_handles(struct radeon_device *rdev, 1666 struct drm_file *filp); 1667 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1668 void radeon_uvd_note_usage(struct radeon_device *rdev); 1669 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1670 unsigned vclk, unsigned dclk, 1671 unsigned vco_min, unsigned vco_max, 1672 unsigned fb_factor, unsigned fb_mask, 1673 unsigned pd_min, unsigned pd_max, 1674 unsigned pd_even, 1675 unsigned *optimal_fb_div, 1676 unsigned *optimal_vclk_div, 1677 unsigned *optimal_dclk_div); 1678 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1679 unsigned cg_upll_func_cntl); 1680 1681 /* 1682 * VCE 1683 */ 1684 #define RADEON_MAX_VCE_HANDLES 16 1685 #define RADEON_VCE_STACK_SIZE (1024*1024) 1686 #define RADEON_VCE_HEAP_SIZE (4*1024*1024) 1687 1688 struct radeon_vce { 1689 struct radeon_bo *vcpu_bo; 1690 uint64_t gpu_addr; 1691 unsigned fw_version; 1692 unsigned fb_version; 1693 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1694 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1695 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1696 struct delayed_work idle_work; 1697 }; 1698 1699 int radeon_vce_init(struct radeon_device *rdev); 1700 void radeon_vce_fini(struct radeon_device *rdev); 1701 int radeon_vce_suspend(struct radeon_device *rdev); 1702 int radeon_vce_resume(struct radeon_device *rdev); 1703 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1704 uint32_t handle, struct radeon_fence **fence); 1705 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1706 uint32_t handle, struct radeon_fence **fence); 1707 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1708 void radeon_vce_note_usage(struct radeon_device *rdev); 1709 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1710 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1711 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1712 struct radeon_ring *ring, 1713 struct radeon_semaphore *semaphore, 1714 bool emit_wait); 1715 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1716 void radeon_vce_fence_emit(struct radeon_device *rdev, 1717 struct radeon_fence *fence); 1718 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1719 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1720 1721 struct r600_audio_pin { 1722 int channels; 1723 int rate; 1724 int bits_per_sample; 1725 u8 status_bits; 1726 u8 category_code; 1727 u32 offset; 1728 bool connected; 1729 u32 id; 1730 }; 1731 1732 struct r600_audio { 1733 bool enabled; 1734 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1735 int num_pins; 1736 }; 1737 1738 /* 1739 * Benchmarking 1740 */ 1741 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1742 1743 1744 /* 1745 * Testing 1746 */ 1747 void radeon_test_moves(struct radeon_device *rdev); 1748 void radeon_test_ring_sync(struct radeon_device *rdev, 1749 struct radeon_ring *cpA, 1750 struct radeon_ring *cpB); 1751 void radeon_test_syncing(struct radeon_device *rdev); 1752 1753 1754 /* 1755 * Debugfs 1756 */ 1757 struct radeon_debugfs { 1758 struct drm_info_list *files; 1759 unsigned num_files; 1760 }; 1761 1762 int radeon_debugfs_add_files(struct radeon_device *rdev, 1763 struct drm_info_list *files, 1764 unsigned nfiles); 1765 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1766 1767 /* 1768 * ASIC ring specific functions. 1769 */ 1770 struct radeon_asic_ring { 1771 /* ring read/write ptr handling */ 1772 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1773 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1774 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1775 1776 /* validating and patching of IBs */ 1777 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1778 int (*cs_parse)(struct radeon_cs_parser *p); 1779 1780 /* command emmit functions */ 1781 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1782 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1783 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); 1784 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1785 struct radeon_semaphore *semaphore, bool emit_wait); 1786 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 1787 1788 /* testing functions */ 1789 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1790 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1791 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1792 1793 /* deprecated */ 1794 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1795 }; 1796 1797 /* 1798 * ASIC specific functions. 1799 */ 1800 struct radeon_asic { 1801 int (*init)(struct radeon_device *rdev); 1802 void (*fini)(struct radeon_device *rdev); 1803 int (*resume)(struct radeon_device *rdev); 1804 int (*suspend)(struct radeon_device *rdev); 1805 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1806 int (*asic_reset)(struct radeon_device *rdev); 1807 /* Flush the HDP cache via MMIO */ 1808 void (*mmio_hdp_flush)(struct radeon_device *rdev); 1809 /* check if 3D engine is idle */ 1810 bool (*gui_idle)(struct radeon_device *rdev); 1811 /* wait for mc_idle */ 1812 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1813 /* get the reference clock */ 1814 u32 (*get_xclk)(struct radeon_device *rdev); 1815 /* get the gpu clock counter */ 1816 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1817 /* gart */ 1818 struct { 1819 void (*tlb_flush)(struct radeon_device *rdev); 1820 void (*set_page)(struct radeon_device *rdev, unsigned i, 1821 uint64_t addr, uint32_t flags); 1822 } gart; 1823 struct { 1824 int (*init)(struct radeon_device *rdev); 1825 void (*fini)(struct radeon_device *rdev); 1826 void (*copy_pages)(struct radeon_device *rdev, 1827 struct radeon_ib *ib, 1828 uint64_t pe, uint64_t src, 1829 unsigned count); 1830 void (*write_pages)(struct radeon_device *rdev, 1831 struct radeon_ib *ib, 1832 uint64_t pe, 1833 uint64_t addr, unsigned count, 1834 uint32_t incr, uint32_t flags); 1835 void (*set_pages)(struct radeon_device *rdev, 1836 struct radeon_ib *ib, 1837 uint64_t pe, 1838 uint64_t addr, unsigned count, 1839 uint32_t incr, uint32_t flags); 1840 void (*pad_ib)(struct radeon_ib *ib); 1841 } vm; 1842 /* ring specific callbacks */ 1843 struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1844 /* irqs */ 1845 struct { 1846 int (*set)(struct radeon_device *rdev); 1847 irqreturn_t (*process)(struct radeon_device *rdev); 1848 } irq; 1849 /* displays */ 1850 struct { 1851 /* display watermarks */ 1852 void (*bandwidth_update)(struct radeon_device *rdev); 1853 /* get frame count */ 1854 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1855 /* wait for vblank */ 1856 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1857 /* set backlight level */ 1858 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1859 /* get backlight level */ 1860 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1861 /* audio callbacks */ 1862 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1863 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1864 } display; 1865 /* copy functions for bo handling */ 1866 struct { 1867 int (*blit)(struct radeon_device *rdev, 1868 uint64_t src_offset, 1869 uint64_t dst_offset, 1870 unsigned num_gpu_pages, 1871 struct radeon_fence **fence); 1872 u32 blit_ring_index; 1873 int (*dma)(struct radeon_device *rdev, 1874 uint64_t src_offset, 1875 uint64_t dst_offset, 1876 unsigned num_gpu_pages, 1877 struct radeon_fence **fence); 1878 u32 dma_ring_index; 1879 /* method used for bo copy */ 1880 int (*copy)(struct radeon_device *rdev, 1881 uint64_t src_offset, 1882 uint64_t dst_offset, 1883 unsigned num_gpu_pages, 1884 struct radeon_fence **fence); 1885 /* ring used for bo copies */ 1886 u32 copy_ring_index; 1887 } copy; 1888 /* surfaces */ 1889 struct { 1890 int (*set_reg)(struct radeon_device *rdev, int reg, 1891 uint32_t tiling_flags, uint32_t pitch, 1892 uint32_t offset, uint32_t obj_size); 1893 void (*clear_reg)(struct radeon_device *rdev, int reg); 1894 } surface; 1895 /* hotplug detect */ 1896 struct { 1897 void (*init)(struct radeon_device *rdev); 1898 void (*fini)(struct radeon_device *rdev); 1899 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1900 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1901 } hpd; 1902 /* static power management */ 1903 struct { 1904 void (*misc)(struct radeon_device *rdev); 1905 void (*prepare)(struct radeon_device *rdev); 1906 void (*finish)(struct radeon_device *rdev); 1907 void (*init_profile)(struct radeon_device *rdev); 1908 void (*get_dynpm_state)(struct radeon_device *rdev); 1909 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1910 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1911 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1912 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1913 int (*get_pcie_lanes)(struct radeon_device *rdev); 1914 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1915 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1916 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 1917 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 1918 int (*get_temperature)(struct radeon_device *rdev); 1919 } pm; 1920 /* dynamic power management */ 1921 struct { 1922 int (*init)(struct radeon_device *rdev); 1923 void (*setup_asic)(struct radeon_device *rdev); 1924 int (*enable)(struct radeon_device *rdev); 1925 int (*late_enable)(struct radeon_device *rdev); 1926 void (*disable)(struct radeon_device *rdev); 1927 int (*pre_set_power_state)(struct radeon_device *rdev); 1928 int (*set_power_state)(struct radeon_device *rdev); 1929 void (*post_set_power_state)(struct radeon_device *rdev); 1930 void (*display_configuration_changed)(struct radeon_device *rdev); 1931 void (*fini)(struct radeon_device *rdev); 1932 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 1933 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 1934 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 1935 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 1936 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 1937 bool (*vblank_too_short)(struct radeon_device *rdev); 1938 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 1939 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 1940 } dpm; 1941 /* pageflipping */ 1942 struct { 1943 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 1944 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); 1945 } pflip; 1946 }; 1947 1948 /* 1949 * Asic structures 1950 */ 1951 struct r100_asic { 1952 const unsigned *reg_safe_bm; 1953 unsigned reg_safe_bm_size; 1954 u32 hdp_cntl; 1955 }; 1956 1957 struct r300_asic { 1958 const unsigned *reg_safe_bm; 1959 unsigned reg_safe_bm_size; 1960 u32 resync_scratch; 1961 u32 hdp_cntl; 1962 }; 1963 1964 struct r600_asic { 1965 unsigned max_pipes; 1966 unsigned max_tile_pipes; 1967 unsigned max_simds; 1968 unsigned max_backends; 1969 unsigned max_gprs; 1970 unsigned max_threads; 1971 unsigned max_stack_entries; 1972 unsigned max_hw_contexts; 1973 unsigned max_gs_threads; 1974 unsigned sx_max_export_size; 1975 unsigned sx_max_export_pos_size; 1976 unsigned sx_max_export_smx_size; 1977 unsigned sq_num_cf_insts; 1978 unsigned tiling_nbanks; 1979 unsigned tiling_npipes; 1980 unsigned tiling_group_size; 1981 unsigned tile_config; 1982 unsigned backend_map; 1983 unsigned active_simds; 1984 }; 1985 1986 struct rv770_asic { 1987 unsigned max_pipes; 1988 unsigned max_tile_pipes; 1989 unsigned max_simds; 1990 unsigned max_backends; 1991 unsigned max_gprs; 1992 unsigned max_threads; 1993 unsigned max_stack_entries; 1994 unsigned max_hw_contexts; 1995 unsigned max_gs_threads; 1996 unsigned sx_max_export_size; 1997 unsigned sx_max_export_pos_size; 1998 unsigned sx_max_export_smx_size; 1999 unsigned sq_num_cf_insts; 2000 unsigned sx_num_of_sets; 2001 unsigned sc_prim_fifo_size; 2002 unsigned sc_hiz_tile_fifo_size; 2003 unsigned sc_earlyz_tile_fifo_fize; 2004 unsigned tiling_nbanks; 2005 unsigned tiling_npipes; 2006 unsigned tiling_group_size; 2007 unsigned tile_config; 2008 unsigned backend_map; 2009 unsigned active_simds; 2010 }; 2011 2012 struct evergreen_asic { 2013 unsigned num_ses; 2014 unsigned max_pipes; 2015 unsigned max_tile_pipes; 2016 unsigned max_simds; 2017 unsigned max_backends; 2018 unsigned max_gprs; 2019 unsigned max_threads; 2020 unsigned max_stack_entries; 2021 unsigned max_hw_contexts; 2022 unsigned max_gs_threads; 2023 unsigned sx_max_export_size; 2024 unsigned sx_max_export_pos_size; 2025 unsigned sx_max_export_smx_size; 2026 unsigned sq_num_cf_insts; 2027 unsigned sx_num_of_sets; 2028 unsigned sc_prim_fifo_size; 2029 unsigned sc_hiz_tile_fifo_size; 2030 unsigned sc_earlyz_tile_fifo_size; 2031 unsigned tiling_nbanks; 2032 unsigned tiling_npipes; 2033 unsigned tiling_group_size; 2034 unsigned tile_config; 2035 unsigned backend_map; 2036 unsigned active_simds; 2037 }; 2038 2039 struct cayman_asic { 2040 unsigned max_shader_engines; 2041 unsigned max_pipes_per_simd; 2042 unsigned max_tile_pipes; 2043 unsigned max_simds_per_se; 2044 unsigned max_backends_per_se; 2045 unsigned max_texture_channel_caches; 2046 unsigned max_gprs; 2047 unsigned max_threads; 2048 unsigned max_gs_threads; 2049 unsigned max_stack_entries; 2050 unsigned sx_num_of_sets; 2051 unsigned sx_max_export_size; 2052 unsigned sx_max_export_pos_size; 2053 unsigned sx_max_export_smx_size; 2054 unsigned max_hw_contexts; 2055 unsigned sq_num_cf_insts; 2056 unsigned sc_prim_fifo_size; 2057 unsigned sc_hiz_tile_fifo_size; 2058 unsigned sc_earlyz_tile_fifo_size; 2059 2060 unsigned num_shader_engines; 2061 unsigned num_shader_pipes_per_simd; 2062 unsigned num_tile_pipes; 2063 unsigned num_simds_per_se; 2064 unsigned num_backends_per_se; 2065 unsigned backend_disable_mask_per_asic; 2066 unsigned backend_map; 2067 unsigned num_texture_channel_caches; 2068 unsigned mem_max_burst_length_bytes; 2069 unsigned mem_row_size_in_kb; 2070 unsigned shader_engine_tile_size; 2071 unsigned num_gpus; 2072 unsigned multi_gpu_tile_size; 2073 2074 unsigned tile_config; 2075 unsigned active_simds; 2076 }; 2077 2078 struct si_asic { 2079 unsigned max_shader_engines; 2080 unsigned max_tile_pipes; 2081 unsigned max_cu_per_sh; 2082 unsigned max_sh_per_se; 2083 unsigned max_backends_per_se; 2084 unsigned max_texture_channel_caches; 2085 unsigned max_gprs; 2086 unsigned max_gs_threads; 2087 unsigned max_hw_contexts; 2088 unsigned sc_prim_fifo_size_frontend; 2089 unsigned sc_prim_fifo_size_backend; 2090 unsigned sc_hiz_tile_fifo_size; 2091 unsigned sc_earlyz_tile_fifo_size; 2092 2093 unsigned num_tile_pipes; 2094 unsigned backend_enable_mask; 2095 unsigned backend_disable_mask_per_asic; 2096 unsigned backend_map; 2097 unsigned num_texture_channel_caches; 2098 unsigned mem_max_burst_length_bytes; 2099 unsigned mem_row_size_in_kb; 2100 unsigned shader_engine_tile_size; 2101 unsigned num_gpus; 2102 unsigned multi_gpu_tile_size; 2103 2104 unsigned tile_config; 2105 uint32_t tile_mode_array[32]; 2106 uint32_t active_cus; 2107 }; 2108 2109 struct cik_asic { 2110 unsigned max_shader_engines; 2111 unsigned max_tile_pipes; 2112 unsigned max_cu_per_sh; 2113 unsigned max_sh_per_se; 2114 unsigned max_backends_per_se; 2115 unsigned max_texture_channel_caches; 2116 unsigned max_gprs; 2117 unsigned max_gs_threads; 2118 unsigned max_hw_contexts; 2119 unsigned sc_prim_fifo_size_frontend; 2120 unsigned sc_prim_fifo_size_backend; 2121 unsigned sc_hiz_tile_fifo_size; 2122 unsigned sc_earlyz_tile_fifo_size; 2123 2124 unsigned num_tile_pipes; 2125 unsigned backend_enable_mask; 2126 unsigned backend_disable_mask_per_asic; 2127 unsigned backend_map; 2128 unsigned num_texture_channel_caches; 2129 unsigned mem_max_burst_length_bytes; 2130 unsigned mem_row_size_in_kb; 2131 unsigned shader_engine_tile_size; 2132 unsigned num_gpus; 2133 unsigned multi_gpu_tile_size; 2134 2135 unsigned tile_config; 2136 uint32_t tile_mode_array[32]; 2137 uint32_t macrotile_mode_array[16]; 2138 uint32_t active_cus; 2139 }; 2140 2141 union radeon_asic_config { 2142 struct r300_asic r300; 2143 struct r100_asic r100; 2144 struct r600_asic r600; 2145 struct rv770_asic rv770; 2146 struct evergreen_asic evergreen; 2147 struct cayman_asic cayman; 2148 struct si_asic si; 2149 struct cik_asic cik; 2150 }; 2151 2152 /* 2153 * asic initizalization from radeon_asic.c 2154 */ 2155 int radeon_asic_init(struct radeon_device *rdev); 2156 2157 2158 /* 2159 * IOCTL. 2160 */ 2161 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2162 struct drm_file *filp); 2163 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2164 struct drm_file *filp); 2165 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2166 struct drm_file *file_priv); 2167 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2168 struct drm_file *file_priv); 2169 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2170 struct drm_file *file_priv); 2171 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 2172 struct drm_file *file_priv); 2173 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2174 struct drm_file *filp); 2175 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2176 struct drm_file *filp); 2177 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2178 struct drm_file *filp); 2179 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2180 struct drm_file *filp); 2181 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2182 struct drm_file *filp); 2183 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2184 struct drm_file *filp); 2185 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2186 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2187 struct drm_file *filp); 2188 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2189 struct drm_file *filp); 2190 2191 /* VRAM scratch page for HDP bug, default vram page */ 2192 struct r600_vram_scratch { 2193 struct radeon_bo *robj; 2194 volatile uint32_t *ptr; 2195 u64 gpu_addr; 2196 }; 2197 2198 /* 2199 * ACPI 2200 */ 2201 struct radeon_atif_notification_cfg { 2202 bool enabled; 2203 int command_code; 2204 }; 2205 2206 struct radeon_atif_notifications { 2207 bool display_switch; 2208 bool expansion_mode_change; 2209 bool thermal_state; 2210 bool forced_power_state; 2211 bool system_power_state; 2212 bool display_conf_change; 2213 bool px_gfx_switch; 2214 bool brightness_change; 2215 bool dgpu_display_event; 2216 }; 2217 2218 struct radeon_atif_functions { 2219 bool system_params; 2220 bool sbios_requests; 2221 bool select_active_disp; 2222 bool lid_state; 2223 bool get_tv_standard; 2224 bool set_tv_standard; 2225 bool get_panel_expansion_mode; 2226 bool set_panel_expansion_mode; 2227 bool temperature_change; 2228 bool graphics_device_types; 2229 }; 2230 2231 struct radeon_atif { 2232 struct radeon_atif_notifications notifications; 2233 struct radeon_atif_functions functions; 2234 struct radeon_atif_notification_cfg notification_cfg; 2235 struct radeon_encoder *encoder_for_bl; 2236 }; 2237 2238 struct radeon_atcs_functions { 2239 bool get_ext_state; 2240 bool pcie_perf_req; 2241 bool pcie_dev_rdy; 2242 bool pcie_bus_width; 2243 }; 2244 2245 struct radeon_atcs { 2246 struct radeon_atcs_functions functions; 2247 }; 2248 2249 /* 2250 * Core structure, functions and helpers. 2251 */ 2252 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2253 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2254 2255 struct radeon_device { 2256 struct device *dev; 2257 struct drm_device *ddev; 2258 struct pci_dev *pdev; 2259 struct lock exclusive_lock; 2260 /* ASIC */ 2261 union radeon_asic_config config; 2262 enum radeon_family family; 2263 unsigned long flags; 2264 int usec_timeout; 2265 enum radeon_pll_errata pll_errata; 2266 int num_gb_pipes; 2267 int num_z_pipes; 2268 int disp_priority; 2269 /* BIOS */ 2270 uint8_t *bios; 2271 bool is_atom_bios; 2272 uint16_t bios_header_start; 2273 struct radeon_bo *stollen_vga_memory; 2274 /* Register mmio */ 2275 resource_size_t rmmio_base; 2276 resource_size_t rmmio_size; 2277 /* protects concurrent MM_INDEX/DATA based register access */ 2278 struct spinlock mmio_idx_lock; 2279 /* protects concurrent SMC based register access */ 2280 struct spinlock smc_idx_lock; 2281 /* protects concurrent PLL register access */ 2282 struct spinlock pll_idx_lock; 2283 /* protects concurrent MC register access */ 2284 struct spinlock mc_idx_lock; 2285 /* protects concurrent PCIE register access */ 2286 struct spinlock pcie_idx_lock; 2287 /* protects concurrent PCIE_PORT register access */ 2288 struct spinlock pciep_idx_lock; 2289 /* protects concurrent PIF register access */ 2290 struct spinlock pif_idx_lock; 2291 /* protects concurrent CG register access */ 2292 struct spinlock cg_idx_lock; 2293 /* protects concurrent UVD register access */ 2294 struct spinlock uvd_idx_lock; 2295 /* protects concurrent RCU register access */ 2296 struct spinlock rcu_idx_lock; 2297 /* protects concurrent DIDT register access */ 2298 struct spinlock didt_idx_lock; 2299 /* protects concurrent ENDPOINT (audio) register access */ 2300 struct spinlock end_idx_lock; 2301 int rmmio_rid; 2302 struct resource *rmmio; 2303 radeon_rreg_t mc_rreg; 2304 radeon_wreg_t mc_wreg; 2305 radeon_rreg_t pll_rreg; 2306 radeon_wreg_t pll_wreg; 2307 uint32_t pcie_reg_mask; 2308 radeon_rreg_t pciep_rreg; 2309 radeon_wreg_t pciep_wreg; 2310 /* io port */ 2311 int rio_rid; 2312 struct resource *rio_mem; 2313 resource_size_t rio_mem_size; 2314 struct radeon_clock clock; 2315 struct radeon_mc mc; 2316 struct radeon_gart gart; 2317 struct radeon_mode_info mode_info; 2318 struct radeon_scratch scratch; 2319 struct radeon_doorbell doorbell; 2320 struct radeon_mman mman; 2321 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2322 wait_queue_head_t fence_queue; 2323 struct lock ring_lock; 2324 struct radeon_ring ring[RADEON_NUM_RINGS]; 2325 bool ib_pool_ready; 2326 struct radeon_sa_manager ring_tmp_bo; 2327 struct radeon_irq irq; 2328 struct radeon_asic *asic; 2329 struct radeon_gem gem; 2330 struct radeon_pm pm; 2331 struct radeon_uvd uvd; 2332 struct radeon_vce vce; 2333 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2334 struct radeon_wb wb; 2335 struct radeon_dummy_page dummy_page; 2336 bool shutdown; 2337 bool suspend; 2338 bool need_dma32; 2339 bool accel_working; 2340 bool fastfb_working; /* IGP feature*/ 2341 bool needs_reset, in_reset; 2342 bool fictitious_range_registered; 2343 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2344 const struct firmware *me_fw; /* all family ME firmware */ 2345 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2346 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2347 const struct firmware *mc_fw; /* NI MC firmware */ 2348 const struct firmware *ce_fw; /* SI CE firmware */ 2349 const struct firmware *mec_fw; /* CIK MEC firmware */ 2350 const struct firmware *mec2_fw; /* KV MEC2 firmware */ 2351 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2352 const struct firmware *smc_fw; /* SMC firmware */ 2353 const struct firmware *uvd_fw; /* UVD firmware */ 2354 const struct firmware *vce_fw; /* VCE firmware */ 2355 bool new_fw; 2356 struct r600_vram_scratch vram_scratch; 2357 int msi_enabled; /* msi enabled */ 2358 struct r600_ih ih; /* r6/700 interrupt ring */ 2359 struct radeon_rlc rlc; 2360 struct radeon_mec mec; 2361 struct taskqueue *tq; 2362 struct task hotplug_work; 2363 struct task audio_work; 2364 int num_crtc; /* number of crtcs */ 2365 struct lock dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2366 bool has_uvd; 2367 struct r600_audio audio; /* audio stuff */ 2368 struct { 2369 ACPI_HANDLE handle; 2370 ACPI_NOTIFY_HANDLER notifier_call; 2371 } acpi; 2372 /* only one userspace can use Hyperz features or CMASK at a time */ 2373 struct drm_file *hyperz_filp; 2374 struct drm_file *cmask_filp; 2375 /* i2c buses */ 2376 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2377 /* debugfs */ 2378 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 2379 unsigned debugfs_count; 2380 /* virtual memory */ 2381 struct radeon_vm_manager vm_manager; 2382 struct spinlock gpu_clock_mutex; 2383 /* memory stats */ 2384 atomic64_t vram_usage; 2385 atomic64_t gtt_usage; 2386 atomic64_t num_bytes_moved; 2387 /* ACPI interface */ 2388 struct radeon_atif atif; 2389 struct radeon_atcs atcs; 2390 /* srbm instance registers */ 2391 struct spinlock srbm_mutex; 2392 /* clock, powergating flags */ 2393 u32 cg_flags; 2394 u32 pg_flags; 2395 2396 #ifdef PM_TODO 2397 struct dev_pm_domain vga_pm_domain; 2398 #endif 2399 bool have_disp_power_ref; 2400 u32 px_quirk_flags; 2401 2402 /* tracking pinned memory */ 2403 u64 vram_pin_size; 2404 u64 gart_pin_size; 2405 }; 2406 2407 bool radeon_is_px(struct drm_device *dev); 2408 int radeon_device_init(struct radeon_device *rdev, 2409 struct drm_device *ddev, 2410 struct pci_dev *pdev, 2411 uint32_t flags); 2412 void radeon_device_fini(struct radeon_device *rdev); 2413 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2414 2415 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2416 bool always_indirect); 2417 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2418 bool always_indirect); 2419 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2420 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2421 2422 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2423 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2424 2425 /* 2426 * Cast helper 2427 */ 2428 #define to_radeon_fence(p) ((struct radeon_fence *)(p)) 2429 2430 /* 2431 * Registers read & write functions. 2432 */ 2433 #define RREG8(reg) bus_read_1((rdev->rmmio), (reg)) 2434 #define WREG8(reg, v) bus_write_1((rdev->rmmio), (reg), v) 2435 #define RREG16(reg) bus_read_2((rdev->rmmio), (reg)) 2436 #define WREG16(reg, v) bus_write_2((rdev->rmmio), (reg), v) 2437 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2438 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2439 #define DREG32(reg) DRM_INFO("REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) 2440 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2441 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2442 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2443 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2444 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2445 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2446 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2447 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2448 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2449 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2450 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2451 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2452 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2453 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2454 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2455 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2456 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2457 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2458 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2459 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2460 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2461 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2462 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2463 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2464 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2465 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2466 #define WREG32_P(reg, val, mask) \ 2467 do { \ 2468 uint32_t tmp_ = RREG32(reg); \ 2469 tmp_ &= (mask); \ 2470 tmp_ |= ((val) & ~(mask)); \ 2471 WREG32(reg, tmp_); \ 2472 } while (0) 2473 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2474 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2475 #define WREG32_PLL_P(reg, val, mask) \ 2476 do { \ 2477 uint32_t tmp_ = RREG32_PLL(reg); \ 2478 tmp_ &= (mask); \ 2479 tmp_ |= ((val) & ~(mask)); \ 2480 WREG32_PLL(reg, tmp_); \ 2481 } while (0) 2482 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2483 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2484 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2485 2486 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2487 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2488 2489 /* 2490 * Indirect registers accessor 2491 */ 2492 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 2493 { 2494 uint32_t r; 2495 2496 spin_lock(&rdev->pcie_idx_lock); 2497 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2498 r = RREG32(RADEON_PCIE_DATA); 2499 spin_unlock(&rdev->pcie_idx_lock); 2500 return r; 2501 } 2502 2503 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2504 { 2505 spin_lock(&rdev->pcie_idx_lock); 2506 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2507 WREG32(RADEON_PCIE_DATA, (v)); 2508 spin_unlock(&rdev->pcie_idx_lock); 2509 } 2510 2511 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) 2512 { 2513 u32 r; 2514 2515 spin_lock(&rdev->smc_idx_lock); 2516 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2517 r = RREG32(TN_SMC_IND_DATA_0); 2518 spin_unlock(&rdev->smc_idx_lock); 2519 return r; 2520 } 2521 2522 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2523 { 2524 spin_lock(&rdev->smc_idx_lock); 2525 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2526 WREG32(TN_SMC_IND_DATA_0, (v)); 2527 spin_unlock(&rdev->smc_idx_lock); 2528 } 2529 2530 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) 2531 { 2532 u32 r; 2533 2534 spin_lock(&rdev->rcu_idx_lock); 2535 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2536 r = RREG32(R600_RCU_DATA); 2537 spin_unlock(&rdev->rcu_idx_lock); 2538 return r; 2539 } 2540 2541 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2542 { 2543 spin_lock(&rdev->rcu_idx_lock); 2544 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2545 WREG32(R600_RCU_DATA, (v)); 2546 spin_unlock(&rdev->rcu_idx_lock); 2547 } 2548 2549 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) 2550 { 2551 u32 r; 2552 2553 spin_lock(&rdev->cg_idx_lock); 2554 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2555 r = RREG32(EVERGREEN_CG_IND_DATA); 2556 spin_unlock(&rdev->cg_idx_lock); 2557 return r; 2558 } 2559 2560 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2561 { 2562 spin_lock(&rdev->cg_idx_lock); 2563 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2564 WREG32(EVERGREEN_CG_IND_DATA, (v)); 2565 spin_unlock(&rdev->cg_idx_lock); 2566 } 2567 2568 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg) 2569 { 2570 u32 r; 2571 2572 spin_lock(&rdev->pif_idx_lock); 2573 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2574 r = RREG32(EVERGREEN_PIF_PHY0_DATA); 2575 spin_unlock(&rdev->pif_idx_lock); 2576 return r; 2577 } 2578 2579 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2580 { 2581 spin_lock(&rdev->pif_idx_lock); 2582 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2583 WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); 2584 spin_unlock(&rdev->pif_idx_lock); 2585 } 2586 2587 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg) 2588 { 2589 u32 r; 2590 2591 spin_lock(&rdev->pif_idx_lock); 2592 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2593 r = RREG32(EVERGREEN_PIF_PHY1_DATA); 2594 spin_unlock(&rdev->pif_idx_lock); 2595 return r; 2596 } 2597 2598 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2599 { 2600 spin_lock(&rdev->pif_idx_lock); 2601 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2602 WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); 2603 spin_unlock(&rdev->pif_idx_lock); 2604 } 2605 2606 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) 2607 { 2608 u32 r; 2609 2610 spin_lock(&rdev->uvd_idx_lock); 2611 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2612 r = RREG32(R600_UVD_CTX_DATA); 2613 spin_unlock(&rdev->uvd_idx_lock); 2614 return r; 2615 } 2616 2617 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2618 { 2619 spin_lock(&rdev->uvd_idx_lock); 2620 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2621 WREG32(R600_UVD_CTX_DATA, (v)); 2622 spin_unlock(&rdev->uvd_idx_lock); 2623 } 2624 2625 2626 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg) 2627 { 2628 u32 r; 2629 2630 spin_lock(&rdev->didt_idx_lock); 2631 WREG32(CIK_DIDT_IND_INDEX, (reg)); 2632 r = RREG32(CIK_DIDT_IND_DATA); 2633 spin_unlock(&rdev->didt_idx_lock); 2634 return r; 2635 } 2636 2637 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2638 { 2639 spin_lock(&rdev->didt_idx_lock); 2640 WREG32(CIK_DIDT_IND_INDEX, (reg)); 2641 WREG32(CIK_DIDT_IND_DATA, (v)); 2642 spin_unlock(&rdev->didt_idx_lock); 2643 } 2644 2645 void r100_pll_errata_after_index(struct radeon_device *rdev); 2646 2647 2648 /* 2649 * ASICs helpers. 2650 */ 2651 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2652 (rdev->pdev->device == 0x5969)) 2653 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2654 (rdev->family == CHIP_RV200) || \ 2655 (rdev->family == CHIP_RS100) || \ 2656 (rdev->family == CHIP_RS200) || \ 2657 (rdev->family == CHIP_RV250) || \ 2658 (rdev->family == CHIP_RV280) || \ 2659 (rdev->family == CHIP_RS300)) 2660 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2661 (rdev->family == CHIP_RV350) || \ 2662 (rdev->family == CHIP_R350) || \ 2663 (rdev->family == CHIP_RV380) || \ 2664 (rdev->family == CHIP_R420) || \ 2665 (rdev->family == CHIP_R423) || \ 2666 (rdev->family == CHIP_RV410) || \ 2667 (rdev->family == CHIP_RS400) || \ 2668 (rdev->family == CHIP_RS480)) 2669 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 2670 (rdev->ddev->pdev->device == 0x9443) || \ 2671 (rdev->ddev->pdev->device == 0x944B) || \ 2672 (rdev->ddev->pdev->device == 0x9506) || \ 2673 (rdev->ddev->pdev->device == 0x9509) || \ 2674 (rdev->ddev->pdev->device == 0x950F) || \ 2675 (rdev->ddev->pdev->device == 0x689C) || \ 2676 (rdev->ddev->pdev->device == 0x689D)) 2677 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2678 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2679 (rdev->family == CHIP_RS690) || \ 2680 (rdev->family == CHIP_RS740) || \ 2681 (rdev->family >= CHIP_R600)) 2682 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2683 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2684 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2685 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2686 (rdev->flags & RADEON_IS_IGP)) 2687 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2688 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2689 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2690 (rdev->flags & RADEON_IS_IGP)) 2691 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2692 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2693 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2694 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2695 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2696 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2697 (rdev->family == CHIP_MULLINS)) 2698 2699 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ 2700 (rdev->ddev->pdev->device == 0x6850) || \ 2701 (rdev->ddev->pdev->device == 0x6858) || \ 2702 (rdev->ddev->pdev->device == 0x6859) || \ 2703 (rdev->ddev->pdev->device == 0x6840) || \ 2704 (rdev->ddev->pdev->device == 0x6841) || \ 2705 (rdev->ddev->pdev->device == 0x6842) || \ 2706 (rdev->ddev->pdev->device == 0x6843)) 2707 2708 /* 2709 * BIOS helpers. 2710 */ 2711 #define RBIOS8(i) (rdev->bios[i]) 2712 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2713 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2714 2715 int radeon_combios_init(struct radeon_device *rdev); 2716 void radeon_combios_fini(struct radeon_device *rdev); 2717 int radeon_atombios_init(struct radeon_device *rdev); 2718 void radeon_atombios_fini(struct radeon_device *rdev); 2719 2720 2721 /* 2722 * RING helpers. 2723 */ 2724 2725 /** 2726 * radeon_ring_write - write a value to the ring 2727 * 2728 * @ring: radeon_ring structure holding ring information 2729 * @v: dword (dw) value to write 2730 * 2731 * Write a value to the requested ring buffer (all asics). 2732 */ 2733 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2734 { 2735 if (ring->count_dw <= 0) 2736 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); 2737 2738 ring->ring[ring->wptr++] = v; 2739 ring->wptr &= ring->ptr_mask; 2740 ring->count_dw--; 2741 ring->ring_free_dw--; 2742 } 2743 2744 /* 2745 * ASICs macro. 2746 */ 2747 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2748 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2749 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2750 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2751 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2752 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2753 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 2754 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2755 #define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f)) 2756 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2757 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2758 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) 2759 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2760 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2761 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) 2762 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2763 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2764 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2765 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2766 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2767 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2768 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm)) 2769 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2770 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2771 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2772 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2773 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2774 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2775 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2776 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2777 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2778 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2779 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2780 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2781 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) 2782 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) 2783 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) 2784 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2785 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2786 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2787 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2788 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2789 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2790 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2791 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2792 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2793 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2794 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2795 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2796 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2797 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2798 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2799 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2800 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2801 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2802 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2803 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2804 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2805 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2806 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2807 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2808 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2809 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2810 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) 2811 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) 2812 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2813 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2814 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2815 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2816 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2817 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2818 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2819 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2820 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2821 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2822 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2823 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2824 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2825 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2826 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2827 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2828 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2829 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2830 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2831 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2832 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2833 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2834 2835 /* Common functions */ 2836 /* AGP */ 2837 extern int radeon_gpu_reset(struct radeon_device *rdev); 2838 extern void radeon_pci_config_reset(struct radeon_device *rdev); 2839 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2840 extern void radeon_agp_disable(struct radeon_device *rdev); 2841 extern int radeon_modeset_init(struct radeon_device *rdev); 2842 extern void radeon_modeset_fini(struct radeon_device *rdev); 2843 extern bool radeon_card_posted(struct radeon_device *rdev); 2844 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2845 extern void radeon_update_display_priority(struct radeon_device *rdev); 2846 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2847 extern void radeon_scratch_init(struct radeon_device *rdev); 2848 extern void radeon_wb_fini(struct radeon_device *rdev); 2849 extern int radeon_wb_init(struct radeon_device *rdev); 2850 extern void radeon_wb_disable(struct radeon_device *rdev); 2851 extern void radeon_surface_init(struct radeon_device *rdev); 2852 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2853 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2854 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2855 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2856 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2857 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2858 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2859 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2860 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2861 const u32 *registers, 2862 const u32 array_size); 2863 2864 /* 2865 * vm 2866 */ 2867 int radeon_vm_manager_init(struct radeon_device *rdev); 2868 void radeon_vm_manager_fini(struct radeon_device *rdev); 2869 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2870 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2871 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev, 2872 struct radeon_vm *vm, 2873 struct list_head *head); 2874 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2875 struct radeon_vm *vm, int ring); 2876 void radeon_vm_flush(struct radeon_device *rdev, 2877 struct radeon_vm *vm, 2878 int ring); 2879 void radeon_vm_fence(struct radeon_device *rdev, 2880 struct radeon_vm *vm, 2881 struct radeon_fence *fence); 2882 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2883 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2884 struct radeon_vm *vm); 2885 int radeon_vm_clear_freed(struct radeon_device *rdev, 2886 struct radeon_vm *vm); 2887 int radeon_vm_clear_invalids(struct radeon_device *rdev, 2888 struct radeon_vm *vm); 2889 int radeon_vm_bo_update(struct radeon_device *rdev, 2890 struct radeon_bo_va *bo_va, 2891 struct ttm_mem_reg *mem); 2892 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2893 struct radeon_bo *bo); 2894 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2895 struct radeon_bo *bo); 2896 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2897 struct radeon_vm *vm, 2898 struct radeon_bo *bo); 2899 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2900 struct radeon_bo_va *bo_va, 2901 uint64_t offset, 2902 uint32_t flags); 2903 void radeon_vm_bo_rmv(struct radeon_device *rdev, 2904 struct radeon_bo_va *bo_va); 2905 2906 /* audio */ 2907 void r600_audio_update_hdmi(void *arg, int pending); 2908 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2909 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2910 void r600_audio_enable(struct radeon_device *rdev, 2911 struct r600_audio_pin *pin, 2912 u8 enable_mask); 2913 void dce6_audio_enable(struct radeon_device *rdev, 2914 struct r600_audio_pin *pin, 2915 u8 enable_mask); 2916 2917 /* 2918 * R600 vram scratch functions 2919 */ 2920 int r600_vram_scratch_init(struct radeon_device *rdev); 2921 void r600_vram_scratch_fini(struct radeon_device *rdev); 2922 2923 /* 2924 * r600 cs checking helper 2925 */ 2926 unsigned r600_mip_minify(unsigned size, unsigned level); 2927 bool r600_fmt_is_valid_color(u32 format); 2928 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2929 int r600_fmt_get_blocksize(u32 format); 2930 int r600_fmt_get_nblocksx(u32 format, u32 w); 2931 int r600_fmt_get_nblocksy(u32 format, u32 h); 2932 2933 /* 2934 * r600 functions used by radeon_encoder.c 2935 */ 2936 struct radeon_hdmi_acr { 2937 u32 clock; 2938 2939 int n_32khz; 2940 int cts_32khz; 2941 2942 int n_44_1khz; 2943 int cts_44_1khz; 2944 2945 int n_48khz; 2946 int cts_48khz; 2947 2948 }; 2949 2950 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 2951 2952 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 2953 u32 tiling_pipe_num, 2954 u32 max_rb_num, 2955 u32 total_max_rb_num, 2956 u32 enabled_rb_mask); 2957 2958 /* 2959 * evergreen functions used by radeon_encoder.c 2960 */ 2961 2962 extern int ni_init_microcode(struct radeon_device *rdev); 2963 extern int ni_mc_load_microcode(struct radeon_device *rdev); 2964 extern void ni_fini_microcode(struct radeon_device *rdev); 2965 2966 /* radeon_acpi.c */ 2967 extern int radeon_acpi_init(struct radeon_device *rdev); 2968 extern void radeon_acpi_fini(struct radeon_device *rdev); 2969 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 2970 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 2971 u8 perf_req, bool advertise); 2972 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 2973 2974 /* Prototypes added by @dumbbell. */ 2975 2976 /* atombios_encoders.c */ 2977 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 2978 struct drm_connector *drm_connector); 2979 void radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, 2980 uint32_t supported_device, u16 caps); 2981 2982 /* radeon_atombios.c */ 2983 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 2984 struct drm_display_mode *mode); 2985 2986 /* radeon_legacy_encoders.c */ 2987 void radeon_add_legacy_encoder(struct drm_device *dev, 2988 uint32_t encoder_enum, uint32_t supported_device); 2989 void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder, 2990 struct drm_connector *drm_connector); 2991 2992 /* radeon_pm.c */ 2993 void radeon_pm_acpi_event_handler(struct radeon_device *rdev); 2994 2995 /* radeon_ttm.c */ 2996 int radeon_ttm_init(struct radeon_device *rdev); 2997 void radeon_ttm_fini(struct radeon_device *rdev); 2998 2999 /* r600.c */ 3000 int r600_ih_ring_alloc(struct radeon_device *rdev); 3001 void r600_ih_ring_fini(struct radeon_device *rdev); 3002 3003 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 3004 struct radeon_cs_packet *pkt, 3005 unsigned idx); 3006 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 3007 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 3008 struct radeon_cs_packet *pkt); 3009 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 3010 struct radeon_cs_reloc **cs_reloc, 3011 int nomm); 3012 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 3013 uint32_t *vline_start_end, 3014 uint32_t *vline_status); 3015 3016 #include "radeon_object.h" 3017 3018 #endif 3019