1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * 28 * $FreeBSD: head/sys/dev/drm2/radeon/radeon.h 254885 2013-08-25 19:37:15Z dumbbell $ 29 */ 30 31 #ifndef __RADEON_H__ 32 #define __RADEON_H__ 33 34 /* TODO: Here are things that needs to be done : 35 * - surface allocator & initializer : (bit like scratch reg) should 36 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 37 * related to surface 38 * - WB : write back stuff (do it bit like scratch reg things) 39 * - Vblank : look at Jesse's rework and what we should do 40 * - r600/r700: gart & cp 41 * - cs : clean cs ioctl use bitmap & things like that. 42 * - power management stuff 43 * - Barrier in gart code 44 * - Unmappabled vram ? 45 * - TESTING, TESTING, TESTING 46 */ 47 48 /* Initialization path: 49 * We expect that acceleration initialization might fail for various 50 * reasons even thought we work hard to make it works on most 51 * configurations. In order to still have a working userspace in such 52 * situation the init path must succeed up to the memory controller 53 * initialization point. Failure before this point are considered as 54 * fatal error. Here is the init callchain : 55 * radeon_device_init perform common structure, mutex initialization 56 * asic_init setup the GPU memory layout and perform all 57 * one time initialization (failure in this 58 * function are considered fatal) 59 * asic_startup setup the GPU acceleration, in order to 60 * follow guideline the first thing this 61 * function should do is setting the GPU 62 * memory controller (only MC setup failure 63 * are considered as fatal) 64 */ 65 66 #include <sys/condvar.h> 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/linker.h> 70 #include <sys/firmware.h> 71 72 #include <contrib/dev/acpica-unix/include/acpi.h> 73 #include <dev/acpica/acpivar.h> 74 75 #include <dev/drm/ttm/ttm_bo_api.h> 76 #include <dev/drm/ttm/ttm_bo_driver.h> 77 #include <dev/drm/ttm/ttm_placement.h> 78 #include <dev/drm/ttm/ttm_module.h> 79 #include <dev/drm/ttm/ttm_execbuf_util.h> 80 81 #include "radeon_family.h" 82 #include "radeon_mode.h" 83 #include "radeon_reg.h" 84 85 /* 86 * Modules parameters. 87 */ 88 extern int radeon_no_wb; 89 extern int radeon_modeset; 90 extern int radeon_dynclks; 91 extern int radeon_r4xx_atom; 92 extern int radeon_agpmode; 93 extern int radeon_vram_limit; 94 extern int radeon_gart_size; 95 extern int radeon_benchmarking; 96 extern int radeon_testing; 97 extern int radeon_connector_table; 98 extern int radeon_tv; 99 extern int radeon_audio; 100 extern int radeon_disp_priority; 101 extern int radeon_hw_i2c; 102 extern int radeon_pcie_gen2; 103 extern int radeon_msi; 104 extern int radeon_lockup_timeout; 105 106 /* 107 * Copy from radeon_drv.h so we don't have to include both and have conflicting 108 * symbol; 109 */ 110 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 111 #define RADEON_FENCE_JIFFIES_TIMEOUT (DRM_HZ / 2) 112 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 113 #define RADEON_IB_POOL_SIZE 16 114 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 115 #define RADEONFB_CONN_LIMIT 4 116 #define RADEON_BIOS_NUM_SCRATCH 8 117 118 /* max number of rings */ 119 #define RADEON_NUM_RINGS 5 120 121 /* fence seq are set to this number when signaled */ 122 #define RADEON_FENCE_SIGNALED_SEQ 0LL 123 124 /* internal ring indices */ 125 /* r1xx+ has gfx CP ring */ 126 #define RADEON_RING_TYPE_GFX_INDEX 0 127 128 /* cayman has 2 compute CP rings */ 129 #define CAYMAN_RING_TYPE_CP1_INDEX 1 130 #define CAYMAN_RING_TYPE_CP2_INDEX 2 131 132 /* R600+ has an async dma ring */ 133 #define R600_RING_TYPE_DMA_INDEX 3 134 /* cayman add a second async dma ring */ 135 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 136 137 /* hardcode those limit for now */ 138 #define RADEON_VA_IB_OFFSET (1 << 20) 139 #define RADEON_VA_RESERVED_SIZE (8 << 20) 140 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 141 142 /* reset flags */ 143 #define RADEON_RESET_GFX (1 << 0) 144 #define RADEON_RESET_COMPUTE (1 << 1) 145 #define RADEON_RESET_DMA (1 << 2) 146 147 /* 148 * Errata workarounds. 149 */ 150 enum radeon_pll_errata { 151 CHIP_ERRATA_R300_CG = 0x00000001, 152 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 153 CHIP_ERRATA_PLL_DELAY = 0x00000004 154 }; 155 156 157 struct radeon_device; 158 159 160 /* 161 * BIOS. 162 */ 163 bool radeon_get_bios(struct radeon_device *rdev); 164 165 /* 166 * Dummy page 167 */ 168 struct radeon_dummy_page { 169 drm_dma_handle_t *dmah; 170 dma_addr_t addr; 171 }; 172 int radeon_dummy_page_init(struct radeon_device *rdev); 173 void radeon_dummy_page_fini(struct radeon_device *rdev); 174 175 176 /* 177 * Clocks 178 */ 179 struct radeon_clock { 180 struct radeon_pll p1pll; 181 struct radeon_pll p2pll; 182 struct radeon_pll dcpll; 183 struct radeon_pll spll; 184 struct radeon_pll mpll; 185 /* 10 Khz units */ 186 uint32_t default_mclk; 187 uint32_t default_sclk; 188 uint32_t default_dispclk; 189 uint32_t dp_extclk; 190 uint32_t max_pixel_clock; 191 }; 192 193 /* 194 * Power management 195 */ 196 int radeon_pm_init(struct radeon_device *rdev); 197 void radeon_pm_fini(struct radeon_device *rdev); 198 void radeon_pm_compute_clocks(struct radeon_device *rdev); 199 void radeon_pm_suspend(struct radeon_device *rdev); 200 void radeon_pm_resume(struct radeon_device *rdev); 201 void radeon_combios_get_power_modes(struct radeon_device *rdev); 202 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 203 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 204 void rs690_pm_info(struct radeon_device *rdev); 205 extern int rv6xx_get_temp(struct radeon_device *rdev); 206 extern int rv770_get_temp(struct radeon_device *rdev); 207 extern int evergreen_get_temp(struct radeon_device *rdev); 208 extern int sumo_get_temp(struct radeon_device *rdev); 209 extern int si_get_temp(struct radeon_device *rdev); 210 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 211 unsigned *bankh, unsigned *mtaspect, 212 unsigned *tile_split); 213 214 /* 215 * Fences. 216 */ 217 struct radeon_fence_driver { 218 uint32_t scratch_reg; 219 uint64_t gpu_addr; 220 volatile uint32_t *cpu_addr; 221 /* sync_seq is protected by ring emission lock */ 222 uint64_t sync_seq[RADEON_NUM_RINGS]; 223 atomic64_t last_seq; 224 unsigned long last_activity; 225 bool initialized; 226 }; 227 228 struct radeon_fence { 229 struct radeon_device *rdev; 230 unsigned int kref; 231 /* protected by radeon_fence.lock */ 232 uint64_t seq; 233 /* RB, DMA, etc. */ 234 unsigned ring; 235 }; 236 237 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 238 int radeon_fence_driver_init(struct radeon_device *rdev); 239 void radeon_fence_driver_fini(struct radeon_device *rdev); 240 void radeon_fence_driver_force_completion(struct radeon_device *rdev); 241 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 242 void radeon_fence_process(struct radeon_device *rdev, int ring); 243 bool radeon_fence_signaled(struct radeon_fence *fence); 244 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 245 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring); 246 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring); 247 int radeon_fence_wait_any(struct radeon_device *rdev, 248 struct radeon_fence **fences, 249 bool intr); 250 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 251 void radeon_fence_unref(struct radeon_fence **fence); 252 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 253 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 254 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 255 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 256 struct radeon_fence *b) 257 { 258 if (!a) { 259 return b; 260 } 261 262 if (!b) { 263 return a; 264 } 265 266 KASSERT(a->ring == b->ring, ("\"a\" and \"b\" belongs to different rings")); 267 268 if (a->seq > b->seq) { 269 return a; 270 } else { 271 return b; 272 } 273 } 274 275 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 276 struct radeon_fence *b) 277 { 278 if (!a) { 279 return false; 280 } 281 282 if (!b) { 283 return true; 284 } 285 286 KASSERT(a->ring == b->ring, ("\"a\" and \"b\" belongs to different rings")); 287 288 return a->seq < b->seq; 289 } 290 291 /* 292 * Tiling registers 293 */ 294 struct radeon_surface_reg { 295 struct radeon_bo *bo; 296 }; 297 298 #define RADEON_GEM_MAX_SURFACES 8 299 300 /* 301 * TTM. 302 */ 303 struct radeon_mman { 304 struct ttm_bo_global_ref bo_global_ref; 305 struct drm_global_reference mem_global_ref; 306 struct ttm_bo_device bdev; 307 bool mem_global_referenced; 308 bool initialized; 309 }; 310 311 /* bo virtual address in a specific vm */ 312 struct radeon_bo_va { 313 /* protected by bo being reserved */ 314 struct list_head bo_list; 315 uint64_t soffset; 316 uint64_t eoffset; 317 uint32_t flags; 318 bool valid; 319 unsigned ref_count; 320 321 /* protected by vm mutex */ 322 struct list_head vm_list; 323 324 /* constant after initialization */ 325 struct radeon_vm *vm; 326 struct radeon_bo *bo; 327 }; 328 329 struct radeon_bo { 330 /* Protected by gem.mutex */ 331 struct list_head list; 332 /* Protected by tbo.reserved */ 333 u32 placements[3]; 334 struct ttm_placement placement; 335 struct ttm_buffer_object tbo; 336 struct ttm_bo_kmap_obj kmap; 337 unsigned pin_count; 338 void *kptr; 339 u32 tiling_flags; 340 u32 pitch; 341 int surface_reg; 342 /* list of all virtual address to which this bo 343 * is associated to 344 */ 345 struct list_head va; 346 /* Constant after initialization */ 347 struct radeon_device *rdev; 348 struct drm_gem_object gem_base; 349 350 struct ttm_bo_kmap_obj dma_buf_vmap; 351 int vmapping_count; 352 }; 353 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 354 355 struct radeon_bo_list { 356 struct ttm_validate_buffer tv; 357 struct radeon_bo *bo; 358 uint64_t gpu_offset; 359 unsigned rdomain; 360 unsigned wdomain; 361 u32 tiling_flags; 362 }; 363 364 /* sub-allocation manager, it has to be protected by another lock. 365 * By conception this is an helper for other part of the driver 366 * like the indirect buffer or semaphore, which both have their 367 * locking. 368 * 369 * Principe is simple, we keep a list of sub allocation in offset 370 * order (first entry has offset == 0, last entry has the highest 371 * offset). 372 * 373 * When allocating new object we first check if there is room at 374 * the end total_size - (last_object_offset + last_object_size) >= 375 * alloc_size. If so we allocate new object there. 376 * 377 * When there is not enough room at the end, we start waiting for 378 * each sub object until we reach object_offset+object_size >= 379 * alloc_size, this object then become the sub object we return. 380 * 381 * Alignment can't be bigger than page size. 382 * 383 * Hole are not considered for allocation to keep things simple. 384 * Assumption is that there won't be hole (all object on same 385 * alignment). 386 */ 387 struct radeon_sa_manager { 388 struct cv wq; 389 struct lock wq_lock; 390 struct radeon_bo *bo; 391 struct list_head *hole; 392 struct list_head flist[RADEON_NUM_RINGS]; 393 struct list_head olist; 394 unsigned size; 395 uint64_t gpu_addr; 396 void *cpu_ptr; 397 uint32_t domain; 398 }; 399 400 struct radeon_sa_bo; 401 402 /* sub-allocation buffer */ 403 struct radeon_sa_bo { 404 struct list_head olist; 405 struct list_head flist; 406 struct radeon_sa_manager *manager; 407 unsigned soffset; 408 unsigned eoffset; 409 struct radeon_fence *fence; 410 }; 411 412 /* 413 * GEM objects. 414 */ 415 struct radeon_gem { 416 struct spinlock mutex; 417 struct list_head objects; 418 }; 419 420 int radeon_gem_init(struct radeon_device *rdev); 421 void radeon_gem_fini(struct radeon_device *rdev); 422 int radeon_gem_object_create(struct radeon_device *rdev, int size, 423 int alignment, int initial_domain, 424 bool discardable, bool kernel, 425 struct drm_gem_object **obj); 426 427 int radeon_mode_dumb_create(struct drm_file *file_priv, 428 struct drm_device *dev, 429 struct drm_mode_create_dumb *args); 430 int radeon_mode_dumb_mmap(struct drm_file *filp, 431 struct drm_device *dev, 432 uint32_t handle, uint64_t *offset_p); 433 int radeon_mode_dumb_destroy(struct drm_file *file_priv, 434 struct drm_device *dev, 435 uint32_t handle); 436 437 /* 438 * Semaphores. 439 */ 440 /* everything here is constant */ 441 struct radeon_semaphore { 442 struct radeon_sa_bo *sa_bo; 443 signed waiters; 444 uint64_t gpu_addr; 445 }; 446 447 int radeon_semaphore_create(struct radeon_device *rdev, 448 struct radeon_semaphore **semaphore); 449 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 450 struct radeon_semaphore *semaphore); 451 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 452 struct radeon_semaphore *semaphore); 453 int radeon_semaphore_sync_rings(struct radeon_device *rdev, 454 struct radeon_semaphore *semaphore, 455 int signaler, int waiter); 456 void radeon_semaphore_free(struct radeon_device *rdev, 457 struct radeon_semaphore **semaphore, 458 struct radeon_fence *fence); 459 460 /* 461 * GART structures, functions & helpers 462 */ 463 struct radeon_mc; 464 465 #define RADEON_GPU_PAGE_SIZE 4096 466 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 467 #define RADEON_GPU_PAGE_SHIFT 12 468 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 469 470 struct radeon_gart { 471 drm_dma_handle_t *dmah; 472 dma_addr_t table_addr; 473 struct radeon_bo *robj; 474 void *ptr; 475 unsigned num_gpu_pages; 476 unsigned num_cpu_pages; 477 unsigned table_size; 478 vm_page_t *pages; 479 dma_addr_t *pages_addr; 480 bool ready; 481 }; 482 483 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 484 void radeon_gart_table_ram_free(struct radeon_device *rdev); 485 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 486 void radeon_gart_table_vram_free(struct radeon_device *rdev); 487 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 488 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 489 int radeon_gart_init(struct radeon_device *rdev); 490 void radeon_gart_fini(struct radeon_device *rdev); 491 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 492 int pages); 493 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 494 int pages, vm_page_t *pagelist, 495 dma_addr_t *dma_addr); 496 void radeon_gart_restore(struct radeon_device *rdev); 497 498 499 /* 500 * GPU MC structures, functions & helpers 501 */ 502 struct radeon_mc { 503 resource_size_t aper_size; 504 resource_size_t aper_base; 505 resource_size_t agp_base; 506 /* for some chips with <= 32MB we need to lie 507 * about vram size near mc fb location */ 508 u64 mc_vram_size; 509 u64 visible_vram_size; 510 u64 gtt_size; 511 u64 gtt_start; 512 u64 gtt_end; 513 u64 vram_start; 514 u64 vram_end; 515 unsigned vram_width; 516 u64 real_vram_size; 517 int vram_mtrr; 518 bool vram_is_ddr; 519 bool igp_sideport_enabled; 520 u64 gtt_base_align; 521 }; 522 523 bool radeon_combios_sideport_present(struct radeon_device *rdev); 524 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 525 526 /* 527 * GPU scratch registers structures, functions & helpers 528 */ 529 struct radeon_scratch { 530 unsigned num_reg; 531 uint32_t reg_base; 532 bool free[32]; 533 uint32_t reg[32]; 534 }; 535 536 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 537 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 538 539 540 /* 541 * IRQS. 542 */ 543 544 struct radeon_unpin_work { 545 struct task work; 546 struct radeon_device *rdev; 547 int crtc_id; 548 struct radeon_fence *fence; 549 struct drm_pending_vblank_event *event; 550 struct radeon_bo *old_rbo; 551 u64 new_crtc_base; 552 }; 553 554 struct r500_irq_stat_regs { 555 u32 disp_int; 556 u32 hdmi0_status; 557 }; 558 559 struct r600_irq_stat_regs { 560 u32 disp_int; 561 u32 disp_int_cont; 562 u32 disp_int_cont2; 563 u32 d1grph_int; 564 u32 d2grph_int; 565 u32 hdmi0_status; 566 u32 hdmi1_status; 567 }; 568 569 struct evergreen_irq_stat_regs { 570 u32 disp_int; 571 u32 disp_int_cont; 572 u32 disp_int_cont2; 573 u32 disp_int_cont3; 574 u32 disp_int_cont4; 575 u32 disp_int_cont5; 576 u32 d1grph_int; 577 u32 d2grph_int; 578 u32 d3grph_int; 579 u32 d4grph_int; 580 u32 d5grph_int; 581 u32 d6grph_int; 582 u32 afmt_status1; 583 u32 afmt_status2; 584 u32 afmt_status3; 585 u32 afmt_status4; 586 u32 afmt_status5; 587 u32 afmt_status6; 588 }; 589 590 union radeon_irq_stat_regs { 591 struct r500_irq_stat_regs r500; 592 struct r600_irq_stat_regs r600; 593 struct evergreen_irq_stat_regs evergreen; 594 }; 595 596 #define RADEON_MAX_HPD_PINS 6 597 #define RADEON_MAX_CRTCS 6 598 #define RADEON_MAX_AFMT_BLOCKS 6 599 600 struct radeon_irq { 601 bool installed; 602 struct lock lock; 603 atomic_t ring_int[RADEON_NUM_RINGS]; 604 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 605 atomic_t pflip[RADEON_MAX_CRTCS]; 606 wait_queue_head_t vblank_queue; 607 bool hpd[RADEON_MAX_HPD_PINS]; 608 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 609 union radeon_irq_stat_regs stat_regs; 610 }; 611 612 int radeon_irq_kms_init(struct radeon_device *rdev); 613 void radeon_irq_kms_fini(struct radeon_device *rdev); 614 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 615 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 616 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 617 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 618 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 619 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 620 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 621 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 622 623 /* 624 * CP & rings. 625 */ 626 627 struct radeon_ib { 628 struct radeon_sa_bo *sa_bo; 629 uint32_t length_dw; 630 uint64_t gpu_addr; 631 uint32_t *ptr; 632 int ring; 633 struct radeon_fence *fence; 634 struct radeon_vm *vm; 635 bool is_const_ib; 636 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 637 struct radeon_semaphore *semaphore; 638 }; 639 640 struct radeon_ring { 641 struct radeon_bo *ring_obj; 642 volatile uint32_t *ring; 643 unsigned rptr; 644 unsigned rptr_offs; 645 unsigned rptr_reg; 646 unsigned rptr_save_reg; 647 u64 next_rptr_gpu_addr; 648 volatile u32 *next_rptr_cpu_addr; 649 unsigned wptr; 650 unsigned wptr_old; 651 unsigned wptr_reg; 652 unsigned ring_size; 653 unsigned ring_free_dw; 654 int count_dw; 655 unsigned long last_activity; 656 unsigned last_rptr; 657 uint64_t gpu_addr; 658 uint32_t align_mask; 659 uint32_t ptr_mask; 660 bool ready; 661 u32 ptr_reg_shift; 662 u32 ptr_reg_mask; 663 u32 nop; 664 u32 idx; 665 u64 last_semaphore_signal_addr; 666 u64 last_semaphore_wait_addr; 667 }; 668 669 /* 670 * VM 671 */ 672 673 /* maximum number of VMIDs */ 674 #define RADEON_NUM_VM 16 675 676 /* defines number of bits in page table versus page directory, 677 * a page is 4KB so we have 12 bits offset, 9 bits in the page 678 * table and the remaining 19 bits are in the page directory */ 679 #define RADEON_VM_BLOCK_SIZE 9 680 681 /* number of entries in page table */ 682 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE) 683 684 struct radeon_vm { 685 struct list_head list; 686 struct list_head va; 687 unsigned id; 688 689 /* contains the page directory */ 690 struct radeon_sa_bo *page_directory; 691 uint64_t pd_gpu_addr; 692 693 /* array of page tables, one for each page directory entry */ 694 struct radeon_sa_bo **page_tables; 695 696 struct lock mutex; 697 /* last fence for cs using this vm */ 698 struct radeon_fence *fence; 699 /* last flush or NULL if we still need to flush */ 700 struct radeon_fence *last_flush; 701 }; 702 703 struct radeon_vm_manager { 704 struct lock lock; 705 struct list_head lru_vm; 706 struct radeon_fence *active[RADEON_NUM_VM]; 707 struct radeon_sa_manager sa_manager; 708 uint32_t max_pfn; 709 /* number of VMIDs */ 710 unsigned nvm; 711 /* vram base address for page table entry */ 712 u64 vram_base_offset; 713 /* is vm enabled? */ 714 bool enabled; 715 }; 716 717 /* 718 * file private structure 719 */ 720 struct radeon_fpriv { 721 struct radeon_vm vm; 722 }; 723 724 /* 725 * R6xx+ IH ring 726 */ 727 struct r600_ih { 728 struct radeon_bo *ring_obj; 729 volatile uint32_t *ring; 730 unsigned rptr; 731 unsigned ring_size; 732 uint64_t gpu_addr; 733 uint32_t ptr_mask; 734 atomic_t lock; 735 bool enabled; 736 }; 737 738 struct r600_blit_cp_primitives { 739 void (*set_render_target)(struct radeon_device *rdev, int format, 740 int w, int h, u64 gpu_addr); 741 void (*cp_set_surface_sync)(struct radeon_device *rdev, 742 u32 sync_type, u32 size, 743 u64 mc_addr); 744 void (*set_shaders)(struct radeon_device *rdev); 745 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr); 746 void (*set_tex_resource)(struct radeon_device *rdev, 747 int format, int w, int h, int pitch, 748 u64 gpu_addr, u32 size); 749 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1, 750 int x2, int y2); 751 void (*draw_auto)(struct radeon_device *rdev); 752 void (*set_default_state)(struct radeon_device *rdev); 753 }; 754 755 struct r600_blit { 756 struct radeon_bo *shader_obj; 757 struct r600_blit_cp_primitives primitives; 758 int max_dim; 759 int ring_size_common; 760 int ring_size_per_loop; 761 u64 shader_gpu_addr; 762 u32 vs_offset, ps_offset; 763 u32 state_offset; 764 u32 state_len; 765 }; 766 767 /* 768 * SI RLC stuff 769 */ 770 struct si_rlc { 771 /* for power gating */ 772 struct radeon_bo *save_restore_obj; 773 uint64_t save_restore_gpu_addr; 774 /* for clear state */ 775 struct radeon_bo *clear_state_obj; 776 uint64_t clear_state_gpu_addr; 777 }; 778 779 int radeon_ib_get(struct radeon_device *rdev, int ring, 780 struct radeon_ib *ib, struct radeon_vm *vm, 781 unsigned size); 782 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 783 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 784 struct radeon_ib *const_ib); 785 int radeon_ib_pool_init(struct radeon_device *rdev); 786 void radeon_ib_pool_fini(struct radeon_device *rdev); 787 int radeon_ib_ring_tests(struct radeon_device *rdev); 788 /* Ring access between begin & end cannot sleep */ 789 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 790 struct radeon_ring *ring); 791 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 792 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 793 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 794 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); 795 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); 796 void radeon_ring_undo(struct radeon_ring *ring); 797 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 798 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 799 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring); 800 void radeon_ring_lockup_update(struct radeon_ring *ring); 801 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 802 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 803 uint32_t **data); 804 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 805 unsigned size, uint32_t *data); 806 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 807 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, 808 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop); 809 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 810 811 812 /* r600 async dma */ 813 void r600_dma_stop(struct radeon_device *rdev); 814 int r600_dma_resume(struct radeon_device *rdev); 815 void r600_dma_fini(struct radeon_device *rdev); 816 817 void cayman_dma_stop(struct radeon_device *rdev); 818 int cayman_dma_resume(struct radeon_device *rdev); 819 void cayman_dma_fini(struct radeon_device *rdev); 820 821 /* 822 * CS. 823 */ 824 struct radeon_cs_reloc { 825 struct drm_gem_object *gobj; 826 struct radeon_bo *robj; 827 struct radeon_bo_list lobj; 828 uint32_t handle; 829 uint32_t flags; 830 }; 831 832 struct radeon_cs_chunk { 833 uint32_t chunk_id; 834 uint32_t length_dw; 835 int kpage_idx[2]; 836 uint32_t *kpage[2]; 837 uint32_t *kdata; 838 void __user *user_ptr; 839 int last_copied_page; 840 int last_page_index; 841 }; 842 843 struct radeon_cs_parser { 844 device_t dev; 845 struct radeon_device *rdev; 846 struct drm_file *filp; 847 /* chunks */ 848 unsigned nchunks; 849 struct radeon_cs_chunk *chunks; 850 uint64_t *chunks_array; 851 /* IB */ 852 unsigned idx; 853 /* relocations */ 854 unsigned nrelocs; 855 struct radeon_cs_reloc *relocs; 856 struct radeon_cs_reloc **relocs_ptr; 857 struct list_head validated; 858 unsigned dma_reloc_idx; 859 /* indices of various chunks */ 860 int chunk_ib_idx; 861 int chunk_relocs_idx; 862 int chunk_flags_idx; 863 int chunk_const_ib_idx; 864 struct radeon_ib ib; 865 struct radeon_ib const_ib; 866 void *track; 867 unsigned family; 868 int parser_error; 869 u32 cs_flags; 870 u32 ring; 871 s32 priority; 872 }; 873 874 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); 875 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx); 876 877 struct radeon_cs_packet { 878 unsigned idx; 879 unsigned type; 880 unsigned reg; 881 unsigned opcode; 882 int count; 883 unsigned one_reg_wr; 884 }; 885 886 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 887 struct radeon_cs_packet *pkt, 888 unsigned idx, unsigned reg); 889 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 890 struct radeon_cs_packet *pkt); 891 892 893 /* 894 * AGP 895 */ 896 int radeon_agp_init(struct radeon_device *rdev); 897 void radeon_agp_resume(struct radeon_device *rdev); 898 void radeon_agp_suspend(struct radeon_device *rdev); 899 void radeon_agp_fini(struct radeon_device *rdev); 900 901 902 /* 903 * Writeback 904 */ 905 struct radeon_wb { 906 struct radeon_bo *wb_obj; 907 volatile uint32_t *wb; 908 uint64_t gpu_addr; 909 bool enabled; 910 bool use_event; 911 }; 912 913 #define RADEON_WB_SCRATCH_OFFSET 0 914 #define RADEON_WB_RING0_NEXT_RPTR 256 915 #define RADEON_WB_CP_RPTR_OFFSET 1024 916 #define RADEON_WB_CP1_RPTR_OFFSET 1280 917 #define RADEON_WB_CP2_RPTR_OFFSET 1536 918 #define R600_WB_DMA_RPTR_OFFSET 1792 919 #define R600_WB_IH_WPTR_OFFSET 2048 920 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 921 #define R600_WB_EVENT_OFFSET 3072 922 923 /** 924 * struct radeon_pm - power management datas 925 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 926 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 927 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 928 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 929 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 930 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 931 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 932 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 933 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 934 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 935 * @needed_bandwidth: current bandwidth needs 936 * 937 * It keeps track of various data needed to take powermanagement decision. 938 * Bandwidth need is used to determine minimun clock of the GPU and memory. 939 * Equation between gpu/memory clock and available bandwidth is hw dependent 940 * (type of memory, bus size, efficiency, ...) 941 */ 942 943 enum radeon_pm_method { 944 PM_METHOD_PROFILE, 945 PM_METHOD_DYNPM, 946 }; 947 948 enum radeon_dynpm_state { 949 DYNPM_STATE_DISABLED, 950 DYNPM_STATE_MINIMUM, 951 DYNPM_STATE_PAUSED, 952 DYNPM_STATE_ACTIVE, 953 DYNPM_STATE_SUSPENDED, 954 }; 955 enum radeon_dynpm_action { 956 DYNPM_ACTION_NONE, 957 DYNPM_ACTION_MINIMUM, 958 DYNPM_ACTION_DOWNCLOCK, 959 DYNPM_ACTION_UPCLOCK, 960 DYNPM_ACTION_DEFAULT 961 }; 962 963 enum radeon_voltage_type { 964 VOLTAGE_NONE = 0, 965 VOLTAGE_GPIO, 966 VOLTAGE_VDDC, 967 VOLTAGE_SW 968 }; 969 970 enum radeon_pm_state_type { 971 POWER_STATE_TYPE_DEFAULT, 972 POWER_STATE_TYPE_POWERSAVE, 973 POWER_STATE_TYPE_BATTERY, 974 POWER_STATE_TYPE_BALANCED, 975 POWER_STATE_TYPE_PERFORMANCE, 976 }; 977 978 enum radeon_pm_profile_type { 979 PM_PROFILE_DEFAULT, 980 PM_PROFILE_AUTO, 981 PM_PROFILE_LOW, 982 PM_PROFILE_MID, 983 PM_PROFILE_HIGH, 984 }; 985 986 #define PM_PROFILE_DEFAULT_IDX 0 987 #define PM_PROFILE_LOW_SH_IDX 1 988 #define PM_PROFILE_MID_SH_IDX 2 989 #define PM_PROFILE_HIGH_SH_IDX 3 990 #define PM_PROFILE_LOW_MH_IDX 4 991 #define PM_PROFILE_MID_MH_IDX 5 992 #define PM_PROFILE_HIGH_MH_IDX 6 993 #define PM_PROFILE_MAX 7 994 995 struct radeon_pm_profile { 996 int dpms_off_ps_idx; 997 int dpms_on_ps_idx; 998 int dpms_off_cm_idx; 999 int dpms_on_cm_idx; 1000 }; 1001 1002 enum radeon_int_thermal_type { 1003 THERMAL_TYPE_NONE, 1004 THERMAL_TYPE_RV6XX, 1005 THERMAL_TYPE_RV770, 1006 THERMAL_TYPE_EVERGREEN, 1007 THERMAL_TYPE_SUMO, 1008 THERMAL_TYPE_NI, 1009 THERMAL_TYPE_SI, 1010 }; 1011 1012 struct radeon_voltage { 1013 enum radeon_voltage_type type; 1014 /* gpio voltage */ 1015 struct radeon_gpio_rec gpio; 1016 u32 delay; /* delay in usec from voltage drop to sclk change */ 1017 bool active_high; /* voltage drop is active when bit is high */ 1018 /* VDDC voltage */ 1019 u8 vddc_id; /* index into vddc voltage table */ 1020 u8 vddci_id; /* index into vddci voltage table */ 1021 bool vddci_enabled; 1022 /* r6xx+ sw */ 1023 u16 voltage; 1024 /* evergreen+ vddci */ 1025 u16 vddci; 1026 }; 1027 1028 /* clock mode flags */ 1029 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1030 1031 struct radeon_pm_clock_info { 1032 /* memory clock */ 1033 u32 mclk; 1034 /* engine clock */ 1035 u32 sclk; 1036 /* voltage info */ 1037 struct radeon_voltage voltage; 1038 /* standardized clock flags */ 1039 u32 flags; 1040 }; 1041 1042 /* state flags */ 1043 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1044 1045 struct radeon_power_state { 1046 enum radeon_pm_state_type type; 1047 struct radeon_pm_clock_info *clock_info; 1048 /* number of valid clock modes in this power state */ 1049 int num_clock_modes; 1050 struct radeon_pm_clock_info *default_clock_mode; 1051 /* standardized state flags */ 1052 u32 flags; 1053 u32 misc; /* vbios specific flags */ 1054 u32 misc2; /* vbios specific flags */ 1055 int pcie_lanes; /* pcie lanes */ 1056 }; 1057 1058 /* 1059 * Some modes are overclocked by very low value, accept them 1060 */ 1061 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1062 1063 struct radeon_pm { 1064 struct lock mutex; 1065 /* write locked while reprogramming mclk */ 1066 struct lock mclk_lock; 1067 u32 active_crtcs; 1068 int active_crtc_count; 1069 int req_vblank; 1070 bool vblank_sync; 1071 fixed20_12 max_bandwidth; 1072 fixed20_12 igp_sideport_mclk; 1073 fixed20_12 igp_system_mclk; 1074 fixed20_12 igp_ht_link_clk; 1075 fixed20_12 igp_ht_link_width; 1076 fixed20_12 k8_bandwidth; 1077 fixed20_12 sideport_bandwidth; 1078 fixed20_12 ht_bandwidth; 1079 fixed20_12 core_bandwidth; 1080 fixed20_12 sclk; 1081 fixed20_12 mclk; 1082 fixed20_12 needed_bandwidth; 1083 struct radeon_power_state *power_state; 1084 /* number of valid power states */ 1085 int num_power_states; 1086 int current_power_state_index; 1087 int current_clock_mode_index; 1088 int requested_power_state_index; 1089 int requested_clock_mode_index; 1090 int default_power_state_index; 1091 u32 current_sclk; 1092 u32 current_mclk; 1093 u16 current_vddc; 1094 u16 current_vddci; 1095 u32 default_sclk; 1096 u32 default_mclk; 1097 u16 default_vddc; 1098 u16 default_vddci; 1099 struct radeon_i2c_chan *i2c_bus; 1100 /* selected pm method */ 1101 enum radeon_pm_method pm_method; 1102 /* dynpm power management */ 1103 #ifdef DUMBBELL_WIP 1104 struct delayed_work dynpm_idle_work; 1105 #endif /* DUMBBELL_WIP */ 1106 enum radeon_dynpm_state dynpm_state; 1107 enum radeon_dynpm_action dynpm_planned_action; 1108 unsigned long dynpm_action_timeout; 1109 bool dynpm_can_upclock; 1110 bool dynpm_can_downclock; 1111 /* profile-based power management */ 1112 enum radeon_pm_profile_type profile; 1113 int profile_index; 1114 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1115 /* internal thermal controller on rv6xx+ */ 1116 enum radeon_int_thermal_type int_thermal_type; 1117 #ifdef DUMBBELL_WIP 1118 struct device *int_hwmon_dev; 1119 #endif /* DUMBBELL_WIP */ 1120 }; 1121 1122 int radeon_pm_get_type_index(struct radeon_device *rdev, 1123 enum radeon_pm_state_type ps_type, 1124 int instance); 1125 1126 struct r600_audio { 1127 int channels; 1128 int rate; 1129 int bits_per_sample; 1130 u8 status_bits; 1131 u8 category_code; 1132 }; 1133 1134 /* 1135 * Benchmarking 1136 */ 1137 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1138 1139 1140 /* 1141 * Testing 1142 */ 1143 void radeon_test_moves(struct radeon_device *rdev); 1144 void radeon_test_ring_sync(struct radeon_device *rdev, 1145 struct radeon_ring *cpA, 1146 struct radeon_ring *cpB); 1147 void radeon_test_syncing(struct radeon_device *rdev); 1148 1149 1150 /* 1151 * Debugfs 1152 */ 1153 struct radeon_debugfs { 1154 struct drm_info_list *files; 1155 unsigned num_files; 1156 }; 1157 1158 int radeon_debugfs_add_files(struct radeon_device *rdev, 1159 struct drm_info_list *files, 1160 unsigned nfiles); 1161 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1162 1163 1164 /* 1165 * ASIC specific functions. 1166 */ 1167 struct radeon_asic { 1168 int (*init)(struct radeon_device *rdev); 1169 void (*fini)(struct radeon_device *rdev); 1170 int (*resume)(struct radeon_device *rdev); 1171 int (*suspend)(struct radeon_device *rdev); 1172 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1173 int (*asic_reset)(struct radeon_device *rdev); 1174 /* ioctl hw specific callback. Some hw might want to perform special 1175 * operation on specific ioctl. For instance on wait idle some hw 1176 * might want to perform and HDP flush through MMIO as it seems that 1177 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed 1178 * through ring. 1179 */ 1180 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); 1181 /* check if 3D engine is idle */ 1182 bool (*gui_idle)(struct radeon_device *rdev); 1183 /* wait for mc_idle */ 1184 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1185 /* gart */ 1186 struct { 1187 void (*tlb_flush)(struct radeon_device *rdev); 1188 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr); 1189 } gart; 1190 struct { 1191 int (*init)(struct radeon_device *rdev); 1192 void (*fini)(struct radeon_device *rdev); 1193 1194 u32 pt_ring_index; 1195 void (*set_page)(struct radeon_device *rdev, uint64_t pe, 1196 uint64_t addr, unsigned count, 1197 uint32_t incr, uint32_t flags); 1198 } vm; 1199 /* ring specific callbacks */ 1200 struct { 1201 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1202 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1203 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1204 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1205 struct radeon_semaphore *semaphore, bool emit_wait); 1206 int (*cs_parse)(struct radeon_cs_parser *p); 1207 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1208 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1209 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1210 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1211 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 1212 } ring[RADEON_NUM_RINGS]; 1213 /* irqs */ 1214 struct { 1215 int (*set)(struct radeon_device *rdev); 1216 irqreturn_t (*process)(struct radeon_device *rdev); 1217 } irq; 1218 /* displays */ 1219 struct { 1220 /* display watermarks */ 1221 void (*bandwidth_update)(struct radeon_device *rdev); 1222 /* get frame count */ 1223 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1224 /* wait for vblank */ 1225 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1226 /* set backlight level */ 1227 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1228 /* get backlight level */ 1229 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1230 } display; 1231 /* copy functions for bo handling */ 1232 struct { 1233 int (*blit)(struct radeon_device *rdev, 1234 uint64_t src_offset, 1235 uint64_t dst_offset, 1236 unsigned num_gpu_pages, 1237 struct radeon_fence **fence); 1238 u32 blit_ring_index; 1239 int (*dma)(struct radeon_device *rdev, 1240 uint64_t src_offset, 1241 uint64_t dst_offset, 1242 unsigned num_gpu_pages, 1243 struct radeon_fence **fence); 1244 u32 dma_ring_index; 1245 /* method used for bo copy */ 1246 int (*copy)(struct radeon_device *rdev, 1247 uint64_t src_offset, 1248 uint64_t dst_offset, 1249 unsigned num_gpu_pages, 1250 struct radeon_fence **fence); 1251 /* ring used for bo copies */ 1252 u32 copy_ring_index; 1253 } copy; 1254 /* surfaces */ 1255 struct { 1256 int (*set_reg)(struct radeon_device *rdev, int reg, 1257 uint32_t tiling_flags, uint32_t pitch, 1258 uint32_t offset, uint32_t obj_size); 1259 void (*clear_reg)(struct radeon_device *rdev, int reg); 1260 } surface; 1261 /* hotplug detect */ 1262 struct { 1263 void (*init)(struct radeon_device *rdev); 1264 void (*fini)(struct radeon_device *rdev); 1265 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1266 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1267 } hpd; 1268 /* power management */ 1269 struct { 1270 void (*misc)(struct radeon_device *rdev); 1271 void (*prepare)(struct radeon_device *rdev); 1272 void (*finish)(struct radeon_device *rdev); 1273 void (*init_profile)(struct radeon_device *rdev); 1274 void (*get_dynpm_state)(struct radeon_device *rdev); 1275 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1276 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1277 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1278 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1279 int (*get_pcie_lanes)(struct radeon_device *rdev); 1280 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1281 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1282 } pm; 1283 /* pageflipping */ 1284 struct { 1285 void (*pre_page_flip)(struct radeon_device *rdev, int crtc); 1286 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 1287 void (*post_page_flip)(struct radeon_device *rdev, int crtc); 1288 } pflip; 1289 }; 1290 1291 /* 1292 * Asic structures 1293 */ 1294 struct r100_asic { 1295 const unsigned *reg_safe_bm; 1296 unsigned reg_safe_bm_size; 1297 u32 hdp_cntl; 1298 }; 1299 1300 struct r300_asic { 1301 const unsigned *reg_safe_bm; 1302 unsigned reg_safe_bm_size; 1303 u32 resync_scratch; 1304 u32 hdp_cntl; 1305 }; 1306 1307 struct r600_asic { 1308 unsigned max_pipes; 1309 unsigned max_tile_pipes; 1310 unsigned max_simds; 1311 unsigned max_backends; 1312 unsigned max_gprs; 1313 unsigned max_threads; 1314 unsigned max_stack_entries; 1315 unsigned max_hw_contexts; 1316 unsigned max_gs_threads; 1317 unsigned sx_max_export_size; 1318 unsigned sx_max_export_pos_size; 1319 unsigned sx_max_export_smx_size; 1320 unsigned sq_num_cf_insts; 1321 unsigned tiling_nbanks; 1322 unsigned tiling_npipes; 1323 unsigned tiling_group_size; 1324 unsigned tile_config; 1325 unsigned backend_map; 1326 }; 1327 1328 struct rv770_asic { 1329 unsigned max_pipes; 1330 unsigned max_tile_pipes; 1331 unsigned max_simds; 1332 unsigned max_backends; 1333 unsigned max_gprs; 1334 unsigned max_threads; 1335 unsigned max_stack_entries; 1336 unsigned max_hw_contexts; 1337 unsigned max_gs_threads; 1338 unsigned sx_max_export_size; 1339 unsigned sx_max_export_pos_size; 1340 unsigned sx_max_export_smx_size; 1341 unsigned sq_num_cf_insts; 1342 unsigned sx_num_of_sets; 1343 unsigned sc_prim_fifo_size; 1344 unsigned sc_hiz_tile_fifo_size; 1345 unsigned sc_earlyz_tile_fifo_fize; 1346 unsigned tiling_nbanks; 1347 unsigned tiling_npipes; 1348 unsigned tiling_group_size; 1349 unsigned tile_config; 1350 unsigned backend_map; 1351 }; 1352 1353 struct evergreen_asic { 1354 unsigned num_ses; 1355 unsigned max_pipes; 1356 unsigned max_tile_pipes; 1357 unsigned max_simds; 1358 unsigned max_backends; 1359 unsigned max_gprs; 1360 unsigned max_threads; 1361 unsigned max_stack_entries; 1362 unsigned max_hw_contexts; 1363 unsigned max_gs_threads; 1364 unsigned sx_max_export_size; 1365 unsigned sx_max_export_pos_size; 1366 unsigned sx_max_export_smx_size; 1367 unsigned sq_num_cf_insts; 1368 unsigned sx_num_of_sets; 1369 unsigned sc_prim_fifo_size; 1370 unsigned sc_hiz_tile_fifo_size; 1371 unsigned sc_earlyz_tile_fifo_size; 1372 unsigned tiling_nbanks; 1373 unsigned tiling_npipes; 1374 unsigned tiling_group_size; 1375 unsigned tile_config; 1376 unsigned backend_map; 1377 }; 1378 1379 struct cayman_asic { 1380 unsigned max_shader_engines; 1381 unsigned max_pipes_per_simd; 1382 unsigned max_tile_pipes; 1383 unsigned max_simds_per_se; 1384 unsigned max_backends_per_se; 1385 unsigned max_texture_channel_caches; 1386 unsigned max_gprs; 1387 unsigned max_threads; 1388 unsigned max_gs_threads; 1389 unsigned max_stack_entries; 1390 unsigned sx_num_of_sets; 1391 unsigned sx_max_export_size; 1392 unsigned sx_max_export_pos_size; 1393 unsigned sx_max_export_smx_size; 1394 unsigned max_hw_contexts; 1395 unsigned sq_num_cf_insts; 1396 unsigned sc_prim_fifo_size; 1397 unsigned sc_hiz_tile_fifo_size; 1398 unsigned sc_earlyz_tile_fifo_size; 1399 1400 unsigned num_shader_engines; 1401 unsigned num_shader_pipes_per_simd; 1402 unsigned num_tile_pipes; 1403 unsigned num_simds_per_se; 1404 unsigned num_backends_per_se; 1405 unsigned backend_disable_mask_per_asic; 1406 unsigned backend_map; 1407 unsigned num_texture_channel_caches; 1408 unsigned mem_max_burst_length_bytes; 1409 unsigned mem_row_size_in_kb; 1410 unsigned shader_engine_tile_size; 1411 unsigned num_gpus; 1412 unsigned multi_gpu_tile_size; 1413 1414 unsigned tile_config; 1415 }; 1416 1417 struct si_asic { 1418 unsigned max_shader_engines; 1419 unsigned max_tile_pipes; 1420 unsigned max_cu_per_sh; 1421 unsigned max_sh_per_se; 1422 unsigned max_backends_per_se; 1423 unsigned max_texture_channel_caches; 1424 unsigned max_gprs; 1425 unsigned max_gs_threads; 1426 unsigned max_hw_contexts; 1427 unsigned sc_prim_fifo_size_frontend; 1428 unsigned sc_prim_fifo_size_backend; 1429 unsigned sc_hiz_tile_fifo_size; 1430 unsigned sc_earlyz_tile_fifo_size; 1431 1432 unsigned num_tile_pipes; 1433 unsigned num_backends_per_se; 1434 unsigned backend_disable_mask_per_asic; 1435 unsigned backend_map; 1436 unsigned num_texture_channel_caches; 1437 unsigned mem_max_burst_length_bytes; 1438 unsigned mem_row_size_in_kb; 1439 unsigned shader_engine_tile_size; 1440 unsigned num_gpus; 1441 unsigned multi_gpu_tile_size; 1442 1443 unsigned tile_config; 1444 }; 1445 1446 union radeon_asic_config { 1447 struct r300_asic r300; 1448 struct r100_asic r100; 1449 struct r600_asic r600; 1450 struct rv770_asic rv770; 1451 struct evergreen_asic evergreen; 1452 struct cayman_asic cayman; 1453 struct si_asic si; 1454 }; 1455 1456 /* 1457 * asic initizalization from radeon_asic.c 1458 */ 1459 int radeon_asic_init(struct radeon_device *rdev); 1460 1461 1462 /* 1463 * IOCTL. 1464 */ 1465 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 1466 struct drm_file *filp); 1467 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 1468 struct drm_file *filp); 1469 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 1470 struct drm_file *file_priv); 1471 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 1472 struct drm_file *file_priv); 1473 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1474 struct drm_file *file_priv); 1475 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 1476 struct drm_file *file_priv); 1477 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1478 struct drm_file *filp); 1479 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 1480 struct drm_file *filp); 1481 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 1482 struct drm_file *filp); 1483 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1484 struct drm_file *filp); 1485 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 1486 struct drm_file *filp); 1487 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1488 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 1489 struct drm_file *filp); 1490 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 1491 struct drm_file *filp); 1492 1493 /* VRAM scratch page for HDP bug, default vram page */ 1494 struct r600_vram_scratch { 1495 struct radeon_bo *robj; 1496 volatile uint32_t *ptr; 1497 u64 gpu_addr; 1498 }; 1499 1500 /* 1501 * ACPI 1502 */ 1503 struct radeon_atif_notification_cfg { 1504 bool enabled; 1505 int command_code; 1506 }; 1507 1508 struct radeon_atif_notifications { 1509 bool display_switch; 1510 bool expansion_mode_change; 1511 bool thermal_state; 1512 bool forced_power_state; 1513 bool system_power_state; 1514 bool display_conf_change; 1515 bool px_gfx_switch; 1516 bool brightness_change; 1517 bool dgpu_display_event; 1518 }; 1519 1520 struct radeon_atif_functions { 1521 bool system_params; 1522 bool sbios_requests; 1523 bool select_active_disp; 1524 bool lid_state; 1525 bool get_tv_standard; 1526 bool set_tv_standard; 1527 bool get_panel_expansion_mode; 1528 bool set_panel_expansion_mode; 1529 bool temperature_change; 1530 bool graphics_device_types; 1531 }; 1532 1533 struct radeon_atif { 1534 struct radeon_atif_notifications notifications; 1535 struct radeon_atif_functions functions; 1536 struct radeon_atif_notification_cfg notification_cfg; 1537 struct radeon_encoder *encoder_for_bl; 1538 }; 1539 1540 struct radeon_atcs_functions { 1541 bool get_ext_state; 1542 bool pcie_perf_req; 1543 bool pcie_dev_rdy; 1544 bool pcie_bus_width; 1545 }; 1546 1547 struct radeon_atcs { 1548 struct radeon_atcs_functions functions; 1549 }; 1550 1551 /* 1552 * Core structure, functions and helpers. 1553 */ 1554 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 1555 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 1556 1557 struct radeon_device { 1558 device_t dev; 1559 struct drm_device *ddev; 1560 struct lock exclusive_lock; 1561 /* ASIC */ 1562 union radeon_asic_config config; 1563 enum radeon_family family; 1564 unsigned long flags; 1565 int usec_timeout; 1566 enum radeon_pll_errata pll_errata; 1567 int num_gb_pipes; 1568 int num_z_pipes; 1569 int disp_priority; 1570 /* BIOS */ 1571 uint8_t *bios; 1572 bool is_atom_bios; 1573 uint16_t bios_header_start; 1574 struct radeon_bo *stollen_vga_memory; 1575 /* Register mmio */ 1576 resource_size_t rmmio_base; 1577 resource_size_t rmmio_size; 1578 /* protects concurrent MM_INDEX/DATA based register access */ 1579 struct spinlock mmio_idx_lock; 1580 int rmmio_rid; 1581 struct resource *rmmio; 1582 radeon_rreg_t mc_rreg; 1583 radeon_wreg_t mc_wreg; 1584 radeon_rreg_t pll_rreg; 1585 radeon_wreg_t pll_wreg; 1586 uint32_t pcie_reg_mask; 1587 radeon_rreg_t pciep_rreg; 1588 radeon_wreg_t pciep_wreg; 1589 /* io port */ 1590 int rio_rid; 1591 struct resource *rio_mem; 1592 resource_size_t rio_mem_size; 1593 struct radeon_clock clock; 1594 struct radeon_mc mc; 1595 struct radeon_gart gart; 1596 struct radeon_mode_info mode_info; 1597 struct radeon_scratch scratch; 1598 struct radeon_mman mman; 1599 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 1600 struct cv fence_queue; 1601 struct lock fence_queue_mtx; 1602 struct lock ring_lock; 1603 struct radeon_ring ring[RADEON_NUM_RINGS]; 1604 bool ib_pool_ready; 1605 struct radeon_sa_manager ring_tmp_bo; 1606 struct radeon_irq irq; 1607 struct radeon_asic *asic; 1608 struct radeon_gem gem; 1609 struct radeon_pm pm; 1610 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 1611 struct radeon_wb wb; 1612 struct radeon_dummy_page dummy_page; 1613 bool shutdown; 1614 bool suspend; 1615 bool need_dma32; 1616 bool accel_working; 1617 bool fictitious_range_registered; 1618 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 1619 const struct firmware *me_fw; /* all family ME firmware */ 1620 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 1621 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 1622 const struct firmware *mc_fw; /* NI MC firmware */ 1623 const struct firmware *ce_fw; /* SI CE firmware */ 1624 struct r600_blit r600_blit; 1625 struct r600_vram_scratch vram_scratch; 1626 int msi_enabled; /* msi enabled */ 1627 struct r600_ih ih; /* r6/700 interrupt ring */ 1628 struct si_rlc rlc; 1629 struct taskqueue *tq; 1630 struct task hotplug_work; 1631 struct task audio_work; 1632 int num_crtc; /* number of crtcs */ 1633 struct lock dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 1634 bool audio_enabled; 1635 struct r600_audio audio_status; /* audio stuff */ 1636 struct { 1637 ACPI_HANDLE handle; 1638 ACPI_NOTIFY_HANDLER notifier_call; 1639 } acpi; 1640 /* only one userspace can use Hyperz features or CMASK at a time */ 1641 struct drm_file *hyperz_filp; 1642 struct drm_file *cmask_filp; 1643 /* i2c buses */ 1644 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 1645 /* debugfs */ 1646 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 1647 unsigned debugfs_count; 1648 /* virtual memory */ 1649 struct radeon_vm_manager vm_manager; 1650 struct spinlock gpu_clock_mutex; 1651 /* ACPI interface */ 1652 struct radeon_atif atif; 1653 struct radeon_atcs atcs; 1654 }; 1655 1656 int radeon_device_init(struct radeon_device *rdev, 1657 struct drm_device *ddev, 1658 uint32_t flags); 1659 void radeon_device_fini(struct radeon_device *rdev); 1660 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 1661 1662 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 1663 bool always_indirect); 1664 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 1665 bool always_indirect); 1666 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 1667 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 1668 1669 /* 1670 * Cast helper 1671 */ 1672 #define to_radeon_fence(p) ((struct radeon_fence *)(p)) 1673 1674 /* 1675 * Registers read & write functions. 1676 */ 1677 #define RREG8(reg) bus_read_1((rdev->rmmio), (reg)) 1678 #define WREG8(reg, v) bus_write_1((rdev->rmmio), (reg), v) 1679 #define RREG16(reg) bus_read_2((rdev->rmmio), (reg)) 1680 #define WREG16(reg, v) bus_write_2((rdev->rmmio), (reg), v) 1681 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 1682 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 1683 #define DREG32(reg) DRM_INFO("REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) 1684 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 1685 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 1686 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1687 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1688 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 1689 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 1690 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 1691 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 1692 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 1693 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 1694 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) 1695 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 1696 #define WREG32_P(reg, val, mask) \ 1697 do { \ 1698 uint32_t tmp_ = RREG32(reg); \ 1699 tmp_ &= (mask); \ 1700 tmp_ |= ((val) & ~(mask)); \ 1701 WREG32(reg, tmp_); \ 1702 } while (0) 1703 #define WREG32_PLL_P(reg, val, mask) \ 1704 do { \ 1705 uint32_t tmp_ = RREG32_PLL(reg); \ 1706 tmp_ &= (mask); \ 1707 tmp_ |= ((val) & ~(mask)); \ 1708 WREG32_PLL(reg, tmp_); \ 1709 } while (0) 1710 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 1711 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 1712 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 1713 1714 /* 1715 * Indirect registers accessor 1716 */ 1717 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 1718 { 1719 uint32_t r; 1720 1721 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 1722 r = RREG32(RADEON_PCIE_DATA); 1723 return r; 1724 } 1725 1726 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1727 { 1728 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 1729 WREG32(RADEON_PCIE_DATA, (v)); 1730 } 1731 1732 void r100_pll_errata_after_index(struct radeon_device *rdev); 1733 1734 1735 /* 1736 * ASICs helpers. 1737 */ 1738 #define ASIC_IS_RN50(rdev) ((rdev->ddev->pci_device == 0x515e) || \ 1739 (rdev->ddev->pci_device == 0x5969)) 1740 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 1741 (rdev->family == CHIP_RV200) || \ 1742 (rdev->family == CHIP_RS100) || \ 1743 (rdev->family == CHIP_RS200) || \ 1744 (rdev->family == CHIP_RV250) || \ 1745 (rdev->family == CHIP_RV280) || \ 1746 (rdev->family == CHIP_RS300)) 1747 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 1748 (rdev->family == CHIP_RV350) || \ 1749 (rdev->family == CHIP_R350) || \ 1750 (rdev->family == CHIP_RV380) || \ 1751 (rdev->family == CHIP_R420) || \ 1752 (rdev->family == CHIP_R423) || \ 1753 (rdev->family == CHIP_RV410) || \ 1754 (rdev->family == CHIP_RS400) || \ 1755 (rdev->family == CHIP_RS480)) 1756 #define ASIC_IS_X2(rdev) ((rdev->ddev->pci_device == 0x9441) || \ 1757 (rdev->ddev->pci_device == 0x9443) || \ 1758 (rdev->ddev->pci_device == 0x944B) || \ 1759 (rdev->ddev->pci_device == 0x9506) || \ 1760 (rdev->ddev->pci_device == 0x9509) || \ 1761 (rdev->ddev->pci_device == 0x950F) || \ 1762 (rdev->ddev->pci_device == 0x689C) || \ 1763 (rdev->ddev->pci_device == 0x689D)) 1764 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 1765 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 1766 (rdev->family == CHIP_RS690) || \ 1767 (rdev->family == CHIP_RS740) || \ 1768 (rdev->family >= CHIP_R600)) 1769 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 1770 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 1771 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 1772 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 1773 (rdev->flags & RADEON_IS_IGP)) 1774 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 1775 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 1776 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 1777 (rdev->flags & RADEON_IS_IGP)) 1778 1779 /* 1780 * BIOS helpers. 1781 */ 1782 #define RBIOS8(i) (rdev->bios[i]) 1783 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1784 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1785 1786 int radeon_combios_init(struct radeon_device *rdev); 1787 void radeon_combios_fini(struct radeon_device *rdev); 1788 int radeon_atombios_init(struct radeon_device *rdev); 1789 void radeon_atombios_fini(struct radeon_device *rdev); 1790 1791 1792 /* 1793 * RING helpers. 1794 */ 1795 #if !defined(DRM_DEBUG_CODE) || DRM_DEBUG_CODE == 0 1796 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 1797 { 1798 ring->ring[ring->wptr++] = v; 1799 ring->wptr &= ring->ptr_mask; 1800 ring->count_dw--; 1801 ring->ring_free_dw--; 1802 } 1803 #else 1804 /* With debugging this is just too big to inline */ 1805 void radeon_ring_write(struct radeon_ring *ring, uint32_t v); 1806 #endif 1807 1808 /* 1809 * ASICs macro. 1810 */ 1811 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 1812 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 1813 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 1814 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 1815 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p)) 1816 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 1817 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 1818 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 1819 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) 1820 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 1821 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 1822 #define radeon_asic_vm_set_page(rdev, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (pe), (addr), (count), (incr), (flags))) 1823 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp)) 1824 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp)) 1825 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp)) 1826 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib)) 1827 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib)) 1828 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp)) 1829 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm)) 1830 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 1831 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 1832 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 1833 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 1834 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 1835 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence)) 1836 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 1837 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) 1838 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) 1839 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) 1840 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 1841 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 1842 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 1843 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 1844 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 1845 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 1846 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 1847 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 1848 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 1849 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 1850 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 1851 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 1852 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 1853 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 1854 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 1855 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 1856 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 1857 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 1858 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 1859 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 1860 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 1861 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 1862 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 1863 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc)) 1864 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) 1865 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc)) 1866 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 1867 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 1868 1869 /* Common functions */ 1870 /* AGP */ 1871 extern int radeon_gpu_reset(struct radeon_device *rdev); 1872 extern void radeon_agp_disable(struct radeon_device *rdev); 1873 extern int radeon_modeset_init(struct radeon_device *rdev); 1874 extern void radeon_modeset_fini(struct radeon_device *rdev); 1875 extern bool radeon_card_posted(struct radeon_device *rdev); 1876 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 1877 extern void radeon_update_display_priority(struct radeon_device *rdev); 1878 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 1879 extern void radeon_scratch_init(struct radeon_device *rdev); 1880 extern void radeon_wb_fini(struct radeon_device *rdev); 1881 extern int radeon_wb_init(struct radeon_device *rdev); 1882 extern void radeon_wb_disable(struct radeon_device *rdev); 1883 extern void radeon_surface_init(struct radeon_device *rdev); 1884 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 1885 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 1886 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 1887 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 1888 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 1889 extern int radeon_resume_kms(struct drm_device *dev); 1890 extern int radeon_suspend_kms(struct drm_device *dev); 1891 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 1892 1893 /* 1894 * vm 1895 */ 1896 int radeon_vm_manager_init(struct radeon_device *rdev); 1897 void radeon_vm_manager_fini(struct radeon_device *rdev); 1898 void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 1899 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 1900 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm); 1901 void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm); 1902 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 1903 struct radeon_vm *vm, int ring); 1904 void radeon_vm_fence(struct radeon_device *rdev, 1905 struct radeon_vm *vm, 1906 struct radeon_fence *fence); 1907 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 1908 int radeon_vm_bo_update_pte(struct radeon_device *rdev, 1909 struct radeon_vm *vm, 1910 struct radeon_bo *bo, 1911 struct ttm_mem_reg *mem); 1912 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 1913 struct radeon_bo *bo); 1914 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 1915 struct radeon_bo *bo); 1916 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 1917 struct radeon_vm *vm, 1918 struct radeon_bo *bo); 1919 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 1920 struct radeon_bo_va *bo_va, 1921 uint64_t offset, 1922 uint32_t flags); 1923 int radeon_vm_bo_rmv(struct radeon_device *rdev, 1924 struct radeon_bo_va *bo_va); 1925 1926 /* audio */ 1927 void r600_audio_update_hdmi(void *arg, int pending); 1928 1929 /* 1930 * R600 vram scratch functions 1931 */ 1932 int r600_vram_scratch_init(struct radeon_device *rdev); 1933 void r600_vram_scratch_fini(struct radeon_device *rdev); 1934 1935 /* 1936 * r600 cs checking helper 1937 */ 1938 unsigned r600_mip_minify(unsigned size, unsigned level); 1939 bool r600_fmt_is_valid_color(u32 format); 1940 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 1941 int r600_fmt_get_blocksize(u32 format); 1942 int r600_fmt_get_nblocksx(u32 format, u32 w); 1943 int r600_fmt_get_nblocksy(u32 format, u32 h); 1944 1945 /* 1946 * r600 functions used by radeon_encoder.c 1947 */ 1948 struct radeon_hdmi_acr { 1949 u32 clock; 1950 1951 int n_32khz; 1952 int cts_32khz; 1953 1954 int n_44_1khz; 1955 int cts_44_1khz; 1956 1957 int n_48khz; 1958 int cts_48khz; 1959 1960 }; 1961 1962 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 1963 1964 extern void r600_hdmi_enable(struct drm_encoder *encoder); 1965 extern void r600_hdmi_disable(struct drm_encoder *encoder); 1966 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 1967 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 1968 u32 tiling_pipe_num, 1969 u32 max_rb_num, 1970 u32 total_max_rb_num, 1971 u32 enabled_rb_mask); 1972 1973 /* 1974 * evergreen functions used by radeon_encoder.c 1975 */ 1976 1977 extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 1978 1979 extern int ni_init_microcode(struct radeon_device *rdev); 1980 extern int ni_mc_load_microcode(struct radeon_device *rdev); 1981 extern void ni_fini_microcode(struct radeon_device *rdev); 1982 1983 /* radeon_acpi.c */ 1984 extern int radeon_acpi_init(struct radeon_device *rdev); 1985 extern void radeon_acpi_fini(struct radeon_device *rdev); 1986 1987 /* Prototypes added by @dumbbell. */ 1988 1989 /* atombios_encoders.c */ 1990 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 1991 struct drm_connector *drm_connector); 1992 void radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, 1993 uint32_t supported_device, u16 caps); 1994 1995 /* radeon_atombios.c */ 1996 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 1997 struct drm_display_mode *mode); 1998 1999 /* radeon_combios.c */ 2000 void radeon_combios_connected_scratch_regs(struct drm_connector *connector, 2001 struct drm_encoder *encoder, bool connected); 2002 2003 /* radeon_connectors.c */ 2004 void radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 2005 struct drm_encoder *encoder, bool connected); 2006 void radeon_add_legacy_connector(struct drm_device *dev, 2007 uint32_t connector_id, 2008 uint32_t supported_device, 2009 int connector_type, 2010 struct radeon_i2c_bus_rec *i2c_bus, 2011 uint16_t connector_object_id, 2012 struct radeon_hpd *hpd); 2013 void radeon_add_atom_connector(struct drm_device *dev, 2014 uint32_t connector_id, 2015 uint32_t supported_device, 2016 int connector_type, 2017 struct radeon_i2c_bus_rec *i2c_bus, 2018 uint32_t igp_lane_info, 2019 uint16_t connector_object_id, 2020 struct radeon_hpd *hpd, 2021 struct radeon_router *router); 2022 2023 /* radeon_encoders.c */ 2024 uint32_t radeon_get_encoder_enum(struct drm_device *dev, 2025 uint32_t supported_device, uint8_t dac); 2026 void radeon_link_encoder_connector(struct drm_device *dev); 2027 2028 /* radeon_legacy_encoders.c */ 2029 void radeon_add_legacy_encoder(struct drm_device *dev, 2030 uint32_t encoder_enum, uint32_t supported_device); 2031 void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder, 2032 struct drm_connector *drm_connector); 2033 2034 /* radeon_pm.c */ 2035 void radeon_pm_acpi_event_handler(struct radeon_device *rdev); 2036 2037 /* radeon_ttm.c */ 2038 int radeon_ttm_init(struct radeon_device *rdev); 2039 void radeon_ttm_fini(struct radeon_device *rdev); 2040 2041 /* r600.c */ 2042 int r600_ih_ring_alloc(struct radeon_device *rdev); 2043 void r600_ih_ring_fini(struct radeon_device *rdev); 2044 2045 #include "radeon_object.h" 2046 2047 #endif 2048