1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #ifndef __RADEON_H__ 30 #define __RADEON_H__ 31 32 /* TODO: Here are things that needs to be done : 33 * - surface allocator & initializer : (bit like scratch reg) should 34 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 35 * related to surface 36 * - WB : write back stuff (do it bit like scratch reg things) 37 * - Vblank : look at Jesse's rework and what we should do 38 * - r600/r700: gart & cp 39 * - cs : clean cs ioctl use bitmap & things like that. 40 * - power management stuff 41 * - Barrier in gart code 42 * - Unmappabled vram ? 43 * - TESTING, TESTING, TESTING 44 */ 45 46 /* Initialization path: 47 * We expect that acceleration initialization might fail for various 48 * reasons even thought we work hard to make it works on most 49 * configurations. In order to still have a working userspace in such 50 * situation the init path must succeed up to the memory controller 51 * initialization point. Failure before this point are considered as 52 * fatal error. Here is the init callchain : 53 * radeon_device_init perform common structure, mutex initialization 54 * asic_init setup the GPU memory layout and perform all 55 * one time initialization (failure in this 56 * function are considered fatal) 57 * asic_startup setup the GPU acceleration, in order to 58 * follow guideline the first thing this 59 * function should do is setting the GPU 60 * memory controller (only MC setup failure 61 * are considered as fatal) 62 */ 63 64 #include <sys/condvar.h> 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/linker.h> 68 #include <linux/firmware.h> 69 #include <linux/seq_file.h> 70 71 #include <contrib/dev/acpica/source/include/acpi.h> 72 #include <dev/acpica/acpivar.h> 73 74 #include <linux/atomic.h> 75 #include <linux/wait.h> 76 #include <linux/list.h> 77 #include <linux/kref.h> 78 #include <linux/hashtable.h> 79 #include <linux/fence.h> 80 81 #include <drm/ttm/ttm_bo_api.h> 82 #include <drm/ttm/ttm_bo_driver.h> 83 #include <drm/ttm/ttm_placement.h> 84 #include <drm/ttm/ttm_module.h> 85 #include <drm/ttm/ttm_execbuf_util.h> 86 87 #include <drm/drm_gem.h> 88 #define CONFIG_ACPI 1 89 90 #include "radeon_family.h" 91 #include "radeon_mode.h" 92 #include "radeon_reg.h" 93 94 /* 95 * Modules parameters. 96 */ 97 extern int radeon_no_wb; 98 extern int radeon_modeset; 99 extern int radeon_dynclks; 100 extern int radeon_r4xx_atom; 101 extern int radeon_agpmode; 102 extern int radeon_vram_limit; 103 extern int radeon_gart_size; 104 extern int radeon_benchmarking; 105 extern int radeon_testing; 106 extern int radeon_connector_table; 107 extern int radeon_tv; 108 extern int radeon_audio; 109 extern int radeon_disp_priority; 110 extern int radeon_hw_i2c; 111 extern int radeon_pcie_gen2; 112 extern int radeon_msi; 113 extern int radeon_lockup_timeout; 114 extern int radeon_fastfb; 115 extern int radeon_dpm; 116 extern int radeon_aspm; 117 extern int radeon_runtime_pm; 118 extern int radeon_hard_reset; 119 extern int radeon_vm_size; 120 extern int radeon_vm_block_size; 121 extern int radeon_deep_color; 122 extern int radeon_use_pflipirq; 123 extern int radeon_bapm; 124 extern int radeon_backlight; 125 extern int radeon_auxch; 126 extern int radeon_uvd; 127 extern int radeon_vce; 128 129 /* 130 * Copy from radeon_drv.h so we don't have to include both and have conflicting 131 * symbol; 132 */ 133 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 134 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 135 #define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */ 136 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 137 #define RADEON_IB_POOL_SIZE 16 138 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 139 #define RADEONFB_CONN_LIMIT 4 140 #define RADEON_BIOS_NUM_SCRATCH 8 141 142 /* internal ring indices */ 143 /* r1xx+ has gfx CP ring */ 144 #define RADEON_RING_TYPE_GFX_INDEX 0 145 146 /* cayman has 2 compute CP rings */ 147 #define CAYMAN_RING_TYPE_CP1_INDEX 1 148 #define CAYMAN_RING_TYPE_CP2_INDEX 2 149 150 /* R600+ has an async dma ring */ 151 #define R600_RING_TYPE_DMA_INDEX 3 152 /* cayman add a second async dma ring */ 153 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 154 155 /* R600+ */ 156 #define R600_RING_TYPE_UVD_INDEX 5 157 158 /* TN+ */ 159 #define TN_RING_TYPE_VCE1_INDEX 6 160 #define TN_RING_TYPE_VCE2_INDEX 7 161 162 /* max number of rings */ 163 #define RADEON_NUM_RINGS 8 164 165 /* number of hw syncs before falling back on blocking */ 166 #define RADEON_NUM_SYNCS 4 167 168 /* hardcode those limit for now */ 169 #define RADEON_VA_IB_OFFSET (1 << 20) 170 #define RADEON_VA_RESERVED_SIZE (8 << 20) 171 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 172 173 /* hard reset data */ 174 #define RADEON_ASIC_RESET_DATA 0x39d5e86b 175 176 /* reset flags */ 177 #define RADEON_RESET_GFX (1 << 0) 178 #define RADEON_RESET_COMPUTE (1 << 1) 179 #define RADEON_RESET_DMA (1 << 2) 180 #define RADEON_RESET_CP (1 << 3) 181 #define RADEON_RESET_GRBM (1 << 4) 182 #define RADEON_RESET_DMA1 (1 << 5) 183 #define RADEON_RESET_RLC (1 << 6) 184 #define RADEON_RESET_SEM (1 << 7) 185 #define RADEON_RESET_IH (1 << 8) 186 #define RADEON_RESET_VMC (1 << 9) 187 #define RADEON_RESET_MC (1 << 10) 188 #define RADEON_RESET_DISPLAY (1 << 11) 189 190 /* CG block flags */ 191 #define RADEON_CG_BLOCK_GFX (1 << 0) 192 #define RADEON_CG_BLOCK_MC (1 << 1) 193 #define RADEON_CG_BLOCK_SDMA (1 << 2) 194 #define RADEON_CG_BLOCK_UVD (1 << 3) 195 #define RADEON_CG_BLOCK_VCE (1 << 4) 196 #define RADEON_CG_BLOCK_HDP (1 << 5) 197 #define RADEON_CG_BLOCK_BIF (1 << 6) 198 199 /* CG flags */ 200 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 201 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 202 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 203 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 204 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 205 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 206 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 207 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 208 #define RADEON_CG_SUPPORT_MC_LS (1 << 8) 209 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 210 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 211 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 212 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 213 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 214 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 215 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 216 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 217 218 /* PG flags */ 219 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 220 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 221 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 222 #define RADEON_PG_SUPPORT_UVD (1 << 3) 223 #define RADEON_PG_SUPPORT_VCE (1 << 4) 224 #define RADEON_PG_SUPPORT_CP (1 << 5) 225 #define RADEON_PG_SUPPORT_GDS (1 << 6) 226 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 227 #define RADEON_PG_SUPPORT_SDMA (1 << 8) 228 #define RADEON_PG_SUPPORT_ACP (1 << 9) 229 #define RADEON_PG_SUPPORT_SAMU (1 << 10) 230 231 /* max cursor sizes (in pixels) */ 232 #define CURSOR_WIDTH 64 233 #define CURSOR_HEIGHT 64 234 235 #define CIK_CURSOR_WIDTH 128 236 #define CIK_CURSOR_HEIGHT 128 237 238 /* 239 * Errata workarounds. 240 */ 241 enum radeon_pll_errata { 242 CHIP_ERRATA_R300_CG = 0x00000001, 243 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 244 CHIP_ERRATA_PLL_DELAY = 0x00000004 245 }; 246 247 248 struct radeon_device; 249 250 251 /* 252 * BIOS. 253 */ 254 bool radeon_get_bios(struct radeon_device *rdev); 255 256 /* 257 * Dummy page 258 */ 259 struct radeon_dummy_page { 260 uint64_t entry; 261 struct drm_dma_handle *dmah; 262 dma_addr_t addr; 263 }; 264 int radeon_dummy_page_init(struct radeon_device *rdev); 265 void radeon_dummy_page_fini(struct radeon_device *rdev); 266 267 268 /* 269 * Clocks 270 */ 271 struct radeon_clock { 272 struct radeon_pll p1pll; 273 struct radeon_pll p2pll; 274 struct radeon_pll dcpll; 275 struct radeon_pll spll; 276 struct radeon_pll mpll; 277 /* 10 Khz units */ 278 uint32_t default_mclk; 279 uint32_t default_sclk; 280 uint32_t default_dispclk; 281 uint32_t current_dispclk; 282 uint32_t dp_extclk; 283 uint32_t max_pixel_clock; 284 uint32_t vco_freq; 285 }; 286 287 /* 288 * Power management 289 */ 290 int radeon_pm_init(struct radeon_device *rdev); 291 int radeon_pm_late_init(struct radeon_device *rdev); 292 void radeon_pm_fini(struct radeon_device *rdev); 293 void radeon_pm_compute_clocks(struct radeon_device *rdev); 294 void radeon_pm_suspend(struct radeon_device *rdev); 295 void radeon_pm_resume(struct radeon_device *rdev); 296 void radeon_combios_get_power_modes(struct radeon_device *rdev); 297 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 298 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 299 u8 clock_type, 300 u32 clock, 301 bool strobe_mode, 302 struct atom_clock_dividers *dividers); 303 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 304 u32 clock, 305 bool strobe_mode, 306 struct atom_mpll_param *mpll_param); 307 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 308 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 309 u16 voltage_level, u8 voltage_type, 310 u32 *gpio_value, u32 *gpio_mask); 311 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 312 u32 eng_clock, u32 mem_clock); 313 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 314 u8 voltage_type, u16 *voltage_step); 315 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 316 u16 voltage_id, u16 *voltage); 317 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 318 u16 *voltage, 319 u16 leakage_idx); 320 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 321 u16 *leakage_id); 322 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 323 u16 *vddc, u16 *vddci, 324 u16 virtual_voltage_id, 325 u16 vbios_voltage_id); 326 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 327 u16 virtual_voltage_id, 328 u16 *voltage); 329 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 330 u8 voltage_type, 331 u16 nominal_voltage, 332 u16 *true_voltage); 333 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 334 u8 voltage_type, u16 *min_voltage); 335 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 336 u8 voltage_type, u16 *max_voltage); 337 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 338 u8 voltage_type, u8 voltage_mode, 339 struct atom_voltage_table *voltage_table); 340 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 341 u8 voltage_type, u8 voltage_mode); 342 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 343 u8 voltage_type, 344 u8 *svd_gpio_id, u8 *svc_gpio_id); 345 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 346 u32 mem_clock); 347 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 348 u32 mem_clock); 349 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 350 u8 module_index, 351 struct atom_mc_reg_table *reg_table); 352 int radeon_atom_get_memory_info(struct radeon_device *rdev, 353 u8 module_index, struct atom_memory_info *mem_info); 354 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 355 bool gddr5, u8 module_index, 356 struct atom_memory_clock_range_table *mclk_range_table); 357 void rs690_pm_info(struct radeon_device *rdev); 358 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 359 unsigned *bankh, unsigned *mtaspect, 360 unsigned *tile_split); 361 362 /* 363 * Fences. 364 */ 365 struct radeon_fence_driver { 366 struct radeon_device *rdev; 367 uint32_t scratch_reg; 368 uint64_t gpu_addr; 369 volatile uint32_t *cpu_addr; 370 /* sync_seq is protected by ring emission lock */ 371 uint64_t sync_seq[RADEON_NUM_RINGS]; 372 atomic64_t last_seq; 373 bool initialized; 374 struct delayed_work lockup_work; 375 }; 376 377 struct radeon_fence { 378 struct radeon_device *rdev; 379 unsigned int kref; 380 /* protected by radeon_fence.lock */ 381 uint64_t seq; 382 /* RB, DMA, etc. */ 383 unsigned ring; 384 }; 385 386 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 387 int radeon_fence_driver_init(struct radeon_device *rdev); 388 void radeon_fence_driver_fini(struct radeon_device *rdev); 389 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); 390 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 391 void radeon_fence_process(struct radeon_device *rdev, int ring); 392 bool radeon_fence_signaled(struct radeon_fence *fence); 393 int radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, int timeout); 394 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 395 int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 396 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 397 int radeon_fence_wait_any(struct radeon_device *rdev, 398 struct radeon_fence **fences, 399 bool intr); 400 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 401 void radeon_fence_unref(struct radeon_fence **fence); 402 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 403 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 404 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 405 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 406 struct radeon_fence *b) 407 { 408 if (!a) { 409 return b; 410 } 411 412 if (!b) { 413 return a; 414 } 415 416 BUG_ON(a->ring != b->ring); 417 418 if (a->seq > b->seq) { 419 return a; 420 } else { 421 return b; 422 } 423 } 424 425 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 426 struct radeon_fence *b) 427 { 428 if (!a) { 429 return false; 430 } 431 432 if (!b) { 433 return true; 434 } 435 436 BUG_ON(a->ring != b->ring); 437 438 return a->seq < b->seq; 439 } 440 441 /* 442 * Tiling registers 443 */ 444 struct radeon_surface_reg { 445 struct radeon_bo *bo; 446 }; 447 448 #define RADEON_GEM_MAX_SURFACES 8 449 450 /* 451 * TTM. 452 */ 453 struct radeon_mman { 454 struct ttm_bo_global_ref bo_global_ref; 455 struct drm_global_reference mem_global_ref; 456 struct ttm_bo_device bdev; 457 bool mem_global_referenced; 458 bool initialized; 459 460 #if defined(CONFIG_DEBUG_FS) 461 struct dentry *vram; 462 struct dentry *gtt; 463 #endif 464 }; 465 466 struct radeon_bo_list { 467 struct radeon_bo *robj; 468 struct ttm_validate_buffer tv; 469 uint64_t gpu_offset; 470 unsigned prefered_domains; 471 unsigned allowed_domains; 472 uint32_t tiling_flags; 473 }; 474 475 /* bo virtual address in a specific vm */ 476 struct radeon_bo_va { 477 /* protected by bo being reserved */ 478 struct list_head bo_list; 479 uint64_t soffset; 480 uint64_t eoffset; 481 uint32_t flags; 482 uint64_t addr; 483 unsigned ref_count; 484 485 /* protected by vm mutex */ 486 struct list_head vm_list; 487 struct list_head vm_status; 488 489 /* constant after initialization */ 490 struct radeon_vm *vm; 491 struct radeon_bo *bo; 492 }; 493 494 struct radeon_bo { 495 /* Protected by gem.mutex */ 496 struct list_head list; 497 /* Protected by tbo.reserved */ 498 u32 initial_domain; 499 struct ttm_place placements[4]; 500 struct ttm_placement placement; 501 struct ttm_buffer_object tbo; 502 struct ttm_bo_kmap_obj kmap; 503 u32 flags; 504 unsigned pin_count; 505 void *kptr; 506 u32 tiling_flags; 507 u32 pitch; 508 int surface_reg; 509 /* list of all virtual address to which this bo 510 * is associated to 511 */ 512 struct list_head va; 513 /* Constant after initialization */ 514 struct radeon_device *rdev; 515 struct drm_gem_object gem_base; 516 517 struct ttm_bo_kmap_obj dma_buf_vmap; 518 pid_t pid; 519 }; 520 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 521 522 int radeon_gem_debugfs_init(struct radeon_device *rdev); 523 524 /* sub-allocation manager, it has to be protected by another lock. 525 * By conception this is an helper for other part of the driver 526 * like the indirect buffer or semaphore, which both have their 527 * locking. 528 * 529 * Principe is simple, we keep a list of sub allocation in offset 530 * order (first entry has offset == 0, last entry has the highest 531 * offset). 532 * 533 * When allocating new object we first check if there is room at 534 * the end total_size - (last_object_offset + last_object_size) >= 535 * alloc_size. If so we allocate new object there. 536 * 537 * When there is not enough room at the end, we start waiting for 538 * each sub object until we reach object_offset+object_size >= 539 * alloc_size, this object then become the sub object we return. 540 * 541 * Alignment can't be bigger than page size. 542 * 543 * Hole are not considered for allocation to keep things simple. 544 * Assumption is that there won't be hole (all object on same 545 * alignment). 546 */ 547 struct radeon_sa_manager { 548 struct cv wq; 549 struct lock wq_lock; 550 struct radeon_bo *bo; 551 struct list_head *hole; 552 struct list_head flist[RADEON_NUM_RINGS]; 553 struct list_head olist; 554 unsigned size; 555 u64 gpu_addr; 556 void *cpu_ptr; 557 uint32_t domain; 558 uint32_t align; 559 }; 560 561 struct radeon_sa_bo; 562 563 /* sub-allocation buffer */ 564 struct radeon_sa_bo { 565 struct list_head olist; 566 struct list_head flist; 567 struct radeon_sa_manager *manager; 568 unsigned soffset; 569 unsigned eoffset; 570 struct radeon_fence *fence; 571 }; 572 573 /* 574 * GEM objects. 575 */ 576 struct radeon_gem { 577 struct lock mutex; 578 struct list_head objects; 579 }; 580 581 int radeon_gem_init(struct radeon_device *rdev); 582 void radeon_gem_fini(struct radeon_device *rdev); 583 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, 584 int alignment, int initial_domain, 585 u32 flags, bool kernel, 586 struct drm_gem_object **obj); 587 588 int radeon_mode_dumb_create(struct drm_file *file_priv, 589 struct drm_device *dev, 590 struct drm_mode_create_dumb *args); 591 int radeon_mode_dumb_mmap(struct drm_file *filp, 592 struct drm_device *dev, 593 uint32_t handle, uint64_t *offset_p); 594 595 /* 596 * Semaphores. 597 */ 598 struct radeon_semaphore { 599 struct radeon_sa_bo *sa_bo; 600 signed waiters; 601 uint64_t gpu_addr; 602 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 603 }; 604 605 int radeon_semaphore_create(struct radeon_device *rdev, 606 struct radeon_semaphore **semaphore); 607 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 608 struct radeon_semaphore *semaphore); 609 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 610 struct radeon_semaphore *semaphore); 611 void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore, 612 struct radeon_fence *fence); 613 int radeon_semaphore_sync_rings(struct radeon_device *rdev, 614 struct radeon_semaphore *semaphore, 615 int waiting_ring); 616 void radeon_semaphore_free(struct radeon_device *rdev, 617 struct radeon_semaphore **semaphore, 618 struct radeon_fence *fence); 619 620 /* 621 * GART structures, functions & helpers 622 */ 623 struct radeon_mc; 624 625 #define RADEON_GPU_PAGE_SIZE 4096 626 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 627 #define RADEON_GPU_PAGE_SHIFT 12 628 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 629 630 #define RADEON_GART_PAGE_DUMMY 0 631 #define RADEON_GART_PAGE_VALID (1 << 0) 632 #define RADEON_GART_PAGE_READ (1 << 1) 633 #define RADEON_GART_PAGE_WRITE (1 << 2) 634 #define RADEON_GART_PAGE_SNOOP (1 << 3) 635 636 struct radeon_gart { 637 struct drm_dma_handle *dmah; 638 dma_addr_t table_addr; 639 struct radeon_bo *robj; 640 void *ptr; 641 unsigned num_gpu_pages; 642 unsigned num_cpu_pages; 643 unsigned table_size; 644 vm_page_t *pages; 645 uint64_t *pages_entry; 646 bool ready; 647 }; 648 649 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 650 void radeon_gart_table_ram_free(struct radeon_device *rdev); 651 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 652 void radeon_gart_table_vram_free(struct radeon_device *rdev); 653 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 654 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 655 int radeon_gart_init(struct radeon_device *rdev); 656 void radeon_gart_fini(struct radeon_device *rdev); 657 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 658 int pages); 659 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 660 int pages, vm_page_t *pagelist, 661 dma_addr_t *dma_addr, uint32_t flags); 662 663 664 /* 665 * GPU MC structures, functions & helpers 666 */ 667 struct radeon_mc { 668 resource_size_t aper_size; 669 resource_size_t aper_base; 670 resource_size_t agp_base; 671 /* for some chips with <= 32MB we need to lie 672 * about vram size near mc fb location */ 673 u64 mc_vram_size; 674 u64 visible_vram_size; 675 u64 gtt_size; 676 u64 gtt_start; 677 u64 gtt_end; 678 u64 vram_start; 679 u64 vram_end; 680 unsigned vram_width; 681 u64 real_vram_size; 682 int vram_mtrr; 683 bool vram_is_ddr; 684 bool igp_sideport_enabled; 685 u64 gtt_base_align; 686 u64 mc_mask; 687 }; 688 689 bool radeon_combios_sideport_present(struct radeon_device *rdev); 690 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 691 692 /* 693 * GPU scratch registers structures, functions & helpers 694 */ 695 struct radeon_scratch { 696 unsigned num_reg; 697 uint32_t reg_base; 698 bool free[32]; 699 uint32_t reg[32]; 700 }; 701 702 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 703 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 704 705 /* 706 * GPU doorbell structures, functions & helpers 707 */ 708 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 709 710 struct radeon_doorbell { 711 /* doorbell mmio */ 712 resource_size_t base; 713 resource_size_t size; 714 u32 __iomem *ptr; 715 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 716 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)]; 717 }; 718 719 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 720 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 721 722 /* 723 * IRQS. 724 */ 725 726 struct radeon_flip_work { 727 struct work_struct flip_work; 728 struct work_struct unpin_work; 729 struct radeon_device *rdev; 730 int crtc_id; 731 uint64_t base; 732 struct drm_pending_vblank_event *event; 733 struct radeon_bo *old_rbo; 734 struct radeon_fence *fence; 735 bool async; 736 }; 737 738 struct r500_irq_stat_regs { 739 u32 disp_int; 740 u32 hdmi0_status; 741 }; 742 743 struct r600_irq_stat_regs { 744 u32 disp_int; 745 u32 disp_int_cont; 746 u32 disp_int_cont2; 747 u32 d1grph_int; 748 u32 d2grph_int; 749 u32 hdmi0_status; 750 u32 hdmi1_status; 751 }; 752 753 struct evergreen_irq_stat_regs { 754 u32 disp_int; 755 u32 disp_int_cont; 756 u32 disp_int_cont2; 757 u32 disp_int_cont3; 758 u32 disp_int_cont4; 759 u32 disp_int_cont5; 760 u32 d1grph_int; 761 u32 d2grph_int; 762 u32 d3grph_int; 763 u32 d4grph_int; 764 u32 d5grph_int; 765 u32 d6grph_int; 766 u32 afmt_status1; 767 u32 afmt_status2; 768 u32 afmt_status3; 769 u32 afmt_status4; 770 u32 afmt_status5; 771 u32 afmt_status6; 772 }; 773 774 struct cik_irq_stat_regs { 775 u32 disp_int; 776 u32 disp_int_cont; 777 u32 disp_int_cont2; 778 u32 disp_int_cont3; 779 u32 disp_int_cont4; 780 u32 disp_int_cont5; 781 u32 disp_int_cont6; 782 u32 d1grph_int; 783 u32 d2grph_int; 784 u32 d3grph_int; 785 u32 d4grph_int; 786 u32 d5grph_int; 787 u32 d6grph_int; 788 }; 789 790 union radeon_irq_stat_regs { 791 struct r500_irq_stat_regs r500; 792 struct r600_irq_stat_regs r600; 793 struct evergreen_irq_stat_regs evergreen; 794 struct cik_irq_stat_regs cik; 795 }; 796 797 struct radeon_irq { 798 bool installed; 799 struct lock lock; 800 atomic_t ring_int[RADEON_NUM_RINGS]; 801 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 802 atomic_t pflip[RADEON_MAX_CRTCS]; 803 wait_queue_head_t vblank_queue; 804 bool hpd[RADEON_MAX_HPD_PINS]; 805 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 806 union radeon_irq_stat_regs stat_regs; 807 bool dpm_thermal; 808 }; 809 810 int radeon_irq_kms_init(struct radeon_device *rdev); 811 void radeon_irq_kms_fini(struct radeon_device *rdev); 812 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 813 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 814 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 815 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 816 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 817 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 818 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 819 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 820 821 /* 822 * CP & rings. 823 */ 824 825 struct radeon_ib { 826 struct radeon_sa_bo *sa_bo; 827 uint32_t length_dw; 828 uint64_t gpu_addr; 829 uint32_t *ptr; 830 int ring; 831 struct radeon_fence *fence; 832 struct radeon_vm *vm; 833 bool is_const_ib; 834 struct radeon_semaphore *semaphore; 835 }; 836 837 struct radeon_ring { 838 struct radeon_bo *ring_obj; 839 volatile uint32_t *ring; 840 unsigned rptr_offs; 841 unsigned rptr_save_reg; 842 u64 next_rptr_gpu_addr; 843 volatile u32 *next_rptr_cpu_addr; 844 unsigned wptr; 845 unsigned wptr_old; 846 unsigned ring_size; 847 unsigned ring_free_dw; 848 int count_dw; 849 atomic_t last_rptr; 850 atomic64_t last_activity; 851 uint64_t gpu_addr; 852 uint32_t align_mask; 853 uint32_t ptr_mask; 854 bool ready; 855 u32 nop; 856 u32 idx; 857 u64 last_semaphore_signal_addr; 858 u64 last_semaphore_wait_addr; 859 /* for CIK queues */ 860 u32 me; 861 u32 pipe; 862 u32 queue; 863 struct radeon_bo *mqd_obj; 864 u32 doorbell_index; 865 unsigned wptr_offs; 866 }; 867 868 struct radeon_mec { 869 struct radeon_bo *hpd_eop_obj; 870 u64 hpd_eop_gpu_addr; 871 u32 num_pipe; 872 u32 num_mec; 873 u32 num_queue; 874 }; 875 876 /* 877 * VM 878 */ 879 880 /* maximum number of VMIDs */ 881 #define RADEON_NUM_VM 16 882 883 /* number of entries in page table */ 884 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) 885 886 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 887 #define RADEON_VM_PTB_ALIGN_SIZE 32768 888 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 889 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 890 891 #define R600_PTE_VALID (1 << 0) 892 #define R600_PTE_SYSTEM (1 << 1) 893 #define R600_PTE_SNOOPED (1 << 2) 894 #define R600_PTE_READABLE (1 << 5) 895 #define R600_PTE_WRITEABLE (1 << 6) 896 897 /* PTE (Page Table Entry) fragment field for different page sizes */ 898 #define R600_PTE_FRAG_4KB (0 << 7) 899 #define R600_PTE_FRAG_64KB (4 << 7) 900 #define R600_PTE_FRAG_256KB (6 << 7) 901 902 /* flags needed to be set so we can copy directly from the GART table */ 903 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ 904 R600_PTE_SYSTEM | R600_PTE_VALID ) 905 906 struct radeon_vm_pt { 907 struct radeon_bo *bo; 908 uint64_t addr; 909 }; 910 911 struct radeon_vm { 912 struct list_head va; 913 unsigned id; 914 915 /* protecting invalidated and freed */ 916 struct spinlock status_lock; 917 918 /* BOs moved, but not yet updated in the PT */ 919 struct list_head invalidated; 920 921 /* BOs freed, but not yet updated in the PT */ 922 struct list_head freed; 923 924 /* contains the page directory */ 925 struct radeon_bo *page_directory; 926 uint64_t pd_gpu_addr; 927 unsigned max_pde_used; 928 929 /* array of page tables, one for each page directory entry */ 930 struct radeon_vm_pt *page_tables; 931 932 struct radeon_bo_va *ib_bo_va; 933 934 struct lock mutex; 935 struct radeon_fence *fence; 936 /* last flush or NULL if we still need to flush */ 937 struct radeon_fence *last_flush; 938 /* last use of vmid */ 939 struct radeon_fence *last_id_use; 940 }; 941 942 struct radeon_vm_manager { 943 struct radeon_fence *active[RADEON_NUM_VM]; 944 uint32_t max_pfn; 945 /* number of VMIDs */ 946 unsigned nvm; 947 /* vram base address for page table entry */ 948 u64 vram_base_offset; 949 /* is vm enabled? */ 950 bool enabled; 951 /* for hw to save the PD addr on suspend/resume */ 952 uint32_t saved_table_addr[RADEON_NUM_VM]; 953 }; 954 955 /* 956 * file private structure 957 */ 958 struct radeon_fpriv { 959 struct radeon_vm vm; 960 }; 961 962 /* 963 * R6xx+ IH ring 964 */ 965 struct r600_ih { 966 struct radeon_bo *ring_obj; 967 volatile uint32_t *ring; 968 unsigned rptr; 969 unsigned ring_size; 970 uint64_t gpu_addr; 971 uint32_t ptr_mask; 972 atomic_t lock; 973 bool enabled; 974 }; 975 976 /* 977 * RLC stuff 978 */ 979 #include "clearstate_defs.h" 980 981 struct radeon_rlc { 982 /* for power gating */ 983 struct radeon_bo *save_restore_obj; 984 u64 save_restore_gpu_addr; 985 volatile uint32_t *sr_ptr; 986 const u32 *reg_list; 987 u32 reg_list_size; 988 /* for clear state */ 989 struct radeon_bo *clear_state_obj; 990 u64 clear_state_gpu_addr; 991 volatile uint32_t *cs_ptr; 992 const struct cs_section_def *cs_data; 993 u32 clear_state_size; 994 /* for cp tables */ 995 struct radeon_bo *cp_table_obj; 996 u64 cp_table_gpu_addr; 997 volatile uint32_t *cp_table_ptr; 998 u32 cp_table_size; 999 }; 1000 1001 int radeon_ib_get(struct radeon_device *rdev, int ring, 1002 struct radeon_ib *ib, struct radeon_vm *vm, 1003 unsigned size); 1004 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 1005 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 1006 struct radeon_ib *const_ib, bool hdp_flush); 1007 int radeon_ib_pool_init(struct radeon_device *rdev); 1008 void radeon_ib_pool_fini(struct radeon_device *rdev); 1009 int radeon_ib_ring_tests(struct radeon_device *rdev); 1010 /* Ring access between begin & end cannot sleep */ 1011 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 1012 struct radeon_ring *ring); 1013 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 1014 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1015 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1016 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1017 bool hdp_flush); 1018 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1019 bool hdp_flush); 1020 void radeon_ring_undo(struct radeon_ring *ring); 1021 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 1022 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 1023 void radeon_ring_lockup_update(struct radeon_device *rdev, 1024 struct radeon_ring *ring); 1025 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 1026 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 1027 uint32_t **data); 1028 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 1029 unsigned size, uint32_t *data); 1030 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 1031 unsigned rptr_offs, u32 nop); 1032 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 1033 1034 1035 /* r600 async dma */ 1036 void r600_dma_stop(struct radeon_device *rdev); 1037 int r600_dma_resume(struct radeon_device *rdev); 1038 void r600_dma_fini(struct radeon_device *rdev); 1039 1040 void cayman_dma_stop(struct radeon_device *rdev); 1041 int cayman_dma_resume(struct radeon_device *rdev); 1042 void cayman_dma_fini(struct radeon_device *rdev); 1043 1044 /* 1045 * CS. 1046 */ 1047 struct radeon_cs_chunk { 1048 uint32_t chunk_id; 1049 uint32_t length_dw; 1050 uint32_t *kdata; 1051 void __user *user_ptr; 1052 }; 1053 1054 struct radeon_cs_parser { 1055 struct device *dev; 1056 struct radeon_device *rdev; 1057 struct drm_file *filp; 1058 /* chunks */ 1059 unsigned nchunks; 1060 struct radeon_cs_chunk *chunks; 1061 uint64_t *chunks_array; 1062 /* IB */ 1063 unsigned idx; 1064 /* relocations */ 1065 unsigned nrelocs; 1066 struct radeon_bo_list *relocs; 1067 struct radeon_bo_list **relocs_ptr; 1068 struct radeon_bo_list *vm_bos; 1069 struct list_head validated; 1070 unsigned dma_reloc_idx; 1071 /* indices of various chunks */ 1072 int chunk_ib_idx; 1073 int chunk_relocs_idx; 1074 int chunk_flags_idx; 1075 int chunk_const_ib_idx; 1076 struct radeon_ib ib; 1077 struct radeon_ib const_ib; 1078 void *track; 1079 unsigned family; 1080 int parser_error; 1081 u32 cs_flags; 1082 u32 ring; 1083 s32 priority; 1084 struct ww_acquire_ctx ticket; 1085 }; 1086 1087 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1088 { 1089 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 1090 1091 if (ibc->kdata) 1092 return ibc->kdata[idx]; 1093 return p->ib.ptr[idx]; 1094 } 1095 1096 1097 struct radeon_cs_packet { 1098 unsigned idx; 1099 unsigned type; 1100 unsigned reg; 1101 unsigned opcode; 1102 int count; 1103 unsigned one_reg_wr; 1104 }; 1105 1106 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1107 struct radeon_cs_packet *pkt, 1108 unsigned idx, unsigned reg); 1109 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 1110 struct radeon_cs_packet *pkt); 1111 1112 1113 /* 1114 * AGP 1115 */ 1116 int radeon_agp_init(struct radeon_device *rdev); 1117 void radeon_agp_resume(struct radeon_device *rdev); 1118 void radeon_agp_suspend(struct radeon_device *rdev); 1119 void radeon_agp_fini(struct radeon_device *rdev); 1120 1121 1122 /* 1123 * Writeback 1124 */ 1125 struct radeon_wb { 1126 struct radeon_bo *wb_obj; 1127 volatile uint32_t *wb; 1128 uint64_t gpu_addr; 1129 bool enabled; 1130 bool use_event; 1131 }; 1132 1133 #define RADEON_WB_SCRATCH_OFFSET 0 1134 #define RADEON_WB_RING0_NEXT_RPTR 256 1135 #define RADEON_WB_CP_RPTR_OFFSET 1024 1136 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1137 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1138 #define R600_WB_DMA_RPTR_OFFSET 1792 1139 #define R600_WB_IH_WPTR_OFFSET 2048 1140 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1141 #define R600_WB_EVENT_OFFSET 3072 1142 #define CIK_WB_CP1_WPTR_OFFSET 3328 1143 #define CIK_WB_CP2_WPTR_OFFSET 3584 1144 #define R600_WB_DMA_RING_TEST_OFFSET 3588 1145 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 1146 1147 /** 1148 * struct radeon_pm - power management datas 1149 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1150 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1151 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1152 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1153 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1154 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1155 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1156 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1157 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1158 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1159 * @needed_bandwidth: current bandwidth needs 1160 * 1161 * It keeps track of various data needed to take powermanagement decision. 1162 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1163 * Equation between gpu/memory clock and available bandwidth is hw dependent 1164 * (type of memory, bus size, efficiency, ...) 1165 */ 1166 1167 enum radeon_pm_method { 1168 PM_METHOD_PROFILE, 1169 PM_METHOD_DYNPM, 1170 PM_METHOD_DPM, 1171 }; 1172 1173 enum radeon_dynpm_state { 1174 DYNPM_STATE_DISABLED, 1175 DYNPM_STATE_MINIMUM, 1176 DYNPM_STATE_PAUSED, 1177 DYNPM_STATE_ACTIVE, 1178 DYNPM_STATE_SUSPENDED, 1179 }; 1180 enum radeon_dynpm_action { 1181 DYNPM_ACTION_NONE, 1182 DYNPM_ACTION_MINIMUM, 1183 DYNPM_ACTION_DOWNCLOCK, 1184 DYNPM_ACTION_UPCLOCK, 1185 DYNPM_ACTION_DEFAULT 1186 }; 1187 1188 enum radeon_voltage_type { 1189 VOLTAGE_NONE = 0, 1190 VOLTAGE_GPIO, 1191 VOLTAGE_VDDC, 1192 VOLTAGE_SW 1193 }; 1194 1195 enum radeon_pm_state_type { 1196 /* not used for dpm */ 1197 POWER_STATE_TYPE_DEFAULT, 1198 POWER_STATE_TYPE_POWERSAVE, 1199 /* user selectable states */ 1200 POWER_STATE_TYPE_BATTERY, 1201 POWER_STATE_TYPE_BALANCED, 1202 POWER_STATE_TYPE_PERFORMANCE, 1203 /* internal states */ 1204 POWER_STATE_TYPE_INTERNAL_UVD, 1205 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1206 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1207 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1208 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1209 POWER_STATE_TYPE_INTERNAL_BOOT, 1210 POWER_STATE_TYPE_INTERNAL_THERMAL, 1211 POWER_STATE_TYPE_INTERNAL_ACPI, 1212 POWER_STATE_TYPE_INTERNAL_ULV, 1213 POWER_STATE_TYPE_INTERNAL_3DPERF, 1214 }; 1215 1216 enum radeon_pm_profile_type { 1217 PM_PROFILE_DEFAULT, 1218 PM_PROFILE_AUTO, 1219 PM_PROFILE_LOW, 1220 PM_PROFILE_MID, 1221 PM_PROFILE_HIGH, 1222 }; 1223 1224 #define PM_PROFILE_DEFAULT_IDX 0 1225 #define PM_PROFILE_LOW_SH_IDX 1 1226 #define PM_PROFILE_MID_SH_IDX 2 1227 #define PM_PROFILE_HIGH_SH_IDX 3 1228 #define PM_PROFILE_LOW_MH_IDX 4 1229 #define PM_PROFILE_MID_MH_IDX 5 1230 #define PM_PROFILE_HIGH_MH_IDX 6 1231 #define PM_PROFILE_MAX 7 1232 1233 struct radeon_pm_profile { 1234 int dpms_off_ps_idx; 1235 int dpms_on_ps_idx; 1236 int dpms_off_cm_idx; 1237 int dpms_on_cm_idx; 1238 }; 1239 1240 enum radeon_int_thermal_type { 1241 THERMAL_TYPE_NONE, 1242 THERMAL_TYPE_EXTERNAL, 1243 THERMAL_TYPE_EXTERNAL_GPIO, 1244 THERMAL_TYPE_RV6XX, 1245 THERMAL_TYPE_RV770, 1246 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1247 THERMAL_TYPE_EVERGREEN, 1248 THERMAL_TYPE_SUMO, 1249 THERMAL_TYPE_NI, 1250 THERMAL_TYPE_SI, 1251 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1252 THERMAL_TYPE_CI, 1253 THERMAL_TYPE_KV, 1254 }; 1255 1256 struct radeon_voltage { 1257 enum radeon_voltage_type type; 1258 /* gpio voltage */ 1259 struct radeon_gpio_rec gpio; 1260 u32 delay; /* delay in usec from voltage drop to sclk change */ 1261 bool active_high; /* voltage drop is active when bit is high */ 1262 /* VDDC voltage */ 1263 u8 vddc_id; /* index into vddc voltage table */ 1264 u8 vddci_id; /* index into vddci voltage table */ 1265 bool vddci_enabled; 1266 /* r6xx+ sw */ 1267 u16 voltage; 1268 /* evergreen+ vddci */ 1269 u16 vddci; 1270 }; 1271 1272 /* clock mode flags */ 1273 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1274 1275 struct radeon_pm_clock_info { 1276 /* memory clock */ 1277 u32 mclk; 1278 /* engine clock */ 1279 u32 sclk; 1280 /* voltage info */ 1281 struct radeon_voltage voltage; 1282 /* standardized clock flags */ 1283 u32 flags; 1284 }; 1285 1286 /* state flags */ 1287 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1288 1289 struct radeon_power_state { 1290 enum radeon_pm_state_type type; 1291 struct radeon_pm_clock_info *clock_info; 1292 /* number of valid clock modes in this power state */ 1293 int num_clock_modes; 1294 struct radeon_pm_clock_info *default_clock_mode; 1295 /* standardized state flags */ 1296 u32 flags; 1297 u32 misc; /* vbios specific flags */ 1298 u32 misc2; /* vbios specific flags */ 1299 int pcie_lanes; /* pcie lanes */ 1300 }; 1301 1302 /* 1303 * Some modes are overclocked by very low value, accept them 1304 */ 1305 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1306 1307 enum radeon_dpm_auto_throttle_src { 1308 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1309 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1310 }; 1311 1312 enum radeon_dpm_event_src { 1313 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1314 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1315 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1316 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1317 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1318 }; 1319 1320 #define RADEON_MAX_VCE_LEVELS 6 1321 1322 enum radeon_vce_level { 1323 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1324 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1325 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1326 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1327 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1328 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1329 }; 1330 1331 struct radeon_ps { 1332 u32 caps; /* vbios flags */ 1333 u32 class; /* vbios flags */ 1334 u32 class2; /* vbios flags */ 1335 /* UVD clocks */ 1336 u32 vclk; 1337 u32 dclk; 1338 /* VCE clocks */ 1339 u32 evclk; 1340 u32 ecclk; 1341 bool vce_active; 1342 enum radeon_vce_level vce_level; 1343 /* asic priv */ 1344 void *ps_priv; 1345 }; 1346 1347 struct radeon_dpm_thermal { 1348 /* thermal interrupt work */ 1349 struct task work; 1350 /* low temperature threshold */ 1351 int min_temp; 1352 /* high temperature threshold */ 1353 int max_temp; 1354 /* was interrupt low to high or high to low */ 1355 bool high_to_low; 1356 }; 1357 1358 enum radeon_clk_action 1359 { 1360 RADEON_SCLK_UP = 1, 1361 RADEON_SCLK_DOWN 1362 }; 1363 1364 struct radeon_blacklist_clocks 1365 { 1366 u32 sclk; 1367 u32 mclk; 1368 enum radeon_clk_action action; 1369 }; 1370 1371 struct radeon_clock_and_voltage_limits { 1372 u32 sclk; 1373 u32 mclk; 1374 u16 vddc; 1375 u16 vddci; 1376 }; 1377 1378 struct radeon_clock_array { 1379 u32 count; 1380 u32 *values; 1381 }; 1382 1383 struct radeon_clock_voltage_dependency_entry { 1384 u32 clk; 1385 u16 v; 1386 }; 1387 1388 struct radeon_clock_voltage_dependency_table { 1389 u32 count; 1390 struct radeon_clock_voltage_dependency_entry *entries; 1391 }; 1392 1393 union radeon_cac_leakage_entry { 1394 struct { 1395 u16 vddc; 1396 u32 leakage; 1397 }; 1398 struct { 1399 u16 vddc1; 1400 u16 vddc2; 1401 u16 vddc3; 1402 }; 1403 }; 1404 1405 struct radeon_cac_leakage_table { 1406 u32 count; 1407 union radeon_cac_leakage_entry *entries; 1408 }; 1409 1410 struct radeon_phase_shedding_limits_entry { 1411 u16 voltage; 1412 u32 sclk; 1413 u32 mclk; 1414 }; 1415 1416 struct radeon_phase_shedding_limits_table { 1417 u32 count; 1418 struct radeon_phase_shedding_limits_entry *entries; 1419 }; 1420 1421 struct radeon_uvd_clock_voltage_dependency_entry { 1422 u32 vclk; 1423 u32 dclk; 1424 u16 v; 1425 }; 1426 1427 struct radeon_uvd_clock_voltage_dependency_table { 1428 u8 count; 1429 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1430 }; 1431 1432 struct radeon_vce_clock_voltage_dependency_entry { 1433 u32 ecclk; 1434 u32 evclk; 1435 u16 v; 1436 }; 1437 1438 struct radeon_vce_clock_voltage_dependency_table { 1439 u8 count; 1440 struct radeon_vce_clock_voltage_dependency_entry *entries; 1441 }; 1442 1443 struct radeon_ppm_table { 1444 u8 ppm_design; 1445 u16 cpu_core_number; 1446 u32 platform_tdp; 1447 u32 small_ac_platform_tdp; 1448 u32 platform_tdc; 1449 u32 small_ac_platform_tdc; 1450 u32 apu_tdp; 1451 u32 dgpu_tdp; 1452 u32 dgpu_ulv_power; 1453 u32 tj_max; 1454 }; 1455 1456 struct radeon_cac_tdp_table { 1457 u16 tdp; 1458 u16 configurable_tdp; 1459 u16 tdc; 1460 u16 battery_power_limit; 1461 u16 small_power_limit; 1462 u16 low_cac_leakage; 1463 u16 high_cac_leakage; 1464 u16 maximum_power_delivery_limit; 1465 }; 1466 1467 struct radeon_dpm_dynamic_state { 1468 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1469 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1470 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1471 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1472 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1473 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1474 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1475 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1476 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1477 struct radeon_clock_array valid_sclk_values; 1478 struct radeon_clock_array valid_mclk_values; 1479 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1480 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1481 u32 mclk_sclk_ratio; 1482 u32 sclk_mclk_delta; 1483 u16 vddc_vddci_delta; 1484 u16 min_vddc_for_pcie_gen2; 1485 struct radeon_cac_leakage_table cac_leakage_table; 1486 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1487 struct radeon_ppm_table *ppm_table; 1488 struct radeon_cac_tdp_table *cac_tdp_table; 1489 }; 1490 1491 struct radeon_dpm_fan { 1492 u16 t_min; 1493 u16 t_med; 1494 u16 t_high; 1495 u16 pwm_min; 1496 u16 pwm_med; 1497 u16 pwm_high; 1498 u8 t_hyst; 1499 u32 cycle_delay; 1500 u16 t_max; 1501 u8 control_mode; 1502 u16 default_max_fan_pwm; 1503 u16 default_fan_output_sensitivity; 1504 u16 fan_output_sensitivity; 1505 bool ucode_fan_control; 1506 }; 1507 1508 enum radeon_pcie_gen { 1509 RADEON_PCIE_GEN1 = 0, 1510 RADEON_PCIE_GEN2 = 1, 1511 RADEON_PCIE_GEN3 = 2, 1512 RADEON_PCIE_GEN_INVALID = 0xffff 1513 }; 1514 1515 enum radeon_dpm_forced_level { 1516 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1517 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1518 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1519 }; 1520 1521 struct radeon_vce_state { 1522 /* vce clocks */ 1523 u32 evclk; 1524 u32 ecclk; 1525 /* gpu clocks */ 1526 u32 sclk; 1527 u32 mclk; 1528 u8 clk_idx; 1529 u8 pstate; 1530 }; 1531 1532 struct radeon_dpm { 1533 struct radeon_ps *ps; 1534 /* number of valid power states */ 1535 int num_ps; 1536 /* current power state that is active */ 1537 struct radeon_ps *current_ps; 1538 /* requested power state */ 1539 struct radeon_ps *requested_ps; 1540 /* boot up power state */ 1541 struct radeon_ps *boot_ps; 1542 /* default uvd power state */ 1543 struct radeon_ps *uvd_ps; 1544 /* vce requirements */ 1545 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1546 enum radeon_vce_level vce_level; 1547 enum radeon_pm_state_type state; 1548 enum radeon_pm_state_type user_state; 1549 u32 platform_caps; 1550 u32 voltage_response_time; 1551 u32 backbias_response_time; 1552 void *priv; 1553 u32 new_active_crtcs; 1554 int new_active_crtc_count; 1555 u32 current_active_crtcs; 1556 int current_active_crtc_count; 1557 bool single_display; 1558 struct radeon_dpm_dynamic_state dyn_state; 1559 struct radeon_dpm_fan fan; 1560 u32 tdp_limit; 1561 u32 near_tdp_limit; 1562 u32 near_tdp_limit_adjusted; 1563 u32 sq_ramping_threshold; 1564 u32 cac_leakage; 1565 u16 tdp_od_limit; 1566 u32 tdp_adjustment; 1567 u16 load_line_slope; 1568 bool power_control; 1569 bool ac_power; 1570 /* special states active */ 1571 bool thermal_active; 1572 bool uvd_active; 1573 bool vce_active; 1574 /* thermal handling */ 1575 struct radeon_dpm_thermal thermal; 1576 /* forced levels */ 1577 enum radeon_dpm_forced_level forced_level; 1578 /* track UVD streams */ 1579 unsigned sd; 1580 unsigned hd; 1581 }; 1582 1583 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1584 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1585 1586 struct radeon_pm { 1587 struct lock mutex; 1588 /* write locked while reprogramming mclk */ 1589 struct lock mclk_lock; 1590 u32 active_crtcs; 1591 int active_crtc_count; 1592 int req_vblank; 1593 bool vblank_sync; 1594 fixed20_12 max_bandwidth; 1595 fixed20_12 igp_sideport_mclk; 1596 fixed20_12 igp_system_mclk; 1597 fixed20_12 igp_ht_link_clk; 1598 fixed20_12 igp_ht_link_width; 1599 fixed20_12 k8_bandwidth; 1600 fixed20_12 sideport_bandwidth; 1601 fixed20_12 ht_bandwidth; 1602 fixed20_12 core_bandwidth; 1603 fixed20_12 sclk; 1604 fixed20_12 mclk; 1605 fixed20_12 needed_bandwidth; 1606 struct radeon_power_state *power_state; 1607 /* number of valid power states */ 1608 int num_power_states; 1609 int current_power_state_index; 1610 int current_clock_mode_index; 1611 int requested_power_state_index; 1612 int requested_clock_mode_index; 1613 int default_power_state_index; 1614 u32 current_sclk; 1615 u32 current_mclk; 1616 u16 current_vddc; 1617 u16 current_vddci; 1618 u32 default_sclk; 1619 u32 default_mclk; 1620 u16 default_vddc; 1621 u16 default_vddci; 1622 struct radeon_i2c_chan *i2c_bus; 1623 /* selected pm method */ 1624 enum radeon_pm_method pm_method; 1625 /* dynpm power management */ 1626 struct delayed_work dynpm_idle_work; 1627 enum radeon_dynpm_state dynpm_state; 1628 enum radeon_dynpm_action dynpm_planned_action; 1629 unsigned long dynpm_action_timeout; 1630 bool dynpm_can_upclock; 1631 bool dynpm_can_downclock; 1632 /* profile-based power management */ 1633 enum radeon_pm_profile_type profile; 1634 int profile_index; 1635 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1636 /* internal thermal controller on rv6xx+ */ 1637 enum radeon_int_thermal_type int_thermal_type; 1638 struct ksensor *int_sensor; 1639 struct ksensordev *int_sensordev; 1640 /* fan control parameters */ 1641 bool no_fan; 1642 u8 fan_pulses_per_revolution; 1643 u8 fan_min_rpm; 1644 u8 fan_max_rpm; 1645 /* dpm */ 1646 bool dpm_enabled; 1647 bool sysfs_initialized; 1648 struct radeon_dpm dpm; 1649 }; 1650 1651 int radeon_pm_get_type_index(struct radeon_device *rdev, 1652 enum radeon_pm_state_type ps_type, 1653 int instance); 1654 /* 1655 * UVD 1656 */ 1657 #define RADEON_DEFAULT_UVD_HANDLES 10 1658 #define RADEON_MAX_UVD_HANDLES 30 1659 #define RADEON_UVD_STACK_SIZE (200*1024) 1660 #define RADEON_UVD_HEAP_SIZE (256*1024) 1661 #define RADEON_UVD_SESSION_SIZE (50*1024) 1662 1663 struct radeon_uvd { 1664 bool fw_header_present; 1665 struct radeon_bo *vcpu_bo; 1666 void *cpu_addr; 1667 u64 gpu_addr; 1668 unsigned max_handles; 1669 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1670 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1671 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1672 struct delayed_work idle_work; 1673 }; 1674 1675 int radeon_uvd_init(struct radeon_device *rdev); 1676 void radeon_uvd_fini(struct radeon_device *rdev); 1677 int radeon_uvd_suspend(struct radeon_device *rdev); 1678 int radeon_uvd_resume(struct radeon_device *rdev); 1679 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1680 uint32_t handle, struct radeon_fence **fence); 1681 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1682 uint32_t handle, struct radeon_fence **fence); 1683 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, 1684 uint32_t allowed_domains); 1685 void radeon_uvd_free_handles(struct radeon_device *rdev, 1686 struct drm_file *filp); 1687 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1688 void radeon_uvd_note_usage(struct radeon_device *rdev); 1689 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1690 unsigned vclk, unsigned dclk, 1691 unsigned vco_min, unsigned vco_max, 1692 unsigned fb_factor, unsigned fb_mask, 1693 unsigned pd_min, unsigned pd_max, 1694 unsigned pd_even, 1695 unsigned *optimal_fb_div, 1696 unsigned *optimal_vclk_div, 1697 unsigned *optimal_dclk_div); 1698 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1699 unsigned cg_upll_func_cntl); 1700 1701 /* 1702 * VCE 1703 */ 1704 #define RADEON_MAX_VCE_HANDLES 16 1705 1706 struct radeon_vce { 1707 struct radeon_bo *vcpu_bo; 1708 u64 gpu_addr; 1709 unsigned fw_version; 1710 unsigned fb_version; 1711 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1712 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1713 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1714 struct delayed_work idle_work; 1715 uint32_t keyselect; 1716 }; 1717 1718 int radeon_vce_init(struct radeon_device *rdev); 1719 void radeon_vce_fini(struct radeon_device *rdev); 1720 int radeon_vce_suspend(struct radeon_device *rdev); 1721 int radeon_vce_resume(struct radeon_device *rdev); 1722 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1723 uint32_t handle, struct radeon_fence **fence); 1724 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1725 uint32_t handle, struct radeon_fence **fence); 1726 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1727 void radeon_vce_note_usage(struct radeon_device *rdev); 1728 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1729 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1730 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1731 struct radeon_ring *ring, 1732 struct radeon_semaphore *semaphore, 1733 bool emit_wait); 1734 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1735 void radeon_vce_fence_emit(struct radeon_device *rdev, 1736 struct radeon_fence *fence); 1737 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1738 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1739 1740 struct r600_audio_pin { 1741 int channels; 1742 int rate; 1743 int bits_per_sample; 1744 u8 status_bits; 1745 u8 category_code; 1746 u32 offset; 1747 bool connected; 1748 u32 id; 1749 }; 1750 1751 struct r600_audio { 1752 bool enabled; 1753 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1754 int num_pins; 1755 struct radeon_audio_funcs *hdmi_funcs; 1756 struct radeon_audio_funcs *dp_funcs; 1757 struct radeon_audio_basic_funcs *funcs; 1758 }; 1759 1760 /* 1761 * Benchmarking 1762 */ 1763 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1764 1765 1766 /* 1767 * Testing 1768 */ 1769 void radeon_test_moves(struct radeon_device *rdev); 1770 void radeon_test_ring_sync(struct radeon_device *rdev, 1771 struct radeon_ring *cpA, 1772 struct radeon_ring *cpB); 1773 void radeon_test_syncing(struct radeon_device *rdev); 1774 1775 1776 /* 1777 * Debugfs 1778 */ 1779 struct radeon_debugfs { 1780 struct drm_info_list *files; 1781 unsigned num_files; 1782 }; 1783 1784 int radeon_debugfs_add_files(struct radeon_device *rdev, 1785 struct drm_info_list *files, 1786 unsigned nfiles); 1787 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1788 1789 /* 1790 * ASIC ring specific functions. 1791 */ 1792 struct radeon_asic_ring { 1793 /* ring read/write ptr handling */ 1794 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1795 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1796 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1797 1798 /* validating and patching of IBs */ 1799 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1800 int (*cs_parse)(struct radeon_cs_parser *p); 1801 1802 /* command emmit functions */ 1803 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1804 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1805 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); 1806 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1807 struct radeon_semaphore *semaphore, bool emit_wait); 1808 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring, 1809 unsigned vm_id, uint64_t pd_addr); 1810 1811 /* testing functions */ 1812 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1813 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1814 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1815 1816 /* deprecated */ 1817 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1818 }; 1819 1820 /* 1821 * ASIC specific functions. 1822 */ 1823 struct radeon_asic { 1824 int (*init)(struct radeon_device *rdev); 1825 void (*fini)(struct radeon_device *rdev); 1826 int (*resume)(struct radeon_device *rdev); 1827 int (*suspend)(struct radeon_device *rdev); 1828 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1829 int (*asic_reset)(struct radeon_device *rdev, bool hard); 1830 /* Flush the HDP cache via MMIO */ 1831 void (*mmio_hdp_flush)(struct radeon_device *rdev); 1832 /* check if 3D engine is idle */ 1833 bool (*gui_idle)(struct radeon_device *rdev); 1834 /* wait for mc_idle */ 1835 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1836 /* get the reference clock */ 1837 u32 (*get_xclk)(struct radeon_device *rdev); 1838 /* get the gpu clock counter */ 1839 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1840 /* get register for info ioctl */ 1841 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val); 1842 /* gart */ 1843 struct { 1844 void (*tlb_flush)(struct radeon_device *rdev); 1845 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags); 1846 void (*set_page)(struct radeon_device *rdev, unsigned i, 1847 uint64_t entry); 1848 } gart; 1849 struct { 1850 int (*init)(struct radeon_device *rdev); 1851 void (*fini)(struct radeon_device *rdev); 1852 void (*copy_pages)(struct radeon_device *rdev, 1853 struct radeon_ib *ib, 1854 uint64_t pe, uint64_t src, 1855 unsigned count); 1856 void (*write_pages)(struct radeon_device *rdev, 1857 struct radeon_ib *ib, 1858 uint64_t pe, 1859 uint64_t addr, unsigned count, 1860 uint32_t incr, uint32_t flags); 1861 void (*set_pages)(struct radeon_device *rdev, 1862 struct radeon_ib *ib, 1863 uint64_t pe, 1864 uint64_t addr, unsigned count, 1865 uint32_t incr, uint32_t flags); 1866 void (*pad_ib)(struct radeon_ib *ib); 1867 } vm; 1868 /* ring specific callbacks */ 1869 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1870 /* irqs */ 1871 struct { 1872 int (*set)(struct radeon_device *rdev); 1873 irqreturn_t (*process)(struct radeon_device *rdev); 1874 } irq; 1875 /* displays */ 1876 struct { 1877 /* display watermarks */ 1878 void (*bandwidth_update)(struct radeon_device *rdev); 1879 /* get frame count */ 1880 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1881 /* wait for vblank */ 1882 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1883 /* set backlight level */ 1884 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1885 /* get backlight level */ 1886 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1887 /* audio callbacks */ 1888 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1889 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1890 } display; 1891 /* copy functions for bo handling */ 1892 struct { 1893 int (*blit)(struct radeon_device *rdev, 1894 uint64_t src_offset, 1895 uint64_t dst_offset, 1896 unsigned num_gpu_pages, 1897 struct radeon_fence **fence); 1898 u32 blit_ring_index; 1899 int (*dma)(struct radeon_device *rdev, 1900 uint64_t src_offset, 1901 uint64_t dst_offset, 1902 unsigned num_gpu_pages, 1903 struct radeon_fence **fence); 1904 u32 dma_ring_index; 1905 /* method used for bo copy */ 1906 int (*copy)(struct radeon_device *rdev, 1907 uint64_t src_offset, 1908 uint64_t dst_offset, 1909 unsigned num_gpu_pages, 1910 struct radeon_fence **fence); 1911 /* ring used for bo copies */ 1912 u32 copy_ring_index; 1913 } copy; 1914 /* surfaces */ 1915 struct { 1916 int (*set_reg)(struct radeon_device *rdev, int reg, 1917 uint32_t tiling_flags, uint32_t pitch, 1918 uint32_t offset, uint32_t obj_size); 1919 void (*clear_reg)(struct radeon_device *rdev, int reg); 1920 } surface; 1921 /* hotplug detect */ 1922 struct { 1923 void (*init)(struct radeon_device *rdev); 1924 void (*fini)(struct radeon_device *rdev); 1925 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1926 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1927 } hpd; 1928 /* static power management */ 1929 struct { 1930 void (*misc)(struct radeon_device *rdev); 1931 void (*prepare)(struct radeon_device *rdev); 1932 void (*finish)(struct radeon_device *rdev); 1933 void (*init_profile)(struct radeon_device *rdev); 1934 void (*get_dynpm_state)(struct radeon_device *rdev); 1935 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1936 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1937 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1938 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1939 int (*get_pcie_lanes)(struct radeon_device *rdev); 1940 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1941 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1942 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 1943 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 1944 int (*get_temperature)(struct radeon_device *rdev); 1945 } pm; 1946 /* dynamic power management */ 1947 struct { 1948 int (*init)(struct radeon_device *rdev); 1949 void (*setup_asic)(struct radeon_device *rdev); 1950 int (*enable)(struct radeon_device *rdev); 1951 int (*late_enable)(struct radeon_device *rdev); 1952 void (*disable)(struct radeon_device *rdev); 1953 int (*pre_set_power_state)(struct radeon_device *rdev); 1954 int (*set_power_state)(struct radeon_device *rdev); 1955 void (*post_set_power_state)(struct radeon_device *rdev); 1956 void (*display_configuration_changed)(struct radeon_device *rdev); 1957 void (*fini)(struct radeon_device *rdev); 1958 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 1959 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 1960 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 1961 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 1962 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 1963 bool (*vblank_too_short)(struct radeon_device *rdev); 1964 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 1965 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 1966 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode); 1967 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev); 1968 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed); 1969 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed); 1970 u32 (*get_current_sclk)(struct radeon_device *rdev); 1971 u32 (*get_current_mclk)(struct radeon_device *rdev); 1972 } dpm; 1973 /* pageflipping */ 1974 struct { 1975 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async); 1976 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); 1977 } pflip; 1978 }; 1979 1980 /* 1981 * Asic structures 1982 */ 1983 struct r100_asic { 1984 const unsigned *reg_safe_bm; 1985 unsigned reg_safe_bm_size; 1986 u32 hdp_cntl; 1987 }; 1988 1989 struct r300_asic { 1990 const unsigned *reg_safe_bm; 1991 unsigned reg_safe_bm_size; 1992 u32 resync_scratch; 1993 u32 hdp_cntl; 1994 }; 1995 1996 struct r600_asic { 1997 unsigned max_pipes; 1998 unsigned max_tile_pipes; 1999 unsigned max_simds; 2000 unsigned max_backends; 2001 unsigned max_gprs; 2002 unsigned max_threads; 2003 unsigned max_stack_entries; 2004 unsigned max_hw_contexts; 2005 unsigned max_gs_threads; 2006 unsigned sx_max_export_size; 2007 unsigned sx_max_export_pos_size; 2008 unsigned sx_max_export_smx_size; 2009 unsigned sq_num_cf_insts; 2010 unsigned tiling_nbanks; 2011 unsigned tiling_npipes; 2012 unsigned tiling_group_size; 2013 unsigned tile_config; 2014 unsigned backend_map; 2015 unsigned active_simds; 2016 }; 2017 2018 struct rv770_asic { 2019 unsigned max_pipes; 2020 unsigned max_tile_pipes; 2021 unsigned max_simds; 2022 unsigned max_backends; 2023 unsigned max_gprs; 2024 unsigned max_threads; 2025 unsigned max_stack_entries; 2026 unsigned max_hw_contexts; 2027 unsigned max_gs_threads; 2028 unsigned sx_max_export_size; 2029 unsigned sx_max_export_pos_size; 2030 unsigned sx_max_export_smx_size; 2031 unsigned sq_num_cf_insts; 2032 unsigned sx_num_of_sets; 2033 unsigned sc_prim_fifo_size; 2034 unsigned sc_hiz_tile_fifo_size; 2035 unsigned sc_earlyz_tile_fifo_fize; 2036 unsigned tiling_nbanks; 2037 unsigned tiling_npipes; 2038 unsigned tiling_group_size; 2039 unsigned tile_config; 2040 unsigned backend_map; 2041 unsigned active_simds; 2042 }; 2043 2044 struct evergreen_asic { 2045 unsigned num_ses; 2046 unsigned max_pipes; 2047 unsigned max_tile_pipes; 2048 unsigned max_simds; 2049 unsigned max_backends; 2050 unsigned max_gprs; 2051 unsigned max_threads; 2052 unsigned max_stack_entries; 2053 unsigned max_hw_contexts; 2054 unsigned max_gs_threads; 2055 unsigned sx_max_export_size; 2056 unsigned sx_max_export_pos_size; 2057 unsigned sx_max_export_smx_size; 2058 unsigned sq_num_cf_insts; 2059 unsigned sx_num_of_sets; 2060 unsigned sc_prim_fifo_size; 2061 unsigned sc_hiz_tile_fifo_size; 2062 unsigned sc_earlyz_tile_fifo_size; 2063 unsigned tiling_nbanks; 2064 unsigned tiling_npipes; 2065 unsigned tiling_group_size; 2066 unsigned tile_config; 2067 unsigned backend_map; 2068 unsigned active_simds; 2069 }; 2070 2071 struct cayman_asic { 2072 unsigned max_shader_engines; 2073 unsigned max_pipes_per_simd; 2074 unsigned max_tile_pipes; 2075 unsigned max_simds_per_se; 2076 unsigned max_backends_per_se; 2077 unsigned max_texture_channel_caches; 2078 unsigned max_gprs; 2079 unsigned max_threads; 2080 unsigned max_gs_threads; 2081 unsigned max_stack_entries; 2082 unsigned sx_num_of_sets; 2083 unsigned sx_max_export_size; 2084 unsigned sx_max_export_pos_size; 2085 unsigned sx_max_export_smx_size; 2086 unsigned max_hw_contexts; 2087 unsigned sq_num_cf_insts; 2088 unsigned sc_prim_fifo_size; 2089 unsigned sc_hiz_tile_fifo_size; 2090 unsigned sc_earlyz_tile_fifo_size; 2091 2092 unsigned num_shader_engines; 2093 unsigned num_shader_pipes_per_simd; 2094 unsigned num_tile_pipes; 2095 unsigned num_simds_per_se; 2096 unsigned num_backends_per_se; 2097 unsigned backend_disable_mask_per_asic; 2098 unsigned backend_map; 2099 unsigned num_texture_channel_caches; 2100 unsigned mem_max_burst_length_bytes; 2101 unsigned mem_row_size_in_kb; 2102 unsigned shader_engine_tile_size; 2103 unsigned num_gpus; 2104 unsigned multi_gpu_tile_size; 2105 2106 unsigned tile_config; 2107 unsigned active_simds; 2108 }; 2109 2110 struct si_asic { 2111 unsigned max_shader_engines; 2112 unsigned max_tile_pipes; 2113 unsigned max_cu_per_sh; 2114 unsigned max_sh_per_se; 2115 unsigned max_backends_per_se; 2116 unsigned max_texture_channel_caches; 2117 unsigned max_gprs; 2118 unsigned max_gs_threads; 2119 unsigned max_hw_contexts; 2120 unsigned sc_prim_fifo_size_frontend; 2121 unsigned sc_prim_fifo_size_backend; 2122 unsigned sc_hiz_tile_fifo_size; 2123 unsigned sc_earlyz_tile_fifo_size; 2124 2125 unsigned num_tile_pipes; 2126 unsigned backend_enable_mask; 2127 unsigned backend_disable_mask_per_asic; 2128 unsigned backend_map; 2129 unsigned num_texture_channel_caches; 2130 unsigned mem_max_burst_length_bytes; 2131 unsigned mem_row_size_in_kb; 2132 unsigned shader_engine_tile_size; 2133 unsigned num_gpus; 2134 unsigned multi_gpu_tile_size; 2135 2136 unsigned tile_config; 2137 uint32_t tile_mode_array[32]; 2138 uint32_t active_cus; 2139 }; 2140 2141 struct cik_asic { 2142 unsigned max_shader_engines; 2143 unsigned max_tile_pipes; 2144 unsigned max_cu_per_sh; 2145 unsigned max_sh_per_se; 2146 unsigned max_backends_per_se; 2147 unsigned max_texture_channel_caches; 2148 unsigned max_gprs; 2149 unsigned max_gs_threads; 2150 unsigned max_hw_contexts; 2151 unsigned sc_prim_fifo_size_frontend; 2152 unsigned sc_prim_fifo_size_backend; 2153 unsigned sc_hiz_tile_fifo_size; 2154 unsigned sc_earlyz_tile_fifo_size; 2155 2156 unsigned num_tile_pipes; 2157 unsigned backend_enable_mask; 2158 unsigned backend_disable_mask_per_asic; 2159 unsigned backend_map; 2160 unsigned num_texture_channel_caches; 2161 unsigned mem_max_burst_length_bytes; 2162 unsigned mem_row_size_in_kb; 2163 unsigned shader_engine_tile_size; 2164 unsigned num_gpus; 2165 unsigned multi_gpu_tile_size; 2166 2167 unsigned tile_config; 2168 uint32_t tile_mode_array[32]; 2169 uint32_t macrotile_mode_array[16]; 2170 uint32_t active_cus; 2171 }; 2172 2173 union radeon_asic_config { 2174 struct r300_asic r300; 2175 struct r100_asic r100; 2176 struct r600_asic r600; 2177 struct rv770_asic rv770; 2178 struct evergreen_asic evergreen; 2179 struct cayman_asic cayman; 2180 struct si_asic si; 2181 struct cik_asic cik; 2182 }; 2183 2184 /* 2185 * asic initizalization from radeon_asic.c 2186 */ 2187 int radeon_asic_init(struct radeon_device *rdev); 2188 2189 2190 /* 2191 * IOCTL. 2192 */ 2193 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2194 struct drm_file *filp); 2195 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2196 struct drm_file *filp); 2197 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2198 struct drm_file *file_priv); 2199 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2200 struct drm_file *file_priv); 2201 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2202 struct drm_file *file_priv); 2203 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 2204 struct drm_file *file_priv); 2205 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2206 struct drm_file *filp); 2207 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2208 struct drm_file *filp); 2209 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2210 struct drm_file *filp); 2211 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2212 struct drm_file *filp); 2213 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2214 struct drm_file *filp); 2215 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2216 struct drm_file *filp); 2217 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2218 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2219 struct drm_file *filp); 2220 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2221 struct drm_file *filp); 2222 2223 /* VRAM scratch page for HDP bug, default vram page */ 2224 struct r600_vram_scratch { 2225 struct radeon_bo *robj; 2226 volatile uint32_t *ptr; 2227 u64 gpu_addr; 2228 }; 2229 2230 /* 2231 * ACPI 2232 */ 2233 struct radeon_atif_notification_cfg { 2234 bool enabled; 2235 int command_code; 2236 }; 2237 2238 struct radeon_atif_notifications { 2239 bool display_switch; 2240 bool expansion_mode_change; 2241 bool thermal_state; 2242 bool forced_power_state; 2243 bool system_power_state; 2244 bool display_conf_change; 2245 bool px_gfx_switch; 2246 bool brightness_change; 2247 bool dgpu_display_event; 2248 }; 2249 2250 struct radeon_atif_functions { 2251 bool system_params; 2252 bool sbios_requests; 2253 bool select_active_disp; 2254 bool lid_state; 2255 bool get_tv_standard; 2256 bool set_tv_standard; 2257 bool get_panel_expansion_mode; 2258 bool set_panel_expansion_mode; 2259 bool temperature_change; 2260 bool graphics_device_types; 2261 }; 2262 2263 struct radeon_atif { 2264 struct radeon_atif_notifications notifications; 2265 struct radeon_atif_functions functions; 2266 struct radeon_atif_notification_cfg notification_cfg; 2267 struct radeon_encoder *encoder_for_bl; 2268 }; 2269 2270 struct radeon_atcs_functions { 2271 bool get_ext_state; 2272 bool pcie_perf_req; 2273 bool pcie_dev_rdy; 2274 bool pcie_bus_width; 2275 }; 2276 2277 struct radeon_atcs { 2278 struct radeon_atcs_functions functions; 2279 }; 2280 2281 /* 2282 * Core structure, functions and helpers. 2283 */ 2284 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2285 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2286 2287 struct radeon_device { 2288 struct device *dev; 2289 struct drm_device *ddev; 2290 struct pci_dev *pdev; 2291 struct lock exclusive_lock; 2292 /* ASIC */ 2293 union radeon_asic_config config; 2294 enum radeon_family family; 2295 unsigned long flags; 2296 int usec_timeout; 2297 enum radeon_pll_errata pll_errata; 2298 int num_gb_pipes; 2299 int num_z_pipes; 2300 int disp_priority; 2301 /* BIOS */ 2302 uint8_t *bios; 2303 bool is_atom_bios; 2304 uint16_t bios_header_start; 2305 struct radeon_bo *stollen_vga_memory; 2306 /* Register mmio */ 2307 resource_size_t rmmio_base; 2308 resource_size_t rmmio_size; 2309 /* protects concurrent MM_INDEX/DATA based register access */ 2310 struct lock mmio_idx_lock; 2311 /* protects concurrent SMC based register access */ 2312 struct lock smc_idx_lock; 2313 /* protects concurrent PLL register access */ 2314 struct lock pll_idx_lock; 2315 /* protects concurrent MC register access */ 2316 struct lock mc_idx_lock; 2317 /* protects concurrent PCIE register access */ 2318 struct lock pcie_idx_lock; 2319 /* protects concurrent PCIE_PORT register access */ 2320 struct lock pciep_idx_lock; 2321 /* protects concurrent PIF register access */ 2322 struct lock pif_idx_lock; 2323 /* protects concurrent CG register access */ 2324 struct lock cg_idx_lock; 2325 /* protects concurrent UVD register access */ 2326 struct lock uvd_idx_lock; 2327 /* protects concurrent RCU register access */ 2328 struct lock rcu_idx_lock; 2329 /* protects concurrent DIDT register access */ 2330 struct lock didt_idx_lock; 2331 /* protects concurrent ENDPOINT (audio) register access */ 2332 struct lock end_idx_lock; 2333 int rmmio_rid; 2334 struct resource *rmmio; 2335 radeon_rreg_t mc_rreg; 2336 radeon_wreg_t mc_wreg; 2337 radeon_rreg_t pll_rreg; 2338 radeon_wreg_t pll_wreg; 2339 uint32_t pcie_reg_mask; 2340 radeon_rreg_t pciep_rreg; 2341 radeon_wreg_t pciep_wreg; 2342 /* io port */ 2343 int rio_rid; 2344 struct resource *rio_mem; 2345 resource_size_t rio_mem_size; 2346 struct radeon_clock clock; 2347 struct radeon_mc mc; 2348 struct radeon_gart gart; 2349 struct radeon_mode_info mode_info; 2350 struct radeon_scratch scratch; 2351 struct radeon_doorbell doorbell; 2352 struct radeon_mman mman; 2353 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2354 wait_queue_head_t fence_queue; 2355 struct lock ring_lock; 2356 struct radeon_ring ring[RADEON_NUM_RINGS]; 2357 bool ib_pool_ready; 2358 struct radeon_sa_manager ring_tmp_bo; 2359 struct radeon_irq irq; 2360 struct radeon_asic *asic; 2361 struct radeon_gem gem; 2362 struct radeon_pm pm; 2363 struct radeon_uvd uvd; 2364 struct radeon_vce vce; 2365 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2366 struct radeon_wb wb; 2367 struct radeon_dummy_page dummy_page; 2368 bool shutdown; 2369 bool suspend; 2370 bool need_dma32; 2371 bool accel_working; 2372 bool fastfb_working; /* IGP feature*/ 2373 bool needs_reset, in_reset; 2374 bool fictitious_range_registered; 2375 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2376 const struct firmware *me_fw; /* all family ME firmware */ 2377 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2378 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2379 const struct firmware *mc_fw; /* NI MC firmware */ 2380 const struct firmware *ce_fw; /* SI CE firmware */ 2381 const struct firmware *mec_fw; /* CIK MEC firmware */ 2382 const struct firmware *mec2_fw; /* KV MEC2 firmware */ 2383 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2384 const struct firmware *smc_fw; /* SMC firmware */ 2385 const struct firmware *uvd_fw; /* UVD firmware */ 2386 const struct firmware *vce_fw; /* VCE firmware */ 2387 bool new_fw; 2388 struct r600_vram_scratch vram_scratch; 2389 int msi_enabled; /* msi enabled */ 2390 struct r600_ih ih; /* r6/700 interrupt ring */ 2391 struct radeon_rlc rlc; 2392 struct radeon_mec mec; 2393 struct taskqueue *tq; 2394 struct task hotplug_work; 2395 struct work_struct dp_work; 2396 struct task audio_work; 2397 int num_crtc; /* number of crtcs */ 2398 struct lock dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2399 bool has_uvd; 2400 bool has_vce; 2401 struct r600_audio audio; /* audio stuff */ 2402 struct { 2403 ACPI_HANDLE handle; 2404 ACPI_NOTIFY_HANDLER notifier_call; 2405 } acpi; 2406 /* only one userspace can use Hyperz features or CMASK at a time */ 2407 struct drm_file *hyperz_filp; 2408 struct drm_file *cmask_filp; 2409 /* i2c buses */ 2410 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2411 /* debugfs */ 2412 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 2413 unsigned debugfs_count; 2414 /* virtual memory */ 2415 struct radeon_vm_manager vm_manager; 2416 struct lock gpu_clock_mutex; 2417 /* memory stats */ 2418 atomic64_t vram_usage; 2419 atomic64_t gtt_usage; 2420 atomic64_t num_bytes_moved; 2421 atomic_t gpu_reset_counter; 2422 /* ACPI interface */ 2423 struct radeon_atif atif; 2424 struct radeon_atcs atcs; 2425 /* srbm instance registers */ 2426 struct lock srbm_mutex; 2427 /* GRBM index mutex. Protects concurrents access to GRBM index */ 2428 struct lock grbm_idx_mutex; 2429 /* clock, powergating flags */ 2430 u32 cg_flags; 2431 u32 pg_flags; 2432 2433 #ifdef PM_TODO 2434 struct dev_pm_domain vga_pm_domain; 2435 #endif 2436 bool have_disp_power_ref; 2437 u32 px_quirk_flags; 2438 2439 /* tracking pinned memory */ 2440 u64 vram_pin_size; 2441 u64 gart_pin_size; 2442 }; 2443 2444 bool radeon_is_px(struct drm_device *dev); 2445 int radeon_device_init(struct radeon_device *rdev, 2446 struct drm_device *ddev, 2447 struct pci_dev *pdev, 2448 uint32_t flags); 2449 void radeon_device_fini(struct radeon_device *rdev); 2450 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2451 2452 #define RADEON_MIN_MMIO_SIZE 0x10000 2453 2454 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2455 bool always_indirect); 2456 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2457 bool always_indirect); 2458 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2459 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2460 2461 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2462 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2463 2464 /* 2465 * Cast helper 2466 */ 2467 #define to_radeon_fence(p) ((struct radeon_fence *)(p)) 2468 2469 /* 2470 * Registers read & write functions. 2471 */ 2472 #define RREG8(reg) bus_read_1((rdev->rmmio), (reg)) 2473 #define WREG8(reg, v) bus_write_1((rdev->rmmio), (reg), v) 2474 #define RREG16(reg) bus_read_2((rdev->rmmio), (reg)) 2475 #define WREG16(reg, v) bus_write_2((rdev->rmmio), (reg), v) 2476 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2477 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2478 #define DREG32(reg) DRM_INFO("REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) 2479 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2480 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2481 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2482 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2483 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2484 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2485 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2486 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2487 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2488 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2489 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2490 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2491 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2492 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2493 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2494 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2495 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2496 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2497 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2498 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2499 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2500 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2501 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2502 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2503 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2504 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2505 #define WREG32_P(reg, val, mask) \ 2506 do { \ 2507 uint32_t tmp_ = RREG32(reg); \ 2508 tmp_ &= (mask); \ 2509 tmp_ |= ((val) & ~(mask)); \ 2510 WREG32(reg, tmp_); \ 2511 } while (0) 2512 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2513 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2514 #define WREG32_PLL_P(reg, val, mask) \ 2515 do { \ 2516 uint32_t tmp_ = RREG32_PLL(reg); \ 2517 tmp_ &= (mask); \ 2518 tmp_ |= ((val) & ~(mask)); \ 2519 WREG32_PLL(reg, tmp_); \ 2520 } while (0) 2521 #define WREG32_SMC_P(reg, val, mask) \ 2522 do { \ 2523 uint32_t tmp_ = RREG32_SMC(reg); \ 2524 tmp_ &= (mask); \ 2525 tmp_ |= ((val) & ~(mask)); \ 2526 WREG32_SMC(reg, tmp_); \ 2527 } while (0) 2528 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2529 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2530 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2531 2532 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2533 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2534 2535 /* 2536 * Indirect registers accessors. 2537 * They used to be inlined, but this increases code size by ~65 kbytes. 2538 * Since each performs a pair of MMIO ops 2539 * within a spin_lock_irqsave/spin_unlock_irqrestore region, 2540 * the cost of call+ret is almost negligible. MMIO and locking 2541 * costs several dozens of cycles each at best, call+ret is ~5 cycles. 2542 */ 2543 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); 2544 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2545 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg); 2546 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2547 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg); 2548 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2549 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg); 2550 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2551 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg); 2552 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2553 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg); 2554 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2555 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg); 2556 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2557 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg); 2558 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2559 2560 void r100_pll_errata_after_index(struct radeon_device *rdev); 2561 2562 2563 /* 2564 * ASICs helpers. 2565 */ 2566 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2567 (rdev->pdev->device == 0x5969)) 2568 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2569 (rdev->family == CHIP_RV200) || \ 2570 (rdev->family == CHIP_RS100) || \ 2571 (rdev->family == CHIP_RS200) || \ 2572 (rdev->family == CHIP_RV250) || \ 2573 (rdev->family == CHIP_RV280) || \ 2574 (rdev->family == CHIP_RS300)) 2575 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2576 (rdev->family == CHIP_RV350) || \ 2577 (rdev->family == CHIP_R350) || \ 2578 (rdev->family == CHIP_RV380) || \ 2579 (rdev->family == CHIP_R420) || \ 2580 (rdev->family == CHIP_R423) || \ 2581 (rdev->family == CHIP_RV410) || \ 2582 (rdev->family == CHIP_RS400) || \ 2583 (rdev->family == CHIP_RS480)) 2584 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 2585 (rdev->ddev->pdev->device == 0x9443) || \ 2586 (rdev->ddev->pdev->device == 0x944B) || \ 2587 (rdev->ddev->pdev->device == 0x9506) || \ 2588 (rdev->ddev->pdev->device == 0x9509) || \ 2589 (rdev->ddev->pdev->device == 0x950F) || \ 2590 (rdev->ddev->pdev->device == 0x689C) || \ 2591 (rdev->ddev->pdev->device == 0x689D)) 2592 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2593 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2594 (rdev->family == CHIP_RS690) || \ 2595 (rdev->family == CHIP_RS740) || \ 2596 (rdev->family >= CHIP_R600)) 2597 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2598 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2599 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2600 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2601 (rdev->flags & RADEON_IS_IGP)) 2602 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2603 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2604 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2605 (rdev->flags & RADEON_IS_IGP)) 2606 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2607 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2608 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2609 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2610 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2611 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2612 (rdev->family == CHIP_MULLINS)) 2613 2614 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ 2615 (rdev->ddev->pdev->device == 0x6850) || \ 2616 (rdev->ddev->pdev->device == 0x6858) || \ 2617 (rdev->ddev->pdev->device == 0x6859) || \ 2618 (rdev->ddev->pdev->device == 0x6840) || \ 2619 (rdev->ddev->pdev->device == 0x6841) || \ 2620 (rdev->ddev->pdev->device == 0x6842) || \ 2621 (rdev->ddev->pdev->device == 0x6843)) 2622 2623 /* 2624 * BIOS helpers. 2625 */ 2626 #define RBIOS8(i) (rdev->bios[i]) 2627 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2628 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2629 2630 int radeon_combios_init(struct radeon_device *rdev); 2631 void radeon_combios_fini(struct radeon_device *rdev); 2632 int radeon_atombios_init(struct radeon_device *rdev); 2633 void radeon_atombios_fini(struct radeon_device *rdev); 2634 2635 2636 /* 2637 * RING helpers. 2638 */ 2639 2640 /** 2641 * radeon_ring_write - write a value to the ring 2642 * 2643 * @ring: radeon_ring structure holding ring information 2644 * @v: dword (dw) value to write 2645 * 2646 * Write a value to the requested ring buffer (all asics). 2647 */ 2648 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2649 { 2650 if (ring->count_dw <= 0) 2651 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); 2652 2653 ring->ring[ring->wptr++] = v; 2654 ring->wptr &= ring->ptr_mask; 2655 ring->count_dw--; 2656 ring->ring_free_dw--; 2657 } 2658 2659 /* 2660 * ASICs macro. 2661 */ 2662 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2663 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2664 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2665 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2666 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2667 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2668 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false) 2669 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2670 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f)) 2671 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e)) 2672 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2673 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2674 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) 2675 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2676 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2677 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) 2678 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2679 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2680 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2681 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2682 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2683 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2684 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr)) 2685 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2686 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2687 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2688 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2689 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2690 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2691 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2692 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2693 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2694 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2695 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2696 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2697 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) 2698 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) 2699 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) 2700 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2701 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2702 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2703 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2704 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2705 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2706 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2707 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2708 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2709 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2710 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2711 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2712 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2713 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2714 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2715 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2716 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2717 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2718 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2719 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2720 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2721 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2722 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2723 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2724 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2725 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2726 #define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async)) 2727 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) 2728 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2729 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2730 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2731 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2732 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v)) 2733 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2734 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2735 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2736 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2737 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2738 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2739 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2740 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2741 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2742 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2743 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2744 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2745 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2746 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2747 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2748 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2749 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2750 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2751 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev)) 2752 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev)) 2753 2754 /* Common functions */ 2755 /* AGP */ 2756 extern int radeon_gpu_reset(struct radeon_device *rdev); 2757 extern void radeon_pci_config_reset(struct radeon_device *rdev); 2758 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2759 extern void radeon_agp_disable(struct radeon_device *rdev); 2760 extern int radeon_modeset_init(struct radeon_device *rdev); 2761 extern void radeon_modeset_fini(struct radeon_device *rdev); 2762 extern bool radeon_card_posted(struct radeon_device *rdev); 2763 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2764 extern void radeon_update_display_priority(struct radeon_device *rdev); 2765 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2766 extern void radeon_scratch_init(struct radeon_device *rdev); 2767 extern void radeon_wb_fini(struct radeon_device *rdev); 2768 extern int radeon_wb_init(struct radeon_device *rdev); 2769 extern void radeon_wb_disable(struct radeon_device *rdev); 2770 extern void radeon_surface_init(struct radeon_device *rdev); 2771 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2772 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2773 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2774 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2775 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2776 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2777 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, 2778 bool fbcon, bool freeze); 2779 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2780 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2781 const u32 *registers, 2782 const u32 array_size); 2783 2784 /* 2785 * vm 2786 */ 2787 int radeon_vm_manager_init(struct radeon_device *rdev); 2788 void radeon_vm_manager_fini(struct radeon_device *rdev); 2789 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2790 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2791 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, 2792 struct radeon_vm *vm, 2793 struct list_head *head); 2794 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2795 struct radeon_vm *vm, int ring); 2796 void radeon_vm_flush(struct radeon_device *rdev, 2797 struct radeon_vm *vm, 2798 int ring); 2799 void radeon_vm_fence(struct radeon_device *rdev, 2800 struct radeon_vm *vm, 2801 struct radeon_fence *fence); 2802 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2803 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2804 struct radeon_vm *vm); 2805 int radeon_vm_clear_freed(struct radeon_device *rdev, 2806 struct radeon_vm *vm); 2807 int radeon_vm_clear_invalids(struct radeon_device *rdev, 2808 struct radeon_vm *vm); 2809 int radeon_vm_bo_update(struct radeon_device *rdev, 2810 struct radeon_bo_va *bo_va, 2811 struct ttm_mem_reg *mem); 2812 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2813 struct radeon_bo *bo); 2814 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2815 struct radeon_bo *bo); 2816 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2817 struct radeon_vm *vm, 2818 struct radeon_bo *bo); 2819 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2820 struct radeon_bo_va *bo_va, 2821 uint64_t offset, 2822 uint32_t flags); 2823 void radeon_vm_bo_rmv(struct radeon_device *rdev, 2824 struct radeon_bo_va *bo_va); 2825 2826 /* audio */ 2827 void r600_audio_update_hdmi(void *arg, int pending); 2828 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2829 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2830 void r600_audio_enable(struct radeon_device *rdev, 2831 struct r600_audio_pin *pin, 2832 u8 enable_mask); 2833 void dce6_audio_enable(struct radeon_device *rdev, 2834 struct r600_audio_pin *pin, 2835 u8 enable_mask); 2836 2837 /* 2838 * R600 vram scratch functions 2839 */ 2840 int r600_vram_scratch_init(struct radeon_device *rdev); 2841 void r600_vram_scratch_fini(struct radeon_device *rdev); 2842 2843 /* 2844 * r600 cs checking helper 2845 */ 2846 unsigned r600_mip_minify(unsigned size, unsigned level); 2847 bool r600_fmt_is_valid_color(u32 format); 2848 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2849 int r600_fmt_get_blocksize(u32 format); 2850 int r600_fmt_get_nblocksx(u32 format, u32 w); 2851 int r600_fmt_get_nblocksy(u32 format, u32 h); 2852 2853 /* 2854 * r600 functions used by radeon_encoder.c 2855 */ 2856 struct radeon_hdmi_acr { 2857 u32 clock; 2858 2859 int n_32khz; 2860 int cts_32khz; 2861 2862 int n_44_1khz; 2863 int cts_44_1khz; 2864 2865 int n_48khz; 2866 int cts_48khz; 2867 2868 }; 2869 2870 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 2871 2872 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 2873 u32 tiling_pipe_num, 2874 u32 max_rb_num, 2875 u32 total_max_rb_num, 2876 u32 enabled_rb_mask); 2877 2878 /* 2879 * evergreen functions used by radeon_encoder.c 2880 */ 2881 2882 extern int ni_init_microcode(struct radeon_device *rdev); 2883 extern int ni_mc_load_microcode(struct radeon_device *rdev); 2884 extern void ni_fini_microcode(struct radeon_device *rdev); 2885 2886 /* radeon_acpi.c */ 2887 extern int radeon_acpi_init(struct radeon_device *rdev); 2888 extern void radeon_acpi_fini(struct radeon_device *rdev); 2889 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 2890 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 2891 u8 perf_req, bool advertise); 2892 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 2893 2894 /* Prototypes added by @dumbbell. */ 2895 2896 /* atombios_encoders.c */ 2897 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 2898 struct drm_connector *drm_connector); 2899 void radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, 2900 uint32_t supported_device, u16 caps); 2901 2902 /* radeon_atombios.c */ 2903 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 2904 struct drm_display_mode *mode); 2905 2906 /* radeon_legacy_encoders.c */ 2907 void radeon_add_legacy_encoder(struct drm_device *dev, 2908 uint32_t encoder_enum, uint32_t supported_device); 2909 void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder, 2910 struct drm_connector *drm_connector); 2911 2912 /* radeon_pm.c */ 2913 void radeon_pm_acpi_event_handler(struct radeon_device *rdev); 2914 2915 /* radeon_ttm.c */ 2916 int radeon_ttm_init(struct radeon_device *rdev); 2917 void radeon_ttm_fini(struct radeon_device *rdev); 2918 2919 /* r600.c */ 2920 int r600_ih_ring_alloc(struct radeon_device *rdev); 2921 void r600_ih_ring_fini(struct radeon_device *rdev); 2922 2923 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 2924 struct radeon_cs_packet *pkt, 2925 unsigned idx); 2926 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 2927 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 2928 struct radeon_cs_packet *pkt); 2929 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 2930 struct radeon_bo_list **cs_reloc, 2931 int nomm); 2932 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 2933 uint32_t *vline_start_end, 2934 uint32_t *vline_status); 2935 2936 #include "radeon_object.h" 2937 2938 #endif 2939