1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #ifndef __RADEON_H__ 30 #define __RADEON_H__ 31 32 /* TODO: Here are things that needs to be done : 33 * - surface allocator & initializer : (bit like scratch reg) should 34 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 35 * related to surface 36 * - WB : write back stuff (do it bit like scratch reg things) 37 * - Vblank : look at Jesse's rework and what we should do 38 * - r600/r700: gart & cp 39 * - cs : clean cs ioctl use bitmap & things like that. 40 * - power management stuff 41 * - Barrier in gart code 42 * - Unmappabled vram ? 43 * - TESTING, TESTING, TESTING 44 */ 45 46 /* Initialization path: 47 * We expect that acceleration initialization might fail for various 48 * reasons even thought we work hard to make it works on most 49 * configurations. In order to still have a working userspace in such 50 * situation the init path must succeed up to the memory controller 51 * initialization point. Failure before this point are considered as 52 * fatal error. Here is the init callchain : 53 * radeon_device_init perform common structure, mutex initialization 54 * asic_init setup the GPU memory layout and perform all 55 * one time initialization (failure in this 56 * function are considered fatal) 57 * asic_startup setup the GPU acceleration, in order to 58 * follow guideline the first thing this 59 * function should do is setting the GPU 60 * memory controller (only MC setup failure 61 * are considered as fatal) 62 */ 63 64 #include <sys/condvar.h> 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/linker.h> 68 #include <linux/firmware.h> 69 #include <linux/seq_file.h> 70 71 #include <contrib/dev/acpica/source/include/acpi.h> 72 #include <dev/acpica/acpivar.h> 73 74 #include <linux/atomic.h> 75 #include <linux/wait.h> 76 #include <linux/list.h> 77 #include <linux/kref.h> 78 #include <linux/hashtable.h> 79 #include <linux/fence.h> 80 81 #include <drm/ttm/ttm_bo_api.h> 82 #include <drm/ttm/ttm_bo_driver.h> 83 #include <drm/ttm/ttm_placement.h> 84 #include <drm/ttm/ttm_module.h> 85 #include <drm/ttm/ttm_execbuf_util.h> 86 87 #include <drm/drm_gem.h> 88 #define CONFIG_ACPI 1 89 90 #include "radeon_family.h" 91 #include "radeon_mode.h" 92 #include "radeon_reg.h" 93 94 /* 95 * Modules parameters. 96 */ 97 extern int radeon_no_wb; 98 extern int radeon_modeset; 99 extern int radeon_dynclks; 100 extern int radeon_r4xx_atom; 101 extern int radeon_agpmode; 102 extern int radeon_vram_limit; 103 extern int radeon_gart_size; 104 extern int radeon_benchmarking; 105 extern int radeon_testing; 106 extern int radeon_connector_table; 107 extern int radeon_tv; 108 extern int radeon_audio; 109 extern int radeon_disp_priority; 110 extern int radeon_hw_i2c; 111 extern int radeon_pcie_gen2; 112 extern int radeon_msi; 113 extern int radeon_lockup_timeout; 114 extern int radeon_fastfb; 115 extern int radeon_dpm; 116 extern int radeon_aspm; 117 extern int radeon_runtime_pm; 118 extern int radeon_hard_reset; 119 extern int radeon_vm_size; 120 extern int radeon_vm_block_size; 121 extern int radeon_deep_color; 122 extern int radeon_use_pflipirq; 123 extern int radeon_bapm; 124 extern int radeon_backlight; 125 126 /* 127 * Copy from radeon_drv.h so we don't have to include both and have conflicting 128 * symbol; 129 */ 130 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 131 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 132 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 133 #define RADEON_IB_POOL_SIZE 16 134 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 135 #define RADEONFB_CONN_LIMIT 4 136 #define RADEON_BIOS_NUM_SCRATCH 8 137 138 /* internal ring indices */ 139 /* r1xx+ has gfx CP ring */ 140 #define RADEON_RING_TYPE_GFX_INDEX 0 141 142 /* cayman has 2 compute CP rings */ 143 #define CAYMAN_RING_TYPE_CP1_INDEX 1 144 #define CAYMAN_RING_TYPE_CP2_INDEX 2 145 146 /* R600+ has an async dma ring */ 147 #define R600_RING_TYPE_DMA_INDEX 3 148 /* cayman add a second async dma ring */ 149 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 150 151 /* R600+ */ 152 #define R600_RING_TYPE_UVD_INDEX 5 153 154 /* TN+ */ 155 #define TN_RING_TYPE_VCE1_INDEX 6 156 #define TN_RING_TYPE_VCE2_INDEX 7 157 158 /* max number of rings */ 159 #define RADEON_NUM_RINGS 8 160 161 /* number of hw syncs before falling back on blocking */ 162 #define RADEON_NUM_SYNCS 4 163 164 /* hardcode those limit for now */ 165 #define RADEON_VA_IB_OFFSET (1 << 20) 166 #define RADEON_VA_RESERVED_SIZE (8 << 20) 167 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 168 169 /* hard reset data */ 170 #define RADEON_ASIC_RESET_DATA 0x39d5e86b 171 172 /* reset flags */ 173 #define RADEON_RESET_GFX (1 << 0) 174 #define RADEON_RESET_COMPUTE (1 << 1) 175 #define RADEON_RESET_DMA (1 << 2) 176 #define RADEON_RESET_CP (1 << 3) 177 #define RADEON_RESET_GRBM (1 << 4) 178 #define RADEON_RESET_DMA1 (1 << 5) 179 #define RADEON_RESET_RLC (1 << 6) 180 #define RADEON_RESET_SEM (1 << 7) 181 #define RADEON_RESET_IH (1 << 8) 182 #define RADEON_RESET_VMC (1 << 9) 183 #define RADEON_RESET_MC (1 << 10) 184 #define RADEON_RESET_DISPLAY (1 << 11) 185 186 /* CG block flags */ 187 #define RADEON_CG_BLOCK_GFX (1 << 0) 188 #define RADEON_CG_BLOCK_MC (1 << 1) 189 #define RADEON_CG_BLOCK_SDMA (1 << 2) 190 #define RADEON_CG_BLOCK_UVD (1 << 3) 191 #define RADEON_CG_BLOCK_VCE (1 << 4) 192 #define RADEON_CG_BLOCK_HDP (1 << 5) 193 #define RADEON_CG_BLOCK_BIF (1 << 6) 194 195 /* CG flags */ 196 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 197 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 198 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 199 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 200 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 201 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 202 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 203 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 204 #define RADEON_CG_SUPPORT_MC_LS (1 << 8) 205 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 206 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 207 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 208 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 209 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 210 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 211 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 212 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 213 214 /* PG flags */ 215 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 216 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 217 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 218 #define RADEON_PG_SUPPORT_UVD (1 << 3) 219 #define RADEON_PG_SUPPORT_VCE (1 << 4) 220 #define RADEON_PG_SUPPORT_CP (1 << 5) 221 #define RADEON_PG_SUPPORT_GDS (1 << 6) 222 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 223 #define RADEON_PG_SUPPORT_SDMA (1 << 8) 224 #define RADEON_PG_SUPPORT_ACP (1 << 9) 225 #define RADEON_PG_SUPPORT_SAMU (1 << 10) 226 227 /* max cursor sizes (in pixels) */ 228 #define CURSOR_WIDTH 64 229 #define CURSOR_HEIGHT 64 230 231 #define CIK_CURSOR_WIDTH 128 232 #define CIK_CURSOR_HEIGHT 128 233 234 /* 235 * Errata workarounds. 236 */ 237 enum radeon_pll_errata { 238 CHIP_ERRATA_R300_CG = 0x00000001, 239 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 240 CHIP_ERRATA_PLL_DELAY = 0x00000004 241 }; 242 243 244 struct radeon_device; 245 246 247 /* 248 * BIOS. 249 */ 250 bool radeon_get_bios(struct radeon_device *rdev); 251 252 /* 253 * Dummy page 254 */ 255 struct radeon_dummy_page { 256 drm_dma_handle_t *dmah; 257 dma_addr_t addr; 258 }; 259 int radeon_dummy_page_init(struct radeon_device *rdev); 260 void radeon_dummy_page_fini(struct radeon_device *rdev); 261 262 263 /* 264 * Clocks 265 */ 266 struct radeon_clock { 267 struct radeon_pll p1pll; 268 struct radeon_pll p2pll; 269 struct radeon_pll dcpll; 270 struct radeon_pll spll; 271 struct radeon_pll mpll; 272 /* 10 Khz units */ 273 uint32_t default_mclk; 274 uint32_t default_sclk; 275 uint32_t default_dispclk; 276 uint32_t current_dispclk; 277 uint32_t dp_extclk; 278 uint32_t max_pixel_clock; 279 }; 280 281 /* 282 * Power management 283 */ 284 int radeon_pm_init(struct radeon_device *rdev); 285 int radeon_pm_late_init(struct radeon_device *rdev); 286 void radeon_pm_fini(struct radeon_device *rdev); 287 void radeon_pm_compute_clocks(struct radeon_device *rdev); 288 void radeon_pm_suspend(struct radeon_device *rdev); 289 void radeon_pm_resume(struct radeon_device *rdev); 290 void radeon_combios_get_power_modes(struct radeon_device *rdev); 291 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 292 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 293 u8 clock_type, 294 u32 clock, 295 bool strobe_mode, 296 struct atom_clock_dividers *dividers); 297 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 298 u32 clock, 299 bool strobe_mode, 300 struct atom_mpll_param *mpll_param); 301 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 302 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 303 u16 voltage_level, u8 voltage_type, 304 u32 *gpio_value, u32 *gpio_mask); 305 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 306 u32 eng_clock, u32 mem_clock); 307 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 308 u8 voltage_type, u16 *voltage_step); 309 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 310 u16 voltage_id, u16 *voltage); 311 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 312 u16 *voltage, 313 u16 leakage_idx); 314 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 315 u16 *leakage_id); 316 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 317 u16 *vddc, u16 *vddci, 318 u16 virtual_voltage_id, 319 u16 vbios_voltage_id); 320 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 321 u16 virtual_voltage_id, 322 u16 *voltage); 323 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 324 u8 voltage_type, 325 u16 nominal_voltage, 326 u16 *true_voltage); 327 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 328 u8 voltage_type, u16 *min_voltage); 329 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 330 u8 voltage_type, u16 *max_voltage); 331 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 332 u8 voltage_type, u8 voltage_mode, 333 struct atom_voltage_table *voltage_table); 334 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 335 u8 voltage_type, u8 voltage_mode); 336 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 337 u8 voltage_type, 338 u8 *svd_gpio_id, u8 *svc_gpio_id); 339 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 340 u32 mem_clock); 341 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 342 u32 mem_clock); 343 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 344 u8 module_index, 345 struct atom_mc_reg_table *reg_table); 346 int radeon_atom_get_memory_info(struct radeon_device *rdev, 347 u8 module_index, struct atom_memory_info *mem_info); 348 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 349 bool gddr5, u8 module_index, 350 struct atom_memory_clock_range_table *mclk_range_table); 351 void rs690_pm_info(struct radeon_device *rdev); 352 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 353 unsigned *bankh, unsigned *mtaspect, 354 unsigned *tile_split); 355 356 /* 357 * Fences. 358 */ 359 struct radeon_fence_driver { 360 struct radeon_device *rdev; 361 uint32_t scratch_reg; 362 uint64_t gpu_addr; 363 volatile uint32_t *cpu_addr; 364 /* sync_seq is protected by ring emission lock */ 365 uint64_t sync_seq[RADEON_NUM_RINGS]; 366 atomic64_t last_seq; 367 bool initialized, delayed_irq; 368 struct delayed_work lockup_work; 369 }; 370 371 struct radeon_fence { 372 struct radeon_device *rdev; 373 unsigned int kref; 374 uint64_t seq; 375 /* RB, DMA, etc. */ 376 unsigned ring; 377 378 wait_queue_t fence_wake; 379 }; 380 381 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 382 int radeon_fence_driver_init(struct radeon_device *rdev); 383 void radeon_fence_driver_fini(struct radeon_device *rdev); 384 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); 385 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 386 void radeon_fence_process(struct radeon_device *rdev, int ring); 387 bool radeon_fence_signaled(struct radeon_fence *fence); 388 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 389 int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 390 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 391 int radeon_fence_wait_any(struct radeon_device *rdev, 392 struct radeon_fence **fences, 393 bool intr); 394 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 395 void radeon_fence_unref(struct radeon_fence **fence); 396 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 397 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 398 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 399 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 400 struct radeon_fence *b) 401 { 402 if (!a) { 403 return b; 404 } 405 406 if (!b) { 407 return a; 408 } 409 410 BUG_ON(a->ring != b->ring); 411 412 if (a->seq > b->seq) { 413 return a; 414 } else { 415 return b; 416 } 417 } 418 419 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 420 struct radeon_fence *b) 421 { 422 if (!a) { 423 return false; 424 } 425 426 if (!b) { 427 return true; 428 } 429 430 BUG_ON(a->ring != b->ring); 431 432 return a->seq < b->seq; 433 } 434 435 /* 436 * Tiling registers 437 */ 438 struct radeon_surface_reg { 439 struct radeon_bo *bo; 440 }; 441 442 #define RADEON_GEM_MAX_SURFACES 8 443 444 /* 445 * TTM. 446 */ 447 struct radeon_mman { 448 struct ttm_bo_global_ref bo_global_ref; 449 struct drm_global_reference mem_global_ref; 450 struct ttm_bo_device bdev; 451 bool mem_global_referenced; 452 bool initialized; 453 454 #if defined(CONFIG_DEBUG_FS) 455 struct dentry *vram; 456 struct dentry *gtt; 457 #endif 458 }; 459 460 /* bo virtual address in a specific vm */ 461 struct radeon_bo_va { 462 /* protected by bo being reserved */ 463 struct list_head bo_list; 464 uint64_t soffset; 465 uint64_t eoffset; 466 uint32_t flags; 467 uint64_t addr; 468 unsigned ref_count; 469 470 /* protected by vm mutex */ 471 struct list_head vm_list; 472 struct list_head vm_status; 473 474 /* constant after initialization */ 475 struct radeon_vm *vm; 476 struct radeon_bo *bo; 477 }; 478 479 struct radeon_bo { 480 /* Protected by gem.mutex */ 481 struct list_head list; 482 /* Protected by tbo.reserved */ 483 u32 initial_domain; 484 struct ttm_place placements[3]; 485 struct ttm_placement placement; 486 struct ttm_buffer_object tbo; 487 struct ttm_bo_kmap_obj kmap; 488 u32 flags; 489 unsigned pin_count; 490 void *kptr; 491 u32 tiling_flags; 492 u32 pitch; 493 int surface_reg; 494 /* list of all virtual address to which this bo 495 * is associated to 496 */ 497 struct list_head va; 498 /* Constant after initialization */ 499 struct radeon_device *rdev; 500 struct drm_gem_object gem_base; 501 502 struct ttm_bo_kmap_obj dma_buf_vmap; 503 pid_t pid; 504 }; 505 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 506 507 int radeon_gem_debugfs_init(struct radeon_device *rdev); 508 509 /* sub-allocation manager, it has to be protected by another lock. 510 * By conception this is an helper for other part of the driver 511 * like the indirect buffer or semaphore, which both have their 512 * locking. 513 * 514 * Principe is simple, we keep a list of sub allocation in offset 515 * order (first entry has offset == 0, last entry has the highest 516 * offset). 517 * 518 * When allocating new object we first check if there is room at 519 * the end total_size - (last_object_offset + last_object_size) >= 520 * alloc_size. If so we allocate new object there. 521 * 522 * When there is not enough room at the end, we start waiting for 523 * each sub object until we reach object_offset+object_size >= 524 * alloc_size, this object then become the sub object we return. 525 * 526 * Alignment can't be bigger than page size. 527 * 528 * Hole are not considered for allocation to keep things simple. 529 * Assumption is that there won't be hole (all object on same 530 * alignment). 531 */ 532 struct radeon_sa_manager { 533 struct cv wq; 534 struct lock wq_lock; 535 struct radeon_bo *bo; 536 struct list_head *hole; 537 struct list_head flist[RADEON_NUM_RINGS]; 538 struct list_head olist; 539 unsigned size; 540 uint64_t gpu_addr; 541 void *cpu_ptr; 542 uint32_t domain; 543 uint32_t align; 544 }; 545 546 struct radeon_sa_bo; 547 548 /* sub-allocation buffer */ 549 struct radeon_sa_bo { 550 struct list_head olist; 551 struct list_head flist; 552 struct radeon_sa_manager *manager; 553 unsigned soffset; 554 unsigned eoffset; 555 struct radeon_fence *fence; 556 }; 557 558 /* 559 * GEM objects. 560 */ 561 struct radeon_gem { 562 struct spinlock mutex; 563 struct list_head objects; 564 }; 565 566 int radeon_gem_init(struct radeon_device *rdev); 567 void radeon_gem_fini(struct radeon_device *rdev); 568 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, 569 int alignment, int initial_domain, 570 u32 flags, bool kernel, 571 struct drm_gem_object **obj); 572 573 int radeon_mode_dumb_create(struct drm_file *file_priv, 574 struct drm_device *dev, 575 struct drm_mode_create_dumb *args); 576 int radeon_mode_dumb_mmap(struct drm_file *filp, 577 struct drm_device *dev, 578 uint32_t handle, uint64_t *offset_p); 579 580 /* 581 * Semaphores. 582 */ 583 struct radeon_semaphore { 584 struct radeon_sa_bo *sa_bo; 585 signed waiters; 586 uint64_t gpu_addr; 587 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 588 }; 589 590 int radeon_semaphore_create(struct radeon_device *rdev, 591 struct radeon_semaphore **semaphore); 592 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 593 struct radeon_semaphore *semaphore); 594 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 595 struct radeon_semaphore *semaphore); 596 void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore, 597 struct radeon_fence *fence); 598 int radeon_semaphore_sync_rings(struct radeon_device *rdev, 599 struct radeon_semaphore *semaphore, 600 int waiting_ring); 601 void radeon_semaphore_free(struct radeon_device *rdev, 602 struct radeon_semaphore **semaphore, 603 struct radeon_fence *fence); 604 605 /* 606 * GART structures, functions & helpers 607 */ 608 struct radeon_mc; 609 610 #define RADEON_GPU_PAGE_SIZE 4096 611 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 612 #define RADEON_GPU_PAGE_SHIFT 12 613 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 614 615 #define RADEON_GART_PAGE_DUMMY 0 616 #define RADEON_GART_PAGE_VALID (1 << 0) 617 #define RADEON_GART_PAGE_READ (1 << 1) 618 #define RADEON_GART_PAGE_WRITE (1 << 2) 619 #define RADEON_GART_PAGE_SNOOP (1 << 3) 620 621 struct radeon_gart { 622 drm_dma_handle_t *dmah; 623 dma_addr_t table_addr; 624 struct radeon_bo *robj; 625 void *ptr; 626 unsigned num_gpu_pages; 627 unsigned num_cpu_pages; 628 unsigned table_size; 629 vm_page_t *pages; 630 dma_addr_t *pages_addr; 631 bool ready; 632 }; 633 634 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 635 void radeon_gart_table_ram_free(struct radeon_device *rdev); 636 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 637 void radeon_gart_table_vram_free(struct radeon_device *rdev); 638 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 639 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 640 int radeon_gart_init(struct radeon_device *rdev); 641 void radeon_gart_fini(struct radeon_device *rdev); 642 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 643 int pages); 644 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 645 int pages, vm_page_t *pagelist, 646 dma_addr_t *dma_addr, uint32_t flags); 647 648 649 /* 650 * GPU MC structures, functions & helpers 651 */ 652 struct radeon_mc { 653 resource_size_t aper_size; 654 resource_size_t aper_base; 655 resource_size_t agp_base; 656 /* for some chips with <= 32MB we need to lie 657 * about vram size near mc fb location */ 658 u64 mc_vram_size; 659 u64 visible_vram_size; 660 u64 gtt_size; 661 u64 gtt_start; 662 u64 gtt_end; 663 u64 vram_start; 664 u64 vram_end; 665 unsigned vram_width; 666 u64 real_vram_size; 667 int vram_mtrr; 668 bool vram_is_ddr; 669 bool igp_sideport_enabled; 670 u64 gtt_base_align; 671 u64 mc_mask; 672 }; 673 674 bool radeon_combios_sideport_present(struct radeon_device *rdev); 675 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 676 677 /* 678 * GPU scratch registers structures, functions & helpers 679 */ 680 struct radeon_scratch { 681 unsigned num_reg; 682 uint32_t reg_base; 683 bool free[32]; 684 uint32_t reg[32]; 685 }; 686 687 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 688 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 689 690 /* 691 * GPU doorbell structures, functions & helpers 692 */ 693 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 694 695 struct radeon_doorbell { 696 /* doorbell mmio */ 697 resource_size_t base; 698 resource_size_t size; 699 u32 __iomem *ptr; 700 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 701 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)]; 702 }; 703 704 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 705 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 706 707 /* 708 * IRQS. 709 */ 710 711 struct radeon_flip_work { 712 struct work_struct flip_work; 713 struct work_struct unpin_work; 714 struct radeon_device *rdev; 715 int crtc_id; 716 uint64_t base; 717 struct drm_pending_vblank_event *event; 718 struct radeon_bo *old_rbo; 719 struct radeon_fence *fence; 720 }; 721 722 struct r500_irq_stat_regs { 723 u32 disp_int; 724 u32 hdmi0_status; 725 }; 726 727 struct r600_irq_stat_regs { 728 u32 disp_int; 729 u32 disp_int_cont; 730 u32 disp_int_cont2; 731 u32 d1grph_int; 732 u32 d2grph_int; 733 u32 hdmi0_status; 734 u32 hdmi1_status; 735 }; 736 737 struct evergreen_irq_stat_regs { 738 u32 disp_int; 739 u32 disp_int_cont; 740 u32 disp_int_cont2; 741 u32 disp_int_cont3; 742 u32 disp_int_cont4; 743 u32 disp_int_cont5; 744 u32 d1grph_int; 745 u32 d2grph_int; 746 u32 d3grph_int; 747 u32 d4grph_int; 748 u32 d5grph_int; 749 u32 d6grph_int; 750 u32 afmt_status1; 751 u32 afmt_status2; 752 u32 afmt_status3; 753 u32 afmt_status4; 754 u32 afmt_status5; 755 u32 afmt_status6; 756 }; 757 758 struct cik_irq_stat_regs { 759 u32 disp_int; 760 u32 disp_int_cont; 761 u32 disp_int_cont2; 762 u32 disp_int_cont3; 763 u32 disp_int_cont4; 764 u32 disp_int_cont5; 765 u32 disp_int_cont6; 766 u32 d1grph_int; 767 u32 d2grph_int; 768 u32 d3grph_int; 769 u32 d4grph_int; 770 u32 d5grph_int; 771 u32 d6grph_int; 772 }; 773 774 union radeon_irq_stat_regs { 775 struct r500_irq_stat_regs r500; 776 struct r600_irq_stat_regs r600; 777 struct evergreen_irq_stat_regs evergreen; 778 struct cik_irq_stat_regs cik; 779 }; 780 781 struct radeon_irq { 782 bool installed; 783 struct lock lock; 784 atomic_t ring_int[RADEON_NUM_RINGS]; 785 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 786 atomic_t pflip[RADEON_MAX_CRTCS]; 787 wait_queue_head_t vblank_queue; 788 bool hpd[RADEON_MAX_HPD_PINS]; 789 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 790 union radeon_irq_stat_regs stat_regs; 791 bool dpm_thermal; 792 }; 793 794 int radeon_irq_kms_init(struct radeon_device *rdev); 795 void radeon_irq_kms_fini(struct radeon_device *rdev); 796 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 797 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring); 798 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 799 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 800 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 801 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 802 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 803 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 804 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 805 806 /* 807 * CP & rings. 808 */ 809 810 struct radeon_ib { 811 struct radeon_sa_bo *sa_bo; 812 uint32_t length_dw; 813 uint64_t gpu_addr; 814 uint32_t *ptr; 815 int ring; 816 struct radeon_fence *fence; 817 struct radeon_vm *vm; 818 bool is_const_ib; 819 struct radeon_semaphore *semaphore; 820 }; 821 822 struct radeon_ring { 823 struct radeon_bo *ring_obj; 824 volatile uint32_t *ring; 825 unsigned rptr_offs; 826 unsigned rptr_save_reg; 827 u64 next_rptr_gpu_addr; 828 volatile u32 *next_rptr_cpu_addr; 829 unsigned wptr; 830 unsigned wptr_old; 831 unsigned ring_size; 832 unsigned ring_free_dw; 833 int count_dw; 834 atomic_t last_rptr; 835 atomic64_t last_activity; 836 uint64_t gpu_addr; 837 uint32_t align_mask; 838 uint32_t ptr_mask; 839 bool ready; 840 u32 nop; 841 u32 idx; 842 u64 last_semaphore_signal_addr; 843 u64 last_semaphore_wait_addr; 844 /* for CIK queues */ 845 u32 me; 846 u32 pipe; 847 u32 queue; 848 struct radeon_bo *mqd_obj; 849 u32 doorbell_index; 850 unsigned wptr_offs; 851 }; 852 853 struct radeon_mec { 854 struct radeon_bo *hpd_eop_obj; 855 u64 hpd_eop_gpu_addr; 856 u32 num_pipe; 857 u32 num_mec; 858 u32 num_queue; 859 }; 860 861 /* 862 * VM 863 */ 864 865 /* maximum number of VMIDs */ 866 #define RADEON_NUM_VM 16 867 868 /* number of entries in page table */ 869 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) 870 871 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 872 #define RADEON_VM_PTB_ALIGN_SIZE 32768 873 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 874 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 875 876 #define R600_PTE_VALID (1 << 0) 877 #define R600_PTE_SYSTEM (1 << 1) 878 #define R600_PTE_SNOOPED (1 << 2) 879 #define R600_PTE_READABLE (1 << 5) 880 #define R600_PTE_WRITEABLE (1 << 6) 881 882 /* PTE (Page Table Entry) fragment field for different page sizes */ 883 #define R600_PTE_FRAG_4KB (0 << 7) 884 #define R600_PTE_FRAG_64KB (4 << 7) 885 #define R600_PTE_FRAG_256KB (6 << 7) 886 887 /* flags needed to be set so we can copy directly from the GART table */ 888 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ 889 R600_PTE_SYSTEM | R600_PTE_VALID ) 890 891 struct radeon_vm_pt { 892 struct radeon_bo *bo; 893 uint64_t addr; 894 }; 895 896 struct radeon_vm { 897 struct list_head va; 898 unsigned id; 899 900 /* BOs moved, but not yet updated in the PT */ 901 struct list_head invalidated; 902 903 /* BOs freed, but not yet updated in the PT */ 904 struct list_head freed; 905 906 /* contains the page directory */ 907 struct radeon_bo *page_directory; 908 uint64_t pd_gpu_addr; 909 unsigned max_pde_used; 910 911 /* array of page tables, one for each page directory entry */ 912 struct radeon_vm_pt *page_tables; 913 914 struct radeon_bo_va *ib_bo_va; 915 916 struct lock mutex; 917 /* last fence for cs using this vm */ 918 struct radeon_fence *fence; 919 /* last flush or NULL if we still need to flush */ 920 struct radeon_fence *last_flush; 921 /* last use of vmid */ 922 struct radeon_fence *last_id_use; 923 }; 924 925 struct radeon_vm_manager { 926 struct radeon_fence *active[RADEON_NUM_VM]; 927 uint32_t max_pfn; 928 /* number of VMIDs */ 929 unsigned nvm; 930 /* vram base address for page table entry */ 931 u64 vram_base_offset; 932 /* is vm enabled? */ 933 bool enabled; 934 /* for hw to save the PD addr on suspend/resume */ 935 uint32_t saved_table_addr[RADEON_NUM_VM]; 936 }; 937 938 /* 939 * file private structure 940 */ 941 struct radeon_fpriv { 942 struct radeon_vm vm; 943 }; 944 945 /* 946 * R6xx+ IH ring 947 */ 948 struct r600_ih { 949 struct radeon_bo *ring_obj; 950 volatile uint32_t *ring; 951 unsigned rptr; 952 unsigned ring_size; 953 uint64_t gpu_addr; 954 uint32_t ptr_mask; 955 atomic_t lock; 956 bool enabled; 957 }; 958 959 /* 960 * RLC stuff 961 */ 962 #include "clearstate_defs.h" 963 964 struct radeon_rlc { 965 /* for power gating */ 966 struct radeon_bo *save_restore_obj; 967 uint64_t save_restore_gpu_addr; 968 volatile uint32_t *sr_ptr; 969 const u32 *reg_list; 970 u32 reg_list_size; 971 /* for clear state */ 972 struct radeon_bo *clear_state_obj; 973 uint64_t clear_state_gpu_addr; 974 volatile uint32_t *cs_ptr; 975 const struct cs_section_def *cs_data; 976 u32 clear_state_size; 977 /* for cp tables */ 978 struct radeon_bo *cp_table_obj; 979 uint64_t cp_table_gpu_addr; 980 volatile uint32_t *cp_table_ptr; 981 u32 cp_table_size; 982 }; 983 984 int radeon_ib_get(struct radeon_device *rdev, int ring, 985 struct radeon_ib *ib, struct radeon_vm *vm, 986 unsigned size); 987 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 988 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 989 struct radeon_ib *const_ib, bool hdp_flush); 990 int radeon_ib_pool_init(struct radeon_device *rdev); 991 void radeon_ib_pool_fini(struct radeon_device *rdev); 992 int radeon_ib_ring_tests(struct radeon_device *rdev); 993 /* Ring access between begin & end cannot sleep */ 994 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 995 struct radeon_ring *ring); 996 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 997 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 998 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 999 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1000 bool hdp_flush); 1001 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1002 bool hdp_flush); 1003 void radeon_ring_undo(struct radeon_ring *ring); 1004 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 1005 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 1006 void radeon_ring_lockup_update(struct radeon_device *rdev, 1007 struct radeon_ring *ring); 1008 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 1009 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 1010 uint32_t **data); 1011 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 1012 unsigned size, uint32_t *data); 1013 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 1014 unsigned rptr_offs, u32 nop); 1015 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 1016 1017 1018 /* r600 async dma */ 1019 void r600_dma_stop(struct radeon_device *rdev); 1020 int r600_dma_resume(struct radeon_device *rdev); 1021 void r600_dma_fini(struct radeon_device *rdev); 1022 1023 void cayman_dma_stop(struct radeon_device *rdev); 1024 int cayman_dma_resume(struct radeon_device *rdev); 1025 void cayman_dma_fini(struct radeon_device *rdev); 1026 1027 /* 1028 * CS. 1029 */ 1030 struct radeon_cs_reloc { 1031 struct drm_gem_object *gobj; 1032 struct radeon_bo *robj; 1033 struct ttm_validate_buffer tv; 1034 uint64_t gpu_offset; 1035 unsigned prefered_domains; 1036 unsigned allowed_domains; 1037 uint32_t tiling_flags; 1038 uint32_t handle; 1039 }; 1040 1041 struct radeon_cs_chunk { 1042 uint32_t chunk_id; 1043 uint32_t length_dw; 1044 uint32_t *kdata; 1045 void __user *user_ptr; 1046 }; 1047 1048 struct radeon_cs_parser { 1049 device_t dev; 1050 struct radeon_device *rdev; 1051 struct drm_file *filp; 1052 /* chunks */ 1053 unsigned nchunks; 1054 struct radeon_cs_chunk *chunks; 1055 uint64_t *chunks_array; 1056 /* IB */ 1057 unsigned idx; 1058 /* relocations */ 1059 unsigned nrelocs; 1060 struct radeon_cs_reloc *relocs; 1061 struct radeon_cs_reloc **relocs_ptr; 1062 struct radeon_cs_reloc *vm_bos; 1063 struct list_head validated; 1064 unsigned dma_reloc_idx; 1065 /* indices of various chunks */ 1066 int chunk_ib_idx; 1067 int chunk_relocs_idx; 1068 int chunk_flags_idx; 1069 int chunk_const_ib_idx; 1070 struct radeon_ib ib; 1071 struct radeon_ib const_ib; 1072 void *track; 1073 unsigned family; 1074 int parser_error; 1075 u32 cs_flags; 1076 u32 ring; 1077 s32 priority; 1078 struct ww_acquire_ctx ticket; 1079 }; 1080 1081 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1082 { 1083 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 1084 1085 if (ibc->kdata) 1086 return ibc->kdata[idx]; 1087 return p->ib.ptr[idx]; 1088 } 1089 1090 1091 struct radeon_cs_packet { 1092 unsigned idx; 1093 unsigned type; 1094 unsigned reg; 1095 unsigned opcode; 1096 int count; 1097 unsigned one_reg_wr; 1098 }; 1099 1100 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1101 struct radeon_cs_packet *pkt, 1102 unsigned idx, unsigned reg); 1103 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 1104 struct radeon_cs_packet *pkt); 1105 1106 1107 /* 1108 * AGP 1109 */ 1110 int radeon_agp_init(struct radeon_device *rdev); 1111 void radeon_agp_resume(struct radeon_device *rdev); 1112 void radeon_agp_suspend(struct radeon_device *rdev); 1113 void radeon_agp_fini(struct radeon_device *rdev); 1114 1115 1116 /* 1117 * Writeback 1118 */ 1119 struct radeon_wb { 1120 struct radeon_bo *wb_obj; 1121 volatile uint32_t *wb; 1122 uint64_t gpu_addr; 1123 bool enabled; 1124 bool use_event; 1125 }; 1126 1127 #define RADEON_WB_SCRATCH_OFFSET 0 1128 #define RADEON_WB_RING0_NEXT_RPTR 256 1129 #define RADEON_WB_CP_RPTR_OFFSET 1024 1130 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1131 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1132 #define R600_WB_DMA_RPTR_OFFSET 1792 1133 #define R600_WB_IH_WPTR_OFFSET 2048 1134 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1135 #define R600_WB_EVENT_OFFSET 3072 1136 #define CIK_WB_CP1_WPTR_OFFSET 3328 1137 #define CIK_WB_CP2_WPTR_OFFSET 3584 1138 #define R600_WB_DMA_RING_TEST_OFFSET 3588 1139 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 1140 1141 /** 1142 * struct radeon_pm - power management datas 1143 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1144 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1145 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1146 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1147 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1148 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1149 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1150 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1151 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1152 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1153 * @needed_bandwidth: current bandwidth needs 1154 * 1155 * It keeps track of various data needed to take powermanagement decision. 1156 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1157 * Equation between gpu/memory clock and available bandwidth is hw dependent 1158 * (type of memory, bus size, efficiency, ...) 1159 */ 1160 1161 enum radeon_pm_method { 1162 PM_METHOD_PROFILE, 1163 PM_METHOD_DYNPM, 1164 PM_METHOD_DPM, 1165 }; 1166 1167 enum radeon_dynpm_state { 1168 DYNPM_STATE_DISABLED, 1169 DYNPM_STATE_MINIMUM, 1170 DYNPM_STATE_PAUSED, 1171 DYNPM_STATE_ACTIVE, 1172 DYNPM_STATE_SUSPENDED, 1173 }; 1174 enum radeon_dynpm_action { 1175 DYNPM_ACTION_NONE, 1176 DYNPM_ACTION_MINIMUM, 1177 DYNPM_ACTION_DOWNCLOCK, 1178 DYNPM_ACTION_UPCLOCK, 1179 DYNPM_ACTION_DEFAULT 1180 }; 1181 1182 enum radeon_voltage_type { 1183 VOLTAGE_NONE = 0, 1184 VOLTAGE_GPIO, 1185 VOLTAGE_VDDC, 1186 VOLTAGE_SW 1187 }; 1188 1189 enum radeon_pm_state_type { 1190 /* not used for dpm */ 1191 POWER_STATE_TYPE_DEFAULT, 1192 POWER_STATE_TYPE_POWERSAVE, 1193 /* user selectable states */ 1194 POWER_STATE_TYPE_BATTERY, 1195 POWER_STATE_TYPE_BALANCED, 1196 POWER_STATE_TYPE_PERFORMANCE, 1197 /* internal states */ 1198 POWER_STATE_TYPE_INTERNAL_UVD, 1199 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1200 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1201 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1202 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1203 POWER_STATE_TYPE_INTERNAL_BOOT, 1204 POWER_STATE_TYPE_INTERNAL_THERMAL, 1205 POWER_STATE_TYPE_INTERNAL_ACPI, 1206 POWER_STATE_TYPE_INTERNAL_ULV, 1207 POWER_STATE_TYPE_INTERNAL_3DPERF, 1208 }; 1209 1210 enum radeon_pm_profile_type { 1211 PM_PROFILE_DEFAULT, 1212 PM_PROFILE_AUTO, 1213 PM_PROFILE_LOW, 1214 PM_PROFILE_MID, 1215 PM_PROFILE_HIGH, 1216 }; 1217 1218 #define PM_PROFILE_DEFAULT_IDX 0 1219 #define PM_PROFILE_LOW_SH_IDX 1 1220 #define PM_PROFILE_MID_SH_IDX 2 1221 #define PM_PROFILE_HIGH_SH_IDX 3 1222 #define PM_PROFILE_LOW_MH_IDX 4 1223 #define PM_PROFILE_MID_MH_IDX 5 1224 #define PM_PROFILE_HIGH_MH_IDX 6 1225 #define PM_PROFILE_MAX 7 1226 1227 struct radeon_pm_profile { 1228 int dpms_off_ps_idx; 1229 int dpms_on_ps_idx; 1230 int dpms_off_cm_idx; 1231 int dpms_on_cm_idx; 1232 }; 1233 1234 enum radeon_int_thermal_type { 1235 THERMAL_TYPE_NONE, 1236 THERMAL_TYPE_EXTERNAL, 1237 THERMAL_TYPE_EXTERNAL_GPIO, 1238 THERMAL_TYPE_RV6XX, 1239 THERMAL_TYPE_RV770, 1240 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1241 THERMAL_TYPE_EVERGREEN, 1242 THERMAL_TYPE_SUMO, 1243 THERMAL_TYPE_NI, 1244 THERMAL_TYPE_SI, 1245 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1246 THERMAL_TYPE_CI, 1247 THERMAL_TYPE_KV, 1248 }; 1249 1250 struct radeon_voltage { 1251 enum radeon_voltage_type type; 1252 /* gpio voltage */ 1253 struct radeon_gpio_rec gpio; 1254 u32 delay; /* delay in usec from voltage drop to sclk change */ 1255 bool active_high; /* voltage drop is active when bit is high */ 1256 /* VDDC voltage */ 1257 u8 vddc_id; /* index into vddc voltage table */ 1258 u8 vddci_id; /* index into vddci voltage table */ 1259 bool vddci_enabled; 1260 /* r6xx+ sw */ 1261 u16 voltage; 1262 /* evergreen+ vddci */ 1263 u16 vddci; 1264 }; 1265 1266 /* clock mode flags */ 1267 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1268 1269 struct radeon_pm_clock_info { 1270 /* memory clock */ 1271 u32 mclk; 1272 /* engine clock */ 1273 u32 sclk; 1274 /* voltage info */ 1275 struct radeon_voltage voltage; 1276 /* standardized clock flags */ 1277 u32 flags; 1278 }; 1279 1280 /* state flags */ 1281 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1282 1283 struct radeon_power_state { 1284 enum radeon_pm_state_type type; 1285 struct radeon_pm_clock_info *clock_info; 1286 /* number of valid clock modes in this power state */ 1287 int num_clock_modes; 1288 struct radeon_pm_clock_info *default_clock_mode; 1289 /* standardized state flags */ 1290 u32 flags; 1291 u32 misc; /* vbios specific flags */ 1292 u32 misc2; /* vbios specific flags */ 1293 int pcie_lanes; /* pcie lanes */ 1294 }; 1295 1296 /* 1297 * Some modes are overclocked by very low value, accept them 1298 */ 1299 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1300 1301 enum radeon_dpm_auto_throttle_src { 1302 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1303 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1304 }; 1305 1306 enum radeon_dpm_event_src { 1307 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1308 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1309 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1310 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1311 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1312 }; 1313 1314 #define RADEON_MAX_VCE_LEVELS 6 1315 1316 enum radeon_vce_level { 1317 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1318 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1319 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1320 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1321 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1322 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1323 }; 1324 1325 struct radeon_ps { 1326 u32 caps; /* vbios flags */ 1327 u32 class; /* vbios flags */ 1328 u32 class2; /* vbios flags */ 1329 /* UVD clocks */ 1330 u32 vclk; 1331 u32 dclk; 1332 /* VCE clocks */ 1333 u32 evclk; 1334 u32 ecclk; 1335 bool vce_active; 1336 enum radeon_vce_level vce_level; 1337 /* asic priv */ 1338 void *ps_priv; 1339 }; 1340 1341 struct radeon_dpm_thermal { 1342 /* thermal interrupt work */ 1343 struct task work; 1344 /* low temperature threshold */ 1345 int min_temp; 1346 /* high temperature threshold */ 1347 int max_temp; 1348 /* was interrupt low to high or high to low */ 1349 bool high_to_low; 1350 }; 1351 1352 enum radeon_clk_action 1353 { 1354 RADEON_SCLK_UP = 1, 1355 RADEON_SCLK_DOWN 1356 }; 1357 1358 struct radeon_blacklist_clocks 1359 { 1360 u32 sclk; 1361 u32 mclk; 1362 enum radeon_clk_action action; 1363 }; 1364 1365 struct radeon_clock_and_voltage_limits { 1366 u32 sclk; 1367 u32 mclk; 1368 u16 vddc; 1369 u16 vddci; 1370 }; 1371 1372 struct radeon_clock_array { 1373 u32 count; 1374 u32 *values; 1375 }; 1376 1377 struct radeon_clock_voltage_dependency_entry { 1378 u32 clk; 1379 u16 v; 1380 }; 1381 1382 struct radeon_clock_voltage_dependency_table { 1383 u32 count; 1384 struct radeon_clock_voltage_dependency_entry *entries; 1385 }; 1386 1387 union radeon_cac_leakage_entry { 1388 struct { 1389 u16 vddc; 1390 u32 leakage; 1391 }; 1392 struct { 1393 u16 vddc1; 1394 u16 vddc2; 1395 u16 vddc3; 1396 }; 1397 }; 1398 1399 struct radeon_cac_leakage_table { 1400 u32 count; 1401 union radeon_cac_leakage_entry *entries; 1402 }; 1403 1404 struct radeon_phase_shedding_limits_entry { 1405 u16 voltage; 1406 u32 sclk; 1407 u32 mclk; 1408 }; 1409 1410 struct radeon_phase_shedding_limits_table { 1411 u32 count; 1412 struct radeon_phase_shedding_limits_entry *entries; 1413 }; 1414 1415 struct radeon_uvd_clock_voltage_dependency_entry { 1416 u32 vclk; 1417 u32 dclk; 1418 u16 v; 1419 }; 1420 1421 struct radeon_uvd_clock_voltage_dependency_table { 1422 u8 count; 1423 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1424 }; 1425 1426 struct radeon_vce_clock_voltage_dependency_entry { 1427 u32 ecclk; 1428 u32 evclk; 1429 u16 v; 1430 }; 1431 1432 struct radeon_vce_clock_voltage_dependency_table { 1433 u8 count; 1434 struct radeon_vce_clock_voltage_dependency_entry *entries; 1435 }; 1436 1437 struct radeon_ppm_table { 1438 u8 ppm_design; 1439 u16 cpu_core_number; 1440 u32 platform_tdp; 1441 u32 small_ac_platform_tdp; 1442 u32 platform_tdc; 1443 u32 small_ac_platform_tdc; 1444 u32 apu_tdp; 1445 u32 dgpu_tdp; 1446 u32 dgpu_ulv_power; 1447 u32 tj_max; 1448 }; 1449 1450 struct radeon_cac_tdp_table { 1451 u16 tdp; 1452 u16 configurable_tdp; 1453 u16 tdc; 1454 u16 battery_power_limit; 1455 u16 small_power_limit; 1456 u16 low_cac_leakage; 1457 u16 high_cac_leakage; 1458 u16 maximum_power_delivery_limit; 1459 }; 1460 1461 struct radeon_dpm_dynamic_state { 1462 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1463 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1464 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1465 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1466 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1467 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1468 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1469 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1470 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1471 struct radeon_clock_array valid_sclk_values; 1472 struct radeon_clock_array valid_mclk_values; 1473 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1474 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1475 u32 mclk_sclk_ratio; 1476 u32 sclk_mclk_delta; 1477 u16 vddc_vddci_delta; 1478 u16 min_vddc_for_pcie_gen2; 1479 struct radeon_cac_leakage_table cac_leakage_table; 1480 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1481 struct radeon_ppm_table *ppm_table; 1482 struct radeon_cac_tdp_table *cac_tdp_table; 1483 }; 1484 1485 struct radeon_dpm_fan { 1486 u16 t_min; 1487 u16 t_med; 1488 u16 t_high; 1489 u16 pwm_min; 1490 u16 pwm_med; 1491 u16 pwm_high; 1492 u8 t_hyst; 1493 u32 cycle_delay; 1494 u16 t_max; 1495 bool ucode_fan_control; 1496 }; 1497 1498 enum radeon_pcie_gen { 1499 RADEON_PCIE_GEN1 = 0, 1500 RADEON_PCIE_GEN2 = 1, 1501 RADEON_PCIE_GEN3 = 2, 1502 RADEON_PCIE_GEN_INVALID = 0xffff 1503 }; 1504 1505 enum radeon_dpm_forced_level { 1506 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1507 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1508 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1509 }; 1510 1511 struct radeon_vce_state { 1512 /* vce clocks */ 1513 u32 evclk; 1514 u32 ecclk; 1515 /* gpu clocks */ 1516 u32 sclk; 1517 u32 mclk; 1518 u8 clk_idx; 1519 u8 pstate; 1520 }; 1521 1522 struct radeon_dpm { 1523 struct radeon_ps *ps; 1524 /* number of valid power states */ 1525 int num_ps; 1526 /* current power state that is active */ 1527 struct radeon_ps *current_ps; 1528 /* requested power state */ 1529 struct radeon_ps *requested_ps; 1530 /* boot up power state */ 1531 struct radeon_ps *boot_ps; 1532 /* default uvd power state */ 1533 struct radeon_ps *uvd_ps; 1534 /* vce requirements */ 1535 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1536 enum radeon_vce_level vce_level; 1537 enum radeon_pm_state_type state; 1538 enum radeon_pm_state_type user_state; 1539 u32 platform_caps; 1540 u32 voltage_response_time; 1541 u32 backbias_response_time; 1542 void *priv; 1543 u32 new_active_crtcs; 1544 int new_active_crtc_count; 1545 u32 current_active_crtcs; 1546 int current_active_crtc_count; 1547 struct radeon_dpm_dynamic_state dyn_state; 1548 struct radeon_dpm_fan fan; 1549 u32 tdp_limit; 1550 u32 near_tdp_limit; 1551 u32 near_tdp_limit_adjusted; 1552 u32 sq_ramping_threshold; 1553 u32 cac_leakage; 1554 u16 tdp_od_limit; 1555 u32 tdp_adjustment; 1556 u16 load_line_slope; 1557 bool power_control; 1558 bool ac_power; 1559 /* special states active */ 1560 bool thermal_active; 1561 bool uvd_active; 1562 bool vce_active; 1563 /* thermal handling */ 1564 struct radeon_dpm_thermal thermal; 1565 /* forced levels */ 1566 enum radeon_dpm_forced_level forced_level; 1567 /* track UVD streams */ 1568 unsigned sd; 1569 unsigned hd; 1570 }; 1571 1572 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1573 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1574 1575 struct radeon_pm { 1576 struct lock mutex; 1577 /* write locked while reprogramming mclk */ 1578 struct lock mclk_lock; 1579 u32 active_crtcs; 1580 int active_crtc_count; 1581 int req_vblank; 1582 bool vblank_sync; 1583 fixed20_12 max_bandwidth; 1584 fixed20_12 igp_sideport_mclk; 1585 fixed20_12 igp_system_mclk; 1586 fixed20_12 igp_ht_link_clk; 1587 fixed20_12 igp_ht_link_width; 1588 fixed20_12 k8_bandwidth; 1589 fixed20_12 sideport_bandwidth; 1590 fixed20_12 ht_bandwidth; 1591 fixed20_12 core_bandwidth; 1592 fixed20_12 sclk; 1593 fixed20_12 mclk; 1594 fixed20_12 needed_bandwidth; 1595 struct radeon_power_state *power_state; 1596 /* number of valid power states */ 1597 int num_power_states; 1598 int current_power_state_index; 1599 int current_clock_mode_index; 1600 int requested_power_state_index; 1601 int requested_clock_mode_index; 1602 int default_power_state_index; 1603 u32 current_sclk; 1604 u32 current_mclk; 1605 u16 current_vddc; 1606 u16 current_vddci; 1607 u32 default_sclk; 1608 u32 default_mclk; 1609 u16 default_vddc; 1610 u16 default_vddci; 1611 struct radeon_i2c_chan *i2c_bus; 1612 /* selected pm method */ 1613 enum radeon_pm_method pm_method; 1614 /* dynpm power management */ 1615 #ifdef DUMBBELL_WIP 1616 struct delayed_work dynpm_idle_work; 1617 #endif /* DUMBBELL_WIP */ 1618 enum radeon_dynpm_state dynpm_state; 1619 enum radeon_dynpm_action dynpm_planned_action; 1620 unsigned long dynpm_action_timeout; 1621 bool dynpm_can_upclock; 1622 bool dynpm_can_downclock; 1623 /* profile-based power management */ 1624 enum radeon_pm_profile_type profile; 1625 int profile_index; 1626 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1627 /* internal thermal controller on rv6xx+ */ 1628 enum radeon_int_thermal_type int_thermal_type; 1629 struct ksensor *int_sensor; 1630 struct ksensordev *int_sensordev; 1631 /* dpm */ 1632 bool dpm_enabled; 1633 struct radeon_dpm dpm; 1634 }; 1635 1636 int radeon_pm_get_type_index(struct radeon_device *rdev, 1637 enum radeon_pm_state_type ps_type, 1638 int instance); 1639 /* 1640 * UVD 1641 */ 1642 #define RADEON_MAX_UVD_HANDLES 10 1643 #define RADEON_UVD_STACK_SIZE (1024*1024) 1644 #define RADEON_UVD_HEAP_SIZE (1024*1024) 1645 1646 struct radeon_uvd { 1647 struct radeon_bo *vcpu_bo; 1648 void *cpu_addr; 1649 uint64_t gpu_addr; 1650 void *saved_bo; 1651 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1652 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1653 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1654 struct delayed_work idle_work; 1655 }; 1656 1657 int radeon_uvd_init(struct radeon_device *rdev); 1658 void radeon_uvd_fini(struct radeon_device *rdev); 1659 int radeon_uvd_suspend(struct radeon_device *rdev); 1660 int radeon_uvd_resume(struct radeon_device *rdev); 1661 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1662 uint32_t handle, struct radeon_fence **fence); 1663 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1664 uint32_t handle, struct radeon_fence **fence); 1665 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, 1666 uint32_t allowed_domains); 1667 void radeon_uvd_free_handles(struct radeon_device *rdev, 1668 struct drm_file *filp); 1669 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1670 void radeon_uvd_note_usage(struct radeon_device *rdev); 1671 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1672 unsigned vclk, unsigned dclk, 1673 unsigned vco_min, unsigned vco_max, 1674 unsigned fb_factor, unsigned fb_mask, 1675 unsigned pd_min, unsigned pd_max, 1676 unsigned pd_even, 1677 unsigned *optimal_fb_div, 1678 unsigned *optimal_vclk_div, 1679 unsigned *optimal_dclk_div); 1680 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1681 unsigned cg_upll_func_cntl); 1682 1683 /* 1684 * VCE 1685 */ 1686 #define RADEON_MAX_VCE_HANDLES 16 1687 #define RADEON_VCE_STACK_SIZE (1024*1024) 1688 #define RADEON_VCE_HEAP_SIZE (4*1024*1024) 1689 1690 struct radeon_vce { 1691 struct radeon_bo *vcpu_bo; 1692 uint64_t gpu_addr; 1693 unsigned fw_version; 1694 unsigned fb_version; 1695 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1696 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1697 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1698 struct delayed_work idle_work; 1699 }; 1700 1701 int radeon_vce_init(struct radeon_device *rdev); 1702 void radeon_vce_fini(struct radeon_device *rdev); 1703 int radeon_vce_suspend(struct radeon_device *rdev); 1704 int radeon_vce_resume(struct radeon_device *rdev); 1705 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1706 uint32_t handle, struct radeon_fence **fence); 1707 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1708 uint32_t handle, struct radeon_fence **fence); 1709 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1710 void radeon_vce_note_usage(struct radeon_device *rdev); 1711 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1712 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1713 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1714 struct radeon_ring *ring, 1715 struct radeon_semaphore *semaphore, 1716 bool emit_wait); 1717 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1718 void radeon_vce_fence_emit(struct radeon_device *rdev, 1719 struct radeon_fence *fence); 1720 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1721 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1722 1723 struct r600_audio_pin { 1724 int channels; 1725 int rate; 1726 int bits_per_sample; 1727 u8 status_bits; 1728 u8 category_code; 1729 u32 offset; 1730 bool connected; 1731 u32 id; 1732 }; 1733 1734 struct r600_audio { 1735 bool enabled; 1736 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1737 int num_pins; 1738 }; 1739 1740 /* 1741 * Benchmarking 1742 */ 1743 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1744 1745 1746 /* 1747 * Testing 1748 */ 1749 void radeon_test_moves(struct radeon_device *rdev); 1750 void radeon_test_ring_sync(struct radeon_device *rdev, 1751 struct radeon_ring *cpA, 1752 struct radeon_ring *cpB); 1753 void radeon_test_syncing(struct radeon_device *rdev); 1754 1755 1756 /* 1757 * Debugfs 1758 */ 1759 struct radeon_debugfs { 1760 struct drm_info_list *files; 1761 unsigned num_files; 1762 }; 1763 1764 int radeon_debugfs_add_files(struct radeon_device *rdev, 1765 struct drm_info_list *files, 1766 unsigned nfiles); 1767 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1768 1769 /* 1770 * ASIC ring specific functions. 1771 */ 1772 struct radeon_asic_ring { 1773 /* ring read/write ptr handling */ 1774 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1775 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1776 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1777 1778 /* validating and patching of IBs */ 1779 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1780 int (*cs_parse)(struct radeon_cs_parser *p); 1781 1782 /* command emmit functions */ 1783 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1784 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1785 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); 1786 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1787 struct radeon_semaphore *semaphore, bool emit_wait); 1788 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 1789 1790 /* testing functions */ 1791 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1792 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1793 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1794 1795 /* deprecated */ 1796 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1797 }; 1798 1799 /* 1800 * ASIC specific functions. 1801 */ 1802 struct radeon_asic { 1803 int (*init)(struct radeon_device *rdev); 1804 void (*fini)(struct radeon_device *rdev); 1805 int (*resume)(struct radeon_device *rdev); 1806 int (*suspend)(struct radeon_device *rdev); 1807 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1808 int (*asic_reset)(struct radeon_device *rdev); 1809 /* Flush the HDP cache via MMIO */ 1810 void (*mmio_hdp_flush)(struct radeon_device *rdev); 1811 /* check if 3D engine is idle */ 1812 bool (*gui_idle)(struct radeon_device *rdev); 1813 /* wait for mc_idle */ 1814 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1815 /* get the reference clock */ 1816 u32 (*get_xclk)(struct radeon_device *rdev); 1817 /* get the gpu clock counter */ 1818 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1819 /* gart */ 1820 struct { 1821 void (*tlb_flush)(struct radeon_device *rdev); 1822 void (*set_page)(struct radeon_device *rdev, unsigned i, 1823 uint64_t addr, uint32_t flags); 1824 } gart; 1825 struct { 1826 int (*init)(struct radeon_device *rdev); 1827 void (*fini)(struct radeon_device *rdev); 1828 void (*copy_pages)(struct radeon_device *rdev, 1829 struct radeon_ib *ib, 1830 uint64_t pe, uint64_t src, 1831 unsigned count); 1832 void (*write_pages)(struct radeon_device *rdev, 1833 struct radeon_ib *ib, 1834 uint64_t pe, 1835 uint64_t addr, unsigned count, 1836 uint32_t incr, uint32_t flags); 1837 void (*set_pages)(struct radeon_device *rdev, 1838 struct radeon_ib *ib, 1839 uint64_t pe, 1840 uint64_t addr, unsigned count, 1841 uint32_t incr, uint32_t flags); 1842 void (*pad_ib)(struct radeon_ib *ib); 1843 } vm; 1844 /* ring specific callbacks */ 1845 struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1846 /* irqs */ 1847 struct { 1848 int (*set)(struct radeon_device *rdev); 1849 irqreturn_t (*process)(struct radeon_device *rdev); 1850 } irq; 1851 /* displays */ 1852 struct { 1853 /* display watermarks */ 1854 void (*bandwidth_update)(struct radeon_device *rdev); 1855 /* get frame count */ 1856 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1857 /* wait for vblank */ 1858 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1859 /* set backlight level */ 1860 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1861 /* get backlight level */ 1862 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1863 /* audio callbacks */ 1864 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1865 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1866 } display; 1867 /* copy functions for bo handling */ 1868 struct { 1869 int (*blit)(struct radeon_device *rdev, 1870 uint64_t src_offset, 1871 uint64_t dst_offset, 1872 unsigned num_gpu_pages, 1873 struct radeon_fence **fence); 1874 u32 blit_ring_index; 1875 int (*dma)(struct radeon_device *rdev, 1876 uint64_t src_offset, 1877 uint64_t dst_offset, 1878 unsigned num_gpu_pages, 1879 struct radeon_fence **fence); 1880 u32 dma_ring_index; 1881 /* method used for bo copy */ 1882 int (*copy)(struct radeon_device *rdev, 1883 uint64_t src_offset, 1884 uint64_t dst_offset, 1885 unsigned num_gpu_pages, 1886 struct radeon_fence **fence); 1887 /* ring used for bo copies */ 1888 u32 copy_ring_index; 1889 } copy; 1890 /* surfaces */ 1891 struct { 1892 int (*set_reg)(struct radeon_device *rdev, int reg, 1893 uint32_t tiling_flags, uint32_t pitch, 1894 uint32_t offset, uint32_t obj_size); 1895 void (*clear_reg)(struct radeon_device *rdev, int reg); 1896 } surface; 1897 /* hotplug detect */ 1898 struct { 1899 void (*init)(struct radeon_device *rdev); 1900 void (*fini)(struct radeon_device *rdev); 1901 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1902 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1903 } hpd; 1904 /* static power management */ 1905 struct { 1906 void (*misc)(struct radeon_device *rdev); 1907 void (*prepare)(struct radeon_device *rdev); 1908 void (*finish)(struct radeon_device *rdev); 1909 void (*init_profile)(struct radeon_device *rdev); 1910 void (*get_dynpm_state)(struct radeon_device *rdev); 1911 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1912 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1913 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1914 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1915 int (*get_pcie_lanes)(struct radeon_device *rdev); 1916 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1917 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1918 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 1919 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 1920 int (*get_temperature)(struct radeon_device *rdev); 1921 } pm; 1922 /* dynamic power management */ 1923 struct { 1924 int (*init)(struct radeon_device *rdev); 1925 void (*setup_asic)(struct radeon_device *rdev); 1926 int (*enable)(struct radeon_device *rdev); 1927 int (*late_enable)(struct radeon_device *rdev); 1928 void (*disable)(struct radeon_device *rdev); 1929 int (*pre_set_power_state)(struct radeon_device *rdev); 1930 int (*set_power_state)(struct radeon_device *rdev); 1931 void (*post_set_power_state)(struct radeon_device *rdev); 1932 void (*display_configuration_changed)(struct radeon_device *rdev); 1933 void (*fini)(struct radeon_device *rdev); 1934 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 1935 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 1936 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 1937 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 1938 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 1939 bool (*vblank_too_short)(struct radeon_device *rdev); 1940 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 1941 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 1942 } dpm; 1943 /* pageflipping */ 1944 struct { 1945 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 1946 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); 1947 } pflip; 1948 }; 1949 1950 /* 1951 * Asic structures 1952 */ 1953 struct r100_asic { 1954 const unsigned *reg_safe_bm; 1955 unsigned reg_safe_bm_size; 1956 u32 hdp_cntl; 1957 }; 1958 1959 struct r300_asic { 1960 const unsigned *reg_safe_bm; 1961 unsigned reg_safe_bm_size; 1962 u32 resync_scratch; 1963 u32 hdp_cntl; 1964 }; 1965 1966 struct r600_asic { 1967 unsigned max_pipes; 1968 unsigned max_tile_pipes; 1969 unsigned max_simds; 1970 unsigned max_backends; 1971 unsigned max_gprs; 1972 unsigned max_threads; 1973 unsigned max_stack_entries; 1974 unsigned max_hw_contexts; 1975 unsigned max_gs_threads; 1976 unsigned sx_max_export_size; 1977 unsigned sx_max_export_pos_size; 1978 unsigned sx_max_export_smx_size; 1979 unsigned sq_num_cf_insts; 1980 unsigned tiling_nbanks; 1981 unsigned tiling_npipes; 1982 unsigned tiling_group_size; 1983 unsigned tile_config; 1984 unsigned backend_map; 1985 unsigned active_simds; 1986 }; 1987 1988 struct rv770_asic { 1989 unsigned max_pipes; 1990 unsigned max_tile_pipes; 1991 unsigned max_simds; 1992 unsigned max_backends; 1993 unsigned max_gprs; 1994 unsigned max_threads; 1995 unsigned max_stack_entries; 1996 unsigned max_hw_contexts; 1997 unsigned max_gs_threads; 1998 unsigned sx_max_export_size; 1999 unsigned sx_max_export_pos_size; 2000 unsigned sx_max_export_smx_size; 2001 unsigned sq_num_cf_insts; 2002 unsigned sx_num_of_sets; 2003 unsigned sc_prim_fifo_size; 2004 unsigned sc_hiz_tile_fifo_size; 2005 unsigned sc_earlyz_tile_fifo_fize; 2006 unsigned tiling_nbanks; 2007 unsigned tiling_npipes; 2008 unsigned tiling_group_size; 2009 unsigned tile_config; 2010 unsigned backend_map; 2011 unsigned active_simds; 2012 }; 2013 2014 struct evergreen_asic { 2015 unsigned num_ses; 2016 unsigned max_pipes; 2017 unsigned max_tile_pipes; 2018 unsigned max_simds; 2019 unsigned max_backends; 2020 unsigned max_gprs; 2021 unsigned max_threads; 2022 unsigned max_stack_entries; 2023 unsigned max_hw_contexts; 2024 unsigned max_gs_threads; 2025 unsigned sx_max_export_size; 2026 unsigned sx_max_export_pos_size; 2027 unsigned sx_max_export_smx_size; 2028 unsigned sq_num_cf_insts; 2029 unsigned sx_num_of_sets; 2030 unsigned sc_prim_fifo_size; 2031 unsigned sc_hiz_tile_fifo_size; 2032 unsigned sc_earlyz_tile_fifo_size; 2033 unsigned tiling_nbanks; 2034 unsigned tiling_npipes; 2035 unsigned tiling_group_size; 2036 unsigned tile_config; 2037 unsigned backend_map; 2038 unsigned active_simds; 2039 }; 2040 2041 struct cayman_asic { 2042 unsigned max_shader_engines; 2043 unsigned max_pipes_per_simd; 2044 unsigned max_tile_pipes; 2045 unsigned max_simds_per_se; 2046 unsigned max_backends_per_se; 2047 unsigned max_texture_channel_caches; 2048 unsigned max_gprs; 2049 unsigned max_threads; 2050 unsigned max_gs_threads; 2051 unsigned max_stack_entries; 2052 unsigned sx_num_of_sets; 2053 unsigned sx_max_export_size; 2054 unsigned sx_max_export_pos_size; 2055 unsigned sx_max_export_smx_size; 2056 unsigned max_hw_contexts; 2057 unsigned sq_num_cf_insts; 2058 unsigned sc_prim_fifo_size; 2059 unsigned sc_hiz_tile_fifo_size; 2060 unsigned sc_earlyz_tile_fifo_size; 2061 2062 unsigned num_shader_engines; 2063 unsigned num_shader_pipes_per_simd; 2064 unsigned num_tile_pipes; 2065 unsigned num_simds_per_se; 2066 unsigned num_backends_per_se; 2067 unsigned backend_disable_mask_per_asic; 2068 unsigned backend_map; 2069 unsigned num_texture_channel_caches; 2070 unsigned mem_max_burst_length_bytes; 2071 unsigned mem_row_size_in_kb; 2072 unsigned shader_engine_tile_size; 2073 unsigned num_gpus; 2074 unsigned multi_gpu_tile_size; 2075 2076 unsigned tile_config; 2077 unsigned active_simds; 2078 }; 2079 2080 struct si_asic { 2081 unsigned max_shader_engines; 2082 unsigned max_tile_pipes; 2083 unsigned max_cu_per_sh; 2084 unsigned max_sh_per_se; 2085 unsigned max_backends_per_se; 2086 unsigned max_texture_channel_caches; 2087 unsigned max_gprs; 2088 unsigned max_gs_threads; 2089 unsigned max_hw_contexts; 2090 unsigned sc_prim_fifo_size_frontend; 2091 unsigned sc_prim_fifo_size_backend; 2092 unsigned sc_hiz_tile_fifo_size; 2093 unsigned sc_earlyz_tile_fifo_size; 2094 2095 unsigned num_tile_pipes; 2096 unsigned backend_enable_mask; 2097 unsigned backend_disable_mask_per_asic; 2098 unsigned backend_map; 2099 unsigned num_texture_channel_caches; 2100 unsigned mem_max_burst_length_bytes; 2101 unsigned mem_row_size_in_kb; 2102 unsigned shader_engine_tile_size; 2103 unsigned num_gpus; 2104 unsigned multi_gpu_tile_size; 2105 2106 unsigned tile_config; 2107 uint32_t tile_mode_array[32]; 2108 uint32_t active_cus; 2109 }; 2110 2111 struct cik_asic { 2112 unsigned max_shader_engines; 2113 unsigned max_tile_pipes; 2114 unsigned max_cu_per_sh; 2115 unsigned max_sh_per_se; 2116 unsigned max_backends_per_se; 2117 unsigned max_texture_channel_caches; 2118 unsigned max_gprs; 2119 unsigned max_gs_threads; 2120 unsigned max_hw_contexts; 2121 unsigned sc_prim_fifo_size_frontend; 2122 unsigned sc_prim_fifo_size_backend; 2123 unsigned sc_hiz_tile_fifo_size; 2124 unsigned sc_earlyz_tile_fifo_size; 2125 2126 unsigned num_tile_pipes; 2127 unsigned backend_enable_mask; 2128 unsigned backend_disable_mask_per_asic; 2129 unsigned backend_map; 2130 unsigned num_texture_channel_caches; 2131 unsigned mem_max_burst_length_bytes; 2132 unsigned mem_row_size_in_kb; 2133 unsigned shader_engine_tile_size; 2134 unsigned num_gpus; 2135 unsigned multi_gpu_tile_size; 2136 2137 unsigned tile_config; 2138 uint32_t tile_mode_array[32]; 2139 uint32_t macrotile_mode_array[16]; 2140 uint32_t active_cus; 2141 }; 2142 2143 union radeon_asic_config { 2144 struct r300_asic r300; 2145 struct r100_asic r100; 2146 struct r600_asic r600; 2147 struct rv770_asic rv770; 2148 struct evergreen_asic evergreen; 2149 struct cayman_asic cayman; 2150 struct si_asic si; 2151 struct cik_asic cik; 2152 }; 2153 2154 /* 2155 * asic initizalization from radeon_asic.c 2156 */ 2157 int radeon_asic_init(struct radeon_device *rdev); 2158 2159 2160 /* 2161 * IOCTL. 2162 */ 2163 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2164 struct drm_file *filp); 2165 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2166 struct drm_file *filp); 2167 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2168 struct drm_file *file_priv); 2169 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2170 struct drm_file *file_priv); 2171 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2172 struct drm_file *file_priv); 2173 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 2174 struct drm_file *file_priv); 2175 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2176 struct drm_file *filp); 2177 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2178 struct drm_file *filp); 2179 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2180 struct drm_file *filp); 2181 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2182 struct drm_file *filp); 2183 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2184 struct drm_file *filp); 2185 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2186 struct drm_file *filp); 2187 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2188 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2189 struct drm_file *filp); 2190 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2191 struct drm_file *filp); 2192 2193 /* VRAM scratch page for HDP bug, default vram page */ 2194 struct r600_vram_scratch { 2195 struct radeon_bo *robj; 2196 volatile uint32_t *ptr; 2197 u64 gpu_addr; 2198 }; 2199 2200 /* 2201 * ACPI 2202 */ 2203 struct radeon_atif_notification_cfg { 2204 bool enabled; 2205 int command_code; 2206 }; 2207 2208 struct radeon_atif_notifications { 2209 bool display_switch; 2210 bool expansion_mode_change; 2211 bool thermal_state; 2212 bool forced_power_state; 2213 bool system_power_state; 2214 bool display_conf_change; 2215 bool px_gfx_switch; 2216 bool brightness_change; 2217 bool dgpu_display_event; 2218 }; 2219 2220 struct radeon_atif_functions { 2221 bool system_params; 2222 bool sbios_requests; 2223 bool select_active_disp; 2224 bool lid_state; 2225 bool get_tv_standard; 2226 bool set_tv_standard; 2227 bool get_panel_expansion_mode; 2228 bool set_panel_expansion_mode; 2229 bool temperature_change; 2230 bool graphics_device_types; 2231 }; 2232 2233 struct radeon_atif { 2234 struct radeon_atif_notifications notifications; 2235 struct radeon_atif_functions functions; 2236 struct radeon_atif_notification_cfg notification_cfg; 2237 struct radeon_encoder *encoder_for_bl; 2238 }; 2239 2240 struct radeon_atcs_functions { 2241 bool get_ext_state; 2242 bool pcie_perf_req; 2243 bool pcie_dev_rdy; 2244 bool pcie_bus_width; 2245 }; 2246 2247 struct radeon_atcs { 2248 struct radeon_atcs_functions functions; 2249 }; 2250 2251 /* 2252 * Core structure, functions and helpers. 2253 */ 2254 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2255 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2256 2257 struct radeon_device { 2258 device_t dev; 2259 struct drm_device *ddev; 2260 struct pci_dev *pdev; 2261 struct lock exclusive_lock; 2262 /* ASIC */ 2263 union radeon_asic_config config; 2264 enum radeon_family family; 2265 unsigned long flags; 2266 int usec_timeout; 2267 enum radeon_pll_errata pll_errata; 2268 int num_gb_pipes; 2269 int num_z_pipes; 2270 int disp_priority; 2271 /* BIOS */ 2272 uint8_t *bios; 2273 bool is_atom_bios; 2274 uint16_t bios_header_start; 2275 struct radeon_bo *stollen_vga_memory; 2276 /* Register mmio */ 2277 resource_size_t rmmio_base; 2278 resource_size_t rmmio_size; 2279 /* protects concurrent MM_INDEX/DATA based register access */ 2280 struct spinlock mmio_idx_lock; 2281 /* protects concurrent SMC based register access */ 2282 struct spinlock smc_idx_lock; 2283 /* protects concurrent PLL register access */ 2284 struct spinlock pll_idx_lock; 2285 /* protects concurrent MC register access */ 2286 struct spinlock mc_idx_lock; 2287 /* protects concurrent PCIE register access */ 2288 struct spinlock pcie_idx_lock; 2289 /* protects concurrent PCIE_PORT register access */ 2290 struct spinlock pciep_idx_lock; 2291 /* protects concurrent PIF register access */ 2292 struct spinlock pif_idx_lock; 2293 /* protects concurrent CG register access */ 2294 struct spinlock cg_idx_lock; 2295 /* protects concurrent UVD register access */ 2296 struct spinlock uvd_idx_lock; 2297 /* protects concurrent RCU register access */ 2298 struct spinlock rcu_idx_lock; 2299 /* protects concurrent DIDT register access */ 2300 struct spinlock didt_idx_lock; 2301 /* protects concurrent ENDPOINT (audio) register access */ 2302 struct spinlock end_idx_lock; 2303 int rmmio_rid; 2304 struct resource *rmmio; 2305 radeon_rreg_t mc_rreg; 2306 radeon_wreg_t mc_wreg; 2307 radeon_rreg_t pll_rreg; 2308 radeon_wreg_t pll_wreg; 2309 uint32_t pcie_reg_mask; 2310 radeon_rreg_t pciep_rreg; 2311 radeon_wreg_t pciep_wreg; 2312 /* io port */ 2313 int rio_rid; 2314 struct resource *rio_mem; 2315 resource_size_t rio_mem_size; 2316 struct radeon_clock clock; 2317 struct radeon_mc mc; 2318 struct radeon_gart gart; 2319 struct radeon_mode_info mode_info; 2320 struct radeon_scratch scratch; 2321 struct radeon_doorbell doorbell; 2322 struct radeon_mman mman; 2323 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2324 wait_queue_head_t fence_queue; 2325 struct lock ring_lock; 2326 struct radeon_ring ring[RADEON_NUM_RINGS]; 2327 bool ib_pool_ready; 2328 struct radeon_sa_manager ring_tmp_bo; 2329 struct radeon_irq irq; 2330 struct radeon_asic *asic; 2331 struct radeon_gem gem; 2332 struct radeon_pm pm; 2333 struct radeon_uvd uvd; 2334 struct radeon_vce vce; 2335 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2336 struct radeon_wb wb; 2337 struct radeon_dummy_page dummy_page; 2338 bool shutdown; 2339 bool suspend; 2340 bool need_dma32; 2341 bool accel_working; 2342 bool fastfb_working; /* IGP feature*/ 2343 bool needs_reset, in_reset; 2344 bool fictitious_range_registered; 2345 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2346 const struct firmware *me_fw; /* all family ME firmware */ 2347 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2348 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2349 const struct firmware *mc_fw; /* NI MC firmware */ 2350 const struct firmware *ce_fw; /* SI CE firmware */ 2351 const struct firmware *mec_fw; /* CIK MEC firmware */ 2352 const struct firmware *mec2_fw; /* KV MEC2 firmware */ 2353 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2354 const struct firmware *smc_fw; /* SMC firmware */ 2355 const struct firmware *uvd_fw; /* UVD firmware */ 2356 const struct firmware *vce_fw; /* VCE firmware */ 2357 bool new_fw; 2358 struct r600_vram_scratch vram_scratch; 2359 int msi_enabled; /* msi enabled */ 2360 struct r600_ih ih; /* r6/700 interrupt ring */ 2361 struct radeon_rlc rlc; 2362 struct radeon_mec mec; 2363 struct taskqueue *tq; 2364 struct work_struct hotplug_work; 2365 struct task audio_work; 2366 int num_crtc; /* number of crtcs */ 2367 struct lock dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2368 bool has_uvd; 2369 struct r600_audio audio; /* audio stuff */ 2370 struct { 2371 ACPI_HANDLE handle; 2372 ACPI_NOTIFY_HANDLER notifier_call; 2373 } acpi; 2374 /* only one userspace can use Hyperz features or CMASK at a time */ 2375 struct drm_file *hyperz_filp; 2376 struct drm_file *cmask_filp; 2377 /* i2c buses */ 2378 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2379 /* debugfs */ 2380 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 2381 unsigned debugfs_count; 2382 /* virtual memory */ 2383 struct radeon_vm_manager vm_manager; 2384 struct spinlock gpu_clock_mutex; 2385 /* memory stats */ 2386 atomic64_t vram_usage; 2387 atomic64_t gtt_usage; 2388 atomic64_t num_bytes_moved; 2389 /* ACPI interface */ 2390 struct radeon_atif atif; 2391 struct radeon_atcs atcs; 2392 /* srbm instance registers */ 2393 struct spinlock srbm_mutex; 2394 /* clock, powergating flags */ 2395 u32 cg_flags; 2396 u32 pg_flags; 2397 2398 #ifdef PM_TODO 2399 struct dev_pm_domain vga_pm_domain; 2400 #endif 2401 bool have_disp_power_ref; 2402 u32 px_quirk_flags; 2403 2404 /* tracking pinned memory */ 2405 u64 vram_pin_size; 2406 u64 gart_pin_size; 2407 }; 2408 2409 bool radeon_is_px(struct drm_device *dev); 2410 int radeon_device_init(struct radeon_device *rdev, 2411 struct drm_device *ddev, 2412 struct pci_dev *pdev, 2413 uint32_t flags); 2414 void radeon_device_fini(struct radeon_device *rdev); 2415 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2416 2417 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2418 bool always_indirect); 2419 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2420 bool always_indirect); 2421 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2422 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2423 2424 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2425 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2426 2427 /* 2428 * Cast helper 2429 */ 2430 #define to_radeon_fence(p) ((struct radeon_fence *)(p)) 2431 2432 /* 2433 * Registers read & write functions. 2434 */ 2435 #define RREG8(reg) bus_read_1((rdev->rmmio), (reg)) 2436 #define WREG8(reg, v) bus_write_1((rdev->rmmio), (reg), v) 2437 #define RREG16(reg) bus_read_2((rdev->rmmio), (reg)) 2438 #define WREG16(reg, v) bus_write_2((rdev->rmmio), (reg), v) 2439 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2440 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2441 #define DREG32(reg) DRM_INFO("REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) 2442 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2443 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2444 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2445 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2446 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2447 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2448 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2449 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2450 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2451 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2452 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2453 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2454 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2455 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2456 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2457 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2458 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2459 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2460 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2461 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2462 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2463 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2464 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2465 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2466 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2467 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2468 #define WREG32_P(reg, val, mask) \ 2469 do { \ 2470 uint32_t tmp_ = RREG32(reg); \ 2471 tmp_ &= (mask); \ 2472 tmp_ |= ((val) & ~(mask)); \ 2473 WREG32(reg, tmp_); \ 2474 } while (0) 2475 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2476 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2477 #define WREG32_PLL_P(reg, val, mask) \ 2478 do { \ 2479 uint32_t tmp_ = RREG32_PLL(reg); \ 2480 tmp_ &= (mask); \ 2481 tmp_ |= ((val) & ~(mask)); \ 2482 WREG32_PLL(reg, tmp_); \ 2483 } while (0) 2484 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2485 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2486 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2487 2488 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2489 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2490 2491 /* 2492 * Indirect registers accessor 2493 */ 2494 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 2495 { 2496 uint32_t r; 2497 2498 spin_lock(&rdev->pcie_idx_lock); 2499 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2500 r = RREG32(RADEON_PCIE_DATA); 2501 spin_unlock(&rdev->pcie_idx_lock); 2502 return r; 2503 } 2504 2505 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2506 { 2507 spin_lock(&rdev->pcie_idx_lock); 2508 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2509 WREG32(RADEON_PCIE_DATA, (v)); 2510 spin_unlock(&rdev->pcie_idx_lock); 2511 } 2512 2513 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) 2514 { 2515 u32 r; 2516 2517 spin_lock(&rdev->smc_idx_lock); 2518 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2519 r = RREG32(TN_SMC_IND_DATA_0); 2520 spin_unlock(&rdev->smc_idx_lock); 2521 return r; 2522 } 2523 2524 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2525 { 2526 spin_lock(&rdev->smc_idx_lock); 2527 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2528 WREG32(TN_SMC_IND_DATA_0, (v)); 2529 spin_unlock(&rdev->smc_idx_lock); 2530 } 2531 2532 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) 2533 { 2534 u32 r; 2535 2536 spin_lock(&rdev->rcu_idx_lock); 2537 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2538 r = RREG32(R600_RCU_DATA); 2539 spin_unlock(&rdev->rcu_idx_lock); 2540 return r; 2541 } 2542 2543 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2544 { 2545 spin_lock(&rdev->rcu_idx_lock); 2546 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2547 WREG32(R600_RCU_DATA, (v)); 2548 spin_unlock(&rdev->rcu_idx_lock); 2549 } 2550 2551 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) 2552 { 2553 u32 r; 2554 2555 spin_lock(&rdev->cg_idx_lock); 2556 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2557 r = RREG32(EVERGREEN_CG_IND_DATA); 2558 spin_unlock(&rdev->cg_idx_lock); 2559 return r; 2560 } 2561 2562 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2563 { 2564 spin_lock(&rdev->cg_idx_lock); 2565 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2566 WREG32(EVERGREEN_CG_IND_DATA, (v)); 2567 spin_unlock(&rdev->cg_idx_lock); 2568 } 2569 2570 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg) 2571 { 2572 u32 r; 2573 2574 spin_lock(&rdev->pif_idx_lock); 2575 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2576 r = RREG32(EVERGREEN_PIF_PHY0_DATA); 2577 spin_unlock(&rdev->pif_idx_lock); 2578 return r; 2579 } 2580 2581 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2582 { 2583 spin_lock(&rdev->pif_idx_lock); 2584 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2585 WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); 2586 spin_unlock(&rdev->pif_idx_lock); 2587 } 2588 2589 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg) 2590 { 2591 u32 r; 2592 2593 spin_lock(&rdev->pif_idx_lock); 2594 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2595 r = RREG32(EVERGREEN_PIF_PHY1_DATA); 2596 spin_unlock(&rdev->pif_idx_lock); 2597 return r; 2598 } 2599 2600 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2601 { 2602 spin_lock(&rdev->pif_idx_lock); 2603 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2604 WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); 2605 spin_unlock(&rdev->pif_idx_lock); 2606 } 2607 2608 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) 2609 { 2610 u32 r; 2611 2612 spin_lock(&rdev->uvd_idx_lock); 2613 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2614 r = RREG32(R600_UVD_CTX_DATA); 2615 spin_unlock(&rdev->uvd_idx_lock); 2616 return r; 2617 } 2618 2619 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2620 { 2621 spin_lock(&rdev->uvd_idx_lock); 2622 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2623 WREG32(R600_UVD_CTX_DATA, (v)); 2624 spin_unlock(&rdev->uvd_idx_lock); 2625 } 2626 2627 2628 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg) 2629 { 2630 u32 r; 2631 2632 spin_lock(&rdev->didt_idx_lock); 2633 WREG32(CIK_DIDT_IND_INDEX, (reg)); 2634 r = RREG32(CIK_DIDT_IND_DATA); 2635 spin_unlock(&rdev->didt_idx_lock); 2636 return r; 2637 } 2638 2639 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2640 { 2641 spin_lock(&rdev->didt_idx_lock); 2642 WREG32(CIK_DIDT_IND_INDEX, (reg)); 2643 WREG32(CIK_DIDT_IND_DATA, (v)); 2644 spin_unlock(&rdev->didt_idx_lock); 2645 } 2646 2647 void r100_pll_errata_after_index(struct radeon_device *rdev); 2648 2649 2650 /* 2651 * ASICs helpers. 2652 */ 2653 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2654 (rdev->pdev->device == 0x5969)) 2655 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2656 (rdev->family == CHIP_RV200) || \ 2657 (rdev->family == CHIP_RS100) || \ 2658 (rdev->family == CHIP_RS200) || \ 2659 (rdev->family == CHIP_RV250) || \ 2660 (rdev->family == CHIP_RV280) || \ 2661 (rdev->family == CHIP_RS300)) 2662 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2663 (rdev->family == CHIP_RV350) || \ 2664 (rdev->family == CHIP_R350) || \ 2665 (rdev->family == CHIP_RV380) || \ 2666 (rdev->family == CHIP_R420) || \ 2667 (rdev->family == CHIP_R423) || \ 2668 (rdev->family == CHIP_RV410) || \ 2669 (rdev->family == CHIP_RS400) || \ 2670 (rdev->family == CHIP_RS480)) 2671 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 2672 (rdev->ddev->pdev->device == 0x9443) || \ 2673 (rdev->ddev->pdev->device == 0x944B) || \ 2674 (rdev->ddev->pdev->device == 0x9506) || \ 2675 (rdev->ddev->pdev->device == 0x9509) || \ 2676 (rdev->ddev->pdev->device == 0x950F) || \ 2677 (rdev->ddev->pdev->device == 0x689C) || \ 2678 (rdev->ddev->pdev->device == 0x689D)) 2679 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2680 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2681 (rdev->family == CHIP_RS690) || \ 2682 (rdev->family == CHIP_RS740) || \ 2683 (rdev->family >= CHIP_R600)) 2684 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2685 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2686 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2687 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2688 (rdev->flags & RADEON_IS_IGP)) 2689 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2690 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2691 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2692 (rdev->flags & RADEON_IS_IGP)) 2693 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2694 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2695 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2696 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2697 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2698 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2699 (rdev->family == CHIP_MULLINS)) 2700 2701 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ 2702 (rdev->ddev->pdev->device == 0x6850) || \ 2703 (rdev->ddev->pdev->device == 0x6858) || \ 2704 (rdev->ddev->pdev->device == 0x6859) || \ 2705 (rdev->ddev->pdev->device == 0x6840) || \ 2706 (rdev->ddev->pdev->device == 0x6841) || \ 2707 (rdev->ddev->pdev->device == 0x6842) || \ 2708 (rdev->ddev->pdev->device == 0x6843)) 2709 2710 /* 2711 * BIOS helpers. 2712 */ 2713 #define RBIOS8(i) (rdev->bios[i]) 2714 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2715 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2716 2717 int radeon_combios_init(struct radeon_device *rdev); 2718 void radeon_combios_fini(struct radeon_device *rdev); 2719 int radeon_atombios_init(struct radeon_device *rdev); 2720 void radeon_atombios_fini(struct radeon_device *rdev); 2721 2722 2723 /* 2724 * RING helpers. 2725 */ 2726 2727 /** 2728 * radeon_ring_write - write a value to the ring 2729 * 2730 * @ring: radeon_ring structure holding ring information 2731 * @v: dword (dw) value to write 2732 * 2733 * Write a value to the requested ring buffer (all asics). 2734 */ 2735 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2736 { 2737 if (ring->count_dw <= 0) 2738 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); 2739 2740 ring->ring[ring->wptr++] = v; 2741 ring->wptr &= ring->ptr_mask; 2742 ring->count_dw--; 2743 ring->ring_free_dw--; 2744 } 2745 2746 /* 2747 * ASICs macro. 2748 */ 2749 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2750 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2751 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2752 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2753 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2754 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2755 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 2756 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2757 #define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f)) 2758 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2759 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2760 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) 2761 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2762 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2763 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) 2764 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2765 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2766 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2767 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2768 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2769 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2770 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm)) 2771 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2772 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2773 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2774 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2775 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2776 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2777 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2778 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2779 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2780 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2781 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2782 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2783 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) 2784 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) 2785 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) 2786 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2787 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2788 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2789 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2790 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2791 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2792 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2793 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2794 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2795 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2796 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2797 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2798 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2799 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2800 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2801 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2802 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2803 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2804 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2805 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2806 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2807 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2808 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2809 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2810 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2811 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2812 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) 2813 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) 2814 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2815 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2816 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2817 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2818 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2819 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2820 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2821 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2822 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2823 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2824 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2825 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2826 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2827 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2828 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2829 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2830 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2831 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2832 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2833 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2834 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2835 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2836 2837 /* Common functions */ 2838 /* AGP */ 2839 extern int radeon_gpu_reset(struct radeon_device *rdev); 2840 extern void radeon_pci_config_reset(struct radeon_device *rdev); 2841 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2842 extern void radeon_agp_disable(struct radeon_device *rdev); 2843 extern int radeon_modeset_init(struct radeon_device *rdev); 2844 extern void radeon_modeset_fini(struct radeon_device *rdev); 2845 extern bool radeon_card_posted(struct radeon_device *rdev); 2846 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2847 extern void radeon_update_display_priority(struct radeon_device *rdev); 2848 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2849 extern void radeon_scratch_init(struct radeon_device *rdev); 2850 extern void radeon_wb_fini(struct radeon_device *rdev); 2851 extern int radeon_wb_init(struct radeon_device *rdev); 2852 extern void radeon_wb_disable(struct radeon_device *rdev); 2853 extern void radeon_surface_init(struct radeon_device *rdev); 2854 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2855 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2856 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2857 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2858 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2859 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2860 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2861 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2862 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2863 const u32 *registers, 2864 const u32 array_size); 2865 2866 /* 2867 * vm 2868 */ 2869 int radeon_vm_manager_init(struct radeon_device *rdev); 2870 void radeon_vm_manager_fini(struct radeon_device *rdev); 2871 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2872 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2873 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev, 2874 struct radeon_vm *vm, 2875 struct list_head *head); 2876 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2877 struct radeon_vm *vm, int ring); 2878 void radeon_vm_flush(struct radeon_device *rdev, 2879 struct radeon_vm *vm, 2880 int ring); 2881 void radeon_vm_fence(struct radeon_device *rdev, 2882 struct radeon_vm *vm, 2883 struct radeon_fence *fence); 2884 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2885 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2886 struct radeon_vm *vm); 2887 int radeon_vm_clear_freed(struct radeon_device *rdev, 2888 struct radeon_vm *vm); 2889 int radeon_vm_clear_invalids(struct radeon_device *rdev, 2890 struct radeon_vm *vm); 2891 int radeon_vm_bo_update(struct radeon_device *rdev, 2892 struct radeon_bo_va *bo_va, 2893 struct ttm_mem_reg *mem); 2894 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2895 struct radeon_bo *bo); 2896 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2897 struct radeon_bo *bo); 2898 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2899 struct radeon_vm *vm, 2900 struct radeon_bo *bo); 2901 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2902 struct radeon_bo_va *bo_va, 2903 uint64_t offset, 2904 uint32_t flags); 2905 void radeon_vm_bo_rmv(struct radeon_device *rdev, 2906 struct radeon_bo_va *bo_va); 2907 2908 /* audio */ 2909 void r600_audio_update_hdmi(void *arg, int pending); 2910 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2911 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2912 void r600_audio_enable(struct radeon_device *rdev, 2913 struct r600_audio_pin *pin, 2914 u8 enable_mask); 2915 void dce6_audio_enable(struct radeon_device *rdev, 2916 struct r600_audio_pin *pin, 2917 u8 enable_mask); 2918 2919 /* 2920 * R600 vram scratch functions 2921 */ 2922 int r600_vram_scratch_init(struct radeon_device *rdev); 2923 void r600_vram_scratch_fini(struct radeon_device *rdev); 2924 2925 /* 2926 * r600 cs checking helper 2927 */ 2928 unsigned r600_mip_minify(unsigned size, unsigned level); 2929 bool r600_fmt_is_valid_color(u32 format); 2930 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2931 int r600_fmt_get_blocksize(u32 format); 2932 int r600_fmt_get_nblocksx(u32 format, u32 w); 2933 int r600_fmt_get_nblocksy(u32 format, u32 h); 2934 2935 /* 2936 * r600 functions used by radeon_encoder.c 2937 */ 2938 struct radeon_hdmi_acr { 2939 u32 clock; 2940 2941 int n_32khz; 2942 int cts_32khz; 2943 2944 int n_44_1khz; 2945 int cts_44_1khz; 2946 2947 int n_48khz; 2948 int cts_48khz; 2949 2950 }; 2951 2952 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 2953 2954 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 2955 u32 tiling_pipe_num, 2956 u32 max_rb_num, 2957 u32 total_max_rb_num, 2958 u32 enabled_rb_mask); 2959 2960 /* 2961 * evergreen functions used by radeon_encoder.c 2962 */ 2963 2964 extern int ni_init_microcode(struct radeon_device *rdev); 2965 extern int ni_mc_load_microcode(struct radeon_device *rdev); 2966 extern void ni_fini_microcode(struct radeon_device *rdev); 2967 2968 /* radeon_acpi.c */ 2969 extern int radeon_acpi_init(struct radeon_device *rdev); 2970 extern void radeon_acpi_fini(struct radeon_device *rdev); 2971 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 2972 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 2973 u8 perf_req, bool advertise); 2974 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 2975 2976 /* Prototypes added by @dumbbell. */ 2977 2978 /* atombios_encoders.c */ 2979 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 2980 struct drm_connector *drm_connector); 2981 void radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, 2982 uint32_t supported_device, u16 caps); 2983 2984 /* radeon_atombios.c */ 2985 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 2986 struct drm_display_mode *mode); 2987 2988 /* radeon_legacy_encoders.c */ 2989 void radeon_add_legacy_encoder(struct drm_device *dev, 2990 uint32_t encoder_enum, uint32_t supported_device); 2991 void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder, 2992 struct drm_connector *drm_connector); 2993 2994 /* radeon_pm.c */ 2995 void radeon_pm_acpi_event_handler(struct radeon_device *rdev); 2996 2997 /* radeon_ttm.c */ 2998 int radeon_ttm_init(struct radeon_device *rdev); 2999 void radeon_ttm_fini(struct radeon_device *rdev); 3000 3001 /* r600.c */ 3002 int r600_ih_ring_alloc(struct radeon_device *rdev); 3003 void r600_ih_ring_fini(struct radeon_device *rdev); 3004 3005 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 3006 struct radeon_cs_packet *pkt, 3007 unsigned idx); 3008 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 3009 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 3010 struct radeon_cs_packet *pkt); 3011 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 3012 struct radeon_cs_reloc **cs_reloc, 3013 int nomm); 3014 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 3015 uint32_t *vline_start_end, 3016 uint32_t *vline_status); 3017 3018 #include "radeon_object.h" 3019 3020 #endif 3021