1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * 28 * $FreeBSD: head/sys/dev/drm2/radeon/radeon.h 254885 2013-08-25 19:37:15Z dumbbell $ 29 */ 30 31 #ifndef __RADEON_H__ 32 #define __RADEON_H__ 33 34 /* TODO: Here are things that needs to be done : 35 * - surface allocator & initializer : (bit like scratch reg) should 36 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 37 * related to surface 38 * - WB : write back stuff (do it bit like scratch reg things) 39 * - Vblank : look at Jesse's rework and what we should do 40 * - r600/r700: gart & cp 41 * - cs : clean cs ioctl use bitmap & things like that. 42 * - power management stuff 43 * - Barrier in gart code 44 * - Unmappabled vram ? 45 * - TESTING, TESTING, TESTING 46 */ 47 48 /* Initialization path: 49 * We expect that acceleration initialization might fail for various 50 * reasons even thought we work hard to make it works on most 51 * configurations. In order to still have a working userspace in such 52 * situation the init path must succeed up to the memory controller 53 * initialization point. Failure before this point are considered as 54 * fatal error. Here is the init callchain : 55 * radeon_device_init perform common structure, mutex initialization 56 * asic_init setup the GPU memory layout and perform all 57 * one time initialization (failure in this 58 * function are considered fatal) 59 * asic_startup setup the GPU acceleration, in order to 60 * follow guideline the first thing this 61 * function should do is setting the GPU 62 * memory controller (only MC setup failure 63 * are considered as fatal) 64 */ 65 66 #include <sys/condvar.h> 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/linker.h> 70 #include <sys/firmware.h> 71 72 #include <contrib/dev/acpica/source/include/acpi.h> 73 #include <dev/acpica/acpivar.h> 74 75 #include <drm/ttm/ttm_bo_api.h> 76 #include <drm/ttm/ttm_bo_driver.h> 77 #include <drm/ttm/ttm_placement.h> 78 #include <drm/ttm/ttm_module.h> 79 #include <drm/ttm/ttm_execbuf_util.h> 80 81 #include "radeon_family.h" 82 #include "radeon_mode.h" 83 #include "radeon_reg.h" 84 85 /* 86 * Modules parameters. 87 */ 88 extern int radeon_no_wb; 89 extern int radeon_modeset; 90 extern int radeon_dynclks; 91 extern int radeon_r4xx_atom; 92 extern int radeon_agpmode; 93 extern int radeon_vram_limit; 94 extern int radeon_gart_size; 95 extern int radeon_benchmarking; 96 extern int radeon_testing; 97 extern int radeon_connector_table; 98 extern int radeon_tv; 99 extern int radeon_audio; 100 extern int radeon_disp_priority; 101 extern int radeon_hw_i2c; 102 extern int radeon_pcie_gen2; 103 extern int radeon_msi; 104 extern int radeon_lockup_timeout; 105 106 /* 107 * Copy from radeon_drv.h so we don't have to include both and have conflicting 108 * symbol; 109 */ 110 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 111 #define RADEON_FENCE_JIFFIES_TIMEOUT (DRM_HZ / 2) 112 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 113 #define RADEON_IB_POOL_SIZE 16 114 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 115 #define RADEONFB_CONN_LIMIT 4 116 #define RADEON_BIOS_NUM_SCRATCH 8 117 118 /* max number of rings */ 119 #define RADEON_NUM_RINGS 5 120 121 /* fence seq are set to this number when signaled */ 122 #define RADEON_FENCE_SIGNALED_SEQ 0LL 123 124 /* internal ring indices */ 125 /* r1xx+ has gfx CP ring */ 126 #define RADEON_RING_TYPE_GFX_INDEX 0 127 128 /* cayman has 2 compute CP rings */ 129 #define CAYMAN_RING_TYPE_CP1_INDEX 1 130 #define CAYMAN_RING_TYPE_CP2_INDEX 2 131 132 /* R600+ has an async dma ring */ 133 #define R600_RING_TYPE_DMA_INDEX 3 134 /* cayman add a second async dma ring */ 135 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 136 137 /* hardcode those limit for now */ 138 #define RADEON_VA_IB_OFFSET (1 << 20) 139 #define RADEON_VA_RESERVED_SIZE (8 << 20) 140 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 141 142 /* reset flags */ 143 #define RADEON_RESET_GFX (1 << 0) 144 #define RADEON_RESET_COMPUTE (1 << 1) 145 #define RADEON_RESET_DMA (1 << 2) 146 #define RADEON_RESET_CP (1 << 3) 147 #define RADEON_RESET_GRBM (1 << 4) 148 #define RADEON_RESET_DMA1 (1 << 5) 149 #define RADEON_RESET_RLC (1 << 6) 150 #define RADEON_RESET_SEM (1 << 7) 151 #define RADEON_RESET_IH (1 << 8) 152 #define RADEON_RESET_VMC (1 << 9) 153 #define RADEON_RESET_MC (1 << 10) 154 #define RADEON_RESET_DISPLAY (1 << 11) 155 156 /* 157 * Errata workarounds. 158 */ 159 enum radeon_pll_errata { 160 CHIP_ERRATA_R300_CG = 0x00000001, 161 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 162 CHIP_ERRATA_PLL_DELAY = 0x00000004 163 }; 164 165 166 struct radeon_device; 167 168 169 /* 170 * BIOS. 171 */ 172 bool radeon_get_bios(struct radeon_device *rdev); 173 174 /* 175 * Dummy page 176 */ 177 struct radeon_dummy_page { 178 drm_dma_handle_t *dmah; 179 dma_addr_t addr; 180 }; 181 int radeon_dummy_page_init(struct radeon_device *rdev); 182 void radeon_dummy_page_fini(struct radeon_device *rdev); 183 184 185 /* 186 * Clocks 187 */ 188 struct radeon_clock { 189 struct radeon_pll p1pll; 190 struct radeon_pll p2pll; 191 struct radeon_pll dcpll; 192 struct radeon_pll spll; 193 struct radeon_pll mpll; 194 /* 10 Khz units */ 195 uint32_t default_mclk; 196 uint32_t default_sclk; 197 uint32_t default_dispclk; 198 uint32_t dp_extclk; 199 uint32_t max_pixel_clock; 200 }; 201 202 /* 203 * Power management 204 */ 205 int radeon_pm_init(struct radeon_device *rdev); 206 void radeon_pm_fini(struct radeon_device *rdev); 207 void radeon_pm_compute_clocks(struct radeon_device *rdev); 208 void radeon_pm_suspend(struct radeon_device *rdev); 209 void radeon_pm_resume(struct radeon_device *rdev); 210 void radeon_combios_get_power_modes(struct radeon_device *rdev); 211 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 212 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 213 void rs690_pm_info(struct radeon_device *rdev); 214 extern int rv6xx_get_temp(struct radeon_device *rdev); 215 extern int rv770_get_temp(struct radeon_device *rdev); 216 extern int evergreen_get_temp(struct radeon_device *rdev); 217 extern int sumo_get_temp(struct radeon_device *rdev); 218 extern int si_get_temp(struct radeon_device *rdev); 219 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 220 unsigned *bankh, unsigned *mtaspect, 221 unsigned *tile_split); 222 223 /* 224 * Fences. 225 */ 226 struct radeon_fence_driver { 227 uint32_t scratch_reg; 228 uint64_t gpu_addr; 229 volatile uint32_t *cpu_addr; 230 /* sync_seq is protected by ring emission lock */ 231 uint64_t sync_seq[RADEON_NUM_RINGS]; 232 atomic64_t last_seq; 233 unsigned long last_activity; 234 bool initialized; 235 }; 236 237 struct radeon_fence { 238 struct radeon_device *rdev; 239 unsigned int kref; 240 /* protected by radeon_fence.lock */ 241 uint64_t seq; 242 /* RB, DMA, etc. */ 243 unsigned ring; 244 }; 245 246 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 247 int radeon_fence_driver_init(struct radeon_device *rdev); 248 void radeon_fence_driver_fini(struct radeon_device *rdev); 249 void radeon_fence_driver_force_completion(struct radeon_device *rdev); 250 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 251 void radeon_fence_process(struct radeon_device *rdev, int ring); 252 bool radeon_fence_signaled(struct radeon_fence *fence); 253 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 254 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring); 255 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring); 256 int radeon_fence_wait_any(struct radeon_device *rdev, 257 struct radeon_fence **fences, 258 bool intr); 259 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 260 void radeon_fence_unref(struct radeon_fence **fence); 261 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 262 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 263 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 264 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 265 struct radeon_fence *b) 266 { 267 if (!a) { 268 return b; 269 } 270 271 if (!b) { 272 return a; 273 } 274 275 KASSERT(a->ring == b->ring, ("\"a\" and \"b\" belongs to different rings")); 276 277 if (a->seq > b->seq) { 278 return a; 279 } else { 280 return b; 281 } 282 } 283 284 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 285 struct radeon_fence *b) 286 { 287 if (!a) { 288 return false; 289 } 290 291 if (!b) { 292 return true; 293 } 294 295 KASSERT(a->ring == b->ring, ("\"a\" and \"b\" belongs to different rings")); 296 297 return a->seq < b->seq; 298 } 299 300 /* 301 * Tiling registers 302 */ 303 struct radeon_surface_reg { 304 struct radeon_bo *bo; 305 }; 306 307 #define RADEON_GEM_MAX_SURFACES 8 308 309 /* 310 * TTM. 311 */ 312 struct radeon_mman { 313 struct ttm_bo_global_ref bo_global_ref; 314 struct drm_global_reference mem_global_ref; 315 struct ttm_bo_device bdev; 316 bool mem_global_referenced; 317 bool initialized; 318 }; 319 320 /* bo virtual address in a specific vm */ 321 struct radeon_bo_va { 322 /* protected by bo being reserved */ 323 struct list_head bo_list; 324 uint64_t soffset; 325 uint64_t eoffset; 326 uint32_t flags; 327 bool valid; 328 unsigned ref_count; 329 330 /* protected by vm mutex */ 331 struct list_head vm_list; 332 333 /* constant after initialization */ 334 struct radeon_vm *vm; 335 struct radeon_bo *bo; 336 }; 337 338 struct radeon_bo { 339 /* Protected by gem.mutex */ 340 struct list_head list; 341 /* Protected by tbo.reserved */ 342 u32 placements[3]; 343 struct ttm_placement placement; 344 struct ttm_buffer_object tbo; 345 struct ttm_bo_kmap_obj kmap; 346 unsigned pin_count; 347 void *kptr; 348 u32 tiling_flags; 349 u32 pitch; 350 int surface_reg; 351 /* list of all virtual address to which this bo 352 * is associated to 353 */ 354 struct list_head va; 355 /* Constant after initialization */ 356 struct radeon_device *rdev; 357 struct drm_gem_object gem_base; 358 359 struct ttm_bo_kmap_obj dma_buf_vmap; 360 }; 361 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 362 363 struct radeon_bo_list { 364 struct ttm_validate_buffer tv; 365 struct radeon_bo *bo; 366 uint64_t gpu_offset; 367 unsigned rdomain; 368 unsigned wdomain; 369 u32 tiling_flags; 370 }; 371 372 /* sub-allocation manager, it has to be protected by another lock. 373 * By conception this is an helper for other part of the driver 374 * like the indirect buffer or semaphore, which both have their 375 * locking. 376 * 377 * Principe is simple, we keep a list of sub allocation in offset 378 * order (first entry has offset == 0, last entry has the highest 379 * offset). 380 * 381 * When allocating new object we first check if there is room at 382 * the end total_size - (last_object_offset + last_object_size) >= 383 * alloc_size. If so we allocate new object there. 384 * 385 * When there is not enough room at the end, we start waiting for 386 * each sub object until we reach object_offset+object_size >= 387 * alloc_size, this object then become the sub object we return. 388 * 389 * Alignment can't be bigger than page size. 390 * 391 * Hole are not considered for allocation to keep things simple. 392 * Assumption is that there won't be hole (all object on same 393 * alignment). 394 */ 395 struct radeon_sa_manager { 396 struct cv wq; 397 struct lock wq_lock; 398 struct radeon_bo *bo; 399 struct list_head *hole; 400 struct list_head flist[RADEON_NUM_RINGS]; 401 struct list_head olist; 402 unsigned size; 403 uint64_t gpu_addr; 404 void *cpu_ptr; 405 uint32_t domain; 406 }; 407 408 struct radeon_sa_bo; 409 410 /* sub-allocation buffer */ 411 struct radeon_sa_bo { 412 struct list_head olist; 413 struct list_head flist; 414 struct radeon_sa_manager *manager; 415 unsigned soffset; 416 unsigned eoffset; 417 struct radeon_fence *fence; 418 }; 419 420 /* 421 * GEM objects. 422 */ 423 struct radeon_gem { 424 struct spinlock mutex; 425 struct list_head objects; 426 }; 427 428 int radeon_gem_init(struct radeon_device *rdev); 429 void radeon_gem_fini(struct radeon_device *rdev); 430 int radeon_gem_object_create(struct radeon_device *rdev, int size, 431 int alignment, int initial_domain, 432 bool discardable, bool kernel, 433 struct drm_gem_object **obj); 434 435 int radeon_mode_dumb_create(struct drm_file *file_priv, 436 struct drm_device *dev, 437 struct drm_mode_create_dumb *args); 438 int radeon_mode_dumb_mmap(struct drm_file *filp, 439 struct drm_device *dev, 440 uint32_t handle, uint64_t *offset_p); 441 int radeon_mode_dumb_destroy(struct drm_file *file_priv, 442 struct drm_device *dev, 443 uint32_t handle); 444 445 /* 446 * Semaphores. 447 */ 448 /* everything here is constant */ 449 struct radeon_semaphore { 450 struct radeon_sa_bo *sa_bo; 451 signed waiters; 452 uint64_t gpu_addr; 453 }; 454 455 int radeon_semaphore_create(struct radeon_device *rdev, 456 struct radeon_semaphore **semaphore); 457 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 458 struct radeon_semaphore *semaphore); 459 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 460 struct radeon_semaphore *semaphore); 461 int radeon_semaphore_sync_rings(struct radeon_device *rdev, 462 struct radeon_semaphore *semaphore, 463 int signaler, int waiter); 464 void radeon_semaphore_free(struct radeon_device *rdev, 465 struct radeon_semaphore **semaphore, 466 struct radeon_fence *fence); 467 468 /* 469 * GART structures, functions & helpers 470 */ 471 struct radeon_mc; 472 473 #define RADEON_GPU_PAGE_SIZE 4096 474 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 475 #define RADEON_GPU_PAGE_SHIFT 12 476 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 477 478 struct radeon_gart { 479 drm_dma_handle_t *dmah; 480 dma_addr_t table_addr; 481 struct radeon_bo *robj; 482 void *ptr; 483 unsigned num_gpu_pages; 484 unsigned num_cpu_pages; 485 unsigned table_size; 486 vm_page_t *pages; 487 dma_addr_t *pages_addr; 488 bool ready; 489 }; 490 491 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 492 void radeon_gart_table_ram_free(struct radeon_device *rdev); 493 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 494 void radeon_gart_table_vram_free(struct radeon_device *rdev); 495 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 496 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 497 int radeon_gart_init(struct radeon_device *rdev); 498 void radeon_gart_fini(struct radeon_device *rdev); 499 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 500 int pages); 501 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 502 int pages, vm_page_t *pagelist, 503 dma_addr_t *dma_addr); 504 void radeon_gart_restore(struct radeon_device *rdev); 505 506 507 /* 508 * GPU MC structures, functions & helpers 509 */ 510 struct radeon_mc { 511 resource_size_t aper_size; 512 resource_size_t aper_base; 513 resource_size_t agp_base; 514 /* for some chips with <= 32MB we need to lie 515 * about vram size near mc fb location */ 516 u64 mc_vram_size; 517 u64 visible_vram_size; 518 u64 gtt_size; 519 u64 gtt_start; 520 u64 gtt_end; 521 u64 vram_start; 522 u64 vram_end; 523 unsigned vram_width; 524 u64 real_vram_size; 525 int vram_mtrr; 526 bool vram_is_ddr; 527 bool igp_sideport_enabled; 528 u64 gtt_base_align; 529 }; 530 531 bool radeon_combios_sideport_present(struct radeon_device *rdev); 532 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 533 534 /* 535 * GPU scratch registers structures, functions & helpers 536 */ 537 struct radeon_scratch { 538 unsigned num_reg; 539 uint32_t reg_base; 540 bool free[32]; 541 uint32_t reg[32]; 542 }; 543 544 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 545 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 546 547 548 /* 549 * IRQS. 550 */ 551 552 struct radeon_unpin_work { 553 struct task work; 554 struct radeon_device *rdev; 555 int crtc_id; 556 struct radeon_fence *fence; 557 struct drm_pending_vblank_event *event; 558 struct radeon_bo *old_rbo; 559 u64 new_crtc_base; 560 }; 561 562 struct r500_irq_stat_regs { 563 u32 disp_int; 564 u32 hdmi0_status; 565 }; 566 567 struct r600_irq_stat_regs { 568 u32 disp_int; 569 u32 disp_int_cont; 570 u32 disp_int_cont2; 571 u32 d1grph_int; 572 u32 d2grph_int; 573 u32 hdmi0_status; 574 u32 hdmi1_status; 575 }; 576 577 struct evergreen_irq_stat_regs { 578 u32 disp_int; 579 u32 disp_int_cont; 580 u32 disp_int_cont2; 581 u32 disp_int_cont3; 582 u32 disp_int_cont4; 583 u32 disp_int_cont5; 584 u32 d1grph_int; 585 u32 d2grph_int; 586 u32 d3grph_int; 587 u32 d4grph_int; 588 u32 d5grph_int; 589 u32 d6grph_int; 590 u32 afmt_status1; 591 u32 afmt_status2; 592 u32 afmt_status3; 593 u32 afmt_status4; 594 u32 afmt_status5; 595 u32 afmt_status6; 596 }; 597 598 union radeon_irq_stat_regs { 599 struct r500_irq_stat_regs r500; 600 struct r600_irq_stat_regs r600; 601 struct evergreen_irq_stat_regs evergreen; 602 }; 603 604 #define RADEON_MAX_HPD_PINS 6 605 #define RADEON_MAX_CRTCS 6 606 #define RADEON_MAX_AFMT_BLOCKS 6 607 608 struct radeon_irq { 609 bool installed; 610 struct lock lock; 611 atomic_t ring_int[RADEON_NUM_RINGS]; 612 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 613 atomic_t pflip[RADEON_MAX_CRTCS]; 614 wait_queue_head_t vblank_queue; 615 bool hpd[RADEON_MAX_HPD_PINS]; 616 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 617 union radeon_irq_stat_regs stat_regs; 618 }; 619 620 int radeon_irq_kms_init(struct radeon_device *rdev); 621 void radeon_irq_kms_fini(struct radeon_device *rdev); 622 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 623 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 624 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 625 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 626 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 627 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 628 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 629 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 630 631 /* 632 * CP & rings. 633 */ 634 635 struct radeon_ib { 636 struct radeon_sa_bo *sa_bo; 637 uint32_t length_dw; 638 uint64_t gpu_addr; 639 uint32_t *ptr; 640 int ring; 641 struct radeon_fence *fence; 642 struct radeon_vm *vm; 643 bool is_const_ib; 644 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 645 struct radeon_semaphore *semaphore; 646 }; 647 648 struct radeon_ring { 649 struct radeon_bo *ring_obj; 650 volatile uint32_t *ring; 651 unsigned rptr; 652 unsigned rptr_offs; 653 unsigned rptr_reg; 654 unsigned rptr_save_reg; 655 u64 next_rptr_gpu_addr; 656 volatile u32 *next_rptr_cpu_addr; 657 unsigned wptr; 658 unsigned wptr_old; 659 unsigned wptr_reg; 660 unsigned ring_size; 661 unsigned ring_free_dw; 662 int count_dw; 663 unsigned long last_activity; 664 unsigned last_rptr; 665 uint64_t gpu_addr; 666 uint32_t align_mask; 667 uint32_t ptr_mask; 668 bool ready; 669 u32 ptr_reg_shift; 670 u32 ptr_reg_mask; 671 u32 nop; 672 u32 idx; 673 u64 last_semaphore_signal_addr; 674 u64 last_semaphore_wait_addr; 675 }; 676 677 /* 678 * VM 679 */ 680 681 /* maximum number of VMIDs */ 682 #define RADEON_NUM_VM 16 683 684 /* defines number of bits in page table versus page directory, 685 * a page is 4KB so we have 12 bits offset, 9 bits in the page 686 * table and the remaining 19 bits are in the page directory */ 687 #define RADEON_VM_BLOCK_SIZE 9 688 689 /* number of entries in page table */ 690 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE) 691 692 struct radeon_vm { 693 struct list_head list; 694 struct list_head va; 695 unsigned id; 696 697 /* contains the page directory */ 698 struct radeon_sa_bo *page_directory; 699 uint64_t pd_gpu_addr; 700 701 /* array of page tables, one for each page directory entry */ 702 struct radeon_sa_bo **page_tables; 703 704 struct lock mutex; 705 /* last fence for cs using this vm */ 706 struct radeon_fence *fence; 707 /* last flush or NULL if we still need to flush */ 708 struct radeon_fence *last_flush; 709 }; 710 711 struct radeon_vm_manager { 712 struct lock lock; 713 struct list_head lru_vm; 714 struct radeon_fence *active[RADEON_NUM_VM]; 715 struct radeon_sa_manager sa_manager; 716 uint32_t max_pfn; 717 /* number of VMIDs */ 718 unsigned nvm; 719 /* vram base address for page table entry */ 720 u64 vram_base_offset; 721 /* is vm enabled? */ 722 bool enabled; 723 }; 724 725 /* 726 * file private structure 727 */ 728 struct radeon_fpriv { 729 struct radeon_vm vm; 730 }; 731 732 /* 733 * R6xx+ IH ring 734 */ 735 struct r600_ih { 736 struct radeon_bo *ring_obj; 737 volatile uint32_t *ring; 738 unsigned rptr; 739 unsigned ring_size; 740 uint64_t gpu_addr; 741 uint32_t ptr_mask; 742 atomic_t lock; 743 bool enabled; 744 }; 745 746 struct r600_blit_cp_primitives { 747 void (*set_render_target)(struct radeon_device *rdev, int format, 748 int w, int h, u64 gpu_addr); 749 void (*cp_set_surface_sync)(struct radeon_device *rdev, 750 u32 sync_type, u32 size, 751 u64 mc_addr); 752 void (*set_shaders)(struct radeon_device *rdev); 753 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr); 754 void (*set_tex_resource)(struct radeon_device *rdev, 755 int format, int w, int h, int pitch, 756 u64 gpu_addr, u32 size); 757 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1, 758 int x2, int y2); 759 void (*draw_auto)(struct radeon_device *rdev); 760 void (*set_default_state)(struct radeon_device *rdev); 761 }; 762 763 struct r600_blit { 764 struct radeon_bo *shader_obj; 765 struct r600_blit_cp_primitives primitives; 766 int max_dim; 767 int ring_size_common; 768 int ring_size_per_loop; 769 u64 shader_gpu_addr; 770 u32 vs_offset, ps_offset; 771 u32 state_offset; 772 u32 state_len; 773 }; 774 775 /* 776 * SI RLC stuff 777 */ 778 struct si_rlc { 779 /* for power gating */ 780 struct radeon_bo *save_restore_obj; 781 uint64_t save_restore_gpu_addr; 782 /* for clear state */ 783 struct radeon_bo *clear_state_obj; 784 uint64_t clear_state_gpu_addr; 785 }; 786 787 int radeon_ib_get(struct radeon_device *rdev, int ring, 788 struct radeon_ib *ib, struct radeon_vm *vm, 789 unsigned size); 790 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 791 void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence); 792 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 793 struct radeon_ib *const_ib); 794 int radeon_ib_pool_init(struct radeon_device *rdev); 795 void radeon_ib_pool_fini(struct radeon_device *rdev); 796 int radeon_ib_ring_tests(struct radeon_device *rdev); 797 /* Ring access between begin & end cannot sleep */ 798 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 799 struct radeon_ring *ring); 800 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 801 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 802 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 803 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); 804 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); 805 void radeon_ring_undo(struct radeon_ring *ring); 806 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 807 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 808 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring); 809 void radeon_ring_lockup_update(struct radeon_ring *ring); 810 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 811 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 812 uint32_t **data); 813 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 814 unsigned size, uint32_t *data); 815 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 816 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, 817 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop); 818 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 819 820 821 /* r600 async dma */ 822 void r600_dma_stop(struct radeon_device *rdev); 823 int r600_dma_resume(struct radeon_device *rdev); 824 void r600_dma_fini(struct radeon_device *rdev); 825 826 void cayman_dma_stop(struct radeon_device *rdev); 827 int cayman_dma_resume(struct radeon_device *rdev); 828 void cayman_dma_fini(struct radeon_device *rdev); 829 830 /* 831 * CS. 832 */ 833 struct radeon_cs_reloc { 834 struct drm_gem_object *gobj; 835 struct radeon_bo *robj; 836 struct radeon_bo_list lobj; 837 uint32_t handle; 838 uint32_t flags; 839 }; 840 841 struct radeon_cs_chunk { 842 uint32_t chunk_id; 843 uint32_t length_dw; 844 int kpage_idx[2]; 845 uint32_t *kpage[2]; 846 uint32_t *kdata; 847 void __user *user_ptr; 848 int last_copied_page; 849 int last_page_index; 850 }; 851 852 struct radeon_cs_parser { 853 device_t dev; 854 struct radeon_device *rdev; 855 struct drm_file *filp; 856 /* chunks */ 857 unsigned nchunks; 858 struct radeon_cs_chunk *chunks; 859 uint64_t *chunks_array; 860 /* IB */ 861 unsigned idx; 862 /* relocations */ 863 unsigned nrelocs; 864 struct radeon_cs_reloc *relocs; 865 struct radeon_cs_reloc **relocs_ptr; 866 struct list_head validated; 867 unsigned dma_reloc_idx; 868 /* indices of various chunks */ 869 int chunk_ib_idx; 870 int chunk_relocs_idx; 871 int chunk_flags_idx; 872 int chunk_const_ib_idx; 873 struct radeon_ib ib; 874 struct radeon_ib const_ib; 875 void *track; 876 unsigned family; 877 int parser_error; 878 u32 cs_flags; 879 u32 ring; 880 s32 priority; 881 }; 882 883 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); 884 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx); 885 886 struct radeon_cs_packet { 887 unsigned idx; 888 unsigned type; 889 unsigned reg; 890 unsigned opcode; 891 int count; 892 unsigned one_reg_wr; 893 }; 894 895 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 896 struct radeon_cs_packet *pkt, 897 unsigned idx, unsigned reg); 898 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 899 struct radeon_cs_packet *pkt); 900 901 902 /* 903 * AGP 904 */ 905 int radeon_agp_init(struct radeon_device *rdev); 906 void radeon_agp_resume(struct radeon_device *rdev); 907 void radeon_agp_suspend(struct radeon_device *rdev); 908 void radeon_agp_fini(struct radeon_device *rdev); 909 910 911 /* 912 * Writeback 913 */ 914 struct radeon_wb { 915 struct radeon_bo *wb_obj; 916 volatile uint32_t *wb; 917 uint64_t gpu_addr; 918 bool enabled; 919 bool use_event; 920 }; 921 922 #define RADEON_WB_SCRATCH_OFFSET 0 923 #define RADEON_WB_RING0_NEXT_RPTR 256 924 #define RADEON_WB_CP_RPTR_OFFSET 1024 925 #define RADEON_WB_CP1_RPTR_OFFSET 1280 926 #define RADEON_WB_CP2_RPTR_OFFSET 1536 927 #define R600_WB_DMA_RPTR_OFFSET 1792 928 #define R600_WB_IH_WPTR_OFFSET 2048 929 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 930 #define R600_WB_EVENT_OFFSET 3072 931 932 /** 933 * struct radeon_pm - power management datas 934 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 935 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 936 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 937 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 938 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 939 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 940 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 941 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 942 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 943 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 944 * @needed_bandwidth: current bandwidth needs 945 * 946 * It keeps track of various data needed to take powermanagement decision. 947 * Bandwidth need is used to determine minimun clock of the GPU and memory. 948 * Equation between gpu/memory clock and available bandwidth is hw dependent 949 * (type of memory, bus size, efficiency, ...) 950 */ 951 952 enum radeon_pm_method { 953 PM_METHOD_PROFILE, 954 PM_METHOD_DYNPM, 955 }; 956 957 enum radeon_dynpm_state { 958 DYNPM_STATE_DISABLED, 959 DYNPM_STATE_MINIMUM, 960 DYNPM_STATE_PAUSED, 961 DYNPM_STATE_ACTIVE, 962 DYNPM_STATE_SUSPENDED, 963 }; 964 enum radeon_dynpm_action { 965 DYNPM_ACTION_NONE, 966 DYNPM_ACTION_MINIMUM, 967 DYNPM_ACTION_DOWNCLOCK, 968 DYNPM_ACTION_UPCLOCK, 969 DYNPM_ACTION_DEFAULT 970 }; 971 972 enum radeon_voltage_type { 973 VOLTAGE_NONE = 0, 974 VOLTAGE_GPIO, 975 VOLTAGE_VDDC, 976 VOLTAGE_SW 977 }; 978 979 enum radeon_pm_state_type { 980 POWER_STATE_TYPE_DEFAULT, 981 POWER_STATE_TYPE_POWERSAVE, 982 POWER_STATE_TYPE_BATTERY, 983 POWER_STATE_TYPE_BALANCED, 984 POWER_STATE_TYPE_PERFORMANCE, 985 }; 986 987 enum radeon_pm_profile_type { 988 PM_PROFILE_DEFAULT, 989 PM_PROFILE_AUTO, 990 PM_PROFILE_LOW, 991 PM_PROFILE_MID, 992 PM_PROFILE_HIGH, 993 }; 994 995 #define PM_PROFILE_DEFAULT_IDX 0 996 #define PM_PROFILE_LOW_SH_IDX 1 997 #define PM_PROFILE_MID_SH_IDX 2 998 #define PM_PROFILE_HIGH_SH_IDX 3 999 #define PM_PROFILE_LOW_MH_IDX 4 1000 #define PM_PROFILE_MID_MH_IDX 5 1001 #define PM_PROFILE_HIGH_MH_IDX 6 1002 #define PM_PROFILE_MAX 7 1003 1004 struct radeon_pm_profile { 1005 int dpms_off_ps_idx; 1006 int dpms_on_ps_idx; 1007 int dpms_off_cm_idx; 1008 int dpms_on_cm_idx; 1009 }; 1010 1011 enum radeon_int_thermal_type { 1012 THERMAL_TYPE_NONE, 1013 THERMAL_TYPE_RV6XX, 1014 THERMAL_TYPE_RV770, 1015 THERMAL_TYPE_EVERGREEN, 1016 THERMAL_TYPE_SUMO, 1017 THERMAL_TYPE_NI, 1018 THERMAL_TYPE_SI, 1019 }; 1020 1021 struct radeon_voltage { 1022 enum radeon_voltage_type type; 1023 /* gpio voltage */ 1024 struct radeon_gpio_rec gpio; 1025 u32 delay; /* delay in usec from voltage drop to sclk change */ 1026 bool active_high; /* voltage drop is active when bit is high */ 1027 /* VDDC voltage */ 1028 u8 vddc_id; /* index into vddc voltage table */ 1029 u8 vddci_id; /* index into vddci voltage table */ 1030 bool vddci_enabled; 1031 /* r6xx+ sw */ 1032 u16 voltage; 1033 /* evergreen+ vddci */ 1034 u16 vddci; 1035 }; 1036 1037 /* clock mode flags */ 1038 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1039 1040 struct radeon_pm_clock_info { 1041 /* memory clock */ 1042 u32 mclk; 1043 /* engine clock */ 1044 u32 sclk; 1045 /* voltage info */ 1046 struct radeon_voltage voltage; 1047 /* standardized clock flags */ 1048 u32 flags; 1049 }; 1050 1051 /* state flags */ 1052 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1053 1054 struct radeon_power_state { 1055 enum radeon_pm_state_type type; 1056 struct radeon_pm_clock_info *clock_info; 1057 /* number of valid clock modes in this power state */ 1058 int num_clock_modes; 1059 struct radeon_pm_clock_info *default_clock_mode; 1060 /* standardized state flags */ 1061 u32 flags; 1062 u32 misc; /* vbios specific flags */ 1063 u32 misc2; /* vbios specific flags */ 1064 int pcie_lanes; /* pcie lanes */ 1065 }; 1066 1067 /* 1068 * Some modes are overclocked by very low value, accept them 1069 */ 1070 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1071 1072 struct radeon_pm { 1073 struct lock mutex; 1074 /* write locked while reprogramming mclk */ 1075 struct lock mclk_lock; 1076 u32 active_crtcs; 1077 int active_crtc_count; 1078 int req_vblank; 1079 bool vblank_sync; 1080 fixed20_12 max_bandwidth; 1081 fixed20_12 igp_sideport_mclk; 1082 fixed20_12 igp_system_mclk; 1083 fixed20_12 igp_ht_link_clk; 1084 fixed20_12 igp_ht_link_width; 1085 fixed20_12 k8_bandwidth; 1086 fixed20_12 sideport_bandwidth; 1087 fixed20_12 ht_bandwidth; 1088 fixed20_12 core_bandwidth; 1089 fixed20_12 sclk; 1090 fixed20_12 mclk; 1091 fixed20_12 needed_bandwidth; 1092 struct radeon_power_state *power_state; 1093 /* number of valid power states */ 1094 int num_power_states; 1095 int current_power_state_index; 1096 int current_clock_mode_index; 1097 int requested_power_state_index; 1098 int requested_clock_mode_index; 1099 int default_power_state_index; 1100 u32 current_sclk; 1101 u32 current_mclk; 1102 u16 current_vddc; 1103 u16 current_vddci; 1104 u32 default_sclk; 1105 u32 default_mclk; 1106 u16 default_vddc; 1107 u16 default_vddci; 1108 struct radeon_i2c_chan *i2c_bus; 1109 /* selected pm method */ 1110 enum radeon_pm_method pm_method; 1111 /* dynpm power management */ 1112 #ifdef DUMBBELL_WIP 1113 struct delayed_work dynpm_idle_work; 1114 #endif /* DUMBBELL_WIP */ 1115 enum radeon_dynpm_state dynpm_state; 1116 enum radeon_dynpm_action dynpm_planned_action; 1117 unsigned long dynpm_action_timeout; 1118 bool dynpm_can_upclock; 1119 bool dynpm_can_downclock; 1120 /* profile-based power management */ 1121 enum radeon_pm_profile_type profile; 1122 int profile_index; 1123 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1124 /* internal thermal controller on rv6xx+ */ 1125 enum radeon_int_thermal_type int_thermal_type; 1126 #ifdef DUMBBELL_WIP 1127 struct device *int_hwmon_dev; 1128 #endif /* DUMBBELL_WIP */ 1129 }; 1130 1131 int radeon_pm_get_type_index(struct radeon_device *rdev, 1132 enum radeon_pm_state_type ps_type, 1133 int instance); 1134 1135 struct r600_audio { 1136 int channels; 1137 int rate; 1138 int bits_per_sample; 1139 u8 status_bits; 1140 u8 category_code; 1141 }; 1142 1143 /* 1144 * Benchmarking 1145 */ 1146 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1147 1148 1149 /* 1150 * Testing 1151 */ 1152 void radeon_test_moves(struct radeon_device *rdev); 1153 void radeon_test_ring_sync(struct radeon_device *rdev, 1154 struct radeon_ring *cpA, 1155 struct radeon_ring *cpB); 1156 void radeon_test_syncing(struct radeon_device *rdev); 1157 1158 1159 /* 1160 * Debugfs 1161 */ 1162 struct radeon_debugfs { 1163 struct drm_info_list *files; 1164 unsigned num_files; 1165 }; 1166 1167 int radeon_debugfs_add_files(struct radeon_device *rdev, 1168 struct drm_info_list *files, 1169 unsigned nfiles); 1170 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1171 1172 1173 /* 1174 * ASIC specific functions. 1175 */ 1176 struct radeon_asic { 1177 int (*init)(struct radeon_device *rdev); 1178 void (*fini)(struct radeon_device *rdev); 1179 int (*resume)(struct radeon_device *rdev); 1180 int (*suspend)(struct radeon_device *rdev); 1181 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1182 int (*asic_reset)(struct radeon_device *rdev); 1183 /* ioctl hw specific callback. Some hw might want to perform special 1184 * operation on specific ioctl. For instance on wait idle some hw 1185 * might want to perform and HDP flush through MMIO as it seems that 1186 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed 1187 * through ring. 1188 */ 1189 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); 1190 /* check if 3D engine is idle */ 1191 bool (*gui_idle)(struct radeon_device *rdev); 1192 /* wait for mc_idle */ 1193 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1194 /* get the reference clock */ 1195 u32 (*get_xclk)(struct radeon_device *rdev); 1196 /* get the gpu clock counter */ 1197 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1198 /* gart */ 1199 struct { 1200 void (*tlb_flush)(struct radeon_device *rdev); 1201 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr); 1202 } gart; 1203 struct { 1204 int (*init)(struct radeon_device *rdev); 1205 void (*fini)(struct radeon_device *rdev); 1206 1207 u32 pt_ring_index; 1208 void (*set_page)(struct radeon_device *rdev, 1209 struct radeon_ib *ib, 1210 uint64_t pe, 1211 uint64_t addr, unsigned count, 1212 uint32_t incr, uint32_t flags); 1213 } vm; 1214 /* ring specific callbacks */ 1215 struct { 1216 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1217 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1218 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1219 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1220 struct radeon_semaphore *semaphore, bool emit_wait); 1221 int (*cs_parse)(struct radeon_cs_parser *p); 1222 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1223 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1224 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1225 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1226 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 1227 } ring[RADEON_NUM_RINGS]; 1228 /* irqs */ 1229 struct { 1230 int (*set)(struct radeon_device *rdev); 1231 irqreturn_t (*process)(struct radeon_device *rdev); 1232 } irq; 1233 /* displays */ 1234 struct { 1235 /* display watermarks */ 1236 void (*bandwidth_update)(struct radeon_device *rdev); 1237 /* get frame count */ 1238 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1239 /* wait for vblank */ 1240 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1241 /* set backlight level */ 1242 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1243 /* get backlight level */ 1244 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1245 } display; 1246 /* copy functions for bo handling */ 1247 struct { 1248 int (*blit)(struct radeon_device *rdev, 1249 uint64_t src_offset, 1250 uint64_t dst_offset, 1251 unsigned num_gpu_pages, 1252 struct radeon_fence **fence); 1253 u32 blit_ring_index; 1254 int (*dma)(struct radeon_device *rdev, 1255 uint64_t src_offset, 1256 uint64_t dst_offset, 1257 unsigned num_gpu_pages, 1258 struct radeon_fence **fence); 1259 u32 dma_ring_index; 1260 /* method used for bo copy */ 1261 int (*copy)(struct radeon_device *rdev, 1262 uint64_t src_offset, 1263 uint64_t dst_offset, 1264 unsigned num_gpu_pages, 1265 struct radeon_fence **fence); 1266 /* ring used for bo copies */ 1267 u32 copy_ring_index; 1268 } copy; 1269 /* surfaces */ 1270 struct { 1271 int (*set_reg)(struct radeon_device *rdev, int reg, 1272 uint32_t tiling_flags, uint32_t pitch, 1273 uint32_t offset, uint32_t obj_size); 1274 void (*clear_reg)(struct radeon_device *rdev, int reg); 1275 } surface; 1276 /* hotplug detect */ 1277 struct { 1278 void (*init)(struct radeon_device *rdev); 1279 void (*fini)(struct radeon_device *rdev); 1280 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1281 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1282 } hpd; 1283 /* power management */ 1284 struct { 1285 void (*misc)(struct radeon_device *rdev); 1286 void (*prepare)(struct radeon_device *rdev); 1287 void (*finish)(struct radeon_device *rdev); 1288 void (*init_profile)(struct radeon_device *rdev); 1289 void (*get_dynpm_state)(struct radeon_device *rdev); 1290 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1291 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1292 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1293 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1294 int (*get_pcie_lanes)(struct radeon_device *rdev); 1295 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1296 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1297 } pm; 1298 /* pageflipping */ 1299 struct { 1300 void (*pre_page_flip)(struct radeon_device *rdev, int crtc); 1301 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 1302 void (*post_page_flip)(struct radeon_device *rdev, int crtc); 1303 } pflip; 1304 }; 1305 1306 /* 1307 * Asic structures 1308 */ 1309 struct r100_asic { 1310 const unsigned *reg_safe_bm; 1311 unsigned reg_safe_bm_size; 1312 u32 hdp_cntl; 1313 }; 1314 1315 struct r300_asic { 1316 const unsigned *reg_safe_bm; 1317 unsigned reg_safe_bm_size; 1318 u32 resync_scratch; 1319 u32 hdp_cntl; 1320 }; 1321 1322 struct r600_asic { 1323 unsigned max_pipes; 1324 unsigned max_tile_pipes; 1325 unsigned max_simds; 1326 unsigned max_backends; 1327 unsigned max_gprs; 1328 unsigned max_threads; 1329 unsigned max_stack_entries; 1330 unsigned max_hw_contexts; 1331 unsigned max_gs_threads; 1332 unsigned sx_max_export_size; 1333 unsigned sx_max_export_pos_size; 1334 unsigned sx_max_export_smx_size; 1335 unsigned sq_num_cf_insts; 1336 unsigned tiling_nbanks; 1337 unsigned tiling_npipes; 1338 unsigned tiling_group_size; 1339 unsigned tile_config; 1340 unsigned backend_map; 1341 }; 1342 1343 struct rv770_asic { 1344 unsigned max_pipes; 1345 unsigned max_tile_pipes; 1346 unsigned max_simds; 1347 unsigned max_backends; 1348 unsigned max_gprs; 1349 unsigned max_threads; 1350 unsigned max_stack_entries; 1351 unsigned max_hw_contexts; 1352 unsigned max_gs_threads; 1353 unsigned sx_max_export_size; 1354 unsigned sx_max_export_pos_size; 1355 unsigned sx_max_export_smx_size; 1356 unsigned sq_num_cf_insts; 1357 unsigned sx_num_of_sets; 1358 unsigned sc_prim_fifo_size; 1359 unsigned sc_hiz_tile_fifo_size; 1360 unsigned sc_earlyz_tile_fifo_fize; 1361 unsigned tiling_nbanks; 1362 unsigned tiling_npipes; 1363 unsigned tiling_group_size; 1364 unsigned tile_config; 1365 unsigned backend_map; 1366 }; 1367 1368 struct evergreen_asic { 1369 unsigned num_ses; 1370 unsigned max_pipes; 1371 unsigned max_tile_pipes; 1372 unsigned max_simds; 1373 unsigned max_backends; 1374 unsigned max_gprs; 1375 unsigned max_threads; 1376 unsigned max_stack_entries; 1377 unsigned max_hw_contexts; 1378 unsigned max_gs_threads; 1379 unsigned sx_max_export_size; 1380 unsigned sx_max_export_pos_size; 1381 unsigned sx_max_export_smx_size; 1382 unsigned sq_num_cf_insts; 1383 unsigned sx_num_of_sets; 1384 unsigned sc_prim_fifo_size; 1385 unsigned sc_hiz_tile_fifo_size; 1386 unsigned sc_earlyz_tile_fifo_size; 1387 unsigned tiling_nbanks; 1388 unsigned tiling_npipes; 1389 unsigned tiling_group_size; 1390 unsigned tile_config; 1391 unsigned backend_map; 1392 }; 1393 1394 struct cayman_asic { 1395 unsigned max_shader_engines; 1396 unsigned max_pipes_per_simd; 1397 unsigned max_tile_pipes; 1398 unsigned max_simds_per_se; 1399 unsigned max_backends_per_se; 1400 unsigned max_texture_channel_caches; 1401 unsigned max_gprs; 1402 unsigned max_threads; 1403 unsigned max_gs_threads; 1404 unsigned max_stack_entries; 1405 unsigned sx_num_of_sets; 1406 unsigned sx_max_export_size; 1407 unsigned sx_max_export_pos_size; 1408 unsigned sx_max_export_smx_size; 1409 unsigned max_hw_contexts; 1410 unsigned sq_num_cf_insts; 1411 unsigned sc_prim_fifo_size; 1412 unsigned sc_hiz_tile_fifo_size; 1413 unsigned sc_earlyz_tile_fifo_size; 1414 1415 unsigned num_shader_engines; 1416 unsigned num_shader_pipes_per_simd; 1417 unsigned num_tile_pipes; 1418 unsigned num_simds_per_se; 1419 unsigned num_backends_per_se; 1420 unsigned backend_disable_mask_per_asic; 1421 unsigned backend_map; 1422 unsigned num_texture_channel_caches; 1423 unsigned mem_max_burst_length_bytes; 1424 unsigned mem_row_size_in_kb; 1425 unsigned shader_engine_tile_size; 1426 unsigned num_gpus; 1427 unsigned multi_gpu_tile_size; 1428 1429 unsigned tile_config; 1430 }; 1431 1432 struct si_asic { 1433 unsigned max_shader_engines; 1434 unsigned max_tile_pipes; 1435 unsigned max_cu_per_sh; 1436 unsigned max_sh_per_se; 1437 unsigned max_backends_per_se; 1438 unsigned max_texture_channel_caches; 1439 unsigned max_gprs; 1440 unsigned max_gs_threads; 1441 unsigned max_hw_contexts; 1442 unsigned sc_prim_fifo_size_frontend; 1443 unsigned sc_prim_fifo_size_backend; 1444 unsigned sc_hiz_tile_fifo_size; 1445 unsigned sc_earlyz_tile_fifo_size; 1446 1447 unsigned num_tile_pipes; 1448 unsigned num_backends_per_se; 1449 unsigned backend_disable_mask_per_asic; 1450 unsigned backend_map; 1451 unsigned num_texture_channel_caches; 1452 unsigned mem_max_burst_length_bytes; 1453 unsigned mem_row_size_in_kb; 1454 unsigned shader_engine_tile_size; 1455 unsigned num_gpus; 1456 unsigned multi_gpu_tile_size; 1457 1458 unsigned tile_config; 1459 }; 1460 1461 union radeon_asic_config { 1462 struct r300_asic r300; 1463 struct r100_asic r100; 1464 struct r600_asic r600; 1465 struct rv770_asic rv770; 1466 struct evergreen_asic evergreen; 1467 struct cayman_asic cayman; 1468 struct si_asic si; 1469 }; 1470 1471 /* 1472 * asic initizalization from radeon_asic.c 1473 */ 1474 int radeon_asic_init(struct radeon_device *rdev); 1475 1476 1477 /* 1478 * IOCTL. 1479 */ 1480 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 1481 struct drm_file *filp); 1482 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 1483 struct drm_file *filp); 1484 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 1485 struct drm_file *file_priv); 1486 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 1487 struct drm_file *file_priv); 1488 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1489 struct drm_file *file_priv); 1490 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 1491 struct drm_file *file_priv); 1492 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1493 struct drm_file *filp); 1494 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 1495 struct drm_file *filp); 1496 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 1497 struct drm_file *filp); 1498 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1499 struct drm_file *filp); 1500 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 1501 struct drm_file *filp); 1502 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1503 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 1504 struct drm_file *filp); 1505 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 1506 struct drm_file *filp); 1507 1508 /* VRAM scratch page for HDP bug, default vram page */ 1509 struct r600_vram_scratch { 1510 struct radeon_bo *robj; 1511 volatile uint32_t *ptr; 1512 u64 gpu_addr; 1513 }; 1514 1515 /* 1516 * ACPI 1517 */ 1518 struct radeon_atif_notification_cfg { 1519 bool enabled; 1520 int command_code; 1521 }; 1522 1523 struct radeon_atif_notifications { 1524 bool display_switch; 1525 bool expansion_mode_change; 1526 bool thermal_state; 1527 bool forced_power_state; 1528 bool system_power_state; 1529 bool display_conf_change; 1530 bool px_gfx_switch; 1531 bool brightness_change; 1532 bool dgpu_display_event; 1533 }; 1534 1535 struct radeon_atif_functions { 1536 bool system_params; 1537 bool sbios_requests; 1538 bool select_active_disp; 1539 bool lid_state; 1540 bool get_tv_standard; 1541 bool set_tv_standard; 1542 bool get_panel_expansion_mode; 1543 bool set_panel_expansion_mode; 1544 bool temperature_change; 1545 bool graphics_device_types; 1546 }; 1547 1548 struct radeon_atif { 1549 struct radeon_atif_notifications notifications; 1550 struct radeon_atif_functions functions; 1551 struct radeon_atif_notification_cfg notification_cfg; 1552 struct radeon_encoder *encoder_for_bl; 1553 }; 1554 1555 struct radeon_atcs_functions { 1556 bool get_ext_state; 1557 bool pcie_perf_req; 1558 bool pcie_dev_rdy; 1559 bool pcie_bus_width; 1560 }; 1561 1562 struct radeon_atcs { 1563 struct radeon_atcs_functions functions; 1564 }; 1565 1566 /* 1567 * Core structure, functions and helpers. 1568 */ 1569 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 1570 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 1571 1572 struct radeon_device { 1573 device_t dev; 1574 struct drm_device *ddev; 1575 struct lock exclusive_lock; 1576 /* ASIC */ 1577 union radeon_asic_config config; 1578 enum radeon_family family; 1579 unsigned long flags; 1580 int usec_timeout; 1581 enum radeon_pll_errata pll_errata; 1582 int num_gb_pipes; 1583 int num_z_pipes; 1584 int disp_priority; 1585 /* BIOS */ 1586 uint8_t *bios; 1587 bool is_atom_bios; 1588 uint16_t bios_header_start; 1589 struct radeon_bo *stollen_vga_memory; 1590 /* Register mmio */ 1591 resource_size_t rmmio_base; 1592 resource_size_t rmmio_size; 1593 /* protects concurrent MM_INDEX/DATA based register access */ 1594 struct spinlock mmio_idx_lock; 1595 int rmmio_rid; 1596 struct resource *rmmio; 1597 radeon_rreg_t mc_rreg; 1598 radeon_wreg_t mc_wreg; 1599 radeon_rreg_t pll_rreg; 1600 radeon_wreg_t pll_wreg; 1601 uint32_t pcie_reg_mask; 1602 radeon_rreg_t pciep_rreg; 1603 radeon_wreg_t pciep_wreg; 1604 /* io port */ 1605 int rio_rid; 1606 struct resource *rio_mem; 1607 resource_size_t rio_mem_size; 1608 struct radeon_clock clock; 1609 struct radeon_mc mc; 1610 struct radeon_gart gart; 1611 struct radeon_mode_info mode_info; 1612 struct radeon_scratch scratch; 1613 struct radeon_mman mman; 1614 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 1615 wait_queue_head_t fence_queue; 1616 struct lock ring_lock; 1617 struct radeon_ring ring[RADEON_NUM_RINGS]; 1618 bool ib_pool_ready; 1619 struct radeon_sa_manager ring_tmp_bo; 1620 struct radeon_irq irq; 1621 struct radeon_asic *asic; 1622 struct radeon_gem gem; 1623 struct radeon_pm pm; 1624 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 1625 struct radeon_wb wb; 1626 struct radeon_dummy_page dummy_page; 1627 bool shutdown; 1628 bool suspend; 1629 bool need_dma32; 1630 bool accel_working; 1631 bool fictitious_range_registered; 1632 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 1633 const struct firmware *me_fw; /* all family ME firmware */ 1634 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 1635 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 1636 const struct firmware *mc_fw; /* NI MC firmware */ 1637 const struct firmware *ce_fw; /* SI CE firmware */ 1638 struct r600_blit r600_blit; 1639 struct r600_vram_scratch vram_scratch; 1640 int msi_enabled; /* msi enabled */ 1641 struct r600_ih ih; /* r6/700 interrupt ring */ 1642 struct si_rlc rlc; 1643 struct taskqueue *tq; 1644 struct task hotplug_work; 1645 struct task audio_work; 1646 int num_crtc; /* number of crtcs */ 1647 struct lock dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 1648 bool audio_enabled; 1649 struct r600_audio audio_status; /* audio stuff */ 1650 struct { 1651 ACPI_HANDLE handle; 1652 ACPI_NOTIFY_HANDLER notifier_call; 1653 } acpi; 1654 /* only one userspace can use Hyperz features or CMASK at a time */ 1655 struct drm_file *hyperz_filp; 1656 struct drm_file *cmask_filp; 1657 /* i2c buses */ 1658 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 1659 /* debugfs */ 1660 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 1661 unsigned debugfs_count; 1662 /* virtual memory */ 1663 struct radeon_vm_manager vm_manager; 1664 struct spinlock gpu_clock_mutex; 1665 /* ACPI interface */ 1666 struct radeon_atif atif; 1667 struct radeon_atcs atcs; 1668 }; 1669 1670 int radeon_device_init(struct radeon_device *rdev, 1671 struct drm_device *ddev, 1672 uint32_t flags); 1673 void radeon_device_fini(struct radeon_device *rdev); 1674 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 1675 1676 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 1677 bool always_indirect); 1678 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 1679 bool always_indirect); 1680 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 1681 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 1682 1683 /* 1684 * Cast helper 1685 */ 1686 #define to_radeon_fence(p) ((struct radeon_fence *)(p)) 1687 1688 /* 1689 * Registers read & write functions. 1690 */ 1691 #define RREG8(reg) bus_read_1((rdev->rmmio), (reg)) 1692 #define WREG8(reg, v) bus_write_1((rdev->rmmio), (reg), v) 1693 #define RREG16(reg) bus_read_2((rdev->rmmio), (reg)) 1694 #define WREG16(reg, v) bus_write_2((rdev->rmmio), (reg), v) 1695 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 1696 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 1697 #define DREG32(reg) DRM_INFO("REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) 1698 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 1699 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 1700 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1701 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1702 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 1703 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 1704 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 1705 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 1706 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 1707 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 1708 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) 1709 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 1710 #define WREG32_P(reg, val, mask) \ 1711 do { \ 1712 uint32_t tmp_ = RREG32(reg); \ 1713 tmp_ &= (mask); \ 1714 tmp_ |= ((val) & ~(mask)); \ 1715 WREG32(reg, tmp_); \ 1716 } while (0) 1717 #define WREG32_PLL_P(reg, val, mask) \ 1718 do { \ 1719 uint32_t tmp_ = RREG32_PLL(reg); \ 1720 tmp_ &= (mask); \ 1721 tmp_ |= ((val) & ~(mask)); \ 1722 WREG32_PLL(reg, tmp_); \ 1723 } while (0) 1724 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 1725 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 1726 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 1727 1728 /* 1729 * Indirect registers accessor 1730 */ 1731 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 1732 { 1733 uint32_t r; 1734 1735 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 1736 r = RREG32(RADEON_PCIE_DATA); 1737 return r; 1738 } 1739 1740 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1741 { 1742 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 1743 WREG32(RADEON_PCIE_DATA, (v)); 1744 } 1745 1746 void r100_pll_errata_after_index(struct radeon_device *rdev); 1747 1748 1749 /* 1750 * ASICs helpers. 1751 */ 1752 #define ASIC_IS_RN50(rdev) ((rdev->ddev->pci_device == 0x515e) || \ 1753 (rdev->ddev->pci_device == 0x5969)) 1754 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 1755 (rdev->family == CHIP_RV200) || \ 1756 (rdev->family == CHIP_RS100) || \ 1757 (rdev->family == CHIP_RS200) || \ 1758 (rdev->family == CHIP_RV250) || \ 1759 (rdev->family == CHIP_RV280) || \ 1760 (rdev->family == CHIP_RS300)) 1761 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 1762 (rdev->family == CHIP_RV350) || \ 1763 (rdev->family == CHIP_R350) || \ 1764 (rdev->family == CHIP_RV380) || \ 1765 (rdev->family == CHIP_R420) || \ 1766 (rdev->family == CHIP_R423) || \ 1767 (rdev->family == CHIP_RV410) || \ 1768 (rdev->family == CHIP_RS400) || \ 1769 (rdev->family == CHIP_RS480)) 1770 #define ASIC_IS_X2(rdev) ((rdev->ddev->pci_device == 0x9441) || \ 1771 (rdev->ddev->pci_device == 0x9443) || \ 1772 (rdev->ddev->pci_device == 0x944B) || \ 1773 (rdev->ddev->pci_device == 0x9506) || \ 1774 (rdev->ddev->pci_device == 0x9509) || \ 1775 (rdev->ddev->pci_device == 0x950F) || \ 1776 (rdev->ddev->pci_device == 0x689C) || \ 1777 (rdev->ddev->pci_device == 0x689D)) 1778 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 1779 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 1780 (rdev->family == CHIP_RS690) || \ 1781 (rdev->family == CHIP_RS740) || \ 1782 (rdev->family >= CHIP_R600)) 1783 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 1784 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 1785 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 1786 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 1787 (rdev->flags & RADEON_IS_IGP)) 1788 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 1789 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 1790 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 1791 (rdev->flags & RADEON_IS_IGP)) 1792 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 1793 1794 /* 1795 * BIOS helpers. 1796 */ 1797 #define RBIOS8(i) (rdev->bios[i]) 1798 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1799 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1800 1801 int radeon_combios_init(struct radeon_device *rdev); 1802 void radeon_combios_fini(struct radeon_device *rdev); 1803 int radeon_atombios_init(struct radeon_device *rdev); 1804 void radeon_atombios_fini(struct radeon_device *rdev); 1805 1806 1807 /* 1808 * RING helpers. 1809 */ 1810 #if !defined(DRM_DEBUG_CODE) || DRM_DEBUG_CODE == 0 1811 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 1812 { 1813 ring->ring[ring->wptr++] = v; 1814 ring->wptr &= ring->ptr_mask; 1815 ring->count_dw--; 1816 ring->ring_free_dw--; 1817 } 1818 #else 1819 /* With debugging this is just too big to inline */ 1820 void radeon_ring_write(struct radeon_ring *ring, uint32_t v); 1821 #endif 1822 1823 /* 1824 * ASICs macro. 1825 */ 1826 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 1827 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 1828 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 1829 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 1830 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p)) 1831 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 1832 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 1833 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 1834 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) 1835 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 1836 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 1837 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 1838 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp)) 1839 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp)) 1840 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp)) 1841 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib)) 1842 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib)) 1843 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp)) 1844 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm)) 1845 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 1846 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 1847 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 1848 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 1849 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 1850 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence)) 1851 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 1852 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) 1853 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) 1854 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) 1855 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 1856 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 1857 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 1858 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 1859 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 1860 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 1861 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 1862 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 1863 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 1864 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 1865 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 1866 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 1867 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 1868 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 1869 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 1870 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 1871 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 1872 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 1873 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 1874 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 1875 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 1876 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 1877 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 1878 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc)) 1879 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) 1880 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc)) 1881 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 1882 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 1883 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 1884 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 1885 1886 /* Common functions */ 1887 /* AGP */ 1888 extern int radeon_gpu_reset(struct radeon_device *rdev); 1889 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 1890 extern void radeon_agp_disable(struct radeon_device *rdev); 1891 extern int radeon_modeset_init(struct radeon_device *rdev); 1892 extern void radeon_modeset_fini(struct radeon_device *rdev); 1893 extern bool radeon_card_posted(struct radeon_device *rdev); 1894 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 1895 extern void radeon_update_display_priority(struct radeon_device *rdev); 1896 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 1897 extern void radeon_scratch_init(struct radeon_device *rdev); 1898 extern void radeon_wb_fini(struct radeon_device *rdev); 1899 extern int radeon_wb_init(struct radeon_device *rdev); 1900 extern void radeon_wb_disable(struct radeon_device *rdev); 1901 extern void radeon_surface_init(struct radeon_device *rdev); 1902 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 1903 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 1904 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 1905 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 1906 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 1907 extern int radeon_resume_kms(struct drm_device *dev); 1908 extern int radeon_suspend_kms(struct drm_device *dev); 1909 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 1910 1911 /* 1912 * vm 1913 */ 1914 int radeon_vm_manager_init(struct radeon_device *rdev); 1915 void radeon_vm_manager_fini(struct radeon_device *rdev); 1916 void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 1917 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 1918 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm); 1919 void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm); 1920 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 1921 struct radeon_vm *vm, int ring); 1922 void radeon_vm_fence(struct radeon_device *rdev, 1923 struct radeon_vm *vm, 1924 struct radeon_fence *fence); 1925 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 1926 int radeon_vm_bo_update_pte(struct radeon_device *rdev, 1927 struct radeon_vm *vm, 1928 struct radeon_bo *bo, 1929 struct ttm_mem_reg *mem); 1930 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 1931 struct radeon_bo *bo); 1932 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 1933 struct radeon_bo *bo); 1934 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 1935 struct radeon_vm *vm, 1936 struct radeon_bo *bo); 1937 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 1938 struct radeon_bo_va *bo_va, 1939 uint64_t offset, 1940 uint32_t flags); 1941 int radeon_vm_bo_rmv(struct radeon_device *rdev, 1942 struct radeon_bo_va *bo_va); 1943 1944 /* audio */ 1945 void r600_audio_update_hdmi(void *arg, int pending); 1946 1947 /* 1948 * R600 vram scratch functions 1949 */ 1950 int r600_vram_scratch_init(struct radeon_device *rdev); 1951 void r600_vram_scratch_fini(struct radeon_device *rdev); 1952 1953 /* 1954 * r600 cs checking helper 1955 */ 1956 unsigned r600_mip_minify(unsigned size, unsigned level); 1957 bool r600_fmt_is_valid_color(u32 format); 1958 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 1959 int r600_fmt_get_blocksize(u32 format); 1960 int r600_fmt_get_nblocksx(u32 format, u32 w); 1961 int r600_fmt_get_nblocksy(u32 format, u32 h); 1962 1963 /* 1964 * r600 functions used by radeon_encoder.c 1965 */ 1966 struct radeon_hdmi_acr { 1967 u32 clock; 1968 1969 int n_32khz; 1970 int cts_32khz; 1971 1972 int n_44_1khz; 1973 int cts_44_1khz; 1974 1975 int n_48khz; 1976 int cts_48khz; 1977 1978 }; 1979 1980 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 1981 1982 extern void r600_hdmi_enable(struct drm_encoder *encoder); 1983 extern void r600_hdmi_disable(struct drm_encoder *encoder); 1984 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 1985 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 1986 u32 tiling_pipe_num, 1987 u32 max_rb_num, 1988 u32 total_max_rb_num, 1989 u32 enabled_rb_mask); 1990 1991 /* 1992 * evergreen functions used by radeon_encoder.c 1993 */ 1994 1995 extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 1996 1997 extern int ni_init_microcode(struct radeon_device *rdev); 1998 extern int ni_mc_load_microcode(struct radeon_device *rdev); 1999 extern void ni_fini_microcode(struct radeon_device *rdev); 2000 2001 /* radeon_acpi.c */ 2002 extern int radeon_acpi_init(struct radeon_device *rdev); 2003 extern void radeon_acpi_fini(struct radeon_device *rdev); 2004 2005 /* Prototypes added by @dumbbell. */ 2006 2007 /* atombios_encoders.c */ 2008 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 2009 struct drm_connector *drm_connector); 2010 void radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, 2011 uint32_t supported_device, u16 caps); 2012 2013 /* radeon_atombios.c */ 2014 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 2015 struct drm_display_mode *mode); 2016 2017 /* radeon_combios.c */ 2018 void radeon_combios_connected_scratch_regs(struct drm_connector *connector, 2019 struct drm_encoder *encoder, bool connected); 2020 2021 /* radeon_connectors.c */ 2022 void radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 2023 struct drm_encoder *encoder, bool connected); 2024 void radeon_add_legacy_connector(struct drm_device *dev, 2025 uint32_t connector_id, 2026 uint32_t supported_device, 2027 int connector_type, 2028 struct radeon_i2c_bus_rec *i2c_bus, 2029 uint16_t connector_object_id, 2030 struct radeon_hpd *hpd); 2031 void radeon_add_atom_connector(struct drm_device *dev, 2032 uint32_t connector_id, 2033 uint32_t supported_device, 2034 int connector_type, 2035 struct radeon_i2c_bus_rec *i2c_bus, 2036 uint32_t igp_lane_info, 2037 uint16_t connector_object_id, 2038 struct radeon_hpd *hpd, 2039 struct radeon_router *router); 2040 2041 /* radeon_encoders.c */ 2042 uint32_t radeon_get_encoder_enum(struct drm_device *dev, 2043 uint32_t supported_device, uint8_t dac); 2044 void radeon_link_encoder_connector(struct drm_device *dev); 2045 2046 /* radeon_legacy_encoders.c */ 2047 void radeon_add_legacy_encoder(struct drm_device *dev, 2048 uint32_t encoder_enum, uint32_t supported_device); 2049 void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder, 2050 struct drm_connector *drm_connector); 2051 2052 /* radeon_pm.c */ 2053 void radeon_pm_acpi_event_handler(struct radeon_device *rdev); 2054 2055 /* radeon_ttm.c */ 2056 int radeon_ttm_init(struct radeon_device *rdev); 2057 void radeon_ttm_fini(struct radeon_device *rdev); 2058 2059 /* r600.c */ 2060 int r600_ih_ring_alloc(struct radeon_device *rdev); 2061 void r600_ih_ring_fini(struct radeon_device *rdev); 2062 2063 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 2064 struct radeon_cs_packet *pkt, 2065 unsigned idx); 2066 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 2067 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 2068 struct radeon_cs_packet *pkt); 2069 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 2070 struct radeon_cs_reloc **cs_reloc, 2071 int nomm); 2072 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 2073 uint32_t *vline_start_end, 2074 uint32_t *vline_status); 2075 2076 #include "radeon_object.h" 2077 2078 #endif 2079