1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <drm/drmP.h> 30 #include <drm/drm_crtc_helper.h> 31 #include <drm/radeon_drm.h> 32 #include "radeon_reg.h" 33 #include "radeon.h" 34 #include "radeon_asic.h" 35 #include "atom.h" 36 #include "rv770_dpm.h" 37 #include "ni_dpm.h" 38 39 /* 40 * Registers accessors functions. 41 */ 42 /** 43 * radeon_invalid_rreg - dummy reg read function 44 * 45 * @rdev: radeon device pointer 46 * @reg: offset of register 47 * 48 * Dummy register read function. Used for register blocks 49 * that certain asics don't have (all asics). 50 * Returns the value in the register. 51 */ 52 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) 53 { 54 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); 55 BUG_ON(1); 56 return 0; 57 } 58 59 /** 60 * radeon_invalid_wreg - dummy reg write function 61 * 62 * @rdev: radeon device pointer 63 * @reg: offset of register 64 * @v: value to write to the register 65 * 66 * Dummy register read function. Used for register blocks 67 * that certain asics don't have (all asics). 68 */ 69 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 70 { 71 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", 72 reg, v); 73 BUG_ON(1); 74 } 75 76 /** 77 * radeon_register_accessor_init - sets up the register accessor callbacks 78 * 79 * @rdev: radeon device pointer 80 * 81 * Sets up the register accessor callbacks for various register 82 * apertures. Not all asics have all apertures (all asics). 83 */ 84 static void radeon_register_accessor_init(struct radeon_device *rdev) 85 { 86 rdev->mc_rreg = &radeon_invalid_rreg; 87 rdev->mc_wreg = &radeon_invalid_wreg; 88 rdev->pll_rreg = &radeon_invalid_rreg; 89 rdev->pll_wreg = &radeon_invalid_wreg; 90 rdev->pciep_rreg = &radeon_invalid_rreg; 91 rdev->pciep_wreg = &radeon_invalid_wreg; 92 93 /* Don't change order as we are overridding accessor. */ 94 if (rdev->family < CHIP_RV515) { 95 rdev->pcie_reg_mask = 0xff; 96 } else { 97 rdev->pcie_reg_mask = 0x7ff; 98 } 99 /* FIXME: not sure here */ 100 if (rdev->family <= CHIP_R580) { 101 rdev->pll_rreg = &r100_pll_rreg; 102 rdev->pll_wreg = &r100_pll_wreg; 103 } 104 if (rdev->family >= CHIP_R420) { 105 rdev->mc_rreg = &r420_mc_rreg; 106 rdev->mc_wreg = &r420_mc_wreg; 107 } 108 if (rdev->family >= CHIP_RV515) { 109 rdev->mc_rreg = &rv515_mc_rreg; 110 rdev->mc_wreg = &rv515_mc_wreg; 111 } 112 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { 113 rdev->mc_rreg = &rs400_mc_rreg; 114 rdev->mc_wreg = &rs400_mc_wreg; 115 } 116 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 117 rdev->mc_rreg = &rs690_mc_rreg; 118 rdev->mc_wreg = &rs690_mc_wreg; 119 } 120 if (rdev->family == CHIP_RS600) { 121 rdev->mc_rreg = &rs600_mc_rreg; 122 rdev->mc_wreg = &rs600_mc_wreg; 123 } 124 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { 125 rdev->mc_rreg = &rs780_mc_rreg; 126 rdev->mc_wreg = &rs780_mc_wreg; 127 } 128 129 if (rdev->family >= CHIP_BONAIRE) { 130 rdev->pciep_rreg = &cik_pciep_rreg; 131 rdev->pciep_wreg = &cik_pciep_wreg; 132 } else if (rdev->family >= CHIP_R600) { 133 rdev->pciep_rreg = &r600_pciep_rreg; 134 rdev->pciep_wreg = &r600_pciep_wreg; 135 } 136 } 137 138 139 /* helper to disable agp */ 140 /** 141 * radeon_agp_disable - AGP disable helper function 142 * 143 * @rdev: radeon device pointer 144 * 145 * Removes AGP flags and changes the gart callbacks on AGP 146 * cards when using the internal gart rather than AGP (all asics). 147 */ 148 void radeon_agp_disable(struct radeon_device *rdev) 149 { 150 rdev->flags &= ~RADEON_IS_AGP; 151 if (rdev->family >= CHIP_R600) { 152 DRM_INFO("Forcing AGP to PCIE mode\n"); 153 rdev->flags |= RADEON_IS_PCIE; 154 } else if (rdev->family >= CHIP_RV515 || 155 rdev->family == CHIP_RV380 || 156 rdev->family == CHIP_RV410 || 157 rdev->family == CHIP_R423) { 158 DRM_INFO("Forcing AGP to PCIE mode\n"); 159 rdev->flags |= RADEON_IS_PCIE; 160 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; 161 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; 162 } else { 163 DRM_INFO("Forcing AGP to PCI mode\n"); 164 rdev->flags |= RADEON_IS_PCI; 165 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; 166 rdev->asic->gart.set_page = &r100_pci_gart_set_page; 167 } 168 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 169 } 170 171 /* 172 * ASIC 173 */ 174 175 static struct radeon_asic_ring r100_gfx_ring = { 176 .ib_execute = &r100_ring_ib_execute, 177 .emit_fence = &r100_fence_ring_emit, 178 .emit_semaphore = &r100_semaphore_ring_emit, 179 .cs_parse = &r100_cs_parse, 180 .ring_start = &r100_ring_start, 181 .ring_test = &r100_ring_test, 182 .ib_test = &r100_ib_test, 183 .is_lockup = &r100_gpu_is_lockup, 184 .get_rptr = &r100_gfx_get_rptr, 185 .get_wptr = &r100_gfx_get_wptr, 186 .set_wptr = &r100_gfx_set_wptr, 187 }; 188 189 static struct radeon_asic r100_asic = { 190 .init = &r100_init, 191 .fini = &r100_fini, 192 .suspend = &r100_suspend, 193 .resume = &r100_resume, 194 .vga_set_state = &r100_vga_set_state, 195 .asic_reset = &r100_asic_reset, 196 .mmio_hdp_flush = NULL, 197 .gui_idle = &r100_gui_idle, 198 .mc_wait_for_idle = &r100_mc_wait_for_idle, 199 .gart = { 200 .tlb_flush = &r100_pci_gart_tlb_flush, 201 .set_page = &r100_pci_gart_set_page, 202 }, 203 .ring = { 204 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring 205 }, 206 .irq = { 207 .set = &r100_irq_set, 208 .process = &r100_irq_process, 209 }, 210 .display = { 211 .bandwidth_update = &r100_bandwidth_update, 212 .get_vblank_counter = &r100_get_vblank_counter, 213 .wait_for_vblank = &r100_wait_for_vblank, 214 .set_backlight_level = &radeon_legacy_set_backlight_level, 215 .get_backlight_level = &radeon_legacy_get_backlight_level, 216 }, 217 .copy = { 218 .blit = &r100_copy_blit, 219 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 220 .dma = NULL, 221 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 222 .copy = &r100_copy_blit, 223 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 224 }, 225 .surface = { 226 .set_reg = r100_set_surface_reg, 227 .clear_reg = r100_clear_surface_reg, 228 }, 229 .hpd = { 230 .init = &r100_hpd_init, 231 .fini = &r100_hpd_fini, 232 .sense = &r100_hpd_sense, 233 .set_polarity = &r100_hpd_set_polarity, 234 }, 235 .pm = { 236 .misc = &r100_pm_misc, 237 .prepare = &r100_pm_prepare, 238 .finish = &r100_pm_finish, 239 .init_profile = &r100_pm_init_profile, 240 .get_dynpm_state = &r100_pm_get_dynpm_state, 241 .get_engine_clock = &radeon_legacy_get_engine_clock, 242 .set_engine_clock = &radeon_legacy_set_engine_clock, 243 .get_memory_clock = &radeon_legacy_get_memory_clock, 244 .set_memory_clock = NULL, 245 .get_pcie_lanes = NULL, 246 .set_pcie_lanes = NULL, 247 .set_clock_gating = &radeon_legacy_set_clock_gating, 248 }, 249 .pflip = { 250 .page_flip = &r100_page_flip, 251 .page_flip_pending = &r100_page_flip_pending, 252 }, 253 }; 254 255 static struct radeon_asic r200_asic = { 256 .init = &r100_init, 257 .fini = &r100_fini, 258 .suspend = &r100_suspend, 259 .resume = &r100_resume, 260 .vga_set_state = &r100_vga_set_state, 261 .asic_reset = &r100_asic_reset, 262 .mmio_hdp_flush = NULL, 263 .gui_idle = &r100_gui_idle, 264 .mc_wait_for_idle = &r100_mc_wait_for_idle, 265 .gart = { 266 .tlb_flush = &r100_pci_gart_tlb_flush, 267 .set_page = &r100_pci_gart_set_page, 268 }, 269 .ring = { 270 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring 271 }, 272 .irq = { 273 .set = &r100_irq_set, 274 .process = &r100_irq_process, 275 }, 276 .display = { 277 .bandwidth_update = &r100_bandwidth_update, 278 .get_vblank_counter = &r100_get_vblank_counter, 279 .wait_for_vblank = &r100_wait_for_vblank, 280 .set_backlight_level = &radeon_legacy_set_backlight_level, 281 .get_backlight_level = &radeon_legacy_get_backlight_level, 282 }, 283 .copy = { 284 .blit = &r100_copy_blit, 285 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 286 .dma = &r200_copy_dma, 287 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 288 .copy = &r100_copy_blit, 289 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 290 }, 291 .surface = { 292 .set_reg = r100_set_surface_reg, 293 .clear_reg = r100_clear_surface_reg, 294 }, 295 .hpd = { 296 .init = &r100_hpd_init, 297 .fini = &r100_hpd_fini, 298 .sense = &r100_hpd_sense, 299 .set_polarity = &r100_hpd_set_polarity, 300 }, 301 .pm = { 302 .misc = &r100_pm_misc, 303 .prepare = &r100_pm_prepare, 304 .finish = &r100_pm_finish, 305 .init_profile = &r100_pm_init_profile, 306 .get_dynpm_state = &r100_pm_get_dynpm_state, 307 .get_engine_clock = &radeon_legacy_get_engine_clock, 308 .set_engine_clock = &radeon_legacy_set_engine_clock, 309 .get_memory_clock = &radeon_legacy_get_memory_clock, 310 .set_memory_clock = NULL, 311 .get_pcie_lanes = NULL, 312 .set_pcie_lanes = NULL, 313 .set_clock_gating = &radeon_legacy_set_clock_gating, 314 }, 315 .pflip = { 316 .page_flip = &r100_page_flip, 317 .page_flip_pending = &r100_page_flip_pending, 318 }, 319 }; 320 321 static struct radeon_asic_ring r300_gfx_ring = { 322 .ib_execute = &r100_ring_ib_execute, 323 .emit_fence = &r300_fence_ring_emit, 324 .emit_semaphore = &r100_semaphore_ring_emit, 325 .cs_parse = &r300_cs_parse, 326 .ring_start = &r300_ring_start, 327 .ring_test = &r100_ring_test, 328 .ib_test = &r100_ib_test, 329 .is_lockup = &r100_gpu_is_lockup, 330 .get_rptr = &r100_gfx_get_rptr, 331 .get_wptr = &r100_gfx_get_wptr, 332 .set_wptr = &r100_gfx_set_wptr, 333 }; 334 335 static struct radeon_asic_ring rv515_gfx_ring = { 336 .ib_execute = &r100_ring_ib_execute, 337 .emit_fence = &r300_fence_ring_emit, 338 .emit_semaphore = &r100_semaphore_ring_emit, 339 .cs_parse = &r300_cs_parse, 340 .ring_start = &rv515_ring_start, 341 .ring_test = &r100_ring_test, 342 .ib_test = &r100_ib_test, 343 .is_lockup = &r100_gpu_is_lockup, 344 .get_rptr = &r100_gfx_get_rptr, 345 .get_wptr = &r100_gfx_get_wptr, 346 .set_wptr = &r100_gfx_set_wptr, 347 }; 348 349 static struct radeon_asic r300_asic = { 350 .init = &r300_init, 351 .fini = &r300_fini, 352 .suspend = &r300_suspend, 353 .resume = &r300_resume, 354 .vga_set_state = &r100_vga_set_state, 355 .asic_reset = &r300_asic_reset, 356 .mmio_hdp_flush = NULL, 357 .gui_idle = &r100_gui_idle, 358 .mc_wait_for_idle = &r300_mc_wait_for_idle, 359 .gart = { 360 .tlb_flush = &r100_pci_gart_tlb_flush, 361 .set_page = &r100_pci_gart_set_page, 362 }, 363 .ring = { 364 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 365 }, 366 .irq = { 367 .set = &r100_irq_set, 368 .process = &r100_irq_process, 369 }, 370 .display = { 371 .bandwidth_update = &r100_bandwidth_update, 372 .get_vblank_counter = &r100_get_vblank_counter, 373 .wait_for_vblank = &r100_wait_for_vblank, 374 .set_backlight_level = &radeon_legacy_set_backlight_level, 375 .get_backlight_level = &radeon_legacy_get_backlight_level, 376 }, 377 .copy = { 378 .blit = &r100_copy_blit, 379 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 380 .dma = &r200_copy_dma, 381 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 382 .copy = &r100_copy_blit, 383 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 384 }, 385 .surface = { 386 .set_reg = r100_set_surface_reg, 387 .clear_reg = r100_clear_surface_reg, 388 }, 389 .hpd = { 390 .init = &r100_hpd_init, 391 .fini = &r100_hpd_fini, 392 .sense = &r100_hpd_sense, 393 .set_polarity = &r100_hpd_set_polarity, 394 }, 395 .pm = { 396 .misc = &r100_pm_misc, 397 .prepare = &r100_pm_prepare, 398 .finish = &r100_pm_finish, 399 .init_profile = &r100_pm_init_profile, 400 .get_dynpm_state = &r100_pm_get_dynpm_state, 401 .get_engine_clock = &radeon_legacy_get_engine_clock, 402 .set_engine_clock = &radeon_legacy_set_engine_clock, 403 .get_memory_clock = &radeon_legacy_get_memory_clock, 404 .set_memory_clock = NULL, 405 .get_pcie_lanes = &rv370_get_pcie_lanes, 406 .set_pcie_lanes = &rv370_set_pcie_lanes, 407 .set_clock_gating = &radeon_legacy_set_clock_gating, 408 }, 409 .pflip = { 410 .page_flip = &r100_page_flip, 411 .page_flip_pending = &r100_page_flip_pending, 412 }, 413 }; 414 415 static struct radeon_asic r300_asic_pcie = { 416 .init = &r300_init, 417 .fini = &r300_fini, 418 .suspend = &r300_suspend, 419 .resume = &r300_resume, 420 .vga_set_state = &r100_vga_set_state, 421 .asic_reset = &r300_asic_reset, 422 .mmio_hdp_flush = NULL, 423 .gui_idle = &r100_gui_idle, 424 .mc_wait_for_idle = &r300_mc_wait_for_idle, 425 .gart = { 426 .tlb_flush = &rv370_pcie_gart_tlb_flush, 427 .set_page = &rv370_pcie_gart_set_page, 428 }, 429 .ring = { 430 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 431 }, 432 .irq = { 433 .set = &r100_irq_set, 434 .process = &r100_irq_process, 435 }, 436 .display = { 437 .bandwidth_update = &r100_bandwidth_update, 438 .get_vblank_counter = &r100_get_vblank_counter, 439 .wait_for_vblank = &r100_wait_for_vblank, 440 .set_backlight_level = &radeon_legacy_set_backlight_level, 441 .get_backlight_level = &radeon_legacy_get_backlight_level, 442 }, 443 .copy = { 444 .blit = &r100_copy_blit, 445 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 446 .dma = &r200_copy_dma, 447 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 448 .copy = &r100_copy_blit, 449 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 450 }, 451 .surface = { 452 .set_reg = r100_set_surface_reg, 453 .clear_reg = r100_clear_surface_reg, 454 }, 455 .hpd = { 456 .init = &r100_hpd_init, 457 .fini = &r100_hpd_fini, 458 .sense = &r100_hpd_sense, 459 .set_polarity = &r100_hpd_set_polarity, 460 }, 461 .pm = { 462 .misc = &r100_pm_misc, 463 .prepare = &r100_pm_prepare, 464 .finish = &r100_pm_finish, 465 .init_profile = &r100_pm_init_profile, 466 .get_dynpm_state = &r100_pm_get_dynpm_state, 467 .get_engine_clock = &radeon_legacy_get_engine_clock, 468 .set_engine_clock = &radeon_legacy_set_engine_clock, 469 .get_memory_clock = &radeon_legacy_get_memory_clock, 470 .set_memory_clock = NULL, 471 .get_pcie_lanes = &rv370_get_pcie_lanes, 472 .set_pcie_lanes = &rv370_set_pcie_lanes, 473 .set_clock_gating = &radeon_legacy_set_clock_gating, 474 }, 475 .pflip = { 476 .page_flip = &r100_page_flip, 477 .page_flip_pending = &r100_page_flip_pending, 478 }, 479 }; 480 481 static struct radeon_asic r420_asic = { 482 .init = &r420_init, 483 .fini = &r420_fini, 484 .suspend = &r420_suspend, 485 .resume = &r420_resume, 486 .vga_set_state = &r100_vga_set_state, 487 .asic_reset = &r300_asic_reset, 488 .mmio_hdp_flush = NULL, 489 .gui_idle = &r100_gui_idle, 490 .mc_wait_for_idle = &r300_mc_wait_for_idle, 491 .gart = { 492 .tlb_flush = &rv370_pcie_gart_tlb_flush, 493 .set_page = &rv370_pcie_gart_set_page, 494 }, 495 .ring = { 496 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 497 }, 498 .irq = { 499 .set = &r100_irq_set, 500 .process = &r100_irq_process, 501 }, 502 .display = { 503 .bandwidth_update = &r100_bandwidth_update, 504 .get_vblank_counter = &r100_get_vblank_counter, 505 .wait_for_vblank = &r100_wait_for_vblank, 506 .set_backlight_level = &atombios_set_backlight_level, 507 .get_backlight_level = &atombios_get_backlight_level, 508 }, 509 .copy = { 510 .blit = &r100_copy_blit, 511 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 512 .dma = &r200_copy_dma, 513 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 514 .copy = &r100_copy_blit, 515 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 516 }, 517 .surface = { 518 .set_reg = r100_set_surface_reg, 519 .clear_reg = r100_clear_surface_reg, 520 }, 521 .hpd = { 522 .init = &r100_hpd_init, 523 .fini = &r100_hpd_fini, 524 .sense = &r100_hpd_sense, 525 .set_polarity = &r100_hpd_set_polarity, 526 }, 527 .pm = { 528 .misc = &r100_pm_misc, 529 .prepare = &r100_pm_prepare, 530 .finish = &r100_pm_finish, 531 .init_profile = &r420_pm_init_profile, 532 .get_dynpm_state = &r100_pm_get_dynpm_state, 533 .get_engine_clock = &radeon_atom_get_engine_clock, 534 .set_engine_clock = &radeon_atom_set_engine_clock, 535 .get_memory_clock = &radeon_atom_get_memory_clock, 536 .set_memory_clock = &radeon_atom_set_memory_clock, 537 .get_pcie_lanes = &rv370_get_pcie_lanes, 538 .set_pcie_lanes = &rv370_set_pcie_lanes, 539 .set_clock_gating = &radeon_atom_set_clock_gating, 540 }, 541 .pflip = { 542 .page_flip = &r100_page_flip, 543 .page_flip_pending = &r100_page_flip_pending, 544 }, 545 }; 546 547 static struct radeon_asic rs400_asic = { 548 .init = &rs400_init, 549 .fini = &rs400_fini, 550 .suspend = &rs400_suspend, 551 .resume = &rs400_resume, 552 .vga_set_state = &r100_vga_set_state, 553 .asic_reset = &r300_asic_reset, 554 .mmio_hdp_flush = NULL, 555 .gui_idle = &r100_gui_idle, 556 .mc_wait_for_idle = &rs400_mc_wait_for_idle, 557 .gart = { 558 .tlb_flush = &rs400_gart_tlb_flush, 559 .set_page = &rs400_gart_set_page, 560 }, 561 .ring = { 562 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 563 }, 564 .irq = { 565 .set = &r100_irq_set, 566 .process = &r100_irq_process, 567 }, 568 .display = { 569 .bandwidth_update = &r100_bandwidth_update, 570 .get_vblank_counter = &r100_get_vblank_counter, 571 .wait_for_vblank = &r100_wait_for_vblank, 572 .set_backlight_level = &radeon_legacy_set_backlight_level, 573 .get_backlight_level = &radeon_legacy_get_backlight_level, 574 }, 575 .copy = { 576 .blit = &r100_copy_blit, 577 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 578 .dma = &r200_copy_dma, 579 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 580 .copy = &r100_copy_blit, 581 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 582 }, 583 .surface = { 584 .set_reg = r100_set_surface_reg, 585 .clear_reg = r100_clear_surface_reg, 586 }, 587 .hpd = { 588 .init = &r100_hpd_init, 589 .fini = &r100_hpd_fini, 590 .sense = &r100_hpd_sense, 591 .set_polarity = &r100_hpd_set_polarity, 592 }, 593 .pm = { 594 .misc = &r100_pm_misc, 595 .prepare = &r100_pm_prepare, 596 .finish = &r100_pm_finish, 597 .init_profile = &r100_pm_init_profile, 598 .get_dynpm_state = &r100_pm_get_dynpm_state, 599 .get_engine_clock = &radeon_legacy_get_engine_clock, 600 .set_engine_clock = &radeon_legacy_set_engine_clock, 601 .get_memory_clock = &radeon_legacy_get_memory_clock, 602 .set_memory_clock = NULL, 603 .get_pcie_lanes = NULL, 604 .set_pcie_lanes = NULL, 605 .set_clock_gating = &radeon_legacy_set_clock_gating, 606 }, 607 .pflip = { 608 .page_flip = &r100_page_flip, 609 .page_flip_pending = &r100_page_flip_pending, 610 }, 611 }; 612 613 static struct radeon_asic rs600_asic = { 614 .init = &rs600_init, 615 .fini = &rs600_fini, 616 .suspend = &rs600_suspend, 617 .resume = &rs600_resume, 618 .vga_set_state = &r100_vga_set_state, 619 .asic_reset = &rs600_asic_reset, 620 .mmio_hdp_flush = NULL, 621 .gui_idle = &r100_gui_idle, 622 .mc_wait_for_idle = &rs600_mc_wait_for_idle, 623 .gart = { 624 .tlb_flush = &rs600_gart_tlb_flush, 625 .set_page = &rs600_gart_set_page, 626 }, 627 .ring = { 628 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 629 }, 630 .irq = { 631 .set = &rs600_irq_set, 632 .process = &rs600_irq_process, 633 }, 634 .display = { 635 .bandwidth_update = &rs600_bandwidth_update, 636 .get_vblank_counter = &rs600_get_vblank_counter, 637 .wait_for_vblank = &avivo_wait_for_vblank, 638 .set_backlight_level = &atombios_set_backlight_level, 639 .get_backlight_level = &atombios_get_backlight_level, 640 .hdmi_enable = &r600_hdmi_enable, 641 .hdmi_setmode = &r600_hdmi_setmode, 642 }, 643 .copy = { 644 .blit = &r100_copy_blit, 645 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 646 .dma = &r200_copy_dma, 647 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 648 .copy = &r100_copy_blit, 649 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 650 }, 651 .surface = { 652 .set_reg = r100_set_surface_reg, 653 .clear_reg = r100_clear_surface_reg, 654 }, 655 .hpd = { 656 .init = &rs600_hpd_init, 657 .fini = &rs600_hpd_fini, 658 .sense = &rs600_hpd_sense, 659 .set_polarity = &rs600_hpd_set_polarity, 660 }, 661 .pm = { 662 .misc = &rs600_pm_misc, 663 .prepare = &rs600_pm_prepare, 664 .finish = &rs600_pm_finish, 665 .init_profile = &r420_pm_init_profile, 666 .get_dynpm_state = &r100_pm_get_dynpm_state, 667 .get_engine_clock = &radeon_atom_get_engine_clock, 668 .set_engine_clock = &radeon_atom_set_engine_clock, 669 .get_memory_clock = &radeon_atom_get_memory_clock, 670 .set_memory_clock = &radeon_atom_set_memory_clock, 671 .get_pcie_lanes = NULL, 672 .set_pcie_lanes = NULL, 673 .set_clock_gating = &radeon_atom_set_clock_gating, 674 }, 675 .pflip = { 676 .page_flip = &rs600_page_flip, 677 .page_flip_pending = &rs600_page_flip_pending, 678 }, 679 }; 680 681 static struct radeon_asic rs690_asic = { 682 .init = &rs690_init, 683 .fini = &rs690_fini, 684 .suspend = &rs690_suspend, 685 .resume = &rs690_resume, 686 .vga_set_state = &r100_vga_set_state, 687 .asic_reset = &rs600_asic_reset, 688 .mmio_hdp_flush = NULL, 689 .gui_idle = &r100_gui_idle, 690 .mc_wait_for_idle = &rs690_mc_wait_for_idle, 691 .gart = { 692 .tlb_flush = &rs400_gart_tlb_flush, 693 .set_page = &rs400_gart_set_page, 694 }, 695 .ring = { 696 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 697 }, 698 .irq = { 699 .set = &rs600_irq_set, 700 .process = &rs600_irq_process, 701 }, 702 .display = { 703 .get_vblank_counter = &rs600_get_vblank_counter, 704 .bandwidth_update = &rs690_bandwidth_update, 705 .wait_for_vblank = &avivo_wait_for_vblank, 706 .set_backlight_level = &atombios_set_backlight_level, 707 .get_backlight_level = &atombios_get_backlight_level, 708 .hdmi_enable = &r600_hdmi_enable, 709 .hdmi_setmode = &r600_hdmi_setmode, 710 }, 711 .copy = { 712 .blit = &r100_copy_blit, 713 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 714 .dma = &r200_copy_dma, 715 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 716 .copy = &r200_copy_dma, 717 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 718 }, 719 .surface = { 720 .set_reg = r100_set_surface_reg, 721 .clear_reg = r100_clear_surface_reg, 722 }, 723 .hpd = { 724 .init = &rs600_hpd_init, 725 .fini = &rs600_hpd_fini, 726 .sense = &rs600_hpd_sense, 727 .set_polarity = &rs600_hpd_set_polarity, 728 }, 729 .pm = { 730 .misc = &rs600_pm_misc, 731 .prepare = &rs600_pm_prepare, 732 .finish = &rs600_pm_finish, 733 .init_profile = &r420_pm_init_profile, 734 .get_dynpm_state = &r100_pm_get_dynpm_state, 735 .get_engine_clock = &radeon_atom_get_engine_clock, 736 .set_engine_clock = &radeon_atom_set_engine_clock, 737 .get_memory_clock = &radeon_atom_get_memory_clock, 738 .set_memory_clock = &radeon_atom_set_memory_clock, 739 .get_pcie_lanes = NULL, 740 .set_pcie_lanes = NULL, 741 .set_clock_gating = &radeon_atom_set_clock_gating, 742 }, 743 .pflip = { 744 .page_flip = &rs600_page_flip, 745 .page_flip_pending = &rs600_page_flip_pending, 746 }, 747 }; 748 749 static struct radeon_asic rv515_asic = { 750 .init = &rv515_init, 751 .fini = &rv515_fini, 752 .suspend = &rv515_suspend, 753 .resume = &rv515_resume, 754 .vga_set_state = &r100_vga_set_state, 755 .asic_reset = &rs600_asic_reset, 756 .mmio_hdp_flush = NULL, 757 .gui_idle = &r100_gui_idle, 758 .mc_wait_for_idle = &rv515_mc_wait_for_idle, 759 .gart = { 760 .tlb_flush = &rv370_pcie_gart_tlb_flush, 761 .set_page = &rv370_pcie_gart_set_page, 762 }, 763 .ring = { 764 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring 765 }, 766 .irq = { 767 .set = &rs600_irq_set, 768 .process = &rs600_irq_process, 769 }, 770 .display = { 771 .get_vblank_counter = &rs600_get_vblank_counter, 772 .bandwidth_update = &rv515_bandwidth_update, 773 .wait_for_vblank = &avivo_wait_for_vblank, 774 .set_backlight_level = &atombios_set_backlight_level, 775 .get_backlight_level = &atombios_get_backlight_level, 776 }, 777 .copy = { 778 .blit = &r100_copy_blit, 779 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 780 .dma = &r200_copy_dma, 781 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 782 .copy = &r100_copy_blit, 783 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 784 }, 785 .surface = { 786 .set_reg = r100_set_surface_reg, 787 .clear_reg = r100_clear_surface_reg, 788 }, 789 .hpd = { 790 .init = &rs600_hpd_init, 791 .fini = &rs600_hpd_fini, 792 .sense = &rs600_hpd_sense, 793 .set_polarity = &rs600_hpd_set_polarity, 794 }, 795 .pm = { 796 .misc = &rs600_pm_misc, 797 .prepare = &rs600_pm_prepare, 798 .finish = &rs600_pm_finish, 799 .init_profile = &r420_pm_init_profile, 800 .get_dynpm_state = &r100_pm_get_dynpm_state, 801 .get_engine_clock = &radeon_atom_get_engine_clock, 802 .set_engine_clock = &radeon_atom_set_engine_clock, 803 .get_memory_clock = &radeon_atom_get_memory_clock, 804 .set_memory_clock = &radeon_atom_set_memory_clock, 805 .get_pcie_lanes = &rv370_get_pcie_lanes, 806 .set_pcie_lanes = &rv370_set_pcie_lanes, 807 .set_clock_gating = &radeon_atom_set_clock_gating, 808 }, 809 .pflip = { 810 .page_flip = &rs600_page_flip, 811 .page_flip_pending = &rs600_page_flip_pending, 812 }, 813 }; 814 815 static struct radeon_asic r520_asic = { 816 .init = &r520_init, 817 .fini = &rv515_fini, 818 .suspend = &rv515_suspend, 819 .resume = &r520_resume, 820 .vga_set_state = &r100_vga_set_state, 821 .asic_reset = &rs600_asic_reset, 822 .mmio_hdp_flush = NULL, 823 .gui_idle = &r100_gui_idle, 824 .mc_wait_for_idle = &r520_mc_wait_for_idle, 825 .gart = { 826 .tlb_flush = &rv370_pcie_gart_tlb_flush, 827 .set_page = &rv370_pcie_gart_set_page, 828 }, 829 .ring = { 830 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring 831 }, 832 .irq = { 833 .set = &rs600_irq_set, 834 .process = &rs600_irq_process, 835 }, 836 .display = { 837 .bandwidth_update = &rv515_bandwidth_update, 838 .get_vblank_counter = &rs600_get_vblank_counter, 839 .wait_for_vblank = &avivo_wait_for_vblank, 840 .set_backlight_level = &atombios_set_backlight_level, 841 .get_backlight_level = &atombios_get_backlight_level, 842 }, 843 .copy = { 844 .blit = &r100_copy_blit, 845 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 846 .dma = &r200_copy_dma, 847 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 848 .copy = &r100_copy_blit, 849 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 850 }, 851 .surface = { 852 .set_reg = r100_set_surface_reg, 853 .clear_reg = r100_clear_surface_reg, 854 }, 855 .hpd = { 856 .init = &rs600_hpd_init, 857 .fini = &rs600_hpd_fini, 858 .sense = &rs600_hpd_sense, 859 .set_polarity = &rs600_hpd_set_polarity, 860 }, 861 .pm = { 862 .misc = &rs600_pm_misc, 863 .prepare = &rs600_pm_prepare, 864 .finish = &rs600_pm_finish, 865 .init_profile = &r420_pm_init_profile, 866 .get_dynpm_state = &r100_pm_get_dynpm_state, 867 .get_engine_clock = &radeon_atom_get_engine_clock, 868 .set_engine_clock = &radeon_atom_set_engine_clock, 869 .get_memory_clock = &radeon_atom_get_memory_clock, 870 .set_memory_clock = &radeon_atom_set_memory_clock, 871 .get_pcie_lanes = &rv370_get_pcie_lanes, 872 .set_pcie_lanes = &rv370_set_pcie_lanes, 873 .set_clock_gating = &radeon_atom_set_clock_gating, 874 }, 875 .pflip = { 876 .page_flip = &rs600_page_flip, 877 .page_flip_pending = &rs600_page_flip_pending, 878 }, 879 }; 880 881 static struct radeon_asic_ring r600_gfx_ring = { 882 .ib_execute = &r600_ring_ib_execute, 883 .emit_fence = &r600_fence_ring_emit, 884 .emit_semaphore = &r600_semaphore_ring_emit, 885 .cs_parse = &r600_cs_parse, 886 .ring_test = &r600_ring_test, 887 .ib_test = &r600_ib_test, 888 .is_lockup = &r600_gfx_is_lockup, 889 .get_rptr = &r600_gfx_get_rptr, 890 .get_wptr = &r600_gfx_get_wptr, 891 .set_wptr = &r600_gfx_set_wptr, 892 }; 893 894 static struct radeon_asic_ring r600_dma_ring = { 895 .ib_execute = &r600_dma_ring_ib_execute, 896 .emit_fence = &r600_dma_fence_ring_emit, 897 .emit_semaphore = &r600_dma_semaphore_ring_emit, 898 .cs_parse = &r600_dma_cs_parse, 899 .ring_test = &r600_dma_ring_test, 900 .ib_test = &r600_dma_ib_test, 901 .is_lockup = &r600_dma_is_lockup, 902 .get_rptr = &r600_dma_get_rptr, 903 .get_wptr = &r600_dma_get_wptr, 904 .set_wptr = &r600_dma_set_wptr, 905 }; 906 907 static struct radeon_asic r600_asic = { 908 .init = &r600_init, 909 .fini = &r600_fini, 910 .suspend = &r600_suspend, 911 .resume = &r600_resume, 912 .vga_set_state = &r600_vga_set_state, 913 .asic_reset = &r600_asic_reset, 914 .mmio_hdp_flush = r600_mmio_hdp_flush, 915 .gui_idle = &r600_gui_idle, 916 .mc_wait_for_idle = &r600_mc_wait_for_idle, 917 .get_xclk = &r600_get_xclk, 918 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 919 .gart = { 920 .tlb_flush = &r600_pcie_gart_tlb_flush, 921 .set_page = &rs600_gart_set_page, 922 }, 923 .ring = { 924 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 925 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 926 }, 927 .irq = { 928 .set = &r600_irq_set, 929 .process = &r600_irq_process, 930 }, 931 .display = { 932 .bandwidth_update = &rv515_bandwidth_update, 933 .get_vblank_counter = &rs600_get_vblank_counter, 934 .wait_for_vblank = &avivo_wait_for_vblank, 935 .set_backlight_level = &atombios_set_backlight_level, 936 .get_backlight_level = &atombios_get_backlight_level, 937 .hdmi_enable = &r600_hdmi_enable, 938 .hdmi_setmode = &r600_hdmi_setmode, 939 }, 940 .copy = { 941 .blit = &r600_copy_cpdma, 942 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 943 .dma = &r600_copy_dma, 944 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 945 .copy = &r600_copy_cpdma, 946 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 947 }, 948 .surface = { 949 .set_reg = r600_set_surface_reg, 950 .clear_reg = r600_clear_surface_reg, 951 }, 952 .hpd = { 953 .init = &r600_hpd_init, 954 .fini = &r600_hpd_fini, 955 .sense = &r600_hpd_sense, 956 .set_polarity = &r600_hpd_set_polarity, 957 }, 958 .pm = { 959 .misc = &r600_pm_misc, 960 .prepare = &rs600_pm_prepare, 961 .finish = &rs600_pm_finish, 962 .init_profile = &r600_pm_init_profile, 963 .get_dynpm_state = &r600_pm_get_dynpm_state, 964 .get_engine_clock = &radeon_atom_get_engine_clock, 965 .set_engine_clock = &radeon_atom_set_engine_clock, 966 .get_memory_clock = &radeon_atom_get_memory_clock, 967 .set_memory_clock = &radeon_atom_set_memory_clock, 968 .get_pcie_lanes = &r600_get_pcie_lanes, 969 .set_pcie_lanes = &r600_set_pcie_lanes, 970 .set_clock_gating = NULL, 971 .get_temperature = &rv6xx_get_temp, 972 }, 973 .pflip = { 974 .page_flip = &rs600_page_flip, 975 .page_flip_pending = &rs600_page_flip_pending, 976 }, 977 }; 978 979 static struct radeon_asic_ring rv6xx_uvd_ring = { 980 .ib_execute = &uvd_v1_0_ib_execute, 981 .emit_fence = &uvd_v1_0_fence_emit, 982 .emit_semaphore = &uvd_v1_0_semaphore_emit, 983 .cs_parse = &radeon_uvd_cs_parse, 984 .ring_test = &uvd_v1_0_ring_test, 985 .ib_test = &uvd_v1_0_ib_test, 986 .is_lockup = &radeon_ring_test_lockup, 987 .get_rptr = &uvd_v1_0_get_rptr, 988 .get_wptr = &uvd_v1_0_get_wptr, 989 .set_wptr = &uvd_v1_0_set_wptr, 990 }; 991 992 static struct radeon_asic rv6xx_asic = { 993 .init = &r600_init, 994 .fini = &r600_fini, 995 .suspend = &r600_suspend, 996 .resume = &r600_resume, 997 .vga_set_state = &r600_vga_set_state, 998 .asic_reset = &r600_asic_reset, 999 .mmio_hdp_flush = r600_mmio_hdp_flush, 1000 .gui_idle = &r600_gui_idle, 1001 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1002 .get_xclk = &r600_get_xclk, 1003 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1004 .gart = { 1005 .tlb_flush = &r600_pcie_gart_tlb_flush, 1006 .set_page = &rs600_gart_set_page, 1007 }, 1008 .ring = { 1009 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 1010 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 1011 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring, 1012 }, 1013 .irq = { 1014 .set = &r600_irq_set, 1015 .process = &r600_irq_process, 1016 }, 1017 .display = { 1018 .bandwidth_update = &rv515_bandwidth_update, 1019 .get_vblank_counter = &rs600_get_vblank_counter, 1020 .wait_for_vblank = &avivo_wait_for_vblank, 1021 .set_backlight_level = &atombios_set_backlight_level, 1022 .get_backlight_level = &atombios_get_backlight_level, 1023 .hdmi_enable = &r600_hdmi_enable, 1024 .hdmi_setmode = &r600_hdmi_setmode, 1025 }, 1026 .copy = { 1027 .blit = &r600_copy_cpdma, 1028 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1029 .dma = &r600_copy_dma, 1030 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1031 .copy = &r600_copy_cpdma, 1032 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1033 }, 1034 .surface = { 1035 .set_reg = r600_set_surface_reg, 1036 .clear_reg = r600_clear_surface_reg, 1037 }, 1038 .hpd = { 1039 .init = &r600_hpd_init, 1040 .fini = &r600_hpd_fini, 1041 .sense = &r600_hpd_sense, 1042 .set_polarity = &r600_hpd_set_polarity, 1043 }, 1044 .pm = { 1045 .misc = &r600_pm_misc, 1046 .prepare = &rs600_pm_prepare, 1047 .finish = &rs600_pm_finish, 1048 .init_profile = &r600_pm_init_profile, 1049 .get_dynpm_state = &r600_pm_get_dynpm_state, 1050 .get_engine_clock = &radeon_atom_get_engine_clock, 1051 .set_engine_clock = &radeon_atom_set_engine_clock, 1052 .get_memory_clock = &radeon_atom_get_memory_clock, 1053 .set_memory_clock = &radeon_atom_set_memory_clock, 1054 .get_pcie_lanes = &r600_get_pcie_lanes, 1055 .set_pcie_lanes = &r600_set_pcie_lanes, 1056 .set_clock_gating = NULL, 1057 .get_temperature = &rv6xx_get_temp, 1058 .set_uvd_clocks = &r600_set_uvd_clocks, 1059 }, 1060 .dpm = { 1061 .init = &rv6xx_dpm_init, 1062 .setup_asic = &rv6xx_setup_asic, 1063 .enable = &rv6xx_dpm_enable, 1064 .late_enable = &r600_dpm_late_enable, 1065 .disable = &rv6xx_dpm_disable, 1066 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1067 .set_power_state = &rv6xx_dpm_set_power_state, 1068 .post_set_power_state = &r600_dpm_post_set_power_state, 1069 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed, 1070 .fini = &rv6xx_dpm_fini, 1071 .get_sclk = &rv6xx_dpm_get_sclk, 1072 .get_mclk = &rv6xx_dpm_get_mclk, 1073 .print_power_state = &rv6xx_dpm_print_power_state, 1074 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level, 1075 .force_performance_level = &rv6xx_dpm_force_performance_level, 1076 }, 1077 .pflip = { 1078 .page_flip = &rs600_page_flip, 1079 .page_flip_pending = &rs600_page_flip_pending, 1080 }, 1081 }; 1082 1083 static struct radeon_asic rs780_asic = { 1084 .init = &r600_init, 1085 .fini = &r600_fini, 1086 .suspend = &r600_suspend, 1087 .resume = &r600_resume, 1088 .vga_set_state = &r600_vga_set_state, 1089 .asic_reset = &r600_asic_reset, 1090 .mmio_hdp_flush = r600_mmio_hdp_flush, 1091 .gui_idle = &r600_gui_idle, 1092 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1093 .get_xclk = &r600_get_xclk, 1094 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1095 .gart = { 1096 .tlb_flush = &r600_pcie_gart_tlb_flush, 1097 .set_page = &rs600_gart_set_page, 1098 }, 1099 .ring = { 1100 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 1101 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 1102 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring, 1103 }, 1104 .irq = { 1105 .set = &r600_irq_set, 1106 .process = &r600_irq_process, 1107 }, 1108 .display = { 1109 .bandwidth_update = &rs690_bandwidth_update, 1110 .get_vblank_counter = &rs600_get_vblank_counter, 1111 .wait_for_vblank = &avivo_wait_for_vblank, 1112 .set_backlight_level = &atombios_set_backlight_level, 1113 .get_backlight_level = &atombios_get_backlight_level, 1114 .hdmi_enable = &r600_hdmi_enable, 1115 .hdmi_setmode = &r600_hdmi_setmode, 1116 }, 1117 .copy = { 1118 .blit = &r600_copy_cpdma, 1119 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1120 .dma = &r600_copy_dma, 1121 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1122 .copy = &r600_copy_cpdma, 1123 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1124 }, 1125 .surface = { 1126 .set_reg = r600_set_surface_reg, 1127 .clear_reg = r600_clear_surface_reg, 1128 }, 1129 .hpd = { 1130 .init = &r600_hpd_init, 1131 .fini = &r600_hpd_fini, 1132 .sense = &r600_hpd_sense, 1133 .set_polarity = &r600_hpd_set_polarity, 1134 }, 1135 .pm = { 1136 .misc = &r600_pm_misc, 1137 .prepare = &rs600_pm_prepare, 1138 .finish = &rs600_pm_finish, 1139 .init_profile = &rs780_pm_init_profile, 1140 .get_dynpm_state = &r600_pm_get_dynpm_state, 1141 .get_engine_clock = &radeon_atom_get_engine_clock, 1142 .set_engine_clock = &radeon_atom_set_engine_clock, 1143 .get_memory_clock = NULL, 1144 .set_memory_clock = NULL, 1145 .get_pcie_lanes = NULL, 1146 .set_pcie_lanes = NULL, 1147 .set_clock_gating = NULL, 1148 .get_temperature = &rv6xx_get_temp, 1149 .set_uvd_clocks = &r600_set_uvd_clocks, 1150 }, 1151 .dpm = { 1152 .init = &rs780_dpm_init, 1153 .setup_asic = &rs780_dpm_setup_asic, 1154 .enable = &rs780_dpm_enable, 1155 .late_enable = &r600_dpm_late_enable, 1156 .disable = &rs780_dpm_disable, 1157 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1158 .set_power_state = &rs780_dpm_set_power_state, 1159 .post_set_power_state = &r600_dpm_post_set_power_state, 1160 .display_configuration_changed = &rs780_dpm_display_configuration_changed, 1161 .fini = &rs780_dpm_fini, 1162 .get_sclk = &rs780_dpm_get_sclk, 1163 .get_mclk = &rs780_dpm_get_mclk, 1164 .print_power_state = &rs780_dpm_print_power_state, 1165 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level, 1166 .force_performance_level = &rs780_dpm_force_performance_level, 1167 }, 1168 .pflip = { 1169 .page_flip = &rs600_page_flip, 1170 .page_flip_pending = &rs600_page_flip_pending, 1171 }, 1172 }; 1173 1174 static struct radeon_asic_ring rv770_uvd_ring = { 1175 .ib_execute = &uvd_v1_0_ib_execute, 1176 .emit_fence = &uvd_v2_2_fence_emit, 1177 .emit_semaphore = &uvd_v1_0_semaphore_emit, 1178 .cs_parse = &radeon_uvd_cs_parse, 1179 .ring_test = &uvd_v1_0_ring_test, 1180 .ib_test = &uvd_v1_0_ib_test, 1181 .is_lockup = &radeon_ring_test_lockup, 1182 .get_rptr = &uvd_v1_0_get_rptr, 1183 .get_wptr = &uvd_v1_0_get_wptr, 1184 .set_wptr = &uvd_v1_0_set_wptr, 1185 }; 1186 1187 static struct radeon_asic rv770_asic = { 1188 .init = &rv770_init, 1189 .fini = &rv770_fini, 1190 .suspend = &rv770_suspend, 1191 .resume = &rv770_resume, 1192 .asic_reset = &r600_asic_reset, 1193 .vga_set_state = &r600_vga_set_state, 1194 .mmio_hdp_flush = r600_mmio_hdp_flush, 1195 .gui_idle = &r600_gui_idle, 1196 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1197 .get_xclk = &rv770_get_xclk, 1198 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1199 .gart = { 1200 .tlb_flush = &r600_pcie_gart_tlb_flush, 1201 .set_page = &rs600_gart_set_page, 1202 }, 1203 .ring = { 1204 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 1205 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 1206 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1207 }, 1208 .irq = { 1209 .set = &r600_irq_set, 1210 .process = &r600_irq_process, 1211 }, 1212 .display = { 1213 .bandwidth_update = &rv515_bandwidth_update, 1214 .get_vblank_counter = &rs600_get_vblank_counter, 1215 .wait_for_vblank = &avivo_wait_for_vblank, 1216 .set_backlight_level = &atombios_set_backlight_level, 1217 .get_backlight_level = &atombios_get_backlight_level, 1218 .hdmi_enable = &r600_hdmi_enable, 1219 .hdmi_setmode = &dce3_1_hdmi_setmode, 1220 }, 1221 .copy = { 1222 .blit = &r600_copy_cpdma, 1223 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1224 .dma = &rv770_copy_dma, 1225 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1226 .copy = &rv770_copy_dma, 1227 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1228 }, 1229 .surface = { 1230 .set_reg = r600_set_surface_reg, 1231 .clear_reg = r600_clear_surface_reg, 1232 }, 1233 .hpd = { 1234 .init = &r600_hpd_init, 1235 .fini = &r600_hpd_fini, 1236 .sense = &r600_hpd_sense, 1237 .set_polarity = &r600_hpd_set_polarity, 1238 }, 1239 .pm = { 1240 .misc = &rv770_pm_misc, 1241 .prepare = &rs600_pm_prepare, 1242 .finish = &rs600_pm_finish, 1243 .init_profile = &r600_pm_init_profile, 1244 .get_dynpm_state = &r600_pm_get_dynpm_state, 1245 .get_engine_clock = &radeon_atom_get_engine_clock, 1246 .set_engine_clock = &radeon_atom_set_engine_clock, 1247 .get_memory_clock = &radeon_atom_get_memory_clock, 1248 .set_memory_clock = &radeon_atom_set_memory_clock, 1249 .get_pcie_lanes = &r600_get_pcie_lanes, 1250 .set_pcie_lanes = &r600_set_pcie_lanes, 1251 .set_clock_gating = &radeon_atom_set_clock_gating, 1252 .set_uvd_clocks = &rv770_set_uvd_clocks, 1253 .get_temperature = &rv770_get_temp, 1254 }, 1255 .dpm = { 1256 .init = &rv770_dpm_init, 1257 .setup_asic = &rv770_dpm_setup_asic, 1258 .enable = &rv770_dpm_enable, 1259 .late_enable = &rv770_dpm_late_enable, 1260 .disable = &rv770_dpm_disable, 1261 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1262 .set_power_state = &rv770_dpm_set_power_state, 1263 .post_set_power_state = &r600_dpm_post_set_power_state, 1264 .display_configuration_changed = &rv770_dpm_display_configuration_changed, 1265 .fini = &rv770_dpm_fini, 1266 .get_sclk = &rv770_dpm_get_sclk, 1267 .get_mclk = &rv770_dpm_get_mclk, 1268 .print_power_state = &rv770_dpm_print_power_state, 1269 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, 1270 .force_performance_level = &rv770_dpm_force_performance_level, 1271 .vblank_too_short = &rv770_dpm_vblank_too_short, 1272 }, 1273 .pflip = { 1274 .page_flip = &rv770_page_flip, 1275 .page_flip_pending = &rv770_page_flip_pending, 1276 }, 1277 }; 1278 1279 static struct radeon_asic_ring evergreen_gfx_ring = { 1280 .ib_execute = &evergreen_ring_ib_execute, 1281 .emit_fence = &r600_fence_ring_emit, 1282 .emit_semaphore = &r600_semaphore_ring_emit, 1283 .cs_parse = &evergreen_cs_parse, 1284 .ring_test = &r600_ring_test, 1285 .ib_test = &r600_ib_test, 1286 .is_lockup = &evergreen_gfx_is_lockup, 1287 .get_rptr = &r600_gfx_get_rptr, 1288 .get_wptr = &r600_gfx_get_wptr, 1289 .set_wptr = &r600_gfx_set_wptr, 1290 }; 1291 1292 static struct radeon_asic_ring evergreen_dma_ring = { 1293 .ib_execute = &evergreen_dma_ring_ib_execute, 1294 .emit_fence = &evergreen_dma_fence_ring_emit, 1295 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1296 .cs_parse = &evergreen_dma_cs_parse, 1297 .ring_test = &r600_dma_ring_test, 1298 .ib_test = &r600_dma_ib_test, 1299 .is_lockup = &evergreen_dma_is_lockup, 1300 .get_rptr = &r600_dma_get_rptr, 1301 .get_wptr = &r600_dma_get_wptr, 1302 .set_wptr = &r600_dma_set_wptr, 1303 }; 1304 1305 static struct radeon_asic evergreen_asic = { 1306 .init = &evergreen_init, 1307 .fini = &evergreen_fini, 1308 .suspend = &evergreen_suspend, 1309 .resume = &evergreen_resume, 1310 .asic_reset = &evergreen_asic_reset, 1311 .vga_set_state = &r600_vga_set_state, 1312 .mmio_hdp_flush = r600_mmio_hdp_flush, 1313 .gui_idle = &r600_gui_idle, 1314 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1315 .get_xclk = &rv770_get_xclk, 1316 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1317 .gart = { 1318 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1319 .set_page = &rs600_gart_set_page, 1320 }, 1321 .ring = { 1322 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1323 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1324 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1325 }, 1326 .irq = { 1327 .set = &evergreen_irq_set, 1328 .process = &evergreen_irq_process, 1329 }, 1330 .display = { 1331 .bandwidth_update = &evergreen_bandwidth_update, 1332 .get_vblank_counter = &evergreen_get_vblank_counter, 1333 .wait_for_vblank = &dce4_wait_for_vblank, 1334 .set_backlight_level = &atombios_set_backlight_level, 1335 .get_backlight_level = &atombios_get_backlight_level, 1336 .hdmi_enable = &evergreen_hdmi_enable, 1337 .hdmi_setmode = &evergreen_hdmi_setmode, 1338 }, 1339 .copy = { 1340 .blit = &r600_copy_cpdma, 1341 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1342 .dma = &evergreen_copy_dma, 1343 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1344 .copy = &evergreen_copy_dma, 1345 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1346 }, 1347 .surface = { 1348 .set_reg = r600_set_surface_reg, 1349 .clear_reg = r600_clear_surface_reg, 1350 }, 1351 .hpd = { 1352 .init = &evergreen_hpd_init, 1353 .fini = &evergreen_hpd_fini, 1354 .sense = &evergreen_hpd_sense, 1355 .set_polarity = &evergreen_hpd_set_polarity, 1356 }, 1357 .pm = { 1358 .misc = &evergreen_pm_misc, 1359 .prepare = &evergreen_pm_prepare, 1360 .finish = &evergreen_pm_finish, 1361 .init_profile = &r600_pm_init_profile, 1362 .get_dynpm_state = &r600_pm_get_dynpm_state, 1363 .get_engine_clock = &radeon_atom_get_engine_clock, 1364 .set_engine_clock = &radeon_atom_set_engine_clock, 1365 .get_memory_clock = &radeon_atom_get_memory_clock, 1366 .set_memory_clock = &radeon_atom_set_memory_clock, 1367 .get_pcie_lanes = &r600_get_pcie_lanes, 1368 .set_pcie_lanes = &r600_set_pcie_lanes, 1369 .set_clock_gating = NULL, 1370 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1371 .get_temperature = &evergreen_get_temp, 1372 }, 1373 .dpm = { 1374 .init = &cypress_dpm_init, 1375 .setup_asic = &cypress_dpm_setup_asic, 1376 .enable = &cypress_dpm_enable, 1377 .late_enable = &rv770_dpm_late_enable, 1378 .disable = &cypress_dpm_disable, 1379 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1380 .set_power_state = &cypress_dpm_set_power_state, 1381 .post_set_power_state = &r600_dpm_post_set_power_state, 1382 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1383 .fini = &cypress_dpm_fini, 1384 .get_sclk = &rv770_dpm_get_sclk, 1385 .get_mclk = &rv770_dpm_get_mclk, 1386 .print_power_state = &rv770_dpm_print_power_state, 1387 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, 1388 .force_performance_level = &rv770_dpm_force_performance_level, 1389 .vblank_too_short = &cypress_dpm_vblank_too_short, 1390 }, 1391 .pflip = { 1392 .page_flip = &evergreen_page_flip, 1393 .page_flip_pending = &evergreen_page_flip_pending, 1394 }, 1395 }; 1396 1397 static struct radeon_asic sumo_asic = { 1398 .init = &evergreen_init, 1399 .fini = &evergreen_fini, 1400 .suspend = &evergreen_suspend, 1401 .resume = &evergreen_resume, 1402 .asic_reset = &evergreen_asic_reset, 1403 .vga_set_state = &r600_vga_set_state, 1404 .mmio_hdp_flush = r600_mmio_hdp_flush, 1405 .gui_idle = &r600_gui_idle, 1406 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1407 .get_xclk = &r600_get_xclk, 1408 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1409 .gart = { 1410 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1411 .set_page = &rs600_gart_set_page, 1412 }, 1413 .ring = { 1414 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1415 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1416 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1417 }, 1418 .irq = { 1419 .set = &evergreen_irq_set, 1420 .process = &evergreen_irq_process, 1421 }, 1422 .display = { 1423 .bandwidth_update = &evergreen_bandwidth_update, 1424 .get_vblank_counter = &evergreen_get_vblank_counter, 1425 .wait_for_vblank = &dce4_wait_for_vblank, 1426 .set_backlight_level = &atombios_set_backlight_level, 1427 .get_backlight_level = &atombios_get_backlight_level, 1428 .hdmi_enable = &evergreen_hdmi_enable, 1429 .hdmi_setmode = &evergreen_hdmi_setmode, 1430 }, 1431 .copy = { 1432 .blit = &r600_copy_cpdma, 1433 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1434 .dma = &evergreen_copy_dma, 1435 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1436 .copy = &evergreen_copy_dma, 1437 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1438 }, 1439 .surface = { 1440 .set_reg = r600_set_surface_reg, 1441 .clear_reg = r600_clear_surface_reg, 1442 }, 1443 .hpd = { 1444 .init = &evergreen_hpd_init, 1445 .fini = &evergreen_hpd_fini, 1446 .sense = &evergreen_hpd_sense, 1447 .set_polarity = &evergreen_hpd_set_polarity, 1448 }, 1449 .pm = { 1450 .misc = &evergreen_pm_misc, 1451 .prepare = &evergreen_pm_prepare, 1452 .finish = &evergreen_pm_finish, 1453 .init_profile = &sumo_pm_init_profile, 1454 .get_dynpm_state = &r600_pm_get_dynpm_state, 1455 .get_engine_clock = &radeon_atom_get_engine_clock, 1456 .set_engine_clock = &radeon_atom_set_engine_clock, 1457 .get_memory_clock = NULL, 1458 .set_memory_clock = NULL, 1459 .get_pcie_lanes = NULL, 1460 .set_pcie_lanes = NULL, 1461 .set_clock_gating = NULL, 1462 .set_uvd_clocks = &sumo_set_uvd_clocks, 1463 .get_temperature = &sumo_get_temp, 1464 }, 1465 .dpm = { 1466 .init = &sumo_dpm_init, 1467 .setup_asic = &sumo_dpm_setup_asic, 1468 .enable = &sumo_dpm_enable, 1469 .late_enable = &sumo_dpm_late_enable, 1470 .disable = &sumo_dpm_disable, 1471 .pre_set_power_state = &sumo_dpm_pre_set_power_state, 1472 .set_power_state = &sumo_dpm_set_power_state, 1473 .post_set_power_state = &sumo_dpm_post_set_power_state, 1474 .display_configuration_changed = &sumo_dpm_display_configuration_changed, 1475 .fini = &sumo_dpm_fini, 1476 .get_sclk = &sumo_dpm_get_sclk, 1477 .get_mclk = &sumo_dpm_get_mclk, 1478 .print_power_state = &sumo_dpm_print_power_state, 1479 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level, 1480 .force_performance_level = &sumo_dpm_force_performance_level, 1481 }, 1482 .pflip = { 1483 .page_flip = &evergreen_page_flip, 1484 .page_flip_pending = &evergreen_page_flip_pending, 1485 }, 1486 }; 1487 1488 static struct radeon_asic btc_asic = { 1489 .init = &evergreen_init, 1490 .fini = &evergreen_fini, 1491 .suspend = &evergreen_suspend, 1492 .resume = &evergreen_resume, 1493 .asic_reset = &evergreen_asic_reset, 1494 .vga_set_state = &r600_vga_set_state, 1495 .mmio_hdp_flush = r600_mmio_hdp_flush, 1496 .gui_idle = &r600_gui_idle, 1497 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1498 .get_xclk = &rv770_get_xclk, 1499 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1500 .gart = { 1501 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1502 .set_page = &rs600_gart_set_page, 1503 }, 1504 .ring = { 1505 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1506 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1507 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1508 }, 1509 .irq = { 1510 .set = &evergreen_irq_set, 1511 .process = &evergreen_irq_process, 1512 }, 1513 .display = { 1514 .bandwidth_update = &evergreen_bandwidth_update, 1515 .get_vblank_counter = &evergreen_get_vblank_counter, 1516 .wait_for_vblank = &dce4_wait_for_vblank, 1517 .set_backlight_level = &atombios_set_backlight_level, 1518 .get_backlight_level = &atombios_get_backlight_level, 1519 .hdmi_enable = &evergreen_hdmi_enable, 1520 .hdmi_setmode = &evergreen_hdmi_setmode, 1521 }, 1522 .copy = { 1523 .blit = &r600_copy_cpdma, 1524 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1525 .dma = &evergreen_copy_dma, 1526 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1527 .copy = &evergreen_copy_dma, 1528 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1529 }, 1530 .surface = { 1531 .set_reg = r600_set_surface_reg, 1532 .clear_reg = r600_clear_surface_reg, 1533 }, 1534 .hpd = { 1535 .init = &evergreen_hpd_init, 1536 .fini = &evergreen_hpd_fini, 1537 .sense = &evergreen_hpd_sense, 1538 .set_polarity = &evergreen_hpd_set_polarity, 1539 }, 1540 .pm = { 1541 .misc = &evergreen_pm_misc, 1542 .prepare = &evergreen_pm_prepare, 1543 .finish = &evergreen_pm_finish, 1544 .init_profile = &btc_pm_init_profile, 1545 .get_dynpm_state = &r600_pm_get_dynpm_state, 1546 .get_engine_clock = &radeon_atom_get_engine_clock, 1547 .set_engine_clock = &radeon_atom_set_engine_clock, 1548 .get_memory_clock = &radeon_atom_get_memory_clock, 1549 .set_memory_clock = &radeon_atom_set_memory_clock, 1550 .get_pcie_lanes = &r600_get_pcie_lanes, 1551 .set_pcie_lanes = &r600_set_pcie_lanes, 1552 .set_clock_gating = NULL, 1553 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1554 .get_temperature = &evergreen_get_temp, 1555 }, 1556 .dpm = { 1557 .init = &btc_dpm_init, 1558 .setup_asic = &btc_dpm_setup_asic, 1559 .enable = &btc_dpm_enable, 1560 .late_enable = &rv770_dpm_late_enable, 1561 .disable = &btc_dpm_disable, 1562 .pre_set_power_state = &btc_dpm_pre_set_power_state, 1563 .set_power_state = &btc_dpm_set_power_state, 1564 .post_set_power_state = &btc_dpm_post_set_power_state, 1565 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1566 .fini = &btc_dpm_fini, 1567 .get_sclk = &btc_dpm_get_sclk, 1568 .get_mclk = &btc_dpm_get_mclk, 1569 .print_power_state = &rv770_dpm_print_power_state, 1570 .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level, 1571 .force_performance_level = &rv770_dpm_force_performance_level, 1572 .vblank_too_short = &btc_dpm_vblank_too_short, 1573 }, 1574 .pflip = { 1575 .page_flip = &evergreen_page_flip, 1576 .page_flip_pending = &evergreen_page_flip_pending, 1577 }, 1578 }; 1579 1580 static struct radeon_asic_ring cayman_gfx_ring = { 1581 .ib_execute = &cayman_ring_ib_execute, 1582 .ib_parse = &evergreen_ib_parse, 1583 .emit_fence = &cayman_fence_ring_emit, 1584 .emit_semaphore = &r600_semaphore_ring_emit, 1585 .cs_parse = &evergreen_cs_parse, 1586 .ring_test = &r600_ring_test, 1587 .ib_test = &r600_ib_test, 1588 .is_lockup = &cayman_gfx_is_lockup, 1589 .vm_flush = &cayman_vm_flush, 1590 .get_rptr = &cayman_gfx_get_rptr, 1591 .get_wptr = &cayman_gfx_get_wptr, 1592 .set_wptr = &cayman_gfx_set_wptr, 1593 }; 1594 1595 static struct radeon_asic_ring cayman_dma_ring = { 1596 .ib_execute = &cayman_dma_ring_ib_execute, 1597 .ib_parse = &evergreen_dma_ib_parse, 1598 .emit_fence = &evergreen_dma_fence_ring_emit, 1599 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1600 .cs_parse = &evergreen_dma_cs_parse, 1601 .ring_test = &r600_dma_ring_test, 1602 .ib_test = &r600_dma_ib_test, 1603 .is_lockup = &cayman_dma_is_lockup, 1604 .vm_flush = &cayman_dma_vm_flush, 1605 .get_rptr = &cayman_dma_get_rptr, 1606 .get_wptr = &cayman_dma_get_wptr, 1607 .set_wptr = &cayman_dma_set_wptr 1608 }; 1609 1610 static struct radeon_asic_ring cayman_uvd_ring = { 1611 .ib_execute = &uvd_v1_0_ib_execute, 1612 .emit_fence = &uvd_v2_2_fence_emit, 1613 .emit_semaphore = &uvd_v3_1_semaphore_emit, 1614 .cs_parse = &radeon_uvd_cs_parse, 1615 .ring_test = &uvd_v1_0_ring_test, 1616 .ib_test = &uvd_v1_0_ib_test, 1617 .is_lockup = &radeon_ring_test_lockup, 1618 .get_rptr = &uvd_v1_0_get_rptr, 1619 .get_wptr = &uvd_v1_0_get_wptr, 1620 .set_wptr = &uvd_v1_0_set_wptr, 1621 }; 1622 1623 static struct radeon_asic cayman_asic = { 1624 .init = &cayman_init, 1625 .fini = &cayman_fini, 1626 .suspend = &cayman_suspend, 1627 .resume = &cayman_resume, 1628 .asic_reset = &cayman_asic_reset, 1629 .vga_set_state = &r600_vga_set_state, 1630 .mmio_hdp_flush = r600_mmio_hdp_flush, 1631 .gui_idle = &r600_gui_idle, 1632 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1633 .get_xclk = &rv770_get_xclk, 1634 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1635 .gart = { 1636 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1637 .set_page = &rs600_gart_set_page, 1638 }, 1639 .vm = { 1640 .init = &cayman_vm_init, 1641 .fini = &cayman_vm_fini, 1642 .copy_pages = &cayman_dma_vm_copy_pages, 1643 .write_pages = &cayman_dma_vm_write_pages, 1644 .set_pages = &cayman_dma_vm_set_pages, 1645 .pad_ib = &cayman_dma_vm_pad_ib, 1646 }, 1647 .ring = { 1648 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, 1649 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, 1650 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, 1651 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, 1652 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, 1653 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1654 }, 1655 .irq = { 1656 .set = &evergreen_irq_set, 1657 .process = &evergreen_irq_process, 1658 }, 1659 .display = { 1660 .bandwidth_update = &evergreen_bandwidth_update, 1661 .get_vblank_counter = &evergreen_get_vblank_counter, 1662 .wait_for_vblank = &dce4_wait_for_vblank, 1663 .set_backlight_level = &atombios_set_backlight_level, 1664 .get_backlight_level = &atombios_get_backlight_level, 1665 .hdmi_enable = &evergreen_hdmi_enable, 1666 .hdmi_setmode = &evergreen_hdmi_setmode, 1667 }, 1668 .copy = { 1669 .blit = &r600_copy_cpdma, 1670 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1671 .dma = &evergreen_copy_dma, 1672 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1673 .copy = &evergreen_copy_dma, 1674 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1675 }, 1676 .surface = { 1677 .set_reg = r600_set_surface_reg, 1678 .clear_reg = r600_clear_surface_reg, 1679 }, 1680 .hpd = { 1681 .init = &evergreen_hpd_init, 1682 .fini = &evergreen_hpd_fini, 1683 .sense = &evergreen_hpd_sense, 1684 .set_polarity = &evergreen_hpd_set_polarity, 1685 }, 1686 .pm = { 1687 .misc = &evergreen_pm_misc, 1688 .prepare = &evergreen_pm_prepare, 1689 .finish = &evergreen_pm_finish, 1690 .init_profile = &btc_pm_init_profile, 1691 .get_dynpm_state = &r600_pm_get_dynpm_state, 1692 .get_engine_clock = &radeon_atom_get_engine_clock, 1693 .set_engine_clock = &radeon_atom_set_engine_clock, 1694 .get_memory_clock = &radeon_atom_get_memory_clock, 1695 .set_memory_clock = &radeon_atom_set_memory_clock, 1696 .get_pcie_lanes = &r600_get_pcie_lanes, 1697 .set_pcie_lanes = &r600_set_pcie_lanes, 1698 .set_clock_gating = NULL, 1699 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1700 .get_temperature = &evergreen_get_temp, 1701 }, 1702 .dpm = { 1703 .init = &ni_dpm_init, 1704 .setup_asic = &ni_dpm_setup_asic, 1705 .enable = &ni_dpm_enable, 1706 .late_enable = &rv770_dpm_late_enable, 1707 .disable = &ni_dpm_disable, 1708 .pre_set_power_state = &ni_dpm_pre_set_power_state, 1709 .set_power_state = &ni_dpm_set_power_state, 1710 .post_set_power_state = &ni_dpm_post_set_power_state, 1711 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1712 .fini = &ni_dpm_fini, 1713 .get_sclk = &ni_dpm_get_sclk, 1714 .get_mclk = &ni_dpm_get_mclk, 1715 .print_power_state = &ni_dpm_print_power_state, 1716 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level, 1717 .force_performance_level = &ni_dpm_force_performance_level, 1718 .vblank_too_short = &ni_dpm_vblank_too_short, 1719 }, 1720 .pflip = { 1721 .page_flip = &evergreen_page_flip, 1722 .page_flip_pending = &evergreen_page_flip_pending, 1723 }, 1724 }; 1725 1726 static struct radeon_asic trinity_asic = { 1727 .init = &cayman_init, 1728 .fini = &cayman_fini, 1729 .suspend = &cayman_suspend, 1730 .resume = &cayman_resume, 1731 .asic_reset = &cayman_asic_reset, 1732 .vga_set_state = &r600_vga_set_state, 1733 .mmio_hdp_flush = r600_mmio_hdp_flush, 1734 .gui_idle = &r600_gui_idle, 1735 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1736 .get_xclk = &r600_get_xclk, 1737 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1738 .gart = { 1739 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1740 .set_page = &rs600_gart_set_page, 1741 }, 1742 .vm = { 1743 .init = &cayman_vm_init, 1744 .fini = &cayman_vm_fini, 1745 .copy_pages = &cayman_dma_vm_copy_pages, 1746 .write_pages = &cayman_dma_vm_write_pages, 1747 .set_pages = &cayman_dma_vm_set_pages, 1748 .pad_ib = &cayman_dma_vm_pad_ib, 1749 }, 1750 .ring = { 1751 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, 1752 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, 1753 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, 1754 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, 1755 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, 1756 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1757 }, 1758 .irq = { 1759 .set = &evergreen_irq_set, 1760 .process = &evergreen_irq_process, 1761 }, 1762 .display = { 1763 .bandwidth_update = &dce6_bandwidth_update, 1764 .get_vblank_counter = &evergreen_get_vblank_counter, 1765 .wait_for_vblank = &dce4_wait_for_vblank, 1766 .set_backlight_level = &atombios_set_backlight_level, 1767 .get_backlight_level = &atombios_get_backlight_level, 1768 .hdmi_enable = &evergreen_hdmi_enable, 1769 .hdmi_setmode = &evergreen_hdmi_setmode, 1770 }, 1771 .copy = { 1772 .blit = &r600_copy_cpdma, 1773 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1774 .dma = &evergreen_copy_dma, 1775 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1776 .copy = &evergreen_copy_dma, 1777 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1778 }, 1779 .surface = { 1780 .set_reg = r600_set_surface_reg, 1781 .clear_reg = r600_clear_surface_reg, 1782 }, 1783 .hpd = { 1784 .init = &evergreen_hpd_init, 1785 .fini = &evergreen_hpd_fini, 1786 .sense = &evergreen_hpd_sense, 1787 .set_polarity = &evergreen_hpd_set_polarity, 1788 }, 1789 .pm = { 1790 .misc = &evergreen_pm_misc, 1791 .prepare = &evergreen_pm_prepare, 1792 .finish = &evergreen_pm_finish, 1793 .init_profile = &sumo_pm_init_profile, 1794 .get_dynpm_state = &r600_pm_get_dynpm_state, 1795 .get_engine_clock = &radeon_atom_get_engine_clock, 1796 .set_engine_clock = &radeon_atom_set_engine_clock, 1797 .get_memory_clock = NULL, 1798 .set_memory_clock = NULL, 1799 .get_pcie_lanes = NULL, 1800 .set_pcie_lanes = NULL, 1801 .set_clock_gating = NULL, 1802 .set_uvd_clocks = &sumo_set_uvd_clocks, 1803 .get_temperature = &tn_get_temp, 1804 }, 1805 .dpm = { 1806 .init = &trinity_dpm_init, 1807 .setup_asic = &trinity_dpm_setup_asic, 1808 .enable = &trinity_dpm_enable, 1809 .late_enable = &trinity_dpm_late_enable, 1810 .disable = &trinity_dpm_disable, 1811 .pre_set_power_state = &trinity_dpm_pre_set_power_state, 1812 .set_power_state = &trinity_dpm_set_power_state, 1813 .post_set_power_state = &trinity_dpm_post_set_power_state, 1814 .display_configuration_changed = &trinity_dpm_display_configuration_changed, 1815 .fini = &trinity_dpm_fini, 1816 .get_sclk = &trinity_dpm_get_sclk, 1817 .get_mclk = &trinity_dpm_get_mclk, 1818 .print_power_state = &trinity_dpm_print_power_state, 1819 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level, 1820 .force_performance_level = &trinity_dpm_force_performance_level, 1821 .enable_bapm = &trinity_dpm_enable_bapm, 1822 }, 1823 .pflip = { 1824 .page_flip = &evergreen_page_flip, 1825 .page_flip_pending = &evergreen_page_flip_pending, 1826 }, 1827 }; 1828 1829 static struct radeon_asic_ring si_gfx_ring = { 1830 .ib_execute = &si_ring_ib_execute, 1831 .ib_parse = &si_ib_parse, 1832 .emit_fence = &si_fence_ring_emit, 1833 .emit_semaphore = &r600_semaphore_ring_emit, 1834 .cs_parse = NULL, 1835 .ring_test = &r600_ring_test, 1836 .ib_test = &r600_ib_test, 1837 .is_lockup = &si_gfx_is_lockup, 1838 .vm_flush = &si_vm_flush, 1839 .get_rptr = &cayman_gfx_get_rptr, 1840 .get_wptr = &cayman_gfx_get_wptr, 1841 .set_wptr = &cayman_gfx_set_wptr, 1842 }; 1843 1844 static struct radeon_asic_ring si_dma_ring = { 1845 .ib_execute = &cayman_dma_ring_ib_execute, 1846 .ib_parse = &evergreen_dma_ib_parse, 1847 .emit_fence = &evergreen_dma_fence_ring_emit, 1848 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1849 .cs_parse = NULL, 1850 .ring_test = &r600_dma_ring_test, 1851 .ib_test = &r600_dma_ib_test, 1852 .is_lockup = &si_dma_is_lockup, 1853 .vm_flush = &si_dma_vm_flush, 1854 .get_rptr = &cayman_dma_get_rptr, 1855 .get_wptr = &cayman_dma_get_wptr, 1856 .set_wptr = &cayman_dma_set_wptr, 1857 }; 1858 1859 static struct radeon_asic si_asic = { 1860 .init = &si_init, 1861 .fini = &si_fini, 1862 .suspend = &si_suspend, 1863 .resume = &si_resume, 1864 .asic_reset = &si_asic_reset, 1865 .vga_set_state = &r600_vga_set_state, 1866 .mmio_hdp_flush = r600_mmio_hdp_flush, 1867 .gui_idle = &r600_gui_idle, 1868 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1869 .get_xclk = &si_get_xclk, 1870 .get_gpu_clock_counter = &si_get_gpu_clock_counter, 1871 .gart = { 1872 .tlb_flush = &si_pcie_gart_tlb_flush, 1873 .set_page = &rs600_gart_set_page, 1874 }, 1875 .vm = { 1876 .init = &si_vm_init, 1877 .fini = &si_vm_fini, 1878 .copy_pages = &si_dma_vm_copy_pages, 1879 .write_pages = &si_dma_vm_write_pages, 1880 .set_pages = &si_dma_vm_set_pages, 1881 .pad_ib = &cayman_dma_vm_pad_ib, 1882 }, 1883 .ring = { 1884 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring, 1885 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring, 1886 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring, 1887 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring, 1888 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring, 1889 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1890 }, 1891 .irq = { 1892 .set = &si_irq_set, 1893 .process = &si_irq_process, 1894 }, 1895 .display = { 1896 .bandwidth_update = &dce6_bandwidth_update, 1897 .get_vblank_counter = &evergreen_get_vblank_counter, 1898 .wait_for_vblank = &dce4_wait_for_vblank, 1899 .set_backlight_level = &atombios_set_backlight_level, 1900 .get_backlight_level = &atombios_get_backlight_level, 1901 .hdmi_enable = &evergreen_hdmi_enable, 1902 .hdmi_setmode = &evergreen_hdmi_setmode, 1903 }, 1904 .copy = { 1905 .blit = &r600_copy_cpdma, 1906 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1907 .dma = &si_copy_dma, 1908 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1909 .copy = &si_copy_dma, 1910 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1911 }, 1912 .surface = { 1913 .set_reg = r600_set_surface_reg, 1914 .clear_reg = r600_clear_surface_reg, 1915 }, 1916 .hpd = { 1917 .init = &evergreen_hpd_init, 1918 .fini = &evergreen_hpd_fini, 1919 .sense = &evergreen_hpd_sense, 1920 .set_polarity = &evergreen_hpd_set_polarity, 1921 }, 1922 .pm = { 1923 .misc = &evergreen_pm_misc, 1924 .prepare = &evergreen_pm_prepare, 1925 .finish = &evergreen_pm_finish, 1926 .init_profile = &sumo_pm_init_profile, 1927 .get_dynpm_state = &r600_pm_get_dynpm_state, 1928 .get_engine_clock = &radeon_atom_get_engine_clock, 1929 .set_engine_clock = &radeon_atom_set_engine_clock, 1930 .get_memory_clock = &radeon_atom_get_memory_clock, 1931 .set_memory_clock = &radeon_atom_set_memory_clock, 1932 .get_pcie_lanes = &r600_get_pcie_lanes, 1933 .set_pcie_lanes = &r600_set_pcie_lanes, 1934 .set_clock_gating = NULL, 1935 .set_uvd_clocks = &si_set_uvd_clocks, 1936 .get_temperature = &si_get_temp, 1937 }, 1938 .dpm = { 1939 .init = &si_dpm_init, 1940 .setup_asic = &si_dpm_setup_asic, 1941 .enable = &si_dpm_enable, 1942 .late_enable = &si_dpm_late_enable, 1943 .disable = &si_dpm_disable, 1944 .pre_set_power_state = &si_dpm_pre_set_power_state, 1945 .set_power_state = &si_dpm_set_power_state, 1946 .post_set_power_state = &si_dpm_post_set_power_state, 1947 .display_configuration_changed = &si_dpm_display_configuration_changed, 1948 .fini = &si_dpm_fini, 1949 .get_sclk = &ni_dpm_get_sclk, 1950 .get_mclk = &ni_dpm_get_mclk, 1951 .print_power_state = &ni_dpm_print_power_state, 1952 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level, 1953 .force_performance_level = &si_dpm_force_performance_level, 1954 .vblank_too_short = &ni_dpm_vblank_too_short, 1955 }, 1956 .pflip = { 1957 .page_flip = &evergreen_page_flip, 1958 .page_flip_pending = &evergreen_page_flip_pending, 1959 }, 1960 }; 1961 1962 static struct radeon_asic_ring ci_gfx_ring = { 1963 .ib_execute = &cik_ring_ib_execute, 1964 .ib_parse = &cik_ib_parse, 1965 .emit_fence = &cik_fence_gfx_ring_emit, 1966 .emit_semaphore = &cik_semaphore_ring_emit, 1967 .cs_parse = NULL, 1968 .ring_test = &cik_ring_test, 1969 .ib_test = &cik_ib_test, 1970 .is_lockup = &cik_gfx_is_lockup, 1971 .vm_flush = &cik_vm_flush, 1972 .get_rptr = &cik_gfx_get_rptr, 1973 .get_wptr = &cik_gfx_get_wptr, 1974 .set_wptr = &cik_gfx_set_wptr, 1975 }; 1976 1977 static struct radeon_asic_ring ci_cp_ring = { 1978 .ib_execute = &cik_ring_ib_execute, 1979 .ib_parse = &cik_ib_parse, 1980 .emit_fence = &cik_fence_compute_ring_emit, 1981 .emit_semaphore = &cik_semaphore_ring_emit, 1982 .cs_parse = NULL, 1983 .ring_test = &cik_ring_test, 1984 .ib_test = &cik_ib_test, 1985 .is_lockup = &cik_gfx_is_lockup, 1986 .vm_flush = &cik_vm_flush, 1987 .get_rptr = &cik_compute_get_rptr, 1988 .get_wptr = &cik_compute_get_wptr, 1989 .set_wptr = &cik_compute_set_wptr, 1990 }; 1991 1992 static struct radeon_asic_ring ci_dma_ring = { 1993 .ib_execute = &cik_sdma_ring_ib_execute, 1994 .ib_parse = &cik_ib_parse, 1995 .emit_fence = &cik_sdma_fence_ring_emit, 1996 .emit_semaphore = &cik_sdma_semaphore_ring_emit, 1997 .cs_parse = NULL, 1998 .ring_test = &cik_sdma_ring_test, 1999 .ib_test = &cik_sdma_ib_test, 2000 .is_lockup = &cik_sdma_is_lockup, 2001 .vm_flush = &cik_dma_vm_flush, 2002 .get_rptr = &cik_sdma_get_rptr, 2003 .get_wptr = &cik_sdma_get_wptr, 2004 .set_wptr = &cik_sdma_set_wptr, 2005 }; 2006 2007 static struct radeon_asic_ring ci_vce_ring = { 2008 .ib_execute = &radeon_vce_ib_execute, 2009 .emit_fence = &radeon_vce_fence_emit, 2010 .emit_semaphore = &radeon_vce_semaphore_emit, 2011 .cs_parse = &radeon_vce_cs_parse, 2012 .ring_test = &radeon_vce_ring_test, 2013 .ib_test = &radeon_vce_ib_test, 2014 .is_lockup = &radeon_ring_test_lockup, 2015 .get_rptr = &vce_v1_0_get_rptr, 2016 .get_wptr = &vce_v1_0_get_wptr, 2017 .set_wptr = &vce_v1_0_set_wptr, 2018 }; 2019 2020 static struct radeon_asic ci_asic = { 2021 .init = &cik_init, 2022 .fini = &cik_fini, 2023 .suspend = &cik_suspend, 2024 .resume = &cik_resume, 2025 .asic_reset = &cik_asic_reset, 2026 .vga_set_state = &r600_vga_set_state, 2027 .mmio_hdp_flush = &r600_mmio_hdp_flush, 2028 .gui_idle = &r600_gui_idle, 2029 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 2030 .get_xclk = &cik_get_xclk, 2031 .get_gpu_clock_counter = &cik_get_gpu_clock_counter, 2032 .gart = { 2033 .tlb_flush = &cik_pcie_gart_tlb_flush, 2034 .set_page = &rs600_gart_set_page, 2035 }, 2036 .vm = { 2037 .init = &cik_vm_init, 2038 .fini = &cik_vm_fini, 2039 .copy_pages = &cik_sdma_vm_copy_pages, 2040 .write_pages = &cik_sdma_vm_write_pages, 2041 .set_pages = &cik_sdma_vm_set_pages, 2042 .pad_ib = &cik_sdma_vm_pad_ib, 2043 }, 2044 .ring = { 2045 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, 2046 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, 2047 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, 2048 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, 2049 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, 2050 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 2051 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring, 2052 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring, 2053 }, 2054 .irq = { 2055 .set = &cik_irq_set, 2056 .process = &cik_irq_process, 2057 }, 2058 .display = { 2059 .bandwidth_update = &dce8_bandwidth_update, 2060 .get_vblank_counter = &evergreen_get_vblank_counter, 2061 .wait_for_vblank = &dce4_wait_for_vblank, 2062 .set_backlight_level = &atombios_set_backlight_level, 2063 .get_backlight_level = &atombios_get_backlight_level, 2064 .hdmi_enable = &evergreen_hdmi_enable, 2065 .hdmi_setmode = &evergreen_hdmi_setmode, 2066 }, 2067 .copy = { 2068 .blit = &cik_copy_cpdma, 2069 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2070 .dma = &cik_copy_dma, 2071 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2072 .copy = &cik_copy_dma, 2073 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 2074 }, 2075 .surface = { 2076 .set_reg = r600_set_surface_reg, 2077 .clear_reg = r600_clear_surface_reg, 2078 }, 2079 .hpd = { 2080 .init = &evergreen_hpd_init, 2081 .fini = &evergreen_hpd_fini, 2082 .sense = &evergreen_hpd_sense, 2083 .set_polarity = &evergreen_hpd_set_polarity, 2084 }, 2085 .pm = { 2086 .misc = &evergreen_pm_misc, 2087 .prepare = &evergreen_pm_prepare, 2088 .finish = &evergreen_pm_finish, 2089 .init_profile = &sumo_pm_init_profile, 2090 .get_dynpm_state = &r600_pm_get_dynpm_state, 2091 .get_engine_clock = &radeon_atom_get_engine_clock, 2092 .set_engine_clock = &radeon_atom_set_engine_clock, 2093 .get_memory_clock = &radeon_atom_get_memory_clock, 2094 .set_memory_clock = &radeon_atom_set_memory_clock, 2095 .get_pcie_lanes = NULL, 2096 .set_pcie_lanes = NULL, 2097 .set_clock_gating = NULL, 2098 .set_uvd_clocks = &cik_set_uvd_clocks, 2099 .set_vce_clocks = &cik_set_vce_clocks, 2100 .get_temperature = &ci_get_temp, 2101 }, 2102 .dpm = { 2103 .init = &ci_dpm_init, 2104 .setup_asic = &ci_dpm_setup_asic, 2105 .enable = &ci_dpm_enable, 2106 .late_enable = &ci_dpm_late_enable, 2107 .disable = &ci_dpm_disable, 2108 .pre_set_power_state = &ci_dpm_pre_set_power_state, 2109 .set_power_state = &ci_dpm_set_power_state, 2110 .post_set_power_state = &ci_dpm_post_set_power_state, 2111 .display_configuration_changed = &ci_dpm_display_configuration_changed, 2112 .fini = &ci_dpm_fini, 2113 .get_sclk = &ci_dpm_get_sclk, 2114 .get_mclk = &ci_dpm_get_mclk, 2115 .print_power_state = &ci_dpm_print_power_state, 2116 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level, 2117 .force_performance_level = &ci_dpm_force_performance_level, 2118 .vblank_too_short = &ci_dpm_vblank_too_short, 2119 .powergate_uvd = &ci_dpm_powergate_uvd, 2120 }, 2121 .pflip = { 2122 .page_flip = &evergreen_page_flip, 2123 .page_flip_pending = &evergreen_page_flip_pending, 2124 }, 2125 }; 2126 2127 static struct radeon_asic kv_asic = { 2128 .init = &cik_init, 2129 .fini = &cik_fini, 2130 .suspend = &cik_suspend, 2131 .resume = &cik_resume, 2132 .asic_reset = &cik_asic_reset, 2133 .vga_set_state = &r600_vga_set_state, 2134 .mmio_hdp_flush = &r600_mmio_hdp_flush, 2135 .gui_idle = &r600_gui_idle, 2136 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 2137 .get_xclk = &cik_get_xclk, 2138 .get_gpu_clock_counter = &cik_get_gpu_clock_counter, 2139 .gart = { 2140 .tlb_flush = &cik_pcie_gart_tlb_flush, 2141 .set_page = &rs600_gart_set_page, 2142 }, 2143 .vm = { 2144 .init = &cik_vm_init, 2145 .fini = &cik_vm_fini, 2146 .copy_pages = &cik_sdma_vm_copy_pages, 2147 .write_pages = &cik_sdma_vm_write_pages, 2148 .set_pages = &cik_sdma_vm_set_pages, 2149 .pad_ib = &cik_sdma_vm_pad_ib, 2150 }, 2151 .ring = { 2152 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, 2153 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, 2154 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, 2155 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, 2156 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, 2157 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 2158 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring, 2159 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring, 2160 }, 2161 .irq = { 2162 .set = &cik_irq_set, 2163 .process = &cik_irq_process, 2164 }, 2165 .display = { 2166 .bandwidth_update = &dce8_bandwidth_update, 2167 .get_vblank_counter = &evergreen_get_vblank_counter, 2168 .wait_for_vblank = &dce4_wait_for_vblank, 2169 .set_backlight_level = &atombios_set_backlight_level, 2170 .get_backlight_level = &atombios_get_backlight_level, 2171 .hdmi_enable = &evergreen_hdmi_enable, 2172 .hdmi_setmode = &evergreen_hdmi_setmode, 2173 }, 2174 .copy = { 2175 .blit = &cik_copy_cpdma, 2176 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2177 .dma = &cik_copy_dma, 2178 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2179 .copy = &cik_copy_dma, 2180 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 2181 }, 2182 .surface = { 2183 .set_reg = r600_set_surface_reg, 2184 .clear_reg = r600_clear_surface_reg, 2185 }, 2186 .hpd = { 2187 .init = &evergreen_hpd_init, 2188 .fini = &evergreen_hpd_fini, 2189 .sense = &evergreen_hpd_sense, 2190 .set_polarity = &evergreen_hpd_set_polarity, 2191 }, 2192 .pm = { 2193 .misc = &evergreen_pm_misc, 2194 .prepare = &evergreen_pm_prepare, 2195 .finish = &evergreen_pm_finish, 2196 .init_profile = &sumo_pm_init_profile, 2197 .get_dynpm_state = &r600_pm_get_dynpm_state, 2198 .get_engine_clock = &radeon_atom_get_engine_clock, 2199 .set_engine_clock = &radeon_atom_set_engine_clock, 2200 .get_memory_clock = &radeon_atom_get_memory_clock, 2201 .set_memory_clock = &radeon_atom_set_memory_clock, 2202 .get_pcie_lanes = NULL, 2203 .set_pcie_lanes = NULL, 2204 .set_clock_gating = NULL, 2205 .set_uvd_clocks = &cik_set_uvd_clocks, 2206 .set_vce_clocks = &cik_set_vce_clocks, 2207 .get_temperature = &kv_get_temp, 2208 }, 2209 .dpm = { 2210 .init = &kv_dpm_init, 2211 .setup_asic = &kv_dpm_setup_asic, 2212 .enable = &kv_dpm_enable, 2213 .late_enable = &kv_dpm_late_enable, 2214 .disable = &kv_dpm_disable, 2215 .pre_set_power_state = &kv_dpm_pre_set_power_state, 2216 .set_power_state = &kv_dpm_set_power_state, 2217 .post_set_power_state = &kv_dpm_post_set_power_state, 2218 .display_configuration_changed = &kv_dpm_display_configuration_changed, 2219 .fini = &kv_dpm_fini, 2220 .get_sclk = &kv_dpm_get_sclk, 2221 .get_mclk = &kv_dpm_get_mclk, 2222 .print_power_state = &kv_dpm_print_power_state, 2223 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level, 2224 .force_performance_level = &kv_dpm_force_performance_level, 2225 .powergate_uvd = &kv_dpm_powergate_uvd, 2226 .enable_bapm = &kv_dpm_enable_bapm, 2227 }, 2228 .pflip = { 2229 .page_flip = &evergreen_page_flip, 2230 .page_flip_pending = &evergreen_page_flip_pending, 2231 }, 2232 }; 2233 2234 /** 2235 * radeon_asic_init - register asic specific callbacks 2236 * 2237 * @rdev: radeon device pointer 2238 * 2239 * Registers the appropriate asic specific callbacks for each 2240 * chip family. Also sets other asics specific info like the number 2241 * of crtcs and the register aperture accessors (all asics). 2242 * Returns 0 for success. 2243 */ 2244 int radeon_asic_init(struct radeon_device *rdev) 2245 { 2246 radeon_register_accessor_init(rdev); 2247 2248 /* set the number of crtcs */ 2249 if (rdev->flags & RADEON_SINGLE_CRTC) 2250 rdev->num_crtc = 1; 2251 else 2252 rdev->num_crtc = 2; 2253 2254 rdev->has_uvd = false; 2255 2256 switch (rdev->family) { 2257 case CHIP_R100: 2258 case CHIP_RV100: 2259 case CHIP_RS100: 2260 case CHIP_RV200: 2261 case CHIP_RS200: 2262 rdev->asic = &r100_asic; 2263 break; 2264 case CHIP_R200: 2265 case CHIP_RV250: 2266 case CHIP_RS300: 2267 case CHIP_RV280: 2268 rdev->asic = &r200_asic; 2269 break; 2270 case CHIP_R300: 2271 case CHIP_R350: 2272 case CHIP_RV350: 2273 case CHIP_RV380: 2274 if (rdev->flags & RADEON_IS_PCIE) 2275 rdev->asic = &r300_asic_pcie; 2276 else 2277 rdev->asic = &r300_asic; 2278 break; 2279 case CHIP_R420: 2280 case CHIP_R423: 2281 case CHIP_RV410: 2282 rdev->asic = &r420_asic; 2283 /* handle macs */ 2284 if (rdev->bios == NULL) { 2285 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock; 2286 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock; 2287 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock; 2288 rdev->asic->pm.set_memory_clock = NULL; 2289 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level; 2290 } 2291 break; 2292 case CHIP_RS400: 2293 case CHIP_RS480: 2294 rdev->asic = &rs400_asic; 2295 break; 2296 case CHIP_RS600: 2297 rdev->asic = &rs600_asic; 2298 break; 2299 case CHIP_RS690: 2300 case CHIP_RS740: 2301 rdev->asic = &rs690_asic; 2302 break; 2303 case CHIP_RV515: 2304 rdev->asic = &rv515_asic; 2305 break; 2306 case CHIP_R520: 2307 case CHIP_RV530: 2308 case CHIP_RV560: 2309 case CHIP_RV570: 2310 case CHIP_R580: 2311 rdev->asic = &r520_asic; 2312 break; 2313 case CHIP_R600: 2314 rdev->asic = &r600_asic; 2315 break; 2316 case CHIP_RV610: 2317 case CHIP_RV630: 2318 case CHIP_RV620: 2319 case CHIP_RV635: 2320 case CHIP_RV670: 2321 rdev->asic = &rv6xx_asic; 2322 rdev->has_uvd = true; 2323 break; 2324 case CHIP_RS780: 2325 case CHIP_RS880: 2326 rdev->asic = &rs780_asic; 2327 /* 760G/780V/880V don't have UVD */ 2328 if ((rdev->pdev->device == 0x9616)|| 2329 (rdev->pdev->device == 0x9611)|| 2330 (rdev->pdev->device == 0x9613)|| 2331 (rdev->pdev->device == 0x9711)|| 2332 (rdev->pdev->device == 0x9713)) 2333 rdev->has_uvd = false; 2334 else 2335 rdev->has_uvd = true; 2336 break; 2337 case CHIP_RV770: 2338 case CHIP_RV730: 2339 case CHIP_RV710: 2340 case CHIP_RV740: 2341 rdev->asic = &rv770_asic; 2342 rdev->has_uvd = true; 2343 break; 2344 case CHIP_CEDAR: 2345 case CHIP_REDWOOD: 2346 case CHIP_JUNIPER: 2347 case CHIP_CYPRESS: 2348 case CHIP_HEMLOCK: 2349 /* set num crtcs */ 2350 if (rdev->family == CHIP_CEDAR) 2351 rdev->num_crtc = 4; 2352 else 2353 rdev->num_crtc = 6; 2354 rdev->asic = &evergreen_asic; 2355 rdev->has_uvd = true; 2356 break; 2357 case CHIP_PALM: 2358 case CHIP_SUMO: 2359 case CHIP_SUMO2: 2360 rdev->asic = &sumo_asic; 2361 rdev->has_uvd = true; 2362 break; 2363 case CHIP_BARTS: 2364 case CHIP_TURKS: 2365 case CHIP_CAICOS: 2366 /* set num crtcs */ 2367 if (rdev->family == CHIP_CAICOS) 2368 rdev->num_crtc = 4; 2369 else 2370 rdev->num_crtc = 6; 2371 rdev->asic = &btc_asic; 2372 rdev->has_uvd = true; 2373 break; 2374 case CHIP_CAYMAN: 2375 rdev->asic = &cayman_asic; 2376 /* set num crtcs */ 2377 rdev->num_crtc = 6; 2378 rdev->has_uvd = true; 2379 break; 2380 case CHIP_ARUBA: 2381 rdev->asic = &trinity_asic; 2382 /* set num crtcs */ 2383 rdev->num_crtc = 4; 2384 rdev->has_uvd = true; 2385 break; 2386 case CHIP_TAHITI: 2387 case CHIP_PITCAIRN: 2388 case CHIP_VERDE: 2389 case CHIP_OLAND: 2390 case CHIP_HAINAN: 2391 rdev->asic = &si_asic; 2392 /* set num crtcs */ 2393 if (rdev->family == CHIP_HAINAN) 2394 rdev->num_crtc = 0; 2395 else if (rdev->family == CHIP_OLAND) 2396 rdev->num_crtc = 2; 2397 else 2398 rdev->num_crtc = 6; 2399 if (rdev->family == CHIP_HAINAN) 2400 rdev->has_uvd = false; 2401 else 2402 rdev->has_uvd = true; 2403 switch (rdev->family) { 2404 case CHIP_TAHITI: 2405 rdev->cg_flags = 2406 RADEON_CG_SUPPORT_GFX_MGCG | 2407 RADEON_CG_SUPPORT_GFX_MGLS | 2408 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2409 RADEON_CG_SUPPORT_GFX_CGLS | 2410 RADEON_CG_SUPPORT_GFX_CGTS | 2411 RADEON_CG_SUPPORT_GFX_CP_LS | 2412 RADEON_CG_SUPPORT_MC_MGCG | 2413 RADEON_CG_SUPPORT_SDMA_MGCG | 2414 RADEON_CG_SUPPORT_BIF_LS | 2415 RADEON_CG_SUPPORT_VCE_MGCG | 2416 RADEON_CG_SUPPORT_UVD_MGCG | 2417 RADEON_CG_SUPPORT_HDP_LS | 2418 RADEON_CG_SUPPORT_HDP_MGCG; 2419 rdev->pg_flags = 0; 2420 break; 2421 case CHIP_PITCAIRN: 2422 rdev->cg_flags = 2423 RADEON_CG_SUPPORT_GFX_MGCG | 2424 RADEON_CG_SUPPORT_GFX_MGLS | 2425 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2426 RADEON_CG_SUPPORT_GFX_CGLS | 2427 RADEON_CG_SUPPORT_GFX_CGTS | 2428 RADEON_CG_SUPPORT_GFX_CP_LS | 2429 RADEON_CG_SUPPORT_GFX_RLC_LS | 2430 RADEON_CG_SUPPORT_MC_LS | 2431 RADEON_CG_SUPPORT_MC_MGCG | 2432 RADEON_CG_SUPPORT_SDMA_MGCG | 2433 RADEON_CG_SUPPORT_BIF_LS | 2434 RADEON_CG_SUPPORT_VCE_MGCG | 2435 RADEON_CG_SUPPORT_UVD_MGCG | 2436 RADEON_CG_SUPPORT_HDP_LS | 2437 RADEON_CG_SUPPORT_HDP_MGCG; 2438 rdev->pg_flags = 0; 2439 break; 2440 case CHIP_VERDE: 2441 rdev->cg_flags = 2442 RADEON_CG_SUPPORT_GFX_MGCG | 2443 RADEON_CG_SUPPORT_GFX_MGLS | 2444 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2445 RADEON_CG_SUPPORT_GFX_CGLS | 2446 RADEON_CG_SUPPORT_GFX_CGTS | 2447 RADEON_CG_SUPPORT_GFX_CP_LS | 2448 RADEON_CG_SUPPORT_GFX_RLC_LS | 2449 RADEON_CG_SUPPORT_MC_LS | 2450 RADEON_CG_SUPPORT_MC_MGCG | 2451 RADEON_CG_SUPPORT_SDMA_MGCG | 2452 RADEON_CG_SUPPORT_BIF_LS | 2453 RADEON_CG_SUPPORT_VCE_MGCG | 2454 RADEON_CG_SUPPORT_UVD_MGCG | 2455 RADEON_CG_SUPPORT_HDP_LS | 2456 RADEON_CG_SUPPORT_HDP_MGCG; 2457 rdev->pg_flags = 0 | 2458 /*RADEON_PG_SUPPORT_GFX_PG | */ 2459 RADEON_PG_SUPPORT_SDMA; 2460 break; 2461 case CHIP_OLAND: 2462 rdev->cg_flags = 2463 RADEON_CG_SUPPORT_GFX_MGCG | 2464 RADEON_CG_SUPPORT_GFX_MGLS | 2465 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2466 RADEON_CG_SUPPORT_GFX_CGLS | 2467 RADEON_CG_SUPPORT_GFX_CGTS | 2468 RADEON_CG_SUPPORT_GFX_CP_LS | 2469 RADEON_CG_SUPPORT_GFX_RLC_LS | 2470 RADEON_CG_SUPPORT_MC_LS | 2471 RADEON_CG_SUPPORT_MC_MGCG | 2472 RADEON_CG_SUPPORT_SDMA_MGCG | 2473 RADEON_CG_SUPPORT_BIF_LS | 2474 RADEON_CG_SUPPORT_UVD_MGCG | 2475 RADEON_CG_SUPPORT_HDP_LS | 2476 RADEON_CG_SUPPORT_HDP_MGCG; 2477 rdev->pg_flags = 0; 2478 break; 2479 case CHIP_HAINAN: 2480 rdev->cg_flags = 2481 RADEON_CG_SUPPORT_GFX_MGCG | 2482 RADEON_CG_SUPPORT_GFX_MGLS | 2483 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2484 RADEON_CG_SUPPORT_GFX_CGLS | 2485 RADEON_CG_SUPPORT_GFX_CGTS | 2486 RADEON_CG_SUPPORT_GFX_CP_LS | 2487 RADEON_CG_SUPPORT_GFX_RLC_LS | 2488 RADEON_CG_SUPPORT_MC_LS | 2489 RADEON_CG_SUPPORT_MC_MGCG | 2490 RADEON_CG_SUPPORT_SDMA_MGCG | 2491 RADEON_CG_SUPPORT_BIF_LS | 2492 RADEON_CG_SUPPORT_HDP_LS | 2493 RADEON_CG_SUPPORT_HDP_MGCG; 2494 rdev->pg_flags = 0; 2495 break; 2496 default: 2497 rdev->cg_flags = 0; 2498 rdev->pg_flags = 0; 2499 break; 2500 } 2501 break; 2502 case CHIP_BONAIRE: 2503 case CHIP_HAWAII: 2504 rdev->asic = &ci_asic; 2505 rdev->num_crtc = 6; 2506 rdev->has_uvd = true; 2507 if (rdev->family == CHIP_BONAIRE) { 2508 rdev->cg_flags = 2509 RADEON_CG_SUPPORT_GFX_MGCG | 2510 RADEON_CG_SUPPORT_GFX_MGLS | 2511 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2512 RADEON_CG_SUPPORT_GFX_CGLS | 2513 RADEON_CG_SUPPORT_GFX_CGTS | 2514 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2515 RADEON_CG_SUPPORT_GFX_CP_LS | 2516 RADEON_CG_SUPPORT_MC_LS | 2517 RADEON_CG_SUPPORT_MC_MGCG | 2518 RADEON_CG_SUPPORT_SDMA_MGCG | 2519 RADEON_CG_SUPPORT_SDMA_LS | 2520 RADEON_CG_SUPPORT_BIF_LS | 2521 RADEON_CG_SUPPORT_VCE_MGCG | 2522 RADEON_CG_SUPPORT_UVD_MGCG | 2523 RADEON_CG_SUPPORT_HDP_LS | 2524 RADEON_CG_SUPPORT_HDP_MGCG; 2525 rdev->pg_flags = 0; 2526 } else { 2527 rdev->cg_flags = 2528 RADEON_CG_SUPPORT_GFX_MGCG | 2529 RADEON_CG_SUPPORT_GFX_MGLS | 2530 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2531 RADEON_CG_SUPPORT_GFX_CGLS | 2532 RADEON_CG_SUPPORT_GFX_CGTS | 2533 RADEON_CG_SUPPORT_GFX_CP_LS | 2534 RADEON_CG_SUPPORT_MC_LS | 2535 RADEON_CG_SUPPORT_MC_MGCG | 2536 RADEON_CG_SUPPORT_SDMA_MGCG | 2537 RADEON_CG_SUPPORT_SDMA_LS | 2538 RADEON_CG_SUPPORT_BIF_LS | 2539 RADEON_CG_SUPPORT_VCE_MGCG | 2540 RADEON_CG_SUPPORT_UVD_MGCG | 2541 RADEON_CG_SUPPORT_HDP_LS | 2542 RADEON_CG_SUPPORT_HDP_MGCG; 2543 rdev->pg_flags = 0; 2544 } 2545 break; 2546 case CHIP_KAVERI: 2547 case CHIP_KABINI: 2548 case CHIP_MULLINS: 2549 rdev->asic = &kv_asic; 2550 /* set num crtcs */ 2551 if (rdev->family == CHIP_KAVERI) { 2552 rdev->num_crtc = 4; 2553 rdev->cg_flags = 2554 RADEON_CG_SUPPORT_GFX_MGCG | 2555 RADEON_CG_SUPPORT_GFX_MGLS | 2556 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2557 RADEON_CG_SUPPORT_GFX_CGLS | 2558 RADEON_CG_SUPPORT_GFX_CGTS | 2559 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2560 RADEON_CG_SUPPORT_GFX_CP_LS | 2561 RADEON_CG_SUPPORT_SDMA_MGCG | 2562 RADEON_CG_SUPPORT_SDMA_LS | 2563 RADEON_CG_SUPPORT_BIF_LS | 2564 RADEON_CG_SUPPORT_VCE_MGCG | 2565 RADEON_CG_SUPPORT_UVD_MGCG | 2566 RADEON_CG_SUPPORT_HDP_LS | 2567 RADEON_CG_SUPPORT_HDP_MGCG; 2568 rdev->pg_flags = 0; 2569 /*RADEON_PG_SUPPORT_GFX_PG | 2570 RADEON_PG_SUPPORT_GFX_SMG | 2571 RADEON_PG_SUPPORT_GFX_DMG | 2572 RADEON_PG_SUPPORT_UVD | 2573 RADEON_PG_SUPPORT_VCE | 2574 RADEON_PG_SUPPORT_CP | 2575 RADEON_PG_SUPPORT_GDS | 2576 RADEON_PG_SUPPORT_RLC_SMU_HS | 2577 RADEON_PG_SUPPORT_ACP | 2578 RADEON_PG_SUPPORT_SAMU;*/ 2579 } else { 2580 rdev->num_crtc = 2; 2581 rdev->cg_flags = 2582 RADEON_CG_SUPPORT_GFX_MGCG | 2583 RADEON_CG_SUPPORT_GFX_MGLS | 2584 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2585 RADEON_CG_SUPPORT_GFX_CGLS | 2586 RADEON_CG_SUPPORT_GFX_CGTS | 2587 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2588 RADEON_CG_SUPPORT_GFX_CP_LS | 2589 RADEON_CG_SUPPORT_SDMA_MGCG | 2590 RADEON_CG_SUPPORT_SDMA_LS | 2591 RADEON_CG_SUPPORT_BIF_LS | 2592 RADEON_CG_SUPPORT_VCE_MGCG | 2593 RADEON_CG_SUPPORT_UVD_MGCG | 2594 RADEON_CG_SUPPORT_HDP_LS | 2595 RADEON_CG_SUPPORT_HDP_MGCG; 2596 rdev->pg_flags = 0; 2597 /*RADEON_PG_SUPPORT_GFX_PG | 2598 RADEON_PG_SUPPORT_GFX_SMG | 2599 RADEON_PG_SUPPORT_UVD | 2600 RADEON_PG_SUPPORT_VCE | 2601 RADEON_PG_SUPPORT_CP | 2602 RADEON_PG_SUPPORT_GDS | 2603 RADEON_PG_SUPPORT_RLC_SMU_HS | 2604 RADEON_PG_SUPPORT_SAMU;*/ 2605 } 2606 rdev->has_uvd = true; 2607 break; 2608 default: 2609 /* FIXME: not supported yet */ 2610 return -EINVAL; 2611 } 2612 2613 if (rdev->flags & RADEON_IS_IGP) { 2614 rdev->asic->pm.get_memory_clock = NULL; 2615 rdev->asic->pm.set_memory_clock = NULL; 2616 } 2617 2618 return 0; 2619 } 2620 2621