1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * 28 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_asic.c 254885 2013-08-25 19:37:15Z dumbbell $ 29 */ 30 31 #include <drm/drmP.h> 32 #include <drm/drm_crtc_helper.h> 33 #include <uapi_drm/radeon_drm.h> 34 #include "radeon_reg.h" 35 #include "radeon.h" 36 #include "radeon_asic.h" 37 #include "atom.h" 38 39 /* 40 * Registers accessors functions. 41 */ 42 /** 43 * radeon_invalid_rreg - dummy reg read function 44 * 45 * @rdev: radeon device pointer 46 * @reg: offset of register 47 * 48 * Dummy register read function. Used for register blocks 49 * that certain asics don't have (all asics). 50 * Returns the value in the register. 51 */ 52 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) 53 { 54 panic("Invalid callback to read register 0x%04X\n", reg); 55 return 0; 56 } 57 58 /** 59 * radeon_invalid_wreg - dummy reg write function 60 * 61 * @rdev: radeon device pointer 62 * @reg: offset of register 63 * @v: value to write to the register 64 * 65 * Dummy register read function. Used for register blocks 66 * that certain asics don't have (all asics). 67 */ 68 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 69 { 70 panic("Invalid callback to write register 0x%04X with 0x%08X\n", 71 reg, v); 72 } 73 74 /** 75 * radeon_register_accessor_init - sets up the register accessor callbacks 76 * 77 * @rdev: radeon device pointer 78 * 79 * Sets up the register accessor callbacks for various register 80 * apertures. Not all asics have all apertures (all asics). 81 */ 82 static void radeon_register_accessor_init(struct radeon_device *rdev) 83 { 84 rdev->mc_rreg = &radeon_invalid_rreg; 85 rdev->mc_wreg = &radeon_invalid_wreg; 86 rdev->pll_rreg = &radeon_invalid_rreg; 87 rdev->pll_wreg = &radeon_invalid_wreg; 88 rdev->pciep_rreg = &radeon_invalid_rreg; 89 rdev->pciep_wreg = &radeon_invalid_wreg; 90 91 /* Don't change order as we are overridding accessor. */ 92 if (rdev->family < CHIP_RV515) { 93 rdev->pcie_reg_mask = 0xff; 94 } else { 95 rdev->pcie_reg_mask = 0x7ff; 96 } 97 /* FIXME: not sure here */ 98 if (rdev->family <= CHIP_R580) { 99 rdev->pll_rreg = &r100_pll_rreg; 100 rdev->pll_wreg = &r100_pll_wreg; 101 } 102 if (rdev->family >= CHIP_R420) { 103 rdev->mc_rreg = &r420_mc_rreg; 104 rdev->mc_wreg = &r420_mc_wreg; 105 } 106 if (rdev->family >= CHIP_RV515) { 107 rdev->mc_rreg = &rv515_mc_rreg; 108 rdev->mc_wreg = &rv515_mc_wreg; 109 } 110 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { 111 rdev->mc_rreg = &rs400_mc_rreg; 112 rdev->mc_wreg = &rs400_mc_wreg; 113 } 114 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 115 rdev->mc_rreg = &rs690_mc_rreg; 116 rdev->mc_wreg = &rs690_mc_wreg; 117 } 118 if (rdev->family == CHIP_RS600) { 119 rdev->mc_rreg = &rs600_mc_rreg; 120 rdev->mc_wreg = &rs600_mc_wreg; 121 } 122 if (rdev->family >= CHIP_R600) { 123 rdev->pciep_rreg = &r600_pciep_rreg; 124 rdev->pciep_wreg = &r600_pciep_wreg; 125 } 126 } 127 128 129 /* helper to disable agp */ 130 /** 131 * radeon_agp_disable - AGP disable helper function 132 * 133 * @rdev: radeon device pointer 134 * 135 * Removes AGP flags and changes the gart callbacks on AGP 136 * cards when using the internal gart rather than AGP (all asics). 137 */ 138 void radeon_agp_disable(struct radeon_device *rdev) 139 { 140 rdev->flags &= ~RADEON_IS_AGP; 141 if (rdev->family >= CHIP_R600) { 142 DRM_INFO("Forcing AGP to PCIE mode\n"); 143 rdev->flags |= RADEON_IS_PCIE; 144 } else if (rdev->family >= CHIP_RV515 || 145 rdev->family == CHIP_RV380 || 146 rdev->family == CHIP_RV410 || 147 rdev->family == CHIP_R423) { 148 DRM_INFO("Forcing AGP to PCIE mode\n"); 149 rdev->flags |= RADEON_IS_PCIE; 150 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; 151 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; 152 } else { 153 DRM_INFO("Forcing AGP to PCI mode\n"); 154 rdev->flags |= RADEON_IS_PCI; 155 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; 156 rdev->asic->gart.set_page = &r100_pci_gart_set_page; 157 } 158 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 159 } 160 161 /* 162 * ASIC 163 */ 164 static struct radeon_asic r100_asic = { 165 .init = &r100_init, 166 .fini = &r100_fini, 167 .suspend = &r100_suspend, 168 .resume = &r100_resume, 169 .vga_set_state = &r100_vga_set_state, 170 .asic_reset = &r100_asic_reset, 171 .ioctl_wait_idle = NULL, 172 .gui_idle = &r100_gui_idle, 173 .mc_wait_for_idle = &r100_mc_wait_for_idle, 174 .gart = { 175 .tlb_flush = &r100_pci_gart_tlb_flush, 176 .set_page = &r100_pci_gart_set_page, 177 }, 178 .ring = { 179 [RADEON_RING_TYPE_GFX_INDEX] = { 180 .ib_execute = &r100_ring_ib_execute, 181 .emit_fence = &r100_fence_ring_emit, 182 .emit_semaphore = &r100_semaphore_ring_emit, 183 .cs_parse = &r100_cs_parse, 184 .ring_start = &r100_ring_start, 185 .ring_test = &r100_ring_test, 186 .ib_test = &r100_ib_test, 187 .is_lockup = &r100_gpu_is_lockup, 188 } 189 }, 190 .irq = { 191 .set = &r100_irq_set, 192 .process = &r100_irq_process, 193 }, 194 .display = { 195 .bandwidth_update = &r100_bandwidth_update, 196 .get_vblank_counter = &r100_get_vblank_counter, 197 .wait_for_vblank = &r100_wait_for_vblank, 198 .set_backlight_level = &radeon_legacy_set_backlight_level, 199 .get_backlight_level = &radeon_legacy_get_backlight_level, 200 }, 201 .copy = { 202 .blit = &r100_copy_blit, 203 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 204 .dma = NULL, 205 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 206 .copy = &r100_copy_blit, 207 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 208 }, 209 .surface = { 210 .set_reg = r100_set_surface_reg, 211 .clear_reg = r100_clear_surface_reg, 212 }, 213 .hpd = { 214 .init = &r100_hpd_init, 215 .fini = &r100_hpd_fini, 216 .sense = &r100_hpd_sense, 217 .set_polarity = &r100_hpd_set_polarity, 218 }, 219 .pm = { 220 .misc = &r100_pm_misc, 221 .prepare = &r100_pm_prepare, 222 .finish = &r100_pm_finish, 223 .init_profile = &r100_pm_init_profile, 224 .get_dynpm_state = &r100_pm_get_dynpm_state, 225 .get_engine_clock = &radeon_legacy_get_engine_clock, 226 .set_engine_clock = &radeon_legacy_set_engine_clock, 227 .get_memory_clock = &radeon_legacy_get_memory_clock, 228 .set_memory_clock = NULL, 229 .get_pcie_lanes = NULL, 230 .set_pcie_lanes = NULL, 231 .set_clock_gating = &radeon_legacy_set_clock_gating, 232 }, 233 .pflip = { 234 .pre_page_flip = &r100_pre_page_flip, 235 .page_flip = &r100_page_flip, 236 .post_page_flip = &r100_post_page_flip, 237 }, 238 }; 239 240 static struct radeon_asic r200_asic = { 241 .init = &r100_init, 242 .fini = &r100_fini, 243 .suspend = &r100_suspend, 244 .resume = &r100_resume, 245 .vga_set_state = &r100_vga_set_state, 246 .asic_reset = &r100_asic_reset, 247 .ioctl_wait_idle = NULL, 248 .gui_idle = &r100_gui_idle, 249 .mc_wait_for_idle = &r100_mc_wait_for_idle, 250 .gart = { 251 .tlb_flush = &r100_pci_gart_tlb_flush, 252 .set_page = &r100_pci_gart_set_page, 253 }, 254 .ring = { 255 [RADEON_RING_TYPE_GFX_INDEX] = { 256 .ib_execute = &r100_ring_ib_execute, 257 .emit_fence = &r100_fence_ring_emit, 258 .emit_semaphore = &r100_semaphore_ring_emit, 259 .cs_parse = &r100_cs_parse, 260 .ring_start = &r100_ring_start, 261 .ring_test = &r100_ring_test, 262 .ib_test = &r100_ib_test, 263 .is_lockup = &r100_gpu_is_lockup, 264 } 265 }, 266 .irq = { 267 .set = &r100_irq_set, 268 .process = &r100_irq_process, 269 }, 270 .display = { 271 .bandwidth_update = &r100_bandwidth_update, 272 .get_vblank_counter = &r100_get_vblank_counter, 273 .wait_for_vblank = &r100_wait_for_vblank, 274 .set_backlight_level = &radeon_legacy_set_backlight_level, 275 .get_backlight_level = &radeon_legacy_get_backlight_level, 276 }, 277 .copy = { 278 .blit = &r100_copy_blit, 279 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 280 .dma = &r200_copy_dma, 281 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 282 .copy = &r100_copy_blit, 283 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 284 }, 285 .surface = { 286 .set_reg = r100_set_surface_reg, 287 .clear_reg = r100_clear_surface_reg, 288 }, 289 .hpd = { 290 .init = &r100_hpd_init, 291 .fini = &r100_hpd_fini, 292 .sense = &r100_hpd_sense, 293 .set_polarity = &r100_hpd_set_polarity, 294 }, 295 .pm = { 296 .misc = &r100_pm_misc, 297 .prepare = &r100_pm_prepare, 298 .finish = &r100_pm_finish, 299 .init_profile = &r100_pm_init_profile, 300 .get_dynpm_state = &r100_pm_get_dynpm_state, 301 .get_engine_clock = &radeon_legacy_get_engine_clock, 302 .set_engine_clock = &radeon_legacy_set_engine_clock, 303 .get_memory_clock = &radeon_legacy_get_memory_clock, 304 .set_memory_clock = NULL, 305 .get_pcie_lanes = NULL, 306 .set_pcie_lanes = NULL, 307 .set_clock_gating = &radeon_legacy_set_clock_gating, 308 }, 309 .pflip = { 310 .pre_page_flip = &r100_pre_page_flip, 311 .page_flip = &r100_page_flip, 312 .post_page_flip = &r100_post_page_flip, 313 }, 314 }; 315 316 static struct radeon_asic r300_asic = { 317 .init = &r300_init, 318 .fini = &r300_fini, 319 .suspend = &r300_suspend, 320 .resume = &r300_resume, 321 .vga_set_state = &r100_vga_set_state, 322 .asic_reset = &r300_asic_reset, 323 .ioctl_wait_idle = NULL, 324 .gui_idle = &r100_gui_idle, 325 .mc_wait_for_idle = &r300_mc_wait_for_idle, 326 .gart = { 327 .tlb_flush = &r100_pci_gart_tlb_flush, 328 .set_page = &r100_pci_gart_set_page, 329 }, 330 .ring = { 331 [RADEON_RING_TYPE_GFX_INDEX] = { 332 .ib_execute = &r100_ring_ib_execute, 333 .emit_fence = &r300_fence_ring_emit, 334 .emit_semaphore = &r100_semaphore_ring_emit, 335 .cs_parse = &r300_cs_parse, 336 .ring_start = &r300_ring_start, 337 .ring_test = &r100_ring_test, 338 .ib_test = &r100_ib_test, 339 .is_lockup = &r100_gpu_is_lockup, 340 } 341 }, 342 .irq = { 343 .set = &r100_irq_set, 344 .process = &r100_irq_process, 345 }, 346 .display = { 347 .bandwidth_update = &r100_bandwidth_update, 348 .get_vblank_counter = &r100_get_vblank_counter, 349 .wait_for_vblank = &r100_wait_for_vblank, 350 .set_backlight_level = &radeon_legacy_set_backlight_level, 351 .get_backlight_level = &radeon_legacy_get_backlight_level, 352 }, 353 .copy = { 354 .blit = &r100_copy_blit, 355 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 356 .dma = &r200_copy_dma, 357 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 358 .copy = &r100_copy_blit, 359 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 360 }, 361 .surface = { 362 .set_reg = r100_set_surface_reg, 363 .clear_reg = r100_clear_surface_reg, 364 }, 365 .hpd = { 366 .init = &r100_hpd_init, 367 .fini = &r100_hpd_fini, 368 .sense = &r100_hpd_sense, 369 .set_polarity = &r100_hpd_set_polarity, 370 }, 371 .pm = { 372 .misc = &r100_pm_misc, 373 .prepare = &r100_pm_prepare, 374 .finish = &r100_pm_finish, 375 .init_profile = &r100_pm_init_profile, 376 .get_dynpm_state = &r100_pm_get_dynpm_state, 377 .get_engine_clock = &radeon_legacy_get_engine_clock, 378 .set_engine_clock = &radeon_legacy_set_engine_clock, 379 .get_memory_clock = &radeon_legacy_get_memory_clock, 380 .set_memory_clock = NULL, 381 .get_pcie_lanes = &rv370_get_pcie_lanes, 382 .set_pcie_lanes = &rv370_set_pcie_lanes, 383 .set_clock_gating = &radeon_legacy_set_clock_gating, 384 }, 385 .pflip = { 386 .pre_page_flip = &r100_pre_page_flip, 387 .page_flip = &r100_page_flip, 388 .post_page_flip = &r100_post_page_flip, 389 }, 390 }; 391 392 static struct radeon_asic r300_asic_pcie = { 393 .init = &r300_init, 394 .fini = &r300_fini, 395 .suspend = &r300_suspend, 396 .resume = &r300_resume, 397 .vga_set_state = &r100_vga_set_state, 398 .asic_reset = &r300_asic_reset, 399 .ioctl_wait_idle = NULL, 400 .gui_idle = &r100_gui_idle, 401 .mc_wait_for_idle = &r300_mc_wait_for_idle, 402 .gart = { 403 .tlb_flush = &rv370_pcie_gart_tlb_flush, 404 .set_page = &rv370_pcie_gart_set_page, 405 }, 406 .ring = { 407 [RADEON_RING_TYPE_GFX_INDEX] = { 408 .ib_execute = &r100_ring_ib_execute, 409 .emit_fence = &r300_fence_ring_emit, 410 .emit_semaphore = &r100_semaphore_ring_emit, 411 .cs_parse = &r300_cs_parse, 412 .ring_start = &r300_ring_start, 413 .ring_test = &r100_ring_test, 414 .ib_test = &r100_ib_test, 415 .is_lockup = &r100_gpu_is_lockup, 416 } 417 }, 418 .irq = { 419 .set = &r100_irq_set, 420 .process = &r100_irq_process, 421 }, 422 .display = { 423 .bandwidth_update = &r100_bandwidth_update, 424 .get_vblank_counter = &r100_get_vblank_counter, 425 .wait_for_vblank = &r100_wait_for_vblank, 426 .set_backlight_level = &radeon_legacy_set_backlight_level, 427 .get_backlight_level = &radeon_legacy_get_backlight_level, 428 }, 429 .copy = { 430 .blit = &r100_copy_blit, 431 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 432 .dma = &r200_copy_dma, 433 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 434 .copy = &r100_copy_blit, 435 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 436 }, 437 .surface = { 438 .set_reg = r100_set_surface_reg, 439 .clear_reg = r100_clear_surface_reg, 440 }, 441 .hpd = { 442 .init = &r100_hpd_init, 443 .fini = &r100_hpd_fini, 444 .sense = &r100_hpd_sense, 445 .set_polarity = &r100_hpd_set_polarity, 446 }, 447 .pm = { 448 .misc = &r100_pm_misc, 449 .prepare = &r100_pm_prepare, 450 .finish = &r100_pm_finish, 451 .init_profile = &r100_pm_init_profile, 452 .get_dynpm_state = &r100_pm_get_dynpm_state, 453 .get_engine_clock = &radeon_legacy_get_engine_clock, 454 .set_engine_clock = &radeon_legacy_set_engine_clock, 455 .get_memory_clock = &radeon_legacy_get_memory_clock, 456 .set_memory_clock = NULL, 457 .get_pcie_lanes = &rv370_get_pcie_lanes, 458 .set_pcie_lanes = &rv370_set_pcie_lanes, 459 .set_clock_gating = &radeon_legacy_set_clock_gating, 460 }, 461 .pflip = { 462 .pre_page_flip = &r100_pre_page_flip, 463 .page_flip = &r100_page_flip, 464 .post_page_flip = &r100_post_page_flip, 465 }, 466 }; 467 468 static struct radeon_asic r420_asic = { 469 .init = &r420_init, 470 .fini = &r420_fini, 471 .suspend = &r420_suspend, 472 .resume = &r420_resume, 473 .vga_set_state = &r100_vga_set_state, 474 .asic_reset = &r300_asic_reset, 475 .ioctl_wait_idle = NULL, 476 .gui_idle = &r100_gui_idle, 477 .mc_wait_for_idle = &r300_mc_wait_for_idle, 478 .gart = { 479 .tlb_flush = &rv370_pcie_gart_tlb_flush, 480 .set_page = &rv370_pcie_gart_set_page, 481 }, 482 .ring = { 483 [RADEON_RING_TYPE_GFX_INDEX] = { 484 .ib_execute = &r100_ring_ib_execute, 485 .emit_fence = &r300_fence_ring_emit, 486 .emit_semaphore = &r100_semaphore_ring_emit, 487 .cs_parse = &r300_cs_parse, 488 .ring_start = &r300_ring_start, 489 .ring_test = &r100_ring_test, 490 .ib_test = &r100_ib_test, 491 .is_lockup = &r100_gpu_is_lockup, 492 } 493 }, 494 .irq = { 495 .set = &r100_irq_set, 496 .process = &r100_irq_process, 497 }, 498 .display = { 499 .bandwidth_update = &r100_bandwidth_update, 500 .get_vblank_counter = &r100_get_vblank_counter, 501 .wait_for_vblank = &r100_wait_for_vblank, 502 .set_backlight_level = &atombios_set_backlight_level, 503 .get_backlight_level = &atombios_get_backlight_level, 504 }, 505 .copy = { 506 .blit = &r100_copy_blit, 507 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 508 .dma = &r200_copy_dma, 509 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 510 .copy = &r100_copy_blit, 511 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 512 }, 513 .surface = { 514 .set_reg = r100_set_surface_reg, 515 .clear_reg = r100_clear_surface_reg, 516 }, 517 .hpd = { 518 .init = &r100_hpd_init, 519 .fini = &r100_hpd_fini, 520 .sense = &r100_hpd_sense, 521 .set_polarity = &r100_hpd_set_polarity, 522 }, 523 .pm = { 524 .misc = &r100_pm_misc, 525 .prepare = &r100_pm_prepare, 526 .finish = &r100_pm_finish, 527 .init_profile = &r420_pm_init_profile, 528 .get_dynpm_state = &r100_pm_get_dynpm_state, 529 .get_engine_clock = &radeon_atom_get_engine_clock, 530 .set_engine_clock = &radeon_atom_set_engine_clock, 531 .get_memory_clock = &radeon_atom_get_memory_clock, 532 .set_memory_clock = &radeon_atom_set_memory_clock, 533 .get_pcie_lanes = &rv370_get_pcie_lanes, 534 .set_pcie_lanes = &rv370_set_pcie_lanes, 535 .set_clock_gating = &radeon_atom_set_clock_gating, 536 }, 537 .pflip = { 538 .pre_page_flip = &r100_pre_page_flip, 539 .page_flip = &r100_page_flip, 540 .post_page_flip = &r100_post_page_flip, 541 }, 542 }; 543 544 static struct radeon_asic rs400_asic = { 545 .init = &rs400_init, 546 .fini = &rs400_fini, 547 .suspend = &rs400_suspend, 548 .resume = &rs400_resume, 549 .vga_set_state = &r100_vga_set_state, 550 .asic_reset = &r300_asic_reset, 551 .ioctl_wait_idle = NULL, 552 .gui_idle = &r100_gui_idle, 553 .mc_wait_for_idle = &rs400_mc_wait_for_idle, 554 .gart = { 555 .tlb_flush = &rs400_gart_tlb_flush, 556 .set_page = &rs400_gart_set_page, 557 }, 558 .ring = { 559 [RADEON_RING_TYPE_GFX_INDEX] = { 560 .ib_execute = &r100_ring_ib_execute, 561 .emit_fence = &r300_fence_ring_emit, 562 .emit_semaphore = &r100_semaphore_ring_emit, 563 .cs_parse = &r300_cs_parse, 564 .ring_start = &r300_ring_start, 565 .ring_test = &r100_ring_test, 566 .ib_test = &r100_ib_test, 567 .is_lockup = &r100_gpu_is_lockup, 568 } 569 }, 570 .irq = { 571 .set = &r100_irq_set, 572 .process = &r100_irq_process, 573 }, 574 .display = { 575 .bandwidth_update = &r100_bandwidth_update, 576 .get_vblank_counter = &r100_get_vblank_counter, 577 .wait_for_vblank = &r100_wait_for_vblank, 578 .set_backlight_level = &radeon_legacy_set_backlight_level, 579 .get_backlight_level = &radeon_legacy_get_backlight_level, 580 }, 581 .copy = { 582 .blit = &r100_copy_blit, 583 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 584 .dma = &r200_copy_dma, 585 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 586 .copy = &r100_copy_blit, 587 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 588 }, 589 .surface = { 590 .set_reg = r100_set_surface_reg, 591 .clear_reg = r100_clear_surface_reg, 592 }, 593 .hpd = { 594 .init = &r100_hpd_init, 595 .fini = &r100_hpd_fini, 596 .sense = &r100_hpd_sense, 597 .set_polarity = &r100_hpd_set_polarity, 598 }, 599 .pm = { 600 .misc = &r100_pm_misc, 601 .prepare = &r100_pm_prepare, 602 .finish = &r100_pm_finish, 603 .init_profile = &r100_pm_init_profile, 604 .get_dynpm_state = &r100_pm_get_dynpm_state, 605 .get_engine_clock = &radeon_legacy_get_engine_clock, 606 .set_engine_clock = &radeon_legacy_set_engine_clock, 607 .get_memory_clock = &radeon_legacy_get_memory_clock, 608 .set_memory_clock = NULL, 609 .get_pcie_lanes = NULL, 610 .set_pcie_lanes = NULL, 611 .set_clock_gating = &radeon_legacy_set_clock_gating, 612 }, 613 .pflip = { 614 .pre_page_flip = &r100_pre_page_flip, 615 .page_flip = &r100_page_flip, 616 .post_page_flip = &r100_post_page_flip, 617 }, 618 }; 619 620 static struct radeon_asic rs600_asic = { 621 .init = &rs600_init, 622 .fini = &rs600_fini, 623 .suspend = &rs600_suspend, 624 .resume = &rs600_resume, 625 .vga_set_state = &r100_vga_set_state, 626 .asic_reset = &rs600_asic_reset, 627 .ioctl_wait_idle = NULL, 628 .gui_idle = &r100_gui_idle, 629 .mc_wait_for_idle = &rs600_mc_wait_for_idle, 630 .gart = { 631 .tlb_flush = &rs600_gart_tlb_flush, 632 .set_page = &rs600_gart_set_page, 633 }, 634 .ring = { 635 [RADEON_RING_TYPE_GFX_INDEX] = { 636 .ib_execute = &r100_ring_ib_execute, 637 .emit_fence = &r300_fence_ring_emit, 638 .emit_semaphore = &r100_semaphore_ring_emit, 639 .cs_parse = &r300_cs_parse, 640 .ring_start = &r300_ring_start, 641 .ring_test = &r100_ring_test, 642 .ib_test = &r100_ib_test, 643 .is_lockup = &r100_gpu_is_lockup, 644 } 645 }, 646 .irq = { 647 .set = &rs600_irq_set, 648 .process = &rs600_irq_process, 649 }, 650 .display = { 651 .bandwidth_update = &rs600_bandwidth_update, 652 .get_vblank_counter = &rs600_get_vblank_counter, 653 .wait_for_vblank = &avivo_wait_for_vblank, 654 .set_backlight_level = &atombios_set_backlight_level, 655 .get_backlight_level = &atombios_get_backlight_level, 656 }, 657 .copy = { 658 .blit = &r100_copy_blit, 659 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 660 .dma = &r200_copy_dma, 661 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 662 .copy = &r100_copy_blit, 663 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 664 }, 665 .surface = { 666 .set_reg = r100_set_surface_reg, 667 .clear_reg = r100_clear_surface_reg, 668 }, 669 .hpd = { 670 .init = &rs600_hpd_init, 671 .fini = &rs600_hpd_fini, 672 .sense = &rs600_hpd_sense, 673 .set_polarity = &rs600_hpd_set_polarity, 674 }, 675 .pm = { 676 .misc = &rs600_pm_misc, 677 .prepare = &rs600_pm_prepare, 678 .finish = &rs600_pm_finish, 679 .init_profile = &r420_pm_init_profile, 680 .get_dynpm_state = &r100_pm_get_dynpm_state, 681 .get_engine_clock = &radeon_atom_get_engine_clock, 682 .set_engine_clock = &radeon_atom_set_engine_clock, 683 .get_memory_clock = &radeon_atom_get_memory_clock, 684 .set_memory_clock = &radeon_atom_set_memory_clock, 685 .get_pcie_lanes = NULL, 686 .set_pcie_lanes = NULL, 687 .set_clock_gating = &radeon_atom_set_clock_gating, 688 }, 689 .pflip = { 690 .pre_page_flip = &rs600_pre_page_flip, 691 .page_flip = &rs600_page_flip, 692 .post_page_flip = &rs600_post_page_flip, 693 }, 694 }; 695 696 static struct radeon_asic rs690_asic = { 697 .init = &rs690_init, 698 .fini = &rs690_fini, 699 .suspend = &rs690_suspend, 700 .resume = &rs690_resume, 701 .vga_set_state = &r100_vga_set_state, 702 .asic_reset = &rs600_asic_reset, 703 .ioctl_wait_idle = NULL, 704 .gui_idle = &r100_gui_idle, 705 .mc_wait_for_idle = &rs690_mc_wait_for_idle, 706 .gart = { 707 .tlb_flush = &rs400_gart_tlb_flush, 708 .set_page = &rs400_gart_set_page, 709 }, 710 .ring = { 711 [RADEON_RING_TYPE_GFX_INDEX] = { 712 .ib_execute = &r100_ring_ib_execute, 713 .emit_fence = &r300_fence_ring_emit, 714 .emit_semaphore = &r100_semaphore_ring_emit, 715 .cs_parse = &r300_cs_parse, 716 .ring_start = &r300_ring_start, 717 .ring_test = &r100_ring_test, 718 .ib_test = &r100_ib_test, 719 .is_lockup = &r100_gpu_is_lockup, 720 } 721 }, 722 .irq = { 723 .set = &rs600_irq_set, 724 .process = &rs600_irq_process, 725 }, 726 .display = { 727 .get_vblank_counter = &rs600_get_vblank_counter, 728 .bandwidth_update = &rs690_bandwidth_update, 729 .wait_for_vblank = &avivo_wait_for_vblank, 730 .set_backlight_level = &atombios_set_backlight_level, 731 .get_backlight_level = &atombios_get_backlight_level, 732 }, 733 .copy = { 734 .blit = &r100_copy_blit, 735 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 736 .dma = &r200_copy_dma, 737 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 738 .copy = &r200_copy_dma, 739 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 740 }, 741 .surface = { 742 .set_reg = r100_set_surface_reg, 743 .clear_reg = r100_clear_surface_reg, 744 }, 745 .hpd = { 746 .init = &rs600_hpd_init, 747 .fini = &rs600_hpd_fini, 748 .sense = &rs600_hpd_sense, 749 .set_polarity = &rs600_hpd_set_polarity, 750 }, 751 .pm = { 752 .misc = &rs600_pm_misc, 753 .prepare = &rs600_pm_prepare, 754 .finish = &rs600_pm_finish, 755 .init_profile = &r420_pm_init_profile, 756 .get_dynpm_state = &r100_pm_get_dynpm_state, 757 .get_engine_clock = &radeon_atom_get_engine_clock, 758 .set_engine_clock = &radeon_atom_set_engine_clock, 759 .get_memory_clock = &radeon_atom_get_memory_clock, 760 .set_memory_clock = &radeon_atom_set_memory_clock, 761 .get_pcie_lanes = NULL, 762 .set_pcie_lanes = NULL, 763 .set_clock_gating = &radeon_atom_set_clock_gating, 764 }, 765 .pflip = { 766 .pre_page_flip = &rs600_pre_page_flip, 767 .page_flip = &rs600_page_flip, 768 .post_page_flip = &rs600_post_page_flip, 769 }, 770 }; 771 772 static struct radeon_asic rv515_asic = { 773 .init = &rv515_init, 774 .fini = &rv515_fini, 775 .suspend = &rv515_suspend, 776 .resume = &rv515_resume, 777 .vga_set_state = &r100_vga_set_state, 778 .asic_reset = &rs600_asic_reset, 779 .ioctl_wait_idle = NULL, 780 .gui_idle = &r100_gui_idle, 781 .mc_wait_for_idle = &rv515_mc_wait_for_idle, 782 .gart = { 783 .tlb_flush = &rv370_pcie_gart_tlb_flush, 784 .set_page = &rv370_pcie_gart_set_page, 785 }, 786 .ring = { 787 [RADEON_RING_TYPE_GFX_INDEX] = { 788 .ib_execute = &r100_ring_ib_execute, 789 .emit_fence = &r300_fence_ring_emit, 790 .emit_semaphore = &r100_semaphore_ring_emit, 791 .cs_parse = &r300_cs_parse, 792 .ring_start = &rv515_ring_start, 793 .ring_test = &r100_ring_test, 794 .ib_test = &r100_ib_test, 795 .is_lockup = &r100_gpu_is_lockup, 796 } 797 }, 798 .irq = { 799 .set = &rs600_irq_set, 800 .process = &rs600_irq_process, 801 }, 802 .display = { 803 .get_vblank_counter = &rs600_get_vblank_counter, 804 .bandwidth_update = &rv515_bandwidth_update, 805 .wait_for_vblank = &avivo_wait_for_vblank, 806 .set_backlight_level = &atombios_set_backlight_level, 807 .get_backlight_level = &atombios_get_backlight_level, 808 }, 809 .copy = { 810 .blit = &r100_copy_blit, 811 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 812 .dma = &r200_copy_dma, 813 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 814 .copy = &r100_copy_blit, 815 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 816 }, 817 .surface = { 818 .set_reg = r100_set_surface_reg, 819 .clear_reg = r100_clear_surface_reg, 820 }, 821 .hpd = { 822 .init = &rs600_hpd_init, 823 .fini = &rs600_hpd_fini, 824 .sense = &rs600_hpd_sense, 825 .set_polarity = &rs600_hpd_set_polarity, 826 }, 827 .pm = { 828 .misc = &rs600_pm_misc, 829 .prepare = &rs600_pm_prepare, 830 .finish = &rs600_pm_finish, 831 .init_profile = &r420_pm_init_profile, 832 .get_dynpm_state = &r100_pm_get_dynpm_state, 833 .get_engine_clock = &radeon_atom_get_engine_clock, 834 .set_engine_clock = &radeon_atom_set_engine_clock, 835 .get_memory_clock = &radeon_atom_get_memory_clock, 836 .set_memory_clock = &radeon_atom_set_memory_clock, 837 .get_pcie_lanes = &rv370_get_pcie_lanes, 838 .set_pcie_lanes = &rv370_set_pcie_lanes, 839 .set_clock_gating = &radeon_atom_set_clock_gating, 840 }, 841 .pflip = { 842 .pre_page_flip = &rs600_pre_page_flip, 843 .page_flip = &rs600_page_flip, 844 .post_page_flip = &rs600_post_page_flip, 845 }, 846 }; 847 848 static struct radeon_asic r520_asic = { 849 .init = &r520_init, 850 .fini = &rv515_fini, 851 .suspend = &rv515_suspend, 852 .resume = &r520_resume, 853 .vga_set_state = &r100_vga_set_state, 854 .asic_reset = &rs600_asic_reset, 855 .ioctl_wait_idle = NULL, 856 .gui_idle = &r100_gui_idle, 857 .mc_wait_for_idle = &r520_mc_wait_for_idle, 858 .gart = { 859 .tlb_flush = &rv370_pcie_gart_tlb_flush, 860 .set_page = &rv370_pcie_gart_set_page, 861 }, 862 .ring = { 863 [RADEON_RING_TYPE_GFX_INDEX] = { 864 .ib_execute = &r100_ring_ib_execute, 865 .emit_fence = &r300_fence_ring_emit, 866 .emit_semaphore = &r100_semaphore_ring_emit, 867 .cs_parse = &r300_cs_parse, 868 .ring_start = &rv515_ring_start, 869 .ring_test = &r100_ring_test, 870 .ib_test = &r100_ib_test, 871 .is_lockup = &r100_gpu_is_lockup, 872 } 873 }, 874 .irq = { 875 .set = &rs600_irq_set, 876 .process = &rs600_irq_process, 877 }, 878 .display = { 879 .bandwidth_update = &rv515_bandwidth_update, 880 .get_vblank_counter = &rs600_get_vblank_counter, 881 .wait_for_vblank = &avivo_wait_for_vblank, 882 .set_backlight_level = &atombios_set_backlight_level, 883 .get_backlight_level = &atombios_get_backlight_level, 884 }, 885 .copy = { 886 .blit = &r100_copy_blit, 887 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 888 .dma = &r200_copy_dma, 889 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 890 .copy = &r100_copy_blit, 891 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 892 }, 893 .surface = { 894 .set_reg = r100_set_surface_reg, 895 .clear_reg = r100_clear_surface_reg, 896 }, 897 .hpd = { 898 .init = &rs600_hpd_init, 899 .fini = &rs600_hpd_fini, 900 .sense = &rs600_hpd_sense, 901 .set_polarity = &rs600_hpd_set_polarity, 902 }, 903 .pm = { 904 .misc = &rs600_pm_misc, 905 .prepare = &rs600_pm_prepare, 906 .finish = &rs600_pm_finish, 907 .init_profile = &r420_pm_init_profile, 908 .get_dynpm_state = &r100_pm_get_dynpm_state, 909 .get_engine_clock = &radeon_atom_get_engine_clock, 910 .set_engine_clock = &radeon_atom_set_engine_clock, 911 .get_memory_clock = &radeon_atom_get_memory_clock, 912 .set_memory_clock = &radeon_atom_set_memory_clock, 913 .get_pcie_lanes = &rv370_get_pcie_lanes, 914 .set_pcie_lanes = &rv370_set_pcie_lanes, 915 .set_clock_gating = &radeon_atom_set_clock_gating, 916 }, 917 .pflip = { 918 .pre_page_flip = &rs600_pre_page_flip, 919 .page_flip = &rs600_page_flip, 920 .post_page_flip = &rs600_post_page_flip, 921 }, 922 }; 923 924 static struct radeon_asic r600_asic = { 925 .init = &r600_init, 926 .fini = &r600_fini, 927 .suspend = &r600_suspend, 928 .resume = &r600_resume, 929 .vga_set_state = &r600_vga_set_state, 930 .asic_reset = &r600_asic_reset, 931 .ioctl_wait_idle = r600_ioctl_wait_idle, 932 .gui_idle = &r600_gui_idle, 933 .mc_wait_for_idle = &r600_mc_wait_for_idle, 934 .gart = { 935 .tlb_flush = &r600_pcie_gart_tlb_flush, 936 .set_page = &rs600_gart_set_page, 937 }, 938 .ring = { 939 [RADEON_RING_TYPE_GFX_INDEX] = { 940 .ib_execute = &r600_ring_ib_execute, 941 .emit_fence = &r600_fence_ring_emit, 942 .emit_semaphore = &r600_semaphore_ring_emit, 943 .cs_parse = &r600_cs_parse, 944 .ring_test = &r600_ring_test, 945 .ib_test = &r600_ib_test, 946 .is_lockup = &r600_gpu_is_lockup, 947 }, 948 [R600_RING_TYPE_DMA_INDEX] = { 949 .ib_execute = &r600_dma_ring_ib_execute, 950 .emit_fence = &r600_dma_fence_ring_emit, 951 .emit_semaphore = &r600_dma_semaphore_ring_emit, 952 .cs_parse = &r600_dma_cs_parse, 953 .ring_test = &r600_dma_ring_test, 954 .ib_test = &r600_dma_ib_test, 955 .is_lockup = &r600_dma_is_lockup, 956 } 957 }, 958 .irq = { 959 .set = &r600_irq_set, 960 .process = &r600_irq_process, 961 }, 962 .display = { 963 .bandwidth_update = &rv515_bandwidth_update, 964 .get_vblank_counter = &rs600_get_vblank_counter, 965 .wait_for_vblank = &avivo_wait_for_vblank, 966 .set_backlight_level = &atombios_set_backlight_level, 967 .get_backlight_level = &atombios_get_backlight_level, 968 }, 969 .copy = { 970 .blit = &r600_copy_blit, 971 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 972 .dma = &r600_copy_dma, 973 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 974 .copy = &r600_copy_dma, 975 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 976 }, 977 .surface = { 978 .set_reg = r600_set_surface_reg, 979 .clear_reg = r600_clear_surface_reg, 980 }, 981 .hpd = { 982 .init = &r600_hpd_init, 983 .fini = &r600_hpd_fini, 984 .sense = &r600_hpd_sense, 985 .set_polarity = &r600_hpd_set_polarity, 986 }, 987 .pm = { 988 .misc = &r600_pm_misc, 989 .prepare = &rs600_pm_prepare, 990 .finish = &rs600_pm_finish, 991 .init_profile = &r600_pm_init_profile, 992 .get_dynpm_state = &r600_pm_get_dynpm_state, 993 .get_engine_clock = &radeon_atom_get_engine_clock, 994 .set_engine_clock = &radeon_atom_set_engine_clock, 995 .get_memory_clock = &radeon_atom_get_memory_clock, 996 .set_memory_clock = &radeon_atom_set_memory_clock, 997 .get_pcie_lanes = &r600_get_pcie_lanes, 998 .set_pcie_lanes = &r600_set_pcie_lanes, 999 .set_clock_gating = NULL, 1000 }, 1001 .pflip = { 1002 .pre_page_flip = &rs600_pre_page_flip, 1003 .page_flip = &rs600_page_flip, 1004 .post_page_flip = &rs600_post_page_flip, 1005 }, 1006 }; 1007 1008 static struct radeon_asic rs780_asic = { 1009 .init = &r600_init, 1010 .fini = &r600_fini, 1011 .suspend = &r600_suspend, 1012 .resume = &r600_resume, 1013 .vga_set_state = &r600_vga_set_state, 1014 .asic_reset = &r600_asic_reset, 1015 .ioctl_wait_idle = r600_ioctl_wait_idle, 1016 .gui_idle = &r600_gui_idle, 1017 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1018 .gart = { 1019 .tlb_flush = &r600_pcie_gart_tlb_flush, 1020 .set_page = &rs600_gart_set_page, 1021 }, 1022 .ring = { 1023 [RADEON_RING_TYPE_GFX_INDEX] = { 1024 .ib_execute = &r600_ring_ib_execute, 1025 .emit_fence = &r600_fence_ring_emit, 1026 .emit_semaphore = &r600_semaphore_ring_emit, 1027 .cs_parse = &r600_cs_parse, 1028 .ring_test = &r600_ring_test, 1029 .ib_test = &r600_ib_test, 1030 .is_lockup = &r600_gpu_is_lockup, 1031 }, 1032 [R600_RING_TYPE_DMA_INDEX] = { 1033 .ib_execute = &r600_dma_ring_ib_execute, 1034 .emit_fence = &r600_dma_fence_ring_emit, 1035 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1036 .cs_parse = &r600_dma_cs_parse, 1037 .ring_test = &r600_dma_ring_test, 1038 .ib_test = &r600_dma_ib_test, 1039 .is_lockup = &r600_dma_is_lockup, 1040 } 1041 }, 1042 .irq = { 1043 .set = &r600_irq_set, 1044 .process = &r600_irq_process, 1045 }, 1046 .display = { 1047 .bandwidth_update = &rs690_bandwidth_update, 1048 .get_vblank_counter = &rs600_get_vblank_counter, 1049 .wait_for_vblank = &avivo_wait_for_vblank, 1050 .set_backlight_level = &atombios_set_backlight_level, 1051 .get_backlight_level = &atombios_get_backlight_level, 1052 }, 1053 .copy = { 1054 .blit = &r600_copy_blit, 1055 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1056 .dma = &r600_copy_dma, 1057 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1058 .copy = &r600_copy_dma, 1059 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1060 }, 1061 .surface = { 1062 .set_reg = r600_set_surface_reg, 1063 .clear_reg = r600_clear_surface_reg, 1064 }, 1065 .hpd = { 1066 .init = &r600_hpd_init, 1067 .fini = &r600_hpd_fini, 1068 .sense = &r600_hpd_sense, 1069 .set_polarity = &r600_hpd_set_polarity, 1070 }, 1071 .pm = { 1072 .misc = &r600_pm_misc, 1073 .prepare = &rs600_pm_prepare, 1074 .finish = &rs600_pm_finish, 1075 .init_profile = &rs780_pm_init_profile, 1076 .get_dynpm_state = &r600_pm_get_dynpm_state, 1077 .get_engine_clock = &radeon_atom_get_engine_clock, 1078 .set_engine_clock = &radeon_atom_set_engine_clock, 1079 .get_memory_clock = NULL, 1080 .set_memory_clock = NULL, 1081 .get_pcie_lanes = NULL, 1082 .set_pcie_lanes = NULL, 1083 .set_clock_gating = NULL, 1084 }, 1085 .pflip = { 1086 .pre_page_flip = &rs600_pre_page_flip, 1087 .page_flip = &rs600_page_flip, 1088 .post_page_flip = &rs600_post_page_flip, 1089 }, 1090 }; 1091 1092 static struct radeon_asic rv770_asic = { 1093 .init = &rv770_init, 1094 .fini = &rv770_fini, 1095 .suspend = &rv770_suspend, 1096 .resume = &rv770_resume, 1097 .asic_reset = &r600_asic_reset, 1098 .vga_set_state = &r600_vga_set_state, 1099 .ioctl_wait_idle = r600_ioctl_wait_idle, 1100 .gui_idle = &r600_gui_idle, 1101 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1102 .gart = { 1103 .tlb_flush = &r600_pcie_gart_tlb_flush, 1104 .set_page = &rs600_gart_set_page, 1105 }, 1106 .ring = { 1107 [RADEON_RING_TYPE_GFX_INDEX] = { 1108 .ib_execute = &r600_ring_ib_execute, 1109 .emit_fence = &r600_fence_ring_emit, 1110 .emit_semaphore = &r600_semaphore_ring_emit, 1111 .cs_parse = &r600_cs_parse, 1112 .ring_test = &r600_ring_test, 1113 .ib_test = &r600_ib_test, 1114 .is_lockup = &r600_gpu_is_lockup, 1115 }, 1116 [R600_RING_TYPE_DMA_INDEX] = { 1117 .ib_execute = &r600_dma_ring_ib_execute, 1118 .emit_fence = &r600_dma_fence_ring_emit, 1119 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1120 .cs_parse = &r600_dma_cs_parse, 1121 .ring_test = &r600_dma_ring_test, 1122 .ib_test = &r600_dma_ib_test, 1123 .is_lockup = &r600_dma_is_lockup, 1124 } 1125 }, 1126 .irq = { 1127 .set = &r600_irq_set, 1128 .process = &r600_irq_process, 1129 }, 1130 .display = { 1131 .bandwidth_update = &rv515_bandwidth_update, 1132 .get_vblank_counter = &rs600_get_vblank_counter, 1133 .wait_for_vblank = &avivo_wait_for_vblank, 1134 .set_backlight_level = &atombios_set_backlight_level, 1135 .get_backlight_level = &atombios_get_backlight_level, 1136 }, 1137 .copy = { 1138 .blit = &r600_copy_blit, 1139 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1140 .dma = &rv770_copy_dma, 1141 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1142 .copy = &rv770_copy_dma, 1143 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1144 }, 1145 .surface = { 1146 .set_reg = r600_set_surface_reg, 1147 .clear_reg = r600_clear_surface_reg, 1148 }, 1149 .hpd = { 1150 .init = &r600_hpd_init, 1151 .fini = &r600_hpd_fini, 1152 .sense = &r600_hpd_sense, 1153 .set_polarity = &r600_hpd_set_polarity, 1154 }, 1155 .pm = { 1156 .misc = &rv770_pm_misc, 1157 .prepare = &rs600_pm_prepare, 1158 .finish = &rs600_pm_finish, 1159 .init_profile = &r600_pm_init_profile, 1160 .get_dynpm_state = &r600_pm_get_dynpm_state, 1161 .get_engine_clock = &radeon_atom_get_engine_clock, 1162 .set_engine_clock = &radeon_atom_set_engine_clock, 1163 .get_memory_clock = &radeon_atom_get_memory_clock, 1164 .set_memory_clock = &radeon_atom_set_memory_clock, 1165 .get_pcie_lanes = &r600_get_pcie_lanes, 1166 .set_pcie_lanes = &r600_set_pcie_lanes, 1167 .set_clock_gating = &radeon_atom_set_clock_gating, 1168 }, 1169 .pflip = { 1170 .pre_page_flip = &rs600_pre_page_flip, 1171 .page_flip = &rv770_page_flip, 1172 .post_page_flip = &rs600_post_page_flip, 1173 }, 1174 }; 1175 1176 static struct radeon_asic evergreen_asic = { 1177 .init = &evergreen_init, 1178 .fini = &evergreen_fini, 1179 .suspend = &evergreen_suspend, 1180 .resume = &evergreen_resume, 1181 .asic_reset = &evergreen_asic_reset, 1182 .vga_set_state = &r600_vga_set_state, 1183 .ioctl_wait_idle = r600_ioctl_wait_idle, 1184 .gui_idle = &r600_gui_idle, 1185 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1186 .gart = { 1187 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1188 .set_page = &rs600_gart_set_page, 1189 }, 1190 .ring = { 1191 [RADEON_RING_TYPE_GFX_INDEX] = { 1192 .ib_execute = &evergreen_ring_ib_execute, 1193 .emit_fence = &r600_fence_ring_emit, 1194 .emit_semaphore = &r600_semaphore_ring_emit, 1195 .cs_parse = &evergreen_cs_parse, 1196 .ring_test = &r600_ring_test, 1197 .ib_test = &r600_ib_test, 1198 .is_lockup = &evergreen_gpu_is_lockup, 1199 }, 1200 [R600_RING_TYPE_DMA_INDEX] = { 1201 .ib_execute = &evergreen_dma_ring_ib_execute, 1202 .emit_fence = &evergreen_dma_fence_ring_emit, 1203 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1204 .cs_parse = &evergreen_dma_cs_parse, 1205 .ring_test = &r600_dma_ring_test, 1206 .ib_test = &r600_dma_ib_test, 1207 .is_lockup = &r600_dma_is_lockup, 1208 } 1209 }, 1210 .irq = { 1211 .set = &evergreen_irq_set, 1212 .process = &evergreen_irq_process, 1213 }, 1214 .display = { 1215 .bandwidth_update = &evergreen_bandwidth_update, 1216 .get_vblank_counter = &evergreen_get_vblank_counter, 1217 .wait_for_vblank = &dce4_wait_for_vblank, 1218 .set_backlight_level = &atombios_set_backlight_level, 1219 .get_backlight_level = &atombios_get_backlight_level, 1220 }, 1221 .copy = { 1222 .blit = &r600_copy_blit, 1223 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1224 .dma = &evergreen_copy_dma, 1225 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1226 .copy = &evergreen_copy_dma, 1227 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1228 }, 1229 .surface = { 1230 .set_reg = r600_set_surface_reg, 1231 .clear_reg = r600_clear_surface_reg, 1232 }, 1233 .hpd = { 1234 .init = &evergreen_hpd_init, 1235 .fini = &evergreen_hpd_fini, 1236 .sense = &evergreen_hpd_sense, 1237 .set_polarity = &evergreen_hpd_set_polarity, 1238 }, 1239 .pm = { 1240 .misc = &evergreen_pm_misc, 1241 .prepare = &evergreen_pm_prepare, 1242 .finish = &evergreen_pm_finish, 1243 .init_profile = &r600_pm_init_profile, 1244 .get_dynpm_state = &r600_pm_get_dynpm_state, 1245 .get_engine_clock = &radeon_atom_get_engine_clock, 1246 .set_engine_clock = &radeon_atom_set_engine_clock, 1247 .get_memory_clock = &radeon_atom_get_memory_clock, 1248 .set_memory_clock = &radeon_atom_set_memory_clock, 1249 .get_pcie_lanes = &r600_get_pcie_lanes, 1250 .set_pcie_lanes = &r600_set_pcie_lanes, 1251 .set_clock_gating = NULL, 1252 }, 1253 .pflip = { 1254 .pre_page_flip = &evergreen_pre_page_flip, 1255 .page_flip = &evergreen_page_flip, 1256 .post_page_flip = &evergreen_post_page_flip, 1257 }, 1258 }; 1259 1260 static struct radeon_asic sumo_asic = { 1261 .init = &evergreen_init, 1262 .fini = &evergreen_fini, 1263 .suspend = &evergreen_suspend, 1264 .resume = &evergreen_resume, 1265 .asic_reset = &evergreen_asic_reset, 1266 .vga_set_state = &r600_vga_set_state, 1267 .ioctl_wait_idle = r600_ioctl_wait_idle, 1268 .gui_idle = &r600_gui_idle, 1269 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1270 .gart = { 1271 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1272 .set_page = &rs600_gart_set_page, 1273 }, 1274 .ring = { 1275 [RADEON_RING_TYPE_GFX_INDEX] = { 1276 .ib_execute = &evergreen_ring_ib_execute, 1277 .emit_fence = &r600_fence_ring_emit, 1278 .emit_semaphore = &r600_semaphore_ring_emit, 1279 .cs_parse = &evergreen_cs_parse, 1280 .ring_test = &r600_ring_test, 1281 .ib_test = &r600_ib_test, 1282 .is_lockup = &evergreen_gpu_is_lockup, 1283 }, 1284 [R600_RING_TYPE_DMA_INDEX] = { 1285 .ib_execute = &evergreen_dma_ring_ib_execute, 1286 .emit_fence = &evergreen_dma_fence_ring_emit, 1287 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1288 .cs_parse = &evergreen_dma_cs_parse, 1289 .ring_test = &r600_dma_ring_test, 1290 .ib_test = &r600_dma_ib_test, 1291 .is_lockup = &r600_dma_is_lockup, 1292 } 1293 }, 1294 .irq = { 1295 .set = &evergreen_irq_set, 1296 .process = &evergreen_irq_process, 1297 }, 1298 .display = { 1299 .bandwidth_update = &evergreen_bandwidth_update, 1300 .get_vblank_counter = &evergreen_get_vblank_counter, 1301 .wait_for_vblank = &dce4_wait_for_vblank, 1302 .set_backlight_level = &atombios_set_backlight_level, 1303 .get_backlight_level = &atombios_get_backlight_level, 1304 }, 1305 .copy = { 1306 .blit = &r600_copy_blit, 1307 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1308 .dma = &evergreen_copy_dma, 1309 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1310 .copy = &evergreen_copy_dma, 1311 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1312 }, 1313 .surface = { 1314 .set_reg = r600_set_surface_reg, 1315 .clear_reg = r600_clear_surface_reg, 1316 }, 1317 .hpd = { 1318 .init = &evergreen_hpd_init, 1319 .fini = &evergreen_hpd_fini, 1320 .sense = &evergreen_hpd_sense, 1321 .set_polarity = &evergreen_hpd_set_polarity, 1322 }, 1323 .pm = { 1324 .misc = &evergreen_pm_misc, 1325 .prepare = &evergreen_pm_prepare, 1326 .finish = &evergreen_pm_finish, 1327 .init_profile = &sumo_pm_init_profile, 1328 .get_dynpm_state = &r600_pm_get_dynpm_state, 1329 .get_engine_clock = &radeon_atom_get_engine_clock, 1330 .set_engine_clock = &radeon_atom_set_engine_clock, 1331 .get_memory_clock = NULL, 1332 .set_memory_clock = NULL, 1333 .get_pcie_lanes = NULL, 1334 .set_pcie_lanes = NULL, 1335 .set_clock_gating = NULL, 1336 }, 1337 .pflip = { 1338 .pre_page_flip = &evergreen_pre_page_flip, 1339 .page_flip = &evergreen_page_flip, 1340 .post_page_flip = &evergreen_post_page_flip, 1341 }, 1342 }; 1343 1344 static struct radeon_asic btc_asic = { 1345 .init = &evergreen_init, 1346 .fini = &evergreen_fini, 1347 .suspend = &evergreen_suspend, 1348 .resume = &evergreen_resume, 1349 .asic_reset = &evergreen_asic_reset, 1350 .vga_set_state = &r600_vga_set_state, 1351 .ioctl_wait_idle = r600_ioctl_wait_idle, 1352 .gui_idle = &r600_gui_idle, 1353 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1354 .gart = { 1355 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1356 .set_page = &rs600_gart_set_page, 1357 }, 1358 .ring = { 1359 [RADEON_RING_TYPE_GFX_INDEX] = { 1360 .ib_execute = &evergreen_ring_ib_execute, 1361 .emit_fence = &r600_fence_ring_emit, 1362 .emit_semaphore = &r600_semaphore_ring_emit, 1363 .cs_parse = &evergreen_cs_parse, 1364 .ring_test = &r600_ring_test, 1365 .ib_test = &r600_ib_test, 1366 .is_lockup = &evergreen_gpu_is_lockup, 1367 }, 1368 [R600_RING_TYPE_DMA_INDEX] = { 1369 .ib_execute = &evergreen_dma_ring_ib_execute, 1370 .emit_fence = &evergreen_dma_fence_ring_emit, 1371 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1372 .cs_parse = &evergreen_dma_cs_parse, 1373 .ring_test = &r600_dma_ring_test, 1374 .ib_test = &r600_dma_ib_test, 1375 .is_lockup = &r600_dma_is_lockup, 1376 } 1377 }, 1378 .irq = { 1379 .set = &evergreen_irq_set, 1380 .process = &evergreen_irq_process, 1381 }, 1382 .display = { 1383 .bandwidth_update = &evergreen_bandwidth_update, 1384 .get_vblank_counter = &evergreen_get_vblank_counter, 1385 .wait_for_vblank = &dce4_wait_for_vblank, 1386 .set_backlight_level = &atombios_set_backlight_level, 1387 .get_backlight_level = &atombios_get_backlight_level, 1388 }, 1389 .copy = { 1390 .blit = &r600_copy_blit, 1391 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1392 .dma = &evergreen_copy_dma, 1393 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1394 .copy = &evergreen_copy_dma, 1395 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1396 }, 1397 .surface = { 1398 .set_reg = r600_set_surface_reg, 1399 .clear_reg = r600_clear_surface_reg, 1400 }, 1401 .hpd = { 1402 .init = &evergreen_hpd_init, 1403 .fini = &evergreen_hpd_fini, 1404 .sense = &evergreen_hpd_sense, 1405 .set_polarity = &evergreen_hpd_set_polarity, 1406 }, 1407 .pm = { 1408 .misc = &evergreen_pm_misc, 1409 .prepare = &evergreen_pm_prepare, 1410 .finish = &evergreen_pm_finish, 1411 .init_profile = &btc_pm_init_profile, 1412 .get_dynpm_state = &r600_pm_get_dynpm_state, 1413 .get_engine_clock = &radeon_atom_get_engine_clock, 1414 .set_engine_clock = &radeon_atom_set_engine_clock, 1415 .get_memory_clock = &radeon_atom_get_memory_clock, 1416 .set_memory_clock = &radeon_atom_set_memory_clock, 1417 .get_pcie_lanes = NULL, 1418 .set_pcie_lanes = NULL, 1419 .set_clock_gating = NULL, 1420 }, 1421 .pflip = { 1422 .pre_page_flip = &evergreen_pre_page_flip, 1423 .page_flip = &evergreen_page_flip, 1424 .post_page_flip = &evergreen_post_page_flip, 1425 }, 1426 }; 1427 1428 static struct radeon_asic cayman_asic = { 1429 .init = &cayman_init, 1430 .fini = &cayman_fini, 1431 .suspend = &cayman_suspend, 1432 .resume = &cayman_resume, 1433 .asic_reset = &cayman_asic_reset, 1434 .vga_set_state = &r600_vga_set_state, 1435 .ioctl_wait_idle = r600_ioctl_wait_idle, 1436 .gui_idle = &r600_gui_idle, 1437 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1438 .gart = { 1439 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1440 .set_page = &rs600_gart_set_page, 1441 }, 1442 .vm = { 1443 .init = &cayman_vm_init, 1444 .fini = &cayman_vm_fini, 1445 .pt_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1446 .set_page = &cayman_vm_set_page, 1447 }, 1448 .ring = { 1449 [RADEON_RING_TYPE_GFX_INDEX] = { 1450 .ib_execute = &cayman_ring_ib_execute, 1451 .ib_parse = &evergreen_ib_parse, 1452 .emit_fence = &cayman_fence_ring_emit, 1453 .emit_semaphore = &r600_semaphore_ring_emit, 1454 .cs_parse = &evergreen_cs_parse, 1455 .ring_test = &r600_ring_test, 1456 .ib_test = &r600_ib_test, 1457 .is_lockup = &evergreen_gpu_is_lockup, 1458 .vm_flush = &cayman_vm_flush, 1459 }, 1460 [CAYMAN_RING_TYPE_CP1_INDEX] = { 1461 .ib_execute = &cayman_ring_ib_execute, 1462 .ib_parse = &evergreen_ib_parse, 1463 .emit_fence = &cayman_fence_ring_emit, 1464 .emit_semaphore = &r600_semaphore_ring_emit, 1465 .cs_parse = &evergreen_cs_parse, 1466 .ring_test = &r600_ring_test, 1467 .ib_test = &r600_ib_test, 1468 .is_lockup = &evergreen_gpu_is_lockup, 1469 .vm_flush = &cayman_vm_flush, 1470 }, 1471 [CAYMAN_RING_TYPE_CP2_INDEX] = { 1472 .ib_execute = &cayman_ring_ib_execute, 1473 .ib_parse = &evergreen_ib_parse, 1474 .emit_fence = &cayman_fence_ring_emit, 1475 .emit_semaphore = &r600_semaphore_ring_emit, 1476 .cs_parse = &evergreen_cs_parse, 1477 .ring_test = &r600_ring_test, 1478 .ib_test = &r600_ib_test, 1479 .is_lockup = &evergreen_gpu_is_lockup, 1480 .vm_flush = &cayman_vm_flush, 1481 }, 1482 [R600_RING_TYPE_DMA_INDEX] = { 1483 .ib_execute = &cayman_dma_ring_ib_execute, 1484 .ib_parse = &evergreen_dma_ib_parse, 1485 .emit_fence = &evergreen_dma_fence_ring_emit, 1486 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1487 .cs_parse = &evergreen_dma_cs_parse, 1488 .ring_test = &r600_dma_ring_test, 1489 .ib_test = &r600_dma_ib_test, 1490 .is_lockup = &cayman_dma_is_lockup, 1491 .vm_flush = &cayman_dma_vm_flush, 1492 }, 1493 [CAYMAN_RING_TYPE_DMA1_INDEX] = { 1494 .ib_execute = &cayman_dma_ring_ib_execute, 1495 .ib_parse = &evergreen_dma_ib_parse, 1496 .emit_fence = &evergreen_dma_fence_ring_emit, 1497 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1498 .cs_parse = &evergreen_dma_cs_parse, 1499 .ring_test = &r600_dma_ring_test, 1500 .ib_test = &r600_dma_ib_test, 1501 .is_lockup = &cayman_dma_is_lockup, 1502 .vm_flush = &cayman_dma_vm_flush, 1503 } 1504 }, 1505 .irq = { 1506 .set = &evergreen_irq_set, 1507 .process = &evergreen_irq_process, 1508 }, 1509 .display = { 1510 .bandwidth_update = &evergreen_bandwidth_update, 1511 .get_vblank_counter = &evergreen_get_vblank_counter, 1512 .wait_for_vblank = &dce4_wait_for_vblank, 1513 .set_backlight_level = &atombios_set_backlight_level, 1514 .get_backlight_level = &atombios_get_backlight_level, 1515 }, 1516 .copy = { 1517 .blit = &r600_copy_blit, 1518 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1519 .dma = &evergreen_copy_dma, 1520 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1521 .copy = &evergreen_copy_dma, 1522 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1523 }, 1524 .surface = { 1525 .set_reg = r600_set_surface_reg, 1526 .clear_reg = r600_clear_surface_reg, 1527 }, 1528 .hpd = { 1529 .init = &evergreen_hpd_init, 1530 .fini = &evergreen_hpd_fini, 1531 .sense = &evergreen_hpd_sense, 1532 .set_polarity = &evergreen_hpd_set_polarity, 1533 }, 1534 .pm = { 1535 .misc = &evergreen_pm_misc, 1536 .prepare = &evergreen_pm_prepare, 1537 .finish = &evergreen_pm_finish, 1538 .init_profile = &btc_pm_init_profile, 1539 .get_dynpm_state = &r600_pm_get_dynpm_state, 1540 .get_engine_clock = &radeon_atom_get_engine_clock, 1541 .set_engine_clock = &radeon_atom_set_engine_clock, 1542 .get_memory_clock = &radeon_atom_get_memory_clock, 1543 .set_memory_clock = &radeon_atom_set_memory_clock, 1544 .get_pcie_lanes = NULL, 1545 .set_pcie_lanes = NULL, 1546 .set_clock_gating = NULL, 1547 }, 1548 .pflip = { 1549 .pre_page_flip = &evergreen_pre_page_flip, 1550 .page_flip = &evergreen_page_flip, 1551 .post_page_flip = &evergreen_post_page_flip, 1552 }, 1553 }; 1554 1555 static struct radeon_asic trinity_asic = { 1556 .init = &cayman_init, 1557 .fini = &cayman_fini, 1558 .suspend = &cayman_suspend, 1559 .resume = &cayman_resume, 1560 .asic_reset = &cayman_asic_reset, 1561 .vga_set_state = &r600_vga_set_state, 1562 .ioctl_wait_idle = r600_ioctl_wait_idle, 1563 .gui_idle = &r600_gui_idle, 1564 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1565 .gart = { 1566 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1567 .set_page = &rs600_gart_set_page, 1568 }, 1569 .vm = { 1570 .init = &cayman_vm_init, 1571 .fini = &cayman_vm_fini, 1572 .pt_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1573 .set_page = &cayman_vm_set_page, 1574 }, 1575 .ring = { 1576 [RADEON_RING_TYPE_GFX_INDEX] = { 1577 .ib_execute = &cayman_ring_ib_execute, 1578 .ib_parse = &evergreen_ib_parse, 1579 .emit_fence = &cayman_fence_ring_emit, 1580 .emit_semaphore = &r600_semaphore_ring_emit, 1581 .cs_parse = &evergreen_cs_parse, 1582 .ring_test = &r600_ring_test, 1583 .ib_test = &r600_ib_test, 1584 .is_lockup = &evergreen_gpu_is_lockup, 1585 .vm_flush = &cayman_vm_flush, 1586 }, 1587 [CAYMAN_RING_TYPE_CP1_INDEX] = { 1588 .ib_execute = &cayman_ring_ib_execute, 1589 .ib_parse = &evergreen_ib_parse, 1590 .emit_fence = &cayman_fence_ring_emit, 1591 .emit_semaphore = &r600_semaphore_ring_emit, 1592 .cs_parse = &evergreen_cs_parse, 1593 .ring_test = &r600_ring_test, 1594 .ib_test = &r600_ib_test, 1595 .is_lockup = &evergreen_gpu_is_lockup, 1596 .vm_flush = &cayman_vm_flush, 1597 }, 1598 [CAYMAN_RING_TYPE_CP2_INDEX] = { 1599 .ib_execute = &cayman_ring_ib_execute, 1600 .ib_parse = &evergreen_ib_parse, 1601 .emit_fence = &cayman_fence_ring_emit, 1602 .emit_semaphore = &r600_semaphore_ring_emit, 1603 .cs_parse = &evergreen_cs_parse, 1604 .ring_test = &r600_ring_test, 1605 .ib_test = &r600_ib_test, 1606 .is_lockup = &evergreen_gpu_is_lockup, 1607 .vm_flush = &cayman_vm_flush, 1608 }, 1609 [R600_RING_TYPE_DMA_INDEX] = { 1610 .ib_execute = &cayman_dma_ring_ib_execute, 1611 .ib_parse = &evergreen_dma_ib_parse, 1612 .emit_fence = &evergreen_dma_fence_ring_emit, 1613 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1614 .cs_parse = &evergreen_dma_cs_parse, 1615 .ring_test = &r600_dma_ring_test, 1616 .ib_test = &r600_dma_ib_test, 1617 .is_lockup = &cayman_dma_is_lockup, 1618 .vm_flush = &cayman_dma_vm_flush, 1619 }, 1620 [CAYMAN_RING_TYPE_DMA1_INDEX] = { 1621 .ib_execute = &cayman_dma_ring_ib_execute, 1622 .ib_parse = &evergreen_dma_ib_parse, 1623 .emit_fence = &evergreen_dma_fence_ring_emit, 1624 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1625 .cs_parse = &evergreen_dma_cs_parse, 1626 .ring_test = &r600_dma_ring_test, 1627 .ib_test = &r600_dma_ib_test, 1628 .is_lockup = &cayman_dma_is_lockup, 1629 .vm_flush = &cayman_dma_vm_flush, 1630 } 1631 }, 1632 .irq = { 1633 .set = &evergreen_irq_set, 1634 .process = &evergreen_irq_process, 1635 }, 1636 .display = { 1637 .bandwidth_update = &dce6_bandwidth_update, 1638 .get_vblank_counter = &evergreen_get_vblank_counter, 1639 .wait_for_vblank = &dce4_wait_for_vblank, 1640 .set_backlight_level = &atombios_set_backlight_level, 1641 .get_backlight_level = &atombios_get_backlight_level, 1642 }, 1643 .copy = { 1644 .blit = &r600_copy_blit, 1645 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1646 .dma = &evergreen_copy_dma, 1647 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1648 .copy = &evergreen_copy_dma, 1649 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1650 }, 1651 .surface = { 1652 .set_reg = r600_set_surface_reg, 1653 .clear_reg = r600_clear_surface_reg, 1654 }, 1655 .hpd = { 1656 .init = &evergreen_hpd_init, 1657 .fini = &evergreen_hpd_fini, 1658 .sense = &evergreen_hpd_sense, 1659 .set_polarity = &evergreen_hpd_set_polarity, 1660 }, 1661 .pm = { 1662 .misc = &evergreen_pm_misc, 1663 .prepare = &evergreen_pm_prepare, 1664 .finish = &evergreen_pm_finish, 1665 .init_profile = &sumo_pm_init_profile, 1666 .get_dynpm_state = &r600_pm_get_dynpm_state, 1667 .get_engine_clock = &radeon_atom_get_engine_clock, 1668 .set_engine_clock = &radeon_atom_set_engine_clock, 1669 .get_memory_clock = NULL, 1670 .set_memory_clock = NULL, 1671 .get_pcie_lanes = NULL, 1672 .set_pcie_lanes = NULL, 1673 .set_clock_gating = NULL, 1674 }, 1675 .pflip = { 1676 .pre_page_flip = &evergreen_pre_page_flip, 1677 .page_flip = &evergreen_page_flip, 1678 .post_page_flip = &evergreen_post_page_flip, 1679 }, 1680 }; 1681 1682 static struct radeon_asic si_asic = { 1683 .init = &si_init, 1684 .fini = &si_fini, 1685 .suspend = &si_suspend, 1686 .resume = &si_resume, 1687 .asic_reset = &si_asic_reset, 1688 .vga_set_state = &r600_vga_set_state, 1689 .ioctl_wait_idle = r600_ioctl_wait_idle, 1690 .gui_idle = &r600_gui_idle, 1691 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1692 .gart = { 1693 .tlb_flush = &si_pcie_gart_tlb_flush, 1694 .set_page = &rs600_gart_set_page, 1695 }, 1696 .vm = { 1697 .init = &si_vm_init, 1698 .fini = &si_vm_fini, 1699 .pt_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1700 .set_page = &si_vm_set_page, 1701 }, 1702 .ring = { 1703 [RADEON_RING_TYPE_GFX_INDEX] = { 1704 .ib_execute = &si_ring_ib_execute, 1705 .ib_parse = &si_ib_parse, 1706 .emit_fence = &si_fence_ring_emit, 1707 .emit_semaphore = &r600_semaphore_ring_emit, 1708 .cs_parse = NULL, 1709 .ring_test = &r600_ring_test, 1710 .ib_test = &r600_ib_test, 1711 .is_lockup = &si_gpu_is_lockup, 1712 .vm_flush = &si_vm_flush, 1713 }, 1714 [CAYMAN_RING_TYPE_CP1_INDEX] = { 1715 .ib_execute = &si_ring_ib_execute, 1716 .ib_parse = &si_ib_parse, 1717 .emit_fence = &si_fence_ring_emit, 1718 .emit_semaphore = &r600_semaphore_ring_emit, 1719 .cs_parse = NULL, 1720 .ring_test = &r600_ring_test, 1721 .ib_test = &r600_ib_test, 1722 .is_lockup = &si_gpu_is_lockup, 1723 .vm_flush = &si_vm_flush, 1724 }, 1725 [CAYMAN_RING_TYPE_CP2_INDEX] = { 1726 .ib_execute = &si_ring_ib_execute, 1727 .ib_parse = &si_ib_parse, 1728 .emit_fence = &si_fence_ring_emit, 1729 .emit_semaphore = &r600_semaphore_ring_emit, 1730 .cs_parse = NULL, 1731 .ring_test = &r600_ring_test, 1732 .ib_test = &r600_ib_test, 1733 .is_lockup = &si_gpu_is_lockup, 1734 .vm_flush = &si_vm_flush, 1735 }, 1736 [R600_RING_TYPE_DMA_INDEX] = { 1737 .ib_execute = &cayman_dma_ring_ib_execute, 1738 .ib_parse = &evergreen_dma_ib_parse, 1739 .emit_fence = &evergreen_dma_fence_ring_emit, 1740 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1741 .cs_parse = NULL, 1742 .ring_test = &r600_dma_ring_test, 1743 .ib_test = &r600_dma_ib_test, 1744 .is_lockup = &cayman_dma_is_lockup, 1745 .vm_flush = &si_dma_vm_flush, 1746 }, 1747 [CAYMAN_RING_TYPE_DMA1_INDEX] = { 1748 .ib_execute = &cayman_dma_ring_ib_execute, 1749 .ib_parse = &evergreen_dma_ib_parse, 1750 .emit_fence = &evergreen_dma_fence_ring_emit, 1751 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1752 .cs_parse = NULL, 1753 .ring_test = &r600_dma_ring_test, 1754 .ib_test = &r600_dma_ib_test, 1755 .is_lockup = &cayman_dma_is_lockup, 1756 .vm_flush = &si_dma_vm_flush, 1757 } 1758 }, 1759 .irq = { 1760 .set = &si_irq_set, 1761 .process = &si_irq_process, 1762 }, 1763 .display = { 1764 .bandwidth_update = &dce6_bandwidth_update, 1765 .get_vblank_counter = &evergreen_get_vblank_counter, 1766 .wait_for_vblank = &dce4_wait_for_vblank, 1767 .set_backlight_level = &atombios_set_backlight_level, 1768 .get_backlight_level = &atombios_get_backlight_level, 1769 }, 1770 .copy = { 1771 .blit = NULL, 1772 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1773 .dma = &si_copy_dma, 1774 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1775 .copy = &si_copy_dma, 1776 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1777 }, 1778 .surface = { 1779 .set_reg = r600_set_surface_reg, 1780 .clear_reg = r600_clear_surface_reg, 1781 }, 1782 .hpd = { 1783 .init = &evergreen_hpd_init, 1784 .fini = &evergreen_hpd_fini, 1785 .sense = &evergreen_hpd_sense, 1786 .set_polarity = &evergreen_hpd_set_polarity, 1787 }, 1788 .pm = { 1789 .misc = &evergreen_pm_misc, 1790 .prepare = &evergreen_pm_prepare, 1791 .finish = &evergreen_pm_finish, 1792 .init_profile = &sumo_pm_init_profile, 1793 .get_dynpm_state = &r600_pm_get_dynpm_state, 1794 .get_engine_clock = &radeon_atom_get_engine_clock, 1795 .set_engine_clock = &radeon_atom_set_engine_clock, 1796 .get_memory_clock = &radeon_atom_get_memory_clock, 1797 .set_memory_clock = &radeon_atom_set_memory_clock, 1798 .get_pcie_lanes = NULL, 1799 .set_pcie_lanes = NULL, 1800 .set_clock_gating = NULL, 1801 }, 1802 .pflip = { 1803 .pre_page_flip = &evergreen_pre_page_flip, 1804 .page_flip = &evergreen_page_flip, 1805 .post_page_flip = &evergreen_post_page_flip, 1806 }, 1807 }; 1808 1809 /** 1810 * radeon_asic_init - register asic specific callbacks 1811 * 1812 * @rdev: radeon device pointer 1813 * 1814 * Registers the appropriate asic specific callbacks for each 1815 * chip family. Also sets other asics specific info like the number 1816 * of crtcs and the register aperture accessors (all asics). 1817 * Returns 0 for success. 1818 */ 1819 int radeon_asic_init(struct radeon_device *rdev) 1820 { 1821 radeon_register_accessor_init(rdev); 1822 1823 /* set the number of crtcs */ 1824 if (rdev->flags & RADEON_SINGLE_CRTC) 1825 rdev->num_crtc = 1; 1826 else 1827 rdev->num_crtc = 2; 1828 1829 switch (rdev->family) { 1830 case CHIP_R100: 1831 case CHIP_RV100: 1832 case CHIP_RS100: 1833 case CHIP_RV200: 1834 case CHIP_RS200: 1835 rdev->asic = &r100_asic; 1836 break; 1837 case CHIP_R200: 1838 case CHIP_RV250: 1839 case CHIP_RS300: 1840 case CHIP_RV280: 1841 rdev->asic = &r200_asic; 1842 break; 1843 case CHIP_R300: 1844 case CHIP_R350: 1845 case CHIP_RV350: 1846 case CHIP_RV380: 1847 if (rdev->flags & RADEON_IS_PCIE) 1848 rdev->asic = &r300_asic_pcie; 1849 else 1850 rdev->asic = &r300_asic; 1851 break; 1852 case CHIP_R420: 1853 case CHIP_R423: 1854 case CHIP_RV410: 1855 rdev->asic = &r420_asic; 1856 /* handle macs */ 1857 if (rdev->bios == NULL) { 1858 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock; 1859 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock; 1860 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock; 1861 rdev->asic->pm.set_memory_clock = NULL; 1862 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level; 1863 } 1864 break; 1865 case CHIP_RS400: 1866 case CHIP_RS480: 1867 rdev->asic = &rs400_asic; 1868 break; 1869 case CHIP_RS600: 1870 rdev->asic = &rs600_asic; 1871 break; 1872 case CHIP_RS690: 1873 case CHIP_RS740: 1874 rdev->asic = &rs690_asic; 1875 break; 1876 case CHIP_RV515: 1877 rdev->asic = &rv515_asic; 1878 break; 1879 case CHIP_R520: 1880 case CHIP_RV530: 1881 case CHIP_RV560: 1882 case CHIP_RV570: 1883 case CHIP_R580: 1884 rdev->asic = &r520_asic; 1885 break; 1886 case CHIP_R600: 1887 case CHIP_RV610: 1888 case CHIP_RV630: 1889 case CHIP_RV620: 1890 case CHIP_RV635: 1891 case CHIP_RV670: 1892 rdev->asic = &r600_asic; 1893 break; 1894 case CHIP_RS780: 1895 case CHIP_RS880: 1896 rdev->asic = &rs780_asic; 1897 break; 1898 case CHIP_RV770: 1899 case CHIP_RV730: 1900 case CHIP_RV710: 1901 case CHIP_RV740: 1902 rdev->asic = &rv770_asic; 1903 break; 1904 case CHIP_CEDAR: 1905 case CHIP_REDWOOD: 1906 case CHIP_JUNIPER: 1907 case CHIP_CYPRESS: 1908 case CHIP_HEMLOCK: 1909 /* set num crtcs */ 1910 if (rdev->family == CHIP_CEDAR) 1911 rdev->num_crtc = 4; 1912 else 1913 rdev->num_crtc = 6; 1914 rdev->asic = &evergreen_asic; 1915 break; 1916 case CHIP_PALM: 1917 case CHIP_SUMO: 1918 case CHIP_SUMO2: 1919 rdev->asic = &sumo_asic; 1920 break; 1921 case CHIP_BARTS: 1922 case CHIP_TURKS: 1923 case CHIP_CAICOS: 1924 /* set num crtcs */ 1925 if (rdev->family == CHIP_CAICOS) 1926 rdev->num_crtc = 4; 1927 else 1928 rdev->num_crtc = 6; 1929 rdev->asic = &btc_asic; 1930 break; 1931 case CHIP_CAYMAN: 1932 rdev->asic = &cayman_asic; 1933 /* set num crtcs */ 1934 rdev->num_crtc = 6; 1935 break; 1936 case CHIP_ARUBA: 1937 rdev->asic = &trinity_asic; 1938 /* set num crtcs */ 1939 rdev->num_crtc = 4; 1940 break; 1941 case CHIP_TAHITI: 1942 case CHIP_PITCAIRN: 1943 case CHIP_VERDE: 1944 rdev->asic = &si_asic; 1945 /* set num crtcs */ 1946 rdev->num_crtc = 6; 1947 break; 1948 default: 1949 /* FIXME: not supported yet */ 1950 return -EINVAL; 1951 } 1952 1953 if (rdev->flags & RADEON_IS_IGP) { 1954 rdev->asic->pm.get_memory_clock = NULL; 1955 rdev->asic->pm.set_memory_clock = NULL; 1956 } 1957 1958 return 0; 1959 } 1960 1961