1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <drm/drmP.h> 30 #include <drm/drm_crtc_helper.h> 31 #include <uapi_drm/radeon_drm.h> 32 #include "radeon_reg.h" 33 #include "radeon.h" 34 #include "radeon_asic.h" 35 #include "atom.h" 36 #include "rv770_dpm.h" 37 #include "ni_dpm.h" 38 39 /* 40 * Registers accessors functions. 41 */ 42 /** 43 * radeon_invalid_rreg - dummy reg read function 44 * 45 * @rdev: radeon device pointer 46 * @reg: offset of register 47 * 48 * Dummy register read function. Used for register blocks 49 * that certain asics don't have (all asics). 50 * Returns the value in the register. 51 */ 52 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) 53 { 54 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); 55 BUG_ON(1); 56 return 0; 57 } 58 59 /** 60 * radeon_invalid_wreg - dummy reg write function 61 * 62 * @rdev: radeon device pointer 63 * @reg: offset of register 64 * @v: value to write to the register 65 * 66 * Dummy register read function. Used for register blocks 67 * that certain asics don't have (all asics). 68 */ 69 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 70 { 71 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", 72 reg, v); 73 BUG_ON(1); 74 } 75 76 /** 77 * radeon_register_accessor_init - sets up the register accessor callbacks 78 * 79 * @rdev: radeon device pointer 80 * 81 * Sets up the register accessor callbacks for various register 82 * apertures. Not all asics have all apertures (all asics). 83 */ 84 static void radeon_register_accessor_init(struct radeon_device *rdev) 85 { 86 rdev->mc_rreg = &radeon_invalid_rreg; 87 rdev->mc_wreg = &radeon_invalid_wreg; 88 rdev->pll_rreg = &radeon_invalid_rreg; 89 rdev->pll_wreg = &radeon_invalid_wreg; 90 rdev->pciep_rreg = &radeon_invalid_rreg; 91 rdev->pciep_wreg = &radeon_invalid_wreg; 92 93 /* Don't change order as we are overridding accessor. */ 94 if (rdev->family < CHIP_RV515) { 95 rdev->pcie_reg_mask = 0xff; 96 } else { 97 rdev->pcie_reg_mask = 0x7ff; 98 } 99 /* FIXME: not sure here */ 100 if (rdev->family <= CHIP_R580) { 101 rdev->pll_rreg = &r100_pll_rreg; 102 rdev->pll_wreg = &r100_pll_wreg; 103 } 104 if (rdev->family >= CHIP_R420) { 105 rdev->mc_rreg = &r420_mc_rreg; 106 rdev->mc_wreg = &r420_mc_wreg; 107 } 108 if (rdev->family >= CHIP_RV515) { 109 rdev->mc_rreg = &rv515_mc_rreg; 110 rdev->mc_wreg = &rv515_mc_wreg; 111 } 112 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { 113 rdev->mc_rreg = &rs400_mc_rreg; 114 rdev->mc_wreg = &rs400_mc_wreg; 115 } 116 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 117 rdev->mc_rreg = &rs690_mc_rreg; 118 rdev->mc_wreg = &rs690_mc_wreg; 119 } 120 if (rdev->family == CHIP_RS600) { 121 rdev->mc_rreg = &rs600_mc_rreg; 122 rdev->mc_wreg = &rs600_mc_wreg; 123 } 124 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { 125 rdev->mc_rreg = &rs780_mc_rreg; 126 rdev->mc_wreg = &rs780_mc_wreg; 127 } 128 129 if (rdev->family >= CHIP_BONAIRE) { 130 rdev->pciep_rreg = &cik_pciep_rreg; 131 rdev->pciep_wreg = &cik_pciep_wreg; 132 } else if (rdev->family >= CHIP_R600) { 133 rdev->pciep_rreg = &r600_pciep_rreg; 134 rdev->pciep_wreg = &r600_pciep_wreg; 135 } 136 } 137 138 139 /* helper to disable agp */ 140 /** 141 * radeon_agp_disable - AGP disable helper function 142 * 143 * @rdev: radeon device pointer 144 * 145 * Removes AGP flags and changes the gart callbacks on AGP 146 * cards when using the internal gart rather than AGP (all asics). 147 */ 148 void radeon_agp_disable(struct radeon_device *rdev) 149 { 150 rdev->flags &= ~RADEON_IS_AGP; 151 if (rdev->family >= CHIP_R600) { 152 DRM_INFO("Forcing AGP to PCIE mode\n"); 153 rdev->flags |= RADEON_IS_PCIE; 154 } else if (rdev->family >= CHIP_RV515 || 155 rdev->family == CHIP_RV380 || 156 rdev->family == CHIP_RV410 || 157 rdev->family == CHIP_R423) { 158 DRM_INFO("Forcing AGP to PCIE mode\n"); 159 rdev->flags |= RADEON_IS_PCIE; 160 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; 161 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; 162 } else { 163 DRM_INFO("Forcing AGP to PCI mode\n"); 164 rdev->flags |= RADEON_IS_PCI; 165 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; 166 rdev->asic->gart.set_page = &r100_pci_gart_set_page; 167 } 168 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 169 } 170 171 /* 172 * ASIC 173 */ 174 static struct radeon_asic r100_asic = { 175 .init = &r100_init, 176 .fini = &r100_fini, 177 .suspend = &r100_suspend, 178 .resume = &r100_resume, 179 .vga_set_state = &r100_vga_set_state, 180 .asic_reset = &r100_asic_reset, 181 .ioctl_wait_idle = NULL, 182 .gui_idle = &r100_gui_idle, 183 .mc_wait_for_idle = &r100_mc_wait_for_idle, 184 .gart = { 185 .tlb_flush = &r100_pci_gart_tlb_flush, 186 .set_page = &r100_pci_gart_set_page, 187 }, 188 .ring = { 189 [RADEON_RING_TYPE_GFX_INDEX] = { 190 .ib_execute = &r100_ring_ib_execute, 191 .emit_fence = &r100_fence_ring_emit, 192 .emit_semaphore = &r100_semaphore_ring_emit, 193 .cs_parse = &r100_cs_parse, 194 .ring_start = &r100_ring_start, 195 .ring_test = &r100_ring_test, 196 .ib_test = &r100_ib_test, 197 .is_lockup = &r100_gpu_is_lockup, 198 .get_rptr = &radeon_ring_generic_get_rptr, 199 .get_wptr = &radeon_ring_generic_get_wptr, 200 .set_wptr = &radeon_ring_generic_set_wptr, 201 } 202 }, 203 .irq = { 204 .set = &r100_irq_set, 205 .process = &r100_irq_process, 206 }, 207 .display = { 208 .bandwidth_update = &r100_bandwidth_update, 209 .get_vblank_counter = &r100_get_vblank_counter, 210 .wait_for_vblank = &r100_wait_for_vblank, 211 .set_backlight_level = &radeon_legacy_set_backlight_level, 212 .get_backlight_level = &radeon_legacy_get_backlight_level, 213 }, 214 .copy = { 215 .blit = &r100_copy_blit, 216 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 217 .dma = NULL, 218 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 219 .copy = &r100_copy_blit, 220 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 221 }, 222 .surface = { 223 .set_reg = r100_set_surface_reg, 224 .clear_reg = r100_clear_surface_reg, 225 }, 226 .hpd = { 227 .init = &r100_hpd_init, 228 .fini = &r100_hpd_fini, 229 .sense = &r100_hpd_sense, 230 .set_polarity = &r100_hpd_set_polarity, 231 }, 232 .pm = { 233 .misc = &r100_pm_misc, 234 .prepare = &r100_pm_prepare, 235 .finish = &r100_pm_finish, 236 .init_profile = &r100_pm_init_profile, 237 .get_dynpm_state = &r100_pm_get_dynpm_state, 238 .get_engine_clock = &radeon_legacy_get_engine_clock, 239 .set_engine_clock = &radeon_legacy_set_engine_clock, 240 .get_memory_clock = &radeon_legacy_get_memory_clock, 241 .set_memory_clock = NULL, 242 .get_pcie_lanes = NULL, 243 .set_pcie_lanes = NULL, 244 .set_clock_gating = &radeon_legacy_set_clock_gating, 245 }, 246 .pflip = { 247 .pre_page_flip = &r100_pre_page_flip, 248 .page_flip = &r100_page_flip, 249 .post_page_flip = &r100_post_page_flip, 250 }, 251 }; 252 253 static struct radeon_asic r200_asic = { 254 .init = &r100_init, 255 .fini = &r100_fini, 256 .suspend = &r100_suspend, 257 .resume = &r100_resume, 258 .vga_set_state = &r100_vga_set_state, 259 .asic_reset = &r100_asic_reset, 260 .ioctl_wait_idle = NULL, 261 .gui_idle = &r100_gui_idle, 262 .mc_wait_for_idle = &r100_mc_wait_for_idle, 263 .gart = { 264 .tlb_flush = &r100_pci_gart_tlb_flush, 265 .set_page = &r100_pci_gart_set_page, 266 }, 267 .ring = { 268 [RADEON_RING_TYPE_GFX_INDEX] = { 269 .ib_execute = &r100_ring_ib_execute, 270 .emit_fence = &r100_fence_ring_emit, 271 .emit_semaphore = &r100_semaphore_ring_emit, 272 .cs_parse = &r100_cs_parse, 273 .ring_start = &r100_ring_start, 274 .ring_test = &r100_ring_test, 275 .ib_test = &r100_ib_test, 276 .is_lockup = &r100_gpu_is_lockup, 277 .get_rptr = &radeon_ring_generic_get_rptr, 278 .get_wptr = &radeon_ring_generic_get_wptr, 279 .set_wptr = &radeon_ring_generic_set_wptr, 280 } 281 }, 282 .irq = { 283 .set = &r100_irq_set, 284 .process = &r100_irq_process, 285 }, 286 .display = { 287 .bandwidth_update = &r100_bandwidth_update, 288 .get_vblank_counter = &r100_get_vblank_counter, 289 .wait_for_vblank = &r100_wait_for_vblank, 290 .set_backlight_level = &radeon_legacy_set_backlight_level, 291 .get_backlight_level = &radeon_legacy_get_backlight_level, 292 }, 293 .copy = { 294 .blit = &r100_copy_blit, 295 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 296 .dma = &r200_copy_dma, 297 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 298 .copy = &r100_copy_blit, 299 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 300 }, 301 .surface = { 302 .set_reg = r100_set_surface_reg, 303 .clear_reg = r100_clear_surface_reg, 304 }, 305 .hpd = { 306 .init = &r100_hpd_init, 307 .fini = &r100_hpd_fini, 308 .sense = &r100_hpd_sense, 309 .set_polarity = &r100_hpd_set_polarity, 310 }, 311 .pm = { 312 .misc = &r100_pm_misc, 313 .prepare = &r100_pm_prepare, 314 .finish = &r100_pm_finish, 315 .init_profile = &r100_pm_init_profile, 316 .get_dynpm_state = &r100_pm_get_dynpm_state, 317 .get_engine_clock = &radeon_legacy_get_engine_clock, 318 .set_engine_clock = &radeon_legacy_set_engine_clock, 319 .get_memory_clock = &radeon_legacy_get_memory_clock, 320 .set_memory_clock = NULL, 321 .get_pcie_lanes = NULL, 322 .set_pcie_lanes = NULL, 323 .set_clock_gating = &radeon_legacy_set_clock_gating, 324 }, 325 .pflip = { 326 .pre_page_flip = &r100_pre_page_flip, 327 .page_flip = &r100_page_flip, 328 .post_page_flip = &r100_post_page_flip, 329 }, 330 }; 331 332 static struct radeon_asic r300_asic = { 333 .init = &r300_init, 334 .fini = &r300_fini, 335 .suspend = &r300_suspend, 336 .resume = &r300_resume, 337 .vga_set_state = &r100_vga_set_state, 338 .asic_reset = &r300_asic_reset, 339 .ioctl_wait_idle = NULL, 340 .gui_idle = &r100_gui_idle, 341 .mc_wait_for_idle = &r300_mc_wait_for_idle, 342 .gart = { 343 .tlb_flush = &r100_pci_gart_tlb_flush, 344 .set_page = &r100_pci_gart_set_page, 345 }, 346 .ring = { 347 [RADEON_RING_TYPE_GFX_INDEX] = { 348 .ib_execute = &r100_ring_ib_execute, 349 .emit_fence = &r300_fence_ring_emit, 350 .emit_semaphore = &r100_semaphore_ring_emit, 351 .cs_parse = &r300_cs_parse, 352 .ring_start = &r300_ring_start, 353 .ring_test = &r100_ring_test, 354 .ib_test = &r100_ib_test, 355 .is_lockup = &r100_gpu_is_lockup, 356 .get_rptr = &radeon_ring_generic_get_rptr, 357 .get_wptr = &radeon_ring_generic_get_wptr, 358 .set_wptr = &radeon_ring_generic_set_wptr, 359 } 360 }, 361 .irq = { 362 .set = &r100_irq_set, 363 .process = &r100_irq_process, 364 }, 365 .display = { 366 .bandwidth_update = &r100_bandwidth_update, 367 .get_vblank_counter = &r100_get_vblank_counter, 368 .wait_for_vblank = &r100_wait_for_vblank, 369 .set_backlight_level = &radeon_legacy_set_backlight_level, 370 .get_backlight_level = &radeon_legacy_get_backlight_level, 371 }, 372 .copy = { 373 .blit = &r100_copy_blit, 374 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 375 .dma = &r200_copy_dma, 376 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 377 .copy = &r100_copy_blit, 378 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 379 }, 380 .surface = { 381 .set_reg = r100_set_surface_reg, 382 .clear_reg = r100_clear_surface_reg, 383 }, 384 .hpd = { 385 .init = &r100_hpd_init, 386 .fini = &r100_hpd_fini, 387 .sense = &r100_hpd_sense, 388 .set_polarity = &r100_hpd_set_polarity, 389 }, 390 .pm = { 391 .misc = &r100_pm_misc, 392 .prepare = &r100_pm_prepare, 393 .finish = &r100_pm_finish, 394 .init_profile = &r100_pm_init_profile, 395 .get_dynpm_state = &r100_pm_get_dynpm_state, 396 .get_engine_clock = &radeon_legacy_get_engine_clock, 397 .set_engine_clock = &radeon_legacy_set_engine_clock, 398 .get_memory_clock = &radeon_legacy_get_memory_clock, 399 .set_memory_clock = NULL, 400 .get_pcie_lanes = &rv370_get_pcie_lanes, 401 .set_pcie_lanes = &rv370_set_pcie_lanes, 402 .set_clock_gating = &radeon_legacy_set_clock_gating, 403 }, 404 .pflip = { 405 .pre_page_flip = &r100_pre_page_flip, 406 .page_flip = &r100_page_flip, 407 .post_page_flip = &r100_post_page_flip, 408 }, 409 }; 410 411 static struct radeon_asic r300_asic_pcie = { 412 .init = &r300_init, 413 .fini = &r300_fini, 414 .suspend = &r300_suspend, 415 .resume = &r300_resume, 416 .vga_set_state = &r100_vga_set_state, 417 .asic_reset = &r300_asic_reset, 418 .ioctl_wait_idle = NULL, 419 .gui_idle = &r100_gui_idle, 420 .mc_wait_for_idle = &r300_mc_wait_for_idle, 421 .gart = { 422 .tlb_flush = &rv370_pcie_gart_tlb_flush, 423 .set_page = &rv370_pcie_gart_set_page, 424 }, 425 .ring = { 426 [RADEON_RING_TYPE_GFX_INDEX] = { 427 .ib_execute = &r100_ring_ib_execute, 428 .emit_fence = &r300_fence_ring_emit, 429 .emit_semaphore = &r100_semaphore_ring_emit, 430 .cs_parse = &r300_cs_parse, 431 .ring_start = &r300_ring_start, 432 .ring_test = &r100_ring_test, 433 .ib_test = &r100_ib_test, 434 .is_lockup = &r100_gpu_is_lockup, 435 .get_rptr = &radeon_ring_generic_get_rptr, 436 .get_wptr = &radeon_ring_generic_get_wptr, 437 .set_wptr = &radeon_ring_generic_set_wptr, 438 } 439 }, 440 .irq = { 441 .set = &r100_irq_set, 442 .process = &r100_irq_process, 443 }, 444 .display = { 445 .bandwidth_update = &r100_bandwidth_update, 446 .get_vblank_counter = &r100_get_vblank_counter, 447 .wait_for_vblank = &r100_wait_for_vblank, 448 .set_backlight_level = &radeon_legacy_set_backlight_level, 449 .get_backlight_level = &radeon_legacy_get_backlight_level, 450 }, 451 .copy = { 452 .blit = &r100_copy_blit, 453 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 454 .dma = &r200_copy_dma, 455 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 456 .copy = &r100_copy_blit, 457 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 458 }, 459 .surface = { 460 .set_reg = r100_set_surface_reg, 461 .clear_reg = r100_clear_surface_reg, 462 }, 463 .hpd = { 464 .init = &r100_hpd_init, 465 .fini = &r100_hpd_fini, 466 .sense = &r100_hpd_sense, 467 .set_polarity = &r100_hpd_set_polarity, 468 }, 469 .pm = { 470 .misc = &r100_pm_misc, 471 .prepare = &r100_pm_prepare, 472 .finish = &r100_pm_finish, 473 .init_profile = &r100_pm_init_profile, 474 .get_dynpm_state = &r100_pm_get_dynpm_state, 475 .get_engine_clock = &radeon_legacy_get_engine_clock, 476 .set_engine_clock = &radeon_legacy_set_engine_clock, 477 .get_memory_clock = &radeon_legacy_get_memory_clock, 478 .set_memory_clock = NULL, 479 .get_pcie_lanes = &rv370_get_pcie_lanes, 480 .set_pcie_lanes = &rv370_set_pcie_lanes, 481 .set_clock_gating = &radeon_legacy_set_clock_gating, 482 }, 483 .pflip = { 484 .pre_page_flip = &r100_pre_page_flip, 485 .page_flip = &r100_page_flip, 486 .post_page_flip = &r100_post_page_flip, 487 }, 488 }; 489 490 static struct radeon_asic r420_asic = { 491 .init = &r420_init, 492 .fini = &r420_fini, 493 .suspend = &r420_suspend, 494 .resume = &r420_resume, 495 .vga_set_state = &r100_vga_set_state, 496 .asic_reset = &r300_asic_reset, 497 .ioctl_wait_idle = NULL, 498 .gui_idle = &r100_gui_idle, 499 .mc_wait_for_idle = &r300_mc_wait_for_idle, 500 .gart = { 501 .tlb_flush = &rv370_pcie_gart_tlb_flush, 502 .set_page = &rv370_pcie_gart_set_page, 503 }, 504 .ring = { 505 [RADEON_RING_TYPE_GFX_INDEX] = { 506 .ib_execute = &r100_ring_ib_execute, 507 .emit_fence = &r300_fence_ring_emit, 508 .emit_semaphore = &r100_semaphore_ring_emit, 509 .cs_parse = &r300_cs_parse, 510 .ring_start = &r300_ring_start, 511 .ring_test = &r100_ring_test, 512 .ib_test = &r100_ib_test, 513 .is_lockup = &r100_gpu_is_lockup, 514 .get_rptr = &radeon_ring_generic_get_rptr, 515 .get_wptr = &radeon_ring_generic_get_wptr, 516 .set_wptr = &radeon_ring_generic_set_wptr, 517 } 518 }, 519 .irq = { 520 .set = &r100_irq_set, 521 .process = &r100_irq_process, 522 }, 523 .display = { 524 .bandwidth_update = &r100_bandwidth_update, 525 .get_vblank_counter = &r100_get_vblank_counter, 526 .wait_for_vblank = &r100_wait_for_vblank, 527 .set_backlight_level = &atombios_set_backlight_level, 528 .get_backlight_level = &atombios_get_backlight_level, 529 }, 530 .copy = { 531 .blit = &r100_copy_blit, 532 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 533 .dma = &r200_copy_dma, 534 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 535 .copy = &r100_copy_blit, 536 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 537 }, 538 .surface = { 539 .set_reg = r100_set_surface_reg, 540 .clear_reg = r100_clear_surface_reg, 541 }, 542 .hpd = { 543 .init = &r100_hpd_init, 544 .fini = &r100_hpd_fini, 545 .sense = &r100_hpd_sense, 546 .set_polarity = &r100_hpd_set_polarity, 547 }, 548 .pm = { 549 .misc = &r100_pm_misc, 550 .prepare = &r100_pm_prepare, 551 .finish = &r100_pm_finish, 552 .init_profile = &r420_pm_init_profile, 553 .get_dynpm_state = &r100_pm_get_dynpm_state, 554 .get_engine_clock = &radeon_atom_get_engine_clock, 555 .set_engine_clock = &radeon_atom_set_engine_clock, 556 .get_memory_clock = &radeon_atom_get_memory_clock, 557 .set_memory_clock = &radeon_atom_set_memory_clock, 558 .get_pcie_lanes = &rv370_get_pcie_lanes, 559 .set_pcie_lanes = &rv370_set_pcie_lanes, 560 .set_clock_gating = &radeon_atom_set_clock_gating, 561 }, 562 .pflip = { 563 .pre_page_flip = &r100_pre_page_flip, 564 .page_flip = &r100_page_flip, 565 .post_page_flip = &r100_post_page_flip, 566 }, 567 }; 568 569 static struct radeon_asic rs400_asic = { 570 .init = &rs400_init, 571 .fini = &rs400_fini, 572 .suspend = &rs400_suspend, 573 .resume = &rs400_resume, 574 .vga_set_state = &r100_vga_set_state, 575 .asic_reset = &r300_asic_reset, 576 .ioctl_wait_idle = NULL, 577 .gui_idle = &r100_gui_idle, 578 .mc_wait_for_idle = &rs400_mc_wait_for_idle, 579 .gart = { 580 .tlb_flush = &rs400_gart_tlb_flush, 581 .set_page = &rs400_gart_set_page, 582 }, 583 .ring = { 584 [RADEON_RING_TYPE_GFX_INDEX] = { 585 .ib_execute = &r100_ring_ib_execute, 586 .emit_fence = &r300_fence_ring_emit, 587 .emit_semaphore = &r100_semaphore_ring_emit, 588 .cs_parse = &r300_cs_parse, 589 .ring_start = &r300_ring_start, 590 .ring_test = &r100_ring_test, 591 .ib_test = &r100_ib_test, 592 .is_lockup = &r100_gpu_is_lockup, 593 .get_rptr = &radeon_ring_generic_get_rptr, 594 .get_wptr = &radeon_ring_generic_get_wptr, 595 .set_wptr = &radeon_ring_generic_set_wptr, 596 } 597 }, 598 .irq = { 599 .set = &r100_irq_set, 600 .process = &r100_irq_process, 601 }, 602 .display = { 603 .bandwidth_update = &r100_bandwidth_update, 604 .get_vblank_counter = &r100_get_vblank_counter, 605 .wait_for_vblank = &r100_wait_for_vblank, 606 .set_backlight_level = &radeon_legacy_set_backlight_level, 607 .get_backlight_level = &radeon_legacy_get_backlight_level, 608 }, 609 .copy = { 610 .blit = &r100_copy_blit, 611 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 612 .dma = &r200_copy_dma, 613 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 614 .copy = &r100_copy_blit, 615 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 616 }, 617 .surface = { 618 .set_reg = r100_set_surface_reg, 619 .clear_reg = r100_clear_surface_reg, 620 }, 621 .hpd = { 622 .init = &r100_hpd_init, 623 .fini = &r100_hpd_fini, 624 .sense = &r100_hpd_sense, 625 .set_polarity = &r100_hpd_set_polarity, 626 }, 627 .pm = { 628 .misc = &r100_pm_misc, 629 .prepare = &r100_pm_prepare, 630 .finish = &r100_pm_finish, 631 .init_profile = &r100_pm_init_profile, 632 .get_dynpm_state = &r100_pm_get_dynpm_state, 633 .get_engine_clock = &radeon_legacy_get_engine_clock, 634 .set_engine_clock = &radeon_legacy_set_engine_clock, 635 .get_memory_clock = &radeon_legacy_get_memory_clock, 636 .set_memory_clock = NULL, 637 .get_pcie_lanes = NULL, 638 .set_pcie_lanes = NULL, 639 .set_clock_gating = &radeon_legacy_set_clock_gating, 640 }, 641 .pflip = { 642 .pre_page_flip = &r100_pre_page_flip, 643 .page_flip = &r100_page_flip, 644 .post_page_flip = &r100_post_page_flip, 645 }, 646 }; 647 648 static struct radeon_asic rs600_asic = { 649 .init = &rs600_init, 650 .fini = &rs600_fini, 651 .suspend = &rs600_suspend, 652 .resume = &rs600_resume, 653 .vga_set_state = &r100_vga_set_state, 654 .asic_reset = &rs600_asic_reset, 655 .ioctl_wait_idle = NULL, 656 .gui_idle = &r100_gui_idle, 657 .mc_wait_for_idle = &rs600_mc_wait_for_idle, 658 .gart = { 659 .tlb_flush = &rs600_gart_tlb_flush, 660 .set_page = &rs600_gart_set_page, 661 }, 662 .ring = { 663 [RADEON_RING_TYPE_GFX_INDEX] = { 664 .ib_execute = &r100_ring_ib_execute, 665 .emit_fence = &r300_fence_ring_emit, 666 .emit_semaphore = &r100_semaphore_ring_emit, 667 .cs_parse = &r300_cs_parse, 668 .ring_start = &r300_ring_start, 669 .ring_test = &r100_ring_test, 670 .ib_test = &r100_ib_test, 671 .is_lockup = &r100_gpu_is_lockup, 672 .get_rptr = &radeon_ring_generic_get_rptr, 673 .get_wptr = &radeon_ring_generic_get_wptr, 674 .set_wptr = &radeon_ring_generic_set_wptr, 675 } 676 }, 677 .irq = { 678 .set = &rs600_irq_set, 679 .process = &rs600_irq_process, 680 }, 681 .display = { 682 .bandwidth_update = &rs600_bandwidth_update, 683 .get_vblank_counter = &rs600_get_vblank_counter, 684 .wait_for_vblank = &avivo_wait_for_vblank, 685 .set_backlight_level = &atombios_set_backlight_level, 686 .get_backlight_level = &atombios_get_backlight_level, 687 .hdmi_enable = &r600_hdmi_enable, 688 .hdmi_setmode = &r600_hdmi_setmode, 689 }, 690 .copy = { 691 .blit = &r100_copy_blit, 692 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 693 .dma = &r200_copy_dma, 694 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 695 .copy = &r100_copy_blit, 696 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 697 }, 698 .surface = { 699 .set_reg = r100_set_surface_reg, 700 .clear_reg = r100_clear_surface_reg, 701 }, 702 .hpd = { 703 .init = &rs600_hpd_init, 704 .fini = &rs600_hpd_fini, 705 .sense = &rs600_hpd_sense, 706 .set_polarity = &rs600_hpd_set_polarity, 707 }, 708 .pm = { 709 .misc = &rs600_pm_misc, 710 .prepare = &rs600_pm_prepare, 711 .finish = &rs600_pm_finish, 712 .init_profile = &r420_pm_init_profile, 713 .get_dynpm_state = &r100_pm_get_dynpm_state, 714 .get_engine_clock = &radeon_atom_get_engine_clock, 715 .set_engine_clock = &radeon_atom_set_engine_clock, 716 .get_memory_clock = &radeon_atom_get_memory_clock, 717 .set_memory_clock = &radeon_atom_set_memory_clock, 718 .get_pcie_lanes = NULL, 719 .set_pcie_lanes = NULL, 720 .set_clock_gating = &radeon_atom_set_clock_gating, 721 }, 722 .pflip = { 723 .pre_page_flip = &rs600_pre_page_flip, 724 .page_flip = &rs600_page_flip, 725 .post_page_flip = &rs600_post_page_flip, 726 }, 727 }; 728 729 static struct radeon_asic rs690_asic = { 730 .init = &rs690_init, 731 .fini = &rs690_fini, 732 .suspend = &rs690_suspend, 733 .resume = &rs690_resume, 734 .vga_set_state = &r100_vga_set_state, 735 .asic_reset = &rs600_asic_reset, 736 .ioctl_wait_idle = NULL, 737 .gui_idle = &r100_gui_idle, 738 .mc_wait_for_idle = &rs690_mc_wait_for_idle, 739 .gart = { 740 .tlb_flush = &rs400_gart_tlb_flush, 741 .set_page = &rs400_gart_set_page, 742 }, 743 .ring = { 744 [RADEON_RING_TYPE_GFX_INDEX] = { 745 .ib_execute = &r100_ring_ib_execute, 746 .emit_fence = &r300_fence_ring_emit, 747 .emit_semaphore = &r100_semaphore_ring_emit, 748 .cs_parse = &r300_cs_parse, 749 .ring_start = &r300_ring_start, 750 .ring_test = &r100_ring_test, 751 .ib_test = &r100_ib_test, 752 .is_lockup = &r100_gpu_is_lockup, 753 .get_rptr = &radeon_ring_generic_get_rptr, 754 .get_wptr = &radeon_ring_generic_get_wptr, 755 .set_wptr = &radeon_ring_generic_set_wptr, 756 } 757 }, 758 .irq = { 759 .set = &rs600_irq_set, 760 .process = &rs600_irq_process, 761 }, 762 .display = { 763 .get_vblank_counter = &rs600_get_vblank_counter, 764 .bandwidth_update = &rs690_bandwidth_update, 765 .wait_for_vblank = &avivo_wait_for_vblank, 766 .set_backlight_level = &atombios_set_backlight_level, 767 .get_backlight_level = &atombios_get_backlight_level, 768 .hdmi_enable = &r600_hdmi_enable, 769 .hdmi_setmode = &r600_hdmi_setmode, 770 }, 771 .copy = { 772 .blit = &r100_copy_blit, 773 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 774 .dma = &r200_copy_dma, 775 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 776 .copy = &r200_copy_dma, 777 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 778 }, 779 .surface = { 780 .set_reg = r100_set_surface_reg, 781 .clear_reg = r100_clear_surface_reg, 782 }, 783 .hpd = { 784 .init = &rs600_hpd_init, 785 .fini = &rs600_hpd_fini, 786 .sense = &rs600_hpd_sense, 787 .set_polarity = &rs600_hpd_set_polarity, 788 }, 789 .pm = { 790 .misc = &rs600_pm_misc, 791 .prepare = &rs600_pm_prepare, 792 .finish = &rs600_pm_finish, 793 .init_profile = &r420_pm_init_profile, 794 .get_dynpm_state = &r100_pm_get_dynpm_state, 795 .get_engine_clock = &radeon_atom_get_engine_clock, 796 .set_engine_clock = &radeon_atom_set_engine_clock, 797 .get_memory_clock = &radeon_atom_get_memory_clock, 798 .set_memory_clock = &radeon_atom_set_memory_clock, 799 .get_pcie_lanes = NULL, 800 .set_pcie_lanes = NULL, 801 .set_clock_gating = &radeon_atom_set_clock_gating, 802 }, 803 .pflip = { 804 .pre_page_flip = &rs600_pre_page_flip, 805 .page_flip = &rs600_page_flip, 806 .post_page_flip = &rs600_post_page_flip, 807 }, 808 }; 809 810 static struct radeon_asic rv515_asic = { 811 .init = &rv515_init, 812 .fini = &rv515_fini, 813 .suspend = &rv515_suspend, 814 .resume = &rv515_resume, 815 .vga_set_state = &r100_vga_set_state, 816 .asic_reset = &rs600_asic_reset, 817 .ioctl_wait_idle = NULL, 818 .gui_idle = &r100_gui_idle, 819 .mc_wait_for_idle = &rv515_mc_wait_for_idle, 820 .gart = { 821 .tlb_flush = &rv370_pcie_gart_tlb_flush, 822 .set_page = &rv370_pcie_gart_set_page, 823 }, 824 .ring = { 825 [RADEON_RING_TYPE_GFX_INDEX] = { 826 .ib_execute = &r100_ring_ib_execute, 827 .emit_fence = &r300_fence_ring_emit, 828 .emit_semaphore = &r100_semaphore_ring_emit, 829 .cs_parse = &r300_cs_parse, 830 .ring_start = &rv515_ring_start, 831 .ring_test = &r100_ring_test, 832 .ib_test = &r100_ib_test, 833 .is_lockup = &r100_gpu_is_lockup, 834 .get_rptr = &radeon_ring_generic_get_rptr, 835 .get_wptr = &radeon_ring_generic_get_wptr, 836 .set_wptr = &radeon_ring_generic_set_wptr, 837 } 838 }, 839 .irq = { 840 .set = &rs600_irq_set, 841 .process = &rs600_irq_process, 842 }, 843 .display = { 844 .get_vblank_counter = &rs600_get_vblank_counter, 845 .bandwidth_update = &rv515_bandwidth_update, 846 .wait_for_vblank = &avivo_wait_for_vblank, 847 .set_backlight_level = &atombios_set_backlight_level, 848 .get_backlight_level = &atombios_get_backlight_level, 849 }, 850 .copy = { 851 .blit = &r100_copy_blit, 852 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 853 .dma = &r200_copy_dma, 854 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 855 .copy = &r100_copy_blit, 856 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 857 }, 858 .surface = { 859 .set_reg = r100_set_surface_reg, 860 .clear_reg = r100_clear_surface_reg, 861 }, 862 .hpd = { 863 .init = &rs600_hpd_init, 864 .fini = &rs600_hpd_fini, 865 .sense = &rs600_hpd_sense, 866 .set_polarity = &rs600_hpd_set_polarity, 867 }, 868 .pm = { 869 .misc = &rs600_pm_misc, 870 .prepare = &rs600_pm_prepare, 871 .finish = &rs600_pm_finish, 872 .init_profile = &r420_pm_init_profile, 873 .get_dynpm_state = &r100_pm_get_dynpm_state, 874 .get_engine_clock = &radeon_atom_get_engine_clock, 875 .set_engine_clock = &radeon_atom_set_engine_clock, 876 .get_memory_clock = &radeon_atom_get_memory_clock, 877 .set_memory_clock = &radeon_atom_set_memory_clock, 878 .get_pcie_lanes = &rv370_get_pcie_lanes, 879 .set_pcie_lanes = &rv370_set_pcie_lanes, 880 .set_clock_gating = &radeon_atom_set_clock_gating, 881 }, 882 .pflip = { 883 .pre_page_flip = &rs600_pre_page_flip, 884 .page_flip = &rs600_page_flip, 885 .post_page_flip = &rs600_post_page_flip, 886 }, 887 }; 888 889 static struct radeon_asic r520_asic = { 890 .init = &r520_init, 891 .fini = &rv515_fini, 892 .suspend = &rv515_suspend, 893 .resume = &r520_resume, 894 .vga_set_state = &r100_vga_set_state, 895 .asic_reset = &rs600_asic_reset, 896 .ioctl_wait_idle = NULL, 897 .gui_idle = &r100_gui_idle, 898 .mc_wait_for_idle = &r520_mc_wait_for_idle, 899 .gart = { 900 .tlb_flush = &rv370_pcie_gart_tlb_flush, 901 .set_page = &rv370_pcie_gart_set_page, 902 }, 903 .ring = { 904 [RADEON_RING_TYPE_GFX_INDEX] = { 905 .ib_execute = &r100_ring_ib_execute, 906 .emit_fence = &r300_fence_ring_emit, 907 .emit_semaphore = &r100_semaphore_ring_emit, 908 .cs_parse = &r300_cs_parse, 909 .ring_start = &rv515_ring_start, 910 .ring_test = &r100_ring_test, 911 .ib_test = &r100_ib_test, 912 .is_lockup = &r100_gpu_is_lockup, 913 .get_rptr = &radeon_ring_generic_get_rptr, 914 .get_wptr = &radeon_ring_generic_get_wptr, 915 .set_wptr = &radeon_ring_generic_set_wptr, 916 } 917 }, 918 .irq = { 919 .set = &rs600_irq_set, 920 .process = &rs600_irq_process, 921 }, 922 .display = { 923 .bandwidth_update = &rv515_bandwidth_update, 924 .get_vblank_counter = &rs600_get_vblank_counter, 925 .wait_for_vblank = &avivo_wait_for_vblank, 926 .set_backlight_level = &atombios_set_backlight_level, 927 .get_backlight_level = &atombios_get_backlight_level, 928 }, 929 .copy = { 930 .blit = &r100_copy_blit, 931 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 932 .dma = &r200_copy_dma, 933 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 934 .copy = &r100_copy_blit, 935 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 936 }, 937 .surface = { 938 .set_reg = r100_set_surface_reg, 939 .clear_reg = r100_clear_surface_reg, 940 }, 941 .hpd = { 942 .init = &rs600_hpd_init, 943 .fini = &rs600_hpd_fini, 944 .sense = &rs600_hpd_sense, 945 .set_polarity = &rs600_hpd_set_polarity, 946 }, 947 .pm = { 948 .misc = &rs600_pm_misc, 949 .prepare = &rs600_pm_prepare, 950 .finish = &rs600_pm_finish, 951 .init_profile = &r420_pm_init_profile, 952 .get_dynpm_state = &r100_pm_get_dynpm_state, 953 .get_engine_clock = &radeon_atom_get_engine_clock, 954 .set_engine_clock = &radeon_atom_set_engine_clock, 955 .get_memory_clock = &radeon_atom_get_memory_clock, 956 .set_memory_clock = &radeon_atom_set_memory_clock, 957 .get_pcie_lanes = &rv370_get_pcie_lanes, 958 .set_pcie_lanes = &rv370_set_pcie_lanes, 959 .set_clock_gating = &radeon_atom_set_clock_gating, 960 }, 961 .pflip = { 962 .pre_page_flip = &rs600_pre_page_flip, 963 .page_flip = &rs600_page_flip, 964 .post_page_flip = &rs600_post_page_flip, 965 }, 966 }; 967 968 static struct radeon_asic r600_asic = { 969 .init = &r600_init, 970 .fini = &r600_fini, 971 .suspend = &r600_suspend, 972 .resume = &r600_resume, 973 .vga_set_state = &r600_vga_set_state, 974 .asic_reset = &r600_asic_reset, 975 .ioctl_wait_idle = r600_ioctl_wait_idle, 976 .gui_idle = &r600_gui_idle, 977 .mc_wait_for_idle = &r600_mc_wait_for_idle, 978 .get_xclk = &r600_get_xclk, 979 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 980 .gart = { 981 .tlb_flush = &r600_pcie_gart_tlb_flush, 982 .set_page = &rs600_gart_set_page, 983 }, 984 .ring = { 985 [RADEON_RING_TYPE_GFX_INDEX] = { 986 .ib_execute = &r600_ring_ib_execute, 987 .emit_fence = &r600_fence_ring_emit, 988 .emit_semaphore = &r600_semaphore_ring_emit, 989 .cs_parse = &r600_cs_parse, 990 .ring_test = &r600_ring_test, 991 .ib_test = &r600_ib_test, 992 .is_lockup = &r600_gfx_is_lockup, 993 .get_rptr = &radeon_ring_generic_get_rptr, 994 .get_wptr = &radeon_ring_generic_get_wptr, 995 .set_wptr = &radeon_ring_generic_set_wptr, 996 }, 997 [R600_RING_TYPE_DMA_INDEX] = { 998 .ib_execute = &r600_dma_ring_ib_execute, 999 .emit_fence = &r600_dma_fence_ring_emit, 1000 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1001 .cs_parse = &r600_dma_cs_parse, 1002 .ring_test = &r600_dma_ring_test, 1003 .ib_test = &r600_dma_ib_test, 1004 .is_lockup = &r600_dma_is_lockup, 1005 .get_rptr = &radeon_ring_generic_get_rptr, 1006 .get_wptr = &radeon_ring_generic_get_wptr, 1007 .set_wptr = &radeon_ring_generic_set_wptr, 1008 } 1009 }, 1010 .irq = { 1011 .set = &r600_irq_set, 1012 .process = &r600_irq_process, 1013 }, 1014 .display = { 1015 .bandwidth_update = &rv515_bandwidth_update, 1016 .get_vblank_counter = &rs600_get_vblank_counter, 1017 .wait_for_vblank = &avivo_wait_for_vblank, 1018 .set_backlight_level = &atombios_set_backlight_level, 1019 .get_backlight_level = &atombios_get_backlight_level, 1020 .hdmi_enable = &r600_hdmi_enable, 1021 .hdmi_setmode = &r600_hdmi_setmode, 1022 }, 1023 .copy = { 1024 .blit = &r600_copy_blit, 1025 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1026 .dma = &r600_copy_dma, 1027 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1028 .copy = &r600_copy_cpdma, 1029 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1030 }, 1031 .surface = { 1032 .set_reg = r600_set_surface_reg, 1033 .clear_reg = r600_clear_surface_reg, 1034 }, 1035 .hpd = { 1036 .init = &r600_hpd_init, 1037 .fini = &r600_hpd_fini, 1038 .sense = &r600_hpd_sense, 1039 .set_polarity = &r600_hpd_set_polarity, 1040 }, 1041 .pm = { 1042 .misc = &r600_pm_misc, 1043 .prepare = &rs600_pm_prepare, 1044 .finish = &rs600_pm_finish, 1045 .init_profile = &r600_pm_init_profile, 1046 .get_dynpm_state = &r600_pm_get_dynpm_state, 1047 .get_engine_clock = &radeon_atom_get_engine_clock, 1048 .set_engine_clock = &radeon_atom_set_engine_clock, 1049 .get_memory_clock = &radeon_atom_get_memory_clock, 1050 .set_memory_clock = &radeon_atom_set_memory_clock, 1051 .get_pcie_lanes = &r600_get_pcie_lanes, 1052 .set_pcie_lanes = &r600_set_pcie_lanes, 1053 .set_clock_gating = NULL, 1054 .get_temperature = &rv6xx_get_temp, 1055 }, 1056 .pflip = { 1057 .pre_page_flip = &rs600_pre_page_flip, 1058 .page_flip = &rs600_page_flip, 1059 .post_page_flip = &rs600_post_page_flip, 1060 }, 1061 }; 1062 1063 static struct radeon_asic rv6xx_asic = { 1064 .init = &r600_init, 1065 .fini = &r600_fini, 1066 .suspend = &r600_suspend, 1067 .resume = &r600_resume, 1068 .vga_set_state = &r600_vga_set_state, 1069 .asic_reset = &r600_asic_reset, 1070 .ioctl_wait_idle = r600_ioctl_wait_idle, 1071 .gui_idle = &r600_gui_idle, 1072 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1073 .get_xclk = &r600_get_xclk, 1074 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1075 .gart = { 1076 .tlb_flush = &r600_pcie_gart_tlb_flush, 1077 .set_page = &rs600_gart_set_page, 1078 }, 1079 .ring = { 1080 [RADEON_RING_TYPE_GFX_INDEX] = { 1081 .ib_execute = &r600_ring_ib_execute, 1082 .emit_fence = &r600_fence_ring_emit, 1083 .emit_semaphore = &r600_semaphore_ring_emit, 1084 .cs_parse = &r600_cs_parse, 1085 .ring_test = &r600_ring_test, 1086 .ib_test = &r600_ib_test, 1087 .is_lockup = &r600_gfx_is_lockup, 1088 .get_rptr = &radeon_ring_generic_get_rptr, 1089 .get_wptr = &radeon_ring_generic_get_wptr, 1090 .set_wptr = &radeon_ring_generic_set_wptr, 1091 }, 1092 [R600_RING_TYPE_DMA_INDEX] = { 1093 .ib_execute = &r600_dma_ring_ib_execute, 1094 .emit_fence = &r600_dma_fence_ring_emit, 1095 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1096 .cs_parse = &r600_dma_cs_parse, 1097 .ring_test = &r600_dma_ring_test, 1098 .ib_test = &r600_dma_ib_test, 1099 .is_lockup = &r600_dma_is_lockup, 1100 .get_rptr = &radeon_ring_generic_get_rptr, 1101 .get_wptr = &radeon_ring_generic_get_wptr, 1102 .set_wptr = &radeon_ring_generic_set_wptr, 1103 } 1104 }, 1105 .irq = { 1106 .set = &r600_irq_set, 1107 .process = &r600_irq_process, 1108 }, 1109 .display = { 1110 .bandwidth_update = &rv515_bandwidth_update, 1111 .get_vblank_counter = &rs600_get_vblank_counter, 1112 .wait_for_vblank = &avivo_wait_for_vblank, 1113 .set_backlight_level = &atombios_set_backlight_level, 1114 .get_backlight_level = &atombios_get_backlight_level, 1115 }, 1116 .copy = { 1117 .blit = &r600_copy_blit, 1118 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1119 .dma = &r600_copy_dma, 1120 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1121 .copy = &r600_copy_cpdma, 1122 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1123 }, 1124 .surface = { 1125 .set_reg = r600_set_surface_reg, 1126 .clear_reg = r600_clear_surface_reg, 1127 }, 1128 .hpd = { 1129 .init = &r600_hpd_init, 1130 .fini = &r600_hpd_fini, 1131 .sense = &r600_hpd_sense, 1132 .set_polarity = &r600_hpd_set_polarity, 1133 }, 1134 .pm = { 1135 .misc = &r600_pm_misc, 1136 .prepare = &rs600_pm_prepare, 1137 .finish = &rs600_pm_finish, 1138 .init_profile = &r600_pm_init_profile, 1139 .get_dynpm_state = &r600_pm_get_dynpm_state, 1140 .get_engine_clock = &radeon_atom_get_engine_clock, 1141 .set_engine_clock = &radeon_atom_set_engine_clock, 1142 .get_memory_clock = &radeon_atom_get_memory_clock, 1143 .set_memory_clock = &radeon_atom_set_memory_clock, 1144 .get_pcie_lanes = &r600_get_pcie_lanes, 1145 .set_pcie_lanes = &r600_set_pcie_lanes, 1146 .set_clock_gating = NULL, 1147 .get_temperature = &rv6xx_get_temp, 1148 }, 1149 .dpm = { 1150 .init = &rv6xx_dpm_init, 1151 .setup_asic = &rv6xx_setup_asic, 1152 .enable = &rv6xx_dpm_enable, 1153 .disable = &rv6xx_dpm_disable, 1154 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1155 .set_power_state = &rv6xx_dpm_set_power_state, 1156 .post_set_power_state = &r600_dpm_post_set_power_state, 1157 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed, 1158 .fini = &rv6xx_dpm_fini, 1159 .get_sclk = &rv6xx_dpm_get_sclk, 1160 .get_mclk = &rv6xx_dpm_get_mclk, 1161 .print_power_state = &rv6xx_dpm_print_power_state, 1162 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level, 1163 .force_performance_level = &rv6xx_dpm_force_performance_level, 1164 }, 1165 .pflip = { 1166 .pre_page_flip = &rs600_pre_page_flip, 1167 .page_flip = &rs600_page_flip, 1168 .post_page_flip = &rs600_post_page_flip, 1169 }, 1170 }; 1171 1172 static struct radeon_asic rs780_asic = { 1173 .init = &r600_init, 1174 .fini = &r600_fini, 1175 .suspend = &r600_suspend, 1176 .resume = &r600_resume, 1177 .vga_set_state = &r600_vga_set_state, 1178 .asic_reset = &r600_asic_reset, 1179 .ioctl_wait_idle = r600_ioctl_wait_idle, 1180 .gui_idle = &r600_gui_idle, 1181 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1182 .get_xclk = &r600_get_xclk, 1183 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1184 .gart = { 1185 .tlb_flush = &r600_pcie_gart_tlb_flush, 1186 .set_page = &rs600_gart_set_page, 1187 }, 1188 .ring = { 1189 [RADEON_RING_TYPE_GFX_INDEX] = { 1190 .ib_execute = &r600_ring_ib_execute, 1191 .emit_fence = &r600_fence_ring_emit, 1192 .emit_semaphore = &r600_semaphore_ring_emit, 1193 .cs_parse = &r600_cs_parse, 1194 .ring_test = &r600_ring_test, 1195 .ib_test = &r600_ib_test, 1196 .is_lockup = &r600_gfx_is_lockup, 1197 .get_rptr = &radeon_ring_generic_get_rptr, 1198 .get_wptr = &radeon_ring_generic_get_wptr, 1199 .set_wptr = &radeon_ring_generic_set_wptr, 1200 }, 1201 [R600_RING_TYPE_DMA_INDEX] = { 1202 .ib_execute = &r600_dma_ring_ib_execute, 1203 .emit_fence = &r600_dma_fence_ring_emit, 1204 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1205 .cs_parse = &r600_dma_cs_parse, 1206 .ring_test = &r600_dma_ring_test, 1207 .ib_test = &r600_dma_ib_test, 1208 .is_lockup = &r600_dma_is_lockup, 1209 .get_rptr = &radeon_ring_generic_get_rptr, 1210 .get_wptr = &radeon_ring_generic_get_wptr, 1211 .set_wptr = &radeon_ring_generic_set_wptr, 1212 } 1213 }, 1214 .irq = { 1215 .set = &r600_irq_set, 1216 .process = &r600_irq_process, 1217 }, 1218 .display = { 1219 .bandwidth_update = &rs690_bandwidth_update, 1220 .get_vblank_counter = &rs600_get_vblank_counter, 1221 .wait_for_vblank = &avivo_wait_for_vblank, 1222 .set_backlight_level = &atombios_set_backlight_level, 1223 .get_backlight_level = &atombios_get_backlight_level, 1224 .hdmi_enable = &r600_hdmi_enable, 1225 .hdmi_setmode = &r600_hdmi_setmode, 1226 }, 1227 .copy = { 1228 .blit = &r600_copy_blit, 1229 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1230 .dma = &r600_copy_dma, 1231 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1232 .copy = &r600_copy_cpdma, 1233 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1234 }, 1235 .surface = { 1236 .set_reg = r600_set_surface_reg, 1237 .clear_reg = r600_clear_surface_reg, 1238 }, 1239 .hpd = { 1240 .init = &r600_hpd_init, 1241 .fini = &r600_hpd_fini, 1242 .sense = &r600_hpd_sense, 1243 .set_polarity = &r600_hpd_set_polarity, 1244 }, 1245 .pm = { 1246 .misc = &r600_pm_misc, 1247 .prepare = &rs600_pm_prepare, 1248 .finish = &rs600_pm_finish, 1249 .init_profile = &rs780_pm_init_profile, 1250 .get_dynpm_state = &r600_pm_get_dynpm_state, 1251 .get_engine_clock = &radeon_atom_get_engine_clock, 1252 .set_engine_clock = &radeon_atom_set_engine_clock, 1253 .get_memory_clock = NULL, 1254 .set_memory_clock = NULL, 1255 .get_pcie_lanes = NULL, 1256 .set_pcie_lanes = NULL, 1257 .set_clock_gating = NULL, 1258 .get_temperature = &rv6xx_get_temp, 1259 }, 1260 .dpm = { 1261 .init = &rs780_dpm_init, 1262 .setup_asic = &rs780_dpm_setup_asic, 1263 .enable = &rs780_dpm_enable, 1264 .disable = &rs780_dpm_disable, 1265 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1266 .set_power_state = &rs780_dpm_set_power_state, 1267 .post_set_power_state = &r600_dpm_post_set_power_state, 1268 .display_configuration_changed = &rs780_dpm_display_configuration_changed, 1269 .fini = &rs780_dpm_fini, 1270 .get_sclk = &rs780_dpm_get_sclk, 1271 .get_mclk = &rs780_dpm_get_mclk, 1272 .print_power_state = &rs780_dpm_print_power_state, 1273 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level, 1274 }, 1275 .pflip = { 1276 .pre_page_flip = &rs600_pre_page_flip, 1277 .page_flip = &rs600_page_flip, 1278 .post_page_flip = &rs600_post_page_flip, 1279 }, 1280 }; 1281 1282 static struct radeon_asic rv770_asic = { 1283 .init = &rv770_init, 1284 .fini = &rv770_fini, 1285 .suspend = &rv770_suspend, 1286 .resume = &rv770_resume, 1287 .asic_reset = &r600_asic_reset, 1288 .vga_set_state = &r600_vga_set_state, 1289 .ioctl_wait_idle = r600_ioctl_wait_idle, 1290 .gui_idle = &r600_gui_idle, 1291 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1292 .get_xclk = &rv770_get_xclk, 1293 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1294 .gart = { 1295 .tlb_flush = &r600_pcie_gart_tlb_flush, 1296 .set_page = &rs600_gart_set_page, 1297 }, 1298 .ring = { 1299 [RADEON_RING_TYPE_GFX_INDEX] = { 1300 .ib_execute = &r600_ring_ib_execute, 1301 .emit_fence = &r600_fence_ring_emit, 1302 .emit_semaphore = &r600_semaphore_ring_emit, 1303 .cs_parse = &r600_cs_parse, 1304 .ring_test = &r600_ring_test, 1305 .ib_test = &r600_ib_test, 1306 .is_lockup = &r600_gfx_is_lockup, 1307 .get_rptr = &radeon_ring_generic_get_rptr, 1308 .get_wptr = &radeon_ring_generic_get_wptr, 1309 .set_wptr = &radeon_ring_generic_set_wptr, 1310 }, 1311 [R600_RING_TYPE_DMA_INDEX] = { 1312 .ib_execute = &r600_dma_ring_ib_execute, 1313 .emit_fence = &r600_dma_fence_ring_emit, 1314 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1315 .cs_parse = &r600_dma_cs_parse, 1316 .ring_test = &r600_dma_ring_test, 1317 .ib_test = &r600_dma_ib_test, 1318 .is_lockup = &r600_dma_is_lockup, 1319 .get_rptr = &radeon_ring_generic_get_rptr, 1320 .get_wptr = &radeon_ring_generic_get_wptr, 1321 .set_wptr = &radeon_ring_generic_set_wptr, 1322 }, 1323 [R600_RING_TYPE_UVD_INDEX] = { 1324 .ib_execute = &r600_uvd_ib_execute, 1325 .emit_fence = &r600_uvd_fence_emit, 1326 .emit_semaphore = &r600_uvd_semaphore_emit, 1327 .cs_parse = &radeon_uvd_cs_parse, 1328 .ring_test = &r600_uvd_ring_test, 1329 .ib_test = &r600_uvd_ib_test, 1330 .is_lockup = &radeon_ring_test_lockup, 1331 .get_rptr = &radeon_ring_generic_get_rptr, 1332 .get_wptr = &radeon_ring_generic_get_wptr, 1333 .set_wptr = &radeon_ring_generic_set_wptr, 1334 } 1335 }, 1336 .irq = { 1337 .set = &r600_irq_set, 1338 .process = &r600_irq_process, 1339 }, 1340 .display = { 1341 .bandwidth_update = &rv515_bandwidth_update, 1342 .get_vblank_counter = &rs600_get_vblank_counter, 1343 .wait_for_vblank = &avivo_wait_for_vblank, 1344 .set_backlight_level = &atombios_set_backlight_level, 1345 .get_backlight_level = &atombios_get_backlight_level, 1346 .hdmi_enable = &r600_hdmi_enable, 1347 .hdmi_setmode = &r600_hdmi_setmode, 1348 }, 1349 .copy = { 1350 .blit = &r600_copy_blit, 1351 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1352 .dma = &rv770_copy_dma, 1353 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1354 .copy = &rv770_copy_dma, 1355 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1356 }, 1357 .surface = { 1358 .set_reg = r600_set_surface_reg, 1359 .clear_reg = r600_clear_surface_reg, 1360 }, 1361 .hpd = { 1362 .init = &r600_hpd_init, 1363 .fini = &r600_hpd_fini, 1364 .sense = &r600_hpd_sense, 1365 .set_polarity = &r600_hpd_set_polarity, 1366 }, 1367 .pm = { 1368 .misc = &rv770_pm_misc, 1369 .prepare = &rs600_pm_prepare, 1370 .finish = &rs600_pm_finish, 1371 .init_profile = &r600_pm_init_profile, 1372 .get_dynpm_state = &r600_pm_get_dynpm_state, 1373 .get_engine_clock = &radeon_atom_get_engine_clock, 1374 .set_engine_clock = &radeon_atom_set_engine_clock, 1375 .get_memory_clock = &radeon_atom_get_memory_clock, 1376 .set_memory_clock = &radeon_atom_set_memory_clock, 1377 .get_pcie_lanes = &r600_get_pcie_lanes, 1378 .set_pcie_lanes = &r600_set_pcie_lanes, 1379 .set_clock_gating = &radeon_atom_set_clock_gating, 1380 .set_uvd_clocks = &rv770_set_uvd_clocks, 1381 .get_temperature = &rv770_get_temp, 1382 }, 1383 .dpm = { 1384 .init = &rv770_dpm_init, 1385 .setup_asic = &rv770_dpm_setup_asic, 1386 .enable = &rv770_dpm_enable, 1387 .disable = &rv770_dpm_disable, 1388 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1389 .set_power_state = &rv770_dpm_set_power_state, 1390 .post_set_power_state = &r600_dpm_post_set_power_state, 1391 .display_configuration_changed = &rv770_dpm_display_configuration_changed, 1392 .fini = &rv770_dpm_fini, 1393 .get_sclk = &rv770_dpm_get_sclk, 1394 .get_mclk = &rv770_dpm_get_mclk, 1395 .print_power_state = &rv770_dpm_print_power_state, 1396 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, 1397 .force_performance_level = &rv770_dpm_force_performance_level, 1398 .vblank_too_short = &rv770_dpm_vblank_too_short, 1399 }, 1400 .pflip = { 1401 .pre_page_flip = &rs600_pre_page_flip, 1402 .page_flip = &rv770_page_flip, 1403 .post_page_flip = &rs600_post_page_flip, 1404 }, 1405 }; 1406 1407 static struct radeon_asic evergreen_asic = { 1408 .init = &evergreen_init, 1409 .fini = &evergreen_fini, 1410 .suspend = &evergreen_suspend, 1411 .resume = &evergreen_resume, 1412 .asic_reset = &evergreen_asic_reset, 1413 .vga_set_state = &r600_vga_set_state, 1414 .ioctl_wait_idle = r600_ioctl_wait_idle, 1415 .gui_idle = &r600_gui_idle, 1416 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1417 .get_xclk = &rv770_get_xclk, 1418 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1419 .gart = { 1420 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1421 .set_page = &rs600_gart_set_page, 1422 }, 1423 .ring = { 1424 [RADEON_RING_TYPE_GFX_INDEX] = { 1425 .ib_execute = &evergreen_ring_ib_execute, 1426 .emit_fence = &r600_fence_ring_emit, 1427 .emit_semaphore = &r600_semaphore_ring_emit, 1428 .cs_parse = &evergreen_cs_parse, 1429 .ring_test = &r600_ring_test, 1430 .ib_test = &r600_ib_test, 1431 .is_lockup = &evergreen_gfx_is_lockup, 1432 .get_rptr = &radeon_ring_generic_get_rptr, 1433 .get_wptr = &radeon_ring_generic_get_wptr, 1434 .set_wptr = &radeon_ring_generic_set_wptr, 1435 }, 1436 [R600_RING_TYPE_DMA_INDEX] = { 1437 .ib_execute = &evergreen_dma_ring_ib_execute, 1438 .emit_fence = &evergreen_dma_fence_ring_emit, 1439 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1440 .cs_parse = &evergreen_dma_cs_parse, 1441 .ring_test = &r600_dma_ring_test, 1442 .ib_test = &r600_dma_ib_test, 1443 .is_lockup = &evergreen_dma_is_lockup, 1444 .get_rptr = &radeon_ring_generic_get_rptr, 1445 .get_wptr = &radeon_ring_generic_get_wptr, 1446 .set_wptr = &radeon_ring_generic_set_wptr, 1447 }, 1448 [R600_RING_TYPE_UVD_INDEX] = { 1449 .ib_execute = &r600_uvd_ib_execute, 1450 .emit_fence = &r600_uvd_fence_emit, 1451 .emit_semaphore = &r600_uvd_semaphore_emit, 1452 .cs_parse = &radeon_uvd_cs_parse, 1453 .ring_test = &r600_uvd_ring_test, 1454 .ib_test = &r600_uvd_ib_test, 1455 .is_lockup = &radeon_ring_test_lockup, 1456 .get_rptr = &radeon_ring_generic_get_rptr, 1457 .get_wptr = &radeon_ring_generic_get_wptr, 1458 .set_wptr = &radeon_ring_generic_set_wptr, 1459 } 1460 }, 1461 .irq = { 1462 .set = &evergreen_irq_set, 1463 .process = &evergreen_irq_process, 1464 }, 1465 .display = { 1466 .bandwidth_update = &evergreen_bandwidth_update, 1467 .get_vblank_counter = &evergreen_get_vblank_counter, 1468 .wait_for_vblank = &dce4_wait_for_vblank, 1469 .set_backlight_level = &atombios_set_backlight_level, 1470 .get_backlight_level = &atombios_get_backlight_level, 1471 .hdmi_enable = &evergreen_hdmi_enable, 1472 .hdmi_setmode = &evergreen_hdmi_setmode, 1473 }, 1474 .copy = { 1475 .blit = &r600_copy_blit, 1476 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1477 .dma = &evergreen_copy_dma, 1478 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1479 .copy = &evergreen_copy_dma, 1480 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1481 }, 1482 .surface = { 1483 .set_reg = r600_set_surface_reg, 1484 .clear_reg = r600_clear_surface_reg, 1485 }, 1486 .hpd = { 1487 .init = &evergreen_hpd_init, 1488 .fini = &evergreen_hpd_fini, 1489 .sense = &evergreen_hpd_sense, 1490 .set_polarity = &evergreen_hpd_set_polarity, 1491 }, 1492 .pm = { 1493 .misc = &evergreen_pm_misc, 1494 .prepare = &evergreen_pm_prepare, 1495 .finish = &evergreen_pm_finish, 1496 .init_profile = &r600_pm_init_profile, 1497 .get_dynpm_state = &r600_pm_get_dynpm_state, 1498 .get_engine_clock = &radeon_atom_get_engine_clock, 1499 .set_engine_clock = &radeon_atom_set_engine_clock, 1500 .get_memory_clock = &radeon_atom_get_memory_clock, 1501 .set_memory_clock = &radeon_atom_set_memory_clock, 1502 .get_pcie_lanes = &r600_get_pcie_lanes, 1503 .set_pcie_lanes = &r600_set_pcie_lanes, 1504 .set_clock_gating = NULL, 1505 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1506 .get_temperature = &evergreen_get_temp, 1507 }, 1508 .dpm = { 1509 .init = &cypress_dpm_init, 1510 .setup_asic = &cypress_dpm_setup_asic, 1511 .enable = &cypress_dpm_enable, 1512 .disable = &cypress_dpm_disable, 1513 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1514 .set_power_state = &cypress_dpm_set_power_state, 1515 .post_set_power_state = &r600_dpm_post_set_power_state, 1516 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1517 .fini = &cypress_dpm_fini, 1518 .get_sclk = &rv770_dpm_get_sclk, 1519 .get_mclk = &rv770_dpm_get_mclk, 1520 .print_power_state = &rv770_dpm_print_power_state, 1521 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, 1522 .force_performance_level = &rv770_dpm_force_performance_level, 1523 .vblank_too_short = &cypress_dpm_vblank_too_short, 1524 }, 1525 .pflip = { 1526 .pre_page_flip = &evergreen_pre_page_flip, 1527 .page_flip = &evergreen_page_flip, 1528 .post_page_flip = &evergreen_post_page_flip, 1529 }, 1530 }; 1531 1532 static struct radeon_asic sumo_asic = { 1533 .init = &evergreen_init, 1534 .fini = &evergreen_fini, 1535 .suspend = &evergreen_suspend, 1536 .resume = &evergreen_resume, 1537 .asic_reset = &evergreen_asic_reset, 1538 .vga_set_state = &r600_vga_set_state, 1539 .ioctl_wait_idle = r600_ioctl_wait_idle, 1540 .gui_idle = &r600_gui_idle, 1541 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1542 .get_xclk = &r600_get_xclk, 1543 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1544 .gart = { 1545 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1546 .set_page = &rs600_gart_set_page, 1547 }, 1548 .ring = { 1549 [RADEON_RING_TYPE_GFX_INDEX] = { 1550 .ib_execute = &evergreen_ring_ib_execute, 1551 .emit_fence = &r600_fence_ring_emit, 1552 .emit_semaphore = &r600_semaphore_ring_emit, 1553 .cs_parse = &evergreen_cs_parse, 1554 .ring_test = &r600_ring_test, 1555 .ib_test = &r600_ib_test, 1556 .is_lockup = &evergreen_gfx_is_lockup, 1557 .get_rptr = &radeon_ring_generic_get_rptr, 1558 .get_wptr = &radeon_ring_generic_get_wptr, 1559 .set_wptr = &radeon_ring_generic_set_wptr, 1560 }, 1561 [R600_RING_TYPE_DMA_INDEX] = { 1562 .ib_execute = &evergreen_dma_ring_ib_execute, 1563 .emit_fence = &evergreen_dma_fence_ring_emit, 1564 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1565 .cs_parse = &evergreen_dma_cs_parse, 1566 .ring_test = &r600_dma_ring_test, 1567 .ib_test = &r600_dma_ib_test, 1568 .is_lockup = &evergreen_dma_is_lockup, 1569 .get_rptr = &radeon_ring_generic_get_rptr, 1570 .get_wptr = &radeon_ring_generic_get_wptr, 1571 .set_wptr = &radeon_ring_generic_set_wptr, 1572 }, 1573 [R600_RING_TYPE_UVD_INDEX] = { 1574 .ib_execute = &r600_uvd_ib_execute, 1575 .emit_fence = &r600_uvd_fence_emit, 1576 .emit_semaphore = &r600_uvd_semaphore_emit, 1577 .cs_parse = &radeon_uvd_cs_parse, 1578 .ring_test = &r600_uvd_ring_test, 1579 .ib_test = &r600_uvd_ib_test, 1580 .is_lockup = &radeon_ring_test_lockup, 1581 .get_rptr = &radeon_ring_generic_get_rptr, 1582 .get_wptr = &radeon_ring_generic_get_wptr, 1583 .set_wptr = &radeon_ring_generic_set_wptr, 1584 } 1585 }, 1586 .irq = { 1587 .set = &evergreen_irq_set, 1588 .process = &evergreen_irq_process, 1589 }, 1590 .display = { 1591 .bandwidth_update = &evergreen_bandwidth_update, 1592 .get_vblank_counter = &evergreen_get_vblank_counter, 1593 .wait_for_vblank = &dce4_wait_for_vblank, 1594 .set_backlight_level = &atombios_set_backlight_level, 1595 .get_backlight_level = &atombios_get_backlight_level, 1596 .hdmi_enable = &evergreen_hdmi_enable, 1597 .hdmi_setmode = &evergreen_hdmi_setmode, 1598 }, 1599 .copy = { 1600 .blit = &r600_copy_blit, 1601 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1602 .dma = &evergreen_copy_dma, 1603 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1604 .copy = &evergreen_copy_dma, 1605 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1606 }, 1607 .surface = { 1608 .set_reg = r600_set_surface_reg, 1609 .clear_reg = r600_clear_surface_reg, 1610 }, 1611 .hpd = { 1612 .init = &evergreen_hpd_init, 1613 .fini = &evergreen_hpd_fini, 1614 .sense = &evergreen_hpd_sense, 1615 .set_polarity = &evergreen_hpd_set_polarity, 1616 }, 1617 .pm = { 1618 .misc = &evergreen_pm_misc, 1619 .prepare = &evergreen_pm_prepare, 1620 .finish = &evergreen_pm_finish, 1621 .init_profile = &sumo_pm_init_profile, 1622 .get_dynpm_state = &r600_pm_get_dynpm_state, 1623 .get_engine_clock = &radeon_atom_get_engine_clock, 1624 .set_engine_clock = &radeon_atom_set_engine_clock, 1625 .get_memory_clock = NULL, 1626 .set_memory_clock = NULL, 1627 .get_pcie_lanes = NULL, 1628 .set_pcie_lanes = NULL, 1629 .set_clock_gating = NULL, 1630 .set_uvd_clocks = &sumo_set_uvd_clocks, 1631 .get_temperature = &sumo_get_temp, 1632 }, 1633 .dpm = { 1634 .init = &sumo_dpm_init, 1635 .setup_asic = &sumo_dpm_setup_asic, 1636 .enable = &sumo_dpm_enable, 1637 .disable = &sumo_dpm_disable, 1638 .pre_set_power_state = &sumo_dpm_pre_set_power_state, 1639 .set_power_state = &sumo_dpm_set_power_state, 1640 .post_set_power_state = &sumo_dpm_post_set_power_state, 1641 .display_configuration_changed = &sumo_dpm_display_configuration_changed, 1642 .fini = &sumo_dpm_fini, 1643 .get_sclk = &sumo_dpm_get_sclk, 1644 .get_mclk = &sumo_dpm_get_mclk, 1645 .print_power_state = &sumo_dpm_print_power_state, 1646 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level, 1647 .force_performance_level = &sumo_dpm_force_performance_level, 1648 }, 1649 .pflip = { 1650 .pre_page_flip = &evergreen_pre_page_flip, 1651 .page_flip = &evergreen_page_flip, 1652 .post_page_flip = &evergreen_post_page_flip, 1653 }, 1654 }; 1655 1656 static struct radeon_asic btc_asic = { 1657 .init = &evergreen_init, 1658 .fini = &evergreen_fini, 1659 .suspend = &evergreen_suspend, 1660 .resume = &evergreen_resume, 1661 .asic_reset = &evergreen_asic_reset, 1662 .vga_set_state = &r600_vga_set_state, 1663 .ioctl_wait_idle = r600_ioctl_wait_idle, 1664 .gui_idle = &r600_gui_idle, 1665 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1666 .get_xclk = &rv770_get_xclk, 1667 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1668 .gart = { 1669 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1670 .set_page = &rs600_gart_set_page, 1671 }, 1672 .ring = { 1673 [RADEON_RING_TYPE_GFX_INDEX] = { 1674 .ib_execute = &evergreen_ring_ib_execute, 1675 .emit_fence = &r600_fence_ring_emit, 1676 .emit_semaphore = &r600_semaphore_ring_emit, 1677 .cs_parse = &evergreen_cs_parse, 1678 .ring_test = &r600_ring_test, 1679 .ib_test = &r600_ib_test, 1680 .is_lockup = &evergreen_gfx_is_lockup, 1681 .get_rptr = &radeon_ring_generic_get_rptr, 1682 .get_wptr = &radeon_ring_generic_get_wptr, 1683 .set_wptr = &radeon_ring_generic_set_wptr, 1684 }, 1685 [R600_RING_TYPE_DMA_INDEX] = { 1686 .ib_execute = &evergreen_dma_ring_ib_execute, 1687 .emit_fence = &evergreen_dma_fence_ring_emit, 1688 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1689 .cs_parse = &evergreen_dma_cs_parse, 1690 .ring_test = &r600_dma_ring_test, 1691 .ib_test = &r600_dma_ib_test, 1692 .is_lockup = &evergreen_dma_is_lockup, 1693 .get_rptr = &radeon_ring_generic_get_rptr, 1694 .get_wptr = &radeon_ring_generic_get_wptr, 1695 .set_wptr = &radeon_ring_generic_set_wptr, 1696 }, 1697 [R600_RING_TYPE_UVD_INDEX] = { 1698 .ib_execute = &r600_uvd_ib_execute, 1699 .emit_fence = &r600_uvd_fence_emit, 1700 .emit_semaphore = &r600_uvd_semaphore_emit, 1701 .cs_parse = &radeon_uvd_cs_parse, 1702 .ring_test = &r600_uvd_ring_test, 1703 .ib_test = &r600_uvd_ib_test, 1704 .is_lockup = &radeon_ring_test_lockup, 1705 .get_rptr = &radeon_ring_generic_get_rptr, 1706 .get_wptr = &radeon_ring_generic_get_wptr, 1707 .set_wptr = &radeon_ring_generic_set_wptr, 1708 } 1709 }, 1710 .irq = { 1711 .set = &evergreen_irq_set, 1712 .process = &evergreen_irq_process, 1713 }, 1714 .display = { 1715 .bandwidth_update = &evergreen_bandwidth_update, 1716 .get_vblank_counter = &evergreen_get_vblank_counter, 1717 .wait_for_vblank = &dce4_wait_for_vblank, 1718 .set_backlight_level = &atombios_set_backlight_level, 1719 .get_backlight_level = &atombios_get_backlight_level, 1720 .hdmi_enable = &evergreen_hdmi_enable, 1721 .hdmi_setmode = &evergreen_hdmi_setmode, 1722 }, 1723 .copy = { 1724 .blit = &r600_copy_blit, 1725 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1726 .dma = &evergreen_copy_dma, 1727 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1728 .copy = &evergreen_copy_dma, 1729 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1730 }, 1731 .surface = { 1732 .set_reg = r600_set_surface_reg, 1733 .clear_reg = r600_clear_surface_reg, 1734 }, 1735 .hpd = { 1736 .init = &evergreen_hpd_init, 1737 .fini = &evergreen_hpd_fini, 1738 .sense = &evergreen_hpd_sense, 1739 .set_polarity = &evergreen_hpd_set_polarity, 1740 }, 1741 .pm = { 1742 .misc = &evergreen_pm_misc, 1743 .prepare = &evergreen_pm_prepare, 1744 .finish = &evergreen_pm_finish, 1745 .init_profile = &btc_pm_init_profile, 1746 .get_dynpm_state = &r600_pm_get_dynpm_state, 1747 .get_engine_clock = &radeon_atom_get_engine_clock, 1748 .set_engine_clock = &radeon_atom_set_engine_clock, 1749 .get_memory_clock = &radeon_atom_get_memory_clock, 1750 .set_memory_clock = &radeon_atom_set_memory_clock, 1751 .get_pcie_lanes = &r600_get_pcie_lanes, 1752 .set_pcie_lanes = &r600_set_pcie_lanes, 1753 .set_clock_gating = NULL, 1754 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1755 .get_temperature = &evergreen_get_temp, 1756 }, 1757 .dpm = { 1758 .init = &btc_dpm_init, 1759 .setup_asic = &btc_dpm_setup_asic, 1760 .enable = &btc_dpm_enable, 1761 .disable = &btc_dpm_disable, 1762 .pre_set_power_state = &btc_dpm_pre_set_power_state, 1763 .set_power_state = &btc_dpm_set_power_state, 1764 .post_set_power_state = &btc_dpm_post_set_power_state, 1765 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1766 .fini = &btc_dpm_fini, 1767 .get_sclk = &btc_dpm_get_sclk, 1768 .get_mclk = &btc_dpm_get_mclk, 1769 .print_power_state = &rv770_dpm_print_power_state, 1770 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, 1771 .force_performance_level = &rv770_dpm_force_performance_level, 1772 .vblank_too_short = &btc_dpm_vblank_too_short, 1773 }, 1774 .pflip = { 1775 .pre_page_flip = &evergreen_pre_page_flip, 1776 .page_flip = &evergreen_page_flip, 1777 .post_page_flip = &evergreen_post_page_flip, 1778 }, 1779 }; 1780 1781 static struct radeon_asic cayman_asic = { 1782 .init = &cayman_init, 1783 .fini = &cayman_fini, 1784 .suspend = &cayman_suspend, 1785 .resume = &cayman_resume, 1786 .asic_reset = &cayman_asic_reset, 1787 .vga_set_state = &r600_vga_set_state, 1788 .ioctl_wait_idle = r600_ioctl_wait_idle, 1789 .gui_idle = &r600_gui_idle, 1790 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1791 .get_xclk = &rv770_get_xclk, 1792 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1793 .gart = { 1794 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1795 .set_page = &rs600_gart_set_page, 1796 }, 1797 .vm = { 1798 .init = &cayman_vm_init, 1799 .fini = &cayman_vm_fini, 1800 .pt_ring_index = R600_RING_TYPE_DMA_INDEX, 1801 .set_page = &cayman_vm_set_page, 1802 }, 1803 .ring = { 1804 [RADEON_RING_TYPE_GFX_INDEX] = { 1805 .ib_execute = &cayman_ring_ib_execute, 1806 .ib_parse = &evergreen_ib_parse, 1807 .emit_fence = &cayman_fence_ring_emit, 1808 .emit_semaphore = &r600_semaphore_ring_emit, 1809 .cs_parse = &evergreen_cs_parse, 1810 .ring_test = &r600_ring_test, 1811 .ib_test = &r600_ib_test, 1812 .is_lockup = &cayman_gfx_is_lockup, 1813 .vm_flush = &cayman_vm_flush, 1814 .get_rptr = &radeon_ring_generic_get_rptr, 1815 .get_wptr = &radeon_ring_generic_get_wptr, 1816 .set_wptr = &radeon_ring_generic_set_wptr, 1817 }, 1818 [CAYMAN_RING_TYPE_CP1_INDEX] = { 1819 .ib_execute = &cayman_ring_ib_execute, 1820 .ib_parse = &evergreen_ib_parse, 1821 .emit_fence = &cayman_fence_ring_emit, 1822 .emit_semaphore = &r600_semaphore_ring_emit, 1823 .cs_parse = &evergreen_cs_parse, 1824 .ring_test = &r600_ring_test, 1825 .ib_test = &r600_ib_test, 1826 .is_lockup = &cayman_gfx_is_lockup, 1827 .vm_flush = &cayman_vm_flush, 1828 .get_rptr = &radeon_ring_generic_get_rptr, 1829 .get_wptr = &radeon_ring_generic_get_wptr, 1830 .set_wptr = &radeon_ring_generic_set_wptr, 1831 }, 1832 [CAYMAN_RING_TYPE_CP2_INDEX] = { 1833 .ib_execute = &cayman_ring_ib_execute, 1834 .ib_parse = &evergreen_ib_parse, 1835 .emit_fence = &cayman_fence_ring_emit, 1836 .emit_semaphore = &r600_semaphore_ring_emit, 1837 .cs_parse = &evergreen_cs_parse, 1838 .ring_test = &r600_ring_test, 1839 .ib_test = &r600_ib_test, 1840 .is_lockup = &cayman_gfx_is_lockup, 1841 .vm_flush = &cayman_vm_flush, 1842 .get_rptr = &radeon_ring_generic_get_rptr, 1843 .get_wptr = &radeon_ring_generic_get_wptr, 1844 .set_wptr = &radeon_ring_generic_set_wptr, 1845 }, 1846 [R600_RING_TYPE_DMA_INDEX] = { 1847 .ib_execute = &cayman_dma_ring_ib_execute, 1848 .ib_parse = &evergreen_dma_ib_parse, 1849 .emit_fence = &evergreen_dma_fence_ring_emit, 1850 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1851 .cs_parse = &evergreen_dma_cs_parse, 1852 .ring_test = &r600_dma_ring_test, 1853 .ib_test = &r600_dma_ib_test, 1854 .is_lockup = &cayman_dma_is_lockup, 1855 .vm_flush = &cayman_dma_vm_flush, 1856 .get_rptr = &radeon_ring_generic_get_rptr, 1857 .get_wptr = &radeon_ring_generic_get_wptr, 1858 .set_wptr = &radeon_ring_generic_set_wptr, 1859 }, 1860 [CAYMAN_RING_TYPE_DMA1_INDEX] = { 1861 .ib_execute = &cayman_dma_ring_ib_execute, 1862 .ib_parse = &evergreen_dma_ib_parse, 1863 .emit_fence = &evergreen_dma_fence_ring_emit, 1864 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1865 .cs_parse = &evergreen_dma_cs_parse, 1866 .ring_test = &r600_dma_ring_test, 1867 .ib_test = &r600_dma_ib_test, 1868 .is_lockup = &cayman_dma_is_lockup, 1869 .vm_flush = &cayman_dma_vm_flush, 1870 .get_rptr = &radeon_ring_generic_get_rptr, 1871 .get_wptr = &radeon_ring_generic_get_wptr, 1872 .set_wptr = &radeon_ring_generic_set_wptr, 1873 }, 1874 [R600_RING_TYPE_UVD_INDEX] = { 1875 .ib_execute = &r600_uvd_ib_execute, 1876 .emit_fence = &r600_uvd_fence_emit, 1877 .emit_semaphore = &cayman_uvd_semaphore_emit, 1878 .cs_parse = &radeon_uvd_cs_parse, 1879 .ring_test = &r600_uvd_ring_test, 1880 .ib_test = &r600_uvd_ib_test, 1881 .is_lockup = &radeon_ring_test_lockup, 1882 .get_rptr = &radeon_ring_generic_get_rptr, 1883 .get_wptr = &radeon_ring_generic_get_wptr, 1884 .set_wptr = &radeon_ring_generic_set_wptr, 1885 } 1886 }, 1887 .irq = { 1888 .set = &evergreen_irq_set, 1889 .process = &evergreen_irq_process, 1890 }, 1891 .display = { 1892 .bandwidth_update = &evergreen_bandwidth_update, 1893 .get_vblank_counter = &evergreen_get_vblank_counter, 1894 .wait_for_vblank = &dce4_wait_for_vblank, 1895 .set_backlight_level = &atombios_set_backlight_level, 1896 .get_backlight_level = &atombios_get_backlight_level, 1897 .hdmi_enable = &evergreen_hdmi_enable, 1898 .hdmi_setmode = &evergreen_hdmi_setmode, 1899 }, 1900 .copy = { 1901 .blit = &r600_copy_blit, 1902 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1903 .dma = &evergreen_copy_dma, 1904 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1905 .copy = &evergreen_copy_dma, 1906 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1907 }, 1908 .surface = { 1909 .set_reg = r600_set_surface_reg, 1910 .clear_reg = r600_clear_surface_reg, 1911 }, 1912 .hpd = { 1913 .init = &evergreen_hpd_init, 1914 .fini = &evergreen_hpd_fini, 1915 .sense = &evergreen_hpd_sense, 1916 .set_polarity = &evergreen_hpd_set_polarity, 1917 }, 1918 .pm = { 1919 .misc = &evergreen_pm_misc, 1920 .prepare = &evergreen_pm_prepare, 1921 .finish = &evergreen_pm_finish, 1922 .init_profile = &btc_pm_init_profile, 1923 .get_dynpm_state = &r600_pm_get_dynpm_state, 1924 .get_engine_clock = &radeon_atom_get_engine_clock, 1925 .set_engine_clock = &radeon_atom_set_engine_clock, 1926 .get_memory_clock = &radeon_atom_get_memory_clock, 1927 .set_memory_clock = &radeon_atom_set_memory_clock, 1928 .get_pcie_lanes = &r600_get_pcie_lanes, 1929 .set_pcie_lanes = &r600_set_pcie_lanes, 1930 .set_clock_gating = NULL, 1931 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1932 .get_temperature = &evergreen_get_temp, 1933 }, 1934 .dpm = { 1935 .init = &ni_dpm_init, 1936 .setup_asic = &ni_dpm_setup_asic, 1937 .enable = &ni_dpm_enable, 1938 .disable = &ni_dpm_disable, 1939 .pre_set_power_state = &ni_dpm_pre_set_power_state, 1940 .set_power_state = &ni_dpm_set_power_state, 1941 .post_set_power_state = &ni_dpm_post_set_power_state, 1942 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1943 .fini = &ni_dpm_fini, 1944 .get_sclk = &ni_dpm_get_sclk, 1945 .get_mclk = &ni_dpm_get_mclk, 1946 .print_power_state = &ni_dpm_print_power_state, 1947 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level, 1948 .force_performance_level = &ni_dpm_force_performance_level, 1949 .vblank_too_short = &ni_dpm_vblank_too_short, 1950 }, 1951 .pflip = { 1952 .pre_page_flip = &evergreen_pre_page_flip, 1953 .page_flip = &evergreen_page_flip, 1954 .post_page_flip = &evergreen_post_page_flip, 1955 }, 1956 }; 1957 1958 static struct radeon_asic trinity_asic = { 1959 .init = &cayman_init, 1960 .fini = &cayman_fini, 1961 .suspend = &cayman_suspend, 1962 .resume = &cayman_resume, 1963 .asic_reset = &cayman_asic_reset, 1964 .vga_set_state = &r600_vga_set_state, 1965 .ioctl_wait_idle = r600_ioctl_wait_idle, 1966 .gui_idle = &r600_gui_idle, 1967 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1968 .get_xclk = &r600_get_xclk, 1969 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1970 .gart = { 1971 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1972 .set_page = &rs600_gart_set_page, 1973 }, 1974 .vm = { 1975 .init = &cayman_vm_init, 1976 .fini = &cayman_vm_fini, 1977 .pt_ring_index = R600_RING_TYPE_DMA_INDEX, 1978 .set_page = &cayman_vm_set_page, 1979 }, 1980 .ring = { 1981 [RADEON_RING_TYPE_GFX_INDEX] = { 1982 .ib_execute = &cayman_ring_ib_execute, 1983 .ib_parse = &evergreen_ib_parse, 1984 .emit_fence = &cayman_fence_ring_emit, 1985 .emit_semaphore = &r600_semaphore_ring_emit, 1986 .cs_parse = &evergreen_cs_parse, 1987 .ring_test = &r600_ring_test, 1988 .ib_test = &r600_ib_test, 1989 .is_lockup = &cayman_gfx_is_lockup, 1990 .vm_flush = &cayman_vm_flush, 1991 .get_rptr = &radeon_ring_generic_get_rptr, 1992 .get_wptr = &radeon_ring_generic_get_wptr, 1993 .set_wptr = &radeon_ring_generic_set_wptr, 1994 }, 1995 [CAYMAN_RING_TYPE_CP1_INDEX] = { 1996 .ib_execute = &cayman_ring_ib_execute, 1997 .ib_parse = &evergreen_ib_parse, 1998 .emit_fence = &cayman_fence_ring_emit, 1999 .emit_semaphore = &r600_semaphore_ring_emit, 2000 .cs_parse = &evergreen_cs_parse, 2001 .ring_test = &r600_ring_test, 2002 .ib_test = &r600_ib_test, 2003 .is_lockup = &cayman_gfx_is_lockup, 2004 .vm_flush = &cayman_vm_flush, 2005 .get_rptr = &radeon_ring_generic_get_rptr, 2006 .get_wptr = &radeon_ring_generic_get_wptr, 2007 .set_wptr = &radeon_ring_generic_set_wptr, 2008 }, 2009 [CAYMAN_RING_TYPE_CP2_INDEX] = { 2010 .ib_execute = &cayman_ring_ib_execute, 2011 .ib_parse = &evergreen_ib_parse, 2012 .emit_fence = &cayman_fence_ring_emit, 2013 .emit_semaphore = &r600_semaphore_ring_emit, 2014 .cs_parse = &evergreen_cs_parse, 2015 .ring_test = &r600_ring_test, 2016 .ib_test = &r600_ib_test, 2017 .is_lockup = &cayman_gfx_is_lockup, 2018 .vm_flush = &cayman_vm_flush, 2019 .get_rptr = &radeon_ring_generic_get_rptr, 2020 .get_wptr = &radeon_ring_generic_get_wptr, 2021 .set_wptr = &radeon_ring_generic_set_wptr, 2022 }, 2023 [R600_RING_TYPE_DMA_INDEX] = { 2024 .ib_execute = &cayman_dma_ring_ib_execute, 2025 .ib_parse = &evergreen_dma_ib_parse, 2026 .emit_fence = &evergreen_dma_fence_ring_emit, 2027 .emit_semaphore = &r600_dma_semaphore_ring_emit, 2028 .cs_parse = &evergreen_dma_cs_parse, 2029 .ring_test = &r600_dma_ring_test, 2030 .ib_test = &r600_dma_ib_test, 2031 .is_lockup = &cayman_dma_is_lockup, 2032 .vm_flush = &cayman_dma_vm_flush, 2033 .get_rptr = &radeon_ring_generic_get_rptr, 2034 .get_wptr = &radeon_ring_generic_get_wptr, 2035 .set_wptr = &radeon_ring_generic_set_wptr, 2036 }, 2037 [CAYMAN_RING_TYPE_DMA1_INDEX] = { 2038 .ib_execute = &cayman_dma_ring_ib_execute, 2039 .ib_parse = &evergreen_dma_ib_parse, 2040 .emit_fence = &evergreen_dma_fence_ring_emit, 2041 .emit_semaphore = &r600_dma_semaphore_ring_emit, 2042 .cs_parse = &evergreen_dma_cs_parse, 2043 .ring_test = &r600_dma_ring_test, 2044 .ib_test = &r600_dma_ib_test, 2045 .is_lockup = &cayman_dma_is_lockup, 2046 .vm_flush = &cayman_dma_vm_flush, 2047 .get_rptr = &radeon_ring_generic_get_rptr, 2048 .get_wptr = &radeon_ring_generic_get_wptr, 2049 .set_wptr = &radeon_ring_generic_set_wptr, 2050 }, 2051 [R600_RING_TYPE_UVD_INDEX] = { 2052 .ib_execute = &r600_uvd_ib_execute, 2053 .emit_fence = &r600_uvd_fence_emit, 2054 .emit_semaphore = &cayman_uvd_semaphore_emit, 2055 .cs_parse = &radeon_uvd_cs_parse, 2056 .ring_test = &r600_uvd_ring_test, 2057 .ib_test = &r600_uvd_ib_test, 2058 .is_lockup = &radeon_ring_test_lockup, 2059 .get_rptr = &radeon_ring_generic_get_rptr, 2060 .get_wptr = &radeon_ring_generic_get_wptr, 2061 .set_wptr = &radeon_ring_generic_set_wptr, 2062 } 2063 }, 2064 .irq = { 2065 .set = &evergreen_irq_set, 2066 .process = &evergreen_irq_process, 2067 }, 2068 .display = { 2069 .bandwidth_update = &dce6_bandwidth_update, 2070 .get_vblank_counter = &evergreen_get_vblank_counter, 2071 .wait_for_vblank = &dce4_wait_for_vblank, 2072 .set_backlight_level = &atombios_set_backlight_level, 2073 .get_backlight_level = &atombios_get_backlight_level, 2074 }, 2075 .copy = { 2076 .blit = &r600_copy_blit, 2077 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2078 .dma = &evergreen_copy_dma, 2079 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2080 .copy = &evergreen_copy_dma, 2081 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 2082 }, 2083 .surface = { 2084 .set_reg = r600_set_surface_reg, 2085 .clear_reg = r600_clear_surface_reg, 2086 }, 2087 .hpd = { 2088 .init = &evergreen_hpd_init, 2089 .fini = &evergreen_hpd_fini, 2090 .sense = &evergreen_hpd_sense, 2091 .set_polarity = &evergreen_hpd_set_polarity, 2092 }, 2093 .pm = { 2094 .misc = &evergreen_pm_misc, 2095 .prepare = &evergreen_pm_prepare, 2096 .finish = &evergreen_pm_finish, 2097 .init_profile = &sumo_pm_init_profile, 2098 .get_dynpm_state = &r600_pm_get_dynpm_state, 2099 .get_engine_clock = &radeon_atom_get_engine_clock, 2100 .set_engine_clock = &radeon_atom_set_engine_clock, 2101 .get_memory_clock = NULL, 2102 .set_memory_clock = NULL, 2103 .get_pcie_lanes = NULL, 2104 .set_pcie_lanes = NULL, 2105 .set_clock_gating = NULL, 2106 .set_uvd_clocks = &sumo_set_uvd_clocks, 2107 .get_temperature = &tn_get_temp, 2108 }, 2109 .dpm = { 2110 .init = &trinity_dpm_init, 2111 .setup_asic = &trinity_dpm_setup_asic, 2112 .enable = &trinity_dpm_enable, 2113 .disable = &trinity_dpm_disable, 2114 .pre_set_power_state = &trinity_dpm_pre_set_power_state, 2115 .set_power_state = &trinity_dpm_set_power_state, 2116 .post_set_power_state = &trinity_dpm_post_set_power_state, 2117 .display_configuration_changed = &trinity_dpm_display_configuration_changed, 2118 .fini = &trinity_dpm_fini, 2119 .get_sclk = &trinity_dpm_get_sclk, 2120 .get_mclk = &trinity_dpm_get_mclk, 2121 .print_power_state = &trinity_dpm_print_power_state, 2122 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level, 2123 .force_performance_level = &trinity_dpm_force_performance_level, 2124 }, 2125 .pflip = { 2126 .pre_page_flip = &evergreen_pre_page_flip, 2127 .page_flip = &evergreen_page_flip, 2128 .post_page_flip = &evergreen_post_page_flip, 2129 }, 2130 }; 2131 2132 static struct radeon_asic si_asic = { 2133 .init = &si_init, 2134 .fini = &si_fini, 2135 .suspend = &si_suspend, 2136 .resume = &si_resume, 2137 .asic_reset = &si_asic_reset, 2138 .vga_set_state = &r600_vga_set_state, 2139 .ioctl_wait_idle = r600_ioctl_wait_idle, 2140 .gui_idle = &r600_gui_idle, 2141 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 2142 .get_xclk = &si_get_xclk, 2143 .get_gpu_clock_counter = &si_get_gpu_clock_counter, 2144 .gart = { 2145 .tlb_flush = &si_pcie_gart_tlb_flush, 2146 .set_page = &rs600_gart_set_page, 2147 }, 2148 .vm = { 2149 .init = &si_vm_init, 2150 .fini = &si_vm_fini, 2151 .pt_ring_index = R600_RING_TYPE_DMA_INDEX, 2152 .set_page = &si_vm_set_page, 2153 }, 2154 .ring = { 2155 [RADEON_RING_TYPE_GFX_INDEX] = { 2156 .ib_execute = &si_ring_ib_execute, 2157 .ib_parse = &si_ib_parse, 2158 .emit_fence = &si_fence_ring_emit, 2159 .emit_semaphore = &r600_semaphore_ring_emit, 2160 .cs_parse = NULL, 2161 .ring_test = &r600_ring_test, 2162 .ib_test = &r600_ib_test, 2163 .is_lockup = &si_gfx_is_lockup, 2164 .vm_flush = &si_vm_flush, 2165 .get_rptr = &radeon_ring_generic_get_rptr, 2166 .get_wptr = &radeon_ring_generic_get_wptr, 2167 .set_wptr = &radeon_ring_generic_set_wptr, 2168 }, 2169 [CAYMAN_RING_TYPE_CP1_INDEX] = { 2170 .ib_execute = &si_ring_ib_execute, 2171 .ib_parse = &si_ib_parse, 2172 .emit_fence = &si_fence_ring_emit, 2173 .emit_semaphore = &r600_semaphore_ring_emit, 2174 .cs_parse = NULL, 2175 .ring_test = &r600_ring_test, 2176 .ib_test = &r600_ib_test, 2177 .is_lockup = &si_gfx_is_lockup, 2178 .vm_flush = &si_vm_flush, 2179 .get_rptr = &radeon_ring_generic_get_rptr, 2180 .get_wptr = &radeon_ring_generic_get_wptr, 2181 .set_wptr = &radeon_ring_generic_set_wptr, 2182 }, 2183 [CAYMAN_RING_TYPE_CP2_INDEX] = { 2184 .ib_execute = &si_ring_ib_execute, 2185 .ib_parse = &si_ib_parse, 2186 .emit_fence = &si_fence_ring_emit, 2187 .emit_semaphore = &r600_semaphore_ring_emit, 2188 .cs_parse = NULL, 2189 .ring_test = &r600_ring_test, 2190 .ib_test = &r600_ib_test, 2191 .is_lockup = &si_gfx_is_lockup, 2192 .vm_flush = &si_vm_flush, 2193 .get_rptr = &radeon_ring_generic_get_rptr, 2194 .get_wptr = &radeon_ring_generic_get_wptr, 2195 .set_wptr = &radeon_ring_generic_set_wptr, 2196 }, 2197 [R600_RING_TYPE_DMA_INDEX] = { 2198 .ib_execute = &cayman_dma_ring_ib_execute, 2199 .ib_parse = &evergreen_dma_ib_parse, 2200 .emit_fence = &evergreen_dma_fence_ring_emit, 2201 .emit_semaphore = &r600_dma_semaphore_ring_emit, 2202 .cs_parse = NULL, 2203 .ring_test = &r600_dma_ring_test, 2204 .ib_test = &r600_dma_ib_test, 2205 .is_lockup = &si_dma_is_lockup, 2206 .vm_flush = &si_dma_vm_flush, 2207 .get_rptr = &radeon_ring_generic_get_rptr, 2208 .get_wptr = &radeon_ring_generic_get_wptr, 2209 .set_wptr = &radeon_ring_generic_set_wptr, 2210 }, 2211 [CAYMAN_RING_TYPE_DMA1_INDEX] = { 2212 .ib_execute = &cayman_dma_ring_ib_execute, 2213 .ib_parse = &evergreen_dma_ib_parse, 2214 .emit_fence = &evergreen_dma_fence_ring_emit, 2215 .emit_semaphore = &r600_dma_semaphore_ring_emit, 2216 .cs_parse = NULL, 2217 .ring_test = &r600_dma_ring_test, 2218 .ib_test = &r600_dma_ib_test, 2219 .is_lockup = &si_dma_is_lockup, 2220 .vm_flush = &si_dma_vm_flush, 2221 .get_rptr = &radeon_ring_generic_get_rptr, 2222 .get_wptr = &radeon_ring_generic_get_wptr, 2223 .set_wptr = &radeon_ring_generic_set_wptr, 2224 }, 2225 [R600_RING_TYPE_UVD_INDEX] = { 2226 .ib_execute = &r600_uvd_ib_execute, 2227 .emit_fence = &r600_uvd_fence_emit, 2228 .emit_semaphore = &cayman_uvd_semaphore_emit, 2229 .cs_parse = &radeon_uvd_cs_parse, 2230 .ring_test = &r600_uvd_ring_test, 2231 .ib_test = &r600_uvd_ib_test, 2232 .is_lockup = &radeon_ring_test_lockup, 2233 .get_rptr = &radeon_ring_generic_get_rptr, 2234 .get_wptr = &radeon_ring_generic_get_wptr, 2235 .set_wptr = &radeon_ring_generic_set_wptr, 2236 } 2237 }, 2238 .irq = { 2239 .set = &si_irq_set, 2240 .process = &si_irq_process, 2241 }, 2242 .display = { 2243 .bandwidth_update = &dce6_bandwidth_update, 2244 .get_vblank_counter = &evergreen_get_vblank_counter, 2245 .wait_for_vblank = &dce4_wait_for_vblank, 2246 .set_backlight_level = &atombios_set_backlight_level, 2247 .get_backlight_level = &atombios_get_backlight_level, 2248 }, 2249 .copy = { 2250 .blit = NULL, 2251 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2252 .dma = &si_copy_dma, 2253 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2254 .copy = &si_copy_dma, 2255 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 2256 }, 2257 .surface = { 2258 .set_reg = r600_set_surface_reg, 2259 .clear_reg = r600_clear_surface_reg, 2260 }, 2261 .hpd = { 2262 .init = &evergreen_hpd_init, 2263 .fini = &evergreen_hpd_fini, 2264 .sense = &evergreen_hpd_sense, 2265 .set_polarity = &evergreen_hpd_set_polarity, 2266 }, 2267 .pm = { 2268 .misc = &evergreen_pm_misc, 2269 .prepare = &evergreen_pm_prepare, 2270 .finish = &evergreen_pm_finish, 2271 .init_profile = &sumo_pm_init_profile, 2272 .get_dynpm_state = &r600_pm_get_dynpm_state, 2273 .get_engine_clock = &radeon_atom_get_engine_clock, 2274 .set_engine_clock = &radeon_atom_set_engine_clock, 2275 .get_memory_clock = &radeon_atom_get_memory_clock, 2276 .set_memory_clock = &radeon_atom_set_memory_clock, 2277 .get_pcie_lanes = &r600_get_pcie_lanes, 2278 .set_pcie_lanes = &r600_set_pcie_lanes, 2279 .set_clock_gating = NULL, 2280 .set_uvd_clocks = &si_set_uvd_clocks, 2281 .get_temperature = &si_get_temp, 2282 }, 2283 .dpm = { 2284 .init = &si_dpm_init, 2285 .setup_asic = &si_dpm_setup_asic, 2286 .enable = &si_dpm_enable, 2287 .disable = &si_dpm_disable, 2288 .pre_set_power_state = &si_dpm_pre_set_power_state, 2289 .set_power_state = &si_dpm_set_power_state, 2290 .post_set_power_state = &si_dpm_post_set_power_state, 2291 .display_configuration_changed = &si_dpm_display_configuration_changed, 2292 .fini = &si_dpm_fini, 2293 .get_sclk = &ni_dpm_get_sclk, 2294 .get_mclk = &ni_dpm_get_mclk, 2295 .print_power_state = &ni_dpm_print_power_state, 2296 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level, 2297 .force_performance_level = &si_dpm_force_performance_level, 2298 .vblank_too_short = &ni_dpm_vblank_too_short, 2299 }, 2300 .pflip = { 2301 .pre_page_flip = &evergreen_pre_page_flip, 2302 .page_flip = &evergreen_page_flip, 2303 .post_page_flip = &evergreen_post_page_flip, 2304 }, 2305 }; 2306 2307 static struct radeon_asic ci_asic = { 2308 .init = &cik_init, 2309 .fini = &cik_fini, 2310 .suspend = &cik_suspend, 2311 .resume = &cik_resume, 2312 .asic_reset = &cik_asic_reset, 2313 .vga_set_state = &r600_vga_set_state, 2314 .ioctl_wait_idle = NULL, 2315 .gui_idle = &r600_gui_idle, 2316 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 2317 .get_xclk = &cik_get_xclk, 2318 .get_gpu_clock_counter = &cik_get_gpu_clock_counter, 2319 .gart = { 2320 .tlb_flush = &cik_pcie_gart_tlb_flush, 2321 .set_page = &rs600_gart_set_page, 2322 }, 2323 .vm = { 2324 .init = &cik_vm_init, 2325 .fini = &cik_vm_fini, 2326 .pt_ring_index = R600_RING_TYPE_DMA_INDEX, 2327 .set_page = &cik_vm_set_page, 2328 }, 2329 .ring = { 2330 [RADEON_RING_TYPE_GFX_INDEX] = { 2331 .ib_execute = &cik_ring_ib_execute, 2332 .ib_parse = &cik_ib_parse, 2333 .emit_fence = &cik_fence_gfx_ring_emit, 2334 .emit_semaphore = &cik_semaphore_ring_emit, 2335 .cs_parse = NULL, 2336 .ring_test = &cik_ring_test, 2337 .ib_test = &cik_ib_test, 2338 .is_lockup = &cik_gfx_is_lockup, 2339 .vm_flush = &cik_vm_flush, 2340 .get_rptr = &radeon_ring_generic_get_rptr, 2341 .get_wptr = &radeon_ring_generic_get_wptr, 2342 .set_wptr = &radeon_ring_generic_set_wptr, 2343 }, 2344 [CAYMAN_RING_TYPE_CP1_INDEX] = { 2345 .ib_execute = &cik_ring_ib_execute, 2346 .ib_parse = &cik_ib_parse, 2347 .emit_fence = &cik_fence_compute_ring_emit, 2348 .emit_semaphore = &cik_semaphore_ring_emit, 2349 .cs_parse = NULL, 2350 .ring_test = &cik_ring_test, 2351 .ib_test = &cik_ib_test, 2352 .is_lockup = &cik_gfx_is_lockup, 2353 .vm_flush = &cik_vm_flush, 2354 .get_rptr = &cik_compute_ring_get_rptr, 2355 .get_wptr = &cik_compute_ring_get_wptr, 2356 .set_wptr = &cik_compute_ring_set_wptr, 2357 }, 2358 [CAYMAN_RING_TYPE_CP2_INDEX] = { 2359 .ib_execute = &cik_ring_ib_execute, 2360 .ib_parse = &cik_ib_parse, 2361 .emit_fence = &cik_fence_compute_ring_emit, 2362 .emit_semaphore = &cik_semaphore_ring_emit, 2363 .cs_parse = NULL, 2364 .ring_test = &cik_ring_test, 2365 .ib_test = &cik_ib_test, 2366 .is_lockup = &cik_gfx_is_lockup, 2367 .vm_flush = &cik_vm_flush, 2368 .get_rptr = &cik_compute_ring_get_rptr, 2369 .get_wptr = &cik_compute_ring_get_wptr, 2370 .set_wptr = &cik_compute_ring_set_wptr, 2371 }, 2372 [R600_RING_TYPE_DMA_INDEX] = { 2373 .ib_execute = &cik_sdma_ring_ib_execute, 2374 .ib_parse = &cik_ib_parse, 2375 .emit_fence = &cik_sdma_fence_ring_emit, 2376 .emit_semaphore = &cik_sdma_semaphore_ring_emit, 2377 .cs_parse = NULL, 2378 .ring_test = &cik_sdma_ring_test, 2379 .ib_test = &cik_sdma_ib_test, 2380 .is_lockup = &cik_sdma_is_lockup, 2381 .vm_flush = &cik_dma_vm_flush, 2382 .get_rptr = &radeon_ring_generic_get_rptr, 2383 .get_wptr = &radeon_ring_generic_get_wptr, 2384 .set_wptr = &radeon_ring_generic_set_wptr, 2385 }, 2386 [CAYMAN_RING_TYPE_DMA1_INDEX] = { 2387 .ib_execute = &cik_sdma_ring_ib_execute, 2388 .ib_parse = &cik_ib_parse, 2389 .emit_fence = &cik_sdma_fence_ring_emit, 2390 .emit_semaphore = &cik_sdma_semaphore_ring_emit, 2391 .cs_parse = NULL, 2392 .ring_test = &cik_sdma_ring_test, 2393 .ib_test = &cik_sdma_ib_test, 2394 .is_lockup = &cik_sdma_is_lockup, 2395 .vm_flush = &cik_dma_vm_flush, 2396 .get_rptr = &radeon_ring_generic_get_rptr, 2397 .get_wptr = &radeon_ring_generic_get_wptr, 2398 .set_wptr = &radeon_ring_generic_set_wptr, 2399 }, 2400 [R600_RING_TYPE_UVD_INDEX] = { 2401 .ib_execute = &r600_uvd_ib_execute, 2402 .emit_fence = &r600_uvd_fence_emit, 2403 .emit_semaphore = &cayman_uvd_semaphore_emit, 2404 .cs_parse = &radeon_uvd_cs_parse, 2405 .ring_test = &r600_uvd_ring_test, 2406 .ib_test = &r600_uvd_ib_test, 2407 .is_lockup = &radeon_ring_test_lockup, 2408 .get_rptr = &radeon_ring_generic_get_rptr, 2409 .get_wptr = &radeon_ring_generic_get_wptr, 2410 .set_wptr = &radeon_ring_generic_set_wptr, 2411 } 2412 }, 2413 .irq = { 2414 .set = &cik_irq_set, 2415 .process = &cik_irq_process, 2416 }, 2417 .display = { 2418 .bandwidth_update = &dce8_bandwidth_update, 2419 .get_vblank_counter = &evergreen_get_vblank_counter, 2420 .wait_for_vblank = &dce4_wait_for_vblank, 2421 }, 2422 .copy = { 2423 .blit = NULL, 2424 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2425 .dma = &cik_copy_dma, 2426 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2427 .copy = &cik_copy_dma, 2428 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 2429 }, 2430 .surface = { 2431 .set_reg = r600_set_surface_reg, 2432 .clear_reg = r600_clear_surface_reg, 2433 }, 2434 .hpd = { 2435 .init = &evergreen_hpd_init, 2436 .fini = &evergreen_hpd_fini, 2437 .sense = &evergreen_hpd_sense, 2438 .set_polarity = &evergreen_hpd_set_polarity, 2439 }, 2440 .pm = { 2441 .misc = &evergreen_pm_misc, 2442 .prepare = &evergreen_pm_prepare, 2443 .finish = &evergreen_pm_finish, 2444 .init_profile = &sumo_pm_init_profile, 2445 .get_dynpm_state = &r600_pm_get_dynpm_state, 2446 .get_engine_clock = &radeon_atom_get_engine_clock, 2447 .set_engine_clock = &radeon_atom_set_engine_clock, 2448 .get_memory_clock = &radeon_atom_get_memory_clock, 2449 .set_memory_clock = &radeon_atom_set_memory_clock, 2450 .get_pcie_lanes = NULL, 2451 .set_pcie_lanes = NULL, 2452 .set_clock_gating = NULL, 2453 .set_uvd_clocks = &cik_set_uvd_clocks, 2454 }, 2455 .pflip = { 2456 .pre_page_flip = &evergreen_pre_page_flip, 2457 .page_flip = &evergreen_page_flip, 2458 .post_page_flip = &evergreen_post_page_flip, 2459 }, 2460 }; 2461 2462 static struct radeon_asic kv_asic = { 2463 .init = &cik_init, 2464 .fini = &cik_fini, 2465 .suspend = &cik_suspend, 2466 .resume = &cik_resume, 2467 .asic_reset = &cik_asic_reset, 2468 .vga_set_state = &r600_vga_set_state, 2469 .ioctl_wait_idle = NULL, 2470 .gui_idle = &r600_gui_idle, 2471 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 2472 .get_xclk = &cik_get_xclk, 2473 .get_gpu_clock_counter = &cik_get_gpu_clock_counter, 2474 .gart = { 2475 .tlb_flush = &cik_pcie_gart_tlb_flush, 2476 .set_page = &rs600_gart_set_page, 2477 }, 2478 .vm = { 2479 .init = &cik_vm_init, 2480 .fini = &cik_vm_fini, 2481 .pt_ring_index = R600_RING_TYPE_DMA_INDEX, 2482 .set_page = &cik_vm_set_page, 2483 }, 2484 .ring = { 2485 [RADEON_RING_TYPE_GFX_INDEX] = { 2486 .ib_execute = &cik_ring_ib_execute, 2487 .ib_parse = &cik_ib_parse, 2488 .emit_fence = &cik_fence_gfx_ring_emit, 2489 .emit_semaphore = &cik_semaphore_ring_emit, 2490 .cs_parse = NULL, 2491 .ring_test = &cik_ring_test, 2492 .ib_test = &cik_ib_test, 2493 .is_lockup = &cik_gfx_is_lockup, 2494 .vm_flush = &cik_vm_flush, 2495 .get_rptr = &radeon_ring_generic_get_rptr, 2496 .get_wptr = &radeon_ring_generic_get_wptr, 2497 .set_wptr = &radeon_ring_generic_set_wptr, 2498 }, 2499 [CAYMAN_RING_TYPE_CP1_INDEX] = { 2500 .ib_execute = &cik_ring_ib_execute, 2501 .ib_parse = &cik_ib_parse, 2502 .emit_fence = &cik_fence_compute_ring_emit, 2503 .emit_semaphore = &cik_semaphore_ring_emit, 2504 .cs_parse = NULL, 2505 .ring_test = &cik_ring_test, 2506 .ib_test = &cik_ib_test, 2507 .is_lockup = &cik_gfx_is_lockup, 2508 .vm_flush = &cik_vm_flush, 2509 .get_rptr = &cik_compute_ring_get_rptr, 2510 .get_wptr = &cik_compute_ring_get_wptr, 2511 .set_wptr = &cik_compute_ring_set_wptr, 2512 }, 2513 [CAYMAN_RING_TYPE_CP2_INDEX] = { 2514 .ib_execute = &cik_ring_ib_execute, 2515 .ib_parse = &cik_ib_parse, 2516 .emit_fence = &cik_fence_compute_ring_emit, 2517 .emit_semaphore = &cik_semaphore_ring_emit, 2518 .cs_parse = NULL, 2519 .ring_test = &cik_ring_test, 2520 .ib_test = &cik_ib_test, 2521 .is_lockup = &cik_gfx_is_lockup, 2522 .vm_flush = &cik_vm_flush, 2523 .get_rptr = &cik_compute_ring_get_rptr, 2524 .get_wptr = &cik_compute_ring_get_wptr, 2525 .set_wptr = &cik_compute_ring_set_wptr, 2526 }, 2527 [R600_RING_TYPE_DMA_INDEX] = { 2528 .ib_execute = &cik_sdma_ring_ib_execute, 2529 .ib_parse = &cik_ib_parse, 2530 .emit_fence = &cik_sdma_fence_ring_emit, 2531 .emit_semaphore = &cik_sdma_semaphore_ring_emit, 2532 .cs_parse = NULL, 2533 .ring_test = &cik_sdma_ring_test, 2534 .ib_test = &cik_sdma_ib_test, 2535 .is_lockup = &cik_sdma_is_lockup, 2536 .vm_flush = &cik_dma_vm_flush, 2537 .get_rptr = &radeon_ring_generic_get_rptr, 2538 .get_wptr = &radeon_ring_generic_get_wptr, 2539 .set_wptr = &radeon_ring_generic_set_wptr, 2540 }, 2541 [CAYMAN_RING_TYPE_DMA1_INDEX] = { 2542 .ib_execute = &cik_sdma_ring_ib_execute, 2543 .ib_parse = &cik_ib_parse, 2544 .emit_fence = &cik_sdma_fence_ring_emit, 2545 .emit_semaphore = &cik_sdma_semaphore_ring_emit, 2546 .cs_parse = NULL, 2547 .ring_test = &cik_sdma_ring_test, 2548 .ib_test = &cik_sdma_ib_test, 2549 .is_lockup = &cik_sdma_is_lockup, 2550 .vm_flush = &cik_dma_vm_flush, 2551 .get_rptr = &radeon_ring_generic_get_rptr, 2552 .get_wptr = &radeon_ring_generic_get_wptr, 2553 .set_wptr = &radeon_ring_generic_set_wptr, 2554 }, 2555 [R600_RING_TYPE_UVD_INDEX] = { 2556 .ib_execute = &r600_uvd_ib_execute, 2557 .emit_fence = &r600_uvd_fence_emit, 2558 .emit_semaphore = &cayman_uvd_semaphore_emit, 2559 .cs_parse = &radeon_uvd_cs_parse, 2560 .ring_test = &r600_uvd_ring_test, 2561 .ib_test = &r600_uvd_ib_test, 2562 .is_lockup = &radeon_ring_test_lockup, 2563 .get_rptr = &radeon_ring_generic_get_rptr, 2564 .get_wptr = &radeon_ring_generic_get_wptr, 2565 .set_wptr = &radeon_ring_generic_set_wptr, 2566 } 2567 }, 2568 .irq = { 2569 .set = &cik_irq_set, 2570 .process = &cik_irq_process, 2571 }, 2572 .display = { 2573 .bandwidth_update = &dce8_bandwidth_update, 2574 .get_vblank_counter = &evergreen_get_vblank_counter, 2575 .wait_for_vblank = &dce4_wait_for_vblank, 2576 }, 2577 .copy = { 2578 .blit = NULL, 2579 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2580 .dma = &cik_copy_dma, 2581 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2582 .copy = &cik_copy_dma, 2583 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 2584 }, 2585 .surface = { 2586 .set_reg = r600_set_surface_reg, 2587 .clear_reg = r600_clear_surface_reg, 2588 }, 2589 .hpd = { 2590 .init = &evergreen_hpd_init, 2591 .fini = &evergreen_hpd_fini, 2592 .sense = &evergreen_hpd_sense, 2593 .set_polarity = &evergreen_hpd_set_polarity, 2594 }, 2595 .pm = { 2596 .misc = &evergreen_pm_misc, 2597 .prepare = &evergreen_pm_prepare, 2598 .finish = &evergreen_pm_finish, 2599 .init_profile = &sumo_pm_init_profile, 2600 .get_dynpm_state = &r600_pm_get_dynpm_state, 2601 .get_engine_clock = &radeon_atom_get_engine_clock, 2602 .set_engine_clock = &radeon_atom_set_engine_clock, 2603 .get_memory_clock = &radeon_atom_get_memory_clock, 2604 .set_memory_clock = &radeon_atom_set_memory_clock, 2605 .get_pcie_lanes = NULL, 2606 .set_pcie_lanes = NULL, 2607 .set_clock_gating = NULL, 2608 .set_uvd_clocks = &cik_set_uvd_clocks, 2609 }, 2610 .pflip = { 2611 .pre_page_flip = &evergreen_pre_page_flip, 2612 .page_flip = &evergreen_page_flip, 2613 .post_page_flip = &evergreen_post_page_flip, 2614 }, 2615 }; 2616 2617 /** 2618 * radeon_asic_init - register asic specific callbacks 2619 * 2620 * @rdev: radeon device pointer 2621 * 2622 * Registers the appropriate asic specific callbacks for each 2623 * chip family. Also sets other asics specific info like the number 2624 * of crtcs and the register aperture accessors (all asics). 2625 * Returns 0 for success. 2626 */ 2627 int radeon_asic_init(struct radeon_device *rdev) 2628 { 2629 radeon_register_accessor_init(rdev); 2630 2631 /* set the number of crtcs */ 2632 if (rdev->flags & RADEON_SINGLE_CRTC) 2633 rdev->num_crtc = 1; 2634 else 2635 rdev->num_crtc = 2; 2636 2637 rdev->has_uvd = false; 2638 2639 switch (rdev->family) { 2640 case CHIP_R100: 2641 case CHIP_RV100: 2642 case CHIP_RS100: 2643 case CHIP_RV200: 2644 case CHIP_RS200: 2645 rdev->asic = &r100_asic; 2646 break; 2647 case CHIP_R200: 2648 case CHIP_RV250: 2649 case CHIP_RS300: 2650 case CHIP_RV280: 2651 rdev->asic = &r200_asic; 2652 break; 2653 case CHIP_R300: 2654 case CHIP_R350: 2655 case CHIP_RV350: 2656 case CHIP_RV380: 2657 if (rdev->flags & RADEON_IS_PCIE) 2658 rdev->asic = &r300_asic_pcie; 2659 else 2660 rdev->asic = &r300_asic; 2661 break; 2662 case CHIP_R420: 2663 case CHIP_R423: 2664 case CHIP_RV410: 2665 rdev->asic = &r420_asic; 2666 /* handle macs */ 2667 if (rdev->bios == NULL) { 2668 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock; 2669 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock; 2670 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock; 2671 rdev->asic->pm.set_memory_clock = NULL; 2672 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level; 2673 } 2674 break; 2675 case CHIP_RS400: 2676 case CHIP_RS480: 2677 rdev->asic = &rs400_asic; 2678 break; 2679 case CHIP_RS600: 2680 rdev->asic = &rs600_asic; 2681 break; 2682 case CHIP_RS690: 2683 case CHIP_RS740: 2684 rdev->asic = &rs690_asic; 2685 break; 2686 case CHIP_RV515: 2687 rdev->asic = &rv515_asic; 2688 break; 2689 case CHIP_R520: 2690 case CHIP_RV530: 2691 case CHIP_RV560: 2692 case CHIP_RV570: 2693 case CHIP_R580: 2694 rdev->asic = &r520_asic; 2695 break; 2696 case CHIP_R600: 2697 rdev->asic = &r600_asic; 2698 break; 2699 case CHIP_RV610: 2700 case CHIP_RV630: 2701 case CHIP_RV620: 2702 case CHIP_RV635: 2703 case CHIP_RV670: 2704 rdev->asic = &rv6xx_asic; 2705 rdev->has_uvd = true; 2706 break; 2707 case CHIP_RS780: 2708 case CHIP_RS880: 2709 rdev->asic = &rs780_asic; 2710 rdev->has_uvd = true; 2711 break; 2712 case CHIP_RV770: 2713 case CHIP_RV730: 2714 case CHIP_RV710: 2715 case CHIP_RV740: 2716 rdev->asic = &rv770_asic; 2717 rdev->has_uvd = true; 2718 break; 2719 case CHIP_CEDAR: 2720 case CHIP_REDWOOD: 2721 case CHIP_JUNIPER: 2722 case CHIP_CYPRESS: 2723 case CHIP_HEMLOCK: 2724 /* set num crtcs */ 2725 if (rdev->family == CHIP_CEDAR) 2726 rdev->num_crtc = 4; 2727 else 2728 rdev->num_crtc = 6; 2729 rdev->asic = &evergreen_asic; 2730 rdev->has_uvd = true; 2731 break; 2732 case CHIP_PALM: 2733 case CHIP_SUMO: 2734 case CHIP_SUMO2: 2735 rdev->asic = &sumo_asic; 2736 rdev->has_uvd = true; 2737 break; 2738 case CHIP_BARTS: 2739 case CHIP_TURKS: 2740 case CHIP_CAICOS: 2741 /* set num crtcs */ 2742 if (rdev->family == CHIP_CAICOS) 2743 rdev->num_crtc = 4; 2744 else 2745 rdev->num_crtc = 6; 2746 rdev->asic = &btc_asic; 2747 rdev->has_uvd = true; 2748 break; 2749 case CHIP_CAYMAN: 2750 rdev->asic = &cayman_asic; 2751 /* set num crtcs */ 2752 rdev->num_crtc = 6; 2753 rdev->has_uvd = true; 2754 break; 2755 case CHIP_ARUBA: 2756 rdev->asic = &trinity_asic; 2757 /* set num crtcs */ 2758 rdev->num_crtc = 4; 2759 rdev->has_uvd = true; 2760 break; 2761 case CHIP_TAHITI: 2762 case CHIP_PITCAIRN: 2763 case CHIP_VERDE: 2764 case CHIP_OLAND: 2765 case CHIP_HAINAN: 2766 rdev->asic = &si_asic; 2767 /* set num crtcs */ 2768 if (rdev->family == CHIP_HAINAN) 2769 rdev->num_crtc = 0; 2770 else if (rdev->family == CHIP_OLAND) 2771 rdev->num_crtc = 2; 2772 else 2773 rdev->num_crtc = 6; 2774 if (rdev->family == CHIP_HAINAN) 2775 rdev->has_uvd = false; 2776 else 2777 rdev->has_uvd = true; 2778 break; 2779 case CHIP_BONAIRE: 2780 rdev->asic = &ci_asic; 2781 rdev->num_crtc = 6; 2782 break; 2783 case CHIP_KAVERI: 2784 case CHIP_KABINI: 2785 rdev->asic = &kv_asic; 2786 /* set num crtcs */ 2787 if (rdev->family == CHIP_KAVERI) 2788 rdev->num_crtc = 4; 2789 else 2790 rdev->num_crtc = 2; 2791 break; 2792 default: 2793 /* FIXME: not supported yet */ 2794 return -EINVAL; 2795 } 2796 2797 if (rdev->flags & RADEON_IS_IGP) { 2798 rdev->asic->pm.get_memory_clock = NULL; 2799 rdev->asic->pm.set_memory_clock = NULL; 2800 } 2801 2802 return 0; 2803 } 2804 2805