1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <drm/drmP.h> 30 #include <drm/drm_crtc_helper.h> 31 #include <uapi_drm/radeon_drm.h> 32 #include "radeon_reg.h" 33 #include "radeon.h" 34 #include "radeon_asic.h" 35 #include "atom.h" 36 #include "rv770_dpm.h" 37 #include "ni_dpm.h" 38 39 /* 40 * Registers accessors functions. 41 */ 42 /** 43 * radeon_invalid_rreg - dummy reg read function 44 * 45 * @rdev: radeon device pointer 46 * @reg: offset of register 47 * 48 * Dummy register read function. Used for register blocks 49 * that certain asics don't have (all asics). 50 * Returns the value in the register. 51 */ 52 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) 53 { 54 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); 55 BUG_ON(1); 56 return 0; 57 } 58 59 /** 60 * radeon_invalid_wreg - dummy reg write function 61 * 62 * @rdev: radeon device pointer 63 * @reg: offset of register 64 * @v: value to write to the register 65 * 66 * Dummy register read function. Used for register blocks 67 * that certain asics don't have (all asics). 68 */ 69 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 70 { 71 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", 72 reg, v); 73 BUG_ON(1); 74 } 75 76 /** 77 * radeon_register_accessor_init - sets up the register accessor callbacks 78 * 79 * @rdev: radeon device pointer 80 * 81 * Sets up the register accessor callbacks for various register 82 * apertures. Not all asics have all apertures (all asics). 83 */ 84 static void radeon_register_accessor_init(struct radeon_device *rdev) 85 { 86 rdev->mc_rreg = &radeon_invalid_rreg; 87 rdev->mc_wreg = &radeon_invalid_wreg; 88 rdev->pll_rreg = &radeon_invalid_rreg; 89 rdev->pll_wreg = &radeon_invalid_wreg; 90 rdev->pciep_rreg = &radeon_invalid_rreg; 91 rdev->pciep_wreg = &radeon_invalid_wreg; 92 93 /* Don't change order as we are overridding accessor. */ 94 if (rdev->family < CHIP_RV515) { 95 rdev->pcie_reg_mask = 0xff; 96 } else { 97 rdev->pcie_reg_mask = 0x7ff; 98 } 99 /* FIXME: not sure here */ 100 if (rdev->family <= CHIP_R580) { 101 rdev->pll_rreg = &r100_pll_rreg; 102 rdev->pll_wreg = &r100_pll_wreg; 103 } 104 if (rdev->family >= CHIP_R420) { 105 rdev->mc_rreg = &r420_mc_rreg; 106 rdev->mc_wreg = &r420_mc_wreg; 107 } 108 if (rdev->family >= CHIP_RV515) { 109 rdev->mc_rreg = &rv515_mc_rreg; 110 rdev->mc_wreg = &rv515_mc_wreg; 111 } 112 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { 113 rdev->mc_rreg = &rs400_mc_rreg; 114 rdev->mc_wreg = &rs400_mc_wreg; 115 } 116 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 117 rdev->mc_rreg = &rs690_mc_rreg; 118 rdev->mc_wreg = &rs690_mc_wreg; 119 } 120 if (rdev->family == CHIP_RS600) { 121 rdev->mc_rreg = &rs600_mc_rreg; 122 rdev->mc_wreg = &rs600_mc_wreg; 123 } 124 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { 125 rdev->mc_rreg = &rs780_mc_rreg; 126 rdev->mc_wreg = &rs780_mc_wreg; 127 } 128 129 if (rdev->family >= CHIP_BONAIRE) { 130 rdev->pciep_rreg = &cik_pciep_rreg; 131 rdev->pciep_wreg = &cik_pciep_wreg; 132 } else if (rdev->family >= CHIP_R600) { 133 rdev->pciep_rreg = &r600_pciep_rreg; 134 rdev->pciep_wreg = &r600_pciep_wreg; 135 } 136 } 137 138 139 /* helper to disable agp */ 140 /** 141 * radeon_agp_disable - AGP disable helper function 142 * 143 * @rdev: radeon device pointer 144 * 145 * Removes AGP flags and changes the gart callbacks on AGP 146 * cards when using the internal gart rather than AGP (all asics). 147 */ 148 void radeon_agp_disable(struct radeon_device *rdev) 149 { 150 rdev->flags &= ~RADEON_IS_AGP; 151 if (rdev->family >= CHIP_R600) { 152 DRM_INFO("Forcing AGP to PCIE mode\n"); 153 rdev->flags |= RADEON_IS_PCIE; 154 } else if (rdev->family >= CHIP_RV515 || 155 rdev->family == CHIP_RV380 || 156 rdev->family == CHIP_RV410 || 157 rdev->family == CHIP_R423) { 158 DRM_INFO("Forcing AGP to PCIE mode\n"); 159 rdev->flags |= RADEON_IS_PCIE; 160 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; 161 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; 162 } else { 163 DRM_INFO("Forcing AGP to PCI mode\n"); 164 rdev->flags |= RADEON_IS_PCI; 165 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; 166 rdev->asic->gart.set_page = &r100_pci_gart_set_page; 167 } 168 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 169 } 170 171 /* 172 * ASIC 173 */ 174 175 static struct radeon_asic_ring r100_gfx_ring = { 176 .ib_execute = &r100_ring_ib_execute, 177 .emit_fence = &r100_fence_ring_emit, 178 .emit_semaphore = &r100_semaphore_ring_emit, 179 .cs_parse = &r100_cs_parse, 180 .ring_start = &r100_ring_start, 181 .ring_test = &r100_ring_test, 182 .ib_test = &r100_ib_test, 183 .is_lockup = &r100_gpu_is_lockup, 184 .get_rptr = &r100_gfx_get_rptr, 185 .get_wptr = &r100_gfx_get_wptr, 186 .set_wptr = &r100_gfx_set_wptr, 187 }; 188 189 static struct radeon_asic r100_asic = { 190 .init = &r100_init, 191 .fini = &r100_fini, 192 .suspend = &r100_suspend, 193 .resume = &r100_resume, 194 .vga_set_state = &r100_vga_set_state, 195 .asic_reset = &r100_asic_reset, 196 .mmio_hdp_flush = NULL, 197 .gui_idle = &r100_gui_idle, 198 .mc_wait_for_idle = &r100_mc_wait_for_idle, 199 .gart = { 200 .tlb_flush = &r100_pci_gart_tlb_flush, 201 .set_page = &r100_pci_gart_set_page, 202 }, 203 .ring = { 204 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring 205 }, 206 .irq = { 207 .set = &r100_irq_set, 208 .process = &r100_irq_process, 209 }, 210 .display = { 211 .bandwidth_update = &r100_bandwidth_update, 212 .get_vblank_counter = &r100_get_vblank_counter, 213 .wait_for_vblank = &r100_wait_for_vblank, 214 .set_backlight_level = &radeon_legacy_set_backlight_level, 215 .get_backlight_level = &radeon_legacy_get_backlight_level, 216 }, 217 .copy = { 218 .blit = &r100_copy_blit, 219 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 220 .dma = NULL, 221 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 222 .copy = &r100_copy_blit, 223 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 224 }, 225 .surface = { 226 .set_reg = r100_set_surface_reg, 227 .clear_reg = r100_clear_surface_reg, 228 }, 229 .hpd = { 230 .init = &r100_hpd_init, 231 .fini = &r100_hpd_fini, 232 .sense = &r100_hpd_sense, 233 .set_polarity = &r100_hpd_set_polarity, 234 }, 235 .pm = { 236 .misc = &r100_pm_misc, 237 .prepare = &r100_pm_prepare, 238 .finish = &r100_pm_finish, 239 .init_profile = &r100_pm_init_profile, 240 .get_dynpm_state = &r100_pm_get_dynpm_state, 241 .get_engine_clock = &radeon_legacy_get_engine_clock, 242 .set_engine_clock = &radeon_legacy_set_engine_clock, 243 .get_memory_clock = &radeon_legacy_get_memory_clock, 244 .set_memory_clock = NULL, 245 .get_pcie_lanes = NULL, 246 .set_pcie_lanes = NULL, 247 .set_clock_gating = &radeon_legacy_set_clock_gating, 248 }, 249 .pflip = { 250 .page_flip = &r100_page_flip, 251 .page_flip_pending = &r100_page_flip_pending, 252 }, 253 }; 254 255 static struct radeon_asic r200_asic = { 256 .init = &r100_init, 257 .fini = &r100_fini, 258 .suspend = &r100_suspend, 259 .resume = &r100_resume, 260 .vga_set_state = &r100_vga_set_state, 261 .asic_reset = &r100_asic_reset, 262 .mmio_hdp_flush = NULL, 263 .gui_idle = &r100_gui_idle, 264 .mc_wait_for_idle = &r100_mc_wait_for_idle, 265 .gart = { 266 .tlb_flush = &r100_pci_gart_tlb_flush, 267 .set_page = &r100_pci_gart_set_page, 268 }, 269 .ring = { 270 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring 271 }, 272 .irq = { 273 .set = &r100_irq_set, 274 .process = &r100_irq_process, 275 }, 276 .display = { 277 .bandwidth_update = &r100_bandwidth_update, 278 .get_vblank_counter = &r100_get_vblank_counter, 279 .wait_for_vblank = &r100_wait_for_vblank, 280 .set_backlight_level = &radeon_legacy_set_backlight_level, 281 .get_backlight_level = &radeon_legacy_get_backlight_level, 282 }, 283 .copy = { 284 .blit = &r100_copy_blit, 285 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 286 .dma = &r200_copy_dma, 287 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 288 .copy = &r100_copy_blit, 289 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 290 }, 291 .surface = { 292 .set_reg = r100_set_surface_reg, 293 .clear_reg = r100_clear_surface_reg, 294 }, 295 .hpd = { 296 .init = &r100_hpd_init, 297 .fini = &r100_hpd_fini, 298 .sense = &r100_hpd_sense, 299 .set_polarity = &r100_hpd_set_polarity, 300 }, 301 .pm = { 302 .misc = &r100_pm_misc, 303 .prepare = &r100_pm_prepare, 304 .finish = &r100_pm_finish, 305 .init_profile = &r100_pm_init_profile, 306 .get_dynpm_state = &r100_pm_get_dynpm_state, 307 .get_engine_clock = &radeon_legacy_get_engine_clock, 308 .set_engine_clock = &radeon_legacy_set_engine_clock, 309 .get_memory_clock = &radeon_legacy_get_memory_clock, 310 .set_memory_clock = NULL, 311 .get_pcie_lanes = NULL, 312 .set_pcie_lanes = NULL, 313 .set_clock_gating = &radeon_legacy_set_clock_gating, 314 }, 315 .pflip = { 316 .page_flip = &r100_page_flip, 317 .page_flip_pending = &r100_page_flip_pending, 318 }, 319 }; 320 321 static struct radeon_asic_ring r300_gfx_ring = { 322 .ib_execute = &r100_ring_ib_execute, 323 .emit_fence = &r300_fence_ring_emit, 324 .emit_semaphore = &r100_semaphore_ring_emit, 325 .cs_parse = &r300_cs_parse, 326 .ring_start = &r300_ring_start, 327 .ring_test = &r100_ring_test, 328 .ib_test = &r100_ib_test, 329 .is_lockup = &r100_gpu_is_lockup, 330 .get_rptr = &r100_gfx_get_rptr, 331 .get_wptr = &r100_gfx_get_wptr, 332 .set_wptr = &r100_gfx_set_wptr, 333 }; 334 335 static struct radeon_asic r300_asic = { 336 .init = &r300_init, 337 .fini = &r300_fini, 338 .suspend = &r300_suspend, 339 .resume = &r300_resume, 340 .vga_set_state = &r100_vga_set_state, 341 .asic_reset = &r300_asic_reset, 342 .mmio_hdp_flush = NULL, 343 .gui_idle = &r100_gui_idle, 344 .mc_wait_for_idle = &r300_mc_wait_for_idle, 345 .gart = { 346 .tlb_flush = &r100_pci_gart_tlb_flush, 347 .set_page = &r100_pci_gart_set_page, 348 }, 349 .ring = { 350 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 351 }, 352 .irq = { 353 .set = &r100_irq_set, 354 .process = &r100_irq_process, 355 }, 356 .display = { 357 .bandwidth_update = &r100_bandwidth_update, 358 .get_vblank_counter = &r100_get_vblank_counter, 359 .wait_for_vblank = &r100_wait_for_vblank, 360 .set_backlight_level = &radeon_legacy_set_backlight_level, 361 .get_backlight_level = &radeon_legacy_get_backlight_level, 362 }, 363 .copy = { 364 .blit = &r100_copy_blit, 365 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 366 .dma = &r200_copy_dma, 367 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 368 .copy = &r100_copy_blit, 369 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 370 }, 371 .surface = { 372 .set_reg = r100_set_surface_reg, 373 .clear_reg = r100_clear_surface_reg, 374 }, 375 .hpd = { 376 .init = &r100_hpd_init, 377 .fini = &r100_hpd_fini, 378 .sense = &r100_hpd_sense, 379 .set_polarity = &r100_hpd_set_polarity, 380 }, 381 .pm = { 382 .misc = &r100_pm_misc, 383 .prepare = &r100_pm_prepare, 384 .finish = &r100_pm_finish, 385 .init_profile = &r100_pm_init_profile, 386 .get_dynpm_state = &r100_pm_get_dynpm_state, 387 .get_engine_clock = &radeon_legacy_get_engine_clock, 388 .set_engine_clock = &radeon_legacy_set_engine_clock, 389 .get_memory_clock = &radeon_legacy_get_memory_clock, 390 .set_memory_clock = NULL, 391 .get_pcie_lanes = &rv370_get_pcie_lanes, 392 .set_pcie_lanes = &rv370_set_pcie_lanes, 393 .set_clock_gating = &radeon_legacy_set_clock_gating, 394 }, 395 .pflip = { 396 .page_flip = &r100_page_flip, 397 .page_flip_pending = &r100_page_flip_pending, 398 }, 399 }; 400 401 static struct radeon_asic r300_asic_pcie = { 402 .init = &r300_init, 403 .fini = &r300_fini, 404 .suspend = &r300_suspend, 405 .resume = &r300_resume, 406 .vga_set_state = &r100_vga_set_state, 407 .asic_reset = &r300_asic_reset, 408 .mmio_hdp_flush = NULL, 409 .gui_idle = &r100_gui_idle, 410 .mc_wait_for_idle = &r300_mc_wait_for_idle, 411 .gart = { 412 .tlb_flush = &rv370_pcie_gart_tlb_flush, 413 .set_page = &rv370_pcie_gart_set_page, 414 }, 415 .ring = { 416 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 417 }, 418 .irq = { 419 .set = &r100_irq_set, 420 .process = &r100_irq_process, 421 }, 422 .display = { 423 .bandwidth_update = &r100_bandwidth_update, 424 .get_vblank_counter = &r100_get_vblank_counter, 425 .wait_for_vblank = &r100_wait_for_vblank, 426 .set_backlight_level = &radeon_legacy_set_backlight_level, 427 .get_backlight_level = &radeon_legacy_get_backlight_level, 428 }, 429 .copy = { 430 .blit = &r100_copy_blit, 431 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 432 .dma = &r200_copy_dma, 433 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 434 .copy = &r100_copy_blit, 435 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 436 }, 437 .surface = { 438 .set_reg = r100_set_surface_reg, 439 .clear_reg = r100_clear_surface_reg, 440 }, 441 .hpd = { 442 .init = &r100_hpd_init, 443 .fini = &r100_hpd_fini, 444 .sense = &r100_hpd_sense, 445 .set_polarity = &r100_hpd_set_polarity, 446 }, 447 .pm = { 448 .misc = &r100_pm_misc, 449 .prepare = &r100_pm_prepare, 450 .finish = &r100_pm_finish, 451 .init_profile = &r100_pm_init_profile, 452 .get_dynpm_state = &r100_pm_get_dynpm_state, 453 .get_engine_clock = &radeon_legacy_get_engine_clock, 454 .set_engine_clock = &radeon_legacy_set_engine_clock, 455 .get_memory_clock = &radeon_legacy_get_memory_clock, 456 .set_memory_clock = NULL, 457 .get_pcie_lanes = &rv370_get_pcie_lanes, 458 .set_pcie_lanes = &rv370_set_pcie_lanes, 459 .set_clock_gating = &radeon_legacy_set_clock_gating, 460 }, 461 .pflip = { 462 .page_flip = &r100_page_flip, 463 .page_flip_pending = &r100_page_flip_pending, 464 }, 465 }; 466 467 static struct radeon_asic r420_asic = { 468 .init = &r420_init, 469 .fini = &r420_fini, 470 .suspend = &r420_suspend, 471 .resume = &r420_resume, 472 .vga_set_state = &r100_vga_set_state, 473 .asic_reset = &r300_asic_reset, 474 .mmio_hdp_flush = NULL, 475 .gui_idle = &r100_gui_idle, 476 .mc_wait_for_idle = &r300_mc_wait_for_idle, 477 .gart = { 478 .tlb_flush = &rv370_pcie_gart_tlb_flush, 479 .set_page = &rv370_pcie_gart_set_page, 480 }, 481 .ring = { 482 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 483 }, 484 .irq = { 485 .set = &r100_irq_set, 486 .process = &r100_irq_process, 487 }, 488 .display = { 489 .bandwidth_update = &r100_bandwidth_update, 490 .get_vblank_counter = &r100_get_vblank_counter, 491 .wait_for_vblank = &r100_wait_for_vblank, 492 .set_backlight_level = &atombios_set_backlight_level, 493 .get_backlight_level = &atombios_get_backlight_level, 494 }, 495 .copy = { 496 .blit = &r100_copy_blit, 497 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 498 .dma = &r200_copy_dma, 499 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 500 .copy = &r100_copy_blit, 501 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 502 }, 503 .surface = { 504 .set_reg = r100_set_surface_reg, 505 .clear_reg = r100_clear_surface_reg, 506 }, 507 .hpd = { 508 .init = &r100_hpd_init, 509 .fini = &r100_hpd_fini, 510 .sense = &r100_hpd_sense, 511 .set_polarity = &r100_hpd_set_polarity, 512 }, 513 .pm = { 514 .misc = &r100_pm_misc, 515 .prepare = &r100_pm_prepare, 516 .finish = &r100_pm_finish, 517 .init_profile = &r420_pm_init_profile, 518 .get_dynpm_state = &r100_pm_get_dynpm_state, 519 .get_engine_clock = &radeon_atom_get_engine_clock, 520 .set_engine_clock = &radeon_atom_set_engine_clock, 521 .get_memory_clock = &radeon_atom_get_memory_clock, 522 .set_memory_clock = &radeon_atom_set_memory_clock, 523 .get_pcie_lanes = &rv370_get_pcie_lanes, 524 .set_pcie_lanes = &rv370_set_pcie_lanes, 525 .set_clock_gating = &radeon_atom_set_clock_gating, 526 }, 527 .pflip = { 528 .page_flip = &r100_page_flip, 529 .page_flip_pending = &r100_page_flip_pending, 530 }, 531 }; 532 533 static struct radeon_asic rs400_asic = { 534 .init = &rs400_init, 535 .fini = &rs400_fini, 536 .suspend = &rs400_suspend, 537 .resume = &rs400_resume, 538 .vga_set_state = &r100_vga_set_state, 539 .asic_reset = &r300_asic_reset, 540 .mmio_hdp_flush = NULL, 541 .gui_idle = &r100_gui_idle, 542 .mc_wait_for_idle = &rs400_mc_wait_for_idle, 543 .gart = { 544 .tlb_flush = &rs400_gart_tlb_flush, 545 .set_page = &rs400_gart_set_page, 546 }, 547 .ring = { 548 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 549 }, 550 .irq = { 551 .set = &r100_irq_set, 552 .process = &r100_irq_process, 553 }, 554 .display = { 555 .bandwidth_update = &r100_bandwidth_update, 556 .get_vblank_counter = &r100_get_vblank_counter, 557 .wait_for_vblank = &r100_wait_for_vblank, 558 .set_backlight_level = &radeon_legacy_set_backlight_level, 559 .get_backlight_level = &radeon_legacy_get_backlight_level, 560 }, 561 .copy = { 562 .blit = &r100_copy_blit, 563 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 564 .dma = &r200_copy_dma, 565 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 566 .copy = &r100_copy_blit, 567 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 568 }, 569 .surface = { 570 .set_reg = r100_set_surface_reg, 571 .clear_reg = r100_clear_surface_reg, 572 }, 573 .hpd = { 574 .init = &r100_hpd_init, 575 .fini = &r100_hpd_fini, 576 .sense = &r100_hpd_sense, 577 .set_polarity = &r100_hpd_set_polarity, 578 }, 579 .pm = { 580 .misc = &r100_pm_misc, 581 .prepare = &r100_pm_prepare, 582 .finish = &r100_pm_finish, 583 .init_profile = &r100_pm_init_profile, 584 .get_dynpm_state = &r100_pm_get_dynpm_state, 585 .get_engine_clock = &radeon_legacy_get_engine_clock, 586 .set_engine_clock = &radeon_legacy_set_engine_clock, 587 .get_memory_clock = &radeon_legacy_get_memory_clock, 588 .set_memory_clock = NULL, 589 .get_pcie_lanes = NULL, 590 .set_pcie_lanes = NULL, 591 .set_clock_gating = &radeon_legacy_set_clock_gating, 592 }, 593 .pflip = { 594 .page_flip = &r100_page_flip, 595 .page_flip_pending = &r100_page_flip_pending, 596 }, 597 }; 598 599 static struct radeon_asic rs600_asic = { 600 .init = &rs600_init, 601 .fini = &rs600_fini, 602 .suspend = &rs600_suspend, 603 .resume = &rs600_resume, 604 .vga_set_state = &r100_vga_set_state, 605 .asic_reset = &rs600_asic_reset, 606 .mmio_hdp_flush = NULL, 607 .gui_idle = &r100_gui_idle, 608 .mc_wait_for_idle = &rs600_mc_wait_for_idle, 609 .gart = { 610 .tlb_flush = &rs600_gart_tlb_flush, 611 .set_page = &rs600_gart_set_page, 612 }, 613 .ring = { 614 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 615 }, 616 .irq = { 617 .set = &rs600_irq_set, 618 .process = &rs600_irq_process, 619 }, 620 .display = { 621 .bandwidth_update = &rs600_bandwidth_update, 622 .get_vblank_counter = &rs600_get_vblank_counter, 623 .wait_for_vblank = &avivo_wait_for_vblank, 624 .set_backlight_level = &atombios_set_backlight_level, 625 .get_backlight_level = &atombios_get_backlight_level, 626 .hdmi_enable = &r600_hdmi_enable, 627 .hdmi_setmode = &r600_hdmi_setmode, 628 }, 629 .copy = { 630 .blit = &r100_copy_blit, 631 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 632 .dma = &r200_copy_dma, 633 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 634 .copy = &r100_copy_blit, 635 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 636 }, 637 .surface = { 638 .set_reg = r100_set_surface_reg, 639 .clear_reg = r100_clear_surface_reg, 640 }, 641 .hpd = { 642 .init = &rs600_hpd_init, 643 .fini = &rs600_hpd_fini, 644 .sense = &rs600_hpd_sense, 645 .set_polarity = &rs600_hpd_set_polarity, 646 }, 647 .pm = { 648 .misc = &rs600_pm_misc, 649 .prepare = &rs600_pm_prepare, 650 .finish = &rs600_pm_finish, 651 .init_profile = &r420_pm_init_profile, 652 .get_dynpm_state = &r100_pm_get_dynpm_state, 653 .get_engine_clock = &radeon_atom_get_engine_clock, 654 .set_engine_clock = &radeon_atom_set_engine_clock, 655 .get_memory_clock = &radeon_atom_get_memory_clock, 656 .set_memory_clock = &radeon_atom_set_memory_clock, 657 .get_pcie_lanes = NULL, 658 .set_pcie_lanes = NULL, 659 .set_clock_gating = &radeon_atom_set_clock_gating, 660 }, 661 .pflip = { 662 .page_flip = &rs600_page_flip, 663 .page_flip_pending = &rs600_page_flip_pending, 664 }, 665 }; 666 667 static struct radeon_asic rs690_asic = { 668 .init = &rs690_init, 669 .fini = &rs690_fini, 670 .suspend = &rs690_suspend, 671 .resume = &rs690_resume, 672 .vga_set_state = &r100_vga_set_state, 673 .asic_reset = &rs600_asic_reset, 674 .mmio_hdp_flush = NULL, 675 .gui_idle = &r100_gui_idle, 676 .mc_wait_for_idle = &rs690_mc_wait_for_idle, 677 .gart = { 678 .tlb_flush = &rs400_gart_tlb_flush, 679 .set_page = &rs400_gart_set_page, 680 }, 681 .ring = { 682 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 683 }, 684 .irq = { 685 .set = &rs600_irq_set, 686 .process = &rs600_irq_process, 687 }, 688 .display = { 689 .get_vblank_counter = &rs600_get_vblank_counter, 690 .bandwidth_update = &rs690_bandwidth_update, 691 .wait_for_vblank = &avivo_wait_for_vblank, 692 .set_backlight_level = &atombios_set_backlight_level, 693 .get_backlight_level = &atombios_get_backlight_level, 694 .hdmi_enable = &r600_hdmi_enable, 695 .hdmi_setmode = &r600_hdmi_setmode, 696 }, 697 .copy = { 698 .blit = &r100_copy_blit, 699 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 700 .dma = &r200_copy_dma, 701 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 702 .copy = &r200_copy_dma, 703 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 704 }, 705 .surface = { 706 .set_reg = r100_set_surface_reg, 707 .clear_reg = r100_clear_surface_reg, 708 }, 709 .hpd = { 710 .init = &rs600_hpd_init, 711 .fini = &rs600_hpd_fini, 712 .sense = &rs600_hpd_sense, 713 .set_polarity = &rs600_hpd_set_polarity, 714 }, 715 .pm = { 716 .misc = &rs600_pm_misc, 717 .prepare = &rs600_pm_prepare, 718 .finish = &rs600_pm_finish, 719 .init_profile = &r420_pm_init_profile, 720 .get_dynpm_state = &r100_pm_get_dynpm_state, 721 .get_engine_clock = &radeon_atom_get_engine_clock, 722 .set_engine_clock = &radeon_atom_set_engine_clock, 723 .get_memory_clock = &radeon_atom_get_memory_clock, 724 .set_memory_clock = &radeon_atom_set_memory_clock, 725 .get_pcie_lanes = NULL, 726 .set_pcie_lanes = NULL, 727 .set_clock_gating = &radeon_atom_set_clock_gating, 728 }, 729 .pflip = { 730 .page_flip = &rs600_page_flip, 731 .page_flip_pending = &rs600_page_flip_pending, 732 }, 733 }; 734 735 static struct radeon_asic rv515_asic = { 736 .init = &rv515_init, 737 .fini = &rv515_fini, 738 .suspend = &rv515_suspend, 739 .resume = &rv515_resume, 740 .vga_set_state = &r100_vga_set_state, 741 .asic_reset = &rs600_asic_reset, 742 .mmio_hdp_flush = NULL, 743 .gui_idle = &r100_gui_idle, 744 .mc_wait_for_idle = &rv515_mc_wait_for_idle, 745 .gart = { 746 .tlb_flush = &rv370_pcie_gart_tlb_flush, 747 .set_page = &rv370_pcie_gart_set_page, 748 }, 749 .ring = { 750 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 751 }, 752 .irq = { 753 .set = &rs600_irq_set, 754 .process = &rs600_irq_process, 755 }, 756 .display = { 757 .get_vblank_counter = &rs600_get_vblank_counter, 758 .bandwidth_update = &rv515_bandwidth_update, 759 .wait_for_vblank = &avivo_wait_for_vblank, 760 .set_backlight_level = &atombios_set_backlight_level, 761 .get_backlight_level = &atombios_get_backlight_level, 762 }, 763 .copy = { 764 .blit = &r100_copy_blit, 765 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 766 .dma = &r200_copy_dma, 767 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 768 .copy = &r100_copy_blit, 769 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 770 }, 771 .surface = { 772 .set_reg = r100_set_surface_reg, 773 .clear_reg = r100_clear_surface_reg, 774 }, 775 .hpd = { 776 .init = &rs600_hpd_init, 777 .fini = &rs600_hpd_fini, 778 .sense = &rs600_hpd_sense, 779 .set_polarity = &rs600_hpd_set_polarity, 780 }, 781 .pm = { 782 .misc = &rs600_pm_misc, 783 .prepare = &rs600_pm_prepare, 784 .finish = &rs600_pm_finish, 785 .init_profile = &r420_pm_init_profile, 786 .get_dynpm_state = &r100_pm_get_dynpm_state, 787 .get_engine_clock = &radeon_atom_get_engine_clock, 788 .set_engine_clock = &radeon_atom_set_engine_clock, 789 .get_memory_clock = &radeon_atom_get_memory_clock, 790 .set_memory_clock = &radeon_atom_set_memory_clock, 791 .get_pcie_lanes = &rv370_get_pcie_lanes, 792 .set_pcie_lanes = &rv370_set_pcie_lanes, 793 .set_clock_gating = &radeon_atom_set_clock_gating, 794 }, 795 .pflip = { 796 .page_flip = &rs600_page_flip, 797 .page_flip_pending = &rs600_page_flip_pending, 798 }, 799 }; 800 801 static struct radeon_asic r520_asic = { 802 .init = &r520_init, 803 .fini = &rv515_fini, 804 .suspend = &rv515_suspend, 805 .resume = &r520_resume, 806 .vga_set_state = &r100_vga_set_state, 807 .asic_reset = &rs600_asic_reset, 808 .mmio_hdp_flush = NULL, 809 .gui_idle = &r100_gui_idle, 810 .mc_wait_for_idle = &r520_mc_wait_for_idle, 811 .gart = { 812 .tlb_flush = &rv370_pcie_gart_tlb_flush, 813 .set_page = &rv370_pcie_gart_set_page, 814 }, 815 .ring = { 816 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring 817 }, 818 .irq = { 819 .set = &rs600_irq_set, 820 .process = &rs600_irq_process, 821 }, 822 .display = { 823 .bandwidth_update = &rv515_bandwidth_update, 824 .get_vblank_counter = &rs600_get_vblank_counter, 825 .wait_for_vblank = &avivo_wait_for_vblank, 826 .set_backlight_level = &atombios_set_backlight_level, 827 .get_backlight_level = &atombios_get_backlight_level, 828 }, 829 .copy = { 830 .blit = &r100_copy_blit, 831 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 832 .dma = &r200_copy_dma, 833 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, 834 .copy = &r100_copy_blit, 835 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 836 }, 837 .surface = { 838 .set_reg = r100_set_surface_reg, 839 .clear_reg = r100_clear_surface_reg, 840 }, 841 .hpd = { 842 .init = &rs600_hpd_init, 843 .fini = &rs600_hpd_fini, 844 .sense = &rs600_hpd_sense, 845 .set_polarity = &rs600_hpd_set_polarity, 846 }, 847 .pm = { 848 .misc = &rs600_pm_misc, 849 .prepare = &rs600_pm_prepare, 850 .finish = &rs600_pm_finish, 851 .init_profile = &r420_pm_init_profile, 852 .get_dynpm_state = &r100_pm_get_dynpm_state, 853 .get_engine_clock = &radeon_atom_get_engine_clock, 854 .set_engine_clock = &radeon_atom_set_engine_clock, 855 .get_memory_clock = &radeon_atom_get_memory_clock, 856 .set_memory_clock = &radeon_atom_set_memory_clock, 857 .get_pcie_lanes = &rv370_get_pcie_lanes, 858 .set_pcie_lanes = &rv370_set_pcie_lanes, 859 .set_clock_gating = &radeon_atom_set_clock_gating, 860 }, 861 .pflip = { 862 .page_flip = &rs600_page_flip, 863 .page_flip_pending = &rs600_page_flip_pending, 864 }, 865 }; 866 867 static struct radeon_asic_ring r600_gfx_ring = { 868 .ib_execute = &r600_ring_ib_execute, 869 .emit_fence = &r600_fence_ring_emit, 870 .emit_semaphore = &r600_semaphore_ring_emit, 871 .cs_parse = &r600_cs_parse, 872 .ring_test = &r600_ring_test, 873 .ib_test = &r600_ib_test, 874 .is_lockup = &r600_gfx_is_lockup, 875 .get_rptr = &r600_gfx_get_rptr, 876 .get_wptr = &r600_gfx_get_wptr, 877 .set_wptr = &r600_gfx_set_wptr, 878 }; 879 880 static struct radeon_asic_ring r600_dma_ring = { 881 .ib_execute = &r600_dma_ring_ib_execute, 882 .emit_fence = &r600_dma_fence_ring_emit, 883 .emit_semaphore = &r600_dma_semaphore_ring_emit, 884 .cs_parse = &r600_dma_cs_parse, 885 .ring_test = &r600_dma_ring_test, 886 .ib_test = &r600_dma_ib_test, 887 .is_lockup = &r600_dma_is_lockup, 888 .get_rptr = &r600_dma_get_rptr, 889 .get_wptr = &r600_dma_get_wptr, 890 .set_wptr = &r600_dma_set_wptr, 891 }; 892 893 static struct radeon_asic r600_asic = { 894 .init = &r600_init, 895 .fini = &r600_fini, 896 .suspend = &r600_suspend, 897 .resume = &r600_resume, 898 .vga_set_state = &r600_vga_set_state, 899 .asic_reset = &r600_asic_reset, 900 .mmio_hdp_flush = r600_mmio_hdp_flush, 901 .gui_idle = &r600_gui_idle, 902 .mc_wait_for_idle = &r600_mc_wait_for_idle, 903 .get_xclk = &r600_get_xclk, 904 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 905 .gart = { 906 .tlb_flush = &r600_pcie_gart_tlb_flush, 907 .set_page = &rs600_gart_set_page, 908 }, 909 .ring = { 910 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 911 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 912 }, 913 .irq = { 914 .set = &r600_irq_set, 915 .process = &r600_irq_process, 916 }, 917 .display = { 918 .bandwidth_update = &rv515_bandwidth_update, 919 .get_vblank_counter = &rs600_get_vblank_counter, 920 .wait_for_vblank = &avivo_wait_for_vblank, 921 .set_backlight_level = &atombios_set_backlight_level, 922 .get_backlight_level = &atombios_get_backlight_level, 923 .hdmi_enable = &r600_hdmi_enable, 924 .hdmi_setmode = &r600_hdmi_setmode, 925 }, 926 .copy = { 927 .blit = &r600_copy_cpdma, 928 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 929 .dma = &r600_copy_dma, 930 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 931 .copy = &r600_copy_cpdma, 932 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 933 }, 934 .surface = { 935 .set_reg = r600_set_surface_reg, 936 .clear_reg = r600_clear_surface_reg, 937 }, 938 .hpd = { 939 .init = &r600_hpd_init, 940 .fini = &r600_hpd_fini, 941 .sense = &r600_hpd_sense, 942 .set_polarity = &r600_hpd_set_polarity, 943 }, 944 .pm = { 945 .misc = &r600_pm_misc, 946 .prepare = &rs600_pm_prepare, 947 .finish = &rs600_pm_finish, 948 .init_profile = &r600_pm_init_profile, 949 .get_dynpm_state = &r600_pm_get_dynpm_state, 950 .get_engine_clock = &radeon_atom_get_engine_clock, 951 .set_engine_clock = &radeon_atom_set_engine_clock, 952 .get_memory_clock = &radeon_atom_get_memory_clock, 953 .set_memory_clock = &radeon_atom_set_memory_clock, 954 .get_pcie_lanes = &r600_get_pcie_lanes, 955 .set_pcie_lanes = &r600_set_pcie_lanes, 956 .set_clock_gating = NULL, 957 .get_temperature = &rv6xx_get_temp, 958 }, 959 .pflip = { 960 .page_flip = &rs600_page_flip, 961 .page_flip_pending = &rs600_page_flip_pending, 962 }, 963 }; 964 965 static struct radeon_asic rv6xx_asic = { 966 .init = &r600_init, 967 .fini = &r600_fini, 968 .suspend = &r600_suspend, 969 .resume = &r600_resume, 970 .vga_set_state = &r600_vga_set_state, 971 .asic_reset = &r600_asic_reset, 972 .mmio_hdp_flush = r600_mmio_hdp_flush, 973 .gui_idle = &r600_gui_idle, 974 .mc_wait_for_idle = &r600_mc_wait_for_idle, 975 .get_xclk = &r600_get_xclk, 976 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 977 .gart = { 978 .tlb_flush = &r600_pcie_gart_tlb_flush, 979 .set_page = &rs600_gart_set_page, 980 }, 981 .ring = { 982 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 983 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 984 }, 985 .irq = { 986 .set = &r600_irq_set, 987 .process = &r600_irq_process, 988 }, 989 .display = { 990 .bandwidth_update = &rv515_bandwidth_update, 991 .get_vblank_counter = &rs600_get_vblank_counter, 992 .wait_for_vblank = &avivo_wait_for_vblank, 993 .set_backlight_level = &atombios_set_backlight_level, 994 .get_backlight_level = &atombios_get_backlight_level, 995 .hdmi_enable = &r600_hdmi_enable, 996 .hdmi_setmode = &r600_hdmi_setmode, 997 }, 998 .copy = { 999 .blit = &r600_copy_cpdma, 1000 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1001 .dma = &r600_copy_dma, 1002 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1003 .copy = &r600_copy_cpdma, 1004 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1005 }, 1006 .surface = { 1007 .set_reg = r600_set_surface_reg, 1008 .clear_reg = r600_clear_surface_reg, 1009 }, 1010 .hpd = { 1011 .init = &r600_hpd_init, 1012 .fini = &r600_hpd_fini, 1013 .sense = &r600_hpd_sense, 1014 .set_polarity = &r600_hpd_set_polarity, 1015 }, 1016 .pm = { 1017 .misc = &r600_pm_misc, 1018 .prepare = &rs600_pm_prepare, 1019 .finish = &rs600_pm_finish, 1020 .init_profile = &r600_pm_init_profile, 1021 .get_dynpm_state = &r600_pm_get_dynpm_state, 1022 .get_engine_clock = &radeon_atom_get_engine_clock, 1023 .set_engine_clock = &radeon_atom_set_engine_clock, 1024 .get_memory_clock = &radeon_atom_get_memory_clock, 1025 .set_memory_clock = &radeon_atom_set_memory_clock, 1026 .get_pcie_lanes = &r600_get_pcie_lanes, 1027 .set_pcie_lanes = &r600_set_pcie_lanes, 1028 .set_clock_gating = NULL, 1029 .get_temperature = &rv6xx_get_temp, 1030 .set_uvd_clocks = &r600_set_uvd_clocks, 1031 }, 1032 .dpm = { 1033 .init = &rv6xx_dpm_init, 1034 .setup_asic = &rv6xx_setup_asic, 1035 .enable = &rv6xx_dpm_enable, 1036 .late_enable = &r600_dpm_late_enable, 1037 .disable = &rv6xx_dpm_disable, 1038 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1039 .set_power_state = &rv6xx_dpm_set_power_state, 1040 .post_set_power_state = &r600_dpm_post_set_power_state, 1041 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed, 1042 .fini = &rv6xx_dpm_fini, 1043 .get_sclk = &rv6xx_dpm_get_sclk, 1044 .get_mclk = &rv6xx_dpm_get_mclk, 1045 .print_power_state = &rv6xx_dpm_print_power_state, 1046 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level, 1047 .force_performance_level = &rv6xx_dpm_force_performance_level, 1048 }, 1049 .pflip = { 1050 .page_flip = &rs600_page_flip, 1051 .page_flip_pending = &rs600_page_flip_pending, 1052 }, 1053 }; 1054 1055 static struct radeon_asic rs780_asic = { 1056 .init = &r600_init, 1057 .fini = &r600_fini, 1058 .suspend = &r600_suspend, 1059 .resume = &r600_resume, 1060 .vga_set_state = &r600_vga_set_state, 1061 .asic_reset = &r600_asic_reset, 1062 .mmio_hdp_flush = r600_mmio_hdp_flush, 1063 .gui_idle = &r600_gui_idle, 1064 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1065 .get_xclk = &r600_get_xclk, 1066 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1067 .gart = { 1068 .tlb_flush = &r600_pcie_gart_tlb_flush, 1069 .set_page = &rs600_gart_set_page, 1070 }, 1071 .ring = { 1072 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 1073 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 1074 }, 1075 .irq = { 1076 .set = &r600_irq_set, 1077 .process = &r600_irq_process, 1078 }, 1079 .display = { 1080 .bandwidth_update = &rs690_bandwidth_update, 1081 .get_vblank_counter = &rs600_get_vblank_counter, 1082 .wait_for_vblank = &avivo_wait_for_vblank, 1083 .set_backlight_level = &atombios_set_backlight_level, 1084 .get_backlight_level = &atombios_get_backlight_level, 1085 .hdmi_enable = &r600_hdmi_enable, 1086 .hdmi_setmode = &r600_hdmi_setmode, 1087 }, 1088 .copy = { 1089 .blit = &r600_copy_cpdma, 1090 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1091 .dma = &r600_copy_dma, 1092 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1093 .copy = &r600_copy_cpdma, 1094 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1095 }, 1096 .surface = { 1097 .set_reg = r600_set_surface_reg, 1098 .clear_reg = r600_clear_surface_reg, 1099 }, 1100 .hpd = { 1101 .init = &r600_hpd_init, 1102 .fini = &r600_hpd_fini, 1103 .sense = &r600_hpd_sense, 1104 .set_polarity = &r600_hpd_set_polarity, 1105 }, 1106 .pm = { 1107 .misc = &r600_pm_misc, 1108 .prepare = &rs600_pm_prepare, 1109 .finish = &rs600_pm_finish, 1110 .init_profile = &rs780_pm_init_profile, 1111 .get_dynpm_state = &r600_pm_get_dynpm_state, 1112 .get_engine_clock = &radeon_atom_get_engine_clock, 1113 .set_engine_clock = &radeon_atom_set_engine_clock, 1114 .get_memory_clock = NULL, 1115 .set_memory_clock = NULL, 1116 .get_pcie_lanes = NULL, 1117 .set_pcie_lanes = NULL, 1118 .set_clock_gating = NULL, 1119 .get_temperature = &rv6xx_get_temp, 1120 .set_uvd_clocks = &r600_set_uvd_clocks, 1121 }, 1122 .dpm = { 1123 .init = &rs780_dpm_init, 1124 .setup_asic = &rs780_dpm_setup_asic, 1125 .enable = &rs780_dpm_enable, 1126 .late_enable = &r600_dpm_late_enable, 1127 .disable = &rs780_dpm_disable, 1128 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1129 .set_power_state = &rs780_dpm_set_power_state, 1130 .post_set_power_state = &r600_dpm_post_set_power_state, 1131 .display_configuration_changed = &rs780_dpm_display_configuration_changed, 1132 .fini = &rs780_dpm_fini, 1133 .get_sclk = &rs780_dpm_get_sclk, 1134 .get_mclk = &rs780_dpm_get_mclk, 1135 .print_power_state = &rs780_dpm_print_power_state, 1136 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level, 1137 .force_performance_level = &rs780_dpm_force_performance_level, 1138 }, 1139 .pflip = { 1140 .page_flip = &rs600_page_flip, 1141 .page_flip_pending = &rs600_page_flip_pending, 1142 }, 1143 }; 1144 1145 static struct radeon_asic_ring rv770_uvd_ring = { 1146 .ib_execute = &uvd_v1_0_ib_execute, 1147 .emit_fence = &uvd_v2_2_fence_emit, 1148 .emit_semaphore = &uvd_v1_0_semaphore_emit, 1149 .cs_parse = &radeon_uvd_cs_parse, 1150 .ring_test = &uvd_v1_0_ring_test, 1151 .ib_test = &uvd_v1_0_ib_test, 1152 .is_lockup = &radeon_ring_test_lockup, 1153 .get_rptr = &uvd_v1_0_get_rptr, 1154 .get_wptr = &uvd_v1_0_get_wptr, 1155 .set_wptr = &uvd_v1_0_set_wptr, 1156 }; 1157 1158 static struct radeon_asic rv770_asic = { 1159 .init = &rv770_init, 1160 .fini = &rv770_fini, 1161 .suspend = &rv770_suspend, 1162 .resume = &rv770_resume, 1163 .asic_reset = &r600_asic_reset, 1164 .vga_set_state = &r600_vga_set_state, 1165 .mmio_hdp_flush = r600_mmio_hdp_flush, 1166 .gui_idle = &r600_gui_idle, 1167 .mc_wait_for_idle = &r600_mc_wait_for_idle, 1168 .get_xclk = &rv770_get_xclk, 1169 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1170 .gart = { 1171 .tlb_flush = &r600_pcie_gart_tlb_flush, 1172 .set_page = &rs600_gart_set_page, 1173 }, 1174 .ring = { 1175 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, 1176 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, 1177 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1178 }, 1179 .irq = { 1180 .set = &r600_irq_set, 1181 .process = &r600_irq_process, 1182 }, 1183 .display = { 1184 .bandwidth_update = &rv515_bandwidth_update, 1185 .get_vblank_counter = &rs600_get_vblank_counter, 1186 .wait_for_vblank = &avivo_wait_for_vblank, 1187 .set_backlight_level = &atombios_set_backlight_level, 1188 .get_backlight_level = &atombios_get_backlight_level, 1189 .hdmi_enable = &r600_hdmi_enable, 1190 .hdmi_setmode = &dce3_1_hdmi_setmode, 1191 }, 1192 .copy = { 1193 .blit = &r600_copy_cpdma, 1194 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1195 .dma = &rv770_copy_dma, 1196 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1197 .copy = &rv770_copy_dma, 1198 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1199 }, 1200 .surface = { 1201 .set_reg = r600_set_surface_reg, 1202 .clear_reg = r600_clear_surface_reg, 1203 }, 1204 .hpd = { 1205 .init = &r600_hpd_init, 1206 .fini = &r600_hpd_fini, 1207 .sense = &r600_hpd_sense, 1208 .set_polarity = &r600_hpd_set_polarity, 1209 }, 1210 .pm = { 1211 .misc = &rv770_pm_misc, 1212 .prepare = &rs600_pm_prepare, 1213 .finish = &rs600_pm_finish, 1214 .init_profile = &r600_pm_init_profile, 1215 .get_dynpm_state = &r600_pm_get_dynpm_state, 1216 .get_engine_clock = &radeon_atom_get_engine_clock, 1217 .set_engine_clock = &radeon_atom_set_engine_clock, 1218 .get_memory_clock = &radeon_atom_get_memory_clock, 1219 .set_memory_clock = &radeon_atom_set_memory_clock, 1220 .get_pcie_lanes = &r600_get_pcie_lanes, 1221 .set_pcie_lanes = &r600_set_pcie_lanes, 1222 .set_clock_gating = &radeon_atom_set_clock_gating, 1223 .set_uvd_clocks = &rv770_set_uvd_clocks, 1224 .get_temperature = &rv770_get_temp, 1225 }, 1226 .dpm = { 1227 .init = &rv770_dpm_init, 1228 .setup_asic = &rv770_dpm_setup_asic, 1229 .enable = &rv770_dpm_enable, 1230 .late_enable = &rv770_dpm_late_enable, 1231 .disable = &rv770_dpm_disable, 1232 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1233 .set_power_state = &rv770_dpm_set_power_state, 1234 .post_set_power_state = &r600_dpm_post_set_power_state, 1235 .display_configuration_changed = &rv770_dpm_display_configuration_changed, 1236 .fini = &rv770_dpm_fini, 1237 .get_sclk = &rv770_dpm_get_sclk, 1238 .get_mclk = &rv770_dpm_get_mclk, 1239 .print_power_state = &rv770_dpm_print_power_state, 1240 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, 1241 .force_performance_level = &rv770_dpm_force_performance_level, 1242 .vblank_too_short = &rv770_dpm_vblank_too_short, 1243 }, 1244 .pflip = { 1245 .page_flip = &rv770_page_flip, 1246 .page_flip_pending = &rv770_page_flip_pending, 1247 }, 1248 }; 1249 1250 static struct radeon_asic_ring evergreen_gfx_ring = { 1251 .ib_execute = &evergreen_ring_ib_execute, 1252 .emit_fence = &r600_fence_ring_emit, 1253 .emit_semaphore = &r600_semaphore_ring_emit, 1254 .cs_parse = &evergreen_cs_parse, 1255 .ring_test = &r600_ring_test, 1256 .ib_test = &r600_ib_test, 1257 .is_lockup = &evergreen_gfx_is_lockup, 1258 .get_rptr = &r600_gfx_get_rptr, 1259 .get_wptr = &r600_gfx_get_wptr, 1260 .set_wptr = &r600_gfx_set_wptr, 1261 }; 1262 1263 static struct radeon_asic_ring evergreen_dma_ring = { 1264 .ib_execute = &evergreen_dma_ring_ib_execute, 1265 .emit_fence = &evergreen_dma_fence_ring_emit, 1266 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1267 .cs_parse = &evergreen_dma_cs_parse, 1268 .ring_test = &r600_dma_ring_test, 1269 .ib_test = &r600_dma_ib_test, 1270 .is_lockup = &evergreen_dma_is_lockup, 1271 .get_rptr = &r600_dma_get_rptr, 1272 .get_wptr = &r600_dma_get_wptr, 1273 .set_wptr = &r600_dma_set_wptr, 1274 }; 1275 1276 static struct radeon_asic evergreen_asic = { 1277 .init = &evergreen_init, 1278 .fini = &evergreen_fini, 1279 .suspend = &evergreen_suspend, 1280 .resume = &evergreen_resume, 1281 .asic_reset = &evergreen_asic_reset, 1282 .vga_set_state = &r600_vga_set_state, 1283 .mmio_hdp_flush = r600_mmio_hdp_flush, 1284 .gui_idle = &r600_gui_idle, 1285 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1286 .get_xclk = &rv770_get_xclk, 1287 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1288 .gart = { 1289 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1290 .set_page = &rs600_gart_set_page, 1291 }, 1292 .ring = { 1293 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1294 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1295 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1296 }, 1297 .irq = { 1298 .set = &evergreen_irq_set, 1299 .process = &evergreen_irq_process, 1300 }, 1301 .display = { 1302 .bandwidth_update = &evergreen_bandwidth_update, 1303 .get_vblank_counter = &evergreen_get_vblank_counter, 1304 .wait_for_vblank = &dce4_wait_for_vblank, 1305 .set_backlight_level = &atombios_set_backlight_level, 1306 .get_backlight_level = &atombios_get_backlight_level, 1307 .hdmi_enable = &evergreen_hdmi_enable, 1308 .hdmi_setmode = &evergreen_hdmi_setmode, 1309 }, 1310 .copy = { 1311 .blit = &r600_copy_cpdma, 1312 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1313 .dma = &evergreen_copy_dma, 1314 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1315 .copy = &evergreen_copy_dma, 1316 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1317 }, 1318 .surface = { 1319 .set_reg = r600_set_surface_reg, 1320 .clear_reg = r600_clear_surface_reg, 1321 }, 1322 .hpd = { 1323 .init = &evergreen_hpd_init, 1324 .fini = &evergreen_hpd_fini, 1325 .sense = &evergreen_hpd_sense, 1326 .set_polarity = &evergreen_hpd_set_polarity, 1327 }, 1328 .pm = { 1329 .misc = &evergreen_pm_misc, 1330 .prepare = &evergreen_pm_prepare, 1331 .finish = &evergreen_pm_finish, 1332 .init_profile = &r600_pm_init_profile, 1333 .get_dynpm_state = &r600_pm_get_dynpm_state, 1334 .get_engine_clock = &radeon_atom_get_engine_clock, 1335 .set_engine_clock = &radeon_atom_set_engine_clock, 1336 .get_memory_clock = &radeon_atom_get_memory_clock, 1337 .set_memory_clock = &radeon_atom_set_memory_clock, 1338 .get_pcie_lanes = &r600_get_pcie_lanes, 1339 .set_pcie_lanes = &r600_set_pcie_lanes, 1340 .set_clock_gating = NULL, 1341 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1342 .get_temperature = &evergreen_get_temp, 1343 }, 1344 .dpm = { 1345 .init = &cypress_dpm_init, 1346 .setup_asic = &cypress_dpm_setup_asic, 1347 .enable = &cypress_dpm_enable, 1348 .late_enable = &rv770_dpm_late_enable, 1349 .disable = &cypress_dpm_disable, 1350 .pre_set_power_state = &r600_dpm_pre_set_power_state, 1351 .set_power_state = &cypress_dpm_set_power_state, 1352 .post_set_power_state = &r600_dpm_post_set_power_state, 1353 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1354 .fini = &cypress_dpm_fini, 1355 .get_sclk = &rv770_dpm_get_sclk, 1356 .get_mclk = &rv770_dpm_get_mclk, 1357 .print_power_state = &rv770_dpm_print_power_state, 1358 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, 1359 .force_performance_level = &rv770_dpm_force_performance_level, 1360 .vblank_too_short = &cypress_dpm_vblank_too_short, 1361 }, 1362 .pflip = { 1363 .page_flip = &evergreen_page_flip, 1364 .page_flip_pending = &evergreen_page_flip_pending, 1365 }, 1366 }; 1367 1368 static struct radeon_asic sumo_asic = { 1369 .init = &evergreen_init, 1370 .fini = &evergreen_fini, 1371 .suspend = &evergreen_suspend, 1372 .resume = &evergreen_resume, 1373 .asic_reset = &evergreen_asic_reset, 1374 .vga_set_state = &r600_vga_set_state, 1375 .mmio_hdp_flush = r600_mmio_hdp_flush, 1376 .gui_idle = &r600_gui_idle, 1377 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1378 .get_xclk = &r600_get_xclk, 1379 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1380 .gart = { 1381 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1382 .set_page = &rs600_gart_set_page, 1383 }, 1384 .ring = { 1385 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1386 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1387 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1388 }, 1389 .irq = { 1390 .set = &evergreen_irq_set, 1391 .process = &evergreen_irq_process, 1392 }, 1393 .display = { 1394 .bandwidth_update = &evergreen_bandwidth_update, 1395 .get_vblank_counter = &evergreen_get_vblank_counter, 1396 .wait_for_vblank = &dce4_wait_for_vblank, 1397 .set_backlight_level = &atombios_set_backlight_level, 1398 .get_backlight_level = &atombios_get_backlight_level, 1399 .hdmi_enable = &evergreen_hdmi_enable, 1400 .hdmi_setmode = &evergreen_hdmi_setmode, 1401 }, 1402 .copy = { 1403 .blit = &r600_copy_cpdma, 1404 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1405 .dma = &evergreen_copy_dma, 1406 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1407 .copy = &evergreen_copy_dma, 1408 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1409 }, 1410 .surface = { 1411 .set_reg = r600_set_surface_reg, 1412 .clear_reg = r600_clear_surface_reg, 1413 }, 1414 .hpd = { 1415 .init = &evergreen_hpd_init, 1416 .fini = &evergreen_hpd_fini, 1417 .sense = &evergreen_hpd_sense, 1418 .set_polarity = &evergreen_hpd_set_polarity, 1419 }, 1420 .pm = { 1421 .misc = &evergreen_pm_misc, 1422 .prepare = &evergreen_pm_prepare, 1423 .finish = &evergreen_pm_finish, 1424 .init_profile = &sumo_pm_init_profile, 1425 .get_dynpm_state = &r600_pm_get_dynpm_state, 1426 .get_engine_clock = &radeon_atom_get_engine_clock, 1427 .set_engine_clock = &radeon_atom_set_engine_clock, 1428 .get_memory_clock = NULL, 1429 .set_memory_clock = NULL, 1430 .get_pcie_lanes = NULL, 1431 .set_pcie_lanes = NULL, 1432 .set_clock_gating = NULL, 1433 .set_uvd_clocks = &sumo_set_uvd_clocks, 1434 .get_temperature = &sumo_get_temp, 1435 }, 1436 .dpm = { 1437 .init = &sumo_dpm_init, 1438 .setup_asic = &sumo_dpm_setup_asic, 1439 .enable = &sumo_dpm_enable, 1440 .late_enable = &sumo_dpm_late_enable, 1441 .disable = &sumo_dpm_disable, 1442 .pre_set_power_state = &sumo_dpm_pre_set_power_state, 1443 .set_power_state = &sumo_dpm_set_power_state, 1444 .post_set_power_state = &sumo_dpm_post_set_power_state, 1445 .display_configuration_changed = &sumo_dpm_display_configuration_changed, 1446 .fini = &sumo_dpm_fini, 1447 .get_sclk = &sumo_dpm_get_sclk, 1448 .get_mclk = &sumo_dpm_get_mclk, 1449 .print_power_state = &sumo_dpm_print_power_state, 1450 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level, 1451 .force_performance_level = &sumo_dpm_force_performance_level, 1452 }, 1453 .pflip = { 1454 .page_flip = &evergreen_page_flip, 1455 .page_flip_pending = &evergreen_page_flip_pending, 1456 }, 1457 }; 1458 1459 static struct radeon_asic btc_asic = { 1460 .init = &evergreen_init, 1461 .fini = &evergreen_fini, 1462 .suspend = &evergreen_suspend, 1463 .resume = &evergreen_resume, 1464 .asic_reset = &evergreen_asic_reset, 1465 .vga_set_state = &r600_vga_set_state, 1466 .mmio_hdp_flush = r600_mmio_hdp_flush, 1467 .gui_idle = &r600_gui_idle, 1468 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1469 .get_xclk = &rv770_get_xclk, 1470 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1471 .gart = { 1472 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1473 .set_page = &rs600_gart_set_page, 1474 }, 1475 .ring = { 1476 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, 1477 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, 1478 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, 1479 }, 1480 .irq = { 1481 .set = &evergreen_irq_set, 1482 .process = &evergreen_irq_process, 1483 }, 1484 .display = { 1485 .bandwidth_update = &evergreen_bandwidth_update, 1486 .get_vblank_counter = &evergreen_get_vblank_counter, 1487 .wait_for_vblank = &dce4_wait_for_vblank, 1488 .set_backlight_level = &atombios_set_backlight_level, 1489 .get_backlight_level = &atombios_get_backlight_level, 1490 .hdmi_enable = &evergreen_hdmi_enable, 1491 .hdmi_setmode = &evergreen_hdmi_setmode, 1492 }, 1493 .copy = { 1494 .blit = &r600_copy_cpdma, 1495 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1496 .dma = &evergreen_copy_dma, 1497 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1498 .copy = &evergreen_copy_dma, 1499 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1500 }, 1501 .surface = { 1502 .set_reg = r600_set_surface_reg, 1503 .clear_reg = r600_clear_surface_reg, 1504 }, 1505 .hpd = { 1506 .init = &evergreen_hpd_init, 1507 .fini = &evergreen_hpd_fini, 1508 .sense = &evergreen_hpd_sense, 1509 .set_polarity = &evergreen_hpd_set_polarity, 1510 }, 1511 .pm = { 1512 .misc = &evergreen_pm_misc, 1513 .prepare = &evergreen_pm_prepare, 1514 .finish = &evergreen_pm_finish, 1515 .init_profile = &btc_pm_init_profile, 1516 .get_dynpm_state = &r600_pm_get_dynpm_state, 1517 .get_engine_clock = &radeon_atom_get_engine_clock, 1518 .set_engine_clock = &radeon_atom_set_engine_clock, 1519 .get_memory_clock = &radeon_atom_get_memory_clock, 1520 .set_memory_clock = &radeon_atom_set_memory_clock, 1521 .get_pcie_lanes = &r600_get_pcie_lanes, 1522 .set_pcie_lanes = &r600_set_pcie_lanes, 1523 .set_clock_gating = NULL, 1524 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1525 .get_temperature = &evergreen_get_temp, 1526 }, 1527 .dpm = { 1528 .init = &btc_dpm_init, 1529 .setup_asic = &btc_dpm_setup_asic, 1530 .enable = &btc_dpm_enable, 1531 .late_enable = &rv770_dpm_late_enable, 1532 .disable = &btc_dpm_disable, 1533 .pre_set_power_state = &btc_dpm_pre_set_power_state, 1534 .set_power_state = &btc_dpm_set_power_state, 1535 .post_set_power_state = &btc_dpm_post_set_power_state, 1536 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1537 .fini = &btc_dpm_fini, 1538 .get_sclk = &btc_dpm_get_sclk, 1539 .get_mclk = &btc_dpm_get_mclk, 1540 .print_power_state = &rv770_dpm_print_power_state, 1541 .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level, 1542 .force_performance_level = &rv770_dpm_force_performance_level, 1543 .vblank_too_short = &btc_dpm_vblank_too_short, 1544 }, 1545 .pflip = { 1546 .page_flip = &evergreen_page_flip, 1547 .page_flip_pending = &evergreen_page_flip_pending, 1548 }, 1549 }; 1550 1551 static struct radeon_asic_ring cayman_gfx_ring = { 1552 .ib_execute = &cayman_ring_ib_execute, 1553 .ib_parse = &evergreen_ib_parse, 1554 .emit_fence = &cayman_fence_ring_emit, 1555 .emit_semaphore = &r600_semaphore_ring_emit, 1556 .cs_parse = &evergreen_cs_parse, 1557 .ring_test = &r600_ring_test, 1558 .ib_test = &r600_ib_test, 1559 .is_lockup = &cayman_gfx_is_lockup, 1560 .vm_flush = &cayman_vm_flush, 1561 .get_rptr = &cayman_gfx_get_rptr, 1562 .get_wptr = &cayman_gfx_get_wptr, 1563 .set_wptr = &cayman_gfx_set_wptr, 1564 }; 1565 1566 static struct radeon_asic_ring cayman_dma_ring = { 1567 .ib_execute = &cayman_dma_ring_ib_execute, 1568 .ib_parse = &evergreen_dma_ib_parse, 1569 .emit_fence = &evergreen_dma_fence_ring_emit, 1570 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1571 .cs_parse = &evergreen_dma_cs_parse, 1572 .ring_test = &r600_dma_ring_test, 1573 .ib_test = &r600_dma_ib_test, 1574 .is_lockup = &cayman_dma_is_lockup, 1575 .vm_flush = &cayman_dma_vm_flush, 1576 .get_rptr = &cayman_dma_get_rptr, 1577 .get_wptr = &cayman_dma_get_wptr, 1578 .set_wptr = &cayman_dma_set_wptr 1579 }; 1580 1581 static struct radeon_asic_ring cayman_uvd_ring = { 1582 .ib_execute = &uvd_v1_0_ib_execute, 1583 .emit_fence = &uvd_v2_2_fence_emit, 1584 .emit_semaphore = &uvd_v3_1_semaphore_emit, 1585 .cs_parse = &radeon_uvd_cs_parse, 1586 .ring_test = &uvd_v1_0_ring_test, 1587 .ib_test = &uvd_v1_0_ib_test, 1588 .is_lockup = &radeon_ring_test_lockup, 1589 .get_rptr = &uvd_v1_0_get_rptr, 1590 .get_wptr = &uvd_v1_0_get_wptr, 1591 .set_wptr = &uvd_v1_0_set_wptr, 1592 }; 1593 1594 static struct radeon_asic cayman_asic = { 1595 .init = &cayman_init, 1596 .fini = &cayman_fini, 1597 .suspend = &cayman_suspend, 1598 .resume = &cayman_resume, 1599 .asic_reset = &cayman_asic_reset, 1600 .vga_set_state = &r600_vga_set_state, 1601 .mmio_hdp_flush = r600_mmio_hdp_flush, 1602 .gui_idle = &r600_gui_idle, 1603 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1604 .get_xclk = &rv770_get_xclk, 1605 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1606 .gart = { 1607 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1608 .set_page = &rs600_gart_set_page, 1609 }, 1610 .vm = { 1611 .init = &cayman_vm_init, 1612 .fini = &cayman_vm_fini, 1613 .copy_pages = &cayman_dma_vm_copy_pages, 1614 .write_pages = &cayman_dma_vm_write_pages, 1615 .set_pages = &cayman_dma_vm_set_pages, 1616 .pad_ib = &cayman_dma_vm_pad_ib, 1617 }, 1618 .ring = { 1619 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, 1620 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, 1621 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, 1622 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, 1623 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, 1624 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1625 }, 1626 .irq = { 1627 .set = &evergreen_irq_set, 1628 .process = &evergreen_irq_process, 1629 }, 1630 .display = { 1631 .bandwidth_update = &evergreen_bandwidth_update, 1632 .get_vblank_counter = &evergreen_get_vblank_counter, 1633 .wait_for_vblank = &dce4_wait_for_vblank, 1634 .set_backlight_level = &atombios_set_backlight_level, 1635 .get_backlight_level = &atombios_get_backlight_level, 1636 .hdmi_enable = &evergreen_hdmi_enable, 1637 .hdmi_setmode = &evergreen_hdmi_setmode, 1638 }, 1639 .copy = { 1640 .blit = &r600_copy_cpdma, 1641 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1642 .dma = &evergreen_copy_dma, 1643 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1644 .copy = &evergreen_copy_dma, 1645 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1646 }, 1647 .surface = { 1648 .set_reg = r600_set_surface_reg, 1649 .clear_reg = r600_clear_surface_reg, 1650 }, 1651 .hpd = { 1652 .init = &evergreen_hpd_init, 1653 .fini = &evergreen_hpd_fini, 1654 .sense = &evergreen_hpd_sense, 1655 .set_polarity = &evergreen_hpd_set_polarity, 1656 }, 1657 .pm = { 1658 .misc = &evergreen_pm_misc, 1659 .prepare = &evergreen_pm_prepare, 1660 .finish = &evergreen_pm_finish, 1661 .init_profile = &btc_pm_init_profile, 1662 .get_dynpm_state = &r600_pm_get_dynpm_state, 1663 .get_engine_clock = &radeon_atom_get_engine_clock, 1664 .set_engine_clock = &radeon_atom_set_engine_clock, 1665 .get_memory_clock = &radeon_atom_get_memory_clock, 1666 .set_memory_clock = &radeon_atom_set_memory_clock, 1667 .get_pcie_lanes = &r600_get_pcie_lanes, 1668 .set_pcie_lanes = &r600_set_pcie_lanes, 1669 .set_clock_gating = NULL, 1670 .set_uvd_clocks = &evergreen_set_uvd_clocks, 1671 .get_temperature = &evergreen_get_temp, 1672 }, 1673 .dpm = { 1674 .init = &ni_dpm_init, 1675 .setup_asic = &ni_dpm_setup_asic, 1676 .enable = &ni_dpm_enable, 1677 .late_enable = &rv770_dpm_late_enable, 1678 .disable = &ni_dpm_disable, 1679 .pre_set_power_state = &ni_dpm_pre_set_power_state, 1680 .set_power_state = &ni_dpm_set_power_state, 1681 .post_set_power_state = &ni_dpm_post_set_power_state, 1682 .display_configuration_changed = &cypress_dpm_display_configuration_changed, 1683 .fini = &ni_dpm_fini, 1684 .get_sclk = &ni_dpm_get_sclk, 1685 .get_mclk = &ni_dpm_get_mclk, 1686 .print_power_state = &ni_dpm_print_power_state, 1687 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level, 1688 .force_performance_level = &ni_dpm_force_performance_level, 1689 .vblank_too_short = &ni_dpm_vblank_too_short, 1690 }, 1691 .pflip = { 1692 .page_flip = &evergreen_page_flip, 1693 .page_flip_pending = &evergreen_page_flip_pending, 1694 }, 1695 }; 1696 1697 static struct radeon_asic trinity_asic = { 1698 .init = &cayman_init, 1699 .fini = &cayman_fini, 1700 .suspend = &cayman_suspend, 1701 .resume = &cayman_resume, 1702 .asic_reset = &cayman_asic_reset, 1703 .vga_set_state = &r600_vga_set_state, 1704 .mmio_hdp_flush = r600_mmio_hdp_flush, 1705 .gui_idle = &r600_gui_idle, 1706 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1707 .get_xclk = &r600_get_xclk, 1708 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1709 .gart = { 1710 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1711 .set_page = &rs600_gart_set_page, 1712 }, 1713 .vm = { 1714 .init = &cayman_vm_init, 1715 .fini = &cayman_vm_fini, 1716 .copy_pages = &cayman_dma_vm_copy_pages, 1717 .write_pages = &cayman_dma_vm_write_pages, 1718 .set_pages = &cayman_dma_vm_set_pages, 1719 .pad_ib = &cayman_dma_vm_pad_ib, 1720 }, 1721 .ring = { 1722 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, 1723 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, 1724 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, 1725 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, 1726 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, 1727 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1728 }, 1729 .irq = { 1730 .set = &evergreen_irq_set, 1731 .process = &evergreen_irq_process, 1732 }, 1733 .display = { 1734 .bandwidth_update = &dce6_bandwidth_update, 1735 .get_vblank_counter = &evergreen_get_vblank_counter, 1736 .wait_for_vblank = &dce4_wait_for_vblank, 1737 .set_backlight_level = &atombios_set_backlight_level, 1738 .get_backlight_level = &atombios_get_backlight_level, 1739 .hdmi_enable = &evergreen_hdmi_enable, 1740 .hdmi_setmode = &evergreen_hdmi_setmode, 1741 }, 1742 .copy = { 1743 .blit = &r600_copy_cpdma, 1744 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1745 .dma = &evergreen_copy_dma, 1746 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1747 .copy = &evergreen_copy_dma, 1748 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1749 }, 1750 .surface = { 1751 .set_reg = r600_set_surface_reg, 1752 .clear_reg = r600_clear_surface_reg, 1753 }, 1754 .hpd = { 1755 .init = &evergreen_hpd_init, 1756 .fini = &evergreen_hpd_fini, 1757 .sense = &evergreen_hpd_sense, 1758 .set_polarity = &evergreen_hpd_set_polarity, 1759 }, 1760 .pm = { 1761 .misc = &evergreen_pm_misc, 1762 .prepare = &evergreen_pm_prepare, 1763 .finish = &evergreen_pm_finish, 1764 .init_profile = &sumo_pm_init_profile, 1765 .get_dynpm_state = &r600_pm_get_dynpm_state, 1766 .get_engine_clock = &radeon_atom_get_engine_clock, 1767 .set_engine_clock = &radeon_atom_set_engine_clock, 1768 .get_memory_clock = NULL, 1769 .set_memory_clock = NULL, 1770 .get_pcie_lanes = NULL, 1771 .set_pcie_lanes = NULL, 1772 .set_clock_gating = NULL, 1773 .set_uvd_clocks = &sumo_set_uvd_clocks, 1774 .get_temperature = &tn_get_temp, 1775 }, 1776 .dpm = { 1777 .init = &trinity_dpm_init, 1778 .setup_asic = &trinity_dpm_setup_asic, 1779 .enable = &trinity_dpm_enable, 1780 .late_enable = &trinity_dpm_late_enable, 1781 .disable = &trinity_dpm_disable, 1782 .pre_set_power_state = &trinity_dpm_pre_set_power_state, 1783 .set_power_state = &trinity_dpm_set_power_state, 1784 .post_set_power_state = &trinity_dpm_post_set_power_state, 1785 .display_configuration_changed = &trinity_dpm_display_configuration_changed, 1786 .fini = &trinity_dpm_fini, 1787 .get_sclk = &trinity_dpm_get_sclk, 1788 .get_mclk = &trinity_dpm_get_mclk, 1789 .print_power_state = &trinity_dpm_print_power_state, 1790 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level, 1791 .force_performance_level = &trinity_dpm_force_performance_level, 1792 .enable_bapm = &trinity_dpm_enable_bapm, 1793 }, 1794 .pflip = { 1795 .page_flip = &evergreen_page_flip, 1796 .page_flip_pending = &evergreen_page_flip_pending, 1797 }, 1798 }; 1799 1800 static struct radeon_asic_ring si_gfx_ring = { 1801 .ib_execute = &si_ring_ib_execute, 1802 .ib_parse = &si_ib_parse, 1803 .emit_fence = &si_fence_ring_emit, 1804 .emit_semaphore = &r600_semaphore_ring_emit, 1805 .cs_parse = NULL, 1806 .ring_test = &r600_ring_test, 1807 .ib_test = &r600_ib_test, 1808 .is_lockup = &si_gfx_is_lockup, 1809 .vm_flush = &si_vm_flush, 1810 .get_rptr = &cayman_gfx_get_rptr, 1811 .get_wptr = &cayman_gfx_get_wptr, 1812 .set_wptr = &cayman_gfx_set_wptr, 1813 }; 1814 1815 static struct radeon_asic_ring si_dma_ring = { 1816 .ib_execute = &cayman_dma_ring_ib_execute, 1817 .ib_parse = &evergreen_dma_ib_parse, 1818 .emit_fence = &evergreen_dma_fence_ring_emit, 1819 .emit_semaphore = &r600_dma_semaphore_ring_emit, 1820 .cs_parse = NULL, 1821 .ring_test = &r600_dma_ring_test, 1822 .ib_test = &r600_dma_ib_test, 1823 .is_lockup = &si_dma_is_lockup, 1824 .vm_flush = &si_dma_vm_flush, 1825 .get_rptr = &cayman_dma_get_rptr, 1826 .get_wptr = &cayman_dma_get_wptr, 1827 .set_wptr = &cayman_dma_set_wptr, 1828 }; 1829 1830 static struct radeon_asic si_asic = { 1831 .init = &si_init, 1832 .fini = &si_fini, 1833 .suspend = &si_suspend, 1834 .resume = &si_resume, 1835 .asic_reset = &si_asic_reset, 1836 .vga_set_state = &r600_vga_set_state, 1837 .mmio_hdp_flush = r600_mmio_hdp_flush, 1838 .gui_idle = &r600_gui_idle, 1839 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1840 .get_xclk = &si_get_xclk, 1841 .get_gpu_clock_counter = &si_get_gpu_clock_counter, 1842 .gart = { 1843 .tlb_flush = &si_pcie_gart_tlb_flush, 1844 .set_page = &rs600_gart_set_page, 1845 }, 1846 .vm = { 1847 .init = &si_vm_init, 1848 .fini = &si_vm_fini, 1849 .copy_pages = &si_dma_vm_copy_pages, 1850 .write_pages = &si_dma_vm_write_pages, 1851 .set_pages = &si_dma_vm_set_pages, 1852 .pad_ib = &cayman_dma_vm_pad_ib, 1853 }, 1854 .ring = { 1855 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring, 1856 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring, 1857 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring, 1858 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring, 1859 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring, 1860 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 1861 }, 1862 .irq = { 1863 .set = &si_irq_set, 1864 .process = &si_irq_process, 1865 }, 1866 .display = { 1867 .bandwidth_update = &dce6_bandwidth_update, 1868 .get_vblank_counter = &evergreen_get_vblank_counter, 1869 .wait_for_vblank = &dce4_wait_for_vblank, 1870 .set_backlight_level = &atombios_set_backlight_level, 1871 .get_backlight_level = &atombios_get_backlight_level, 1872 .hdmi_enable = &evergreen_hdmi_enable, 1873 .hdmi_setmode = &evergreen_hdmi_setmode, 1874 }, 1875 .copy = { 1876 .blit = &r600_copy_cpdma, 1877 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1878 .dma = &si_copy_dma, 1879 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 1880 .copy = &si_copy_dma, 1881 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 1882 }, 1883 .surface = { 1884 .set_reg = r600_set_surface_reg, 1885 .clear_reg = r600_clear_surface_reg, 1886 }, 1887 .hpd = { 1888 .init = &evergreen_hpd_init, 1889 .fini = &evergreen_hpd_fini, 1890 .sense = &evergreen_hpd_sense, 1891 .set_polarity = &evergreen_hpd_set_polarity, 1892 }, 1893 .pm = { 1894 .misc = &evergreen_pm_misc, 1895 .prepare = &evergreen_pm_prepare, 1896 .finish = &evergreen_pm_finish, 1897 .init_profile = &sumo_pm_init_profile, 1898 .get_dynpm_state = &r600_pm_get_dynpm_state, 1899 .get_engine_clock = &radeon_atom_get_engine_clock, 1900 .set_engine_clock = &radeon_atom_set_engine_clock, 1901 .get_memory_clock = &radeon_atom_get_memory_clock, 1902 .set_memory_clock = &radeon_atom_set_memory_clock, 1903 .get_pcie_lanes = &r600_get_pcie_lanes, 1904 .set_pcie_lanes = &r600_set_pcie_lanes, 1905 .set_clock_gating = NULL, 1906 .set_uvd_clocks = &si_set_uvd_clocks, 1907 .get_temperature = &si_get_temp, 1908 }, 1909 .dpm = { 1910 .init = &si_dpm_init, 1911 .setup_asic = &si_dpm_setup_asic, 1912 .enable = &si_dpm_enable, 1913 .late_enable = &si_dpm_late_enable, 1914 .disable = &si_dpm_disable, 1915 .pre_set_power_state = &si_dpm_pre_set_power_state, 1916 .set_power_state = &si_dpm_set_power_state, 1917 .post_set_power_state = &si_dpm_post_set_power_state, 1918 .display_configuration_changed = &si_dpm_display_configuration_changed, 1919 .fini = &si_dpm_fini, 1920 .get_sclk = &ni_dpm_get_sclk, 1921 .get_mclk = &ni_dpm_get_mclk, 1922 .print_power_state = &ni_dpm_print_power_state, 1923 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level, 1924 .force_performance_level = &si_dpm_force_performance_level, 1925 .vblank_too_short = &ni_dpm_vblank_too_short, 1926 }, 1927 .pflip = { 1928 .page_flip = &evergreen_page_flip, 1929 .page_flip_pending = &evergreen_page_flip_pending, 1930 }, 1931 }; 1932 1933 static struct radeon_asic_ring ci_gfx_ring = { 1934 .ib_execute = &cik_ring_ib_execute, 1935 .ib_parse = &cik_ib_parse, 1936 .emit_fence = &cik_fence_gfx_ring_emit, 1937 .emit_semaphore = &cik_semaphore_ring_emit, 1938 .cs_parse = NULL, 1939 .ring_test = &cik_ring_test, 1940 .ib_test = &cik_ib_test, 1941 .is_lockup = &cik_gfx_is_lockup, 1942 .vm_flush = &cik_vm_flush, 1943 .get_rptr = &cik_gfx_get_rptr, 1944 .get_wptr = &cik_gfx_get_wptr, 1945 .set_wptr = &cik_gfx_set_wptr, 1946 }; 1947 1948 static struct radeon_asic_ring ci_cp_ring = { 1949 .ib_execute = &cik_ring_ib_execute, 1950 .ib_parse = &cik_ib_parse, 1951 .emit_fence = &cik_fence_compute_ring_emit, 1952 .emit_semaphore = &cik_semaphore_ring_emit, 1953 .cs_parse = NULL, 1954 .ring_test = &cik_ring_test, 1955 .ib_test = &cik_ib_test, 1956 .is_lockup = &cik_gfx_is_lockup, 1957 .vm_flush = &cik_vm_flush, 1958 .get_rptr = &cik_compute_get_rptr, 1959 .get_wptr = &cik_compute_get_wptr, 1960 .set_wptr = &cik_compute_set_wptr, 1961 }; 1962 1963 static struct radeon_asic_ring ci_dma_ring = { 1964 .ib_execute = &cik_sdma_ring_ib_execute, 1965 .ib_parse = &cik_ib_parse, 1966 .emit_fence = &cik_sdma_fence_ring_emit, 1967 .emit_semaphore = &cik_sdma_semaphore_ring_emit, 1968 .cs_parse = NULL, 1969 .ring_test = &cik_sdma_ring_test, 1970 .ib_test = &cik_sdma_ib_test, 1971 .is_lockup = &cik_sdma_is_lockup, 1972 .vm_flush = &cik_dma_vm_flush, 1973 .get_rptr = &cik_sdma_get_rptr, 1974 .get_wptr = &cik_sdma_get_wptr, 1975 .set_wptr = &cik_sdma_set_wptr, 1976 }; 1977 1978 static struct radeon_asic_ring ci_vce_ring = { 1979 .ib_execute = &radeon_vce_ib_execute, 1980 .emit_fence = &radeon_vce_fence_emit, 1981 .emit_semaphore = &radeon_vce_semaphore_emit, 1982 .cs_parse = &radeon_vce_cs_parse, 1983 .ring_test = &radeon_vce_ring_test, 1984 .ib_test = &radeon_vce_ib_test, 1985 .is_lockup = &radeon_ring_test_lockup, 1986 .get_rptr = &vce_v1_0_get_rptr, 1987 .get_wptr = &vce_v1_0_get_wptr, 1988 .set_wptr = &vce_v1_0_set_wptr, 1989 }; 1990 1991 static struct radeon_asic ci_asic = { 1992 .init = &cik_init, 1993 .fini = &cik_fini, 1994 .suspend = &cik_suspend, 1995 .resume = &cik_resume, 1996 .asic_reset = &cik_asic_reset, 1997 .vga_set_state = &r600_vga_set_state, 1998 .mmio_hdp_flush = &r600_mmio_hdp_flush, 1999 .gui_idle = &r600_gui_idle, 2000 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 2001 .get_xclk = &cik_get_xclk, 2002 .get_gpu_clock_counter = &cik_get_gpu_clock_counter, 2003 .gart = { 2004 .tlb_flush = &cik_pcie_gart_tlb_flush, 2005 .set_page = &rs600_gart_set_page, 2006 }, 2007 .vm = { 2008 .init = &cik_vm_init, 2009 .fini = &cik_vm_fini, 2010 .copy_pages = &cik_sdma_vm_copy_pages, 2011 .write_pages = &cik_sdma_vm_write_pages, 2012 .set_pages = &cik_sdma_vm_set_pages, 2013 .pad_ib = &cik_sdma_vm_pad_ib, 2014 }, 2015 .ring = { 2016 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, 2017 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, 2018 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, 2019 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, 2020 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, 2021 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 2022 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring, 2023 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring, 2024 }, 2025 .irq = { 2026 .set = &cik_irq_set, 2027 .process = &cik_irq_process, 2028 }, 2029 .display = { 2030 .bandwidth_update = &dce8_bandwidth_update, 2031 .get_vblank_counter = &evergreen_get_vblank_counter, 2032 .wait_for_vblank = &dce4_wait_for_vblank, 2033 .set_backlight_level = &atombios_set_backlight_level, 2034 .get_backlight_level = &atombios_get_backlight_level, 2035 .hdmi_enable = &evergreen_hdmi_enable, 2036 .hdmi_setmode = &evergreen_hdmi_setmode, 2037 }, 2038 .copy = { 2039 .blit = &cik_copy_cpdma, 2040 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2041 .dma = &cik_copy_dma, 2042 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2043 .copy = &cik_copy_dma, 2044 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 2045 }, 2046 .surface = { 2047 .set_reg = r600_set_surface_reg, 2048 .clear_reg = r600_clear_surface_reg, 2049 }, 2050 .hpd = { 2051 .init = &evergreen_hpd_init, 2052 .fini = &evergreen_hpd_fini, 2053 .sense = &evergreen_hpd_sense, 2054 .set_polarity = &evergreen_hpd_set_polarity, 2055 }, 2056 .pm = { 2057 .misc = &evergreen_pm_misc, 2058 .prepare = &evergreen_pm_prepare, 2059 .finish = &evergreen_pm_finish, 2060 .init_profile = &sumo_pm_init_profile, 2061 .get_dynpm_state = &r600_pm_get_dynpm_state, 2062 .get_engine_clock = &radeon_atom_get_engine_clock, 2063 .set_engine_clock = &radeon_atom_set_engine_clock, 2064 .get_memory_clock = &radeon_atom_get_memory_clock, 2065 .set_memory_clock = &radeon_atom_set_memory_clock, 2066 .get_pcie_lanes = NULL, 2067 .set_pcie_lanes = NULL, 2068 .set_clock_gating = NULL, 2069 .set_uvd_clocks = &cik_set_uvd_clocks, 2070 .set_vce_clocks = &cik_set_vce_clocks, 2071 .get_temperature = &ci_get_temp, 2072 }, 2073 .dpm = { 2074 .init = &ci_dpm_init, 2075 .setup_asic = &ci_dpm_setup_asic, 2076 .enable = &ci_dpm_enable, 2077 .late_enable = &ci_dpm_late_enable, 2078 .disable = &ci_dpm_disable, 2079 .pre_set_power_state = &ci_dpm_pre_set_power_state, 2080 .set_power_state = &ci_dpm_set_power_state, 2081 .post_set_power_state = &ci_dpm_post_set_power_state, 2082 .display_configuration_changed = &ci_dpm_display_configuration_changed, 2083 .fini = &ci_dpm_fini, 2084 .get_sclk = &ci_dpm_get_sclk, 2085 .get_mclk = &ci_dpm_get_mclk, 2086 .print_power_state = &ci_dpm_print_power_state, 2087 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level, 2088 .force_performance_level = &ci_dpm_force_performance_level, 2089 .vblank_too_short = &ci_dpm_vblank_too_short, 2090 .powergate_uvd = &ci_dpm_powergate_uvd, 2091 }, 2092 .pflip = { 2093 .page_flip = &evergreen_page_flip, 2094 .page_flip_pending = &evergreen_page_flip_pending, 2095 }, 2096 }; 2097 2098 static struct radeon_asic kv_asic = { 2099 .init = &cik_init, 2100 .fini = &cik_fini, 2101 .suspend = &cik_suspend, 2102 .resume = &cik_resume, 2103 .asic_reset = &cik_asic_reset, 2104 .vga_set_state = &r600_vga_set_state, 2105 .mmio_hdp_flush = &r600_mmio_hdp_flush, 2106 .gui_idle = &r600_gui_idle, 2107 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 2108 .get_xclk = &cik_get_xclk, 2109 .get_gpu_clock_counter = &cik_get_gpu_clock_counter, 2110 .gart = { 2111 .tlb_flush = &cik_pcie_gart_tlb_flush, 2112 .set_page = &rs600_gart_set_page, 2113 }, 2114 .vm = { 2115 .init = &cik_vm_init, 2116 .fini = &cik_vm_fini, 2117 .copy_pages = &cik_sdma_vm_copy_pages, 2118 .write_pages = &cik_sdma_vm_write_pages, 2119 .set_pages = &cik_sdma_vm_set_pages, 2120 .pad_ib = &cik_sdma_vm_pad_ib, 2121 }, 2122 .ring = { 2123 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, 2124 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, 2125 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, 2126 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, 2127 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, 2128 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, 2129 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring, 2130 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring, 2131 }, 2132 .irq = { 2133 .set = &cik_irq_set, 2134 .process = &cik_irq_process, 2135 }, 2136 .display = { 2137 .bandwidth_update = &dce8_bandwidth_update, 2138 .get_vblank_counter = &evergreen_get_vblank_counter, 2139 .wait_for_vblank = &dce4_wait_for_vblank, 2140 .set_backlight_level = &atombios_set_backlight_level, 2141 .get_backlight_level = &atombios_get_backlight_level, 2142 .hdmi_enable = &evergreen_hdmi_enable, 2143 .hdmi_setmode = &evergreen_hdmi_setmode, 2144 }, 2145 .copy = { 2146 .blit = &cik_copy_cpdma, 2147 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, 2148 .dma = &cik_copy_dma, 2149 .dma_ring_index = R600_RING_TYPE_DMA_INDEX, 2150 .copy = &cik_copy_dma, 2151 .copy_ring_index = R600_RING_TYPE_DMA_INDEX, 2152 }, 2153 .surface = { 2154 .set_reg = r600_set_surface_reg, 2155 .clear_reg = r600_clear_surface_reg, 2156 }, 2157 .hpd = { 2158 .init = &evergreen_hpd_init, 2159 .fini = &evergreen_hpd_fini, 2160 .sense = &evergreen_hpd_sense, 2161 .set_polarity = &evergreen_hpd_set_polarity, 2162 }, 2163 .pm = { 2164 .misc = &evergreen_pm_misc, 2165 .prepare = &evergreen_pm_prepare, 2166 .finish = &evergreen_pm_finish, 2167 .init_profile = &sumo_pm_init_profile, 2168 .get_dynpm_state = &r600_pm_get_dynpm_state, 2169 .get_engine_clock = &radeon_atom_get_engine_clock, 2170 .set_engine_clock = &radeon_atom_set_engine_clock, 2171 .get_memory_clock = &radeon_atom_get_memory_clock, 2172 .set_memory_clock = &radeon_atom_set_memory_clock, 2173 .get_pcie_lanes = NULL, 2174 .set_pcie_lanes = NULL, 2175 .set_clock_gating = NULL, 2176 .set_uvd_clocks = &cik_set_uvd_clocks, 2177 .set_vce_clocks = &cik_set_vce_clocks, 2178 .get_temperature = &kv_get_temp, 2179 }, 2180 .dpm = { 2181 .init = &kv_dpm_init, 2182 .setup_asic = &kv_dpm_setup_asic, 2183 .enable = &kv_dpm_enable, 2184 .late_enable = &kv_dpm_late_enable, 2185 .disable = &kv_dpm_disable, 2186 .pre_set_power_state = &kv_dpm_pre_set_power_state, 2187 .set_power_state = &kv_dpm_set_power_state, 2188 .post_set_power_state = &kv_dpm_post_set_power_state, 2189 .display_configuration_changed = &kv_dpm_display_configuration_changed, 2190 .fini = &kv_dpm_fini, 2191 .get_sclk = &kv_dpm_get_sclk, 2192 .get_mclk = &kv_dpm_get_mclk, 2193 .print_power_state = &kv_dpm_print_power_state, 2194 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level, 2195 .force_performance_level = &kv_dpm_force_performance_level, 2196 .powergate_uvd = &kv_dpm_powergate_uvd, 2197 .enable_bapm = &kv_dpm_enable_bapm, 2198 }, 2199 .pflip = { 2200 .page_flip = &evergreen_page_flip, 2201 .page_flip_pending = &evergreen_page_flip_pending, 2202 }, 2203 }; 2204 2205 /** 2206 * radeon_asic_init - register asic specific callbacks 2207 * 2208 * @rdev: radeon device pointer 2209 * 2210 * Registers the appropriate asic specific callbacks for each 2211 * chip family. Also sets other asics specific info like the number 2212 * of crtcs and the register aperture accessors (all asics). 2213 * Returns 0 for success. 2214 */ 2215 int radeon_asic_init(struct radeon_device *rdev) 2216 { 2217 radeon_register_accessor_init(rdev); 2218 2219 /* set the number of crtcs */ 2220 if (rdev->flags & RADEON_SINGLE_CRTC) 2221 rdev->num_crtc = 1; 2222 else 2223 rdev->num_crtc = 2; 2224 2225 rdev->has_uvd = false; 2226 2227 switch (rdev->family) { 2228 case CHIP_R100: 2229 case CHIP_RV100: 2230 case CHIP_RS100: 2231 case CHIP_RV200: 2232 case CHIP_RS200: 2233 rdev->asic = &r100_asic; 2234 break; 2235 case CHIP_R200: 2236 case CHIP_RV250: 2237 case CHIP_RS300: 2238 case CHIP_RV280: 2239 rdev->asic = &r200_asic; 2240 break; 2241 case CHIP_R300: 2242 case CHIP_R350: 2243 case CHIP_RV350: 2244 case CHIP_RV380: 2245 if (rdev->flags & RADEON_IS_PCIE) 2246 rdev->asic = &r300_asic_pcie; 2247 else 2248 rdev->asic = &r300_asic; 2249 break; 2250 case CHIP_R420: 2251 case CHIP_R423: 2252 case CHIP_RV410: 2253 rdev->asic = &r420_asic; 2254 /* handle macs */ 2255 if (rdev->bios == NULL) { 2256 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock; 2257 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock; 2258 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock; 2259 rdev->asic->pm.set_memory_clock = NULL; 2260 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level; 2261 } 2262 break; 2263 case CHIP_RS400: 2264 case CHIP_RS480: 2265 rdev->asic = &rs400_asic; 2266 break; 2267 case CHIP_RS600: 2268 rdev->asic = &rs600_asic; 2269 break; 2270 case CHIP_RS690: 2271 case CHIP_RS740: 2272 rdev->asic = &rs690_asic; 2273 break; 2274 case CHIP_RV515: 2275 rdev->asic = &rv515_asic; 2276 break; 2277 case CHIP_R520: 2278 case CHIP_RV530: 2279 case CHIP_RV560: 2280 case CHIP_RV570: 2281 case CHIP_R580: 2282 rdev->asic = &r520_asic; 2283 break; 2284 case CHIP_R600: 2285 rdev->asic = &r600_asic; 2286 break; 2287 case CHIP_RV610: 2288 case CHIP_RV630: 2289 case CHIP_RV620: 2290 case CHIP_RV635: 2291 case CHIP_RV670: 2292 rdev->asic = &rv6xx_asic; 2293 rdev->has_uvd = true; 2294 break; 2295 case CHIP_RS780: 2296 case CHIP_RS880: 2297 rdev->asic = &rs780_asic; 2298 rdev->has_uvd = true; 2299 break; 2300 case CHIP_RV770: 2301 case CHIP_RV730: 2302 case CHIP_RV710: 2303 case CHIP_RV740: 2304 rdev->asic = &rv770_asic; 2305 rdev->has_uvd = true; 2306 break; 2307 case CHIP_CEDAR: 2308 case CHIP_REDWOOD: 2309 case CHIP_JUNIPER: 2310 case CHIP_CYPRESS: 2311 case CHIP_HEMLOCK: 2312 /* set num crtcs */ 2313 if (rdev->family == CHIP_CEDAR) 2314 rdev->num_crtc = 4; 2315 else 2316 rdev->num_crtc = 6; 2317 rdev->asic = &evergreen_asic; 2318 rdev->has_uvd = true; 2319 break; 2320 case CHIP_PALM: 2321 case CHIP_SUMO: 2322 case CHIP_SUMO2: 2323 rdev->asic = &sumo_asic; 2324 rdev->has_uvd = true; 2325 break; 2326 case CHIP_BARTS: 2327 case CHIP_TURKS: 2328 case CHIP_CAICOS: 2329 /* set num crtcs */ 2330 if (rdev->family == CHIP_CAICOS) 2331 rdev->num_crtc = 4; 2332 else 2333 rdev->num_crtc = 6; 2334 rdev->asic = &btc_asic; 2335 rdev->has_uvd = true; 2336 break; 2337 case CHIP_CAYMAN: 2338 rdev->asic = &cayman_asic; 2339 /* set num crtcs */ 2340 rdev->num_crtc = 6; 2341 rdev->has_uvd = true; 2342 break; 2343 case CHIP_ARUBA: 2344 rdev->asic = &trinity_asic; 2345 /* set num crtcs */ 2346 rdev->num_crtc = 4; 2347 rdev->has_uvd = true; 2348 break; 2349 case CHIP_TAHITI: 2350 case CHIP_PITCAIRN: 2351 case CHIP_VERDE: 2352 case CHIP_OLAND: 2353 case CHIP_HAINAN: 2354 rdev->asic = &si_asic; 2355 /* set num crtcs */ 2356 if (rdev->family == CHIP_HAINAN) 2357 rdev->num_crtc = 0; 2358 else if (rdev->family == CHIP_OLAND) 2359 rdev->num_crtc = 2; 2360 else 2361 rdev->num_crtc = 6; 2362 if (rdev->family == CHIP_HAINAN) 2363 rdev->has_uvd = false; 2364 else 2365 rdev->has_uvd = true; 2366 switch (rdev->family) { 2367 case CHIP_TAHITI: 2368 rdev->cg_flags = 2369 RADEON_CG_SUPPORT_GFX_MGCG | 2370 RADEON_CG_SUPPORT_GFX_MGLS | 2371 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2372 RADEON_CG_SUPPORT_GFX_CGLS | 2373 RADEON_CG_SUPPORT_GFX_CGTS | 2374 RADEON_CG_SUPPORT_GFX_CP_LS | 2375 RADEON_CG_SUPPORT_MC_MGCG | 2376 RADEON_CG_SUPPORT_SDMA_MGCG | 2377 RADEON_CG_SUPPORT_BIF_LS | 2378 RADEON_CG_SUPPORT_VCE_MGCG | 2379 RADEON_CG_SUPPORT_UVD_MGCG | 2380 RADEON_CG_SUPPORT_HDP_LS | 2381 RADEON_CG_SUPPORT_HDP_MGCG; 2382 rdev->pg_flags = 0; 2383 break; 2384 case CHIP_PITCAIRN: 2385 rdev->cg_flags = 2386 RADEON_CG_SUPPORT_GFX_MGCG | 2387 RADEON_CG_SUPPORT_GFX_MGLS | 2388 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2389 RADEON_CG_SUPPORT_GFX_CGLS | 2390 RADEON_CG_SUPPORT_GFX_CGTS | 2391 RADEON_CG_SUPPORT_GFX_CP_LS | 2392 RADEON_CG_SUPPORT_GFX_RLC_LS | 2393 RADEON_CG_SUPPORT_MC_LS | 2394 RADEON_CG_SUPPORT_MC_MGCG | 2395 RADEON_CG_SUPPORT_SDMA_MGCG | 2396 RADEON_CG_SUPPORT_BIF_LS | 2397 RADEON_CG_SUPPORT_VCE_MGCG | 2398 RADEON_CG_SUPPORT_UVD_MGCG | 2399 RADEON_CG_SUPPORT_HDP_LS | 2400 RADEON_CG_SUPPORT_HDP_MGCG; 2401 rdev->pg_flags = 0; 2402 break; 2403 case CHIP_VERDE: 2404 rdev->cg_flags = 2405 RADEON_CG_SUPPORT_GFX_MGCG | 2406 RADEON_CG_SUPPORT_GFX_MGLS | 2407 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2408 RADEON_CG_SUPPORT_GFX_CGLS | 2409 RADEON_CG_SUPPORT_GFX_CGTS | 2410 RADEON_CG_SUPPORT_GFX_CP_LS | 2411 RADEON_CG_SUPPORT_GFX_RLC_LS | 2412 RADEON_CG_SUPPORT_MC_LS | 2413 RADEON_CG_SUPPORT_MC_MGCG | 2414 RADEON_CG_SUPPORT_SDMA_MGCG | 2415 RADEON_CG_SUPPORT_BIF_LS | 2416 RADEON_CG_SUPPORT_VCE_MGCG | 2417 RADEON_CG_SUPPORT_UVD_MGCG | 2418 RADEON_CG_SUPPORT_HDP_LS | 2419 RADEON_CG_SUPPORT_HDP_MGCG; 2420 rdev->pg_flags = 0 | 2421 /*RADEON_PG_SUPPORT_GFX_PG | */ 2422 RADEON_PG_SUPPORT_SDMA; 2423 break; 2424 case CHIP_OLAND: 2425 rdev->cg_flags = 2426 RADEON_CG_SUPPORT_GFX_MGCG | 2427 RADEON_CG_SUPPORT_GFX_MGLS | 2428 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2429 RADEON_CG_SUPPORT_GFX_CGLS | 2430 RADEON_CG_SUPPORT_GFX_CGTS | 2431 RADEON_CG_SUPPORT_GFX_CP_LS | 2432 RADEON_CG_SUPPORT_GFX_RLC_LS | 2433 RADEON_CG_SUPPORT_MC_LS | 2434 RADEON_CG_SUPPORT_MC_MGCG | 2435 RADEON_CG_SUPPORT_SDMA_MGCG | 2436 RADEON_CG_SUPPORT_BIF_LS | 2437 RADEON_CG_SUPPORT_UVD_MGCG | 2438 RADEON_CG_SUPPORT_HDP_LS | 2439 RADEON_CG_SUPPORT_HDP_MGCG; 2440 rdev->pg_flags = 0; 2441 break; 2442 case CHIP_HAINAN: 2443 rdev->cg_flags = 2444 RADEON_CG_SUPPORT_GFX_MGCG | 2445 RADEON_CG_SUPPORT_GFX_MGLS | 2446 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2447 RADEON_CG_SUPPORT_GFX_CGLS | 2448 RADEON_CG_SUPPORT_GFX_CGTS | 2449 RADEON_CG_SUPPORT_GFX_CP_LS | 2450 RADEON_CG_SUPPORT_GFX_RLC_LS | 2451 RADEON_CG_SUPPORT_MC_LS | 2452 RADEON_CG_SUPPORT_MC_MGCG | 2453 RADEON_CG_SUPPORT_SDMA_MGCG | 2454 RADEON_CG_SUPPORT_BIF_LS | 2455 RADEON_CG_SUPPORT_HDP_LS | 2456 RADEON_CG_SUPPORT_HDP_MGCG; 2457 rdev->pg_flags = 0; 2458 break; 2459 default: 2460 rdev->cg_flags = 0; 2461 rdev->pg_flags = 0; 2462 break; 2463 } 2464 break; 2465 case CHIP_BONAIRE: 2466 case CHIP_HAWAII: 2467 rdev->asic = &ci_asic; 2468 rdev->num_crtc = 6; 2469 rdev->has_uvd = true; 2470 if (rdev->family == CHIP_BONAIRE) { 2471 rdev->cg_flags = 2472 RADEON_CG_SUPPORT_GFX_MGCG | 2473 RADEON_CG_SUPPORT_GFX_MGLS | 2474 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2475 RADEON_CG_SUPPORT_GFX_CGLS | 2476 RADEON_CG_SUPPORT_GFX_CGTS | 2477 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2478 RADEON_CG_SUPPORT_GFX_CP_LS | 2479 RADEON_CG_SUPPORT_MC_LS | 2480 RADEON_CG_SUPPORT_MC_MGCG | 2481 RADEON_CG_SUPPORT_SDMA_MGCG | 2482 RADEON_CG_SUPPORT_SDMA_LS | 2483 RADEON_CG_SUPPORT_BIF_LS | 2484 RADEON_CG_SUPPORT_VCE_MGCG | 2485 RADEON_CG_SUPPORT_UVD_MGCG | 2486 RADEON_CG_SUPPORT_HDP_LS | 2487 RADEON_CG_SUPPORT_HDP_MGCG; 2488 rdev->pg_flags = 0; 2489 } else { 2490 rdev->cg_flags = 2491 RADEON_CG_SUPPORT_GFX_MGCG | 2492 RADEON_CG_SUPPORT_GFX_MGLS | 2493 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2494 RADEON_CG_SUPPORT_GFX_CGLS | 2495 RADEON_CG_SUPPORT_GFX_CGTS | 2496 RADEON_CG_SUPPORT_GFX_CP_LS | 2497 RADEON_CG_SUPPORT_MC_LS | 2498 RADEON_CG_SUPPORT_MC_MGCG | 2499 RADEON_CG_SUPPORT_SDMA_MGCG | 2500 RADEON_CG_SUPPORT_SDMA_LS | 2501 RADEON_CG_SUPPORT_BIF_LS | 2502 RADEON_CG_SUPPORT_VCE_MGCG | 2503 RADEON_CG_SUPPORT_UVD_MGCG | 2504 RADEON_CG_SUPPORT_HDP_LS | 2505 RADEON_CG_SUPPORT_HDP_MGCG; 2506 rdev->pg_flags = 0; 2507 } 2508 break; 2509 case CHIP_KAVERI: 2510 case CHIP_KABINI: 2511 case CHIP_MULLINS: 2512 rdev->asic = &kv_asic; 2513 /* set num crtcs */ 2514 if (rdev->family == CHIP_KAVERI) { 2515 rdev->num_crtc = 4; 2516 rdev->cg_flags = 2517 RADEON_CG_SUPPORT_GFX_MGCG | 2518 RADEON_CG_SUPPORT_GFX_MGLS | 2519 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2520 RADEON_CG_SUPPORT_GFX_CGLS | 2521 RADEON_CG_SUPPORT_GFX_CGTS | 2522 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2523 RADEON_CG_SUPPORT_GFX_CP_LS | 2524 RADEON_CG_SUPPORT_SDMA_MGCG | 2525 RADEON_CG_SUPPORT_SDMA_LS | 2526 RADEON_CG_SUPPORT_BIF_LS | 2527 RADEON_CG_SUPPORT_VCE_MGCG | 2528 RADEON_CG_SUPPORT_UVD_MGCG | 2529 RADEON_CG_SUPPORT_HDP_LS | 2530 RADEON_CG_SUPPORT_HDP_MGCG; 2531 rdev->pg_flags = 0; 2532 /*RADEON_PG_SUPPORT_GFX_PG | 2533 RADEON_PG_SUPPORT_GFX_SMG | 2534 RADEON_PG_SUPPORT_GFX_DMG | 2535 RADEON_PG_SUPPORT_UVD | 2536 RADEON_PG_SUPPORT_VCE | 2537 RADEON_PG_SUPPORT_CP | 2538 RADEON_PG_SUPPORT_GDS | 2539 RADEON_PG_SUPPORT_RLC_SMU_HS | 2540 RADEON_PG_SUPPORT_ACP | 2541 RADEON_PG_SUPPORT_SAMU;*/ 2542 } else { 2543 rdev->num_crtc = 2; 2544 rdev->cg_flags = 2545 RADEON_CG_SUPPORT_GFX_MGCG | 2546 RADEON_CG_SUPPORT_GFX_MGLS | 2547 /*RADEON_CG_SUPPORT_GFX_CGCG |*/ 2548 RADEON_CG_SUPPORT_GFX_CGLS | 2549 RADEON_CG_SUPPORT_GFX_CGTS | 2550 RADEON_CG_SUPPORT_GFX_CGTS_LS | 2551 RADEON_CG_SUPPORT_GFX_CP_LS | 2552 RADEON_CG_SUPPORT_SDMA_MGCG | 2553 RADEON_CG_SUPPORT_SDMA_LS | 2554 RADEON_CG_SUPPORT_BIF_LS | 2555 RADEON_CG_SUPPORT_VCE_MGCG | 2556 RADEON_CG_SUPPORT_UVD_MGCG | 2557 RADEON_CG_SUPPORT_HDP_LS | 2558 RADEON_CG_SUPPORT_HDP_MGCG; 2559 rdev->pg_flags = 0; 2560 /*RADEON_PG_SUPPORT_GFX_PG | 2561 RADEON_PG_SUPPORT_GFX_SMG | 2562 RADEON_PG_SUPPORT_UVD | 2563 RADEON_PG_SUPPORT_VCE | 2564 RADEON_PG_SUPPORT_CP | 2565 RADEON_PG_SUPPORT_GDS | 2566 RADEON_PG_SUPPORT_RLC_SMU_HS | 2567 RADEON_PG_SUPPORT_SAMU;*/ 2568 } 2569 rdev->has_uvd = true; 2570 break; 2571 default: 2572 /* FIXME: not supported yet */ 2573 return -EINVAL; 2574 } 2575 2576 if (rdev->flags & RADEON_IS_IGP) { 2577 rdev->asic->pm.get_memory_clock = NULL; 2578 rdev->asic->pm.set_memory_clock = NULL; 2579 } 2580 2581 return 0; 2582 } 2583 2584