1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * 28 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_asic.h 254885 2013-08-25 19:37:15Z dumbbell $ 29 */ 30 31 #ifndef __RADEON_ASIC_H__ 32 #define __RADEON_ASIC_H__ 33 34 /* 35 * common functions 36 */ 37 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); 38 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 39 uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); 40 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 41 42 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); 43 void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 44 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); 45 void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); 46 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 47 48 void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); 49 u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder); 50 void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); 51 u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder); 52 53 54 /* 55 * r100,rv100,rs100,rv200,rs200 56 */ 57 struct r100_mc_save { 58 u32 GENMO_WT; 59 u32 CRTC_EXT_CNTL; 60 u32 CRTC_GEN_CNTL; 61 u32 CRTC2_GEN_CNTL; 62 u32 CUR_OFFSET; 63 u32 CUR2_OFFSET; 64 }; 65 int r100_init(struct radeon_device *rdev); 66 void r100_fini(struct radeon_device *rdev); 67 int r100_suspend(struct radeon_device *rdev); 68 int r100_resume(struct radeon_device *rdev); 69 void r100_vga_set_state(struct radeon_device *rdev, bool state); 70 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 71 int r100_asic_reset(struct radeon_device *rdev); 72 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); 73 void r100_pci_gart_tlb_flush(struct radeon_device *rdev); 74 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 75 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 76 int r100_irq_set(struct radeon_device *rdev); 77 irqreturn_t r100_irq_process(struct radeon_device *rdev); 78 void r100_fence_ring_emit(struct radeon_device *rdev, 79 struct radeon_fence *fence); 80 void r100_semaphore_ring_emit(struct radeon_device *rdev, 81 struct radeon_ring *cp, 82 struct radeon_semaphore *semaphore, 83 bool emit_wait); 84 int r100_cs_parse(struct radeon_cs_parser *p); 85 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 86 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); 87 int r100_copy_blit(struct radeon_device *rdev, 88 uint64_t src_offset, 89 uint64_t dst_offset, 90 unsigned num_gpu_pages, 91 struct radeon_fence **fence); 92 int r100_set_surface_reg(struct radeon_device *rdev, int reg, 93 uint32_t tiling_flags, uint32_t pitch, 94 uint32_t offset, uint32_t obj_size); 95 void r100_clear_surface_reg(struct radeon_device *rdev, int reg); 96 void r100_bandwidth_update(struct radeon_device *rdev); 97 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 98 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 99 void r100_hpd_init(struct radeon_device *rdev); 100 void r100_hpd_fini(struct radeon_device *rdev); 101 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 102 void r100_hpd_set_polarity(struct radeon_device *rdev, 103 enum radeon_hpd_id hpd); 104 int r100_debugfs_rbbm_init(struct radeon_device *rdev); 105 int r100_debugfs_cp_init(struct radeon_device *rdev); 106 void r100_cp_disable(struct radeon_device *rdev); 107 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); 108 void r100_cp_fini(struct radeon_device *rdev); 109 int r100_pci_gart_init(struct radeon_device *rdev); 110 void r100_pci_gart_fini(struct radeon_device *rdev); 111 int r100_pci_gart_enable(struct radeon_device *rdev); 112 void r100_pci_gart_disable(struct radeon_device *rdev); 113 int r100_debugfs_mc_info_init(struct radeon_device *rdev); 114 int r100_gui_wait_for_idle(struct radeon_device *rdev); 115 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 116 void r100_irq_disable(struct radeon_device *rdev); 117 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); 118 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); 119 void r100_vram_init_sizes(struct radeon_device *rdev); 120 int r100_cp_reset(struct radeon_device *rdev); 121 void r100_vga_render_disable(struct radeon_device *rdev); 122 void r100_restore_sanity(struct radeon_device *rdev); 123 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 124 struct radeon_cs_packet *pkt, 125 struct radeon_bo *robj); 126 int r100_cs_parse_packet0(struct radeon_cs_parser *p, 127 struct radeon_cs_packet *pkt, 128 const unsigned *auth, unsigned n, 129 radeon_packet0_check_t check); 130 int r100_cs_packet_parse(struct radeon_cs_parser *p, 131 struct radeon_cs_packet *pkt, 132 unsigned idx); 133 void r100_enable_bm(struct radeon_device *rdev); 134 void r100_set_common_regs(struct radeon_device *rdev); 135 void r100_bm_disable(struct radeon_device *rdev); 136 extern bool r100_gui_idle(struct radeon_device *rdev); 137 extern void r100_pm_misc(struct radeon_device *rdev); 138 extern void r100_pm_prepare(struct radeon_device *rdev); 139 extern void r100_pm_finish(struct radeon_device *rdev); 140 extern void r100_pm_init_profile(struct radeon_device *rdev); 141 extern void r100_pm_get_dynpm_state(struct radeon_device *rdev); 142 extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc); 143 extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 144 extern void r100_post_page_flip(struct radeon_device *rdev, int crtc); 145 extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc); 146 extern int r100_mc_wait_for_idle(struct radeon_device *rdev); 147 148 /* 149 * r200,rv250,rs300,rv280 150 */ 151 extern int r200_copy_dma(struct radeon_device *rdev, 152 uint64_t src_offset, 153 uint64_t dst_offset, 154 unsigned num_gpu_pages, 155 struct radeon_fence **fence); 156 void r200_set_safe_registers(struct radeon_device *rdev); 157 158 /* 159 * r300,r350,rv350,rv380 160 */ 161 extern int r300_init(struct radeon_device *rdev); 162 extern void r300_fini(struct radeon_device *rdev); 163 extern int r300_suspend(struct radeon_device *rdev); 164 extern int r300_resume(struct radeon_device *rdev); 165 extern int r300_asic_reset(struct radeon_device *rdev); 166 extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 167 extern void r300_fence_ring_emit(struct radeon_device *rdev, 168 struct radeon_fence *fence); 169 extern int r300_cs_parse(struct radeon_cs_parser *p); 170 extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); 171 extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 172 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); 173 extern int rv370_get_pcie_lanes(struct radeon_device *rdev); 174 extern void r300_set_reg_safe(struct radeon_device *rdev); 175 extern void r300_mc_program(struct radeon_device *rdev); 176 extern void r300_mc_init(struct radeon_device *rdev); 177 extern void r300_clock_startup(struct radeon_device *rdev); 178 extern int r300_mc_wait_for_idle(struct radeon_device *rdev); 179 extern int rv370_pcie_gart_init(struct radeon_device *rdev); 180 extern void rv370_pcie_gart_fini(struct radeon_device *rdev); 181 extern int rv370_pcie_gart_enable(struct radeon_device *rdev); 182 extern void rv370_pcie_gart_disable(struct radeon_device *rdev); 183 184 /* 185 * r420,r423,rv410 186 */ 187 extern int r420_init(struct radeon_device *rdev); 188 extern void r420_fini(struct radeon_device *rdev); 189 extern int r420_suspend(struct radeon_device *rdev); 190 extern int r420_resume(struct radeon_device *rdev); 191 extern void r420_pm_init_profile(struct radeon_device *rdev); 192 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); 193 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 194 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); 195 extern void r420_pipes_init(struct radeon_device *rdev); 196 197 /* 198 * rs400,rs480 199 */ 200 extern int rs400_init(struct radeon_device *rdev); 201 extern void rs400_fini(struct radeon_device *rdev); 202 extern int rs400_suspend(struct radeon_device *rdev); 203 extern int rs400_resume(struct radeon_device *rdev); 204 void rs400_gart_tlb_flush(struct radeon_device *rdev); 205 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 206 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); 207 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 208 int rs400_gart_init(struct radeon_device *rdev); 209 int rs400_gart_enable(struct radeon_device *rdev); 210 void rs400_gart_adjust_size(struct radeon_device *rdev); 211 void rs400_gart_disable(struct radeon_device *rdev); 212 void rs400_gart_fini(struct radeon_device *rdev); 213 extern int rs400_mc_wait_for_idle(struct radeon_device *rdev); 214 215 /* 216 * rs600. 217 */ 218 extern int rs600_asic_reset(struct radeon_device *rdev); 219 extern int rs600_init(struct radeon_device *rdev); 220 extern void rs600_fini(struct radeon_device *rdev); 221 extern int rs600_suspend(struct radeon_device *rdev); 222 extern int rs600_resume(struct radeon_device *rdev); 223 int rs600_irq_set(struct radeon_device *rdev); 224 irqreturn_t rs600_irq_process(struct radeon_device *rdev); 225 void rs600_irq_disable(struct radeon_device *rdev); 226 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); 227 void rs600_gart_tlb_flush(struct radeon_device *rdev); 228 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 229 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); 230 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 231 void rs600_bandwidth_update(struct radeon_device *rdev); 232 void rs600_hpd_init(struct radeon_device *rdev); 233 void rs600_hpd_fini(struct radeon_device *rdev); 234 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 235 void rs600_hpd_set_polarity(struct radeon_device *rdev, 236 enum radeon_hpd_id hpd); 237 extern void rs600_pm_misc(struct radeon_device *rdev); 238 extern void rs600_pm_prepare(struct radeon_device *rdev); 239 extern void rs600_pm_finish(struct radeon_device *rdev); 240 extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc); 241 extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 242 extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc); 243 void rs600_set_safe_registers(struct radeon_device *rdev); 244 extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc); 245 extern int rs600_mc_wait_for_idle(struct radeon_device *rdev); 246 247 /* 248 * rs690,rs740 249 */ 250 int rs690_init(struct radeon_device *rdev); 251 void rs690_fini(struct radeon_device *rdev); 252 int rs690_resume(struct radeon_device *rdev); 253 int rs690_suspend(struct radeon_device *rdev); 254 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); 255 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 256 void rs690_bandwidth_update(struct radeon_device *rdev); 257 void rs690_line_buffer_adjust(struct radeon_device *rdev, 258 struct drm_display_mode *mode1, 259 struct drm_display_mode *mode2); 260 extern int rs690_mc_wait_for_idle(struct radeon_device *rdev); 261 262 /* 263 * rv515 264 */ 265 struct rv515_mc_save { 266 u32 vga_render_control; 267 u32 vga_hdp_control; 268 bool crtc_enabled[2]; 269 }; 270 271 int rv515_init(struct radeon_device *rdev); 272 void rv515_fini(struct radeon_device *rdev); 273 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); 274 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 275 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 276 void rv515_bandwidth_update(struct radeon_device *rdev); 277 int rv515_resume(struct radeon_device *rdev); 278 int rv515_suspend(struct radeon_device *rdev); 279 void rv515_bandwidth_avivo_update(struct radeon_device *rdev); 280 void rv515_vga_render_disable(struct radeon_device *rdev); 281 void rv515_set_safe_registers(struct radeon_device *rdev); 282 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); 283 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); 284 void rv515_clock_startup(struct radeon_device *rdev); 285 void rv515_debugfs(struct radeon_device *rdev); 286 int rv515_mc_wait_for_idle(struct radeon_device *rdev); 287 288 /* 289 * r520,rv530,rv560,rv570,r580 290 */ 291 int r520_init(struct radeon_device *rdev); 292 int r520_resume(struct radeon_device *rdev); 293 int r520_mc_wait_for_idle(struct radeon_device *rdev); 294 295 /* 296 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 297 */ 298 int r600_init(struct radeon_device *rdev); 299 void r600_fini(struct radeon_device *rdev); 300 int r600_suspend(struct radeon_device *rdev); 301 int r600_resume(struct radeon_device *rdev); 302 void r600_vga_set_state(struct radeon_device *rdev, bool state); 303 int r600_wb_init(struct radeon_device *rdev); 304 void r600_wb_fini(struct radeon_device *rdev); 305 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); 306 uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); 307 void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 308 int r600_cs_parse(struct radeon_cs_parser *p); 309 int r600_dma_cs_parse(struct radeon_cs_parser *p); 310 void r600_fence_ring_emit(struct radeon_device *rdev, 311 struct radeon_fence *fence); 312 void r600_semaphore_ring_emit(struct radeon_device *rdev, 313 struct radeon_ring *cp, 314 struct radeon_semaphore *semaphore, 315 bool emit_wait); 316 void r600_dma_fence_ring_emit(struct radeon_device *rdev, 317 struct radeon_fence *fence); 318 void r600_dma_semaphore_ring_emit(struct radeon_device *rdev, 319 struct radeon_ring *ring, 320 struct radeon_semaphore *semaphore, 321 bool emit_wait); 322 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 323 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 324 bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 325 int r600_asic_reset(struct radeon_device *rdev); 326 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 327 uint32_t tiling_flags, uint32_t pitch, 328 uint32_t offset, uint32_t obj_size); 329 void r600_clear_surface_reg(struct radeon_device *rdev, int reg); 330 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 331 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 332 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 333 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 334 int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 335 int r600_copy_blit(struct radeon_device *rdev, 336 uint64_t src_offset, uint64_t dst_offset, 337 unsigned num_gpu_pages, struct radeon_fence **fence); 338 int r600_copy_dma(struct radeon_device *rdev, 339 uint64_t src_offset, uint64_t dst_offset, 340 unsigned num_gpu_pages, struct radeon_fence **fence); 341 void r600_hpd_init(struct radeon_device *rdev); 342 void r600_hpd_fini(struct radeon_device *rdev); 343 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 344 void r600_hpd_set_polarity(struct radeon_device *rdev, 345 enum radeon_hpd_id hpd); 346 extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo); 347 extern bool r600_gui_idle(struct radeon_device *rdev); 348 extern void r600_pm_misc(struct radeon_device *rdev); 349 extern void r600_pm_init_profile(struct radeon_device *rdev); 350 extern void rs780_pm_init_profile(struct radeon_device *rdev); 351 extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); 352 extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes); 353 extern int r600_get_pcie_lanes(struct radeon_device *rdev); 354 bool r600_card_posted(struct radeon_device *rdev); 355 void r600_cp_stop(struct radeon_device *rdev); 356 int r600_cp_start(struct radeon_device *rdev); 357 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size); 358 int r600_cp_resume(struct radeon_device *rdev); 359 void r600_cp_fini(struct radeon_device *rdev); 360 int r600_count_pipe_bits(uint32_t val); 361 int r600_mc_wait_for_idle(struct radeon_device *rdev); 362 int r600_pcie_gart_init(struct radeon_device *rdev); 363 void r600_scratch_init(struct radeon_device *rdev); 364 int r600_blit_init(struct radeon_device *rdev); 365 void r600_blit_fini(struct radeon_device *rdev); 366 int r600_init_microcode(struct radeon_device *rdev); 367 void r600_fini_microcode(struct radeon_device *rdev); 368 /* r600 irq */ 369 irqreturn_t r600_irq_process(struct radeon_device *rdev); 370 int r600_irq_init(struct radeon_device *rdev); 371 void r600_irq_fini(struct radeon_device *rdev); 372 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); 373 int r600_irq_set(struct radeon_device *rdev); 374 void r600_irq_suspend(struct radeon_device *rdev); 375 void r600_disable_interrupts(struct radeon_device *rdev); 376 void r600_rlc_stop(struct radeon_device *rdev); 377 /* r600 audio */ 378 int r600_audio_init(struct radeon_device *rdev); 379 void r600_audio_set_clock(struct drm_encoder *encoder, int clock); 380 struct r600_audio r600_audio_status(struct radeon_device *rdev); 381 void r600_audio_fini(struct radeon_device *rdev); 382 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); 383 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); 384 /* r600 blit */ 385 int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages, 386 struct radeon_fence **fence, struct radeon_sa_bo **vb, 387 struct radeon_semaphore **sem); 388 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence, 389 struct radeon_sa_bo *vb, struct radeon_semaphore *sem); 390 void r600_kms_blit_copy(struct radeon_device *rdev, 391 u64 src_gpu_addr, u64 dst_gpu_addr, 392 unsigned num_gpu_pages, 393 struct radeon_sa_bo *vb); 394 uint64_t r600_get_gpu_clock(struct radeon_device *rdev); 395 396 /* 397 * rv770,rv730,rv710,rv740 398 */ 399 int rv770_init(struct radeon_device *rdev); 400 void rv770_fini(struct radeon_device *rdev); 401 int rv770_suspend(struct radeon_device *rdev); 402 int rv770_resume(struct radeon_device *rdev); 403 void rv770_pm_misc(struct radeon_device *rdev); 404 u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 405 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 406 void r700_cp_stop(struct radeon_device *rdev); 407 void r700_cp_fini(struct radeon_device *rdev); 408 int rv770_copy_dma(struct radeon_device *rdev, 409 uint64_t src_offset, uint64_t dst_offset, 410 unsigned num_gpu_pages, 411 struct radeon_fence **fence); 412 413 /* 414 * evergreen 415 */ 416 struct evergreen_mc_save { 417 u32 vga_render_control; 418 u32 vga_hdp_control; 419 bool crtc_enabled[RADEON_MAX_CRTCS]; 420 }; 421 422 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); 423 int evergreen_init(struct radeon_device *rdev); 424 void evergreen_fini(struct radeon_device *rdev); 425 int evergreen_suspend(struct radeon_device *rdev); 426 int evergreen_resume(struct radeon_device *rdev); 427 bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 428 int evergreen_asic_reset(struct radeon_device *rdev); 429 void evergreen_bandwidth_update(struct radeon_device *rdev); 430 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 431 void evergreen_hpd_init(struct radeon_device *rdev); 432 void evergreen_hpd_fini(struct radeon_device *rdev); 433 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 434 void evergreen_hpd_set_polarity(struct radeon_device *rdev, 435 enum radeon_hpd_id hpd); 436 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); 437 int evergreen_irq_set(struct radeon_device *rdev); 438 irqreturn_t evergreen_irq_process(struct radeon_device *rdev); 439 extern int evergreen_cs_parse(struct radeon_cs_parser *p); 440 extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p); 441 extern void evergreen_pm_misc(struct radeon_device *rdev); 442 extern void evergreen_pm_prepare(struct radeon_device *rdev); 443 extern void evergreen_pm_finish(struct radeon_device *rdev); 444 extern void sumo_pm_init_profile(struct radeon_device *rdev); 445 extern void btc_pm_init_profile(struct radeon_device *rdev); 446 extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc); 447 extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 448 extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc); 449 extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc); 450 void evergreen_disable_interrupt_state(struct radeon_device *rdev); 451 int evergreen_blit_init(struct radeon_device *rdev); 452 int evergreen_mc_wait_for_idle(struct radeon_device *rdev); 453 void evergreen_dma_fence_ring_emit(struct radeon_device *rdev, 454 struct radeon_fence *fence); 455 void evergreen_dma_ring_ib_execute(struct radeon_device *rdev, 456 struct radeon_ib *ib); 457 int evergreen_copy_dma(struct radeon_device *rdev, 458 uint64_t src_offset, uint64_t dst_offset, 459 unsigned num_gpu_pages, 460 struct radeon_fence **fence); 461 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev); 462 u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev); 463 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); 464 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); 465 void evergreen_mc_program(struct radeon_device *rdev); 466 int evergreen_mc_init(struct radeon_device *rdev); 467 void evergreen_irq_suspend(struct radeon_device *rdev); 468 469 /* 470 * cayman 471 */ 472 void cayman_fence_ring_emit(struct radeon_device *rdev, 473 struct radeon_fence *fence); 474 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev); 475 int cayman_init(struct radeon_device *rdev); 476 void cayman_fini(struct radeon_device *rdev); 477 int cayman_suspend(struct radeon_device *rdev); 478 int cayman_resume(struct radeon_device *rdev); 479 int cayman_asic_reset(struct radeon_device *rdev); 480 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 481 int cayman_vm_init(struct radeon_device *rdev); 482 void cayman_vm_fini(struct radeon_device *rdev); 483 void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 484 uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags); 485 void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe, 486 uint64_t addr, unsigned count, 487 uint32_t incr, uint32_t flags); 488 int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 489 int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 490 void cayman_dma_ring_ib_execute(struct radeon_device *rdev, 491 struct radeon_ib *ib); 492 bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 493 void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 494 extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev, 495 int ring, u32 cp_int_cntl); 496 497 /* DCE6 - SI */ 498 void dce6_bandwidth_update(struct radeon_device *rdev); 499 500 /* 501 * si 502 */ 503 void si_fence_ring_emit(struct radeon_device *rdev, 504 struct radeon_fence *fence); 505 void si_pcie_gart_tlb_flush(struct radeon_device *rdev); 506 int si_init(struct radeon_device *rdev); 507 void si_fini(struct radeon_device *rdev); 508 int si_suspend(struct radeon_device *rdev); 509 int si_resume(struct radeon_device *rdev); 510 bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 511 int si_asic_reset(struct radeon_device *rdev); 512 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 513 int si_irq_set(struct radeon_device *rdev); 514 irqreturn_t si_irq_process(struct radeon_device *rdev); 515 int si_vm_init(struct radeon_device *rdev); 516 void si_vm_fini(struct radeon_device *rdev); 517 void si_vm_set_page(struct radeon_device *rdev, uint64_t pe, 518 uint64_t addr, unsigned count, 519 uint32_t incr, uint32_t flags); 520 void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 521 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 522 uint64_t si_get_gpu_clock(struct radeon_device *rdev); 523 int si_copy_dma(struct radeon_device *rdev, 524 uint64_t src_offset, uint64_t dst_offset, 525 unsigned num_gpu_pages, 526 struct radeon_fence **fence); 527 void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 528 void si_rlc_fini(struct radeon_device *rdev); 529 int si_rlc_init(struct radeon_device *rdev); 530 531 #endif 532