1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_ASIC_H__ 29 #define __RADEON_ASIC_H__ 30 31 /* 32 * common functions 33 */ 34 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); 35 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 36 uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); 37 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 38 39 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); 40 void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 41 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); 42 void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); 43 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 44 45 void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); 46 u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder); 47 void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); 48 u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder); 49 50 /* 51 * r100,rv100,rs100,rv200,rs200 52 */ 53 struct r100_mc_save { 54 u32 GENMO_WT; 55 u32 CRTC_EXT_CNTL; 56 u32 CRTC_GEN_CNTL; 57 u32 CRTC2_GEN_CNTL; 58 u32 CUR_OFFSET; 59 u32 CUR2_OFFSET; 60 }; 61 int r100_init(struct radeon_device *rdev); 62 void r100_fini(struct radeon_device *rdev); 63 int r100_suspend(struct radeon_device *rdev); 64 int r100_resume(struct radeon_device *rdev); 65 void r100_vga_set_state(struct radeon_device *rdev, bool state); 66 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 67 int r100_asic_reset(struct radeon_device *rdev); 68 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); 69 void r100_pci_gart_tlb_flush(struct radeon_device *rdev); 70 void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i, 71 uint64_t addr, uint32_t flags); 72 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 73 int r100_irq_set(struct radeon_device *rdev); 74 irqreturn_t r100_irq_process(struct radeon_device *rdev); 75 void r100_fence_ring_emit(struct radeon_device *rdev, 76 struct radeon_fence *fence); 77 bool r100_semaphore_ring_emit(struct radeon_device *rdev, 78 struct radeon_ring *cp, 79 struct radeon_semaphore *semaphore, 80 bool emit_wait); 81 int r100_cs_parse(struct radeon_cs_parser *p); 82 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 83 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); 84 int r100_copy_blit(struct radeon_device *rdev, 85 uint64_t src_offset, 86 uint64_t dst_offset, 87 unsigned num_gpu_pages, 88 struct radeon_fence **fence); 89 int r100_set_surface_reg(struct radeon_device *rdev, int reg, 90 uint32_t tiling_flags, uint32_t pitch, 91 uint32_t offset, uint32_t obj_size); 92 void r100_clear_surface_reg(struct radeon_device *rdev, int reg); 93 void r100_bandwidth_update(struct radeon_device *rdev); 94 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 95 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 96 void r100_hpd_init(struct radeon_device *rdev); 97 void r100_hpd_fini(struct radeon_device *rdev); 98 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 99 void r100_hpd_set_polarity(struct radeon_device *rdev, 100 enum radeon_hpd_id hpd); 101 int r100_debugfs_rbbm_init(struct radeon_device *rdev); 102 int r100_debugfs_cp_init(struct radeon_device *rdev); 103 void r100_cp_disable(struct radeon_device *rdev); 104 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); 105 void r100_cp_fini(struct radeon_device *rdev); 106 int r100_pci_gart_init(struct radeon_device *rdev); 107 void r100_pci_gart_fini(struct radeon_device *rdev); 108 int r100_pci_gart_enable(struct radeon_device *rdev); 109 void r100_pci_gart_disable(struct radeon_device *rdev); 110 int r100_debugfs_mc_info_init(struct radeon_device *rdev); 111 int r100_gui_wait_for_idle(struct radeon_device *rdev); 112 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 113 void r100_irq_disable(struct radeon_device *rdev); 114 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); 115 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); 116 void r100_vram_init_sizes(struct radeon_device *rdev); 117 int r100_cp_reset(struct radeon_device *rdev); 118 void r100_vga_render_disable(struct radeon_device *rdev); 119 void r100_restore_sanity(struct radeon_device *rdev); 120 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 121 struct radeon_cs_packet *pkt, 122 struct radeon_bo *robj); 123 int r100_cs_parse_packet0(struct radeon_cs_parser *p, 124 struct radeon_cs_packet *pkt, 125 const unsigned *auth, unsigned n, 126 radeon_packet0_check_t check); 127 int r100_cs_packet_parse(struct radeon_cs_parser *p, 128 struct radeon_cs_packet *pkt, 129 unsigned idx); 130 void r100_enable_bm(struct radeon_device *rdev); 131 void r100_set_common_regs(struct radeon_device *rdev); 132 void r100_bm_disable(struct radeon_device *rdev); 133 extern bool r100_gui_idle(struct radeon_device *rdev); 134 extern void r100_pm_misc(struct radeon_device *rdev); 135 extern void r100_pm_prepare(struct radeon_device *rdev); 136 extern void r100_pm_finish(struct radeon_device *rdev); 137 extern void r100_pm_init_profile(struct radeon_device *rdev); 138 extern void r100_pm_get_dynpm_state(struct radeon_device *rdev); 139 extern void r100_page_flip(struct radeon_device *rdev, int crtc, 140 u64 crtc_base); 141 extern bool r100_page_flip_pending(struct radeon_device *rdev, int crtc); 142 extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc); 143 extern int r100_mc_wait_for_idle(struct radeon_device *rdev); 144 145 u32 r100_gfx_get_rptr(struct radeon_device *rdev, 146 struct radeon_ring *ring); 147 u32 r100_gfx_get_wptr(struct radeon_device *rdev, 148 struct radeon_ring *ring); 149 void r100_gfx_set_wptr(struct radeon_device *rdev, 150 struct radeon_ring *ring); 151 152 /* 153 * r200,rv250,rs300,rv280 154 */ 155 extern int r200_copy_dma(struct radeon_device *rdev, 156 uint64_t src_offset, 157 uint64_t dst_offset, 158 unsigned num_gpu_pages, 159 struct radeon_fence **fence); 160 void r200_set_safe_registers(struct radeon_device *rdev); 161 162 /* 163 * r300,r350,rv350,rv380 164 */ 165 extern int r300_init(struct radeon_device *rdev); 166 extern void r300_fini(struct radeon_device *rdev); 167 extern int r300_suspend(struct radeon_device *rdev); 168 extern int r300_resume(struct radeon_device *rdev); 169 extern int r300_asic_reset(struct radeon_device *rdev); 170 extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 171 extern void r300_fence_ring_emit(struct radeon_device *rdev, 172 struct radeon_fence *fence); 173 extern int r300_cs_parse(struct radeon_cs_parser *p); 174 extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); 175 extern void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i, 176 uint64_t addr, uint32_t flags); 177 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); 178 extern int rv370_get_pcie_lanes(struct radeon_device *rdev); 179 extern void r300_set_reg_safe(struct radeon_device *rdev); 180 extern void r300_mc_program(struct radeon_device *rdev); 181 extern void r300_mc_init(struct radeon_device *rdev); 182 extern void r300_clock_startup(struct radeon_device *rdev); 183 extern int r300_mc_wait_for_idle(struct radeon_device *rdev); 184 extern int rv370_pcie_gart_init(struct radeon_device *rdev); 185 extern void rv370_pcie_gart_fini(struct radeon_device *rdev); 186 extern int rv370_pcie_gart_enable(struct radeon_device *rdev); 187 extern void rv370_pcie_gart_disable(struct radeon_device *rdev); 188 189 /* 190 * r420,r423,rv410 191 */ 192 extern int r420_init(struct radeon_device *rdev); 193 extern void r420_fini(struct radeon_device *rdev); 194 extern int r420_suspend(struct radeon_device *rdev); 195 extern int r420_resume(struct radeon_device *rdev); 196 extern void r420_pm_init_profile(struct radeon_device *rdev); 197 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); 198 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 199 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); 200 extern void r420_pipes_init(struct radeon_device *rdev); 201 202 /* 203 * rs400,rs480 204 */ 205 extern int rs400_init(struct radeon_device *rdev); 206 extern void rs400_fini(struct radeon_device *rdev); 207 extern int rs400_suspend(struct radeon_device *rdev); 208 extern int rs400_resume(struct radeon_device *rdev); 209 void rs400_gart_tlb_flush(struct radeon_device *rdev); 210 void rs400_gart_set_page(struct radeon_device *rdev, unsigned i, 211 uint64_t addr, uint32_t flags); 212 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); 213 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 214 int rs400_gart_init(struct radeon_device *rdev); 215 int rs400_gart_enable(struct radeon_device *rdev); 216 void rs400_gart_adjust_size(struct radeon_device *rdev); 217 void rs400_gart_disable(struct radeon_device *rdev); 218 void rs400_gart_fini(struct radeon_device *rdev); 219 extern int rs400_mc_wait_for_idle(struct radeon_device *rdev); 220 221 /* 222 * rs600. 223 */ 224 extern int rs600_asic_reset(struct radeon_device *rdev); 225 extern int rs600_init(struct radeon_device *rdev); 226 extern void rs600_fini(struct radeon_device *rdev); 227 extern int rs600_suspend(struct radeon_device *rdev); 228 extern int rs600_resume(struct radeon_device *rdev); 229 int rs600_irq_set(struct radeon_device *rdev); 230 irqreturn_t rs600_irq_process(struct radeon_device *rdev); 231 void rs600_irq_disable(struct radeon_device *rdev); 232 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); 233 void rs600_gart_tlb_flush(struct radeon_device *rdev); 234 void rs600_gart_set_page(struct radeon_device *rdev, unsigned i, 235 uint64_t addr, uint32_t flags); 236 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); 237 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 238 void rs600_bandwidth_update(struct radeon_device *rdev); 239 void rs600_hpd_init(struct radeon_device *rdev); 240 void rs600_hpd_fini(struct radeon_device *rdev); 241 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 242 void rs600_hpd_set_polarity(struct radeon_device *rdev, 243 enum radeon_hpd_id hpd); 244 extern void rs600_pm_misc(struct radeon_device *rdev); 245 extern void rs600_pm_prepare(struct radeon_device *rdev); 246 extern void rs600_pm_finish(struct radeon_device *rdev); 247 extern void rs600_page_flip(struct radeon_device *rdev, int crtc, 248 u64 crtc_base); 249 extern bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc); 250 void rs600_set_safe_registers(struct radeon_device *rdev); 251 extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc); 252 extern int rs600_mc_wait_for_idle(struct radeon_device *rdev); 253 254 /* 255 * rs690,rs740 256 */ 257 int rs690_init(struct radeon_device *rdev); 258 void rs690_fini(struct radeon_device *rdev); 259 int rs690_resume(struct radeon_device *rdev); 260 int rs690_suspend(struct radeon_device *rdev); 261 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); 262 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 263 void rs690_bandwidth_update(struct radeon_device *rdev); 264 void rs690_line_buffer_adjust(struct radeon_device *rdev, 265 struct drm_display_mode *mode1, 266 struct drm_display_mode *mode2); 267 extern int rs690_mc_wait_for_idle(struct radeon_device *rdev); 268 269 /* 270 * rv515 271 */ 272 struct rv515_mc_save { 273 u32 vga_render_control; 274 u32 vga_hdp_control; 275 bool crtc_enabled[2]; 276 }; 277 278 int rv515_init(struct radeon_device *rdev); 279 void rv515_fini(struct radeon_device *rdev); 280 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); 281 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 282 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 283 void rv515_bandwidth_update(struct radeon_device *rdev); 284 int rv515_resume(struct radeon_device *rdev); 285 int rv515_suspend(struct radeon_device *rdev); 286 void rv515_bandwidth_avivo_update(struct radeon_device *rdev); 287 void rv515_vga_render_disable(struct radeon_device *rdev); 288 void rv515_set_safe_registers(struct radeon_device *rdev); 289 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); 290 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); 291 void rv515_clock_startup(struct radeon_device *rdev); 292 void rv515_debugfs(struct radeon_device *rdev); 293 int rv515_mc_wait_for_idle(struct radeon_device *rdev); 294 295 /* 296 * r520,rv530,rv560,rv570,r580 297 */ 298 int r520_init(struct radeon_device *rdev); 299 int r520_resume(struct radeon_device *rdev); 300 int r520_mc_wait_for_idle(struct radeon_device *rdev); 301 302 /* 303 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 304 */ 305 int r600_init(struct radeon_device *rdev); 306 void r600_fini(struct radeon_device *rdev); 307 int r600_suspend(struct radeon_device *rdev); 308 int r600_resume(struct radeon_device *rdev); 309 void r600_vga_set_state(struct radeon_device *rdev, bool state); 310 int r600_wb_init(struct radeon_device *rdev); 311 void r600_wb_fini(struct radeon_device *rdev); 312 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); 313 uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); 314 void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 315 int r600_cs_parse(struct radeon_cs_parser *p); 316 int r600_dma_cs_parse(struct radeon_cs_parser *p); 317 int r600_dma_cs_next_reloc(struct radeon_cs_parser *p, 318 struct radeon_cs_reloc **cs_reloc); 319 u32 r600_gpu_check_soft_reset(struct radeon_device *rdev); 320 void r600_fence_ring_emit(struct radeon_device *rdev, 321 struct radeon_fence *fence); 322 bool r600_semaphore_ring_emit(struct radeon_device *rdev, 323 struct radeon_ring *cp, 324 struct radeon_semaphore *semaphore, 325 bool emit_wait); 326 void r600_dma_fence_ring_emit(struct radeon_device *rdev, 327 struct radeon_fence *fence); 328 bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev, 329 struct radeon_ring *ring, 330 struct radeon_semaphore *semaphore, 331 bool emit_wait); 332 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 333 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 334 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 335 int r600_asic_reset(struct radeon_device *rdev); 336 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 337 uint32_t tiling_flags, uint32_t pitch, 338 uint32_t offset, uint32_t obj_size); 339 void r600_clear_surface_reg(struct radeon_device *rdev, int reg); 340 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 341 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 342 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 343 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 344 int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 345 int r600_copy_cpdma(struct radeon_device *rdev, 346 uint64_t src_offset, uint64_t dst_offset, 347 unsigned num_gpu_pages, struct radeon_fence **fence); 348 int r600_copy_dma(struct radeon_device *rdev, 349 uint64_t src_offset, uint64_t dst_offset, 350 unsigned num_gpu_pages, struct radeon_fence **fence); 351 void r600_hpd_init(struct radeon_device *rdev); 352 void r600_hpd_fini(struct radeon_device *rdev); 353 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 354 void r600_hpd_set_polarity(struct radeon_device *rdev, 355 enum radeon_hpd_id hpd); 356 extern void r600_mmio_hdp_flush(struct radeon_device *rdev); 357 extern bool r600_gui_idle(struct radeon_device *rdev); 358 extern void r600_pm_misc(struct radeon_device *rdev); 359 extern void r600_pm_init_profile(struct radeon_device *rdev); 360 extern void rs780_pm_init_profile(struct radeon_device *rdev); 361 extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg); 362 extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 363 extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); 364 extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes); 365 extern int r600_get_pcie_lanes(struct radeon_device *rdev); 366 bool r600_card_posted(struct radeon_device *rdev); 367 void r600_cp_stop(struct radeon_device *rdev); 368 int r600_cp_start(struct radeon_device *rdev); 369 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size); 370 int r600_cp_resume(struct radeon_device *rdev); 371 void r600_cp_fini(struct radeon_device *rdev); 372 int r600_count_pipe_bits(uint32_t val); 373 int r600_mc_wait_for_idle(struct radeon_device *rdev); 374 int r600_pcie_gart_init(struct radeon_device *rdev); 375 void r600_scratch_init(struct radeon_device *rdev); 376 int r600_init_microcode(struct radeon_device *rdev); 377 u32 r600_gfx_get_rptr(struct radeon_device *rdev, 378 struct radeon_ring *ring); 379 u32 r600_gfx_get_wptr(struct radeon_device *rdev, 380 struct radeon_ring *ring); 381 void r600_gfx_set_wptr(struct radeon_device *rdev, 382 struct radeon_ring *ring); 383 void r600_fini_microcode(struct radeon_device *rdev); 384 /* r600 irq */ 385 irqreturn_t r600_irq_process(struct radeon_device *rdev); 386 int r600_irq_init(struct radeon_device *rdev); 387 void r600_irq_fini(struct radeon_device *rdev); 388 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); 389 int r600_irq_set(struct radeon_device *rdev); 390 void r600_irq_suspend(struct radeon_device *rdev); 391 void r600_disable_interrupts(struct radeon_device *rdev); 392 void r600_rlc_stop(struct radeon_device *rdev); 393 /* r600 audio */ 394 int r600_audio_init(struct radeon_device *rdev); 395 struct r600_audio_pin r600_audio_status(struct radeon_device *rdev); 396 void r600_audio_fini(struct radeon_device *rdev); 397 void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock); 398 void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer, 399 size_t size); 400 void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock); 401 void r600_hdmi_audio_workaround(struct drm_encoder *encoder); 402 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); 403 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); 404 void r600_hdmi_enable(struct drm_encoder *encoder, bool enable); 405 void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 406 u32 r600_get_xclk(struct radeon_device *rdev); 407 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev); 408 int rv6xx_get_temp(struct radeon_device *rdev); 409 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 410 int r600_dpm_pre_set_power_state(struct radeon_device *rdev); 411 void r600_dpm_post_set_power_state(struct radeon_device *rdev); 412 int r600_dpm_late_enable(struct radeon_device *rdev); 413 /* r600 dma */ 414 uint32_t r600_dma_get_rptr(struct radeon_device *rdev, 415 struct radeon_ring *ring); 416 uint32_t r600_dma_get_wptr(struct radeon_device *rdev, 417 struct radeon_ring *ring); 418 void r600_dma_set_wptr(struct radeon_device *rdev, 419 struct radeon_ring *ring); 420 /* rv6xx dpm */ 421 int rv6xx_dpm_init(struct radeon_device *rdev); 422 int rv6xx_dpm_enable(struct radeon_device *rdev); 423 void rv6xx_dpm_disable(struct radeon_device *rdev); 424 int rv6xx_dpm_set_power_state(struct radeon_device *rdev); 425 void rv6xx_setup_asic(struct radeon_device *rdev); 426 void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev); 427 void rv6xx_dpm_fini(struct radeon_device *rdev); 428 u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low); 429 u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low); 430 void rv6xx_dpm_print_power_state(struct radeon_device *rdev, 431 struct radeon_ps *ps); 432 void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 433 struct seq_file *m); 434 int rv6xx_dpm_force_performance_level(struct radeon_device *rdev, 435 enum radeon_dpm_forced_level level); 436 /* rs780 dpm */ 437 int rs780_dpm_init(struct radeon_device *rdev); 438 int rs780_dpm_enable(struct radeon_device *rdev); 439 void rs780_dpm_disable(struct radeon_device *rdev); 440 int rs780_dpm_set_power_state(struct radeon_device *rdev); 441 void rs780_dpm_setup_asic(struct radeon_device *rdev); 442 void rs780_dpm_display_configuration_changed(struct radeon_device *rdev); 443 void rs780_dpm_fini(struct radeon_device *rdev); 444 u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low); 445 u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low); 446 void rs780_dpm_print_power_state(struct radeon_device *rdev, 447 struct radeon_ps *ps); 448 void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 449 struct seq_file *m); 450 int rs780_dpm_force_performance_level(struct radeon_device *rdev, 451 enum radeon_dpm_forced_level level); 452 453 /* 454 * rv770,rv730,rv710,rv740 455 */ 456 int rv770_init(struct radeon_device *rdev); 457 void rv770_fini(struct radeon_device *rdev); 458 int rv770_suspend(struct radeon_device *rdev); 459 int rv770_resume(struct radeon_device *rdev); 460 void rv770_pm_misc(struct radeon_device *rdev); 461 void rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 462 bool rv770_page_flip_pending(struct radeon_device *rdev, int crtc); 463 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 464 void r700_cp_stop(struct radeon_device *rdev); 465 void r700_cp_fini(struct radeon_device *rdev); 466 int rv770_copy_dma(struct radeon_device *rdev, 467 uint64_t src_offset, uint64_t dst_offset, 468 unsigned num_gpu_pages, 469 struct radeon_fence **fence); 470 u32 rv770_get_xclk(struct radeon_device *rdev); 471 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 472 int rv770_get_temp(struct radeon_device *rdev); 473 /* hdmi */ 474 void dce3_1_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 475 /* rv7xx pm */ 476 int rv770_dpm_init(struct radeon_device *rdev); 477 int rv770_dpm_enable(struct radeon_device *rdev); 478 int rv770_dpm_late_enable(struct radeon_device *rdev); 479 void rv770_dpm_disable(struct radeon_device *rdev); 480 int rv770_dpm_set_power_state(struct radeon_device *rdev); 481 void rv770_dpm_setup_asic(struct radeon_device *rdev); 482 void rv770_dpm_display_configuration_changed(struct radeon_device *rdev); 483 void rv770_dpm_fini(struct radeon_device *rdev); 484 u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low); 485 u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low); 486 void rv770_dpm_print_power_state(struct radeon_device *rdev, 487 struct radeon_ps *ps); 488 void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 489 struct seq_file *m); 490 bool rv770_dpm_vblank_too_short(struct radeon_device *rdev); 491 void rv770_set_clk_bypass_mode(struct radeon_device *rdev); 492 493 /* 494 * evergreen 495 */ 496 struct evergreen_mc_save { 497 u32 vga_render_control; 498 u32 vga_hdp_control; 499 bool crtc_enabled[RADEON_MAX_CRTCS]; 500 }; 501 502 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); 503 int evergreen_init(struct radeon_device *rdev); 504 void evergreen_fini(struct radeon_device *rdev); 505 int evergreen_suspend(struct radeon_device *rdev); 506 int evergreen_resume(struct radeon_device *rdev); 507 bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 508 bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 509 int evergreen_asic_reset(struct radeon_device *rdev); 510 void evergreen_bandwidth_update(struct radeon_device *rdev); 511 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 512 void evergreen_hpd_init(struct radeon_device *rdev); 513 void evergreen_hpd_fini(struct radeon_device *rdev); 514 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 515 void evergreen_hpd_set_polarity(struct radeon_device *rdev, 516 enum radeon_hpd_id hpd); 517 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); 518 int evergreen_irq_set(struct radeon_device *rdev); 519 irqreturn_t evergreen_irq_process(struct radeon_device *rdev); 520 extern int evergreen_cs_parse(struct radeon_cs_parser *p); 521 extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p); 522 extern void evergreen_pm_misc(struct radeon_device *rdev); 523 extern void evergreen_pm_prepare(struct radeon_device *rdev); 524 extern void evergreen_pm_finish(struct radeon_device *rdev); 525 extern void sumo_pm_init_profile(struct radeon_device *rdev); 526 extern void btc_pm_init_profile(struct radeon_device *rdev); 527 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 528 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 529 extern void evergreen_page_flip(struct radeon_device *rdev, int crtc, 530 u64 crtc_base); 531 extern bool evergreen_page_flip_pending(struct radeon_device *rdev, int crtc); 532 extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc); 533 void evergreen_disable_interrupt_state(struct radeon_device *rdev); 534 int evergreen_mc_wait_for_idle(struct radeon_device *rdev); 535 void evergreen_dma_fence_ring_emit(struct radeon_device *rdev, 536 struct radeon_fence *fence); 537 void evergreen_dma_ring_ib_execute(struct radeon_device *rdev, 538 struct radeon_ib *ib); 539 int evergreen_copy_dma(struct radeon_device *rdev, 540 uint64_t src_offset, uint64_t dst_offset, 541 unsigned num_gpu_pages, 542 struct radeon_fence **fence); 543 u32 evergreen_gpu_check_soft_reset(struct radeon_device *rdev); 544 void evergreen_gpu_pci_config_reset(struct radeon_device *rdev); 545 void evergreen_pcie_gen2_enable(struct radeon_device *rdev); 546 void evergreen_print_gpu_status_regs(struct radeon_device *rdev); 547 void evergreen_program_aspm(struct radeon_device *rdev); 548 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev); 549 u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev); 550 void sumo_rlc_fini(struct radeon_device *rdev); 551 int sumo_rlc_init(struct radeon_device *rdev); 552 int evergreen_rlc_resume(struct radeon_device *rdev); 553 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); 554 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); 555 void evergreen_mc_program(struct radeon_device *rdev); 556 int evergreen_mc_init(struct radeon_device *rdev); 557 void evergreen_irq_suspend(struct radeon_device *rdev); 558 bool evergreen_is_display_hung(struct radeon_device *rdev); 559 void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable); 560 void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 561 int evergreen_get_temp(struct radeon_device *rdev); 562 int sumo_get_temp(struct radeon_device *rdev); 563 int tn_get_temp(struct radeon_device *rdev); 564 int cypress_dpm_init(struct radeon_device *rdev); 565 void cypress_dpm_setup_asic(struct radeon_device *rdev); 566 int cypress_dpm_enable(struct radeon_device *rdev); 567 void cypress_dpm_disable(struct radeon_device *rdev); 568 int cypress_dpm_set_power_state(struct radeon_device *rdev); 569 void cypress_dpm_display_configuration_changed(struct radeon_device *rdev); 570 void cypress_dpm_fini(struct radeon_device *rdev); 571 bool cypress_dpm_vblank_too_short(struct radeon_device *rdev); 572 int btc_dpm_init(struct radeon_device *rdev); 573 void btc_dpm_setup_asic(struct radeon_device *rdev); 574 int btc_dpm_enable(struct radeon_device *rdev); 575 void btc_dpm_disable(struct radeon_device *rdev); 576 int btc_dpm_pre_set_power_state(struct radeon_device *rdev); 577 int btc_dpm_set_power_state(struct radeon_device *rdev); 578 void btc_dpm_post_set_power_state(struct radeon_device *rdev); 579 void btc_dpm_fini(struct radeon_device *rdev); 580 u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low); 581 u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low); 582 bool btc_dpm_vblank_too_short(struct radeon_device *rdev); 583 void btc_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 584 struct seq_file *m); 585 int sumo_dpm_init(struct radeon_device *rdev); 586 int sumo_dpm_enable(struct radeon_device *rdev); 587 int sumo_dpm_late_enable(struct radeon_device *rdev); 588 void sumo_dpm_disable(struct radeon_device *rdev); 589 int sumo_dpm_pre_set_power_state(struct radeon_device *rdev); 590 int sumo_dpm_set_power_state(struct radeon_device *rdev); 591 void sumo_dpm_post_set_power_state(struct radeon_device *rdev); 592 void sumo_dpm_setup_asic(struct radeon_device *rdev); 593 void sumo_dpm_display_configuration_changed(struct radeon_device *rdev); 594 void sumo_dpm_fini(struct radeon_device *rdev); 595 u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low); 596 u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low); 597 void sumo_dpm_print_power_state(struct radeon_device *rdev, 598 struct radeon_ps *ps); 599 void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 600 struct seq_file *m); 601 int sumo_dpm_force_performance_level(struct radeon_device *rdev, 602 enum radeon_dpm_forced_level level); 603 604 /* 605 * cayman 606 */ 607 void cayman_fence_ring_emit(struct radeon_device *rdev, 608 struct radeon_fence *fence); 609 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev); 610 int cayman_init(struct radeon_device *rdev); 611 void cayman_fini(struct radeon_device *rdev); 612 int cayman_suspend(struct radeon_device *rdev); 613 int cayman_resume(struct radeon_device *rdev); 614 int cayman_asic_reset(struct radeon_device *rdev); 615 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 616 int cayman_vm_init(struct radeon_device *rdev); 617 void cayman_vm_fini(struct radeon_device *rdev); 618 void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 619 uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags); 620 void cayman_vm_decode_fault(struct radeon_device *rdev, 621 u32 status, u32 addr); 622 u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev); 623 int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 624 int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 625 void cayman_dma_ring_ib_execute(struct radeon_device *rdev, 626 struct radeon_ib *ib); 627 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 628 bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 629 630 void cayman_dma_vm_copy_pages(struct radeon_device *rdev, 631 struct radeon_ib *ib, 632 uint64_t pe, uint64_t src, 633 unsigned count); 634 void cayman_dma_vm_write_pages(struct radeon_device *rdev, 635 struct radeon_ib *ib, 636 uint64_t pe, 637 uint64_t addr, unsigned count, 638 uint32_t incr, uint32_t flags); 639 void cayman_dma_vm_set_pages(struct radeon_device *rdev, 640 struct radeon_ib *ib, 641 uint64_t pe, 642 uint64_t addr, unsigned count, 643 uint32_t incr, uint32_t flags); 644 void cayman_dma_vm_pad_ib(struct radeon_ib *ib); 645 646 void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 647 648 u32 cayman_gfx_get_rptr(struct radeon_device *rdev, 649 struct radeon_ring *ring); 650 u32 cayman_gfx_get_wptr(struct radeon_device *rdev, 651 struct radeon_ring *ring); 652 void cayman_gfx_set_wptr(struct radeon_device *rdev, 653 struct radeon_ring *ring); 654 uint32_t cayman_dma_get_rptr(struct radeon_device *rdev, 655 struct radeon_ring *ring); 656 uint32_t cayman_dma_get_wptr(struct radeon_device *rdev, 657 struct radeon_ring *ring); 658 void cayman_dma_set_wptr(struct radeon_device *rdev, 659 struct radeon_ring *ring); 660 void cayman_cp_int_cntl_setup(struct radeon_device *rdev, 661 int ring, u32 cp_int_cntl); 662 663 int ni_dpm_init(struct radeon_device *rdev); 664 void ni_dpm_setup_asic(struct radeon_device *rdev); 665 int ni_dpm_enable(struct radeon_device *rdev); 666 void ni_dpm_disable(struct radeon_device *rdev); 667 int ni_dpm_pre_set_power_state(struct radeon_device *rdev); 668 int ni_dpm_set_power_state(struct radeon_device *rdev); 669 void ni_dpm_post_set_power_state(struct radeon_device *rdev); 670 void ni_dpm_fini(struct radeon_device *rdev); 671 u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low); 672 u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low); 673 void ni_dpm_print_power_state(struct radeon_device *rdev, 674 struct radeon_ps *ps); 675 void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 676 struct seq_file *m); 677 int ni_dpm_force_performance_level(struct radeon_device *rdev, 678 enum radeon_dpm_forced_level level); 679 //bool ni_dpm_vblank_too_short(struct radeon_device *rdev); 680 int trinity_dpm_init(struct radeon_device *rdev); 681 int trinity_dpm_enable(struct radeon_device *rdev); 682 int trinity_dpm_late_enable(struct radeon_device *rdev); 683 void trinity_dpm_disable(struct radeon_device *rdev); 684 int trinity_dpm_pre_set_power_state(struct radeon_device *rdev); 685 int trinity_dpm_set_power_state(struct radeon_device *rdev); 686 void trinity_dpm_post_set_power_state(struct radeon_device *rdev); 687 void trinity_dpm_setup_asic(struct radeon_device *rdev); 688 void trinity_dpm_display_configuration_changed(struct radeon_device *rdev); 689 void trinity_dpm_fini(struct radeon_device *rdev); 690 u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low); 691 u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low); 692 void trinity_dpm_print_power_state(struct radeon_device *rdev, 693 struct radeon_ps *ps); 694 void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 695 struct seq_file *m); 696 int trinity_dpm_force_performance_level(struct radeon_device *rdev, 697 enum radeon_dpm_forced_level level); 698 void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable); 699 700 /* DCE6 - SI */ 701 void dce6_bandwidth_update(struct radeon_device *rdev); 702 int dce6_audio_init(struct radeon_device *rdev); 703 void dce6_audio_fini(struct radeon_device *rdev); 704 705 void dce6_afmt_write_sad_regs(struct drm_encoder *encoder); 706 void dce6_afmt_select_pin(struct drm_encoder *encoder); 707 void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder); 708 void dce6_afmt_write_latency_fields(struct drm_encoder *encoder, 709 struct drm_display_mode *mode); 710 711 /* 712 * si 713 */ 714 void si_fence_ring_emit(struct radeon_device *rdev, 715 struct radeon_fence *fence); 716 void si_pcie_gart_tlb_flush(struct radeon_device *rdev); 717 int si_init(struct radeon_device *rdev); 718 void si_fini(struct radeon_device *rdev); 719 int si_suspend(struct radeon_device *rdev); 720 int si_resume(struct radeon_device *rdev); 721 bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 722 bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 723 int si_asic_reset(struct radeon_device *rdev); 724 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 725 int si_irq_set(struct radeon_device *rdev); 726 irqreturn_t si_irq_process(struct radeon_device *rdev); 727 int si_vm_init(struct radeon_device *rdev); 728 void si_vm_fini(struct radeon_device *rdev); 729 void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 730 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 731 int si_copy_dma(struct radeon_device *rdev, 732 uint64_t src_offset, uint64_t dst_offset, 733 unsigned num_gpu_pages, 734 struct radeon_fence **fence); 735 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode); 736 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock); 737 u32 si_get_csb_size(struct radeon_device *rdev); 738 void si_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer); 739 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 740 u32 max_voltage_steps, 741 struct atom_voltage_table *voltage_table); 742 u32 si_gpu_check_soft_reset(struct radeon_device *rdev); 743 744 void si_dma_vm_copy_pages(struct radeon_device *rdev, 745 struct radeon_ib *ib, 746 uint64_t pe, uint64_t src, 747 unsigned count); 748 void si_dma_vm_write_pages(struct radeon_device *rdev, 749 struct radeon_ib *ib, 750 uint64_t pe, 751 uint64_t addr, unsigned count, 752 uint32_t incr, uint32_t flags); 753 void si_dma_vm_set_pages(struct radeon_device *rdev, 754 struct radeon_ib *ib, 755 uint64_t pe, 756 uint64_t addr, unsigned count, 757 uint32_t incr, uint32_t flags); 758 759 void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 760 u32 si_get_xclk(struct radeon_device *rdev); 761 uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev); 762 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 763 int si_get_temp(struct radeon_device *rdev); 764 void si_rlc_fini(struct radeon_device *rdev); 765 int si_rlc_init(struct radeon_device *rdev); 766 void si_rlc_reset(struct radeon_device *rdev); 767 int si_mc_load_microcode(struct radeon_device *rdev); 768 void si_vram_gtt_location(struct radeon_device *rdev, 769 struct radeon_mc *mc); 770 void si_init_uvd_internal_cg(struct radeon_device *rdev); 771 int si_dpm_init(struct radeon_device *rdev); 772 void si_dpm_setup_asic(struct radeon_device *rdev); 773 int si_dpm_enable(struct radeon_device *rdev); 774 int si_dpm_late_enable(struct radeon_device *rdev); 775 void si_dpm_disable(struct radeon_device *rdev); 776 int si_dpm_pre_set_power_state(struct radeon_device *rdev); 777 int si_dpm_set_power_state(struct radeon_device *rdev); 778 void si_dpm_post_set_power_state(struct radeon_device *rdev); 779 void si_dpm_fini(struct radeon_device *rdev); 780 void si_dpm_display_configuration_changed(struct radeon_device *rdev); 781 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 782 struct seq_file *m); 783 int si_dpm_force_performance_level(struct radeon_device *rdev, 784 enum radeon_dpm_forced_level level); 785 786 /* DCE8 - CIK */ 787 void dce8_bandwidth_update(struct radeon_device *rdev); 788 789 /* 790 * cik 791 */ 792 u32 cik_get_csb_size(struct radeon_device *rdev); 793 void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer); 794 uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev); 795 u32 cik_get_xclk(struct radeon_device *rdev); 796 uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg); 797 void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 798 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 799 int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk); 800 void cik_init_cp_pg_table(struct radeon_device *rdev); 801 void cik_update_cg(struct radeon_device *rdev, 802 u32 block, bool enable); 803 void cik_enter_rlc_safe_mode(struct radeon_device *rdev); 804 void cik_exit_rlc_safe_mode(struct radeon_device *rdev); 805 int ci_mc_load_microcode(struct radeon_device *rdev); 806 void cik_sdma_fence_ring_emit(struct radeon_device *rdev, 807 struct radeon_fence *fence); 808 bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev, 809 struct radeon_ring *ring, 810 struct radeon_semaphore *semaphore, 811 bool emit_wait); 812 void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 813 int cik_copy_dma(struct radeon_device *rdev, 814 uint64_t src_offset, uint64_t dst_offset, 815 unsigned num_gpu_pages, 816 struct radeon_fence **fence); 817 int cik_copy_cpdma(struct radeon_device *rdev, 818 uint64_t src_offset, uint64_t dst_offset, 819 unsigned num_gpu_pages, 820 struct radeon_fence **fence); 821 int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 822 int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 823 bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 824 void cik_fence_gfx_ring_emit(struct radeon_device *rdev, 825 struct radeon_fence *fence); 826 void cik_fence_compute_ring_emit(struct radeon_device *rdev, 827 struct radeon_fence *fence); 828 bool cik_semaphore_ring_emit(struct radeon_device *rdev, 829 struct radeon_ring *cp, 830 struct radeon_semaphore *semaphore, 831 bool emit_wait); 832 void cik_pcie_gart_tlb_flush(struct radeon_device *rdev); 833 int cik_init(struct radeon_device *rdev); 834 void cik_fini(struct radeon_device *rdev); 835 int cik_suspend(struct radeon_device *rdev); 836 int cik_resume(struct radeon_device *rdev); 837 bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 838 int cik_asic_reset(struct radeon_device *rdev); 839 void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 840 int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 841 int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 842 int cik_irq_set(struct radeon_device *rdev); 843 irqreturn_t cik_irq_process(struct radeon_device *rdev); 844 int cik_vm_init(struct radeon_device *rdev); 845 void cik_vm_fini(struct radeon_device *rdev); 846 void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 847 848 void cik_sdma_vm_copy_pages(struct radeon_device *rdev, 849 struct radeon_ib *ib, 850 uint64_t pe, uint64_t src, 851 unsigned count); 852 void cik_sdma_vm_write_pages(struct radeon_device *rdev, 853 struct radeon_ib *ib, 854 uint64_t pe, 855 uint64_t addr, unsigned count, 856 uint32_t incr, uint32_t flags); 857 void cik_sdma_vm_set_pages(struct radeon_device *rdev, 858 struct radeon_ib *ib, 859 uint64_t pe, 860 uint64_t addr, unsigned count, 861 uint32_t incr, uint32_t flags); 862 void cik_sdma_vm_pad_ib(struct radeon_ib *ib); 863 864 void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 865 int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 866 u32 cik_gfx_get_rptr(struct radeon_device *rdev, 867 struct radeon_ring *ring); 868 u32 cik_gfx_get_wptr(struct radeon_device *rdev, 869 struct radeon_ring *ring); 870 void cik_gfx_set_wptr(struct radeon_device *rdev, 871 struct radeon_ring *ring); 872 u32 cik_compute_get_rptr(struct radeon_device *rdev, 873 struct radeon_ring *ring); 874 u32 cik_compute_get_wptr(struct radeon_device *rdev, 875 struct radeon_ring *ring); 876 void cik_compute_set_wptr(struct radeon_device *rdev, 877 struct radeon_ring *ring); 878 u32 cik_sdma_get_rptr(struct radeon_device *rdev, 879 struct radeon_ring *ring); 880 u32 cik_sdma_get_wptr(struct radeon_device *rdev, 881 struct radeon_ring *ring); 882 void cik_sdma_set_wptr(struct radeon_device *rdev, 883 struct radeon_ring *ring); 884 bool cik_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 885 void cik_fence_ring_emit(struct radeon_device *rdev, 886 struct radeon_fence *fence); 887 u32 cik_gpu_check_soft_reset(struct radeon_device *rdev); 888 void cik_sdma_enable(struct radeon_device *rdev, bool enable); 889 int cik_sdma_resume(struct radeon_device *rdev); 890 void cik_sdma_fini(struct radeon_device *rdev); 891 int ci_get_temp(struct radeon_device *rdev); 892 int kv_get_temp(struct radeon_device *rdev); 893 894 int ci_dpm_init(struct radeon_device *rdev); 895 int ci_dpm_enable(struct radeon_device *rdev); 896 int ci_dpm_late_enable(struct radeon_device *rdev); 897 void ci_dpm_disable(struct radeon_device *rdev); 898 int ci_dpm_pre_set_power_state(struct radeon_device *rdev); 899 int ci_dpm_set_power_state(struct radeon_device *rdev); 900 void ci_dpm_post_set_power_state(struct radeon_device *rdev); 901 void ci_dpm_setup_asic(struct radeon_device *rdev); 902 void ci_dpm_display_configuration_changed(struct radeon_device *rdev); 903 void ci_dpm_fini(struct radeon_device *rdev); 904 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low); 905 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low); 906 void ci_dpm_print_power_state(struct radeon_device *rdev, 907 struct radeon_ps *ps); 908 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 909 struct seq_file *m); 910 int ci_dpm_force_performance_level(struct radeon_device *rdev, 911 enum radeon_dpm_forced_level level); 912 bool ci_dpm_vblank_too_short(struct radeon_device *rdev); 913 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate); 914 915 int kv_dpm_init(struct radeon_device *rdev); 916 int kv_dpm_enable(struct radeon_device *rdev); 917 int kv_dpm_late_enable(struct radeon_device *rdev); 918 void kv_dpm_disable(struct radeon_device *rdev); 919 int kv_dpm_pre_set_power_state(struct radeon_device *rdev); 920 int kv_dpm_set_power_state(struct radeon_device *rdev); 921 void kv_dpm_post_set_power_state(struct radeon_device *rdev); 922 void kv_dpm_setup_asic(struct radeon_device *rdev); 923 void kv_dpm_display_configuration_changed(struct radeon_device *rdev); 924 void kv_dpm_fini(struct radeon_device *rdev); 925 u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low); 926 u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low); 927 void kv_dpm_print_power_state(struct radeon_device *rdev, 928 struct radeon_ps *ps); 929 void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 930 struct seq_file *m); 931 int kv_dpm_force_performance_level(struct radeon_device *rdev, 932 enum radeon_dpm_forced_level level); 933 void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate); 934 void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable); 935 936 /* uvd v1.0 */ 937 uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev, 938 struct radeon_ring *ring); 939 uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev, 940 struct radeon_ring *ring); 941 void uvd_v1_0_set_wptr(struct radeon_device *rdev, 942 struct radeon_ring *ring); 943 944 int uvd_v1_0_init(struct radeon_device *rdev); 945 void uvd_v1_0_fini(struct radeon_device *rdev); 946 int uvd_v1_0_start(struct radeon_device *rdev); 947 void uvd_v1_0_stop(struct radeon_device *rdev); 948 949 int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 950 int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 951 bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev, 952 struct radeon_ring *ring, 953 struct radeon_semaphore *semaphore, 954 bool emit_wait); 955 void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 956 957 /* uvd v2.2 */ 958 int uvd_v2_2_resume(struct radeon_device *rdev); 959 void uvd_v2_2_fence_emit(struct radeon_device *rdev, 960 struct radeon_fence *fence); 961 962 /* uvd v3.1 */ 963 bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev, 964 struct radeon_ring *ring, 965 struct radeon_semaphore *semaphore, 966 bool emit_wait); 967 968 /* uvd v4.2 */ 969 int uvd_v4_2_resume(struct radeon_device *rdev); 970 971 /* vce v1.0 */ 972 uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev, 973 struct radeon_ring *ring); 974 uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev, 975 struct radeon_ring *ring); 976 void vce_v1_0_set_wptr(struct radeon_device *rdev, 977 struct radeon_ring *ring); 978 int vce_v1_0_init(struct radeon_device *rdev); 979 int vce_v1_0_start(struct radeon_device *rdev); 980 981 /* vce v2.0 */ 982 int vce_v2_0_resume(struct radeon_device *rdev); 983 void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable); 984 985 #endif 986