1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_ASIC_H__ 29 #define __RADEON_ASIC_H__ 30 31 /* 32 * common functions 33 */ 34 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); 35 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 36 uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); 37 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 38 39 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); 40 void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 41 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); 42 void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); 43 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 44 45 void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); 46 u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder); 47 void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); 48 u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder); 49 50 /* 51 * r100,rv100,rs100,rv200,rs200 52 */ 53 struct r100_mc_save { 54 u32 GENMO_WT; 55 u32 CRTC_EXT_CNTL; 56 u32 CRTC_GEN_CNTL; 57 u32 CRTC2_GEN_CNTL; 58 u32 CUR_OFFSET; 59 u32 CUR2_OFFSET; 60 }; 61 int r100_init(struct radeon_device *rdev); 62 void r100_fini(struct radeon_device *rdev); 63 int r100_suspend(struct radeon_device *rdev); 64 int r100_resume(struct radeon_device *rdev); 65 void r100_vga_set_state(struct radeon_device *rdev, bool state); 66 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 67 int r100_asic_reset(struct radeon_device *rdev); 68 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); 69 void r100_pci_gart_tlb_flush(struct radeon_device *rdev); 70 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 71 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 72 int r100_irq_set(struct radeon_device *rdev); 73 irqreturn_t r100_irq_process(struct radeon_device *rdev); 74 void r100_fence_ring_emit(struct radeon_device *rdev, 75 struct radeon_fence *fence); 76 void r100_semaphore_ring_emit(struct radeon_device *rdev, 77 struct radeon_ring *cp, 78 struct radeon_semaphore *semaphore, 79 bool emit_wait); 80 int r100_cs_parse(struct radeon_cs_parser *p); 81 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 82 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); 83 int r100_copy_blit(struct radeon_device *rdev, 84 uint64_t src_offset, 85 uint64_t dst_offset, 86 unsigned num_gpu_pages, 87 struct radeon_fence **fence); 88 int r100_set_surface_reg(struct radeon_device *rdev, int reg, 89 uint32_t tiling_flags, uint32_t pitch, 90 uint32_t offset, uint32_t obj_size); 91 void r100_clear_surface_reg(struct radeon_device *rdev, int reg); 92 void r100_bandwidth_update(struct radeon_device *rdev); 93 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 94 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 95 void r100_hpd_init(struct radeon_device *rdev); 96 void r100_hpd_fini(struct radeon_device *rdev); 97 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 98 void r100_hpd_set_polarity(struct radeon_device *rdev, 99 enum radeon_hpd_id hpd); 100 int r100_debugfs_rbbm_init(struct radeon_device *rdev); 101 int r100_debugfs_cp_init(struct radeon_device *rdev); 102 void r100_cp_disable(struct radeon_device *rdev); 103 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); 104 void r100_cp_fini(struct radeon_device *rdev); 105 int r100_pci_gart_init(struct radeon_device *rdev); 106 void r100_pci_gart_fini(struct radeon_device *rdev); 107 int r100_pci_gart_enable(struct radeon_device *rdev); 108 void r100_pci_gart_disable(struct radeon_device *rdev); 109 int r100_debugfs_mc_info_init(struct radeon_device *rdev); 110 int r100_gui_wait_for_idle(struct radeon_device *rdev); 111 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 112 void r100_irq_disable(struct radeon_device *rdev); 113 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); 114 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); 115 void r100_vram_init_sizes(struct radeon_device *rdev); 116 int r100_cp_reset(struct radeon_device *rdev); 117 void r100_vga_render_disable(struct radeon_device *rdev); 118 void r100_restore_sanity(struct radeon_device *rdev); 119 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 120 struct radeon_cs_packet *pkt, 121 struct radeon_bo *robj); 122 int r100_cs_parse_packet0(struct radeon_cs_parser *p, 123 struct radeon_cs_packet *pkt, 124 const unsigned *auth, unsigned n, 125 radeon_packet0_check_t check); 126 int r100_cs_packet_parse(struct radeon_cs_parser *p, 127 struct radeon_cs_packet *pkt, 128 unsigned idx); 129 void r100_enable_bm(struct radeon_device *rdev); 130 void r100_set_common_regs(struct radeon_device *rdev); 131 void r100_bm_disable(struct radeon_device *rdev); 132 extern bool r100_gui_idle(struct radeon_device *rdev); 133 extern void r100_pm_misc(struct radeon_device *rdev); 134 extern void r100_pm_prepare(struct radeon_device *rdev); 135 extern void r100_pm_finish(struct radeon_device *rdev); 136 extern void r100_pm_init_profile(struct radeon_device *rdev); 137 extern void r100_pm_get_dynpm_state(struct radeon_device *rdev); 138 extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc); 139 extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 140 extern void r100_post_page_flip(struct radeon_device *rdev, int crtc); 141 extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc); 142 extern int r100_mc_wait_for_idle(struct radeon_device *rdev); 143 144 /* 145 * r200,rv250,rs300,rv280 146 */ 147 extern int r200_copy_dma(struct radeon_device *rdev, 148 uint64_t src_offset, 149 uint64_t dst_offset, 150 unsigned num_gpu_pages, 151 struct radeon_fence **fence); 152 void r200_set_safe_registers(struct radeon_device *rdev); 153 154 /* 155 * r300,r350,rv350,rv380 156 */ 157 extern int r300_init(struct radeon_device *rdev); 158 extern void r300_fini(struct radeon_device *rdev); 159 extern int r300_suspend(struct radeon_device *rdev); 160 extern int r300_resume(struct radeon_device *rdev); 161 extern int r300_asic_reset(struct radeon_device *rdev); 162 extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 163 extern void r300_fence_ring_emit(struct radeon_device *rdev, 164 struct radeon_fence *fence); 165 extern int r300_cs_parse(struct radeon_cs_parser *p); 166 extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); 167 extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 168 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); 169 extern int rv370_get_pcie_lanes(struct radeon_device *rdev); 170 extern void r300_set_reg_safe(struct radeon_device *rdev); 171 extern void r300_mc_program(struct radeon_device *rdev); 172 extern void r300_mc_init(struct radeon_device *rdev); 173 extern void r300_clock_startup(struct radeon_device *rdev); 174 extern int r300_mc_wait_for_idle(struct radeon_device *rdev); 175 extern int rv370_pcie_gart_init(struct radeon_device *rdev); 176 extern void rv370_pcie_gart_fini(struct radeon_device *rdev); 177 extern int rv370_pcie_gart_enable(struct radeon_device *rdev); 178 extern void rv370_pcie_gart_disable(struct radeon_device *rdev); 179 180 /* 181 * r420,r423,rv410 182 */ 183 extern int r420_init(struct radeon_device *rdev); 184 extern void r420_fini(struct radeon_device *rdev); 185 extern int r420_suspend(struct radeon_device *rdev); 186 extern int r420_resume(struct radeon_device *rdev); 187 extern void r420_pm_init_profile(struct radeon_device *rdev); 188 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); 189 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 190 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); 191 extern void r420_pipes_init(struct radeon_device *rdev); 192 193 /* 194 * rs400,rs480 195 */ 196 extern int rs400_init(struct radeon_device *rdev); 197 extern void rs400_fini(struct radeon_device *rdev); 198 extern int rs400_suspend(struct radeon_device *rdev); 199 extern int rs400_resume(struct radeon_device *rdev); 200 void rs400_gart_tlb_flush(struct radeon_device *rdev); 201 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 202 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); 203 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 204 int rs400_gart_init(struct radeon_device *rdev); 205 int rs400_gart_enable(struct radeon_device *rdev); 206 void rs400_gart_adjust_size(struct radeon_device *rdev); 207 void rs400_gart_disable(struct radeon_device *rdev); 208 void rs400_gart_fini(struct radeon_device *rdev); 209 extern int rs400_mc_wait_for_idle(struct radeon_device *rdev); 210 211 /* 212 * rs600. 213 */ 214 extern int rs600_asic_reset(struct radeon_device *rdev); 215 extern int rs600_init(struct radeon_device *rdev); 216 extern void rs600_fini(struct radeon_device *rdev); 217 extern int rs600_suspend(struct radeon_device *rdev); 218 extern int rs600_resume(struct radeon_device *rdev); 219 int rs600_irq_set(struct radeon_device *rdev); 220 irqreturn_t rs600_irq_process(struct radeon_device *rdev); 221 void rs600_irq_disable(struct radeon_device *rdev); 222 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); 223 void rs600_gart_tlb_flush(struct radeon_device *rdev); 224 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 225 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); 226 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 227 void rs600_bandwidth_update(struct radeon_device *rdev); 228 void rs600_hpd_init(struct radeon_device *rdev); 229 void rs600_hpd_fini(struct radeon_device *rdev); 230 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 231 void rs600_hpd_set_polarity(struct radeon_device *rdev, 232 enum radeon_hpd_id hpd); 233 extern void rs600_pm_misc(struct radeon_device *rdev); 234 extern void rs600_pm_prepare(struct radeon_device *rdev); 235 extern void rs600_pm_finish(struct radeon_device *rdev); 236 extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc); 237 extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 238 extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc); 239 void rs600_set_safe_registers(struct radeon_device *rdev); 240 extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc); 241 extern int rs600_mc_wait_for_idle(struct radeon_device *rdev); 242 243 /* 244 * rs690,rs740 245 */ 246 int rs690_init(struct radeon_device *rdev); 247 void rs690_fini(struct radeon_device *rdev); 248 int rs690_resume(struct radeon_device *rdev); 249 int rs690_suspend(struct radeon_device *rdev); 250 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); 251 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 252 void rs690_bandwidth_update(struct radeon_device *rdev); 253 void rs690_line_buffer_adjust(struct radeon_device *rdev, 254 struct drm_display_mode *mode1, 255 struct drm_display_mode *mode2); 256 extern int rs690_mc_wait_for_idle(struct radeon_device *rdev); 257 258 /* 259 * rv515 260 */ 261 struct rv515_mc_save { 262 u32 vga_render_control; 263 u32 vga_hdp_control; 264 bool crtc_enabled[2]; 265 }; 266 267 int rv515_init(struct radeon_device *rdev); 268 void rv515_fini(struct radeon_device *rdev); 269 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); 270 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 271 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 272 void rv515_bandwidth_update(struct radeon_device *rdev); 273 int rv515_resume(struct radeon_device *rdev); 274 int rv515_suspend(struct radeon_device *rdev); 275 void rv515_bandwidth_avivo_update(struct radeon_device *rdev); 276 void rv515_vga_render_disable(struct radeon_device *rdev); 277 void rv515_set_safe_registers(struct radeon_device *rdev); 278 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); 279 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); 280 void rv515_clock_startup(struct radeon_device *rdev); 281 void rv515_debugfs(struct radeon_device *rdev); 282 int rv515_mc_wait_for_idle(struct radeon_device *rdev); 283 284 /* 285 * r520,rv530,rv560,rv570,r580 286 */ 287 int r520_init(struct radeon_device *rdev); 288 int r520_resume(struct radeon_device *rdev); 289 int r520_mc_wait_for_idle(struct radeon_device *rdev); 290 291 /* 292 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 293 */ 294 int r600_init(struct radeon_device *rdev); 295 void r600_fini(struct radeon_device *rdev); 296 int r600_suspend(struct radeon_device *rdev); 297 int r600_resume(struct radeon_device *rdev); 298 void r600_vga_set_state(struct radeon_device *rdev, bool state); 299 int r600_wb_init(struct radeon_device *rdev); 300 void r600_wb_fini(struct radeon_device *rdev); 301 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); 302 uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); 303 void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 304 int r600_cs_parse(struct radeon_cs_parser *p); 305 int r600_dma_cs_parse(struct radeon_cs_parser *p); 306 int r600_dma_cs_next_reloc(struct radeon_cs_parser *p, 307 struct radeon_cs_reloc **cs_reloc); 308 void r600_fence_ring_emit(struct radeon_device *rdev, 309 struct radeon_fence *fence); 310 void r600_semaphore_ring_emit(struct radeon_device *rdev, 311 struct radeon_ring *cp, 312 struct radeon_semaphore *semaphore, 313 bool emit_wait); 314 void r600_dma_fence_ring_emit(struct radeon_device *rdev, 315 struct radeon_fence *fence); 316 void r600_dma_semaphore_ring_emit(struct radeon_device *rdev, 317 struct radeon_ring *ring, 318 struct radeon_semaphore *semaphore, 319 bool emit_wait); 320 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 321 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 322 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 323 int r600_asic_reset(struct radeon_device *rdev); 324 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 325 uint32_t tiling_flags, uint32_t pitch, 326 uint32_t offset, uint32_t obj_size); 327 void r600_clear_surface_reg(struct radeon_device *rdev, int reg); 328 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 329 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 330 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 331 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 332 int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 333 int r600_uvd_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 334 int r600_copy_blit(struct radeon_device *rdev, 335 uint64_t src_offset, uint64_t dst_offset, 336 unsigned num_gpu_pages, struct radeon_fence **fence); 337 int r600_copy_cpdma(struct radeon_device *rdev, 338 uint64_t src_offset, uint64_t dst_offset, 339 unsigned num_gpu_pages, struct radeon_fence **fence); 340 int r600_copy_dma(struct radeon_device *rdev, 341 uint64_t src_offset, uint64_t dst_offset, 342 unsigned num_gpu_pages, struct radeon_fence **fence); 343 void r600_hpd_init(struct radeon_device *rdev); 344 void r600_hpd_fini(struct radeon_device *rdev); 345 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 346 void r600_hpd_set_polarity(struct radeon_device *rdev, 347 enum radeon_hpd_id hpd); 348 extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo); 349 extern bool r600_gui_idle(struct radeon_device *rdev); 350 extern void r600_pm_misc(struct radeon_device *rdev); 351 extern void r600_pm_init_profile(struct radeon_device *rdev); 352 extern void rs780_pm_init_profile(struct radeon_device *rdev); 353 extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg); 354 extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 355 extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); 356 extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes); 357 extern int r600_get_pcie_lanes(struct radeon_device *rdev); 358 bool r600_card_posted(struct radeon_device *rdev); 359 void r600_cp_stop(struct radeon_device *rdev); 360 int r600_cp_start(struct radeon_device *rdev); 361 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size); 362 int r600_cp_resume(struct radeon_device *rdev); 363 void r600_cp_fini(struct radeon_device *rdev); 364 int r600_count_pipe_bits(uint32_t val); 365 int r600_mc_wait_for_idle(struct radeon_device *rdev); 366 int r600_pcie_gart_init(struct radeon_device *rdev); 367 void r600_scratch_init(struct radeon_device *rdev); 368 int r600_blit_init(struct radeon_device *rdev); 369 void r600_blit_fini(struct radeon_device *rdev); 370 int r600_init_microcode(struct radeon_device *rdev); 371 void r600_fini_microcode(struct radeon_device *rdev); 372 /* r600 irq */ 373 irqreturn_t r600_irq_process(struct radeon_device *rdev); 374 int r600_irq_init(struct radeon_device *rdev); 375 void r600_irq_fini(struct radeon_device *rdev); 376 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); 377 int r600_irq_set(struct radeon_device *rdev); 378 void r600_irq_suspend(struct radeon_device *rdev); 379 void r600_disable_interrupts(struct radeon_device *rdev); 380 void r600_rlc_stop(struct radeon_device *rdev); 381 /* r600 audio */ 382 int r600_audio_init(struct radeon_device *rdev); 383 struct r600_audio r600_audio_status(struct radeon_device *rdev); 384 void r600_audio_fini(struct radeon_device *rdev); 385 void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock); 386 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); 387 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); 388 void r600_hdmi_enable(struct drm_encoder *encoder, bool enable); 389 void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 390 /* r600 blit */ 391 int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages, 392 struct radeon_fence **fence, struct radeon_sa_bo **vb, 393 struct radeon_semaphore **sem); 394 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence, 395 struct radeon_sa_bo *vb, struct radeon_semaphore *sem); 396 void r600_kms_blit_copy(struct radeon_device *rdev, 397 u64 src_gpu_addr, u64 dst_gpu_addr, 398 unsigned num_gpu_pages, 399 struct radeon_sa_bo *vb); 400 u32 r600_get_xclk(struct radeon_device *rdev); 401 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev); 402 int rv6xx_get_temp(struct radeon_device *rdev); 403 int r600_dpm_pre_set_power_state(struct radeon_device *rdev); 404 void r600_dpm_post_set_power_state(struct radeon_device *rdev); 405 /* rv6xx dpm */ 406 int rv6xx_dpm_init(struct radeon_device *rdev); 407 int rv6xx_dpm_enable(struct radeon_device *rdev); 408 void rv6xx_dpm_disable(struct radeon_device *rdev); 409 int rv6xx_dpm_set_power_state(struct radeon_device *rdev); 410 void rv6xx_setup_asic(struct radeon_device *rdev); 411 void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev); 412 void rv6xx_dpm_fini(struct radeon_device *rdev); 413 u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low); 414 u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low); 415 void rv6xx_dpm_print_power_state(struct radeon_device *rdev, 416 struct radeon_ps *ps); 417 void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 418 struct seq_file *m); 419 int rv6xx_dpm_force_performance_level(struct radeon_device *rdev, 420 enum radeon_dpm_forced_level level); 421 /* rs780 dpm */ 422 int rs780_dpm_init(struct radeon_device *rdev); 423 int rs780_dpm_enable(struct radeon_device *rdev); 424 void rs780_dpm_disable(struct radeon_device *rdev); 425 int rs780_dpm_set_power_state(struct radeon_device *rdev); 426 void rs780_dpm_setup_asic(struct radeon_device *rdev); 427 void rs780_dpm_display_configuration_changed(struct radeon_device *rdev); 428 void rs780_dpm_fini(struct radeon_device *rdev); 429 u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low); 430 u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low); 431 void rs780_dpm_print_power_state(struct radeon_device *rdev, 432 struct radeon_ps *ps); 433 void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 434 struct seq_file *m); 435 436 /* uvd */ 437 int r600_uvd_init(struct radeon_device *rdev); 438 int r600_uvd_rbc_start(struct radeon_device *rdev); 439 void r600_uvd_stop(struct radeon_device *rdev); 440 int r600_uvd_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 441 void r600_uvd_fence_emit(struct radeon_device *rdev, 442 struct radeon_fence *fence); 443 void r600_uvd_semaphore_emit(struct radeon_device *rdev, 444 struct radeon_ring *ring, 445 struct radeon_semaphore *semaphore, 446 bool emit_wait); 447 void r600_uvd_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 448 449 /* 450 * rv770,rv730,rv710,rv740 451 */ 452 int rv770_init(struct radeon_device *rdev); 453 void rv770_fini(struct radeon_device *rdev); 454 int rv770_suspend(struct radeon_device *rdev); 455 int rv770_resume(struct radeon_device *rdev); 456 void rv770_pm_misc(struct radeon_device *rdev); 457 u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 458 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 459 void r700_cp_stop(struct radeon_device *rdev); 460 void r700_cp_fini(struct radeon_device *rdev); 461 int rv770_copy_dma(struct radeon_device *rdev, 462 uint64_t src_offset, uint64_t dst_offset, 463 unsigned num_gpu_pages, 464 struct radeon_fence **fence); 465 u32 rv770_get_xclk(struct radeon_device *rdev); 466 int rv770_uvd_resume(struct radeon_device *rdev); 467 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 468 int rv770_get_temp(struct radeon_device *rdev); 469 /* rv7xx pm */ 470 int rv770_dpm_init(struct radeon_device *rdev); 471 int rv770_dpm_enable(struct radeon_device *rdev); 472 void rv770_dpm_disable(struct radeon_device *rdev); 473 int rv770_dpm_set_power_state(struct radeon_device *rdev); 474 void rv770_dpm_setup_asic(struct radeon_device *rdev); 475 void rv770_dpm_display_configuration_changed(struct radeon_device *rdev); 476 void rv770_dpm_fini(struct radeon_device *rdev); 477 u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low); 478 u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low); 479 void rv770_dpm_print_power_state(struct radeon_device *rdev, 480 struct radeon_ps *ps); 481 void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 482 struct seq_file *m); 483 bool rv770_dpm_vblank_too_short(struct radeon_device *rdev); 484 485 /* 486 * evergreen 487 */ 488 struct evergreen_mc_save { 489 u32 vga_render_control; 490 u32 vga_hdp_control; 491 bool crtc_enabled[RADEON_MAX_CRTCS]; 492 }; 493 494 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); 495 int evergreen_init(struct radeon_device *rdev); 496 void evergreen_fini(struct radeon_device *rdev); 497 int evergreen_suspend(struct radeon_device *rdev); 498 int evergreen_resume(struct radeon_device *rdev); 499 bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 500 bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 501 int evergreen_asic_reset(struct radeon_device *rdev); 502 void evergreen_bandwidth_update(struct radeon_device *rdev); 503 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 504 void evergreen_hpd_init(struct radeon_device *rdev); 505 void evergreen_hpd_fini(struct radeon_device *rdev); 506 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 507 void evergreen_hpd_set_polarity(struct radeon_device *rdev, 508 enum radeon_hpd_id hpd); 509 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); 510 int evergreen_irq_set(struct radeon_device *rdev); 511 irqreturn_t evergreen_irq_process(struct radeon_device *rdev); 512 extern int evergreen_cs_parse(struct radeon_cs_parser *p); 513 extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p); 514 extern void evergreen_pm_misc(struct radeon_device *rdev); 515 extern void evergreen_pm_prepare(struct radeon_device *rdev); 516 extern void evergreen_pm_finish(struct radeon_device *rdev); 517 extern void sumo_pm_init_profile(struct radeon_device *rdev); 518 extern void btc_pm_init_profile(struct radeon_device *rdev); 519 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 520 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 521 extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc); 522 extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 523 extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc); 524 extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc); 525 void evergreen_disable_interrupt_state(struct radeon_device *rdev); 526 int evergreen_blit_init(struct radeon_device *rdev); 527 int evergreen_mc_wait_for_idle(struct radeon_device *rdev); 528 void evergreen_dma_fence_ring_emit(struct radeon_device *rdev, 529 struct radeon_fence *fence); 530 void evergreen_dma_ring_ib_execute(struct radeon_device *rdev, 531 struct radeon_ib *ib); 532 int evergreen_copy_dma(struct radeon_device *rdev, 533 uint64_t src_offset, uint64_t dst_offset, 534 unsigned num_gpu_pages, 535 struct radeon_fence **fence); 536 void evergreen_pcie_gen2_enable(struct radeon_device *rdev); 537 void evergreen_print_gpu_status_regs(struct radeon_device *rdev); 538 void evergreen_program_aspm(struct radeon_device *rdev); 539 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev); 540 u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev); 541 void sumo_rlc_fini(struct radeon_device *rdev); 542 int sumo_rlc_init(struct radeon_device *rdev); 543 int evergreen_rlc_resume(struct radeon_device *rdev); 544 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); 545 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); 546 void evergreen_mc_program(struct radeon_device *rdev); 547 int evergreen_mc_init(struct radeon_device *rdev); 548 void evergreen_irq_suspend(struct radeon_device *rdev); 549 bool evergreen_is_display_hung(struct radeon_device *rdev); 550 void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable); 551 void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 552 int evergreen_get_temp(struct radeon_device *rdev); 553 int sumo_get_temp(struct radeon_device *rdev); 554 int tn_get_temp(struct radeon_device *rdev); 555 int cypress_dpm_init(struct radeon_device *rdev); 556 void cypress_dpm_setup_asic(struct radeon_device *rdev); 557 int cypress_dpm_enable(struct radeon_device *rdev); 558 void cypress_dpm_disable(struct radeon_device *rdev); 559 int cypress_dpm_set_power_state(struct radeon_device *rdev); 560 void cypress_dpm_display_configuration_changed(struct radeon_device *rdev); 561 void cypress_dpm_fini(struct radeon_device *rdev); 562 bool cypress_dpm_vblank_too_short(struct radeon_device *rdev); 563 int btc_dpm_init(struct radeon_device *rdev); 564 void btc_dpm_setup_asic(struct radeon_device *rdev); 565 int btc_dpm_enable(struct radeon_device *rdev); 566 void btc_dpm_disable(struct radeon_device *rdev); 567 int btc_dpm_pre_set_power_state(struct radeon_device *rdev); 568 int btc_dpm_set_power_state(struct radeon_device *rdev); 569 void btc_dpm_post_set_power_state(struct radeon_device *rdev); 570 void btc_dpm_fini(struct radeon_device *rdev); 571 u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low); 572 u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low); 573 bool btc_dpm_vblank_too_short(struct radeon_device *rdev); 574 int sumo_dpm_init(struct radeon_device *rdev); 575 int sumo_dpm_enable(struct radeon_device *rdev); 576 void sumo_dpm_disable(struct radeon_device *rdev); 577 int sumo_dpm_pre_set_power_state(struct radeon_device *rdev); 578 int sumo_dpm_set_power_state(struct radeon_device *rdev); 579 void sumo_dpm_post_set_power_state(struct radeon_device *rdev); 580 void sumo_dpm_setup_asic(struct radeon_device *rdev); 581 void sumo_dpm_display_configuration_changed(struct radeon_device *rdev); 582 void sumo_dpm_fini(struct radeon_device *rdev); 583 u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low); 584 u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low); 585 void sumo_dpm_print_power_state(struct radeon_device *rdev, 586 struct radeon_ps *ps); 587 void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 588 struct seq_file *m); 589 int sumo_dpm_force_performance_level(struct radeon_device *rdev, 590 enum radeon_dpm_forced_level level); 591 592 /* 593 * cayman 594 */ 595 void cayman_fence_ring_emit(struct radeon_device *rdev, 596 struct radeon_fence *fence); 597 void cayman_uvd_semaphore_emit(struct radeon_device *rdev, 598 struct radeon_ring *ring, 599 struct radeon_semaphore *semaphore, 600 bool emit_wait); 601 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev); 602 int cayman_init(struct radeon_device *rdev); 603 void cayman_fini(struct radeon_device *rdev); 604 int cayman_suspend(struct radeon_device *rdev); 605 int cayman_resume(struct radeon_device *rdev); 606 int cayman_asic_reset(struct radeon_device *rdev); 607 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 608 int cayman_vm_init(struct radeon_device *rdev); 609 void cayman_vm_fini(struct radeon_device *rdev); 610 void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 611 uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags); 612 void cayman_vm_set_page(struct radeon_device *rdev, 613 struct radeon_ib *ib, 614 uint64_t pe, 615 uint64_t addr, unsigned count, 616 uint32_t incr, uint32_t flags); 617 void cayman_vm_decode_fault(struct radeon_device *rdev, 618 u32 status, u32 addr); 619 int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 620 int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 621 void cayman_dma_ring_ib_execute(struct radeon_device *rdev, 622 struct radeon_ib *ib); 623 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 624 bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 625 void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 626 extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev, 627 int ring, u32 cp_int_cntl); 628 629 int ni_dpm_init(struct radeon_device *rdev); 630 void ni_dpm_setup_asic(struct radeon_device *rdev); 631 int ni_dpm_enable(struct radeon_device *rdev); 632 void ni_dpm_disable(struct radeon_device *rdev); 633 int ni_dpm_pre_set_power_state(struct radeon_device *rdev); 634 int ni_dpm_set_power_state(struct radeon_device *rdev); 635 void ni_dpm_post_set_power_state(struct radeon_device *rdev); 636 void ni_dpm_fini(struct radeon_device *rdev); 637 u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low); 638 u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low); 639 void ni_dpm_print_power_state(struct radeon_device *rdev, 640 struct radeon_ps *ps); 641 void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 642 struct seq_file *m); 643 int ni_dpm_force_performance_level(struct radeon_device *rdev, 644 enum radeon_dpm_forced_level level); 645 //bool ni_dpm_vblank_too_short(struct radeon_device *rdev); 646 int trinity_dpm_init(struct radeon_device *rdev); 647 int trinity_dpm_enable(struct radeon_device *rdev); 648 void trinity_dpm_disable(struct radeon_device *rdev); 649 int trinity_dpm_pre_set_power_state(struct radeon_device *rdev); 650 int trinity_dpm_set_power_state(struct radeon_device *rdev); 651 void trinity_dpm_post_set_power_state(struct radeon_device *rdev); 652 void trinity_dpm_setup_asic(struct radeon_device *rdev); 653 void trinity_dpm_display_configuration_changed(struct radeon_device *rdev); 654 void trinity_dpm_fini(struct radeon_device *rdev); 655 u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low); 656 u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low); 657 void trinity_dpm_print_power_state(struct radeon_device *rdev, 658 struct radeon_ps *ps); 659 void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 660 struct seq_file *m); 661 int trinity_dpm_force_performance_level(struct radeon_device *rdev, 662 enum radeon_dpm_forced_level level); 663 664 /* DCE6 - SI */ 665 void dce6_bandwidth_update(struct radeon_device *rdev); 666 667 /* 668 * si 669 */ 670 void si_fence_ring_emit(struct radeon_device *rdev, 671 struct radeon_fence *fence); 672 void si_pcie_gart_tlb_flush(struct radeon_device *rdev); 673 int si_init(struct radeon_device *rdev); 674 void si_fini(struct radeon_device *rdev); 675 int si_suspend(struct radeon_device *rdev); 676 int si_resume(struct radeon_device *rdev); 677 bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 678 bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 679 int si_asic_reset(struct radeon_device *rdev); 680 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 681 int si_irq_set(struct radeon_device *rdev); 682 irqreturn_t si_irq_process(struct radeon_device *rdev); 683 int si_vm_init(struct radeon_device *rdev); 684 void si_vm_fini(struct radeon_device *rdev); 685 void si_vm_set_page(struct radeon_device *rdev, 686 struct radeon_ib *ib, 687 uint64_t pe, 688 uint64_t addr, unsigned count, 689 uint32_t incr, uint32_t flags); 690 void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 691 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 692 int si_copy_dma(struct radeon_device *rdev, 693 uint64_t src_offset, uint64_t dst_offset, 694 unsigned num_gpu_pages, 695 struct radeon_fence **fence); 696 void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 697 u32 si_get_xclk(struct radeon_device *rdev); 698 uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev); 699 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 700 int si_get_temp(struct radeon_device *rdev); 701 void si_rlc_fini(struct radeon_device *rdev); 702 int si_rlc_init(struct radeon_device *rdev); 703 void si_vram_gtt_location(struct radeon_device *rdev, 704 struct radeon_mc *mc); 705 int si_dpm_init(struct radeon_device *rdev); 706 void si_dpm_setup_asic(struct radeon_device *rdev); 707 int si_dpm_enable(struct radeon_device *rdev); 708 void si_dpm_disable(struct radeon_device *rdev); 709 int si_dpm_pre_set_power_state(struct radeon_device *rdev); 710 int si_dpm_set_power_state(struct radeon_device *rdev); 711 void si_dpm_post_set_power_state(struct radeon_device *rdev); 712 void si_dpm_fini(struct radeon_device *rdev); 713 void si_dpm_display_configuration_changed(struct radeon_device *rdev); 714 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 715 struct seq_file *m); 716 int si_dpm_force_performance_level(struct radeon_device *rdev, 717 enum radeon_dpm_forced_level level); 718 719 /* DCE8 - CIK */ 720 void dce8_bandwidth_update(struct radeon_device *rdev); 721 722 /* 723 * cik 724 */ 725 uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev); 726 u32 cik_get_xclk(struct radeon_device *rdev); 727 uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg); 728 void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 729 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 730 int cik_uvd_resume(struct radeon_device *rdev); 731 void cik_sdma_fence_ring_emit(struct radeon_device *rdev, 732 struct radeon_fence *fence); 733 void cik_sdma_semaphore_ring_emit(struct radeon_device *rdev, 734 struct radeon_ring *ring, 735 struct radeon_semaphore *semaphore, 736 bool emit_wait); 737 void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 738 int cik_copy_dma(struct radeon_device *rdev, 739 uint64_t src_offset, uint64_t dst_offset, 740 unsigned num_gpu_pages, 741 struct radeon_fence **fence); 742 int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 743 int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 744 bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 745 void cik_fence_gfx_ring_emit(struct radeon_device *rdev, 746 struct radeon_fence *fence); 747 void cik_fence_compute_ring_emit(struct radeon_device *rdev, 748 struct radeon_fence *fence); 749 void cik_semaphore_ring_emit(struct radeon_device *rdev, 750 struct radeon_ring *cp, 751 struct radeon_semaphore *semaphore, 752 bool emit_wait); 753 void cik_pcie_gart_tlb_flush(struct radeon_device *rdev); 754 int cik_init(struct radeon_device *rdev); 755 void cik_fini(struct radeon_device *rdev); 756 int cik_suspend(struct radeon_device *rdev); 757 int cik_resume(struct radeon_device *rdev); 758 bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 759 int cik_asic_reset(struct radeon_device *rdev); 760 void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 761 int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 762 int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 763 int cik_irq_set(struct radeon_device *rdev); 764 irqreturn_t cik_irq_process(struct radeon_device *rdev); 765 int cik_vm_init(struct radeon_device *rdev); 766 void cik_vm_fini(struct radeon_device *rdev); 767 void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 768 void cik_vm_set_page(struct radeon_device *rdev, 769 struct radeon_ib *ib, 770 uint64_t pe, 771 uint64_t addr, unsigned count, 772 uint32_t incr, uint32_t flags); 773 void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 774 int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 775 u32 cik_compute_ring_get_rptr(struct radeon_device *rdev, 776 struct radeon_ring *ring); 777 u32 cik_compute_ring_get_wptr(struct radeon_device *rdev, 778 struct radeon_ring *ring); 779 void cik_compute_ring_set_wptr(struct radeon_device *rdev, 780 struct radeon_ring *ring); 781 bool cik_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 782 void cik_fence_ring_emit(struct radeon_device *rdev, 783 struct radeon_fence *fence); 784 #endif 785