1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_ASIC_H__ 29 #define __RADEON_ASIC_H__ 30 31 /* 32 * common functions 33 */ 34 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); 35 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 36 uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); 37 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 38 39 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); 40 void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 41 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); 42 void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); 43 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 44 45 void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); 46 u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder); 47 void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); 48 u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder); 49 50 /* 51 * r100,rv100,rs100,rv200,rs200 52 */ 53 struct r100_mc_save { 54 u32 GENMO_WT; 55 u32 CRTC_EXT_CNTL; 56 u32 CRTC_GEN_CNTL; 57 u32 CRTC2_GEN_CNTL; 58 u32 CUR_OFFSET; 59 u32 CUR2_OFFSET; 60 }; 61 int r100_init(struct radeon_device *rdev); 62 void r100_fini(struct radeon_device *rdev); 63 int r100_suspend(struct radeon_device *rdev); 64 int r100_resume(struct radeon_device *rdev); 65 void r100_vga_set_state(struct radeon_device *rdev, bool state); 66 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 67 int r100_asic_reset(struct radeon_device *rdev); 68 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); 69 void r100_pci_gart_tlb_flush(struct radeon_device *rdev); 70 void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i, 71 uint64_t addr, uint32_t flags); 72 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 73 int r100_irq_set(struct radeon_device *rdev); 74 irqreturn_t r100_irq_process(struct radeon_device *rdev); 75 void r100_fence_ring_emit(struct radeon_device *rdev, 76 struct radeon_fence *fence); 77 bool r100_semaphore_ring_emit(struct radeon_device *rdev, 78 struct radeon_ring *cp, 79 struct radeon_semaphore *semaphore, 80 bool emit_wait); 81 int r100_cs_parse(struct radeon_cs_parser *p); 82 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 83 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); 84 struct radeon_fence *r100_copy_blit(struct radeon_device *rdev, 85 uint64_t src_offset, 86 uint64_t dst_offset, 87 unsigned num_gpu_pages, 88 struct reservation_object *resv); 89 int r100_set_surface_reg(struct radeon_device *rdev, int reg, 90 uint32_t tiling_flags, uint32_t pitch, 91 uint32_t offset, uint32_t obj_size); 92 void r100_clear_surface_reg(struct radeon_device *rdev, int reg); 93 void r100_bandwidth_update(struct radeon_device *rdev); 94 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 95 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 96 void r100_hpd_init(struct radeon_device *rdev); 97 void r100_hpd_fini(struct radeon_device *rdev); 98 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 99 void r100_hpd_set_polarity(struct radeon_device *rdev, 100 enum radeon_hpd_id hpd); 101 int r100_debugfs_rbbm_init(struct radeon_device *rdev); 102 int r100_debugfs_cp_init(struct radeon_device *rdev); 103 void r100_cp_disable(struct radeon_device *rdev); 104 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); 105 void r100_cp_fini(struct radeon_device *rdev); 106 int r100_pci_gart_init(struct radeon_device *rdev); 107 void r100_pci_gart_fini(struct radeon_device *rdev); 108 int r100_pci_gart_enable(struct radeon_device *rdev); 109 void r100_pci_gart_disable(struct radeon_device *rdev); 110 int r100_debugfs_mc_info_init(struct radeon_device *rdev); 111 int r100_gui_wait_for_idle(struct radeon_device *rdev); 112 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 113 void r100_irq_disable(struct radeon_device *rdev); 114 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); 115 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); 116 void r100_vram_init_sizes(struct radeon_device *rdev); 117 int r100_cp_reset(struct radeon_device *rdev); 118 void r100_vga_render_disable(struct radeon_device *rdev); 119 void r100_restore_sanity(struct radeon_device *rdev); 120 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 121 struct radeon_cs_packet *pkt, 122 struct radeon_bo *robj); 123 int r100_cs_parse_packet0(struct radeon_cs_parser *p, 124 struct radeon_cs_packet *pkt, 125 const unsigned *auth, unsigned n, 126 radeon_packet0_check_t check); 127 int r100_cs_packet_parse(struct radeon_cs_parser *p, 128 struct radeon_cs_packet *pkt, 129 unsigned idx); 130 void r100_enable_bm(struct radeon_device *rdev); 131 void r100_set_common_regs(struct radeon_device *rdev); 132 void r100_bm_disable(struct radeon_device *rdev); 133 extern bool r100_gui_idle(struct radeon_device *rdev); 134 extern void r100_pm_misc(struct radeon_device *rdev); 135 extern void r100_pm_prepare(struct radeon_device *rdev); 136 extern void r100_pm_finish(struct radeon_device *rdev); 137 extern void r100_pm_init_profile(struct radeon_device *rdev); 138 extern void r100_pm_get_dynpm_state(struct radeon_device *rdev); 139 extern void r100_page_flip(struct radeon_device *rdev, int crtc, 140 u64 crtc_base); 141 extern bool r100_page_flip_pending(struct radeon_device *rdev, int crtc); 142 extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc); 143 extern int r100_mc_wait_for_idle(struct radeon_device *rdev); 144 145 u32 r100_gfx_get_rptr(struct radeon_device *rdev, 146 struct radeon_ring *ring); 147 u32 r100_gfx_get_wptr(struct radeon_device *rdev, 148 struct radeon_ring *ring); 149 void r100_gfx_set_wptr(struct radeon_device *rdev, 150 struct radeon_ring *ring); 151 152 /* 153 * r200,rv250,rs300,rv280 154 */ 155 struct radeon_fence *r200_copy_dma(struct radeon_device *rdev, 156 uint64_t src_offset, 157 uint64_t dst_offset, 158 unsigned num_gpu_pages, 159 struct reservation_object *resv); 160 void r200_set_safe_registers(struct radeon_device *rdev); 161 162 /* 163 * r300,r350,rv350,rv380 164 */ 165 extern int r300_init(struct radeon_device *rdev); 166 extern void r300_fini(struct radeon_device *rdev); 167 extern int r300_suspend(struct radeon_device *rdev); 168 extern int r300_resume(struct radeon_device *rdev); 169 extern int r300_asic_reset(struct radeon_device *rdev); 170 extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 171 extern void r300_fence_ring_emit(struct radeon_device *rdev, 172 struct radeon_fence *fence); 173 extern int r300_cs_parse(struct radeon_cs_parser *p); 174 extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); 175 extern void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i, 176 uint64_t addr, uint32_t flags); 177 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); 178 extern int rv370_get_pcie_lanes(struct radeon_device *rdev); 179 extern void r300_set_reg_safe(struct radeon_device *rdev); 180 extern void r300_mc_program(struct radeon_device *rdev); 181 extern void r300_mc_init(struct radeon_device *rdev); 182 extern void r300_clock_startup(struct radeon_device *rdev); 183 extern int r300_mc_wait_for_idle(struct radeon_device *rdev); 184 extern int rv370_pcie_gart_init(struct radeon_device *rdev); 185 extern void rv370_pcie_gart_fini(struct radeon_device *rdev); 186 extern int rv370_pcie_gart_enable(struct radeon_device *rdev); 187 extern void rv370_pcie_gart_disable(struct radeon_device *rdev); 188 189 /* 190 * r420,r423,rv410 191 */ 192 extern int r420_init(struct radeon_device *rdev); 193 extern void r420_fini(struct radeon_device *rdev); 194 extern int r420_suspend(struct radeon_device *rdev); 195 extern int r420_resume(struct radeon_device *rdev); 196 extern void r420_pm_init_profile(struct radeon_device *rdev); 197 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); 198 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 199 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); 200 extern void r420_pipes_init(struct radeon_device *rdev); 201 202 /* 203 * rs400,rs480 204 */ 205 extern int rs400_init(struct radeon_device *rdev); 206 extern void rs400_fini(struct radeon_device *rdev); 207 extern int rs400_suspend(struct radeon_device *rdev); 208 extern int rs400_resume(struct radeon_device *rdev); 209 void rs400_gart_tlb_flush(struct radeon_device *rdev); 210 void rs400_gart_set_page(struct radeon_device *rdev, unsigned i, 211 uint64_t addr, uint32_t flags); 212 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); 213 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 214 int rs400_gart_init(struct radeon_device *rdev); 215 int rs400_gart_enable(struct radeon_device *rdev); 216 void rs400_gart_adjust_size(struct radeon_device *rdev); 217 void rs400_gart_disable(struct radeon_device *rdev); 218 void rs400_gart_fini(struct radeon_device *rdev); 219 extern int rs400_mc_wait_for_idle(struct radeon_device *rdev); 220 221 /* 222 * rs600. 223 */ 224 extern int rs600_asic_reset(struct radeon_device *rdev); 225 extern int rs600_init(struct radeon_device *rdev); 226 extern void rs600_fini(struct radeon_device *rdev); 227 extern int rs600_suspend(struct radeon_device *rdev); 228 extern int rs600_resume(struct radeon_device *rdev); 229 int rs600_irq_set(struct radeon_device *rdev); 230 irqreturn_t rs600_irq_process(struct radeon_device *rdev); 231 void rs600_irq_disable(struct radeon_device *rdev); 232 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); 233 void rs600_gart_tlb_flush(struct radeon_device *rdev); 234 void rs600_gart_set_page(struct radeon_device *rdev, unsigned i, 235 uint64_t addr, uint32_t flags); 236 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); 237 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 238 void rs600_bandwidth_update(struct radeon_device *rdev); 239 void rs600_hpd_init(struct radeon_device *rdev); 240 void rs600_hpd_fini(struct radeon_device *rdev); 241 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 242 void rs600_hpd_set_polarity(struct radeon_device *rdev, 243 enum radeon_hpd_id hpd); 244 extern void rs600_pm_misc(struct radeon_device *rdev); 245 extern void rs600_pm_prepare(struct radeon_device *rdev); 246 extern void rs600_pm_finish(struct radeon_device *rdev); 247 extern void rs600_page_flip(struct radeon_device *rdev, int crtc, 248 u64 crtc_base); 249 extern bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc); 250 void rs600_set_safe_registers(struct radeon_device *rdev); 251 extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc); 252 extern int rs600_mc_wait_for_idle(struct radeon_device *rdev); 253 254 /* 255 * rs690,rs740 256 */ 257 int rs690_init(struct radeon_device *rdev); 258 void rs690_fini(struct radeon_device *rdev); 259 int rs690_resume(struct radeon_device *rdev); 260 int rs690_suspend(struct radeon_device *rdev); 261 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); 262 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 263 void rs690_bandwidth_update(struct radeon_device *rdev); 264 void rs690_line_buffer_adjust(struct radeon_device *rdev, 265 struct drm_display_mode *mode1, 266 struct drm_display_mode *mode2); 267 extern int rs690_mc_wait_for_idle(struct radeon_device *rdev); 268 269 /* 270 * rv515 271 */ 272 struct rv515_mc_save { 273 u32 vga_render_control; 274 u32 vga_hdp_control; 275 bool crtc_enabled[2]; 276 }; 277 278 int rv515_init(struct radeon_device *rdev); 279 void rv515_fini(struct radeon_device *rdev); 280 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); 281 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 282 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 283 void rv515_bandwidth_update(struct radeon_device *rdev); 284 int rv515_resume(struct radeon_device *rdev); 285 int rv515_suspend(struct radeon_device *rdev); 286 void rv515_bandwidth_avivo_update(struct radeon_device *rdev); 287 void rv515_vga_render_disable(struct radeon_device *rdev); 288 void rv515_set_safe_registers(struct radeon_device *rdev); 289 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); 290 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); 291 void rv515_clock_startup(struct radeon_device *rdev); 292 void rv515_debugfs(struct radeon_device *rdev); 293 int rv515_mc_wait_for_idle(struct radeon_device *rdev); 294 295 /* 296 * r520,rv530,rv560,rv570,r580 297 */ 298 int r520_init(struct radeon_device *rdev); 299 int r520_resume(struct radeon_device *rdev); 300 int r520_mc_wait_for_idle(struct radeon_device *rdev); 301 302 /* 303 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 304 */ 305 int r600_init(struct radeon_device *rdev); 306 void r600_fini(struct radeon_device *rdev); 307 int r600_suspend(struct radeon_device *rdev); 308 int r600_resume(struct radeon_device *rdev); 309 void r600_vga_set_state(struct radeon_device *rdev, bool state); 310 int r600_wb_init(struct radeon_device *rdev); 311 void r600_wb_fini(struct radeon_device *rdev); 312 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); 313 uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); 314 void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 315 int r600_cs_parse(struct radeon_cs_parser *p); 316 int r600_dma_cs_parse(struct radeon_cs_parser *p); 317 int r600_dma_cs_next_reloc(struct radeon_cs_parser *p, 318 struct radeon_cs_reloc **cs_reloc); 319 u32 r600_gpu_check_soft_reset(struct radeon_device *rdev); 320 void r600_fence_ring_emit(struct radeon_device *rdev, 321 struct radeon_fence *fence); 322 bool r600_semaphore_ring_emit(struct radeon_device *rdev, 323 struct radeon_ring *cp, 324 struct radeon_semaphore *semaphore, 325 bool emit_wait); 326 void r600_dma_fence_ring_emit(struct radeon_device *rdev, 327 struct radeon_fence *fence); 328 bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev, 329 struct radeon_ring *ring, 330 struct radeon_semaphore *semaphore, 331 bool emit_wait); 332 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 333 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 334 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 335 int r600_asic_reset(struct radeon_device *rdev); 336 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 337 uint32_t tiling_flags, uint32_t pitch, 338 uint32_t offset, uint32_t obj_size); 339 void r600_clear_surface_reg(struct radeon_device *rdev, int reg); 340 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 341 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 342 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 343 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 344 int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 345 struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev, 346 uint64_t src_offset, uint64_t dst_offset, 347 unsigned num_gpu_pages, 348 struct reservation_object *resv); 349 struct radeon_fence *r600_copy_dma(struct radeon_device *rdev, 350 uint64_t src_offset, uint64_t dst_offset, 351 unsigned num_gpu_pages, 352 struct reservation_object *resv); 353 void r600_hpd_init(struct radeon_device *rdev); 354 void r600_hpd_fini(struct radeon_device *rdev); 355 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 356 void r600_hpd_set_polarity(struct radeon_device *rdev, 357 enum radeon_hpd_id hpd); 358 extern void r600_mmio_hdp_flush(struct radeon_device *rdev); 359 extern bool r600_gui_idle(struct radeon_device *rdev); 360 extern void r600_pm_misc(struct radeon_device *rdev); 361 extern void r600_pm_init_profile(struct radeon_device *rdev); 362 extern void rs780_pm_init_profile(struct radeon_device *rdev); 363 extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg); 364 extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 365 extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); 366 extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes); 367 extern int r600_get_pcie_lanes(struct radeon_device *rdev); 368 bool r600_card_posted(struct radeon_device *rdev); 369 void r600_cp_stop(struct radeon_device *rdev); 370 int r600_cp_start(struct radeon_device *rdev); 371 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size); 372 int r600_cp_resume(struct radeon_device *rdev); 373 void r600_cp_fini(struct radeon_device *rdev); 374 int r600_count_pipe_bits(uint32_t val); 375 int r600_mc_wait_for_idle(struct radeon_device *rdev); 376 int r600_pcie_gart_init(struct radeon_device *rdev); 377 void r600_scratch_init(struct radeon_device *rdev); 378 int r600_init_microcode(struct radeon_device *rdev); 379 u32 r600_gfx_get_rptr(struct radeon_device *rdev, 380 struct radeon_ring *ring); 381 u32 r600_gfx_get_wptr(struct radeon_device *rdev, 382 struct radeon_ring *ring); 383 void r600_gfx_set_wptr(struct radeon_device *rdev, 384 struct radeon_ring *ring); 385 void r600_fini_microcode(struct radeon_device *rdev); 386 /* r600 irq */ 387 irqreturn_t r600_irq_process(struct radeon_device *rdev); 388 int r600_irq_init(struct radeon_device *rdev); 389 void r600_irq_fini(struct radeon_device *rdev); 390 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); 391 int r600_irq_set(struct radeon_device *rdev); 392 void r600_irq_suspend(struct radeon_device *rdev); 393 void r600_disable_interrupts(struct radeon_device *rdev); 394 void r600_rlc_stop(struct radeon_device *rdev); 395 /* r600 audio */ 396 int r600_audio_init(struct radeon_device *rdev); 397 void r600_audio_fini(struct radeon_device *rdev); 398 void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock); 399 void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer, 400 size_t size); 401 void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock); 402 void r600_hdmi_audio_workaround(struct drm_encoder *encoder); 403 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); 404 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); 405 void r600_hdmi_enable(struct drm_encoder *encoder, bool enable); 406 void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 407 u32 r600_get_xclk(struct radeon_device *rdev); 408 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev); 409 int rv6xx_get_temp(struct radeon_device *rdev); 410 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 411 int r600_dpm_pre_set_power_state(struct radeon_device *rdev); 412 void r600_dpm_post_set_power_state(struct radeon_device *rdev); 413 int r600_dpm_late_enable(struct radeon_device *rdev); 414 /* r600 dma */ 415 uint32_t r600_dma_get_rptr(struct radeon_device *rdev, 416 struct radeon_ring *ring); 417 uint32_t r600_dma_get_wptr(struct radeon_device *rdev, 418 struct radeon_ring *ring); 419 void r600_dma_set_wptr(struct radeon_device *rdev, 420 struct radeon_ring *ring); 421 /* rv6xx dpm */ 422 int rv6xx_dpm_init(struct radeon_device *rdev); 423 int rv6xx_dpm_enable(struct radeon_device *rdev); 424 void rv6xx_dpm_disable(struct radeon_device *rdev); 425 int rv6xx_dpm_set_power_state(struct radeon_device *rdev); 426 void rv6xx_setup_asic(struct radeon_device *rdev); 427 void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev); 428 void rv6xx_dpm_fini(struct radeon_device *rdev); 429 u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low); 430 u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low); 431 void rv6xx_dpm_print_power_state(struct radeon_device *rdev, 432 struct radeon_ps *ps); 433 void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 434 struct seq_file *m); 435 int rv6xx_dpm_force_performance_level(struct radeon_device *rdev, 436 enum radeon_dpm_forced_level level); 437 /* rs780 dpm */ 438 int rs780_dpm_init(struct radeon_device *rdev); 439 int rs780_dpm_enable(struct radeon_device *rdev); 440 void rs780_dpm_disable(struct radeon_device *rdev); 441 int rs780_dpm_set_power_state(struct radeon_device *rdev); 442 void rs780_dpm_setup_asic(struct radeon_device *rdev); 443 void rs780_dpm_display_configuration_changed(struct radeon_device *rdev); 444 void rs780_dpm_fini(struct radeon_device *rdev); 445 u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low); 446 u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low); 447 void rs780_dpm_print_power_state(struct radeon_device *rdev, 448 struct radeon_ps *ps); 449 void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 450 struct seq_file *m); 451 int rs780_dpm_force_performance_level(struct radeon_device *rdev, 452 enum radeon_dpm_forced_level level); 453 454 /* 455 * rv770,rv730,rv710,rv740 456 */ 457 int rv770_init(struct radeon_device *rdev); 458 void rv770_fini(struct radeon_device *rdev); 459 int rv770_suspend(struct radeon_device *rdev); 460 int rv770_resume(struct radeon_device *rdev); 461 void rv770_pm_misc(struct radeon_device *rdev); 462 void rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 463 bool rv770_page_flip_pending(struct radeon_device *rdev, int crtc); 464 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 465 void r700_cp_stop(struct radeon_device *rdev); 466 void r700_cp_fini(struct radeon_device *rdev); 467 struct radeon_fence *rv770_copy_dma(struct radeon_device *rdev, 468 uint64_t src_offset, uint64_t dst_offset, 469 unsigned num_gpu_pages, 470 struct reservation_object *resv); 471 u32 rv770_get_xclk(struct radeon_device *rdev); 472 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 473 int rv770_get_temp(struct radeon_device *rdev); 474 /* hdmi */ 475 void dce3_1_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 476 /* rv7xx pm */ 477 int rv770_dpm_init(struct radeon_device *rdev); 478 int rv770_dpm_enable(struct radeon_device *rdev); 479 int rv770_dpm_late_enable(struct radeon_device *rdev); 480 void rv770_dpm_disable(struct radeon_device *rdev); 481 int rv770_dpm_set_power_state(struct radeon_device *rdev); 482 void rv770_dpm_setup_asic(struct radeon_device *rdev); 483 void rv770_dpm_display_configuration_changed(struct radeon_device *rdev); 484 void rv770_dpm_fini(struct radeon_device *rdev); 485 u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low); 486 u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low); 487 void rv770_dpm_print_power_state(struct radeon_device *rdev, 488 struct radeon_ps *ps); 489 void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 490 struct seq_file *m); 491 bool rv770_dpm_vblank_too_short(struct radeon_device *rdev); 492 void rv770_set_clk_bypass_mode(struct radeon_device *rdev); 493 494 /* 495 * evergreen 496 */ 497 struct evergreen_mc_save { 498 u32 vga_render_control; 499 u32 vga_hdp_control; 500 bool crtc_enabled[RADEON_MAX_CRTCS]; 501 }; 502 503 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); 504 int evergreen_init(struct radeon_device *rdev); 505 void evergreen_fini(struct radeon_device *rdev); 506 int evergreen_suspend(struct radeon_device *rdev); 507 int evergreen_resume(struct radeon_device *rdev); 508 bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 509 bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 510 int evergreen_asic_reset(struct radeon_device *rdev); 511 void evergreen_bandwidth_update(struct radeon_device *rdev); 512 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 513 void evergreen_hpd_init(struct radeon_device *rdev); 514 void evergreen_hpd_fini(struct radeon_device *rdev); 515 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 516 void evergreen_hpd_set_polarity(struct radeon_device *rdev, 517 enum radeon_hpd_id hpd); 518 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); 519 int evergreen_irq_set(struct radeon_device *rdev); 520 irqreturn_t evergreen_irq_process(struct radeon_device *rdev); 521 extern int evergreen_cs_parse(struct radeon_cs_parser *p); 522 extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p); 523 extern void evergreen_pm_misc(struct radeon_device *rdev); 524 extern void evergreen_pm_prepare(struct radeon_device *rdev); 525 extern void evergreen_pm_finish(struct radeon_device *rdev); 526 extern void sumo_pm_init_profile(struct radeon_device *rdev); 527 extern void btc_pm_init_profile(struct radeon_device *rdev); 528 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 529 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 530 extern void evergreen_page_flip(struct radeon_device *rdev, int crtc, 531 u64 crtc_base); 532 extern bool evergreen_page_flip_pending(struct radeon_device *rdev, int crtc); 533 extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc); 534 void evergreen_disable_interrupt_state(struct radeon_device *rdev); 535 int evergreen_mc_wait_for_idle(struct radeon_device *rdev); 536 void evergreen_dma_fence_ring_emit(struct radeon_device *rdev, 537 struct radeon_fence *fence); 538 void evergreen_dma_ring_ib_execute(struct radeon_device *rdev, 539 struct radeon_ib *ib); 540 struct radeon_fence *evergreen_copy_dma(struct radeon_device *rdev, 541 uint64_t src_offset, uint64_t dst_offset, 542 unsigned num_gpu_pages, 543 struct reservation_object *resv); 544 u32 evergreen_gpu_check_soft_reset(struct radeon_device *rdev); 545 void evergreen_gpu_pci_config_reset(struct radeon_device *rdev); 546 void evergreen_pcie_gen2_enable(struct radeon_device *rdev); 547 void evergreen_print_gpu_status_regs(struct radeon_device *rdev); 548 void evergreen_program_aspm(struct radeon_device *rdev); 549 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev); 550 u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev); 551 void sumo_rlc_fini(struct radeon_device *rdev); 552 int sumo_rlc_init(struct radeon_device *rdev); 553 int evergreen_rlc_resume(struct radeon_device *rdev); 554 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); 555 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); 556 void evergreen_mc_program(struct radeon_device *rdev); 557 int evergreen_mc_init(struct radeon_device *rdev); 558 void evergreen_irq_suspend(struct radeon_device *rdev); 559 bool evergreen_is_display_hung(struct radeon_device *rdev); 560 void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable); 561 void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 562 int evergreen_get_temp(struct radeon_device *rdev); 563 int sumo_get_temp(struct radeon_device *rdev); 564 int tn_get_temp(struct radeon_device *rdev); 565 int cypress_dpm_init(struct radeon_device *rdev); 566 void cypress_dpm_setup_asic(struct radeon_device *rdev); 567 int cypress_dpm_enable(struct radeon_device *rdev); 568 void cypress_dpm_disable(struct radeon_device *rdev); 569 int cypress_dpm_set_power_state(struct radeon_device *rdev); 570 void cypress_dpm_display_configuration_changed(struct radeon_device *rdev); 571 void cypress_dpm_fini(struct radeon_device *rdev); 572 bool cypress_dpm_vblank_too_short(struct radeon_device *rdev); 573 int btc_dpm_init(struct radeon_device *rdev); 574 void btc_dpm_setup_asic(struct radeon_device *rdev); 575 int btc_dpm_enable(struct radeon_device *rdev); 576 void btc_dpm_disable(struct radeon_device *rdev); 577 int btc_dpm_pre_set_power_state(struct radeon_device *rdev); 578 int btc_dpm_set_power_state(struct radeon_device *rdev); 579 void btc_dpm_post_set_power_state(struct radeon_device *rdev); 580 void btc_dpm_fini(struct radeon_device *rdev); 581 u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low); 582 u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low); 583 bool btc_dpm_vblank_too_short(struct radeon_device *rdev); 584 void btc_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 585 struct seq_file *m); 586 int sumo_dpm_init(struct radeon_device *rdev); 587 int sumo_dpm_enable(struct radeon_device *rdev); 588 int sumo_dpm_late_enable(struct radeon_device *rdev); 589 void sumo_dpm_disable(struct radeon_device *rdev); 590 int sumo_dpm_pre_set_power_state(struct radeon_device *rdev); 591 int sumo_dpm_set_power_state(struct radeon_device *rdev); 592 void sumo_dpm_post_set_power_state(struct radeon_device *rdev); 593 void sumo_dpm_setup_asic(struct radeon_device *rdev); 594 void sumo_dpm_display_configuration_changed(struct radeon_device *rdev); 595 void sumo_dpm_fini(struct radeon_device *rdev); 596 u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low); 597 u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low); 598 void sumo_dpm_print_power_state(struct radeon_device *rdev, 599 struct radeon_ps *ps); 600 void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 601 struct seq_file *m); 602 int sumo_dpm_force_performance_level(struct radeon_device *rdev, 603 enum radeon_dpm_forced_level level); 604 605 /* 606 * cayman 607 */ 608 void cayman_fence_ring_emit(struct radeon_device *rdev, 609 struct radeon_fence *fence); 610 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev); 611 int cayman_init(struct radeon_device *rdev); 612 void cayman_fini(struct radeon_device *rdev); 613 int cayman_suspend(struct radeon_device *rdev); 614 int cayman_resume(struct radeon_device *rdev); 615 int cayman_asic_reset(struct radeon_device *rdev); 616 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 617 int cayman_vm_init(struct radeon_device *rdev); 618 void cayman_vm_fini(struct radeon_device *rdev); 619 void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 620 uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags); 621 void cayman_vm_decode_fault(struct radeon_device *rdev, 622 u32 status, u32 addr); 623 u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev); 624 int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 625 int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 626 void cayman_dma_ring_ib_execute(struct radeon_device *rdev, 627 struct radeon_ib *ib); 628 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 629 bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 630 631 void cayman_dma_vm_copy_pages(struct radeon_device *rdev, 632 struct radeon_ib *ib, 633 uint64_t pe, uint64_t src, 634 unsigned count); 635 void cayman_dma_vm_write_pages(struct radeon_device *rdev, 636 struct radeon_ib *ib, 637 uint64_t pe, 638 uint64_t addr, unsigned count, 639 uint32_t incr, uint32_t flags); 640 void cayman_dma_vm_set_pages(struct radeon_device *rdev, 641 struct radeon_ib *ib, 642 uint64_t pe, 643 uint64_t addr, unsigned count, 644 uint32_t incr, uint32_t flags); 645 void cayman_dma_vm_pad_ib(struct radeon_ib *ib); 646 647 void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 648 649 u32 cayman_gfx_get_rptr(struct radeon_device *rdev, 650 struct radeon_ring *ring); 651 u32 cayman_gfx_get_wptr(struct radeon_device *rdev, 652 struct radeon_ring *ring); 653 void cayman_gfx_set_wptr(struct radeon_device *rdev, 654 struct radeon_ring *ring); 655 uint32_t cayman_dma_get_rptr(struct radeon_device *rdev, 656 struct radeon_ring *ring); 657 uint32_t cayman_dma_get_wptr(struct radeon_device *rdev, 658 struct radeon_ring *ring); 659 void cayman_dma_set_wptr(struct radeon_device *rdev, 660 struct radeon_ring *ring); 661 void cayman_cp_int_cntl_setup(struct radeon_device *rdev, 662 int ring, u32 cp_int_cntl); 663 664 int ni_dpm_init(struct radeon_device *rdev); 665 void ni_dpm_setup_asic(struct radeon_device *rdev); 666 int ni_dpm_enable(struct radeon_device *rdev); 667 void ni_dpm_disable(struct radeon_device *rdev); 668 int ni_dpm_pre_set_power_state(struct radeon_device *rdev); 669 int ni_dpm_set_power_state(struct radeon_device *rdev); 670 void ni_dpm_post_set_power_state(struct radeon_device *rdev); 671 void ni_dpm_fini(struct radeon_device *rdev); 672 u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low); 673 u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low); 674 void ni_dpm_print_power_state(struct radeon_device *rdev, 675 struct radeon_ps *ps); 676 void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 677 struct seq_file *m); 678 int ni_dpm_force_performance_level(struct radeon_device *rdev, 679 enum radeon_dpm_forced_level level); 680 //bool ni_dpm_vblank_too_short(struct radeon_device *rdev); 681 int trinity_dpm_init(struct radeon_device *rdev); 682 int trinity_dpm_enable(struct radeon_device *rdev); 683 int trinity_dpm_late_enable(struct radeon_device *rdev); 684 void trinity_dpm_disable(struct radeon_device *rdev); 685 int trinity_dpm_pre_set_power_state(struct radeon_device *rdev); 686 int trinity_dpm_set_power_state(struct radeon_device *rdev); 687 void trinity_dpm_post_set_power_state(struct radeon_device *rdev); 688 void trinity_dpm_setup_asic(struct radeon_device *rdev); 689 void trinity_dpm_display_configuration_changed(struct radeon_device *rdev); 690 void trinity_dpm_fini(struct radeon_device *rdev); 691 u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low); 692 u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low); 693 void trinity_dpm_print_power_state(struct radeon_device *rdev, 694 struct radeon_ps *ps); 695 void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 696 struct seq_file *m); 697 int trinity_dpm_force_performance_level(struct radeon_device *rdev, 698 enum radeon_dpm_forced_level level); 699 void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable); 700 701 /* DCE6 - SI */ 702 void dce6_bandwidth_update(struct radeon_device *rdev); 703 int dce6_audio_init(struct radeon_device *rdev); 704 void dce6_audio_fini(struct radeon_device *rdev); 705 706 void dce6_afmt_write_sad_regs(struct drm_encoder *encoder); 707 void dce6_afmt_select_pin(struct drm_encoder *encoder); 708 void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder); 709 void dce6_afmt_write_latency_fields(struct drm_encoder *encoder, 710 struct drm_display_mode *mode); 711 712 /* 713 * si 714 */ 715 void si_fence_ring_emit(struct radeon_device *rdev, 716 struct radeon_fence *fence); 717 void si_pcie_gart_tlb_flush(struct radeon_device *rdev); 718 int si_init(struct radeon_device *rdev); 719 void si_fini(struct radeon_device *rdev); 720 int si_suspend(struct radeon_device *rdev); 721 int si_resume(struct radeon_device *rdev); 722 bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 723 bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 724 int si_asic_reset(struct radeon_device *rdev); 725 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 726 int si_irq_set(struct radeon_device *rdev); 727 irqreturn_t si_irq_process(struct radeon_device *rdev); 728 int si_vm_init(struct radeon_device *rdev); 729 void si_vm_fini(struct radeon_device *rdev); 730 void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 731 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 732 struct radeon_fence *si_copy_dma(struct radeon_device *rdev, 733 uint64_t src_offset, uint64_t dst_offset, 734 unsigned num_gpu_pages, 735 struct reservation_object *resv); 736 737 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode); 738 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock); 739 u32 si_get_csb_size(struct radeon_device *rdev); 740 void si_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer); 741 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 742 u32 max_voltage_steps, 743 struct atom_voltage_table *voltage_table); 744 u32 si_gpu_check_soft_reset(struct radeon_device *rdev); 745 746 void si_dma_vm_copy_pages(struct radeon_device *rdev, 747 struct radeon_ib *ib, 748 uint64_t pe, uint64_t src, 749 unsigned count); 750 void si_dma_vm_write_pages(struct radeon_device *rdev, 751 struct radeon_ib *ib, 752 uint64_t pe, 753 uint64_t addr, unsigned count, 754 uint32_t incr, uint32_t flags); 755 void si_dma_vm_set_pages(struct radeon_device *rdev, 756 struct radeon_ib *ib, 757 uint64_t pe, 758 uint64_t addr, unsigned count, 759 uint32_t incr, uint32_t flags); 760 761 void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 762 u32 si_get_xclk(struct radeon_device *rdev); 763 uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev); 764 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 765 int si_get_temp(struct radeon_device *rdev); 766 void si_rlc_fini(struct radeon_device *rdev); 767 int si_rlc_init(struct radeon_device *rdev); 768 void si_rlc_reset(struct radeon_device *rdev); 769 int si_mc_load_microcode(struct radeon_device *rdev); 770 void si_vram_gtt_location(struct radeon_device *rdev, 771 struct radeon_mc *mc); 772 void si_init_uvd_internal_cg(struct radeon_device *rdev); 773 int si_dpm_init(struct radeon_device *rdev); 774 void si_dpm_setup_asic(struct radeon_device *rdev); 775 int si_dpm_enable(struct radeon_device *rdev); 776 int si_dpm_late_enable(struct radeon_device *rdev); 777 void si_dpm_disable(struct radeon_device *rdev); 778 int si_dpm_pre_set_power_state(struct radeon_device *rdev); 779 int si_dpm_set_power_state(struct radeon_device *rdev); 780 void si_dpm_post_set_power_state(struct radeon_device *rdev); 781 void si_dpm_fini(struct radeon_device *rdev); 782 void si_dpm_display_configuration_changed(struct radeon_device *rdev); 783 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 784 struct seq_file *m); 785 int si_dpm_force_performance_level(struct radeon_device *rdev, 786 enum radeon_dpm_forced_level level); 787 788 /* DCE8 - CIK */ 789 void dce8_bandwidth_update(struct radeon_device *rdev); 790 791 /* 792 * cik 793 */ 794 u32 cik_get_csb_size(struct radeon_device *rdev); 795 void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer); 796 uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev); 797 u32 cik_get_xclk(struct radeon_device *rdev); 798 uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg); 799 void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 800 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 801 int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk); 802 void cik_init_cp_pg_table(struct radeon_device *rdev); 803 void cik_update_cg(struct radeon_device *rdev, 804 u32 block, bool enable); 805 void cik_enter_rlc_safe_mode(struct radeon_device *rdev); 806 void cik_exit_rlc_safe_mode(struct radeon_device *rdev); 807 int ci_mc_load_microcode(struct radeon_device *rdev); 808 void cik_sdma_fence_ring_emit(struct radeon_device *rdev, 809 struct radeon_fence *fence); 810 bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev, 811 struct radeon_ring *ring, 812 struct radeon_semaphore *semaphore, 813 bool emit_wait); 814 void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 815 struct radeon_fence *cik_copy_dma(struct radeon_device *rdev, 816 uint64_t src_offset, uint64_t dst_offset, 817 unsigned num_gpu_pages, 818 struct reservation_object *resv); 819 struct radeon_fence *cik_copy_cpdma(struct radeon_device *rdev, 820 uint64_t src_offset, uint64_t dst_offset, 821 unsigned num_gpu_pages, 822 struct reservation_object *resv); 823 int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 824 int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 825 bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 826 void cik_fence_gfx_ring_emit(struct radeon_device *rdev, 827 struct radeon_fence *fence); 828 void cik_fence_compute_ring_emit(struct radeon_device *rdev, 829 struct radeon_fence *fence); 830 bool cik_semaphore_ring_emit(struct radeon_device *rdev, 831 struct radeon_ring *cp, 832 struct radeon_semaphore *semaphore, 833 bool emit_wait); 834 void cik_pcie_gart_tlb_flush(struct radeon_device *rdev); 835 int cik_init(struct radeon_device *rdev); 836 void cik_fini(struct radeon_device *rdev); 837 int cik_suspend(struct radeon_device *rdev); 838 int cik_resume(struct radeon_device *rdev); 839 bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 840 int cik_asic_reset(struct radeon_device *rdev); 841 void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 842 int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 843 int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 844 int cik_irq_set(struct radeon_device *rdev); 845 irqreturn_t cik_irq_process(struct radeon_device *rdev); 846 int cik_vm_init(struct radeon_device *rdev); 847 void cik_vm_fini(struct radeon_device *rdev); 848 void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 849 850 void cik_sdma_vm_copy_pages(struct radeon_device *rdev, 851 struct radeon_ib *ib, 852 uint64_t pe, uint64_t src, 853 unsigned count); 854 void cik_sdma_vm_write_pages(struct radeon_device *rdev, 855 struct radeon_ib *ib, 856 uint64_t pe, 857 uint64_t addr, unsigned count, 858 uint32_t incr, uint32_t flags); 859 void cik_sdma_vm_set_pages(struct radeon_device *rdev, 860 struct radeon_ib *ib, 861 uint64_t pe, 862 uint64_t addr, unsigned count, 863 uint32_t incr, uint32_t flags); 864 void cik_sdma_vm_pad_ib(struct radeon_ib *ib); 865 866 void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 867 int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 868 u32 cik_gfx_get_rptr(struct radeon_device *rdev, 869 struct radeon_ring *ring); 870 u32 cik_gfx_get_wptr(struct radeon_device *rdev, 871 struct radeon_ring *ring); 872 void cik_gfx_set_wptr(struct radeon_device *rdev, 873 struct radeon_ring *ring); 874 u32 cik_compute_get_rptr(struct radeon_device *rdev, 875 struct radeon_ring *ring); 876 u32 cik_compute_get_wptr(struct radeon_device *rdev, 877 struct radeon_ring *ring); 878 void cik_compute_set_wptr(struct radeon_device *rdev, 879 struct radeon_ring *ring); 880 u32 cik_sdma_get_rptr(struct radeon_device *rdev, 881 struct radeon_ring *ring); 882 u32 cik_sdma_get_wptr(struct radeon_device *rdev, 883 struct radeon_ring *ring); 884 void cik_sdma_set_wptr(struct radeon_device *rdev, 885 struct radeon_ring *ring); 886 bool cik_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 887 void cik_fence_ring_emit(struct radeon_device *rdev, 888 struct radeon_fence *fence); 889 u32 cik_gpu_check_soft_reset(struct radeon_device *rdev); 890 void cik_sdma_enable(struct radeon_device *rdev, bool enable); 891 int cik_sdma_resume(struct radeon_device *rdev); 892 void cik_sdma_fini(struct radeon_device *rdev); 893 int ci_get_temp(struct radeon_device *rdev); 894 int kv_get_temp(struct radeon_device *rdev); 895 896 int ci_dpm_init(struct radeon_device *rdev); 897 int ci_dpm_enable(struct radeon_device *rdev); 898 int ci_dpm_late_enable(struct radeon_device *rdev); 899 void ci_dpm_disable(struct radeon_device *rdev); 900 int ci_dpm_pre_set_power_state(struct radeon_device *rdev); 901 int ci_dpm_set_power_state(struct radeon_device *rdev); 902 void ci_dpm_post_set_power_state(struct radeon_device *rdev); 903 void ci_dpm_setup_asic(struct radeon_device *rdev); 904 void ci_dpm_display_configuration_changed(struct radeon_device *rdev); 905 void ci_dpm_fini(struct radeon_device *rdev); 906 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low); 907 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low); 908 void ci_dpm_print_power_state(struct radeon_device *rdev, 909 struct radeon_ps *ps); 910 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 911 struct seq_file *m); 912 int ci_dpm_force_performance_level(struct radeon_device *rdev, 913 enum radeon_dpm_forced_level level); 914 bool ci_dpm_vblank_too_short(struct radeon_device *rdev); 915 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate); 916 917 int kv_dpm_init(struct radeon_device *rdev); 918 int kv_dpm_enable(struct radeon_device *rdev); 919 int kv_dpm_late_enable(struct radeon_device *rdev); 920 void kv_dpm_disable(struct radeon_device *rdev); 921 int kv_dpm_pre_set_power_state(struct radeon_device *rdev); 922 int kv_dpm_set_power_state(struct radeon_device *rdev); 923 void kv_dpm_post_set_power_state(struct radeon_device *rdev); 924 void kv_dpm_setup_asic(struct radeon_device *rdev); 925 void kv_dpm_display_configuration_changed(struct radeon_device *rdev); 926 void kv_dpm_fini(struct radeon_device *rdev); 927 u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low); 928 u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low); 929 void kv_dpm_print_power_state(struct radeon_device *rdev, 930 struct radeon_ps *ps); 931 void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 932 struct seq_file *m); 933 int kv_dpm_force_performance_level(struct radeon_device *rdev, 934 enum radeon_dpm_forced_level level); 935 void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate); 936 void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable); 937 938 /* uvd v1.0 */ 939 uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev, 940 struct radeon_ring *ring); 941 uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev, 942 struct radeon_ring *ring); 943 void uvd_v1_0_set_wptr(struct radeon_device *rdev, 944 struct radeon_ring *ring); 945 int uvd_v1_0_resume(struct radeon_device *rdev); 946 947 int uvd_v1_0_init(struct radeon_device *rdev); 948 void uvd_v1_0_fini(struct radeon_device *rdev); 949 int uvd_v1_0_start(struct radeon_device *rdev); 950 void uvd_v1_0_stop(struct radeon_device *rdev); 951 952 int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 953 void uvd_v1_0_fence_emit(struct radeon_device *rdev, 954 struct radeon_fence *fence); 955 int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 956 bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev, 957 struct radeon_ring *ring, 958 struct radeon_semaphore *semaphore, 959 bool emit_wait); 960 void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 961 962 /* uvd v2.2 */ 963 int uvd_v2_2_resume(struct radeon_device *rdev); 964 void uvd_v2_2_fence_emit(struct radeon_device *rdev, 965 struct radeon_fence *fence); 966 967 /* uvd v3.1 */ 968 bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev, 969 struct radeon_ring *ring, 970 struct radeon_semaphore *semaphore, 971 bool emit_wait); 972 973 /* uvd v4.2 */ 974 int uvd_v4_2_resume(struct radeon_device *rdev); 975 976 /* vce v1.0 */ 977 uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev, 978 struct radeon_ring *ring); 979 uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev, 980 struct radeon_ring *ring); 981 void vce_v1_0_set_wptr(struct radeon_device *rdev, 982 struct radeon_ring *ring); 983 int vce_v1_0_init(struct radeon_device *rdev); 984 int vce_v1_0_start(struct radeon_device *rdev); 985 986 /* vce v2.0 */ 987 int vce_v2_0_resume(struct radeon_device *rdev); 988 void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable); 989 990 #endif 991