1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * 26 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_atombios.c 254885 2013-08-25 19:37:15Z dumbbell $ 27 */ 28 29 #include <drm/drmP.h> 30 #include <uapi_drm/radeon_drm.h> 31 #include "radeon.h" 32 #include "radeon_asic.h" /* Declares several prototypes; clang is pleased. */ 33 34 #include "atom.h" 35 #include "atom-bits.h" 36 37 union atom_supported_devices { 38 struct _ATOM_SUPPORTED_DEVICES_INFO info; 39 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2; 40 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1; 41 }; 42 43 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev, 44 ATOM_GPIO_I2C_ASSIGMENT *gpio, 45 u8 index) 46 { 47 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */ 48 if ((rdev->family == CHIP_R420) || 49 (rdev->family == CHIP_R423) || 50 (rdev->family == CHIP_RV410)) { 51 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) || 52 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) || 53 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) { 54 gpio->ucClkMaskShift = 0x19; 55 gpio->ucDataMaskShift = 0x18; 56 } 57 } 58 59 /* some evergreen boards have bad data for this entry */ 60 if (ASIC_IS_DCE4(rdev)) { 61 if ((index == 7) && 62 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) && 63 (gpio->sucI2cId.ucAccess == 0)) { 64 gpio->sucI2cId.ucAccess = 0x97; 65 gpio->ucDataMaskShift = 8; 66 gpio->ucDataEnShift = 8; 67 gpio->ucDataY_Shift = 8; 68 gpio->ucDataA_Shift = 8; 69 } 70 } 71 72 /* some DCE3 boards have bad data for this entry */ 73 if (ASIC_IS_DCE3(rdev)) { 74 if ((index == 4) && 75 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) && 76 (gpio->sucI2cId.ucAccess == 0x94)) 77 gpio->sucI2cId.ucAccess = 0x14; 78 } 79 } 80 81 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio) 82 { 83 struct radeon_i2c_bus_rec i2c; 84 85 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); 86 87 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; 88 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4; 89 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4; 90 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4; 91 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4; 92 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4; 93 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4; 94 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4; 95 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift); 96 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift); 97 i2c.en_clk_mask = (1 << gpio->ucClkEnShift); 98 i2c.en_data_mask = (1 << gpio->ucDataEnShift); 99 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift); 100 i2c.y_data_mask = (1 << gpio->ucDataY_Shift); 101 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift); 102 i2c.a_data_mask = (1 << gpio->ucDataA_Shift); 103 104 if (gpio->sucI2cId.sbfAccess.bfHW_Capable) 105 i2c.hw_capable = true; 106 else 107 i2c.hw_capable = false; 108 109 if (gpio->sucI2cId.ucAccess == 0xa0) 110 i2c.mm_i2c = true; 111 else 112 i2c.mm_i2c = false; 113 114 i2c.i2c_id = gpio->sucI2cId.ucAccess; 115 116 if (i2c.mask_clk_reg) 117 i2c.valid = true; 118 else 119 i2c.valid = false; 120 121 return i2c; 122 } 123 124 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev, 125 uint8_t id) 126 { 127 struct atom_context *ctx = rdev->mode_info.atom_context; 128 ATOM_GPIO_I2C_ASSIGMENT *gpio; 129 struct radeon_i2c_bus_rec i2c; 130 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 131 struct _ATOM_GPIO_I2C_INFO *i2c_info; 132 uint16_t data_offset, size; 133 int i, num_indices; 134 135 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); 136 i2c.valid = false; 137 138 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 139 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)((char *)ctx->bios + data_offset); 140 141 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 142 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 143 144 for (i = 0; i < num_indices; i++) { 145 gpio = &i2c_info->asGPIO_Info[i]; 146 147 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i); 148 149 if (gpio->sucI2cId.ucAccess == id) { 150 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio); 151 break; 152 } 153 } 154 } 155 156 return i2c; 157 } 158 159 void radeon_atombios_i2c_init(struct radeon_device *rdev) 160 { 161 struct atom_context *ctx = rdev->mode_info.atom_context; 162 ATOM_GPIO_I2C_ASSIGMENT *gpio; 163 struct radeon_i2c_bus_rec i2c; 164 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 165 struct _ATOM_GPIO_I2C_INFO *i2c_info; 166 uint16_t data_offset, size; 167 int i, num_indices; 168 char stmp[32]; 169 170 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 171 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)((char *)ctx->bios + data_offset); 172 173 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 174 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 175 176 for (i = 0; i < num_indices; i++) { 177 gpio = &i2c_info->asGPIO_Info[i]; 178 179 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i); 180 181 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio); 182 183 if (i2c.valid) { 184 ksprintf(stmp, "0x%x", i2c.i2c_id); 185 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp); 186 } 187 } 188 } 189 } 190 191 static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev, 192 u8 id) 193 { 194 struct atom_context *ctx = rdev->mode_info.atom_context; 195 struct radeon_gpio_rec gpio; 196 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT); 197 struct _ATOM_GPIO_PIN_LUT *gpio_info; 198 ATOM_GPIO_PIN_ASSIGNMENT *pin; 199 u16 data_offset, size; 200 int i, num_indices; 201 202 memset(&gpio, 0, sizeof(struct radeon_gpio_rec)); 203 gpio.valid = false; 204 205 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 206 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)((char *)ctx->bios + data_offset); 207 208 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 209 sizeof(ATOM_GPIO_PIN_ASSIGNMENT); 210 211 for (i = 0; i < num_indices; i++) { 212 pin = &gpio_info->asGPIO_Pin[i]; 213 if (id == pin->ucGPIO_ID) { 214 gpio.id = pin->ucGPIO_ID; 215 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4; 216 gpio.mask = (1 << pin->ucGpioPinBitShift); 217 gpio.valid = true; 218 break; 219 } 220 } 221 } 222 223 return gpio; 224 } 225 226 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev, 227 struct radeon_gpio_rec *gpio) 228 { 229 struct radeon_hpd hpd; 230 u32 reg; 231 232 memset(&hpd, 0, sizeof(struct radeon_hpd)); 233 234 if (ASIC_IS_DCE6(rdev)) 235 reg = SI_DC_GPIO_HPD_A; 236 else if (ASIC_IS_DCE4(rdev)) 237 reg = EVERGREEN_DC_GPIO_HPD_A; 238 else 239 reg = AVIVO_DC_GPIO_HPD_A; 240 241 hpd.gpio = *gpio; 242 if (gpio->reg == reg) { 243 switch(gpio->mask) { 244 case (1 << 0): 245 hpd.hpd = RADEON_HPD_1; 246 break; 247 case (1 << 8): 248 hpd.hpd = RADEON_HPD_2; 249 break; 250 case (1 << 16): 251 hpd.hpd = RADEON_HPD_3; 252 break; 253 case (1 << 24): 254 hpd.hpd = RADEON_HPD_4; 255 break; 256 case (1 << 26): 257 hpd.hpd = RADEON_HPD_5; 258 break; 259 case (1 << 28): 260 hpd.hpd = RADEON_HPD_6; 261 break; 262 default: 263 hpd.hpd = RADEON_HPD_NONE; 264 break; 265 } 266 } else 267 hpd.hpd = RADEON_HPD_NONE; 268 return hpd; 269 } 270 271 static bool radeon_atom_apply_quirks(struct drm_device *dev, 272 uint32_t supported_device, 273 int *connector_type, 274 struct radeon_i2c_bus_rec *i2c_bus, 275 uint16_t *line_mux, 276 struct radeon_hpd *hpd) 277 { 278 279 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ 280 if ((dev->pci_device == 0x791e) && 281 (dev->pci_subvendor == 0x1043) && 282 (dev->pci_subdevice == 0x826d)) { 283 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && 284 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 285 *connector_type = DRM_MODE_CONNECTOR_DVID; 286 } 287 288 /* Asrock RS600 board lists the DVI port as HDMI */ 289 if ((dev->pci_device == 0x7941) && 290 (dev->pci_subvendor == 0x1849) && 291 (dev->pci_subdevice == 0x7941)) { 292 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && 293 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 294 *connector_type = DRM_MODE_CONNECTOR_DVID; 295 } 296 297 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */ 298 if ((dev->pci_device == 0x796e) && 299 (dev->pci_subvendor == 0x1462) && 300 (dev->pci_subdevice == 0x7302)) { 301 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) || 302 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 303 return false; 304 } 305 306 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */ 307 if ((dev->pci_device == 0x7941) && 308 (dev->pci_subvendor == 0x147b) && 309 (dev->pci_subdevice == 0x2412)) { 310 if (*connector_type == DRM_MODE_CONNECTOR_DVII) 311 return false; 312 } 313 314 /* Falcon NW laptop lists vga ddc line for LVDS */ 315 if ((dev->pci_device == 0x5653) && 316 (dev->pci_subvendor == 0x1462) && 317 (dev->pci_subdevice == 0x0291)) { 318 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) { 319 i2c_bus->valid = false; 320 *line_mux = 53; 321 } 322 } 323 324 /* HIS X1300 is DVI+VGA, not DVI+DVI */ 325 if ((dev->pci_device == 0x7146) && 326 (dev->pci_subvendor == 0x17af) && 327 (dev->pci_subdevice == 0x2058)) { 328 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) 329 return false; 330 } 331 332 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */ 333 if ((dev->pci_device == 0x7142) && 334 (dev->pci_subvendor == 0x1458) && 335 (dev->pci_subdevice == 0x2134)) { 336 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) 337 return false; 338 } 339 340 341 /* Funky macbooks */ 342 if ((dev->pci_device == 0x71C5) && 343 (dev->pci_subvendor == 0x106b) && 344 (dev->pci_subdevice == 0x0080)) { 345 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) || 346 (supported_device == ATOM_DEVICE_DFP2_SUPPORT)) 347 return false; 348 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT) 349 *line_mux = 0x90; 350 } 351 352 /* mac rv630, rv730, others */ 353 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) && 354 (*connector_type == DRM_MODE_CONNECTOR_DVII)) { 355 *connector_type = DRM_MODE_CONNECTOR_9PinDIN; 356 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1; 357 } 358 359 /* ASUS HD 3600 XT board lists the DVI port as HDMI */ 360 if ((dev->pci_device == 0x9598) && 361 (dev->pci_subvendor == 0x1043) && 362 (dev->pci_subdevice == 0x01da)) { 363 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 364 *connector_type = DRM_MODE_CONNECTOR_DVII; 365 } 366 } 367 368 /* ASUS HD 3600 board lists the DVI port as HDMI */ 369 if ((dev->pci_device == 0x9598) && 370 (dev->pci_subvendor == 0x1043) && 371 (dev->pci_subdevice == 0x01e4)) { 372 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 373 *connector_type = DRM_MODE_CONNECTOR_DVII; 374 } 375 } 376 377 /* ASUS HD 3450 board lists the DVI port as HDMI */ 378 if ((dev->pci_device == 0x95C5) && 379 (dev->pci_subvendor == 0x1043) && 380 (dev->pci_subdevice == 0x01e2)) { 381 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 382 *connector_type = DRM_MODE_CONNECTOR_DVII; 383 } 384 } 385 386 /* some BIOSes seem to report DAC on HDMI - usually this is a board with 387 * HDMI + VGA reporting as HDMI 388 */ 389 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 390 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) { 391 *connector_type = DRM_MODE_CONNECTOR_VGA; 392 *line_mux = 0; 393 } 394 } 395 396 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port 397 * on the laptop and a DVI port on the docking station and 398 * both share the same encoder, hpd pin, and ddc line. 399 * So while the bios table is technically correct, 400 * we drop the DVI port here since xrandr has no concept of 401 * encoders and will try and drive both connectors 402 * with different crtcs which isn't possible on the hardware 403 * side and leaves no crtcs for LVDS or VGA. 404 */ 405 if (((dev->pci_device == 0x95c4) || (dev->pci_device == 0x9591)) && 406 (dev->pci_subvendor == 0x1025) && 407 (dev->pci_subdevice == 0x013c)) { 408 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) && 409 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) { 410 /* actually it's a DVI-D port not DVI-I */ 411 *connector_type = DRM_MODE_CONNECTOR_DVID; 412 return false; 413 } 414 } 415 416 /* XFX Pine Group device rv730 reports no VGA DDC lines 417 * even though they are wired up to record 0x93 418 */ 419 if ((dev->pci_device == 0x9498) && 420 (dev->pci_subvendor == 0x1682) && 421 (dev->pci_subdevice == 0x2452) && 422 (i2c_bus->valid == false) && 423 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) { 424 struct radeon_device *rdev = dev->dev_private; 425 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93); 426 } 427 428 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */ 429 if (((dev->pci_device == 0x9802) || (dev->pci_device == 0x9806)) && 430 (dev->pci_subvendor == 0x1734) && 431 (dev->pci_subdevice == 0x11bd)) { 432 if (*connector_type == DRM_MODE_CONNECTOR_VGA) { 433 *connector_type = DRM_MODE_CONNECTOR_DVII; 434 *line_mux = 0x3103; 435 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) { 436 *connector_type = DRM_MODE_CONNECTOR_DVII; 437 } 438 } 439 440 441 return true; 442 } 443 444 const int supported_devices_connector_convert[] = { 445 DRM_MODE_CONNECTOR_Unknown, 446 DRM_MODE_CONNECTOR_VGA, 447 DRM_MODE_CONNECTOR_DVII, 448 DRM_MODE_CONNECTOR_DVID, 449 DRM_MODE_CONNECTOR_DVIA, 450 DRM_MODE_CONNECTOR_SVIDEO, 451 DRM_MODE_CONNECTOR_Composite, 452 DRM_MODE_CONNECTOR_LVDS, 453 DRM_MODE_CONNECTOR_Unknown, 454 DRM_MODE_CONNECTOR_Unknown, 455 DRM_MODE_CONNECTOR_HDMIA, 456 DRM_MODE_CONNECTOR_HDMIB, 457 DRM_MODE_CONNECTOR_Unknown, 458 DRM_MODE_CONNECTOR_Unknown, 459 DRM_MODE_CONNECTOR_9PinDIN, 460 DRM_MODE_CONNECTOR_DisplayPort 461 }; 462 463 const uint16_t supported_devices_connector_object_id_convert[] = { 464 CONNECTOR_OBJECT_ID_NONE, 465 CONNECTOR_OBJECT_ID_VGA, 466 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */ 467 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */ 468 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */ 469 CONNECTOR_OBJECT_ID_COMPOSITE, 470 CONNECTOR_OBJECT_ID_SVIDEO, 471 CONNECTOR_OBJECT_ID_LVDS, 472 CONNECTOR_OBJECT_ID_9PIN_DIN, 473 CONNECTOR_OBJECT_ID_9PIN_DIN, 474 CONNECTOR_OBJECT_ID_DISPLAYPORT, 475 CONNECTOR_OBJECT_ID_HDMI_TYPE_A, 476 CONNECTOR_OBJECT_ID_HDMI_TYPE_B, 477 CONNECTOR_OBJECT_ID_SVIDEO 478 }; 479 480 const int object_connector_convert[] = { 481 DRM_MODE_CONNECTOR_Unknown, 482 DRM_MODE_CONNECTOR_DVII, 483 DRM_MODE_CONNECTOR_DVII, 484 DRM_MODE_CONNECTOR_DVID, 485 DRM_MODE_CONNECTOR_DVID, 486 DRM_MODE_CONNECTOR_VGA, 487 DRM_MODE_CONNECTOR_Composite, 488 DRM_MODE_CONNECTOR_SVIDEO, 489 DRM_MODE_CONNECTOR_Unknown, 490 DRM_MODE_CONNECTOR_Unknown, 491 DRM_MODE_CONNECTOR_9PinDIN, 492 DRM_MODE_CONNECTOR_Unknown, 493 DRM_MODE_CONNECTOR_HDMIA, 494 DRM_MODE_CONNECTOR_HDMIB, 495 DRM_MODE_CONNECTOR_LVDS, 496 DRM_MODE_CONNECTOR_9PinDIN, 497 DRM_MODE_CONNECTOR_Unknown, 498 DRM_MODE_CONNECTOR_Unknown, 499 DRM_MODE_CONNECTOR_Unknown, 500 DRM_MODE_CONNECTOR_DisplayPort, 501 DRM_MODE_CONNECTOR_eDP, 502 DRM_MODE_CONNECTOR_Unknown 503 }; 504 505 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) 506 { 507 struct radeon_device *rdev = dev->dev_private; 508 struct radeon_mode_info *mode_info = &rdev->mode_info; 509 struct atom_context *ctx = mode_info->atom_context; 510 int index = GetIndexIntoMasterTable(DATA, Object_Header); 511 u16 size, data_offset; 512 u8 frev, crev; 513 ATOM_CONNECTOR_OBJECT_TABLE *con_obj; 514 ATOM_ENCODER_OBJECT_TABLE *enc_obj; 515 ATOM_OBJECT_TABLE *router_obj; 516 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; 517 ATOM_OBJECT_HEADER *obj_header; 518 int i, j, k, path_size, device_support; 519 int connector_type; 520 u16 igp_lane_info, conn_id, connector_object_id; 521 struct radeon_i2c_bus_rec ddc_bus; 522 struct radeon_router router; 523 struct radeon_gpio_rec gpio; 524 struct radeon_hpd hpd; 525 526 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) 527 return false; 528 529 if (crev < 2) 530 return false; 531 532 obj_header = (ATOM_OBJECT_HEADER *) ((char *)ctx->bios + data_offset); 533 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) 534 ((char *)ctx->bios + data_offset + 535 le16_to_cpu(obj_header->usDisplayPathTableOffset)); 536 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) 537 ((char *)ctx->bios + data_offset + 538 le16_to_cpu(obj_header->usConnectorObjectTableOffset)); 539 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *) 540 ((char *)ctx->bios + data_offset + 541 le16_to_cpu(obj_header->usEncoderObjectTableOffset)); 542 router_obj = (ATOM_OBJECT_TABLE *) 543 ((char *)ctx->bios + data_offset + 544 le16_to_cpu(obj_header->usRouterObjectTableOffset)); 545 device_support = le16_to_cpu(obj_header->usDeviceSupport); 546 547 path_size = 0; 548 for (i = 0; i < path_obj->ucNumOfDispPath; i++) { 549 uint8_t *addr = (uint8_t *) path_obj->asDispPath; 550 ATOM_DISPLAY_OBJECT_PATH *path; 551 addr += path_size; 552 path = (ATOM_DISPLAY_OBJECT_PATH *) addr; 553 path_size += le16_to_cpu(path->usSize); 554 555 if (device_support & le16_to_cpu(path->usDeviceTag)) { 556 uint8_t con_obj_id, con_obj_num, con_obj_type; 557 558 con_obj_id = 559 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) 560 >> OBJECT_ID_SHIFT; 561 con_obj_num = 562 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) 563 >> ENUM_ID_SHIFT; 564 con_obj_type = 565 (le16_to_cpu(path->usConnObjectId) & 566 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 567 568 /* TODO CV support */ 569 if (le16_to_cpu(path->usDeviceTag) == 570 ATOM_DEVICE_CV_SUPPORT) 571 continue; 572 573 /* IGP chips */ 574 if ((rdev->flags & RADEON_IS_IGP) && 575 (con_obj_id == 576 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { 577 uint16_t igp_offset = 0; 578 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj; 579 580 index = 581 GetIndexIntoMasterTable(DATA, 582 IntegratedSystemInfo); 583 584 if (atom_parse_data_header(ctx, index, &size, &frev, 585 &crev, &igp_offset)) { 586 587 if (crev >= 2) { 588 igp_obj = 589 (ATOM_INTEGRATED_SYSTEM_INFO_V2 590 *) ((char *)ctx->bios + igp_offset); 591 592 if (igp_obj) { 593 uint32_t slot_config, ct; 594 595 if (con_obj_num == 1) 596 slot_config = 597 igp_obj-> 598 ulDDISlot1Config; 599 else 600 slot_config = 601 igp_obj-> 602 ulDDISlot2Config; 603 604 ct = (slot_config >> 16) & 0xff; 605 connector_type = 606 object_connector_convert 607 [ct]; 608 connector_object_id = ct; 609 igp_lane_info = 610 slot_config & 0xffff; 611 } else 612 continue; 613 } else 614 continue; 615 } else { 616 igp_lane_info = 0; 617 connector_type = 618 object_connector_convert[con_obj_id]; 619 connector_object_id = con_obj_id; 620 } 621 } else { 622 igp_lane_info = 0; 623 connector_type = 624 object_connector_convert[con_obj_id]; 625 connector_object_id = con_obj_id; 626 } 627 628 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 629 continue; 630 631 router.ddc_valid = false; 632 router.cd_valid = false; 633 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) { 634 uint8_t grph_obj_id, grph_obj_num, grph_obj_type; 635 636 grph_obj_id = 637 (le16_to_cpu(path->usGraphicObjIds[j]) & 638 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 639 grph_obj_num = 640 (le16_to_cpu(path->usGraphicObjIds[j]) & 641 ENUM_ID_MASK) >> ENUM_ID_SHIFT; 642 grph_obj_type = 643 (le16_to_cpu(path->usGraphicObjIds[j]) & 644 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 645 646 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { 647 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) { 648 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID); 649 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) { 650 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 651 ((char *)ctx->bios + data_offset + 652 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset)); 653 ATOM_ENCODER_CAP_RECORD *cap_record; 654 u16 caps = 0; 655 656 while (record->ucRecordSize > 0 && 657 record->ucRecordType > 0 && 658 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 659 switch (record->ucRecordType) { 660 case ATOM_ENCODER_CAP_RECORD_TYPE: 661 cap_record =(ATOM_ENCODER_CAP_RECORD *) 662 record; 663 caps = le16_to_cpu(cap_record->usEncoderCap); 664 break; 665 } 666 record = (ATOM_COMMON_RECORD_HEADER *) 667 ((char *)record + record->ucRecordSize); 668 } 669 radeon_add_atom_encoder(dev, 670 encoder_obj, 671 le16_to_cpu 672 (path-> 673 usDeviceTag), 674 caps); 675 } 676 } 677 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) { 678 for (k = 0; k < router_obj->ucNumberOfObjects; k++) { 679 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID); 680 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) { 681 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 682 ((char *)ctx->bios + data_offset + 683 le16_to_cpu(router_obj->asObjects[k].usRecordOffset)); 684 ATOM_I2C_RECORD *i2c_record; 685 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 686 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path; 687 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path; 688 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table = 689 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) 690 ((char *)ctx->bios + data_offset + 691 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset)); 692 int enum_id; 693 694 router.router_id = router_obj_id; 695 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst; 696 enum_id++) { 697 if (le16_to_cpu(path->usConnObjectId) == 698 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id])) 699 break; 700 } 701 702 while (record->ucRecordSize > 0 && 703 record->ucRecordType > 0 && 704 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 705 switch (record->ucRecordType) { 706 case ATOM_I2C_RECORD_TYPE: 707 i2c_record = 708 (ATOM_I2C_RECORD *) 709 record; 710 i2c_config = 711 (ATOM_I2C_ID_CONFIG_ACCESS *) 712 &i2c_record->sucI2cId; 713 router.i2c_info = 714 radeon_lookup_i2c_gpio(rdev, 715 i2c_config-> 716 ucAccess); 717 router.i2c_addr = i2c_record->ucI2CAddr >> 1; 718 break; 719 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE: 720 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *) 721 record; 722 router.ddc_valid = true; 723 router.ddc_mux_type = ddc_path->ucMuxType; 724 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin; 725 router.ddc_mux_state = ddc_path->ucMuxState[enum_id]; 726 break; 727 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE: 728 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *) 729 record; 730 router.cd_valid = true; 731 router.cd_mux_type = cd_path->ucMuxType; 732 router.cd_mux_control_pin = cd_path->ucMuxControlPin; 733 router.cd_mux_state = cd_path->ucMuxState[enum_id]; 734 break; 735 } 736 record = (ATOM_COMMON_RECORD_HEADER *) 737 ((char *)record + record->ucRecordSize); 738 } 739 } 740 } 741 } 742 } 743 744 /* look up gpio for ddc, hpd */ 745 ddc_bus.valid = false; 746 hpd.hpd = RADEON_HPD_NONE; 747 if ((le16_to_cpu(path->usDeviceTag) & 748 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) { 749 for (j = 0; j < con_obj->ucNumberOfObjects; j++) { 750 if (le16_to_cpu(path->usConnObjectId) == 751 le16_to_cpu(con_obj->asObjects[j]. 752 usObjectID)) { 753 ATOM_COMMON_RECORD_HEADER 754 *record = 755 (ATOM_COMMON_RECORD_HEADER 756 *) 757 ((char *)ctx->bios + data_offset + 758 le16_to_cpu(con_obj-> 759 asObjects[j]. 760 usRecordOffset)); 761 ATOM_I2C_RECORD *i2c_record; 762 ATOM_HPD_INT_RECORD *hpd_record; 763 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 764 765 while (record->ucRecordSize > 0 && 766 record->ucRecordType > 0 && 767 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 768 switch (record->ucRecordType) { 769 case ATOM_I2C_RECORD_TYPE: 770 i2c_record = 771 (ATOM_I2C_RECORD *) 772 record; 773 i2c_config = 774 (ATOM_I2C_ID_CONFIG_ACCESS *) 775 &i2c_record->sucI2cId; 776 ddc_bus = radeon_lookup_i2c_gpio(rdev, 777 i2c_config-> 778 ucAccess); 779 break; 780 case ATOM_HPD_INT_RECORD_TYPE: 781 hpd_record = 782 (ATOM_HPD_INT_RECORD *) 783 record; 784 gpio = radeon_lookup_gpio(rdev, 785 hpd_record->ucHPDIntGPIOID); 786 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio); 787 hpd.plugged_state = hpd_record->ucPlugged_PinState; 788 break; 789 } 790 record = 791 (ATOM_COMMON_RECORD_HEADER 792 *) ((char *)record 793 + 794 record-> 795 ucRecordSize); 796 } 797 break; 798 } 799 } 800 } 801 802 /* needed for aux chan transactions */ 803 ddc_bus.hpd = hpd.hpd; 804 805 conn_id = le16_to_cpu(path->usConnObjectId); 806 807 if (!radeon_atom_apply_quirks 808 (dev, le16_to_cpu(path->usDeviceTag), &connector_type, 809 &ddc_bus, &conn_id, &hpd)) 810 continue; 811 812 radeon_add_atom_connector(dev, 813 conn_id, 814 le16_to_cpu(path-> 815 usDeviceTag), 816 connector_type, &ddc_bus, 817 igp_lane_info, 818 connector_object_id, 819 &hpd, 820 &router); 821 822 } 823 } 824 825 radeon_link_encoder_connector(dev); 826 827 return true; 828 } 829 830 static uint16_t atombios_get_connector_object_id(struct drm_device *dev, 831 int connector_type, 832 uint16_t devices) 833 { 834 struct radeon_device *rdev = dev->dev_private; 835 836 if (rdev->flags & RADEON_IS_IGP) { 837 return supported_devices_connector_object_id_convert 838 [connector_type]; 839 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) || 840 (connector_type == DRM_MODE_CONNECTOR_DVID)) && 841 (devices & ATOM_DEVICE_DFP2_SUPPORT)) { 842 struct radeon_mode_info *mode_info = &rdev->mode_info; 843 struct atom_context *ctx = mode_info->atom_context; 844 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info); 845 uint16_t size, data_offset; 846 uint8_t frev, crev; 847 ATOM_XTMDS_INFO *xtmds; 848 849 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) { 850 xtmds = (ATOM_XTMDS_INFO *)((char *)ctx->bios + data_offset); 851 852 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) { 853 if (connector_type == DRM_MODE_CONNECTOR_DVII) 854 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 855 else 856 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 857 } else { 858 if (connector_type == DRM_MODE_CONNECTOR_DVII) 859 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 860 else 861 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 862 } 863 } else 864 return supported_devices_connector_object_id_convert 865 [connector_type]; 866 } else { 867 return supported_devices_connector_object_id_convert 868 [connector_type]; 869 } 870 } 871 872 struct bios_connector { 873 bool valid; 874 uint16_t line_mux; 875 uint16_t devices; 876 int connector_type; 877 struct radeon_i2c_bus_rec ddc_bus; 878 struct radeon_hpd hpd; 879 }; 880 881 bool radeon_get_atom_connector_info_from_supported_devices_table(struct 882 drm_device 883 *dev) 884 { 885 struct radeon_device *rdev = dev->dev_private; 886 struct radeon_mode_info *mode_info = &rdev->mode_info; 887 struct atom_context *ctx = mode_info->atom_context; 888 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo); 889 uint16_t size, data_offset; 890 uint8_t frev, crev; 891 uint16_t device_support; 892 uint8_t dac; 893 union atom_supported_devices *supported_devices; 894 int i, j, max_device; 895 struct bios_connector *bios_connectors; 896 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE; 897 struct radeon_router router; 898 899 router.ddc_valid = false; 900 router.cd_valid = false; 901 902 bios_connectors = kzalloc(bc_size, GFP_KERNEL); 903 if (!bios_connectors) 904 return false; 905 906 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, 907 &data_offset)) { 908 kfree(bios_connectors); 909 return false; 910 } 911 912 supported_devices = 913 (union atom_supported_devices *)((char *)ctx->bios + data_offset); 914 915 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport); 916 917 if (frev > 1) 918 max_device = ATOM_MAX_SUPPORTED_DEVICE; 919 else 920 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO; 921 922 for (i = 0; i < max_device; i++) { 923 ATOM_CONNECTOR_INFO_I2C ci = 924 supported_devices->info.asConnInfo[i]; 925 926 bios_connectors[i].valid = false; 927 928 if (!(device_support & (1 << i))) { 929 continue; 930 } 931 932 if (i == ATOM_DEVICE_CV_INDEX) { 933 DRM_DEBUG_KMS("Skipping Component Video\n"); 934 continue; 935 } 936 937 bios_connectors[i].connector_type = 938 supported_devices_connector_convert[ci.sucConnectorInfo. 939 sbfAccess. 940 bfConnectorType]; 941 942 if (bios_connectors[i].connector_type == 943 DRM_MODE_CONNECTOR_Unknown) 944 continue; 945 946 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC; 947 948 bios_connectors[i].line_mux = 949 ci.sucI2cId.ucAccess; 950 951 /* give tv unique connector ids */ 952 if (i == ATOM_DEVICE_TV1_INDEX) { 953 bios_connectors[i].ddc_bus.valid = false; 954 bios_connectors[i].line_mux = 50; 955 } else if (i == ATOM_DEVICE_TV2_INDEX) { 956 bios_connectors[i].ddc_bus.valid = false; 957 bios_connectors[i].line_mux = 51; 958 } else if (i == ATOM_DEVICE_CV_INDEX) { 959 bios_connectors[i].ddc_bus.valid = false; 960 bios_connectors[i].line_mux = 52; 961 } else 962 bios_connectors[i].ddc_bus = 963 radeon_lookup_i2c_gpio(rdev, 964 bios_connectors[i].line_mux); 965 966 if ((crev > 1) && (frev > 1)) { 967 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap; 968 switch (isb) { 969 case 0x4: 970 bios_connectors[i].hpd.hpd = RADEON_HPD_1; 971 break; 972 case 0xa: 973 bios_connectors[i].hpd.hpd = RADEON_HPD_2; 974 break; 975 default: 976 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; 977 break; 978 } 979 } else { 980 if (i == ATOM_DEVICE_DFP1_INDEX) 981 bios_connectors[i].hpd.hpd = RADEON_HPD_1; 982 else if (i == ATOM_DEVICE_DFP2_INDEX) 983 bios_connectors[i].hpd.hpd = RADEON_HPD_2; 984 else 985 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; 986 } 987 988 /* Always set the connector type to VGA for CRT1/CRT2. if they are 989 * shared with a DVI port, we'll pick up the DVI connector when we 990 * merge the outputs. Some bioses incorrectly list VGA ports as DVI. 991 */ 992 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) 993 bios_connectors[i].connector_type = 994 DRM_MODE_CONNECTOR_VGA; 995 996 if (!radeon_atom_apply_quirks 997 (dev, (1 << i), &bios_connectors[i].connector_type, 998 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux, 999 &bios_connectors[i].hpd)) 1000 continue; 1001 1002 bios_connectors[i].valid = true; 1003 bios_connectors[i].devices = (1 << i); 1004 1005 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) 1006 radeon_add_atom_encoder(dev, 1007 radeon_get_encoder_enum(dev, 1008 (1 << i), 1009 dac), 1010 (1 << i), 1011 0); 1012 else 1013 radeon_add_legacy_encoder(dev, 1014 radeon_get_encoder_enum(dev, 1015 (1 << i), 1016 dac), 1017 (1 << i)); 1018 } 1019 1020 /* combine shared connectors */ 1021 for (i = 0; i < max_device; i++) { 1022 if (bios_connectors[i].valid) { 1023 for (j = 0; j < max_device; j++) { 1024 if (bios_connectors[j].valid && (i != j)) { 1025 if (bios_connectors[i].line_mux == 1026 bios_connectors[j].line_mux) { 1027 /* make sure not to combine LVDS */ 1028 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1029 bios_connectors[i].line_mux = 53; 1030 bios_connectors[i].ddc_bus.valid = false; 1031 continue; 1032 } 1033 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1034 bios_connectors[j].line_mux = 53; 1035 bios_connectors[j].ddc_bus.valid = false; 1036 continue; 1037 } 1038 /* combine analog and digital for DVI-I */ 1039 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) && 1040 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) || 1041 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) && 1042 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) { 1043 bios_connectors[i].devices |= 1044 bios_connectors[j].devices; 1045 bios_connectors[i].connector_type = 1046 DRM_MODE_CONNECTOR_DVII; 1047 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) 1048 bios_connectors[i].hpd = 1049 bios_connectors[j].hpd; 1050 bios_connectors[j].valid = false; 1051 } 1052 } 1053 } 1054 } 1055 } 1056 } 1057 1058 /* add the connectors */ 1059 for (i = 0; i < max_device; i++) { 1060 if (bios_connectors[i].valid) { 1061 uint16_t connector_object_id = 1062 atombios_get_connector_object_id(dev, 1063 bios_connectors[i].connector_type, 1064 bios_connectors[i].devices); 1065 radeon_add_atom_connector(dev, 1066 bios_connectors[i].line_mux, 1067 bios_connectors[i].devices, 1068 bios_connectors[i]. 1069 connector_type, 1070 &bios_connectors[i].ddc_bus, 1071 0, 1072 connector_object_id, 1073 &bios_connectors[i].hpd, 1074 &router); 1075 } 1076 } 1077 1078 radeon_link_encoder_connector(dev); 1079 1080 kfree(bios_connectors); 1081 return true; 1082 } 1083 1084 union firmware_info { 1085 ATOM_FIRMWARE_INFO info; 1086 ATOM_FIRMWARE_INFO_V1_2 info_12; 1087 ATOM_FIRMWARE_INFO_V1_3 info_13; 1088 ATOM_FIRMWARE_INFO_V1_4 info_14; 1089 ATOM_FIRMWARE_INFO_V2_1 info_21; 1090 ATOM_FIRMWARE_INFO_V2_2 info_22; 1091 }; 1092 1093 bool radeon_atom_get_clock_info(struct drm_device *dev) 1094 { 1095 struct radeon_device *rdev = dev->dev_private; 1096 struct radeon_mode_info *mode_info = &rdev->mode_info; 1097 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 1098 union firmware_info *firmware_info; 1099 uint8_t frev, crev; 1100 struct radeon_pll *p1pll = &rdev->clock.p1pll; 1101 struct radeon_pll *p2pll = &rdev->clock.p2pll; 1102 struct radeon_pll *dcpll = &rdev->clock.dcpll; 1103 struct radeon_pll *spll = &rdev->clock.spll; 1104 struct radeon_pll *mpll = &rdev->clock.mpll; 1105 uint16_t data_offset; 1106 1107 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1108 &frev, &crev, &data_offset)) { 1109 firmware_info = 1110 (union firmware_info *)((char *)mode_info->atom_context->bios + 1111 data_offset); 1112 /* pixel clocks */ 1113 p1pll->reference_freq = 1114 le16_to_cpu(firmware_info->info.usReferenceClock); 1115 p1pll->reference_div = 0; 1116 1117 if (crev < 2) 1118 p1pll->pll_out_min = 1119 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output); 1120 else 1121 p1pll->pll_out_min = 1122 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output); 1123 p1pll->pll_out_max = 1124 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); 1125 1126 if (crev >= 4) { 1127 p1pll->lcd_pll_out_min = 1128 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100; 1129 if (p1pll->lcd_pll_out_min == 0) 1130 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 1131 p1pll->lcd_pll_out_max = 1132 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100; 1133 if (p1pll->lcd_pll_out_max == 0) 1134 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 1135 } else { 1136 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 1137 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 1138 } 1139 1140 if (p1pll->pll_out_min == 0) { 1141 if (ASIC_IS_AVIVO(rdev)) 1142 p1pll->pll_out_min = 64800; 1143 else 1144 p1pll->pll_out_min = 20000; 1145 } 1146 1147 p1pll->pll_in_min = 1148 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input); 1149 p1pll->pll_in_max = 1150 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input); 1151 1152 *p2pll = *p1pll; 1153 1154 /* system clock */ 1155 if (ASIC_IS_DCE4(rdev)) 1156 spll->reference_freq = 1157 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock); 1158 else 1159 spll->reference_freq = 1160 le16_to_cpu(firmware_info->info.usReferenceClock); 1161 spll->reference_div = 0; 1162 1163 spll->pll_out_min = 1164 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output); 1165 spll->pll_out_max = 1166 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output); 1167 1168 /* ??? */ 1169 if (spll->pll_out_min == 0) { 1170 if (ASIC_IS_AVIVO(rdev)) 1171 spll->pll_out_min = 64800; 1172 else 1173 spll->pll_out_min = 20000; 1174 } 1175 1176 spll->pll_in_min = 1177 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input); 1178 spll->pll_in_max = 1179 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); 1180 1181 /* memory clock */ 1182 if (ASIC_IS_DCE4(rdev)) 1183 mpll->reference_freq = 1184 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock); 1185 else 1186 mpll->reference_freq = 1187 le16_to_cpu(firmware_info->info.usReferenceClock); 1188 mpll->reference_div = 0; 1189 1190 mpll->pll_out_min = 1191 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output); 1192 mpll->pll_out_max = 1193 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output); 1194 1195 /* ??? */ 1196 if (mpll->pll_out_min == 0) { 1197 if (ASIC_IS_AVIVO(rdev)) 1198 mpll->pll_out_min = 64800; 1199 else 1200 mpll->pll_out_min = 20000; 1201 } 1202 1203 mpll->pll_in_min = 1204 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input); 1205 mpll->pll_in_max = 1206 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input); 1207 1208 rdev->clock.default_sclk = 1209 le32_to_cpu(firmware_info->info.ulDefaultEngineClock); 1210 rdev->clock.default_mclk = 1211 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); 1212 1213 if (ASIC_IS_DCE4(rdev)) { 1214 rdev->clock.default_dispclk = 1215 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); 1216 if (rdev->clock.default_dispclk == 0) { 1217 if (ASIC_IS_DCE5(rdev)) 1218 rdev->clock.default_dispclk = 54000; /* 540 Mhz */ 1219 else 1220 rdev->clock.default_dispclk = 60000; /* 600 Mhz */ 1221 } 1222 rdev->clock.dp_extclk = 1223 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); 1224 rdev->clock.current_dispclk = rdev->clock.default_dispclk; 1225 } 1226 *dcpll = *p1pll; 1227 1228 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock); 1229 if (rdev->clock.max_pixel_clock == 0) 1230 rdev->clock.max_pixel_clock = 40000; 1231 1232 /* not technically a clock, but... */ 1233 rdev->mode_info.firmware_flags = 1234 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess); 1235 1236 return true; 1237 } 1238 1239 return false; 1240 } 1241 1242 union igp_info { 1243 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 1244 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; 1245 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; 1246 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; 1247 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8; 1248 }; 1249 1250 bool radeon_atombios_sideport_present(struct radeon_device *rdev) 1251 { 1252 struct radeon_mode_info *mode_info = &rdev->mode_info; 1253 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1254 union igp_info *igp_info; 1255 u8 frev, crev; 1256 u16 data_offset; 1257 1258 /* sideport is AMD only */ 1259 if (rdev->family == CHIP_RS600) 1260 return false; 1261 1262 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1263 &frev, &crev, &data_offset)) { 1264 igp_info = (union igp_info *)((char *)mode_info->atom_context->bios + 1265 data_offset); 1266 switch (crev) { 1267 case 1: 1268 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock)) 1269 return true; 1270 break; 1271 case 2: 1272 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock)) 1273 return true; 1274 break; 1275 default: 1276 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 1277 break; 1278 } 1279 } 1280 return false; 1281 } 1282 1283 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 1284 struct radeon_encoder_int_tmds *tmds) 1285 { 1286 struct drm_device *dev = encoder->base.dev; 1287 struct radeon_device *rdev = dev->dev_private; 1288 struct radeon_mode_info *mode_info = &rdev->mode_info; 1289 int index = GetIndexIntoMasterTable(DATA, TMDS_Info); 1290 uint16_t data_offset; 1291 struct _ATOM_TMDS_INFO *tmds_info; 1292 uint8_t frev, crev; 1293 uint16_t maxfreq; 1294 int i; 1295 1296 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1297 &frev, &crev, &data_offset)) { 1298 tmds_info = 1299 (struct _ATOM_TMDS_INFO *)((char *)mode_info->atom_context->bios + 1300 data_offset); 1301 1302 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency); 1303 for (i = 0; i < 4; i++) { 1304 tmds->tmds_pll[i].freq = 1305 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency); 1306 tmds->tmds_pll[i].value = 1307 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f; 1308 tmds->tmds_pll[i].value |= 1309 (tmds_info->asMiscInfo[i]. 1310 ucPLL_VCO_Gain & 0x3f) << 6; 1311 tmds->tmds_pll[i].value |= 1312 (tmds_info->asMiscInfo[i]. 1313 ucPLL_DutyCycle & 0xf) << 12; 1314 tmds->tmds_pll[i].value |= 1315 (tmds_info->asMiscInfo[i]. 1316 ucPLL_VoltageSwing & 0xf) << 16; 1317 1318 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n", 1319 tmds->tmds_pll[i].freq, 1320 tmds->tmds_pll[i].value); 1321 1322 if (maxfreq == tmds->tmds_pll[i].freq) { 1323 tmds->tmds_pll[i].freq = 0xffffffff; 1324 break; 1325 } 1326 } 1327 return true; 1328 } 1329 return false; 1330 } 1331 1332 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 1333 struct radeon_atom_ss *ss, 1334 int id) 1335 { 1336 struct radeon_mode_info *mode_info = &rdev->mode_info; 1337 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info); 1338 uint16_t data_offset, size; 1339 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info; 1340 uint8_t frev, crev; 1341 int i, num_indices; 1342 1343 memset(ss, 0, sizeof(struct radeon_atom_ss)); 1344 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1345 &frev, &crev, &data_offset)) { 1346 ss_info = 1347 (struct _ATOM_SPREAD_SPECTRUM_INFO *)((char *)mode_info->atom_context->bios + data_offset); 1348 1349 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1350 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT); 1351 1352 for (i = 0; i < num_indices; i++) { 1353 if (ss_info->asSS_Info[i].ucSS_Id == id) { 1354 ss->percentage = 1355 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage); 1356 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType; 1357 ss->step = ss_info->asSS_Info[i].ucSS_Step; 1358 ss->delay = ss_info->asSS_Info[i].ucSS_Delay; 1359 ss->range = ss_info->asSS_Info[i].ucSS_Range; 1360 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div; 1361 return true; 1362 } 1363 } 1364 } 1365 return false; 1366 } 1367 1368 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev, 1369 struct radeon_atom_ss *ss, 1370 int id) 1371 { 1372 struct radeon_mode_info *mode_info = &rdev->mode_info; 1373 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1374 u16 data_offset, size; 1375 union igp_info *igp_info; 1376 u8 frev, crev; 1377 u16 percentage = 0, rate = 0; 1378 1379 /* get any igp specific overrides */ 1380 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1381 &frev, &crev, &data_offset)) { 1382 igp_info = (union igp_info *) 1383 ((char *)mode_info->atom_context->bios + data_offset); 1384 switch (crev) { 1385 case 6: 1386 switch (id) { 1387 case ASIC_INTERNAL_SS_ON_TMDS: 1388 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage); 1389 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz); 1390 break; 1391 case ASIC_INTERNAL_SS_ON_HDMI: 1392 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage); 1393 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz); 1394 break; 1395 case ASIC_INTERNAL_SS_ON_LVDS: 1396 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage); 1397 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz); 1398 break; 1399 } 1400 break; 1401 case 7: 1402 switch (id) { 1403 case ASIC_INTERNAL_SS_ON_TMDS: 1404 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage); 1405 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz); 1406 break; 1407 case ASIC_INTERNAL_SS_ON_HDMI: 1408 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage); 1409 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz); 1410 break; 1411 case ASIC_INTERNAL_SS_ON_LVDS: 1412 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage); 1413 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz); 1414 break; 1415 } 1416 break; 1417 case 8: 1418 switch (id) { 1419 case ASIC_INTERNAL_SS_ON_TMDS: 1420 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage); 1421 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz); 1422 break; 1423 case ASIC_INTERNAL_SS_ON_HDMI: 1424 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage); 1425 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz); 1426 break; 1427 case ASIC_INTERNAL_SS_ON_LVDS: 1428 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage); 1429 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz); 1430 break; 1431 } 1432 break; 1433 default: 1434 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 1435 break; 1436 } 1437 if (percentage) 1438 ss->percentage = percentage; 1439 if (rate) 1440 ss->rate = rate; 1441 } 1442 } 1443 1444 union asic_ss_info { 1445 struct _ATOM_ASIC_INTERNAL_SS_INFO info; 1446 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2; 1447 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3; 1448 }; 1449 1450 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 1451 struct radeon_atom_ss *ss, 1452 int id, u32 clock) 1453 { 1454 struct radeon_mode_info *mode_info = &rdev->mode_info; 1455 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 1456 uint16_t data_offset, size; 1457 union asic_ss_info *ss_info; 1458 uint8_t frev, crev; 1459 int i, num_indices; 1460 1461 memset(ss, 0, sizeof(struct radeon_atom_ss)); 1462 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1463 &frev, &crev, &data_offset)) { 1464 1465 ss_info = 1466 (union asic_ss_info *)((char *)mode_info->atom_context->bios + data_offset); 1467 1468 switch (frev) { 1469 case 1: 1470 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1471 sizeof(ATOM_ASIC_SS_ASSIGNMENT); 1472 1473 for (i = 0; i < num_indices; i++) { 1474 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) && 1475 (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) { 1476 ss->percentage = 1477 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage); 1478 ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode; 1479 ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz); 1480 return true; 1481 } 1482 } 1483 break; 1484 case 2: 1485 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1486 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2); 1487 for (i = 0; i < num_indices; i++) { 1488 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) && 1489 (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) { 1490 ss->percentage = 1491 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage); 1492 ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode; 1493 ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz); 1494 if ((crev == 2) && 1495 ((id == ASIC_INTERNAL_ENGINE_SS) || 1496 (id == ASIC_INTERNAL_MEMORY_SS))) 1497 ss->rate /= 100; 1498 return true; 1499 } 1500 } 1501 break; 1502 case 3: 1503 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1504 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3); 1505 for (i = 0; i < num_indices; i++) { 1506 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) && 1507 (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) { 1508 ss->percentage = 1509 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage); 1510 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode; 1511 ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz); 1512 if ((id == ASIC_INTERNAL_ENGINE_SS) || 1513 (id == ASIC_INTERNAL_MEMORY_SS)) 1514 ss->rate /= 100; 1515 if (rdev->flags & RADEON_IS_IGP) 1516 radeon_atombios_get_igp_ss_overrides(rdev, ss, id); 1517 return true; 1518 } 1519 } 1520 break; 1521 default: 1522 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev); 1523 break; 1524 } 1525 1526 } 1527 return false; 1528 } 1529 1530 union lvds_info { 1531 struct _ATOM_LVDS_INFO info; 1532 struct _ATOM_LVDS_INFO_V12 info_12; 1533 }; 1534 1535 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct 1536 radeon_encoder 1537 *encoder) 1538 { 1539 struct drm_device *dev = encoder->base.dev; 1540 struct radeon_device *rdev = dev->dev_private; 1541 struct radeon_mode_info *mode_info = &rdev->mode_info; 1542 int index = GetIndexIntoMasterTable(DATA, LVDS_Info); 1543 uint16_t data_offset, misc; 1544 union lvds_info *lvds_info; 1545 uint8_t frev, crev; 1546 struct radeon_encoder_atom_dig *lvds = NULL; 1547 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1548 1549 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1550 &frev, &crev, &data_offset)) { 1551 lvds_info = 1552 (union lvds_info *)((char *)mode_info->atom_context->bios + data_offset); 1553 lvds = 1554 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 1555 1556 if (!lvds) 1557 return NULL; 1558 1559 lvds->native_mode.clock = 1560 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10; 1561 lvds->native_mode.hdisplay = 1562 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive); 1563 lvds->native_mode.vdisplay = 1564 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive); 1565 lvds->native_mode.htotal = lvds->native_mode.hdisplay + 1566 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time); 1567 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + 1568 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset); 1569 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + 1570 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth); 1571 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + 1572 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time); 1573 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + 1574 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset); 1575 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + 1576 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth); 1577 lvds->panel_pwr_delay = 1578 le16_to_cpu(lvds_info->info.usOffDelayInMs); 1579 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc; 1580 1581 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess); 1582 if (misc & ATOM_VSYNC_POLARITY) 1583 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC; 1584 if (misc & ATOM_HSYNC_POLARITY) 1585 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC; 1586 if (misc & ATOM_COMPOSITESYNC) 1587 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC; 1588 if (misc & ATOM_INTERLACE) 1589 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE; 1590 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1591 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN; 1592 1593 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize); 1594 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize); 1595 1596 /* set crtc values */ 1597 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); 1598 1599 lvds->lcd_ss_id = lvds_info->info.ucSS_Id; 1600 1601 encoder->native_mode = lvds->native_mode; 1602 1603 if (encoder_enum == 2) 1604 lvds->linkb = true; 1605 else 1606 lvds->linkb = false; 1607 1608 /* parse the lcd record table */ 1609 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) { 1610 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record; 1611 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record; 1612 bool bad_record = false; 1613 u8 *record; 1614 1615 if ((frev == 1) && (crev < 2)) 1616 /* absolute */ 1617 record = (u8 *)((char *)mode_info->atom_context->bios + 1618 le16_to_cpu(lvds_info->info.usModePatchTableOffset)); 1619 else 1620 /* relative */ 1621 record = (u8 *)((char *)mode_info->atom_context->bios + 1622 data_offset + 1623 le16_to_cpu(lvds_info->info.usModePatchTableOffset)); 1624 while (*record != ATOM_RECORD_END_TYPE) { 1625 switch (*record) { 1626 case LCD_MODE_PATCH_RECORD_MODE_TYPE: 1627 record += sizeof(ATOM_PATCH_RECORD_MODE); 1628 break; 1629 case LCD_RTS_RECORD_TYPE: 1630 record += sizeof(ATOM_LCD_RTS_RECORD); 1631 break; 1632 case LCD_CAP_RECORD_TYPE: 1633 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP); 1634 break; 1635 case LCD_FAKE_EDID_PATCH_RECORD_TYPE: 1636 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record; 1637 if (fake_edid_record->ucFakeEDIDLength) { 1638 struct edid *edid; 1639 int edid_size = 1640 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength); 1641 edid = kmalloc(edid_size, M_DRM, M_WAITOK); 1642 if (edid) { 1643 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0], 1644 fake_edid_record->ucFakeEDIDLength); 1645 1646 if (drm_edid_is_valid(edid)) { 1647 rdev->mode_info.bios_hardcoded_edid = edid; 1648 rdev->mode_info.bios_hardcoded_edid_size = edid_size; 1649 } else 1650 kfree(edid); 1651 } 1652 } 1653 record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD); 1654 break; 1655 case LCD_PANEL_RESOLUTION_RECORD_TYPE: 1656 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record; 1657 lvds->native_mode.width_mm = panel_res_record->usHSize; 1658 lvds->native_mode.height_mm = panel_res_record->usVSize; 1659 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD); 1660 break; 1661 default: 1662 DRM_ERROR("Bad LCD record %d\n", *record); 1663 bad_record = true; 1664 break; 1665 } 1666 if (bad_record) 1667 break; 1668 } 1669 } 1670 } 1671 return lvds; 1672 } 1673 1674 struct radeon_encoder_primary_dac * 1675 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder) 1676 { 1677 struct drm_device *dev = encoder->base.dev; 1678 struct radeon_device *rdev = dev->dev_private; 1679 struct radeon_mode_info *mode_info = &rdev->mode_info; 1680 int index = GetIndexIntoMasterTable(DATA, CompassionateData); 1681 uint16_t data_offset; 1682 struct _COMPASSIONATE_DATA *dac_info; 1683 uint8_t frev, crev; 1684 uint8_t bg, dac; 1685 struct radeon_encoder_primary_dac *p_dac = NULL; 1686 1687 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1688 &frev, &crev, &data_offset)) { 1689 dac_info = (struct _COMPASSIONATE_DATA *) 1690 ((char *)mode_info->atom_context->bios + data_offset); 1691 1692 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL); 1693 1694 if (!p_dac) 1695 return NULL; 1696 1697 bg = dac_info->ucDAC1_BG_Adjustment; 1698 dac = dac_info->ucDAC1_DAC_Adjustment; 1699 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 1700 1701 } 1702 return p_dac; 1703 } 1704 1705 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 1706 struct drm_display_mode *mode) 1707 { 1708 struct radeon_mode_info *mode_info = &rdev->mode_info; 1709 ATOM_ANALOG_TV_INFO *tv_info; 1710 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2; 1711 ATOM_DTD_FORMAT *dtd_timings; 1712 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); 1713 u8 frev, crev; 1714 u16 data_offset, misc; 1715 1716 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL, 1717 &frev, &crev, &data_offset)) 1718 return false; 1719 1720 switch (crev) { 1721 case 1: 1722 tv_info = (ATOM_ANALOG_TV_INFO *)((char *)mode_info->atom_context->bios + data_offset); 1723 if (index >= MAX_SUPPORTED_TV_TIMING) 1724 return false; 1725 1726 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); 1727 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp); 1728 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart); 1729 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) + 1730 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth); 1731 1732 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total); 1733 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp); 1734 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart); 1735 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) + 1736 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth); 1737 1738 mode->flags = 0; 1739 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess); 1740 if (misc & ATOM_VSYNC_POLARITY) 1741 mode->flags |= DRM_MODE_FLAG_NVSYNC; 1742 if (misc & ATOM_HSYNC_POLARITY) 1743 mode->flags |= DRM_MODE_FLAG_NHSYNC; 1744 if (misc & ATOM_COMPOSITESYNC) 1745 mode->flags |= DRM_MODE_FLAG_CSYNC; 1746 if (misc & ATOM_INTERLACE) 1747 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1748 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1749 mode->flags |= DRM_MODE_FLAG_DBLSCAN; 1750 1751 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; 1752 1753 if (index == 1) { 1754 /* PAL timings appear to have wrong values for totals */ 1755 mode->crtc_htotal -= 1; 1756 mode->crtc_vtotal -= 1; 1757 } 1758 break; 1759 case 2: 1760 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)((char *)mode_info->atom_context->bios + data_offset); 1761 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2) 1762 return false; 1763 1764 dtd_timings = &tv_info_v1_2->aModeTimings[index]; 1765 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) + 1766 le16_to_cpu(dtd_timings->usHBlanking_Time); 1767 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive); 1768 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) + 1769 le16_to_cpu(dtd_timings->usHSyncOffset); 1770 mode->crtc_hsync_end = mode->crtc_hsync_start + 1771 le16_to_cpu(dtd_timings->usHSyncWidth); 1772 1773 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) + 1774 le16_to_cpu(dtd_timings->usVBlanking_Time); 1775 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive); 1776 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) + 1777 le16_to_cpu(dtd_timings->usVSyncOffset); 1778 mode->crtc_vsync_end = mode->crtc_vsync_start + 1779 le16_to_cpu(dtd_timings->usVSyncWidth); 1780 1781 mode->flags = 0; 1782 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess); 1783 if (misc & ATOM_VSYNC_POLARITY) 1784 mode->flags |= DRM_MODE_FLAG_NVSYNC; 1785 if (misc & ATOM_HSYNC_POLARITY) 1786 mode->flags |= DRM_MODE_FLAG_NHSYNC; 1787 if (misc & ATOM_COMPOSITESYNC) 1788 mode->flags |= DRM_MODE_FLAG_CSYNC; 1789 if (misc & ATOM_INTERLACE) 1790 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1791 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1792 mode->flags |= DRM_MODE_FLAG_DBLSCAN; 1793 1794 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10; 1795 break; 1796 } 1797 return true; 1798 } 1799 1800 enum radeon_tv_std 1801 radeon_atombios_get_tv_info(struct radeon_device *rdev) 1802 { 1803 struct radeon_mode_info *mode_info = &rdev->mode_info; 1804 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); 1805 uint16_t data_offset; 1806 uint8_t frev, crev; 1807 struct _ATOM_ANALOG_TV_INFO *tv_info; 1808 enum radeon_tv_std tv_std = TV_STD_NTSC; 1809 1810 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1811 &frev, &crev, &data_offset)) { 1812 1813 tv_info = (struct _ATOM_ANALOG_TV_INFO *) 1814 ((char *)mode_info->atom_context->bios + data_offset); 1815 1816 switch (tv_info->ucTV_BootUpDefaultStandard) { 1817 case ATOM_TV_NTSC: 1818 tv_std = TV_STD_NTSC; 1819 DRM_DEBUG_KMS("Default TV standard: NTSC\n"); 1820 break; 1821 case ATOM_TV_NTSCJ: 1822 tv_std = TV_STD_NTSC_J; 1823 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); 1824 break; 1825 case ATOM_TV_PAL: 1826 tv_std = TV_STD_PAL; 1827 DRM_DEBUG_KMS("Default TV standard: PAL\n"); 1828 break; 1829 case ATOM_TV_PALM: 1830 tv_std = TV_STD_PAL_M; 1831 DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); 1832 break; 1833 case ATOM_TV_PALN: 1834 tv_std = TV_STD_PAL_N; 1835 DRM_DEBUG_KMS("Default TV standard: PAL-N\n"); 1836 break; 1837 case ATOM_TV_PALCN: 1838 tv_std = TV_STD_PAL_CN; 1839 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n"); 1840 break; 1841 case ATOM_TV_PAL60: 1842 tv_std = TV_STD_PAL_60; 1843 DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); 1844 break; 1845 case ATOM_TV_SECAM: 1846 tv_std = TV_STD_SECAM; 1847 DRM_DEBUG_KMS("Default TV standard: SECAM\n"); 1848 break; 1849 default: 1850 tv_std = TV_STD_NTSC; 1851 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n"); 1852 break; 1853 } 1854 } 1855 return tv_std; 1856 } 1857 1858 struct radeon_encoder_tv_dac * 1859 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) 1860 { 1861 struct drm_device *dev = encoder->base.dev; 1862 struct radeon_device *rdev = dev->dev_private; 1863 struct radeon_mode_info *mode_info = &rdev->mode_info; 1864 int index = GetIndexIntoMasterTable(DATA, CompassionateData); 1865 uint16_t data_offset; 1866 struct _COMPASSIONATE_DATA *dac_info; 1867 uint8_t frev, crev; 1868 uint8_t bg, dac; 1869 struct radeon_encoder_tv_dac *tv_dac = NULL; 1870 1871 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1872 &frev, &crev, &data_offset)) { 1873 1874 dac_info = (struct _COMPASSIONATE_DATA *) 1875 ((char *)mode_info->atom_context->bios + data_offset); 1876 1877 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); 1878 1879 if (!tv_dac) 1880 return NULL; 1881 1882 bg = dac_info->ucDAC2_CRT2_BG_Adjustment; 1883 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment; 1884 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1885 1886 bg = dac_info->ucDAC2_PAL_BG_Adjustment; 1887 dac = dac_info->ucDAC2_PAL_DAC_Adjustment; 1888 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1889 1890 bg = dac_info->ucDAC2_NTSC_BG_Adjustment; 1891 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment; 1892 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1893 1894 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev); 1895 } 1896 return tv_dac; 1897 } 1898 1899 static const char *thermal_controller_names[] = { 1900 "NONE", 1901 "lm63", 1902 "adm1032", 1903 "adm1030", 1904 "max6649", 1905 "lm64", 1906 "f75375", 1907 "asc7xxx", 1908 }; 1909 1910 static const char *pp_lib_thermal_controller_names[] = { 1911 "NONE", 1912 "lm63", 1913 "adm1032", 1914 "adm1030", 1915 "max6649", 1916 "lm64", 1917 "f75375", 1918 "RV6xx", 1919 "RV770", 1920 "adt7473", 1921 "NONE", 1922 "External GPIO", 1923 "Evergreen", 1924 "emc2103", 1925 "Sumo", 1926 "Northern Islands", 1927 "Southern Islands", 1928 "lm96163", 1929 "Sea Islands", 1930 }; 1931 1932 union power_info { 1933 struct _ATOM_POWERPLAY_INFO info; 1934 struct _ATOM_POWERPLAY_INFO_V2 info_2; 1935 struct _ATOM_POWERPLAY_INFO_V3 info_3; 1936 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 1937 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 1938 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 1939 }; 1940 1941 union pplib_clock_info { 1942 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 1943 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 1944 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 1945 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 1946 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 1947 struct _ATOM_PPLIB_CI_CLOCK_INFO ci; 1948 }; 1949 1950 union pplib_power_state { 1951 struct _ATOM_PPLIB_STATE v1; 1952 struct _ATOM_PPLIB_STATE_V2 v2; 1953 }; 1954 1955 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev, 1956 int state_index, 1957 u32 misc, u32 misc2) 1958 { 1959 rdev->pm.power_state[state_index].misc = misc; 1960 rdev->pm.power_state[state_index].misc2 = misc2; 1961 /* order matters! */ 1962 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) 1963 rdev->pm.power_state[state_index].type = 1964 POWER_STATE_TYPE_POWERSAVE; 1965 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE) 1966 rdev->pm.power_state[state_index].type = 1967 POWER_STATE_TYPE_BATTERY; 1968 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE) 1969 rdev->pm.power_state[state_index].type = 1970 POWER_STATE_TYPE_BATTERY; 1971 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN) 1972 rdev->pm.power_state[state_index].type = 1973 POWER_STATE_TYPE_BALANCED; 1974 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) { 1975 rdev->pm.power_state[state_index].type = 1976 POWER_STATE_TYPE_PERFORMANCE; 1977 rdev->pm.power_state[state_index].flags &= 1978 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 1979 } 1980 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE) 1981 rdev->pm.power_state[state_index].type = 1982 POWER_STATE_TYPE_BALANCED; 1983 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { 1984 rdev->pm.power_state[state_index].type = 1985 POWER_STATE_TYPE_DEFAULT; 1986 rdev->pm.default_power_state_index = state_index; 1987 rdev->pm.power_state[state_index].default_clock_mode = 1988 &rdev->pm.power_state[state_index].clock_info[0]; 1989 } else if (state_index == 0) { 1990 rdev->pm.power_state[state_index].clock_info[0].flags |= 1991 RADEON_PM_MODE_NO_DISPLAY; 1992 } 1993 } 1994 1995 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev) 1996 { 1997 struct radeon_mode_info *mode_info = &rdev->mode_info; 1998 u32 misc, misc2 = 0; 1999 int num_modes = 0, i; 2000 int state_index = 0; 2001 struct radeon_i2c_bus_rec i2c_bus; 2002 union power_info *power_info; 2003 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2004 u16 data_offset; 2005 u8 frev, crev; 2006 2007 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2008 &frev, &crev, &data_offset)) 2009 return state_index; 2010 power_info = (union power_info *)((char *)mode_info->atom_context->bios + data_offset); 2011 2012 /* add the i2c bus for thermal/fan chip */ 2013 if ((power_info->info.ucOverdriveThermalController > 0) && 2014 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) { 2015 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 2016 thermal_controller_names[power_info->info.ucOverdriveThermalController], 2017 power_info->info.ucOverdriveControllerAddress >> 1); 2018 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine); 2019 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2020 #ifdef DUMBBELL_WIP 2021 if (rdev->pm.i2c_bus) { 2022 struct i2c_board_info info = { }; 2023 const char *name = thermal_controller_names[power_info->info. 2024 ucOverdriveThermalController]; 2025 info.addr = power_info->info.ucOverdriveControllerAddress >> 1; 2026 strlcpy(info.type, name, sizeof(info.type)); 2027 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); 2028 } 2029 #endif /* DUMBBELL_WIP */ 2030 } 2031 num_modes = power_info->info.ucNumOfPowerModeEntries; 2032 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK) 2033 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK; 2034 if (num_modes == 0) 2035 return state_index; 2036 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL); 2037 if (!rdev->pm.power_state) 2038 return state_index; 2039 /* last mode is usually default, array is low to high */ 2040 for (i = 0; i < num_modes; i++) { 2041 rdev->pm.power_state[state_index].clock_info = 2042 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); 2043 if (!rdev->pm.power_state[state_index].clock_info) 2044 return state_index; 2045 rdev->pm.power_state[state_index].num_clock_modes = 1; 2046 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2047 switch (frev) { 2048 case 1: 2049 rdev->pm.power_state[state_index].clock_info[0].mclk = 2050 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock); 2051 rdev->pm.power_state[state_index].clock_info[0].sclk = 2052 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock); 2053 /* skip invalid modes */ 2054 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2055 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2056 continue; 2057 rdev->pm.power_state[state_index].pcie_lanes = 2058 power_info->info.asPowerPlayInfo[i].ucNumPciELanes; 2059 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo); 2060 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2061 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2062 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2063 VOLTAGE_GPIO; 2064 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2065 radeon_lookup_gpio(rdev, 2066 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex); 2067 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2068 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2069 true; 2070 else 2071 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2072 false; 2073 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2074 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2075 VOLTAGE_VDDC; 2076 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2077 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex; 2078 } 2079 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2080 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0); 2081 state_index++; 2082 break; 2083 case 2: 2084 rdev->pm.power_state[state_index].clock_info[0].mclk = 2085 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock); 2086 rdev->pm.power_state[state_index].clock_info[0].sclk = 2087 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock); 2088 /* skip invalid modes */ 2089 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2090 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2091 continue; 2092 rdev->pm.power_state[state_index].pcie_lanes = 2093 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes; 2094 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo); 2095 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2); 2096 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2097 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2098 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2099 VOLTAGE_GPIO; 2100 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2101 radeon_lookup_gpio(rdev, 2102 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex); 2103 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2104 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2105 true; 2106 else 2107 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2108 false; 2109 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2110 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2111 VOLTAGE_VDDC; 2112 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2113 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex; 2114 } 2115 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2116 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); 2117 state_index++; 2118 break; 2119 case 3: 2120 rdev->pm.power_state[state_index].clock_info[0].mclk = 2121 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock); 2122 rdev->pm.power_state[state_index].clock_info[0].sclk = 2123 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock); 2124 /* skip invalid modes */ 2125 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2126 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2127 continue; 2128 rdev->pm.power_state[state_index].pcie_lanes = 2129 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes; 2130 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo); 2131 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2); 2132 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2133 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2134 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2135 VOLTAGE_GPIO; 2136 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2137 radeon_lookup_gpio(rdev, 2138 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex); 2139 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2140 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2141 true; 2142 else 2143 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2144 false; 2145 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2146 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2147 VOLTAGE_VDDC; 2148 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2149 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex; 2150 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) { 2151 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled = 2152 true; 2153 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id = 2154 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex; 2155 } 2156 } 2157 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2158 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); 2159 state_index++; 2160 break; 2161 } 2162 } 2163 /* last mode is usually default */ 2164 if (rdev->pm.default_power_state_index == -1) { 2165 rdev->pm.power_state[state_index - 1].type = 2166 POWER_STATE_TYPE_DEFAULT; 2167 rdev->pm.default_power_state_index = state_index - 1; 2168 rdev->pm.power_state[state_index - 1].default_clock_mode = 2169 &rdev->pm.power_state[state_index - 1].clock_info[0]; 2170 rdev->pm.power_state[state_index].flags &= 2171 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2172 rdev->pm.power_state[state_index].misc = 0; 2173 rdev->pm.power_state[state_index].misc2 = 0; 2174 } 2175 return state_index; 2176 } 2177 2178 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev, 2179 ATOM_PPLIB_THERMALCONTROLLER *controller) 2180 { 2181 struct radeon_i2c_bus_rec i2c_bus; 2182 2183 /* add the i2c bus for thermal/fan chip */ 2184 if (controller->ucType > 0) { 2185 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) { 2186 DRM_INFO("Internal thermal controller %s fan control\n", 2187 (controller->ucFanParameters & 2188 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2189 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX; 2190 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) { 2191 DRM_INFO("Internal thermal controller %s fan control\n", 2192 (controller->ucFanParameters & 2193 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2194 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770; 2195 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) { 2196 DRM_INFO("Internal thermal controller %s fan control\n", 2197 (controller->ucFanParameters & 2198 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2199 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN; 2200 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) { 2201 DRM_INFO("Internal thermal controller %s fan control\n", 2202 (controller->ucFanParameters & 2203 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2204 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO; 2205 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) { 2206 DRM_INFO("Internal thermal controller %s fan control\n", 2207 (controller->ucFanParameters & 2208 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2209 rdev->pm.int_thermal_type = THERMAL_TYPE_NI; 2210 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) { 2211 DRM_INFO("Internal thermal controller %s fan control\n", 2212 (controller->ucFanParameters & 2213 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2214 rdev->pm.int_thermal_type = THERMAL_TYPE_SI; 2215 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) { 2216 DRM_INFO("Internal thermal controller %s fan control\n", 2217 (controller->ucFanParameters & 2218 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2219 rdev->pm.int_thermal_type = THERMAL_TYPE_CI; 2220 } else if ((controller->ucType == 2221 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) || 2222 (controller->ucType == 2223 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) || 2224 (controller->ucType == 2225 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) { 2226 DRM_INFO("Special thermal controller config\n"); 2227 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) { 2228 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n", 2229 pp_lib_thermal_controller_names[controller->ucType], 2230 controller->ucI2cAddress >> 1, 2231 (controller->ucFanParameters & 2232 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2233 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine); 2234 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2235 #ifdef DUMBBELL_WIP 2236 if (rdev->pm.i2c_bus) { 2237 struct i2c_board_info info = { }; 2238 const char *name = pp_lib_thermal_controller_names[controller->ucType]; 2239 info.addr = controller->ucI2cAddress >> 1; 2240 strlcpy(info.type, name, sizeof(info.type)); 2241 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); 2242 } 2243 #endif /* DUMBBELL_WIP */ 2244 } else { 2245 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n", 2246 controller->ucType, 2247 controller->ucI2cAddress >> 1, 2248 (controller->ucFanParameters & 2249 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2250 } 2251 } 2252 } 2253 2254 void radeon_atombios_get_default_voltages(struct radeon_device *rdev, 2255 u16 *vddc, u16 *vddci, u16 *mvdd) 2256 { 2257 struct radeon_mode_info *mode_info = &rdev->mode_info; 2258 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 2259 u8 frev, crev; 2260 u16 data_offset; 2261 union firmware_info *firmware_info; 2262 2263 *vddc = 0; 2264 *vddci = 0; 2265 *mvdd = 0; 2266 2267 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 2268 &frev, &crev, &data_offset)) { 2269 firmware_info = 2270 (union firmware_info *)((char *)mode_info->atom_context->bios + 2271 data_offset); 2272 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage); 2273 if ((frev == 2) && (crev >= 2)) { 2274 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage); 2275 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage); 2276 } 2277 } 2278 } 2279 2280 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev, 2281 int state_index, int mode_index, 2282 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info) 2283 { 2284 int j; 2285 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings); 2286 u32 misc2 = le16_to_cpu(non_clock_info->usClassification); 2287 u16 vddc, vddci, mvdd; 2288 2289 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 2290 2291 rdev->pm.power_state[state_index].misc = misc; 2292 rdev->pm.power_state[state_index].misc2 = misc2; 2293 rdev->pm.power_state[state_index].pcie_lanes = 2294 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> 2295 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 2296 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { 2297 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: 2298 rdev->pm.power_state[state_index].type = 2299 POWER_STATE_TYPE_BATTERY; 2300 break; 2301 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED: 2302 rdev->pm.power_state[state_index].type = 2303 POWER_STATE_TYPE_BALANCED; 2304 break; 2305 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: 2306 rdev->pm.power_state[state_index].type = 2307 POWER_STATE_TYPE_PERFORMANCE; 2308 break; 2309 case ATOM_PPLIB_CLASSIFICATION_UI_NONE: 2310 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) 2311 rdev->pm.power_state[state_index].type = 2312 POWER_STATE_TYPE_PERFORMANCE; 2313 break; 2314 } 2315 rdev->pm.power_state[state_index].flags = 0; 2316 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) 2317 rdev->pm.power_state[state_index].flags |= 2318 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2319 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) { 2320 rdev->pm.power_state[state_index].type = 2321 POWER_STATE_TYPE_DEFAULT; 2322 rdev->pm.default_power_state_index = state_index; 2323 rdev->pm.power_state[state_index].default_clock_mode = 2324 &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; 2325 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) { 2326 /* NI chips post without MC ucode, so default clocks are strobe mode only */ 2327 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk; 2328 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk; 2329 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage; 2330 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci; 2331 } else { 2332 u16 max_vddci = 0; 2333 2334 if (ASIC_IS_DCE4(rdev)) 2335 radeon_atom_get_max_voltage(rdev, 2336 SET_VOLTAGE_TYPE_ASIC_VDDCI, 2337 &max_vddci); 2338 /* patch the table values with the default sclk/mclk from firmware info */ 2339 for (j = 0; j < mode_index; j++) { 2340 rdev->pm.power_state[state_index].clock_info[j].mclk = 2341 rdev->clock.default_mclk; 2342 rdev->pm.power_state[state_index].clock_info[j].sclk = 2343 rdev->clock.default_sclk; 2344 if (vddc) 2345 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage = 2346 vddc; 2347 if (max_vddci) 2348 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci = 2349 max_vddci; 2350 } 2351 } 2352 } 2353 } 2354 2355 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev, 2356 int state_index, int mode_index, 2357 union pplib_clock_info *clock_info) 2358 { 2359 u32 sclk, mclk; 2360 u16 vddc; 2361 2362 if (rdev->flags & RADEON_IS_IGP) { 2363 if (rdev->family >= CHIP_PALM) { 2364 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); 2365 sclk |= clock_info->sumo.ucEngineClockHigh << 16; 2366 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2367 } else { 2368 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow); 2369 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16; 2370 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2371 } 2372 } else if (rdev->family >= CHIP_BONAIRE) { 2373 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); 2374 sclk |= clock_info->ci.ucEngineClockHigh << 16; 2375 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); 2376 mclk |= clock_info->ci.ucMemoryClockHigh << 16; 2377 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2378 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2379 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2380 VOLTAGE_NONE; 2381 } else if (rdev->family >= CHIP_TAHITI) { 2382 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 2383 sclk |= clock_info->si.ucEngineClockHigh << 16; 2384 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 2385 mclk |= clock_info->si.ucMemoryClockHigh << 16; 2386 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2387 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2388 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2389 VOLTAGE_SW; 2390 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2391 le16_to_cpu(clock_info->si.usVDDC); 2392 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = 2393 le16_to_cpu(clock_info->si.usVDDCI); 2394 } else if (rdev->family >= CHIP_CEDAR) { 2395 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow); 2396 sclk |= clock_info->evergreen.ucEngineClockHigh << 16; 2397 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow); 2398 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16; 2399 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2400 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2401 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2402 VOLTAGE_SW; 2403 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2404 le16_to_cpu(clock_info->evergreen.usVDDC); 2405 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = 2406 le16_to_cpu(clock_info->evergreen.usVDDCI); 2407 } else { 2408 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow); 2409 sclk |= clock_info->r600.ucEngineClockHigh << 16; 2410 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow); 2411 mclk |= clock_info->r600.ucMemoryClockHigh << 16; 2412 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2413 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2414 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2415 VOLTAGE_SW; 2416 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2417 le16_to_cpu(clock_info->r600.usVDDC); 2418 } 2419 2420 /* patch up vddc if necessary */ 2421 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) { 2422 case ATOM_VIRTUAL_VOLTAGE_ID0: 2423 case ATOM_VIRTUAL_VOLTAGE_ID1: 2424 case ATOM_VIRTUAL_VOLTAGE_ID2: 2425 case ATOM_VIRTUAL_VOLTAGE_ID3: 2426 case ATOM_VIRTUAL_VOLTAGE_ID4: 2427 case ATOM_VIRTUAL_VOLTAGE_ID5: 2428 case ATOM_VIRTUAL_VOLTAGE_ID6: 2429 case ATOM_VIRTUAL_VOLTAGE_ID7: 2430 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, 2431 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage, 2432 &vddc) == 0) 2433 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc; 2434 break; 2435 default: 2436 break; 2437 } 2438 2439 if (rdev->flags & RADEON_IS_IGP) { 2440 /* skip invalid modes */ 2441 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0) 2442 return false; 2443 } else { 2444 /* skip invalid modes */ 2445 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) || 2446 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)) 2447 return false; 2448 } 2449 return true; 2450 } 2451 2452 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev) 2453 { 2454 struct radeon_mode_info *mode_info = &rdev->mode_info; 2455 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 2456 union pplib_power_state *power_state; 2457 int i, j; 2458 int state_index = 0, mode_index = 0; 2459 union pplib_clock_info *clock_info; 2460 bool valid; 2461 union power_info *power_info; 2462 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2463 u16 data_offset; 2464 u8 frev, crev; 2465 2466 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2467 &frev, &crev, &data_offset)) 2468 return state_index; 2469 power_info = (union power_info *)((char *)mode_info->atom_context->bios + data_offset); 2470 2471 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); 2472 if (power_info->pplib.ucNumStates == 0) 2473 return state_index; 2474 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2475 power_info->pplib.ucNumStates, GFP_KERNEL); 2476 if (!rdev->pm.power_state) 2477 return state_index; 2478 /* first mode is usually default, followed by low to high */ 2479 for (i = 0; i < power_info->pplib.ucNumStates; i++) { 2480 mode_index = 0; 2481 power_state = (union pplib_power_state *) 2482 ((char *)mode_info->atom_context->bios + data_offset + 2483 le16_to_cpu(power_info->pplib.usStateArrayOffset) + 2484 i * power_info->pplib.ucStateEntrySize); 2485 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2486 ((char *)mode_info->atom_context->bios + data_offset + 2487 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) + 2488 (power_state->v1.ucNonClockStateIndex * 2489 power_info->pplib.ucNonClockSize)); 2490 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) * 2491 ((power_info->pplib.ucStateEntrySize - 1) ? 2492 (power_info->pplib.ucStateEntrySize - 1) : 1), 2493 GFP_KERNEL); 2494 if (!rdev->pm.power_state[i].clock_info) 2495 return state_index; 2496 if (power_info->pplib.ucStateEntrySize - 1) { 2497 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) { 2498 clock_info = (union pplib_clock_info *) 2499 ((char *)mode_info->atom_context->bios + data_offset + 2500 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) + 2501 (power_state->v1.ucClockStateIndices[j] * 2502 power_info->pplib.ucClockInfoSize)); 2503 valid = radeon_atombios_parse_pplib_clock_info(rdev, 2504 state_index, mode_index, 2505 clock_info); 2506 if (valid) 2507 mode_index++; 2508 } 2509 } else { 2510 rdev->pm.power_state[state_index].clock_info[0].mclk = 2511 rdev->clock.default_mclk; 2512 rdev->pm.power_state[state_index].clock_info[0].sclk = 2513 rdev->clock.default_sclk; 2514 mode_index++; 2515 } 2516 rdev->pm.power_state[state_index].num_clock_modes = mode_index; 2517 if (mode_index) { 2518 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index, 2519 non_clock_info); 2520 state_index++; 2521 } 2522 } 2523 /* if multiple clock modes, mark the lowest as no display */ 2524 for (i = 0; i < state_index; i++) { 2525 if (rdev->pm.power_state[i].num_clock_modes > 1) 2526 rdev->pm.power_state[i].clock_info[0].flags |= 2527 RADEON_PM_MODE_NO_DISPLAY; 2528 } 2529 /* first mode is usually default */ 2530 if (rdev->pm.default_power_state_index == -1) { 2531 rdev->pm.power_state[0].type = 2532 POWER_STATE_TYPE_DEFAULT; 2533 rdev->pm.default_power_state_index = 0; 2534 rdev->pm.power_state[0].default_clock_mode = 2535 &rdev->pm.power_state[0].clock_info[0]; 2536 } 2537 return state_index; 2538 } 2539 2540 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev) 2541 { 2542 struct radeon_mode_info *mode_info = &rdev->mode_info; 2543 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 2544 union pplib_power_state *power_state; 2545 int i, j, non_clock_array_index, clock_array_index; 2546 int state_index = 0, mode_index = 0; 2547 union pplib_clock_info *clock_info; 2548 struct _StateArray *state_array; 2549 struct _ClockInfoArray *clock_info_array; 2550 struct _NonClockInfoArray *non_clock_info_array; 2551 bool valid; 2552 union power_info *power_info; 2553 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2554 u16 data_offset; 2555 u8 frev, crev; 2556 u8 *power_state_offset; 2557 2558 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2559 &frev, &crev, &data_offset)) 2560 return state_index; 2561 power_info = (union power_info *)((char *)mode_info->atom_context->bios + data_offset); 2562 2563 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); 2564 state_array = (struct _StateArray *) 2565 ((char *)mode_info->atom_context->bios + data_offset + 2566 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 2567 clock_info_array = (struct _ClockInfoArray *) 2568 ((char *)mode_info->atom_context->bios + data_offset + 2569 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 2570 non_clock_info_array = (struct _NonClockInfoArray *) 2571 ((char *)mode_info->atom_context->bios + data_offset + 2572 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 2573 if (state_array->ucNumEntries == 0) 2574 return state_index; 2575 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2576 state_array->ucNumEntries, GFP_KERNEL); 2577 if (!rdev->pm.power_state) 2578 return state_index; 2579 power_state_offset = (u8 *)state_array->states; 2580 for (i = 0; i < state_array->ucNumEntries; i++) { 2581 mode_index = 0; 2582 power_state = (union pplib_power_state *)power_state_offset; 2583 non_clock_array_index = power_state->v2.nonClockInfoIndex; 2584 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2585 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 2586 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) * 2587 (power_state->v2.ucNumDPMLevels ? 2588 power_state->v2.ucNumDPMLevels : 1), 2589 GFP_KERNEL); 2590 if (!rdev->pm.power_state[i].clock_info) 2591 return state_index; 2592 if (power_state->v2.ucNumDPMLevels) { 2593 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 2594 clock_array_index = power_state->v2.clockInfoIndex[j]; 2595 clock_info = (union pplib_clock_info *) 2596 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 2597 valid = radeon_atombios_parse_pplib_clock_info(rdev, 2598 state_index, mode_index, 2599 clock_info); 2600 if (valid) 2601 mode_index++; 2602 } 2603 } else { 2604 rdev->pm.power_state[state_index].clock_info[0].mclk = 2605 rdev->clock.default_mclk; 2606 rdev->pm.power_state[state_index].clock_info[0].sclk = 2607 rdev->clock.default_sclk; 2608 mode_index++; 2609 } 2610 rdev->pm.power_state[state_index].num_clock_modes = mode_index; 2611 if (mode_index) { 2612 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index, 2613 non_clock_info); 2614 state_index++; 2615 } 2616 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 2617 } 2618 /* if multiple clock modes, mark the lowest as no display */ 2619 for (i = 0; i < state_index; i++) { 2620 if (rdev->pm.power_state[i].num_clock_modes > 1) 2621 rdev->pm.power_state[i].clock_info[0].flags |= 2622 RADEON_PM_MODE_NO_DISPLAY; 2623 } 2624 /* first mode is usually default */ 2625 if (rdev->pm.default_power_state_index == -1) { 2626 rdev->pm.power_state[0].type = 2627 POWER_STATE_TYPE_DEFAULT; 2628 rdev->pm.default_power_state_index = 0; 2629 rdev->pm.power_state[0].default_clock_mode = 2630 &rdev->pm.power_state[0].clock_info[0]; 2631 } 2632 return state_index; 2633 } 2634 2635 void radeon_atombios_get_power_modes(struct radeon_device *rdev) 2636 { 2637 struct radeon_mode_info *mode_info = &rdev->mode_info; 2638 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2639 u16 data_offset; 2640 u8 frev, crev; 2641 int state_index = 0; 2642 2643 rdev->pm.default_power_state_index = -1; 2644 2645 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 2646 &frev, &crev, &data_offset)) { 2647 switch (frev) { 2648 case 1: 2649 case 2: 2650 case 3: 2651 state_index = radeon_atombios_parse_power_table_1_3(rdev); 2652 break; 2653 case 4: 2654 case 5: 2655 state_index = radeon_atombios_parse_power_table_4_5(rdev); 2656 break; 2657 case 6: 2658 state_index = radeon_atombios_parse_power_table_6(rdev); 2659 break; 2660 default: 2661 break; 2662 } 2663 } 2664 2665 if (state_index == 0) { 2666 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL); 2667 if (rdev->pm.power_state) { 2668 rdev->pm.power_state[0].clock_info = 2669 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); 2670 if (rdev->pm.power_state[0].clock_info) { 2671 /* add the default mode */ 2672 rdev->pm.power_state[state_index].type = 2673 POWER_STATE_TYPE_DEFAULT; 2674 rdev->pm.power_state[state_index].num_clock_modes = 1; 2675 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; 2676 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; 2677 rdev->pm.power_state[state_index].default_clock_mode = 2678 &rdev->pm.power_state[state_index].clock_info[0]; 2679 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2680 rdev->pm.power_state[state_index].pcie_lanes = 16; 2681 rdev->pm.default_power_state_index = state_index; 2682 rdev->pm.power_state[state_index].flags = 0; 2683 state_index++; 2684 } 2685 } 2686 } 2687 2688 rdev->pm.num_power_states = state_index; 2689 2690 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2691 rdev->pm.current_clock_mode_index = 0; 2692 if (rdev->pm.default_power_state_index >= 0) 2693 rdev->pm.current_vddc = 2694 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; 2695 else 2696 rdev->pm.current_vddc = 0; 2697 } 2698 2699 union get_clock_dividers { 2700 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1; 2701 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2; 2702 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3; 2703 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4; 2704 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5; 2705 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in; 2706 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out; 2707 }; 2708 2709 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 2710 u8 clock_type, 2711 u32 clock, 2712 bool strobe_mode, 2713 struct atom_clock_dividers *dividers) 2714 { 2715 union get_clock_dividers args; 2716 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL); 2717 u8 frev, crev; 2718 2719 memset(&args, 0, sizeof(args)); 2720 memset(dividers, 0, sizeof(struct atom_clock_dividers)); 2721 2722 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2723 return -EINVAL; 2724 2725 switch (crev) { 2726 case 1: 2727 /* r4xx, r5xx */ 2728 args.v1.ucAction = clock_type; 2729 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */ 2730 2731 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2732 2733 dividers->post_div = args.v1.ucPostDiv; 2734 dividers->fb_div = args.v1.ucFbDiv; 2735 dividers->enable_post_div = true; 2736 break; 2737 case 2: 2738 case 3: 2739 case 5: 2740 /* r6xx, r7xx, evergreen, ni, si */ 2741 if (rdev->family <= CHIP_RV770) { 2742 args.v2.ucAction = clock_type; 2743 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */ 2744 2745 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2746 2747 dividers->post_div = args.v2.ucPostDiv; 2748 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv); 2749 dividers->ref_div = args.v2.ucAction; 2750 if (rdev->family == CHIP_RV770) { 2751 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ? 2752 true : false; 2753 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0; 2754 } else 2755 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false; 2756 } else { 2757 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) { 2758 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock); 2759 2760 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2761 2762 dividers->post_div = args.v3.ucPostDiv; 2763 dividers->enable_post_div = (args.v3.ucCntlFlag & 2764 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; 2765 dividers->enable_dithen = (args.v3.ucCntlFlag & 2766 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; 2767 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv); 2768 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac); 2769 dividers->ref_div = args.v3.ucRefDiv; 2770 dividers->vco_mode = (args.v3.ucCntlFlag & 2771 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; 2772 } else { 2773 /* for SI we use ComputeMemoryClockParam for memory plls */ 2774 if (rdev->family >= CHIP_TAHITI) 2775 return -EINVAL; 2776 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock); 2777 if (strobe_mode) 2778 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN; 2779 2780 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2781 2782 dividers->post_div = args.v5.ucPostDiv; 2783 dividers->enable_post_div = (args.v5.ucCntlFlag & 2784 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; 2785 dividers->enable_dithen = (args.v5.ucCntlFlag & 2786 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; 2787 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv); 2788 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac); 2789 dividers->ref_div = args.v5.ucRefDiv; 2790 dividers->vco_mode = (args.v5.ucCntlFlag & 2791 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; 2792 } 2793 } 2794 break; 2795 case 4: 2796 /* fusion */ 2797 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */ 2798 2799 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2800 2801 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; 2802 dividers->real_clock = le32_to_cpu(args.v4.ulClock); 2803 break; 2804 case 6: 2805 /* CI */ 2806 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */ 2807 args.v6_in.ulClock.ulComputeClockFlag = clock_type; 2808 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */ 2809 2810 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2811 2812 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv); 2813 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac); 2814 dividers->ref_div = args.v6_out.ucPllRefDiv; 2815 dividers->post_div = args.v6_out.ucPllPostDiv; 2816 dividers->flags = args.v6_out.ucPllCntlFlag; 2817 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock); 2818 dividers->post_divider = args.v6_out.ulClock.ucPostDiv; 2819 break; 2820 default: 2821 return -EINVAL; 2822 } 2823 return 0; 2824 } 2825 2826 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 2827 u32 clock, 2828 bool strobe_mode, 2829 struct atom_mpll_param *mpll_param) 2830 { 2831 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args; 2832 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam); 2833 u8 frev, crev; 2834 2835 memset(&args, 0, sizeof(args)); 2836 memset(mpll_param, 0, sizeof(struct atom_mpll_param)); 2837 2838 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2839 return -EINVAL; 2840 2841 switch (frev) { 2842 case 2: 2843 switch (crev) { 2844 case 1: 2845 /* SI */ 2846 args.ulClock = cpu_to_le32(clock); /* 10 khz */ 2847 args.ucInputFlag = 0; 2848 if (strobe_mode) 2849 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN; 2850 2851 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2852 2853 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac); 2854 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv); 2855 mpll_param->post_div = args.ucPostDiv; 2856 mpll_param->dll_speed = args.ucDllSpeed; 2857 mpll_param->bwcntl = args.ucBWCntl; 2858 mpll_param->vco_mode = 2859 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK) ? 1 : 0; 2860 mpll_param->yclk_sel = 2861 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0; 2862 mpll_param->qdr = 2863 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0; 2864 mpll_param->half_rate = 2865 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0; 2866 break; 2867 default: 2868 return -EINVAL; 2869 } 2870 break; 2871 default: 2872 return -EINVAL; 2873 } 2874 return 0; 2875 } 2876 2877 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) 2878 { 2879 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args; 2880 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating); 2881 2882 args.ucEnable = enable; 2883 2884 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2885 } 2886 2887 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev) 2888 { 2889 GET_ENGINE_CLOCK_PS_ALLOCATION args; 2890 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock); 2891 2892 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2893 return le32_to_cpu(args.ulReturnEngineClock); 2894 } 2895 2896 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev) 2897 { 2898 GET_MEMORY_CLOCK_PS_ALLOCATION args; 2899 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock); 2900 2901 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2902 return le32_to_cpu(args.ulReturnMemoryClock); 2903 } 2904 2905 void radeon_atom_set_engine_clock(struct radeon_device *rdev, 2906 uint32_t eng_clock) 2907 { 2908 SET_ENGINE_CLOCK_PS_ALLOCATION args; 2909 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); 2910 2911 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */ 2912 2913 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2914 } 2915 2916 void radeon_atom_set_memory_clock(struct radeon_device *rdev, 2917 uint32_t mem_clock) 2918 { 2919 SET_MEMORY_CLOCK_PS_ALLOCATION args; 2920 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); 2921 2922 if (rdev->flags & RADEON_IS_IGP) 2923 return; 2924 2925 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */ 2926 2927 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2928 } 2929 2930 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 2931 u32 eng_clock, u32 mem_clock) 2932 { 2933 SET_ENGINE_CLOCK_PS_ALLOCATION args; 2934 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 2935 u32 tmp; 2936 2937 memset(&args, 0, sizeof(args)); 2938 2939 tmp = eng_clock & SET_CLOCK_FREQ_MASK; 2940 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24); 2941 2942 args.ulTargetEngineClock = cpu_to_le32(tmp); 2943 if (mem_clock) 2944 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK); 2945 2946 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2947 } 2948 2949 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 2950 u32 mem_clock) 2951 { 2952 u32 args; 2953 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 2954 2955 args = cpu_to_le32(mem_clock); /* 10 khz */ 2956 2957 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2958 } 2959 2960 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 2961 u32 mem_clock) 2962 { 2963 SET_MEMORY_CLOCK_PS_ALLOCATION args; 2964 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 2965 u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24); 2966 2967 args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */ 2968 2969 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2970 } 2971 2972 union set_voltage { 2973 struct _SET_VOLTAGE_PS_ALLOCATION alloc; 2974 struct _SET_VOLTAGE_PARAMETERS v1; 2975 struct _SET_VOLTAGE_PARAMETERS_V2 v2; 2976 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3; 2977 }; 2978 2979 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type) 2980 { 2981 union set_voltage args; 2982 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 2983 u8 frev, crev, volt_index = voltage_level; 2984 2985 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2986 return; 2987 2988 /* 0xff01 is a flag rather then an actual voltage */ 2989 if (voltage_level == 0xff01) 2990 return; 2991 2992 switch (crev) { 2993 case 1: 2994 args.v1.ucVoltageType = voltage_type; 2995 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE; 2996 args.v1.ucVoltageIndex = volt_index; 2997 break; 2998 case 2: 2999 args.v2.ucVoltageType = voltage_type; 3000 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE; 3001 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 3002 break; 3003 case 3: 3004 args.v3.ucVoltageType = voltage_type; 3005 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE; 3006 args.v3.usVoltageLevel = cpu_to_le16(voltage_level); 3007 break; 3008 default: 3009 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3010 return; 3011 } 3012 3013 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3014 } 3015 3016 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 3017 u16 voltage_id, u16 *voltage) 3018 { 3019 union set_voltage args; 3020 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3021 u8 frev, crev; 3022 3023 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3024 return -EINVAL; 3025 3026 switch (crev) { 3027 case 1: 3028 return -EINVAL; 3029 case 2: 3030 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE; 3031 args.v2.ucVoltageMode = 0; 3032 args.v2.usVoltageLevel = 0; 3033 3034 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3035 3036 *voltage = le16_to_cpu(args.v2.usVoltageLevel); 3037 break; 3038 case 3: 3039 args.v3.ucVoltageType = voltage_type; 3040 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL; 3041 args.v3.usVoltageLevel = cpu_to_le16(voltage_id); 3042 3043 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3044 3045 *voltage = le16_to_cpu(args.v3.usVoltageLevel); 3046 break; 3047 default: 3048 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3049 return -EINVAL; 3050 } 3051 3052 return 0; 3053 } 3054 3055 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 3056 u16 *voltage, 3057 u16 leakage_idx) 3058 { 3059 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage); 3060 } 3061 3062 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 3063 u16 voltage_level, u8 voltage_type, 3064 u32 *gpio_value, u32 *gpio_mask) 3065 { 3066 union set_voltage args; 3067 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3068 u8 frev, crev; 3069 3070 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3071 return -EINVAL; 3072 3073 switch (crev) { 3074 case 1: 3075 return -EINVAL; 3076 case 2: 3077 args.v2.ucVoltageType = voltage_type; 3078 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK; 3079 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 3080 3081 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3082 3083 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2); 3084 3085 args.v2.ucVoltageType = voltage_type; 3086 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL; 3087 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 3088 3089 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3090 3091 *gpio_value = le32_to_cpu(*(u32 *)&args.v2); 3092 break; 3093 default: 3094 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3095 return -EINVAL; 3096 } 3097 3098 return 0; 3099 } 3100 3101 union voltage_object_info { 3102 struct _ATOM_VOLTAGE_OBJECT_INFO v1; 3103 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2; 3104 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3; 3105 }; 3106 3107 union voltage_object { 3108 struct _ATOM_VOLTAGE_OBJECT v1; 3109 struct _ATOM_VOLTAGE_OBJECT_V2 v2; 3110 union _ATOM_VOLTAGE_OBJECT_V3 v3; 3111 }; 3112 3113 static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1, 3114 u8 voltage_type) 3115 { 3116 u32 size = le16_to_cpu(v1->sHeader.usStructureSize); 3117 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]); 3118 u8 *start = (u8 *)v1; 3119 3120 while (offset < size) { 3121 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset); 3122 if (vo->ucVoltageType == voltage_type) 3123 return vo; 3124 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) + 3125 vo->asFormula.ucNumOfVoltageEntries; 3126 } 3127 return NULL; 3128 } 3129 3130 static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2, 3131 u8 voltage_type) 3132 { 3133 u32 size = le16_to_cpu(v2->sHeader.usStructureSize); 3134 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]); 3135 u8 *start = (u8*)v2; 3136 3137 while (offset < size) { 3138 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset); 3139 if (vo->ucVoltageType == voltage_type) 3140 return vo; 3141 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) + 3142 (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY)); 3143 } 3144 return NULL; 3145 } 3146 3147 static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3, 3148 u8 voltage_type, u8 voltage_mode) 3149 { 3150 u32 size = le16_to_cpu(v3->sHeader.usStructureSize); 3151 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]); 3152 u8 *start = (u8*)v3; 3153 3154 while (offset < size) { 3155 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset); 3156 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) && 3157 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode)) 3158 return vo; 3159 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize); 3160 } 3161 return NULL; 3162 } 3163 3164 bool 3165 radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 3166 u8 voltage_type, u8 voltage_mode) 3167 { 3168 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3169 u8 frev, crev; 3170 u16 data_offset, size; 3171 union voltage_object_info *voltage_info; 3172 union voltage_object *voltage_object = NULL; 3173 3174 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3175 &frev, &crev, &data_offset)) { 3176 voltage_info = (union voltage_object_info *) 3177 ((uint8_t*)rdev->mode_info.atom_context->bios + data_offset); 3178 3179 switch (frev) { 3180 case 1: 3181 case 2: 3182 switch (crev) { 3183 case 1: 3184 voltage_object = (union voltage_object *) 3185 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3186 if (voltage_object && 3187 (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO)) 3188 return true; 3189 break; 3190 case 2: 3191 voltage_object = (union voltage_object *) 3192 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3193 if (voltage_object && 3194 (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO)) 3195 return true; 3196 break; 3197 default: 3198 DRM_ERROR("unknown voltage object table\n"); 3199 return false; 3200 } 3201 break; 3202 case 3: 3203 switch (crev) { 3204 case 1: 3205 if (atom_lookup_voltage_object_v3(&voltage_info->v3, 3206 voltage_type, voltage_mode)) 3207 return true; 3208 break; 3209 default: 3210 DRM_ERROR("unknown voltage object table\n"); 3211 return false; 3212 } 3213 break; 3214 default: 3215 DRM_ERROR("unknown voltage object table\n"); 3216 return false; 3217 } 3218 3219 } 3220 return false; 3221 } 3222 3223 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 3224 u8 voltage_type, u16 *max_voltage) 3225 { 3226 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3227 u8 frev, crev; 3228 u16 data_offset, size; 3229 union voltage_object_info *voltage_info; 3230 union voltage_object *voltage_object = NULL; 3231 3232 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3233 &frev, &crev, &data_offset)) { 3234 voltage_info = (union voltage_object_info *) 3235 ((uint8_t*)rdev->mode_info.atom_context->bios + data_offset); 3236 3237 switch (crev) { 3238 case 1: 3239 voltage_object = (union voltage_object *) 3240 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3241 if (voltage_object) { 3242 ATOM_VOLTAGE_FORMULA *formula = 3243 &voltage_object->v1.asFormula; 3244 if (formula->ucFlag & 1) 3245 *max_voltage = 3246 le16_to_cpu(formula->usVoltageBaseLevel) + 3247 formula->ucNumOfVoltageEntries / 2 * 3248 le16_to_cpu(formula->usVoltageStep); 3249 else 3250 *max_voltage = 3251 le16_to_cpu(formula->usVoltageBaseLevel) + 3252 (formula->ucNumOfVoltageEntries - 1) * 3253 le16_to_cpu(formula->usVoltageStep); 3254 return 0; 3255 } 3256 break; 3257 case 2: 3258 voltage_object = (union voltage_object *) 3259 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3260 if (voltage_object) { 3261 ATOM_VOLTAGE_FORMULA_V2 *formula = 3262 &voltage_object->v2.asFormula; 3263 if (formula->ucNumOfVoltageEntries) { 3264 *max_voltage = 3265 le16_to_cpu(formula->asVIDAdjustEntries[ 3266 formula->ucNumOfVoltageEntries - 1 3267 ].usVoltageValue); 3268 return 0; 3269 } 3270 } 3271 break; 3272 default: 3273 DRM_ERROR("unknown voltage object table\n"); 3274 return -EINVAL; 3275 } 3276 3277 } 3278 return -EINVAL; 3279 } 3280 3281 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 3282 u8 voltage_type, u16 *min_voltage) 3283 { 3284 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3285 u8 frev, crev; 3286 u16 data_offset, size; 3287 union voltage_object_info *voltage_info; 3288 union voltage_object *voltage_object = NULL; 3289 3290 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3291 &frev, &crev, &data_offset)) { 3292 voltage_info = (union voltage_object_info *) 3293 ((uint8_t*)rdev->mode_info.atom_context->bios + data_offset); 3294 3295 switch (crev) { 3296 case 1: 3297 voltage_object = (union voltage_object *) 3298 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3299 if (voltage_object) { 3300 ATOM_VOLTAGE_FORMULA *formula = 3301 &voltage_object->v1.asFormula; 3302 *min_voltage = 3303 le16_to_cpu(formula->usVoltageBaseLevel); 3304 return 0; 3305 } 3306 break; 3307 case 2: 3308 voltage_object = (union voltage_object *) 3309 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3310 if (voltage_object) { 3311 ATOM_VOLTAGE_FORMULA_V2 *formula = 3312 &voltage_object->v2.asFormula; 3313 if (formula->ucNumOfVoltageEntries) { 3314 *min_voltage = 3315 le16_to_cpu(formula->asVIDAdjustEntries[ 3316 0 3317 ].usVoltageValue); 3318 return 0; 3319 } 3320 } 3321 break; 3322 default: 3323 DRM_ERROR("unknown voltage object table\n"); 3324 return -EINVAL; 3325 } 3326 3327 } 3328 return -EINVAL; 3329 } 3330 3331 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 3332 u8 voltage_type, u16 *voltage_step) 3333 { 3334 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3335 u8 frev, crev; 3336 u16 data_offset, size; 3337 union voltage_object_info *voltage_info; 3338 union voltage_object *voltage_object = NULL; 3339 3340 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3341 &frev, &crev, &data_offset)) { 3342 voltage_info = (union voltage_object_info *) 3343 ((uint8_t*)rdev->mode_info.atom_context->bios + data_offset); 3344 3345 switch (crev) { 3346 case 1: 3347 voltage_object = (union voltage_object *) 3348 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3349 if (voltage_object) { 3350 ATOM_VOLTAGE_FORMULA *formula = 3351 &voltage_object->v1.asFormula; 3352 if (formula->ucFlag & 1) 3353 *voltage_step = 3354 (le16_to_cpu(formula->usVoltageStep) + 1) / 2; 3355 else 3356 *voltage_step = 3357 le16_to_cpu(formula->usVoltageStep); 3358 return 0; 3359 } 3360 break; 3361 case 2: 3362 return -EINVAL; 3363 default: 3364 DRM_ERROR("unknown voltage object table\n"); 3365 return -EINVAL; 3366 } 3367 3368 } 3369 return -EINVAL; 3370 } 3371 3372 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 3373 u8 voltage_type, 3374 u16 nominal_voltage, 3375 u16 *true_voltage) 3376 { 3377 u16 min_voltage, max_voltage, voltage_step; 3378 3379 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage)) 3380 return -EINVAL; 3381 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage)) 3382 return -EINVAL; 3383 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step)) 3384 return -EINVAL; 3385 3386 if (nominal_voltage <= min_voltage) 3387 *true_voltage = min_voltage; 3388 else if (nominal_voltage >= max_voltage) 3389 *true_voltage = max_voltage; 3390 else 3391 *true_voltage = min_voltage + 3392 ((nominal_voltage - min_voltage) / voltage_step) * 3393 voltage_step; 3394 3395 return 0; 3396 } 3397 3398 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 3399 u8 voltage_type, u8 voltage_mode, 3400 struct atom_voltage_table *voltage_table) 3401 { 3402 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3403 u8 frev, crev; 3404 u16 data_offset, size; 3405 int i, ret; 3406 union voltage_object_info *voltage_info; 3407 union voltage_object *voltage_object = NULL; 3408 3409 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3410 &frev, &crev, &data_offset)) { 3411 voltage_info = (union voltage_object_info *) 3412 ((uint8_t*)rdev->mode_info.atom_context->bios + data_offset); 3413 3414 switch (frev) { 3415 case 1: 3416 case 2: 3417 switch (crev) { 3418 case 1: 3419 DRM_ERROR("old table version %d, %d\n", frev, crev); 3420 return -EINVAL; 3421 case 2: 3422 voltage_object = (union voltage_object *) 3423 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3424 if (voltage_object) { 3425 ATOM_VOLTAGE_FORMULA_V2 *formula = 3426 &voltage_object->v2.asFormula; 3427 if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES) 3428 return -EINVAL; 3429 for (i = 0; i < formula->ucNumOfVoltageEntries; i++) { 3430 voltage_table->entries[i].value = 3431 le16_to_cpu(formula->asVIDAdjustEntries[i].usVoltageValue); 3432 ret = radeon_atom_get_voltage_gpio_settings(rdev, 3433 voltage_table->entries[i].value, 3434 voltage_type, 3435 &voltage_table->entries[i].smio_low, 3436 &voltage_table->mask_low); 3437 if (ret) 3438 return ret; 3439 } 3440 voltage_table->count = formula->ucNumOfVoltageEntries; 3441 return 0; 3442 } 3443 break; 3444 default: 3445 DRM_ERROR("unknown voltage object table\n"); 3446 return -EINVAL; 3447 } 3448 break; 3449 case 3: 3450 switch (crev) { 3451 case 1: 3452 voltage_object = (union voltage_object *) 3453 atom_lookup_voltage_object_v3(&voltage_info->v3, 3454 voltage_type, voltage_mode); 3455 if (voltage_object) { 3456 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio = 3457 &voltage_object->v3.asGpioVoltageObj; 3458 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES) 3459 return -EINVAL; 3460 for (i = 0; i < gpio->ucGpioEntryNum; i++) { 3461 voltage_table->entries[i].value = 3462 le16_to_cpu(gpio->asVolGpioLut[i].usVoltageValue); 3463 voltage_table->entries[i].smio_low = 3464 le32_to_cpu(gpio->asVolGpioLut[i].ulVoltageId); 3465 } 3466 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal); 3467 voltage_table->count = gpio->ucGpioEntryNum; 3468 voltage_table->phase_delay = gpio->ucPhaseDelay; 3469 return 0; 3470 } 3471 break; 3472 default: 3473 DRM_ERROR("unknown voltage object table\n"); 3474 return -EINVAL; 3475 } 3476 break; 3477 default: 3478 DRM_ERROR("unknown voltage object table\n"); 3479 return -EINVAL; 3480 } 3481 } 3482 return -EINVAL; 3483 } 3484 3485 union vram_info { 3486 struct _ATOM_VRAM_INFO_V3 v1_3; 3487 struct _ATOM_VRAM_INFO_V4 v1_4; 3488 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1; 3489 }; 3490 3491 int radeon_atom_get_memory_info(struct radeon_device *rdev, 3492 u8 module_index, struct atom_memory_info *mem_info) 3493 { 3494 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 3495 u8 frev, crev, i; 3496 u16 data_offset, size; 3497 union vram_info *vram_info; 3498 3499 memset(mem_info, 0, sizeof(struct atom_memory_info)); 3500 3501 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3502 &frev, &crev, &data_offset)) { 3503 vram_info = (union vram_info *) 3504 ((uint8_t*)rdev->mode_info.atom_context->bios + data_offset); 3505 switch (frev) { 3506 case 1: 3507 switch (crev) { 3508 case 3: 3509 /* r6xx */ 3510 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) { 3511 ATOM_VRAM_MODULE_V3 *vram_module = 3512 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo; 3513 3514 for (i = 0; i < module_index; i++) { 3515 if (le16_to_cpu(vram_module->usSize) == 0) 3516 return -EINVAL; 3517 vram_module = (ATOM_VRAM_MODULE_V3 *) 3518 ((u8 *)vram_module + le16_to_cpu(vram_module->usSize)); 3519 } 3520 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf; 3521 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0; 3522 } else 3523 return -EINVAL; 3524 break; 3525 case 4: 3526 /* r7xx, evergreen */ 3527 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) { 3528 ATOM_VRAM_MODULE_V4 *vram_module = 3529 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo; 3530 3531 for (i = 0; i < module_index; i++) { 3532 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3533 return -EINVAL; 3534 vram_module = (ATOM_VRAM_MODULE_V4 *) 3535 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); 3536 } 3537 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf; 3538 mem_info->mem_type = vram_module->ucMemoryType & 0xf0; 3539 } else 3540 return -EINVAL; 3541 break; 3542 default: 3543 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3544 return -EINVAL; 3545 } 3546 break; 3547 case 2: 3548 switch (crev) { 3549 case 1: 3550 /* ni */ 3551 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { 3552 ATOM_VRAM_MODULE_V7 *vram_module = 3553 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo; 3554 3555 for (i = 0; i < module_index; i++) { 3556 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3557 return -EINVAL; 3558 vram_module = (ATOM_VRAM_MODULE_V7 *) 3559 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); 3560 } 3561 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf; 3562 mem_info->mem_type = vram_module->ucMemoryType & 0xf0; 3563 } else 3564 return -EINVAL; 3565 break; 3566 default: 3567 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3568 return -EINVAL; 3569 } 3570 break; 3571 default: 3572 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3573 return -EINVAL; 3574 } 3575 return 0; 3576 } 3577 return -EINVAL; 3578 } 3579 3580 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 3581 bool gddr5, u8 module_index, 3582 struct atom_memory_clock_range_table *mclk_range_table) 3583 { 3584 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 3585 u8 frev, crev, i; 3586 u16 data_offset, size; 3587 union vram_info *vram_info; 3588 u32 mem_timing_size = gddr5 ? 3589 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT); 3590 u8 *p; 3591 3592 memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table)); 3593 3594 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3595 &frev, &crev, &data_offset)) { 3596 vram_info = (union vram_info *) 3597 ((uint8_t*)rdev->mode_info.atom_context->bios + data_offset); 3598 switch (frev) { 3599 case 1: 3600 switch (crev) { 3601 case 3: 3602 DRM_ERROR("old table version %d, %d\n", frev, crev); 3603 return -EINVAL; 3604 case 4: 3605 /* r7xx, evergreen */ 3606 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) { 3607 ATOM_VRAM_MODULE_V4 *vram_module = 3608 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo; 3609 3610 for (i = 0; i < module_index; i++) { 3611 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3612 return -EINVAL; 3613 vram_module = (ATOM_VRAM_MODULE_V4 *) 3614 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); 3615 } 3616 mclk_range_table->num_entries = (u8) 3617 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) / 3618 mem_timing_size); 3619 p = (u8 *)&vram_module->asMemTiming[0]; 3620 for (i = 0; i < mclk_range_table->num_entries; i++) { 3621 ATOM_MEMORY_TIMING_FORMAT *format = (ATOM_MEMORY_TIMING_FORMAT *)p; 3622 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange); 3623 p += mem_timing_size; 3624 } 3625 } else 3626 return -EINVAL; 3627 break; 3628 default: 3629 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3630 return -EINVAL; 3631 } 3632 break; 3633 case 2: 3634 DRM_ERROR("new table version %d, %d\n", frev, crev); 3635 return -EINVAL; 3636 default: 3637 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3638 return -EINVAL; 3639 } 3640 return 0; 3641 } 3642 return -EINVAL; 3643 } 3644 3645 #define MEM_ID_MASK 0xff000000 3646 #define MEM_ID_SHIFT 24 3647 #define CLOCK_RANGE_MASK 0x00ffffff 3648 #define CLOCK_RANGE_SHIFT 0 3649 #define LOW_NIBBLE_MASK 0xf 3650 #define DATA_EQU_PREV 0 3651 #define DATA_FROM_TABLE 4 3652 3653 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 3654 u8 module_index, 3655 struct atom_mc_reg_table *reg_table) 3656 { 3657 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 3658 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0; 3659 u32 i = 0, j; 3660 u16 data_offset, size; 3661 union vram_info *vram_info; 3662 3663 memset(reg_table, 0, sizeof(struct atom_mc_reg_table)); 3664 3665 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3666 &frev, &crev, &data_offset)) { 3667 vram_info = (union vram_info *) 3668 ((uint8_t*)rdev->mode_info.atom_context->bios + data_offset); 3669 switch (frev) { 3670 case 1: 3671 DRM_ERROR("old table version %d, %d\n", frev, crev); 3672 return -EINVAL; 3673 case 2: 3674 switch (crev) { 3675 case 1: 3676 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { 3677 ATOM_INIT_REG_BLOCK *reg_block = 3678 (ATOM_INIT_REG_BLOCK *) 3679 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset)); 3680 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = 3681 (ATOM_MEMORY_SETTING_DATA_BLOCK *) 3682 ((u8 *)reg_block + (2 * sizeof(u16)) + 3683 le16_to_cpu(reg_block->usRegIndexTblSize)); 3684 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0]; 3685 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) / 3686 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1; 3687 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE) 3688 return -EINVAL; 3689 while (i < num_entries) { 3690 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER) 3691 break; 3692 reg_table->mc_reg_address[i].s1 = 3693 (u16)(le16_to_cpu(format->usRegIndex)); 3694 reg_table->mc_reg_address[i].pre_reg_data = 3695 (u8)(format->ucPreRegDataLength); 3696 i++; 3697 format = (ATOM_INIT_REG_INDEX_FORMAT *) 3698 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT)); 3699 } 3700 reg_table->last = i; 3701 while ((*(u32 *)reg_data != END_OF_REG_DATA_BLOCK) && 3702 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) { 3703 t_mem_id = (u8)((*(u32 *)reg_data & MEM_ID_MASK) >> MEM_ID_SHIFT); 3704 if (module_index == t_mem_id) { 3705 reg_table->mc_reg_table_entry[num_ranges].mclk_max = 3706 (u32)((*(u32 *)reg_data & CLOCK_RANGE_MASK) >> CLOCK_RANGE_SHIFT); 3707 for (i = 0, j = 1; i < reg_table->last; i++) { 3708 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { 3709 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 3710 (u32)*((u32 *)reg_data + j); 3711 j++; 3712 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { 3713 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 3714 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1]; 3715 } 3716 } 3717 num_ranges++; 3718 } 3719 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) 3720 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); 3721 } 3722 if (*(u32 *)reg_data != END_OF_REG_DATA_BLOCK) 3723 return -EINVAL; 3724 reg_table->num_entries = num_ranges; 3725 } else 3726 return -EINVAL; 3727 break; 3728 default: 3729 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3730 return -EINVAL; 3731 } 3732 break; 3733 default: 3734 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3735 return -EINVAL; 3736 } 3737 return 0; 3738 } 3739 return -EINVAL; 3740 } 3741 3742 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) 3743 { 3744 struct radeon_device *rdev = dev->dev_private; 3745 uint32_t bios_2_scratch, bios_6_scratch; 3746 3747 if (rdev->family >= CHIP_R600) { 3748 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 3749 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 3750 } else { 3751 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 3752 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3753 } 3754 3755 /* let the bios control the backlight */ 3756 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; 3757 3758 /* tell the bios not to handle mode switching */ 3759 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH; 3760 3761 if (rdev->family >= CHIP_R600) { 3762 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 3763 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 3764 } else { 3765 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 3766 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3767 } 3768 3769 } 3770 3771 void radeon_save_bios_scratch_regs(struct radeon_device *rdev) 3772 { 3773 uint32_t scratch_reg; 3774 int i; 3775 3776 if (rdev->family >= CHIP_R600) 3777 scratch_reg = R600_BIOS_0_SCRATCH; 3778 else 3779 scratch_reg = RADEON_BIOS_0_SCRATCH; 3780 3781 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) 3782 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4)); 3783 } 3784 3785 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev) 3786 { 3787 uint32_t scratch_reg; 3788 int i; 3789 3790 if (rdev->family >= CHIP_R600) 3791 scratch_reg = R600_BIOS_0_SCRATCH; 3792 else 3793 scratch_reg = RADEON_BIOS_0_SCRATCH; 3794 3795 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) 3796 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]); 3797 } 3798 3799 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock) 3800 { 3801 struct drm_device *dev = encoder->dev; 3802 struct radeon_device *rdev = dev->dev_private; 3803 uint32_t bios_6_scratch; 3804 3805 if (rdev->family >= CHIP_R600) 3806 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 3807 else 3808 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3809 3810 if (lock) { 3811 bios_6_scratch |= ATOM_S6_CRITICAL_STATE; 3812 bios_6_scratch &= ~ATOM_S6_ACC_MODE; 3813 } else { 3814 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; 3815 bios_6_scratch |= ATOM_S6_ACC_MODE; 3816 } 3817 3818 if (rdev->family >= CHIP_R600) 3819 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 3820 else 3821 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3822 } 3823 3824 /* at some point we may want to break this out into individual functions */ 3825 void 3826 radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 3827 struct drm_encoder *encoder, 3828 bool connected) 3829 { 3830 struct drm_device *dev = connector->dev; 3831 struct radeon_device *rdev = dev->dev_private; 3832 struct radeon_connector *radeon_connector = 3833 to_radeon_connector(connector); 3834 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3835 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch; 3836 3837 if (rdev->family >= CHIP_R600) { 3838 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 3839 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); 3840 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 3841 } else { 3842 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 3843 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); 3844 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3845 } 3846 3847 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 3848 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 3849 if (connected) { 3850 DRM_DEBUG_KMS("TV1 connected\n"); 3851 bios_3_scratch |= ATOM_S3_TV1_ACTIVE; 3852 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1; 3853 } else { 3854 DRM_DEBUG_KMS("TV1 disconnected\n"); 3855 bios_0_scratch &= ~ATOM_S0_TV1_MASK; 3856 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE; 3857 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1; 3858 } 3859 } 3860 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) && 3861 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) { 3862 if (connected) { 3863 DRM_DEBUG_KMS("CV connected\n"); 3864 bios_3_scratch |= ATOM_S3_CV_ACTIVE; 3865 bios_6_scratch |= ATOM_S6_ACC_REQ_CV; 3866 } else { 3867 DRM_DEBUG_KMS("CV disconnected\n"); 3868 bios_0_scratch &= ~ATOM_S0_CV_MASK; 3869 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE; 3870 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV; 3871 } 3872 } 3873 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 3874 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 3875 if (connected) { 3876 DRM_DEBUG_KMS("LCD1 connected\n"); 3877 bios_0_scratch |= ATOM_S0_LCD1; 3878 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE; 3879 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1; 3880 } else { 3881 DRM_DEBUG_KMS("LCD1 disconnected\n"); 3882 bios_0_scratch &= ~ATOM_S0_LCD1; 3883 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE; 3884 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1; 3885 } 3886 } 3887 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 3888 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 3889 if (connected) { 3890 DRM_DEBUG_KMS("CRT1 connected\n"); 3891 bios_0_scratch |= ATOM_S0_CRT1_COLOR; 3892 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE; 3893 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1; 3894 } else { 3895 DRM_DEBUG_KMS("CRT1 disconnected\n"); 3896 bios_0_scratch &= ~ATOM_S0_CRT1_MASK; 3897 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE; 3898 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1; 3899 } 3900 } 3901 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 3902 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 3903 if (connected) { 3904 DRM_DEBUG_KMS("CRT2 connected\n"); 3905 bios_0_scratch |= ATOM_S0_CRT2_COLOR; 3906 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE; 3907 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2; 3908 } else { 3909 DRM_DEBUG_KMS("CRT2 disconnected\n"); 3910 bios_0_scratch &= ~ATOM_S0_CRT2_MASK; 3911 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE; 3912 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2; 3913 } 3914 } 3915 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 3916 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 3917 if (connected) { 3918 DRM_DEBUG_KMS("DFP1 connected\n"); 3919 bios_0_scratch |= ATOM_S0_DFP1; 3920 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE; 3921 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1; 3922 } else { 3923 DRM_DEBUG_KMS("DFP1 disconnected\n"); 3924 bios_0_scratch &= ~ATOM_S0_DFP1; 3925 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE; 3926 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1; 3927 } 3928 } 3929 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 3930 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 3931 if (connected) { 3932 DRM_DEBUG_KMS("DFP2 connected\n"); 3933 bios_0_scratch |= ATOM_S0_DFP2; 3934 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE; 3935 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2; 3936 } else { 3937 DRM_DEBUG_KMS("DFP2 disconnected\n"); 3938 bios_0_scratch &= ~ATOM_S0_DFP2; 3939 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE; 3940 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2; 3941 } 3942 } 3943 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) && 3944 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) { 3945 if (connected) { 3946 DRM_DEBUG_KMS("DFP3 connected\n"); 3947 bios_0_scratch |= ATOM_S0_DFP3; 3948 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE; 3949 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3; 3950 } else { 3951 DRM_DEBUG_KMS("DFP3 disconnected\n"); 3952 bios_0_scratch &= ~ATOM_S0_DFP3; 3953 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE; 3954 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3; 3955 } 3956 } 3957 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) && 3958 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) { 3959 if (connected) { 3960 DRM_DEBUG_KMS("DFP4 connected\n"); 3961 bios_0_scratch |= ATOM_S0_DFP4; 3962 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE; 3963 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4; 3964 } else { 3965 DRM_DEBUG_KMS("DFP4 disconnected\n"); 3966 bios_0_scratch &= ~ATOM_S0_DFP4; 3967 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE; 3968 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4; 3969 } 3970 } 3971 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) && 3972 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) { 3973 if (connected) { 3974 DRM_DEBUG_KMS("DFP5 connected\n"); 3975 bios_0_scratch |= ATOM_S0_DFP5; 3976 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE; 3977 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5; 3978 } else { 3979 DRM_DEBUG_KMS("DFP5 disconnected\n"); 3980 bios_0_scratch &= ~ATOM_S0_DFP5; 3981 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE; 3982 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5; 3983 } 3984 } 3985 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) && 3986 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) { 3987 if (connected) { 3988 DRM_DEBUG_KMS("DFP6 connected\n"); 3989 bios_0_scratch |= ATOM_S0_DFP6; 3990 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE; 3991 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6; 3992 } else { 3993 DRM_DEBUG_KMS("DFP6 disconnected\n"); 3994 bios_0_scratch &= ~ATOM_S0_DFP6; 3995 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE; 3996 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6; 3997 } 3998 } 3999 4000 if (rdev->family >= CHIP_R600) { 4001 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch); 4002 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); 4003 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 4004 } else { 4005 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); 4006 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); 4007 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 4008 } 4009 } 4010 4011 void 4012 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) 4013 { 4014 struct drm_device *dev = encoder->dev; 4015 struct radeon_device *rdev = dev->dev_private; 4016 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 4017 uint32_t bios_3_scratch; 4018 4019 if (ASIC_IS_DCE4(rdev)) 4020 return; 4021 4022 if (rdev->family >= CHIP_R600) 4023 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); 4024 else 4025 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); 4026 4027 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 4028 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE; 4029 bios_3_scratch |= (crtc << 18); 4030 } 4031 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { 4032 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE; 4033 bios_3_scratch |= (crtc << 24); 4034 } 4035 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 4036 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE; 4037 bios_3_scratch |= (crtc << 16); 4038 } 4039 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 4040 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE; 4041 bios_3_scratch |= (crtc << 20); 4042 } 4043 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 4044 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE; 4045 bios_3_scratch |= (crtc << 17); 4046 } 4047 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 4048 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE; 4049 bios_3_scratch |= (crtc << 19); 4050 } 4051 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 4052 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE; 4053 bios_3_scratch |= (crtc << 23); 4054 } 4055 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { 4056 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE; 4057 bios_3_scratch |= (crtc << 25); 4058 } 4059 4060 if (rdev->family >= CHIP_R600) 4061 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); 4062 else 4063 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); 4064 } 4065 4066 void 4067 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) 4068 { 4069 struct drm_device *dev = encoder->dev; 4070 struct radeon_device *rdev = dev->dev_private; 4071 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 4072 uint32_t bios_2_scratch; 4073 4074 if (ASIC_IS_DCE4(rdev)) 4075 return; 4076 4077 if (rdev->family >= CHIP_R600) 4078 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 4079 else 4080 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 4081 4082 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 4083 if (on) 4084 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE; 4085 else 4086 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE; 4087 } 4088 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { 4089 if (on) 4090 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE; 4091 else 4092 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE; 4093 } 4094 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 4095 if (on) 4096 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE; 4097 else 4098 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE; 4099 } 4100 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 4101 if (on) 4102 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE; 4103 else 4104 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE; 4105 } 4106 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 4107 if (on) 4108 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE; 4109 else 4110 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE; 4111 } 4112 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 4113 if (on) 4114 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE; 4115 else 4116 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE; 4117 } 4118 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 4119 if (on) 4120 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE; 4121 else 4122 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE; 4123 } 4124 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { 4125 if (on) 4126 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE; 4127 else 4128 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE; 4129 } 4130 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) { 4131 if (on) 4132 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE; 4133 else 4134 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE; 4135 } 4136 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) { 4137 if (on) 4138 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE; 4139 else 4140 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE; 4141 } 4142 4143 if (rdev->family >= CHIP_R600) 4144 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 4145 else 4146 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 4147 } 4148