1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * 28 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_bios.c 255572 2013-09-14 17:22:34Z dumbbell $ 29 */ 30 31 #include <drm/drmP.h> 32 #include "radeon_reg.h" 33 #include "radeon.h" 34 #include "atom.h" 35 36 #include <linux/slab.h> 37 /* 38 * BIOS. 39 */ 40 41 /* If you boot an IGP board with a discrete card as the primary, 42 * the IGP rom is not accessible via the rom bar as the IGP rom is 43 * part of the system bios. On boot, the system bios puts a 44 * copy of the igp rom at the start of vram if a discrete card is 45 * present. 46 */ 47 static bool igp_read_bios_from_vram(struct radeon_device *rdev) 48 { 49 uint8_t __iomem *bios; 50 resource_size_t vram_base; 51 resource_size_t size = 256 * 1024; /* ??? */ 52 53 if (!(rdev->flags & RADEON_IS_IGP)) 54 if (!radeon_card_posted(rdev)) 55 return false; 56 57 rdev->bios = NULL; 58 vram_base = pci_resource_start(rdev->pdev, 0); 59 bios = ioremap(vram_base, size); 60 if (!bios) { 61 return false; 62 } 63 64 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 65 iounmap(bios); 66 return false; 67 } 68 rdev->bios = kmalloc(size, M_DRM, M_WAITOK); 69 if (rdev->bios == NULL) { 70 iounmap(bios); 71 return false; 72 } 73 memcpy_fromio(rdev->bios, bios, size); 74 iounmap(bios); 75 return true; 76 } 77 78 static bool radeon_read_bios(struct radeon_device *rdev) 79 { 80 device_t vga_dev; 81 uint8_t __iomem *bios; 82 size_t size; 83 84 DRM_INFO("%s: ===> Try PCI Expansion ROM...\n", __func__); 85 86 vga_dev = device_get_parent(rdev->dev); 87 rdev->bios = NULL; 88 /* XXX: some cards may return 0 for rom size? ddx has a workaround */ 89 bios = vga_pci_map_bios(vga_dev, &size); 90 if (!bios) { 91 return false; 92 } 93 DRM_INFO("%s: Map address: %p (%zu bytes)\n", __func__, bios, size); 94 95 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 96 if (size == 0) { 97 DRM_INFO("%s: Incorrect BIOS size\n", __func__); 98 } else { 99 DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n", 100 __func__, bios[0], bios[1]); 101 } 102 vga_pci_unmap_bios(vga_dev, bios); 103 return false; 104 } 105 rdev->bios = kmalloc(size, M_DRM, M_WAITOK); 106 memcpy(rdev->bios, bios, size); 107 vga_pci_unmap_bios(vga_dev, bios); 108 return true; 109 } 110 111 static bool radeon_read_platform_bios(struct radeon_device *rdev) 112 { 113 uint8_t __iomem *bios; 114 size_t size; 115 116 rdev->bios = NULL; 117 118 #if 0 119 // XXX: FIXME 120 bios = pci_platform_rom(rdev->pdev, &size); 121 #else 122 size = 0; 123 bios = NULL; 124 #endif 125 if (!bios) { 126 return false; 127 } 128 129 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 130 return false; 131 } 132 rdev->bios = kmalloc(size, M_DRM, M_WAITOK); 133 if (rdev->bios == NULL) { 134 return false; 135 } 136 memcpy(rdev->bios, bios, size); 137 return true; 138 } 139 140 /* ATRM is used to get the BIOS on the discrete cards in 141 * dual-gpu systems. 142 */ 143 /* retrieve the ROM in 4k blocks */ 144 #define ATRM_BIOS_PAGE 4096 145 /** 146 * radeon_atrm_call - fetch a chunk of the vbios 147 * 148 * @atrm_handle: acpi ATRM handle 149 * @bios: vbios image pointer 150 * @offset: offset of vbios image data to fetch 151 * @len: length of vbios image data to fetch 152 * 153 * Executes ATRM to fetch a chunk of the discrete 154 * vbios image on PX systems (all asics). 155 * Returns the length of the buffer fetched. 156 */ 157 static int radeon_atrm_call(ACPI_HANDLE atrm_handle, uint8_t *bios, 158 int offset, int len) 159 { 160 ACPI_STATUS status; 161 ACPI_OBJECT atrm_arg_elements[2], *obj; 162 ACPI_OBJECT_LIST atrm_arg; 163 ACPI_BUFFER buffer = { ACPI_ALLOCATE_BUFFER, NULL}; 164 165 atrm_arg.Count = 2; 166 atrm_arg.Pointer = &atrm_arg_elements[0]; 167 168 atrm_arg_elements[0].Type = ACPI_TYPE_INTEGER; 169 atrm_arg_elements[0].Integer.Value = offset; 170 171 atrm_arg_elements[1].Type = ACPI_TYPE_INTEGER; 172 atrm_arg_elements[1].Integer.Value = len; 173 174 status = AcpiEvaluateObject(atrm_handle, NULL, &atrm_arg, &buffer); 175 if (ACPI_FAILURE(status)) { 176 printk("failed to evaluate ATRM got %s\n", AcpiFormatException(status)); 177 return -ENODEV; 178 } 179 180 obj = (ACPI_OBJECT *)buffer.Pointer; 181 memcpy(bios+offset, obj->Buffer.Pointer, obj->Buffer.Length); 182 len = obj->Buffer.Length; 183 AcpiOsFree(buffer.Pointer); 184 return len; 185 } 186 187 static bool radeon_atrm_get_bios(struct radeon_device *rdev) 188 { 189 int ret; 190 int size = 256 * 1024; 191 int i; 192 device_t dev; 193 ACPI_HANDLE dhandle, atrm_handle; 194 ACPI_STATUS status; 195 bool found = false; 196 197 DRM_INFO("%s: ===> Try ATRM...\n", __func__); 198 199 /* ATRM is for the discrete card only */ 200 if (rdev->flags & RADEON_IS_IGP) { 201 DRM_INFO("%s: IGP card detected, skipping this method...\n", 202 __func__); 203 return false; 204 } 205 206 #ifdef DUMBBELL_WIP 207 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 208 #endif /* DUMBBELL_WIP */ 209 if ((dev = pci_find_class(PCIC_DISPLAY, PCIS_DISPLAY_VGA)) != NULL) { 210 DRM_INFO("%s: pci_find_class() found: %d:%d:%d:%d, vendor=%04x, device=%04x\n", 211 __func__, 212 pci_get_domain(dev), 213 pci_get_bus(dev), 214 pci_get_slot(dev), 215 pci_get_function(dev), 216 pci_get_vendor(dev), 217 pci_get_device(dev)); 218 DRM_INFO("%s: Get ACPI device handle\n", __func__); 219 dhandle = acpi_get_handle(dev); 220 #ifdef DUMBBELL_WIP 221 if (!dhandle) 222 continue; 223 #endif /* DUMBBELL_WIP */ 224 if (!dhandle) 225 return false; 226 227 DRM_INFO("%s: Get ACPI handle for \"ATRM\"\n", __func__); 228 status = AcpiGetHandle(dhandle, "ATRM", &atrm_handle); 229 if (!ACPI_FAILURE(status)) { 230 found = true; 231 #ifdef DUMBBELL_WIP 232 break; 233 #endif /* DUMBBELL_WIP */ 234 } else { 235 DRM_INFO("%s: Failed to get \"ATRM\" handle: %s\n", 236 __func__, AcpiFormatException(status)); 237 } 238 } 239 240 if (!found) 241 return false; 242 243 rdev->bios = kmalloc(size, M_DRM, M_WAITOK); 244 if (!rdev->bios) { 245 DRM_ERROR("Unable to allocate bios\n"); 246 return false; 247 } 248 249 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { 250 DRM_INFO("%s: Call radeon_atrm_call()\n", __func__); 251 ret = radeon_atrm_call(atrm_handle, 252 rdev->bios, 253 (i * ATRM_BIOS_PAGE), 254 ATRM_BIOS_PAGE); 255 if (ret < ATRM_BIOS_PAGE) 256 break; 257 } 258 259 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 260 if (i == 0) { 261 DRM_INFO("%s: Incorrect BIOS size\n", __func__); 262 } else { 263 DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n", 264 __func__, rdev->bios[0], rdev->bios[1]); 265 } 266 kfree(rdev->bios); 267 return false; 268 } 269 return true; 270 } 271 272 static bool ni_read_disabled_bios(struct radeon_device *rdev) 273 { 274 u32 bus_cntl; 275 u32 d1vga_control; 276 u32 d2vga_control; 277 u32 vga_render_control; 278 u32 rom_cntl; 279 bool r; 280 281 DRM_INFO("%s: ===> Try disabled BIOS (ni)...\n", __func__); 282 283 bus_cntl = RREG32(R600_BUS_CNTL); 284 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 285 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 286 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 287 rom_cntl = RREG32(R600_ROM_CNTL); 288 289 /* enable the rom */ 290 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 291 if (!ASIC_IS_NODCE(rdev)) { 292 /* Disable VGA mode */ 293 WREG32(AVIVO_D1VGA_CONTROL, 294 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 295 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 296 WREG32(AVIVO_D2VGA_CONTROL, 297 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 298 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 299 WREG32(AVIVO_VGA_RENDER_CONTROL, 300 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 301 } 302 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 303 304 r = radeon_read_bios(rdev); 305 306 /* restore regs */ 307 WREG32(R600_BUS_CNTL, bus_cntl); 308 if (!ASIC_IS_NODCE(rdev)) { 309 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 310 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 311 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 312 } 313 WREG32(R600_ROM_CNTL, rom_cntl); 314 return r; 315 } 316 317 static bool r700_read_disabled_bios(struct radeon_device *rdev) 318 { 319 uint32_t viph_control; 320 uint32_t bus_cntl; 321 uint32_t d1vga_control; 322 uint32_t d2vga_control; 323 uint32_t vga_render_control; 324 uint32_t rom_cntl; 325 uint32_t cg_spll_func_cntl = 0; 326 uint32_t cg_spll_status; 327 bool r; 328 329 DRM_INFO("%s: ===> Try disabled BIOS (r700)...\n", __func__); 330 331 viph_control = RREG32(RADEON_VIPH_CONTROL); 332 bus_cntl = RREG32(R600_BUS_CNTL); 333 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 334 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 335 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 336 rom_cntl = RREG32(R600_ROM_CNTL); 337 338 /* disable VIP */ 339 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 340 /* enable the rom */ 341 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 342 /* Disable VGA mode */ 343 WREG32(AVIVO_D1VGA_CONTROL, 344 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 345 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 346 WREG32(AVIVO_D2VGA_CONTROL, 347 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 348 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 349 WREG32(AVIVO_VGA_RENDER_CONTROL, 350 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 351 352 if (rdev->family == CHIP_RV730) { 353 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); 354 355 /* enable bypass mode */ 356 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | 357 R600_SPLL_BYPASS_EN)); 358 359 /* wait for SPLL_CHG_STATUS to change to 1 */ 360 cg_spll_status = 0; 361 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 362 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 363 364 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); 365 } else 366 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 367 368 r = radeon_read_bios(rdev); 369 370 /* restore regs */ 371 if (rdev->family == CHIP_RV730) { 372 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); 373 374 /* wait for SPLL_CHG_STATUS to change to 1 */ 375 cg_spll_status = 0; 376 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 377 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 378 } 379 WREG32(RADEON_VIPH_CONTROL, viph_control); 380 WREG32(R600_BUS_CNTL, bus_cntl); 381 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 382 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 383 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 384 WREG32(R600_ROM_CNTL, rom_cntl); 385 return r; 386 } 387 388 static bool r600_read_disabled_bios(struct radeon_device *rdev) 389 { 390 uint32_t viph_control; 391 uint32_t bus_cntl; 392 uint32_t d1vga_control; 393 uint32_t d2vga_control; 394 uint32_t vga_render_control; 395 uint32_t rom_cntl; 396 uint32_t general_pwrmgt; 397 uint32_t low_vid_lower_gpio_cntl; 398 uint32_t medium_vid_lower_gpio_cntl; 399 uint32_t high_vid_lower_gpio_cntl; 400 uint32_t ctxsw_vid_lower_gpio_cntl; 401 uint32_t lower_gpio_enable; 402 bool r; 403 404 DRM_INFO("%s: ===> Try disabled BIOS (r600)...\n", __func__); 405 406 viph_control = RREG32(RADEON_VIPH_CONTROL); 407 bus_cntl = RREG32(R600_BUS_CNTL); 408 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 409 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 410 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 411 rom_cntl = RREG32(R600_ROM_CNTL); 412 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); 413 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); 414 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); 415 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); 416 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); 417 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); 418 419 /* disable VIP */ 420 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 421 /* enable the rom */ 422 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 423 /* Disable VGA mode */ 424 WREG32(AVIVO_D1VGA_CONTROL, 425 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 426 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 427 WREG32(AVIVO_D2VGA_CONTROL, 428 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 429 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 430 WREG32(AVIVO_VGA_RENDER_CONTROL, 431 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 432 433 WREG32(R600_ROM_CNTL, 434 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | 435 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | 436 R600_SCK_OVERWRITE)); 437 438 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 439 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, 440 (low_vid_lower_gpio_cntl & ~0x400)); 441 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, 442 (medium_vid_lower_gpio_cntl & ~0x400)); 443 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, 444 (high_vid_lower_gpio_cntl & ~0x400)); 445 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, 446 (ctxsw_vid_lower_gpio_cntl & ~0x400)); 447 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); 448 449 r = radeon_read_bios(rdev); 450 451 /* restore regs */ 452 WREG32(RADEON_VIPH_CONTROL, viph_control); 453 WREG32(R600_BUS_CNTL, bus_cntl); 454 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 455 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 456 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 457 WREG32(R600_ROM_CNTL, rom_cntl); 458 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); 459 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); 460 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); 461 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); 462 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); 463 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 464 return r; 465 } 466 467 static bool avivo_read_disabled_bios(struct radeon_device *rdev) 468 { 469 uint32_t seprom_cntl1; 470 uint32_t viph_control; 471 uint32_t bus_cntl; 472 uint32_t d1vga_control; 473 uint32_t d2vga_control; 474 uint32_t vga_render_control; 475 uint32_t gpiopad_a; 476 uint32_t gpiopad_en; 477 uint32_t gpiopad_mask; 478 bool r; 479 480 DRM_INFO("%s: ===> Try disabled BIOS (avivo)...\n", __func__); 481 482 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 483 viph_control = RREG32(RADEON_VIPH_CONTROL); 484 bus_cntl = RREG32(RV370_BUS_CNTL); 485 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 486 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 487 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 488 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 489 gpiopad_en = RREG32(RADEON_GPIOPAD_EN); 490 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); 491 492 WREG32(RADEON_SEPROM_CNTL1, 493 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 494 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 495 WREG32(RADEON_GPIOPAD_A, 0); 496 WREG32(RADEON_GPIOPAD_EN, 0); 497 WREG32(RADEON_GPIOPAD_MASK, 0); 498 499 /* disable VIP */ 500 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 501 502 /* enable the rom */ 503 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 504 505 /* Disable VGA mode */ 506 WREG32(AVIVO_D1VGA_CONTROL, 507 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 508 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 509 WREG32(AVIVO_D2VGA_CONTROL, 510 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 511 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 512 WREG32(AVIVO_VGA_RENDER_CONTROL, 513 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 514 515 r = radeon_read_bios(rdev); 516 517 /* restore regs */ 518 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 519 WREG32(RADEON_VIPH_CONTROL, viph_control); 520 WREG32(RV370_BUS_CNTL, bus_cntl); 521 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 522 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 523 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 524 WREG32(RADEON_GPIOPAD_A, gpiopad_a); 525 WREG32(RADEON_GPIOPAD_EN, gpiopad_en); 526 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); 527 return r; 528 } 529 530 static bool legacy_read_disabled_bios(struct radeon_device *rdev) 531 { 532 uint32_t seprom_cntl1; 533 uint32_t viph_control; 534 uint32_t bus_cntl; 535 uint32_t crtc_gen_cntl; 536 uint32_t crtc2_gen_cntl; 537 uint32_t crtc_ext_cntl; 538 uint32_t fp2_gen_cntl; 539 bool r; 540 541 DRM_INFO("%s: ===> Try disabled BIOS (legacy)...\n", __func__); 542 543 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 544 viph_control = RREG32(RADEON_VIPH_CONTROL); 545 if (rdev->flags & RADEON_IS_PCIE) 546 bus_cntl = RREG32(RV370_BUS_CNTL); 547 else 548 bus_cntl = RREG32(RADEON_BUS_CNTL); 549 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 550 crtc2_gen_cntl = 0; 551 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 552 fp2_gen_cntl = 0; 553 554 #define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 555 556 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 557 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 558 } 559 560 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 561 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 562 } 563 564 WREG32(RADEON_SEPROM_CNTL1, 565 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 566 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 567 568 /* disable VIP */ 569 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 570 571 /* enable the rom */ 572 if (rdev->flags & RADEON_IS_PCIE) 573 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 574 else 575 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 576 577 /* Turn off mem requests and CRTC for both controllers */ 578 WREG32(RADEON_CRTC_GEN_CNTL, 579 ((crtc_gen_cntl & ~RADEON_CRTC_EN) | 580 (RADEON_CRTC_DISP_REQ_EN_B | 581 RADEON_CRTC_EXT_DISP_EN))); 582 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 583 WREG32(RADEON_CRTC2_GEN_CNTL, 584 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | 585 RADEON_CRTC2_DISP_REQ_EN_B)); 586 } 587 /* Turn off CRTC */ 588 WREG32(RADEON_CRTC_EXT_CNTL, 589 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | 590 (RADEON_CRTC_SYNC_TRISTAT | 591 RADEON_CRTC_DISPLAY_DIS))); 592 593 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 594 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); 595 } 596 597 r = radeon_read_bios(rdev); 598 599 /* restore regs */ 600 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 601 WREG32(RADEON_VIPH_CONTROL, viph_control); 602 if (rdev->flags & RADEON_IS_PCIE) 603 WREG32(RV370_BUS_CNTL, bus_cntl); 604 else 605 WREG32(RADEON_BUS_CNTL, bus_cntl); 606 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 607 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 608 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 609 } 610 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 611 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 612 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 613 } 614 return r; 615 } 616 617 static bool radeon_read_disabled_bios(struct radeon_device *rdev) 618 { 619 if (rdev->flags & RADEON_IS_IGP) 620 return igp_read_bios_from_vram(rdev); 621 else if (rdev->family >= CHIP_BARTS) 622 return ni_read_disabled_bios(rdev); 623 else if (rdev->family >= CHIP_RV770) 624 return r700_read_disabled_bios(rdev); 625 else if (rdev->family >= CHIP_R600) 626 return r600_read_disabled_bios(rdev); 627 else if (rdev->family >= CHIP_RS600) 628 return avivo_read_disabled_bios(rdev); 629 else 630 return legacy_read_disabled_bios(rdev); 631 } 632 633 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 634 { 635 bool ret = false; 636 ACPI_TABLE_HEADER *hdr; 637 ACPI_SIZE tbl_size; 638 UEFI_ACPI_VFCT *vfct; 639 GOP_VBIOS_CONTENT *vbios; 640 VFCT_IMAGE_HEADER *vhdr; 641 ACPI_STATUS status; 642 643 DRM_INFO("%s: ===> Try VFCT...\n", __func__); 644 645 DRM_INFO("%s: Get \"VFCT\" ACPI table\n", __func__); 646 status = AcpiGetTable("VFCT", 1, &hdr); 647 if (!ACPI_SUCCESS(status)) { 648 DRM_INFO("%s: Failed to get \"VFCT\" table: %s\n", 649 __func__, AcpiFormatException(status)); 650 return false; 651 } 652 tbl_size = hdr->Length; 653 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { 654 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); 655 goto out_unmap; 656 } 657 658 vfct = (UEFI_ACPI_VFCT *)hdr; 659 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) { 660 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); 661 goto out_unmap; 662 } 663 664 vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset); 665 vhdr = &vbios->VbiosHeader; 666 DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n", 667 vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction, 668 vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength); 669 670 if (vhdr->PCIBus != rdev->pdev->bus->number || 671 vhdr->PCIDevice != rdev->ddev->pci_slot || 672 vhdr->PCIFunction != rdev->ddev->pci_func || 673 vhdr->VendorID != rdev->pdev->vendor || 674 vhdr->DeviceID != rdev->pdev->device) { 675 DRM_INFO("ACPI VFCT table is not for this card\n"); 676 goto out_unmap; 677 } 678 679 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) { 680 DRM_ERROR("ACPI VFCT image truncated\n"); 681 goto out_unmap; 682 } 683 684 rdev->bios = kmalloc(vhdr->ImageLength, M_DRM, M_WAITOK); 685 memcpy(rdev->bios, &vbios->VbiosContent, vhdr->ImageLength); 686 ret = !!rdev->bios; 687 688 out_unmap: 689 return ret; 690 } 691 692 bool radeon_get_bios(struct radeon_device *rdev) 693 { 694 bool r; 695 uint16_t tmp; 696 697 r = radeon_atrm_get_bios(rdev); 698 if (r == false) 699 r = radeon_acpi_vfct_bios(rdev); 700 if (r == false) 701 r = igp_read_bios_from_vram(rdev); 702 if (r == false) 703 r = radeon_read_bios(rdev); 704 if (r == false) 705 r = radeon_read_disabled_bios(rdev); 706 if (r == false) 707 r = radeon_read_platform_bios(rdev); 708 if (r == false || rdev->bios == NULL) { 709 DRM_ERROR("Unable to locate a BIOS ROM\n"); 710 rdev->bios = NULL; 711 return false; 712 } 713 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 714 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); 715 goto free_bios; 716 } 717 718 tmp = RBIOS16(0x18); 719 if (RBIOS8(tmp + 0x14) != 0x0) { 720 DRM_INFO("Not an x86 BIOS ROM, not using.\n"); 721 goto free_bios; 722 } 723 724 rdev->bios_header_start = RBIOS16(0x48); 725 if (!rdev->bios_header_start) { 726 goto free_bios; 727 } 728 tmp = rdev->bios_header_start + 4; 729 if (!memcmp(rdev->bios + tmp, "ATOM", 4) || 730 !memcmp(rdev->bios + tmp, "MOTA", 4)) { 731 rdev->is_atom_bios = true; 732 } else { 733 rdev->is_atom_bios = false; 734 } 735 736 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); 737 return true; 738 free_bios: 739 kfree(rdev->bios); 740 rdev->bios = NULL; 741 return false; 742 } 743