1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * 28 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_bios.c 255572 2013-09-14 17:22:34Z dumbbell $ 29 */ 30 31 #include <drm/drmP.h> 32 #include "radeon_reg.h" 33 #include "radeon.h" 34 #include "atom.h" 35 36 #include <linux/slab.h> 37 /* 38 * BIOS. 39 */ 40 41 /* If you boot an IGP board with a discrete card as the primary, 42 * the IGP rom is not accessible via the rom bar as the IGP rom is 43 * part of the system bios. On boot, the system bios puts a 44 * copy of the igp rom at the start of vram if a discrete card is 45 * present. 46 */ 47 static bool igp_read_bios_from_vram(struct radeon_device *rdev) 48 { 49 uint8_t __iomem *bios; 50 resource_size_t vram_base; 51 resource_size_t size = 256 * 1024; /* ??? */ 52 53 if (!(rdev->flags & RADEON_IS_IGP)) 54 if (!radeon_card_posted(rdev)) 55 return false; 56 57 rdev->bios = NULL; 58 vram_base = pci_resource_start(rdev->pdev, 0); 59 bios = ioremap(vram_base, size); 60 if (!bios) { 61 return false; 62 } 63 64 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 65 iounmap(bios); 66 return false; 67 } 68 rdev->bios = kmalloc(size, M_DRM, M_WAITOK); 69 if (rdev->bios == NULL) { 70 iounmap(bios); 71 return false; 72 } 73 memcpy_fromio(rdev->bios, bios, size); 74 iounmap(bios); 75 return true; 76 } 77 78 static bool radeon_read_bios(struct radeon_device *rdev) 79 { 80 device_t vga_dev; 81 uint8_t __iomem *bios; 82 size_t size; 83 84 DRM_INFO("%s: ===> Try PCI Expansion ROM...\n", __func__); 85 86 vga_dev = device_get_parent(rdev->dev); 87 rdev->bios = NULL; 88 /* XXX: some cards may return 0 for rom size? ddx has a workaround */ 89 bios = vga_pci_map_bios(vga_dev, &size); 90 if (!bios) { 91 return false; 92 } 93 DRM_INFO("%s: Map address: %p (%zu bytes)\n", __func__, bios, size); 94 95 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 96 if (size == 0) { 97 DRM_INFO("%s: Incorrect BIOS size\n", __func__); 98 } else { 99 DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n", 100 __func__, bios[0], bios[1]); 101 } 102 vga_pci_unmap_bios(vga_dev, bios); 103 return false; 104 } 105 rdev->bios = kmalloc(size, M_DRM, M_WAITOK); 106 memcpy(rdev->bios, bios, size); 107 vga_pci_unmap_bios(vga_dev, bios); 108 return true; 109 } 110 111 static bool radeon_read_platform_bios(struct radeon_device *rdev) 112 { 113 uint8_t __iomem *bios; 114 size_t size; 115 116 rdev->bios = NULL; 117 118 #if 0 119 // XXX: FIXME 120 bios = pci_platform_rom(rdev->pdev, &size); 121 #else 122 size = 0; 123 bios = NULL; 124 #endif 125 if (!bios) { 126 return false; 127 } 128 129 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 130 return false; 131 } 132 rdev->bios = kmalloc(size, M_DRM, M_WAITOK); 133 if (rdev->bios == NULL) { 134 return false; 135 } 136 memcpy(rdev->bios, bios, size); 137 return true; 138 } 139 140 #ifdef CONFIG_ACPI 141 /* ATRM is used to get the BIOS on the discrete cards in 142 * dual-gpu systems. 143 */ 144 /* retrieve the ROM in 4k blocks */ 145 #define ATRM_BIOS_PAGE 4096 146 /** 147 * radeon_atrm_call - fetch a chunk of the vbios 148 * 149 * @atrm_handle: acpi ATRM handle 150 * @bios: vbios image pointer 151 * @offset: offset of vbios image data to fetch 152 * @len: length of vbios image data to fetch 153 * 154 * Executes ATRM to fetch a chunk of the discrete 155 * vbios image on PX systems (all asics). 156 * Returns the length of the buffer fetched. 157 */ 158 static int radeon_atrm_call(ACPI_HANDLE atrm_handle, uint8_t *bios, 159 int offset, int len) 160 { 161 ACPI_STATUS status; 162 ACPI_OBJECT atrm_arg_elements[2], *obj; 163 ACPI_OBJECT_LIST atrm_arg; 164 ACPI_BUFFER buffer = { ACPI_ALLOCATE_BUFFER, NULL}; 165 166 atrm_arg.Count = 2; 167 atrm_arg.Pointer = &atrm_arg_elements[0]; 168 169 atrm_arg_elements[0].Type = ACPI_TYPE_INTEGER; 170 atrm_arg_elements[0].Integer.Value = offset; 171 172 atrm_arg_elements[1].Type = ACPI_TYPE_INTEGER; 173 atrm_arg_elements[1].Integer.Value = len; 174 175 status = AcpiEvaluateObject(atrm_handle, NULL, &atrm_arg, &buffer); 176 if (ACPI_FAILURE(status)) { 177 printk("failed to evaluate ATRM got %s\n", AcpiFormatException(status)); 178 return -ENODEV; 179 } 180 181 obj = (ACPI_OBJECT *)buffer.Pointer; 182 memcpy(bios+offset, obj->Buffer.Pointer, obj->Buffer.Length); 183 len = obj->Buffer.Length; 184 AcpiOsFree(buffer.Pointer); 185 return len; 186 } 187 188 static bool radeon_atrm_get_bios(struct radeon_device *rdev) 189 { 190 int ret; 191 int size = 256 * 1024; 192 int i; 193 device_t dev; 194 ACPI_HANDLE dhandle, atrm_handle; 195 ACPI_STATUS status; 196 bool found = false; 197 198 DRM_INFO("%s: ===> Try ATRM...\n", __func__); 199 200 /* ATRM is for the discrete card only */ 201 if (rdev->flags & RADEON_IS_IGP) { 202 DRM_INFO("%s: IGP card detected, skipping this method...\n", 203 __func__); 204 return false; 205 } 206 207 #ifdef DUMBBELL_WIP 208 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 209 #endif /* DUMBBELL_WIP */ 210 if ((dev = pci_find_class(PCIC_DISPLAY, PCIS_DISPLAY_VGA)) != NULL) { 211 DRM_INFO("%s: pci_find_class() found: %d:%d:%d:%d, vendor=%04x, device=%04x\n", 212 __func__, 213 pci_get_domain(dev), 214 pci_get_bus(dev), 215 pci_get_slot(dev), 216 pci_get_function(dev), 217 pci_get_vendor(dev), 218 pci_get_device(dev)); 219 DRM_INFO("%s: Get ACPI device handle\n", __func__); 220 dhandle = acpi_get_handle(dev); 221 #ifdef DUMBBELL_WIP 222 if (!dhandle) 223 continue; 224 #endif /* DUMBBELL_WIP */ 225 if (!dhandle) 226 return false; 227 228 DRM_INFO("%s: Get ACPI handle for \"ATRM\"\n", __func__); 229 status = AcpiGetHandle(dhandle, "ATRM", &atrm_handle); 230 if (!ACPI_FAILURE(status)) { 231 found = true; 232 #ifdef DUMBBELL_WIP 233 break; 234 #endif /* DUMBBELL_WIP */ 235 } else { 236 DRM_INFO("%s: Failed to get \"ATRM\" handle: %s\n", 237 __func__, AcpiFormatException(status)); 238 } 239 } 240 241 if (!found) 242 return false; 243 244 rdev->bios = kmalloc(size, M_DRM, M_WAITOK); 245 if (!rdev->bios) { 246 DRM_ERROR("Unable to allocate bios\n"); 247 return false; 248 } 249 250 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { 251 DRM_INFO("%s: Call radeon_atrm_call()\n", __func__); 252 ret = radeon_atrm_call(atrm_handle, 253 rdev->bios, 254 (i * ATRM_BIOS_PAGE), 255 ATRM_BIOS_PAGE); 256 if (ret < ATRM_BIOS_PAGE) 257 break; 258 } 259 260 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 261 if (i == 0) { 262 DRM_INFO("%s: Incorrect BIOS size\n", __func__); 263 } else { 264 DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n", 265 __func__, rdev->bios[0], rdev->bios[1]); 266 } 267 kfree(rdev->bios); 268 return false; 269 } 270 return true; 271 } 272 #else 273 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev) 274 { 275 return false; 276 } 277 #endif 278 279 static bool ni_read_disabled_bios(struct radeon_device *rdev) 280 { 281 u32 bus_cntl; 282 u32 d1vga_control; 283 u32 d2vga_control; 284 u32 vga_render_control; 285 u32 rom_cntl; 286 bool r; 287 288 DRM_INFO("%s: ===> Try disabled BIOS (ni)...\n", __func__); 289 290 bus_cntl = RREG32(R600_BUS_CNTL); 291 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 292 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 293 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 294 rom_cntl = RREG32(R600_ROM_CNTL); 295 296 /* enable the rom */ 297 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 298 if (!ASIC_IS_NODCE(rdev)) { 299 /* Disable VGA mode */ 300 WREG32(AVIVO_D1VGA_CONTROL, 301 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 302 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 303 WREG32(AVIVO_D2VGA_CONTROL, 304 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 305 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 306 WREG32(AVIVO_VGA_RENDER_CONTROL, 307 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 308 } 309 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 310 311 r = radeon_read_bios(rdev); 312 313 /* restore regs */ 314 WREG32(R600_BUS_CNTL, bus_cntl); 315 if (!ASIC_IS_NODCE(rdev)) { 316 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 317 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 318 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 319 } 320 WREG32(R600_ROM_CNTL, rom_cntl); 321 return r; 322 } 323 324 static bool r700_read_disabled_bios(struct radeon_device *rdev) 325 { 326 uint32_t viph_control; 327 uint32_t bus_cntl; 328 uint32_t d1vga_control; 329 uint32_t d2vga_control; 330 uint32_t vga_render_control; 331 uint32_t rom_cntl; 332 uint32_t cg_spll_func_cntl = 0; 333 uint32_t cg_spll_status; 334 bool r; 335 336 DRM_INFO("%s: ===> Try disabled BIOS (r700)...\n", __func__); 337 338 viph_control = RREG32(RADEON_VIPH_CONTROL); 339 bus_cntl = RREG32(R600_BUS_CNTL); 340 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 341 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 342 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 343 rom_cntl = RREG32(R600_ROM_CNTL); 344 345 /* disable VIP */ 346 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 347 /* enable the rom */ 348 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 349 /* Disable VGA mode */ 350 WREG32(AVIVO_D1VGA_CONTROL, 351 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 352 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 353 WREG32(AVIVO_D2VGA_CONTROL, 354 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 355 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 356 WREG32(AVIVO_VGA_RENDER_CONTROL, 357 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 358 359 if (rdev->family == CHIP_RV730) { 360 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); 361 362 /* enable bypass mode */ 363 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | 364 R600_SPLL_BYPASS_EN)); 365 366 /* wait for SPLL_CHG_STATUS to change to 1 */ 367 cg_spll_status = 0; 368 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 369 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 370 371 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); 372 } else 373 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 374 375 r = radeon_read_bios(rdev); 376 377 /* restore regs */ 378 if (rdev->family == CHIP_RV730) { 379 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); 380 381 /* wait for SPLL_CHG_STATUS to change to 1 */ 382 cg_spll_status = 0; 383 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 384 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 385 } 386 WREG32(RADEON_VIPH_CONTROL, viph_control); 387 WREG32(R600_BUS_CNTL, bus_cntl); 388 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 389 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 390 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 391 WREG32(R600_ROM_CNTL, rom_cntl); 392 return r; 393 } 394 395 static bool r600_read_disabled_bios(struct radeon_device *rdev) 396 { 397 uint32_t viph_control; 398 uint32_t bus_cntl; 399 uint32_t d1vga_control; 400 uint32_t d2vga_control; 401 uint32_t vga_render_control; 402 uint32_t rom_cntl; 403 uint32_t general_pwrmgt; 404 uint32_t low_vid_lower_gpio_cntl; 405 uint32_t medium_vid_lower_gpio_cntl; 406 uint32_t high_vid_lower_gpio_cntl; 407 uint32_t ctxsw_vid_lower_gpio_cntl; 408 uint32_t lower_gpio_enable; 409 bool r; 410 411 DRM_INFO("%s: ===> Try disabled BIOS (r600)...\n", __func__); 412 413 viph_control = RREG32(RADEON_VIPH_CONTROL); 414 bus_cntl = RREG32(R600_BUS_CNTL); 415 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 416 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 417 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 418 rom_cntl = RREG32(R600_ROM_CNTL); 419 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); 420 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); 421 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); 422 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); 423 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); 424 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); 425 426 /* disable VIP */ 427 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 428 /* enable the rom */ 429 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 430 /* Disable VGA mode */ 431 WREG32(AVIVO_D1VGA_CONTROL, 432 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 433 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 434 WREG32(AVIVO_D2VGA_CONTROL, 435 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 436 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 437 WREG32(AVIVO_VGA_RENDER_CONTROL, 438 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 439 440 WREG32(R600_ROM_CNTL, 441 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | 442 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | 443 R600_SCK_OVERWRITE)); 444 445 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 446 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, 447 (low_vid_lower_gpio_cntl & ~0x400)); 448 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, 449 (medium_vid_lower_gpio_cntl & ~0x400)); 450 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, 451 (high_vid_lower_gpio_cntl & ~0x400)); 452 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, 453 (ctxsw_vid_lower_gpio_cntl & ~0x400)); 454 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); 455 456 r = radeon_read_bios(rdev); 457 458 /* restore regs */ 459 WREG32(RADEON_VIPH_CONTROL, viph_control); 460 WREG32(R600_BUS_CNTL, bus_cntl); 461 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 462 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 463 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 464 WREG32(R600_ROM_CNTL, rom_cntl); 465 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); 466 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); 467 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); 468 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); 469 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); 470 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 471 return r; 472 } 473 474 static bool avivo_read_disabled_bios(struct radeon_device *rdev) 475 { 476 uint32_t seprom_cntl1; 477 uint32_t viph_control; 478 uint32_t bus_cntl; 479 uint32_t d1vga_control; 480 uint32_t d2vga_control; 481 uint32_t vga_render_control; 482 uint32_t gpiopad_a; 483 uint32_t gpiopad_en; 484 uint32_t gpiopad_mask; 485 bool r; 486 487 DRM_INFO("%s: ===> Try disabled BIOS (avivo)...\n", __func__); 488 489 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 490 viph_control = RREG32(RADEON_VIPH_CONTROL); 491 bus_cntl = RREG32(RV370_BUS_CNTL); 492 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 493 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 494 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 495 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 496 gpiopad_en = RREG32(RADEON_GPIOPAD_EN); 497 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); 498 499 WREG32(RADEON_SEPROM_CNTL1, 500 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 501 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 502 WREG32(RADEON_GPIOPAD_A, 0); 503 WREG32(RADEON_GPIOPAD_EN, 0); 504 WREG32(RADEON_GPIOPAD_MASK, 0); 505 506 /* disable VIP */ 507 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 508 509 /* enable the rom */ 510 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 511 512 /* Disable VGA mode */ 513 WREG32(AVIVO_D1VGA_CONTROL, 514 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 515 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 516 WREG32(AVIVO_D2VGA_CONTROL, 517 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 518 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 519 WREG32(AVIVO_VGA_RENDER_CONTROL, 520 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 521 522 r = radeon_read_bios(rdev); 523 524 /* restore regs */ 525 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 526 WREG32(RADEON_VIPH_CONTROL, viph_control); 527 WREG32(RV370_BUS_CNTL, bus_cntl); 528 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 529 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 530 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 531 WREG32(RADEON_GPIOPAD_A, gpiopad_a); 532 WREG32(RADEON_GPIOPAD_EN, gpiopad_en); 533 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); 534 return r; 535 } 536 537 static bool legacy_read_disabled_bios(struct radeon_device *rdev) 538 { 539 uint32_t seprom_cntl1; 540 uint32_t viph_control; 541 uint32_t bus_cntl; 542 uint32_t crtc_gen_cntl; 543 uint32_t crtc2_gen_cntl; 544 uint32_t crtc_ext_cntl; 545 uint32_t fp2_gen_cntl; 546 bool r; 547 548 DRM_INFO("%s: ===> Try disabled BIOS (legacy)...\n", __func__); 549 550 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 551 viph_control = RREG32(RADEON_VIPH_CONTROL); 552 if (rdev->flags & RADEON_IS_PCIE) 553 bus_cntl = RREG32(RV370_BUS_CNTL); 554 else 555 bus_cntl = RREG32(RADEON_BUS_CNTL); 556 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 557 crtc2_gen_cntl = 0; 558 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 559 fp2_gen_cntl = 0; 560 561 #define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 562 563 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 564 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 565 } 566 567 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 568 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 569 } 570 571 WREG32(RADEON_SEPROM_CNTL1, 572 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 573 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 574 575 /* disable VIP */ 576 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 577 578 /* enable the rom */ 579 if (rdev->flags & RADEON_IS_PCIE) 580 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 581 else 582 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 583 584 /* Turn off mem requests and CRTC for both controllers */ 585 WREG32(RADEON_CRTC_GEN_CNTL, 586 ((crtc_gen_cntl & ~RADEON_CRTC_EN) | 587 (RADEON_CRTC_DISP_REQ_EN_B | 588 RADEON_CRTC_EXT_DISP_EN))); 589 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 590 WREG32(RADEON_CRTC2_GEN_CNTL, 591 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | 592 RADEON_CRTC2_DISP_REQ_EN_B)); 593 } 594 /* Turn off CRTC */ 595 WREG32(RADEON_CRTC_EXT_CNTL, 596 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | 597 (RADEON_CRTC_SYNC_TRISTAT | 598 RADEON_CRTC_DISPLAY_DIS))); 599 600 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 601 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); 602 } 603 604 r = radeon_read_bios(rdev); 605 606 /* restore regs */ 607 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 608 WREG32(RADEON_VIPH_CONTROL, viph_control); 609 if (rdev->flags & RADEON_IS_PCIE) 610 WREG32(RV370_BUS_CNTL, bus_cntl); 611 else 612 WREG32(RADEON_BUS_CNTL, bus_cntl); 613 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 614 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 615 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 616 } 617 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 618 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 619 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 620 } 621 return r; 622 } 623 624 static bool radeon_read_disabled_bios(struct radeon_device *rdev) 625 { 626 if (rdev->flags & RADEON_IS_IGP) 627 return igp_read_bios_from_vram(rdev); 628 else if (rdev->family >= CHIP_BARTS) 629 return ni_read_disabled_bios(rdev); 630 else if (rdev->family >= CHIP_RV770) 631 return r700_read_disabled_bios(rdev); 632 else if (rdev->family >= CHIP_R600) 633 return r600_read_disabled_bios(rdev); 634 else if (rdev->family >= CHIP_RS600) 635 return avivo_read_disabled_bios(rdev); 636 else 637 return legacy_read_disabled_bios(rdev); 638 } 639 640 #ifdef CONFIG_ACPI 641 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 642 { 643 bool ret = false; 644 ACPI_TABLE_HEADER *hdr; 645 ACPI_SIZE tbl_size; 646 UEFI_ACPI_VFCT *vfct; 647 GOP_VBIOS_CONTENT *vbios; 648 VFCT_IMAGE_HEADER *vhdr; 649 ACPI_STATUS status; 650 651 DRM_INFO("%s: ===> Try VFCT...\n", __func__); 652 653 DRM_INFO("%s: Get \"VFCT\" ACPI table\n", __func__); 654 status = AcpiGetTable("VFCT", 1, &hdr); 655 if (!ACPI_SUCCESS(status)) { 656 DRM_INFO("%s: Failed to get \"VFCT\" table: %s\n", 657 __func__, AcpiFormatException(status)); 658 return false; 659 } 660 tbl_size = hdr->Length; 661 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { 662 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); 663 goto out_unmap; 664 } 665 666 vfct = (UEFI_ACPI_VFCT *)hdr; 667 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) { 668 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); 669 goto out_unmap; 670 } 671 672 vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset); 673 vhdr = &vbios->VbiosHeader; 674 DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n", 675 vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction, 676 vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength); 677 678 if (vhdr->PCIBus != rdev->pdev->bus->number || 679 vhdr->PCIDevice != rdev->ddev->pci_slot || 680 vhdr->PCIFunction != rdev->ddev->pci_func || 681 vhdr->VendorID != rdev->pdev->vendor || 682 vhdr->DeviceID != rdev->pdev->device) { 683 DRM_INFO("ACPI VFCT table is not for this card\n"); 684 goto out_unmap; 685 } 686 687 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) { 688 DRM_ERROR("ACPI VFCT image truncated\n"); 689 goto out_unmap; 690 } 691 692 rdev->bios = kmalloc(vhdr->ImageLength, M_DRM, M_WAITOK); 693 memcpy(rdev->bios, &vbios->VbiosContent, vhdr->ImageLength); 694 ret = !!rdev->bios; 695 696 out_unmap: 697 return ret; 698 } 699 #else 700 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 701 { 702 return false; 703 } 704 #endif 705 706 bool radeon_get_bios(struct radeon_device *rdev) 707 { 708 bool r; 709 uint16_t tmp; 710 711 r = radeon_atrm_get_bios(rdev); 712 if (r == false) 713 r = radeon_acpi_vfct_bios(rdev); 714 if (r == false) 715 r = igp_read_bios_from_vram(rdev); 716 if (r == false) 717 r = radeon_read_bios(rdev); 718 if (r == false) 719 r = radeon_read_disabled_bios(rdev); 720 if (r == false) 721 r = radeon_read_platform_bios(rdev); 722 if (r == false || rdev->bios == NULL) { 723 DRM_ERROR("Unable to locate a BIOS ROM\n"); 724 rdev->bios = NULL; 725 return false; 726 } 727 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 728 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); 729 goto free_bios; 730 } 731 732 tmp = RBIOS16(0x18); 733 if (RBIOS8(tmp + 0x14) != 0x0) { 734 DRM_INFO("Not an x86 BIOS ROM, not using.\n"); 735 goto free_bios; 736 } 737 738 rdev->bios_header_start = RBIOS16(0x48); 739 if (!rdev->bios_header_start) { 740 goto free_bios; 741 } 742 tmp = rdev->bios_header_start + 4; 743 if (!memcmp(rdev->bios + tmp, "ATOM", 4) || 744 !memcmp(rdev->bios + tmp, "MOTA", 4)) { 745 rdev->is_atom_bios = true; 746 } else { 747 rdev->is_atom_bios = false; 748 } 749 750 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); 751 return true; 752 free_bios: 753 kfree(rdev->bios); 754 rdev->bios = NULL; 755 return false; 756 } 757