1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * 28 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_bios.c 255572 2013-09-14 17:22:34Z dumbbell $ 29 */ 30 31 #include <drm/drmP.h> 32 #include "radeon_reg.h" 33 #include "radeon.h" 34 #include "atom.h" 35 36 #include <linux/slab.h> 37 /* 38 * BIOS. 39 */ 40 41 /* If you boot an IGP board with a discrete card as the primary, 42 * the IGP rom is not accessible via the rom bar as the IGP rom is 43 * part of the system bios. On boot, the system bios puts a 44 * copy of the igp rom at the start of vram if a discrete card is 45 * present. 46 */ 47 static bool igp_read_bios_from_vram(struct radeon_device *rdev) 48 { 49 drm_local_map_t bios_map; 50 uint8_t __iomem *bios; 51 resource_size_t vram_base; 52 resource_size_t size = 256 * 1024; /* ??? */ 53 54 DRM_INFO("%s: ===> Try IGP's VRAM...\n", __func__); 55 56 if (!(rdev->flags & RADEON_IS_IGP)) 57 if (!radeon_card_posted(rdev)) { 58 DRM_INFO("%s: not POSTed discrete card detected, skipping this method...\n", 59 __func__); 60 return false; 61 } 62 63 rdev->bios = NULL; 64 vram_base = drm_get_resource_start(rdev->ddev, 0); 65 DRM_INFO("%s: VRAM base address: 0x%jx\n", __func__, (uintmax_t)vram_base); 66 67 bios_map.offset = vram_base; 68 bios_map.size = size; 69 bios_map.type = 0; 70 bios_map.flags = 0; 71 bios_map.mtrr = 0; 72 drm_core_ioremap(&bios_map, rdev->ddev); 73 if (bios_map.handle == NULL) { 74 DRM_INFO("%s: failed to ioremap\n", __func__); 75 return false; 76 } 77 bios = bios_map.handle; 78 size = bios_map.size; 79 DRM_INFO("%s: Map address: %p (%ju bytes)\n", __func__, bios, (uintmax_t)size); 80 81 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 82 if (size == 0) { 83 DRM_INFO("%s: Incorrect BIOS size\n", __func__); 84 } else { 85 DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n", 86 __func__, bios[0], bios[1]); 87 } 88 drm_core_ioremapfree(&bios_map, rdev->ddev); 89 return false; 90 } 91 rdev->bios = kmalloc(size, M_DRM, M_WAITOK); 92 if (rdev->bios == NULL) { 93 drm_core_ioremapfree(&bios_map, rdev->ddev); 94 return false; 95 } 96 memcpy_fromio(rdev->bios, bios, size); 97 drm_core_ioremapfree(&bios_map, rdev->ddev); 98 return true; 99 } 100 101 static bool radeon_read_bios(struct radeon_device *rdev) 102 { 103 device_t vga_dev; 104 uint8_t __iomem *bios; 105 size_t size; 106 107 DRM_INFO("%s: ===> Try PCI Expansion ROM...\n", __func__); 108 109 vga_dev = device_get_parent(rdev->dev); 110 rdev->bios = NULL; 111 /* XXX: some cards may return 0 for rom size? ddx has a workaround */ 112 bios = vga_pci_map_bios(vga_dev, &size); 113 if (!bios) { 114 return false; 115 } 116 DRM_INFO("%s: Map address: %p (%zu bytes)\n", __func__, bios, size); 117 118 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 119 if (size == 0) { 120 DRM_INFO("%s: Incorrect BIOS size\n", __func__); 121 } else { 122 DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n", 123 __func__, bios[0], bios[1]); 124 } 125 vga_pci_unmap_bios(vga_dev, bios); 126 return false; 127 } 128 rdev->bios = kmalloc(size, M_DRM, M_WAITOK); 129 memcpy(rdev->bios, bios, size); 130 vga_pci_unmap_bios(vga_dev, bios); 131 return true; 132 } 133 134 static bool radeon_read_platform_bios(struct radeon_device *rdev) 135 { 136 uint8_t __iomem *bios; 137 size_t size; 138 139 rdev->bios = NULL; 140 141 #if 0 142 // XXX: FIXME 143 bios = pci_platform_rom(rdev->pdev, &size); 144 #else 145 size = 0; 146 bios = NULL; 147 #endif 148 if (!bios) { 149 return false; 150 } 151 152 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 153 return false; 154 } 155 rdev->bios = kmalloc(size, M_DRM, M_WAITOK); 156 if (rdev->bios == NULL) { 157 return false; 158 } 159 memcpy(rdev->bios, bios, size); 160 return true; 161 } 162 163 /* ATRM is used to get the BIOS on the discrete cards in 164 * dual-gpu systems. 165 */ 166 /* retrieve the ROM in 4k blocks */ 167 #define ATRM_BIOS_PAGE 4096 168 /** 169 * radeon_atrm_call - fetch a chunk of the vbios 170 * 171 * @atrm_handle: acpi ATRM handle 172 * @bios: vbios image pointer 173 * @offset: offset of vbios image data to fetch 174 * @len: length of vbios image data to fetch 175 * 176 * Executes ATRM to fetch a chunk of the discrete 177 * vbios image on PX systems (all asics). 178 * Returns the length of the buffer fetched. 179 */ 180 static int radeon_atrm_call(ACPI_HANDLE atrm_handle, uint8_t *bios, 181 int offset, int len) 182 { 183 ACPI_STATUS status; 184 ACPI_OBJECT atrm_arg_elements[2], *obj; 185 ACPI_OBJECT_LIST atrm_arg; 186 ACPI_BUFFER buffer = { ACPI_ALLOCATE_BUFFER, NULL}; 187 188 atrm_arg.Count = 2; 189 atrm_arg.Pointer = &atrm_arg_elements[0]; 190 191 atrm_arg_elements[0].Type = ACPI_TYPE_INTEGER; 192 atrm_arg_elements[0].Integer.Value = offset; 193 194 atrm_arg_elements[1].Type = ACPI_TYPE_INTEGER; 195 atrm_arg_elements[1].Integer.Value = len; 196 197 status = AcpiEvaluateObject(atrm_handle, NULL, &atrm_arg, &buffer); 198 if (ACPI_FAILURE(status)) { 199 printk("failed to evaluate ATRM got %s\n", AcpiFormatException(status)); 200 return -ENODEV; 201 } 202 203 obj = (ACPI_OBJECT *)buffer.Pointer; 204 memcpy(bios+offset, obj->Buffer.Pointer, obj->Buffer.Length); 205 len = obj->Buffer.Length; 206 AcpiOsFree(buffer.Pointer); 207 return len; 208 } 209 210 static bool radeon_atrm_get_bios(struct radeon_device *rdev) 211 { 212 int ret; 213 int size = 256 * 1024; 214 int i; 215 device_t dev; 216 ACPI_HANDLE dhandle, atrm_handle; 217 ACPI_STATUS status; 218 bool found = false; 219 220 DRM_INFO("%s: ===> Try ATRM...\n", __func__); 221 222 /* ATRM is for the discrete card only */ 223 if (rdev->flags & RADEON_IS_IGP) { 224 DRM_INFO("%s: IGP card detected, skipping this method...\n", 225 __func__); 226 return false; 227 } 228 229 #ifdef DUMBBELL_WIP 230 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 231 #endif /* DUMBBELL_WIP */ 232 if ((dev = pci_find_class(PCIC_DISPLAY, PCIS_DISPLAY_VGA)) != NULL) { 233 DRM_INFO("%s: pci_find_class() found: %d:%d:%d:%d, vendor=%04x, device=%04x\n", 234 __func__, 235 pci_get_domain(dev), 236 pci_get_bus(dev), 237 pci_get_slot(dev), 238 pci_get_function(dev), 239 pci_get_vendor(dev), 240 pci_get_device(dev)); 241 DRM_INFO("%s: Get ACPI device handle\n", __func__); 242 dhandle = acpi_get_handle(dev); 243 #ifdef DUMBBELL_WIP 244 if (!dhandle) 245 continue; 246 #endif /* DUMBBELL_WIP */ 247 if (!dhandle) 248 return false; 249 250 DRM_INFO("%s: Get ACPI handle for \"ATRM\"\n", __func__); 251 status = AcpiGetHandle(dhandle, "ATRM", &atrm_handle); 252 if (!ACPI_FAILURE(status)) { 253 found = true; 254 #ifdef DUMBBELL_WIP 255 break; 256 #endif /* DUMBBELL_WIP */ 257 } else { 258 DRM_INFO("%s: Failed to get \"ATRM\" handle: %s\n", 259 __func__, AcpiFormatException(status)); 260 } 261 } 262 263 if (!found) 264 return false; 265 266 rdev->bios = kmalloc(size, M_DRM, M_WAITOK); 267 if (!rdev->bios) { 268 DRM_ERROR("Unable to allocate bios\n"); 269 return false; 270 } 271 272 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { 273 DRM_INFO("%s: Call radeon_atrm_call()\n", __func__); 274 ret = radeon_atrm_call(atrm_handle, 275 rdev->bios, 276 (i * ATRM_BIOS_PAGE), 277 ATRM_BIOS_PAGE); 278 if (ret < ATRM_BIOS_PAGE) 279 break; 280 } 281 282 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 283 if (i == 0) { 284 DRM_INFO("%s: Incorrect BIOS size\n", __func__); 285 } else { 286 DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n", 287 __func__, rdev->bios[0], rdev->bios[1]); 288 } 289 kfree(rdev->bios); 290 return false; 291 } 292 return true; 293 } 294 295 static bool ni_read_disabled_bios(struct radeon_device *rdev) 296 { 297 u32 bus_cntl; 298 u32 d1vga_control; 299 u32 d2vga_control; 300 u32 vga_render_control; 301 u32 rom_cntl; 302 bool r; 303 304 DRM_INFO("%s: ===> Try disabled BIOS (ni)...\n", __func__); 305 306 bus_cntl = RREG32(R600_BUS_CNTL); 307 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 308 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 309 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 310 rom_cntl = RREG32(R600_ROM_CNTL); 311 312 /* enable the rom */ 313 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 314 if (!ASIC_IS_NODCE(rdev)) { 315 /* Disable VGA mode */ 316 WREG32(AVIVO_D1VGA_CONTROL, 317 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 318 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 319 WREG32(AVIVO_D2VGA_CONTROL, 320 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 321 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 322 WREG32(AVIVO_VGA_RENDER_CONTROL, 323 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 324 } 325 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 326 327 r = radeon_read_bios(rdev); 328 329 /* restore regs */ 330 WREG32(R600_BUS_CNTL, bus_cntl); 331 if (!ASIC_IS_NODCE(rdev)) { 332 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 333 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 334 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 335 } 336 WREG32(R600_ROM_CNTL, rom_cntl); 337 return r; 338 } 339 340 static bool r700_read_disabled_bios(struct radeon_device *rdev) 341 { 342 uint32_t viph_control; 343 uint32_t bus_cntl; 344 uint32_t d1vga_control; 345 uint32_t d2vga_control; 346 uint32_t vga_render_control; 347 uint32_t rom_cntl; 348 uint32_t cg_spll_func_cntl = 0; 349 uint32_t cg_spll_status; 350 bool r; 351 352 DRM_INFO("%s: ===> Try disabled BIOS (r700)...\n", __func__); 353 354 viph_control = RREG32(RADEON_VIPH_CONTROL); 355 bus_cntl = RREG32(R600_BUS_CNTL); 356 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 357 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 358 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 359 rom_cntl = RREG32(R600_ROM_CNTL); 360 361 /* disable VIP */ 362 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 363 /* enable the rom */ 364 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 365 /* Disable VGA mode */ 366 WREG32(AVIVO_D1VGA_CONTROL, 367 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 368 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 369 WREG32(AVIVO_D2VGA_CONTROL, 370 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 371 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 372 WREG32(AVIVO_VGA_RENDER_CONTROL, 373 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 374 375 if (rdev->family == CHIP_RV730) { 376 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); 377 378 /* enable bypass mode */ 379 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | 380 R600_SPLL_BYPASS_EN)); 381 382 /* wait for SPLL_CHG_STATUS to change to 1 */ 383 cg_spll_status = 0; 384 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 385 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 386 387 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); 388 } else 389 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 390 391 r = radeon_read_bios(rdev); 392 393 /* restore regs */ 394 if (rdev->family == CHIP_RV730) { 395 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); 396 397 /* wait for SPLL_CHG_STATUS to change to 1 */ 398 cg_spll_status = 0; 399 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 400 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 401 } 402 WREG32(RADEON_VIPH_CONTROL, viph_control); 403 WREG32(R600_BUS_CNTL, bus_cntl); 404 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 405 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 406 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 407 WREG32(R600_ROM_CNTL, rom_cntl); 408 return r; 409 } 410 411 static bool r600_read_disabled_bios(struct radeon_device *rdev) 412 { 413 uint32_t viph_control; 414 uint32_t bus_cntl; 415 uint32_t d1vga_control; 416 uint32_t d2vga_control; 417 uint32_t vga_render_control; 418 uint32_t rom_cntl; 419 uint32_t general_pwrmgt; 420 uint32_t low_vid_lower_gpio_cntl; 421 uint32_t medium_vid_lower_gpio_cntl; 422 uint32_t high_vid_lower_gpio_cntl; 423 uint32_t ctxsw_vid_lower_gpio_cntl; 424 uint32_t lower_gpio_enable; 425 bool r; 426 427 DRM_INFO("%s: ===> Try disabled BIOS (r600)...\n", __func__); 428 429 viph_control = RREG32(RADEON_VIPH_CONTROL); 430 bus_cntl = RREG32(R600_BUS_CNTL); 431 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 432 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 433 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 434 rom_cntl = RREG32(R600_ROM_CNTL); 435 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); 436 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); 437 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); 438 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); 439 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); 440 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); 441 442 /* disable VIP */ 443 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 444 /* enable the rom */ 445 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 446 /* Disable VGA mode */ 447 WREG32(AVIVO_D1VGA_CONTROL, 448 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 449 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 450 WREG32(AVIVO_D2VGA_CONTROL, 451 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 452 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 453 WREG32(AVIVO_VGA_RENDER_CONTROL, 454 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 455 456 WREG32(R600_ROM_CNTL, 457 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | 458 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | 459 R600_SCK_OVERWRITE)); 460 461 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 462 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, 463 (low_vid_lower_gpio_cntl & ~0x400)); 464 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, 465 (medium_vid_lower_gpio_cntl & ~0x400)); 466 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, 467 (high_vid_lower_gpio_cntl & ~0x400)); 468 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, 469 (ctxsw_vid_lower_gpio_cntl & ~0x400)); 470 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); 471 472 r = radeon_read_bios(rdev); 473 474 /* restore regs */ 475 WREG32(RADEON_VIPH_CONTROL, viph_control); 476 WREG32(R600_BUS_CNTL, bus_cntl); 477 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 478 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 479 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 480 WREG32(R600_ROM_CNTL, rom_cntl); 481 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); 482 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); 483 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); 484 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); 485 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); 486 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 487 return r; 488 } 489 490 static bool avivo_read_disabled_bios(struct radeon_device *rdev) 491 { 492 uint32_t seprom_cntl1; 493 uint32_t viph_control; 494 uint32_t bus_cntl; 495 uint32_t d1vga_control; 496 uint32_t d2vga_control; 497 uint32_t vga_render_control; 498 uint32_t gpiopad_a; 499 uint32_t gpiopad_en; 500 uint32_t gpiopad_mask; 501 bool r; 502 503 DRM_INFO("%s: ===> Try disabled BIOS (avivo)...\n", __func__); 504 505 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 506 viph_control = RREG32(RADEON_VIPH_CONTROL); 507 bus_cntl = RREG32(RV370_BUS_CNTL); 508 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 509 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 510 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 511 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 512 gpiopad_en = RREG32(RADEON_GPIOPAD_EN); 513 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); 514 515 WREG32(RADEON_SEPROM_CNTL1, 516 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 517 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 518 WREG32(RADEON_GPIOPAD_A, 0); 519 WREG32(RADEON_GPIOPAD_EN, 0); 520 WREG32(RADEON_GPIOPAD_MASK, 0); 521 522 /* disable VIP */ 523 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 524 525 /* enable the rom */ 526 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 527 528 /* Disable VGA mode */ 529 WREG32(AVIVO_D1VGA_CONTROL, 530 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 531 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 532 WREG32(AVIVO_D2VGA_CONTROL, 533 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 534 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 535 WREG32(AVIVO_VGA_RENDER_CONTROL, 536 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 537 538 r = radeon_read_bios(rdev); 539 540 /* restore regs */ 541 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 542 WREG32(RADEON_VIPH_CONTROL, viph_control); 543 WREG32(RV370_BUS_CNTL, bus_cntl); 544 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 545 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 546 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 547 WREG32(RADEON_GPIOPAD_A, gpiopad_a); 548 WREG32(RADEON_GPIOPAD_EN, gpiopad_en); 549 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); 550 return r; 551 } 552 553 static bool legacy_read_disabled_bios(struct radeon_device *rdev) 554 { 555 uint32_t seprom_cntl1; 556 uint32_t viph_control; 557 uint32_t bus_cntl; 558 uint32_t crtc_gen_cntl; 559 uint32_t crtc2_gen_cntl; 560 uint32_t crtc_ext_cntl; 561 uint32_t fp2_gen_cntl; 562 bool r; 563 564 DRM_INFO("%s: ===> Try disabled BIOS (legacy)...\n", __func__); 565 566 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 567 viph_control = RREG32(RADEON_VIPH_CONTROL); 568 if (rdev->flags & RADEON_IS_PCIE) 569 bus_cntl = RREG32(RV370_BUS_CNTL); 570 else 571 bus_cntl = RREG32(RADEON_BUS_CNTL); 572 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 573 crtc2_gen_cntl = 0; 574 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 575 fp2_gen_cntl = 0; 576 577 #define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 578 579 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 580 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 581 } 582 583 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 584 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 585 } 586 587 WREG32(RADEON_SEPROM_CNTL1, 588 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 589 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 590 591 /* disable VIP */ 592 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 593 594 /* enable the rom */ 595 if (rdev->flags & RADEON_IS_PCIE) 596 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 597 else 598 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 599 600 /* Turn off mem requests and CRTC for both controllers */ 601 WREG32(RADEON_CRTC_GEN_CNTL, 602 ((crtc_gen_cntl & ~RADEON_CRTC_EN) | 603 (RADEON_CRTC_DISP_REQ_EN_B | 604 RADEON_CRTC_EXT_DISP_EN))); 605 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 606 WREG32(RADEON_CRTC2_GEN_CNTL, 607 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | 608 RADEON_CRTC2_DISP_REQ_EN_B)); 609 } 610 /* Turn off CRTC */ 611 WREG32(RADEON_CRTC_EXT_CNTL, 612 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | 613 (RADEON_CRTC_SYNC_TRISTAT | 614 RADEON_CRTC_DISPLAY_DIS))); 615 616 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 617 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); 618 } 619 620 r = radeon_read_bios(rdev); 621 622 /* restore regs */ 623 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 624 WREG32(RADEON_VIPH_CONTROL, viph_control); 625 if (rdev->flags & RADEON_IS_PCIE) 626 WREG32(RV370_BUS_CNTL, bus_cntl); 627 else 628 WREG32(RADEON_BUS_CNTL, bus_cntl); 629 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 630 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 631 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 632 } 633 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 634 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 635 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 636 } 637 return r; 638 } 639 640 static bool radeon_read_disabled_bios(struct radeon_device *rdev) 641 { 642 if (rdev->flags & RADEON_IS_IGP) 643 return igp_read_bios_from_vram(rdev); 644 else if (rdev->family >= CHIP_BARTS) 645 return ni_read_disabled_bios(rdev); 646 else if (rdev->family >= CHIP_RV770) 647 return r700_read_disabled_bios(rdev); 648 else if (rdev->family >= CHIP_R600) 649 return r600_read_disabled_bios(rdev); 650 else if (rdev->family >= CHIP_RS600) 651 return avivo_read_disabled_bios(rdev); 652 else 653 return legacy_read_disabled_bios(rdev); 654 } 655 656 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 657 { 658 bool ret = false; 659 ACPI_TABLE_HEADER *hdr; 660 ACPI_SIZE tbl_size; 661 UEFI_ACPI_VFCT *vfct; 662 GOP_VBIOS_CONTENT *vbios; 663 VFCT_IMAGE_HEADER *vhdr; 664 ACPI_STATUS status; 665 666 DRM_INFO("%s: ===> Try VFCT...\n", __func__); 667 668 DRM_INFO("%s: Get \"VFCT\" ACPI table\n", __func__); 669 status = AcpiGetTable("VFCT", 1, &hdr); 670 if (!ACPI_SUCCESS(status)) { 671 DRM_INFO("%s: Failed to get \"VFCT\" table: %s\n", 672 __func__, AcpiFormatException(status)); 673 return false; 674 } 675 tbl_size = hdr->Length; 676 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { 677 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); 678 goto out_unmap; 679 } 680 681 vfct = (UEFI_ACPI_VFCT *)hdr; 682 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) { 683 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); 684 goto out_unmap; 685 } 686 687 vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset); 688 vhdr = &vbios->VbiosHeader; 689 DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n", 690 vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction, 691 vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength); 692 693 if (vhdr->PCIBus != rdev->pdev->bus->number || 694 vhdr->PCIDevice != rdev->ddev->pci_slot || 695 vhdr->PCIFunction != rdev->ddev->pci_func || 696 vhdr->VendorID != rdev->pdev->vendor || 697 vhdr->DeviceID != rdev->pdev->device) { 698 DRM_INFO("ACPI VFCT table is not for this card\n"); 699 goto out_unmap; 700 } 701 702 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) { 703 DRM_ERROR("ACPI VFCT image truncated\n"); 704 goto out_unmap; 705 } 706 707 rdev->bios = kmalloc(vhdr->ImageLength, M_DRM, M_WAITOK); 708 memcpy(rdev->bios, &vbios->VbiosContent, vhdr->ImageLength); 709 ret = !!rdev->bios; 710 711 out_unmap: 712 return ret; 713 } 714 715 bool radeon_get_bios(struct radeon_device *rdev) 716 { 717 bool r; 718 uint16_t tmp; 719 720 r = radeon_atrm_get_bios(rdev); 721 if (r == false) 722 r = radeon_acpi_vfct_bios(rdev); 723 if (r == false) 724 r = igp_read_bios_from_vram(rdev); 725 if (r == false) 726 r = radeon_read_bios(rdev); 727 if (r == false) { 728 r = radeon_read_disabled_bios(rdev); 729 } 730 if (r == false) { 731 r = radeon_read_platform_bios(rdev); 732 } 733 if (r == false || rdev->bios == NULL) { 734 DRM_ERROR("Unable to locate a BIOS ROM\n"); 735 rdev->bios = NULL; 736 return false; 737 } 738 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 739 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); 740 goto free_bios; 741 } 742 743 tmp = RBIOS16(0x18); 744 if (RBIOS8(tmp + 0x14) != 0x0) { 745 DRM_INFO("Not an x86 BIOS ROM, not using.\n"); 746 goto free_bios; 747 } 748 749 rdev->bios_header_start = RBIOS16(0x48); 750 if (!rdev->bios_header_start) { 751 goto free_bios; 752 } 753 tmp = rdev->bios_header_start + 4; 754 if (!memcmp(rdev->bios + tmp, "ATOM", 4) || 755 !memcmp(rdev->bios + tmp, "MOTA", 4)) { 756 rdev->is_atom_bios = true; 757 } else { 758 rdev->is_atom_bios = false; 759 } 760 761 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); 762 return true; 763 free_bios: 764 kfree(rdev->bios); 765 rdev->bios = NULL; 766 return false; 767 } 768