1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * 28 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_bios.c 255572 2013-09-14 17:22:34Z dumbbell $ 29 */ 30 31 #include <drm/drmP.h> 32 #include "radeon_reg.h" 33 #include "radeon.h" 34 #include "atom.h" 35 36 /* 37 * BIOS. 38 */ 39 40 /* If you boot an IGP board with a discrete card as the primary, 41 * the IGP rom is not accessible via the rom bar as the IGP rom is 42 * part of the system bios. On boot, the system bios puts a 43 * copy of the igp rom at the start of vram if a discrete card is 44 * present. 45 */ 46 static bool igp_read_bios_from_vram(struct radeon_device *rdev) 47 { 48 drm_local_map_t bios_map; 49 uint8_t __iomem *bios; 50 resource_size_t vram_base; 51 resource_size_t size = 256 * 1024; /* ??? */ 52 53 DRM_INFO("%s: ===> Try IGP's VRAM...\n", __func__); 54 55 if (!(rdev->flags & RADEON_IS_IGP)) 56 if (!radeon_card_posted(rdev)) { 57 DRM_INFO("%s: not POSTed discrete card detected, skipping this method...\n", 58 __func__); 59 return false; 60 } 61 62 rdev->bios = NULL; 63 vram_base = drm_get_resource_start(rdev->ddev, 0); 64 DRM_INFO("%s: VRAM base address: 0x%jx\n", __func__, (uintmax_t)vram_base); 65 66 bios_map.offset = vram_base; 67 bios_map.size = size; 68 bios_map.type = 0; 69 bios_map.flags = 0; 70 bios_map.mtrr = 0; 71 drm_core_ioremap(&bios_map, rdev->ddev); 72 if (bios_map.handle == NULL) { 73 DRM_INFO("%s: failed to ioremap\n", __func__); 74 return false; 75 } 76 bios = bios_map.handle; 77 size = bios_map.size; 78 DRM_INFO("%s: Map address: %p (%ju bytes)\n", __func__, bios, (uintmax_t)size); 79 80 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 81 if (size == 0) { 82 DRM_INFO("%s: Incorrect BIOS size\n", __func__); 83 } else { 84 DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n", 85 __func__, bios[0], bios[1]); 86 } 87 drm_core_ioremapfree(&bios_map, rdev->ddev); 88 return false; 89 } 90 rdev->bios = kmalloc(size, M_DRM, M_WAITOK); 91 if (rdev->bios == NULL) { 92 drm_core_ioremapfree(&bios_map, rdev->ddev); 93 return false; 94 } 95 memcpy_fromio(rdev->bios, bios, size); 96 drm_core_ioremapfree(&bios_map, rdev->ddev); 97 return true; 98 } 99 100 static bool radeon_read_bios(struct radeon_device *rdev) 101 { 102 device_t vga_dev; 103 uint8_t __iomem *bios; 104 size_t size; 105 106 DRM_INFO("%s: ===> Try PCI Expansion ROM...\n", __func__); 107 108 vga_dev = device_get_parent(rdev->dev); 109 rdev->bios = NULL; 110 /* XXX: some cards may return 0 for rom size? ddx has a workaround */ 111 bios = vga_pci_map_bios(vga_dev, &size); 112 if (!bios) { 113 return false; 114 } 115 DRM_INFO("%s: Map address: %p (%zu bytes)\n", __func__, bios, size); 116 117 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 118 if (size == 0) { 119 DRM_INFO("%s: Incorrect BIOS size\n", __func__); 120 } else { 121 DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n", 122 __func__, bios[0], bios[1]); 123 } 124 vga_pci_unmap_bios(vga_dev, bios); 125 return false; 126 } 127 rdev->bios = kmalloc(size, M_DRM, M_WAITOK); 128 memcpy(rdev->bios, bios, size); 129 vga_pci_unmap_bios(vga_dev, bios); 130 return true; 131 } 132 133 static bool radeon_read_platform_bios(struct radeon_device *rdev) 134 { 135 uint8_t __iomem *bios; 136 size_t size; 137 138 rdev->bios = NULL; 139 140 #if 0 141 // XXX: FIXME 142 bios = pci_platform_rom(rdev->pdev, &size); 143 #else 144 size = 0; 145 bios = NULL; 146 #endif 147 if (!bios) { 148 return false; 149 } 150 151 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 152 return false; 153 } 154 rdev->bios = kmalloc(size, M_DRM, M_WAITOK); 155 if (rdev->bios == NULL) { 156 return false; 157 } 158 memcpy(rdev->bios, bios, size); 159 return true; 160 } 161 162 /* ATRM is used to get the BIOS on the discrete cards in 163 * dual-gpu systems. 164 */ 165 /* retrieve the ROM in 4k blocks */ 166 #define ATRM_BIOS_PAGE 4096 167 /** 168 * radeon_atrm_call - fetch a chunk of the vbios 169 * 170 * @atrm_handle: acpi ATRM handle 171 * @bios: vbios image pointer 172 * @offset: offset of vbios image data to fetch 173 * @len: length of vbios image data to fetch 174 * 175 * Executes ATRM to fetch a chunk of the discrete 176 * vbios image on PX systems (all asics). 177 * Returns the length of the buffer fetched. 178 */ 179 static int radeon_atrm_call(ACPI_HANDLE atrm_handle, uint8_t *bios, 180 int offset, int len) 181 { 182 ACPI_STATUS status; 183 ACPI_OBJECT atrm_arg_elements[2], *obj; 184 ACPI_OBJECT_LIST atrm_arg; 185 ACPI_BUFFER buffer = { ACPI_ALLOCATE_BUFFER, NULL}; 186 187 atrm_arg.Count = 2; 188 atrm_arg.Pointer = &atrm_arg_elements[0]; 189 190 atrm_arg_elements[0].Type = ACPI_TYPE_INTEGER; 191 atrm_arg_elements[0].Integer.Value = offset; 192 193 atrm_arg_elements[1].Type = ACPI_TYPE_INTEGER; 194 atrm_arg_elements[1].Integer.Value = len; 195 196 status = AcpiEvaluateObject(atrm_handle, NULL, &atrm_arg, &buffer); 197 if (ACPI_FAILURE(status)) { 198 DRM_ERROR("failed to evaluate ATRM got %s\n", AcpiFormatException(status)); 199 return -ENODEV; 200 } 201 202 obj = (ACPI_OBJECT *)buffer.Pointer; 203 memcpy(bios+offset, obj->Buffer.Pointer, obj->Buffer.Length); 204 len = obj->Buffer.Length; 205 AcpiOsFree(buffer.Pointer); 206 return len; 207 } 208 209 static bool radeon_atrm_get_bios(struct radeon_device *rdev) 210 { 211 int ret; 212 int size = 256 * 1024; 213 int i; 214 device_t dev; 215 ACPI_HANDLE dhandle, atrm_handle; 216 ACPI_STATUS status; 217 bool found = false; 218 219 DRM_INFO("%s: ===> Try ATRM...\n", __func__); 220 221 /* ATRM is for the discrete card only */ 222 if (rdev->flags & RADEON_IS_IGP) { 223 DRM_INFO("%s: IGP card detected, skipping this method...\n", 224 __func__); 225 return false; 226 } 227 228 #ifdef DUMBBELL_WIP 229 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 230 #endif /* DUMBBELL_WIP */ 231 if ((dev = pci_find_class(PCIC_DISPLAY, PCIS_DISPLAY_VGA)) != NULL) { 232 DRM_INFO("%s: pci_find_class() found: %d:%d:%d:%d, vendor=%04x, device=%04x\n", 233 __func__, 234 pci_get_domain(dev), 235 pci_get_bus(dev), 236 pci_get_slot(dev), 237 pci_get_function(dev), 238 pci_get_vendor(dev), 239 pci_get_device(dev)); 240 DRM_INFO("%s: Get ACPI device handle\n", __func__); 241 dhandle = acpi_get_handle(dev); 242 #ifdef DUMBBELL_WIP 243 if (!dhandle) 244 continue; 245 #endif /* DUMBBELL_WIP */ 246 if (!dhandle) 247 return false; 248 249 DRM_INFO("%s: Get ACPI handle for \"ATRM\"\n", __func__); 250 status = AcpiGetHandle(dhandle, "ATRM", &atrm_handle); 251 if (!ACPI_FAILURE(status)) { 252 found = true; 253 #ifdef DUMBBELL_WIP 254 break; 255 #endif /* DUMBBELL_WIP */ 256 } else { 257 DRM_INFO("%s: Failed to get \"ATRM\" handle: %s\n", 258 __func__, AcpiFormatException(status)); 259 } 260 } 261 262 if (!found) 263 return false; 264 265 rdev->bios = kmalloc(size, M_DRM, M_WAITOK); 266 if (!rdev->bios) { 267 DRM_ERROR("Unable to allocate bios\n"); 268 return false; 269 } 270 271 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { 272 DRM_INFO("%s: Call radeon_atrm_call()\n", __func__); 273 ret = radeon_atrm_call(atrm_handle, 274 rdev->bios, 275 (i * ATRM_BIOS_PAGE), 276 ATRM_BIOS_PAGE); 277 if (ret < ATRM_BIOS_PAGE) 278 break; 279 } 280 281 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 282 if (i == 0) { 283 DRM_INFO("%s: Incorrect BIOS size\n", __func__); 284 } else { 285 DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n", 286 __func__, rdev->bios[0], rdev->bios[1]); 287 } 288 drm_free(rdev->bios, M_DRM); 289 return false; 290 } 291 return true; 292 } 293 294 static bool ni_read_disabled_bios(struct radeon_device *rdev) 295 { 296 u32 bus_cntl; 297 u32 d1vga_control; 298 u32 d2vga_control; 299 u32 vga_render_control; 300 u32 rom_cntl; 301 bool r; 302 303 DRM_INFO("%s: ===> Try disabled BIOS (ni)...\n", __func__); 304 305 bus_cntl = RREG32(R600_BUS_CNTL); 306 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 307 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 308 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 309 rom_cntl = RREG32(R600_ROM_CNTL); 310 311 /* enable the rom */ 312 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 313 /* Disable VGA mode */ 314 WREG32(AVIVO_D1VGA_CONTROL, 315 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 316 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 317 WREG32(AVIVO_D2VGA_CONTROL, 318 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 319 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 320 WREG32(AVIVO_VGA_RENDER_CONTROL, 321 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 322 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 323 324 r = radeon_read_bios(rdev); 325 326 /* restore regs */ 327 WREG32(R600_BUS_CNTL, bus_cntl); 328 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 329 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 330 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 331 WREG32(R600_ROM_CNTL, rom_cntl); 332 return r; 333 } 334 335 static bool r700_read_disabled_bios(struct radeon_device *rdev) 336 { 337 uint32_t viph_control; 338 uint32_t bus_cntl; 339 uint32_t d1vga_control; 340 uint32_t d2vga_control; 341 uint32_t vga_render_control; 342 uint32_t rom_cntl; 343 uint32_t cg_spll_func_cntl = 0; 344 uint32_t cg_spll_status; 345 bool r; 346 347 DRM_INFO("%s: ===> Try disabled BIOS (r700)...\n", __func__); 348 349 viph_control = RREG32(RADEON_VIPH_CONTROL); 350 bus_cntl = RREG32(R600_BUS_CNTL); 351 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 352 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 353 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 354 rom_cntl = RREG32(R600_ROM_CNTL); 355 356 /* disable VIP */ 357 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 358 /* enable the rom */ 359 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 360 /* Disable VGA mode */ 361 WREG32(AVIVO_D1VGA_CONTROL, 362 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 363 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 364 WREG32(AVIVO_D2VGA_CONTROL, 365 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 366 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 367 WREG32(AVIVO_VGA_RENDER_CONTROL, 368 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 369 370 if (rdev->family == CHIP_RV730) { 371 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); 372 373 /* enable bypass mode */ 374 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | 375 R600_SPLL_BYPASS_EN)); 376 377 /* wait for SPLL_CHG_STATUS to change to 1 */ 378 cg_spll_status = 0; 379 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 380 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 381 382 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); 383 } else 384 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 385 386 r = radeon_read_bios(rdev); 387 388 /* restore regs */ 389 if (rdev->family == CHIP_RV730) { 390 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); 391 392 /* wait for SPLL_CHG_STATUS to change to 1 */ 393 cg_spll_status = 0; 394 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 395 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 396 } 397 WREG32(RADEON_VIPH_CONTROL, viph_control); 398 WREG32(R600_BUS_CNTL, bus_cntl); 399 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 400 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 401 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 402 WREG32(R600_ROM_CNTL, rom_cntl); 403 return r; 404 } 405 406 static bool r600_read_disabled_bios(struct radeon_device *rdev) 407 { 408 uint32_t viph_control; 409 uint32_t bus_cntl; 410 uint32_t d1vga_control; 411 uint32_t d2vga_control; 412 uint32_t vga_render_control; 413 uint32_t rom_cntl; 414 uint32_t general_pwrmgt; 415 uint32_t low_vid_lower_gpio_cntl; 416 uint32_t medium_vid_lower_gpio_cntl; 417 uint32_t high_vid_lower_gpio_cntl; 418 uint32_t ctxsw_vid_lower_gpio_cntl; 419 uint32_t lower_gpio_enable; 420 bool r; 421 422 DRM_INFO("%s: ===> Try disabled BIOS (r600)...\n", __func__); 423 424 viph_control = RREG32(RADEON_VIPH_CONTROL); 425 bus_cntl = RREG32(R600_BUS_CNTL); 426 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 427 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 428 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 429 rom_cntl = RREG32(R600_ROM_CNTL); 430 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); 431 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); 432 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); 433 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); 434 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); 435 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); 436 437 /* disable VIP */ 438 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 439 /* enable the rom */ 440 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 441 /* Disable VGA mode */ 442 WREG32(AVIVO_D1VGA_CONTROL, 443 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 444 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 445 WREG32(AVIVO_D2VGA_CONTROL, 446 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 447 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 448 WREG32(AVIVO_VGA_RENDER_CONTROL, 449 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 450 451 WREG32(R600_ROM_CNTL, 452 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | 453 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | 454 R600_SCK_OVERWRITE)); 455 456 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 457 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, 458 (low_vid_lower_gpio_cntl & ~0x400)); 459 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, 460 (medium_vid_lower_gpio_cntl & ~0x400)); 461 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, 462 (high_vid_lower_gpio_cntl & ~0x400)); 463 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, 464 (ctxsw_vid_lower_gpio_cntl & ~0x400)); 465 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); 466 467 r = radeon_read_bios(rdev); 468 469 /* restore regs */ 470 WREG32(RADEON_VIPH_CONTROL, viph_control); 471 WREG32(R600_BUS_CNTL, bus_cntl); 472 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 473 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 474 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 475 WREG32(R600_ROM_CNTL, rom_cntl); 476 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); 477 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); 478 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); 479 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); 480 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); 481 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 482 return r; 483 } 484 485 static bool avivo_read_disabled_bios(struct radeon_device *rdev) 486 { 487 uint32_t seprom_cntl1; 488 uint32_t viph_control; 489 uint32_t bus_cntl; 490 uint32_t d1vga_control; 491 uint32_t d2vga_control; 492 uint32_t vga_render_control; 493 uint32_t gpiopad_a; 494 uint32_t gpiopad_en; 495 uint32_t gpiopad_mask; 496 bool r; 497 498 DRM_INFO("%s: ===> Try disabled BIOS (avivo)...\n", __func__); 499 500 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 501 viph_control = RREG32(RADEON_VIPH_CONTROL); 502 bus_cntl = RREG32(RV370_BUS_CNTL); 503 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 504 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 505 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 506 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 507 gpiopad_en = RREG32(RADEON_GPIOPAD_EN); 508 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); 509 510 WREG32(RADEON_SEPROM_CNTL1, 511 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 512 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 513 WREG32(RADEON_GPIOPAD_A, 0); 514 WREG32(RADEON_GPIOPAD_EN, 0); 515 WREG32(RADEON_GPIOPAD_MASK, 0); 516 517 /* disable VIP */ 518 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 519 520 /* enable the rom */ 521 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 522 523 /* Disable VGA mode */ 524 WREG32(AVIVO_D1VGA_CONTROL, 525 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 526 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 527 WREG32(AVIVO_D2VGA_CONTROL, 528 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 529 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 530 WREG32(AVIVO_VGA_RENDER_CONTROL, 531 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 532 533 r = radeon_read_bios(rdev); 534 535 /* restore regs */ 536 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 537 WREG32(RADEON_VIPH_CONTROL, viph_control); 538 WREG32(RV370_BUS_CNTL, bus_cntl); 539 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 540 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 541 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 542 WREG32(RADEON_GPIOPAD_A, gpiopad_a); 543 WREG32(RADEON_GPIOPAD_EN, gpiopad_en); 544 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); 545 return r; 546 } 547 548 static bool legacy_read_disabled_bios(struct radeon_device *rdev) 549 { 550 uint32_t seprom_cntl1; 551 uint32_t viph_control; 552 uint32_t bus_cntl; 553 uint32_t crtc_gen_cntl; 554 uint32_t crtc2_gen_cntl; 555 uint32_t crtc_ext_cntl; 556 uint32_t fp2_gen_cntl; 557 bool r; 558 559 DRM_INFO("%s: ===> Try disabled BIOS (legacy)...\n", __func__); 560 561 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 562 viph_control = RREG32(RADEON_VIPH_CONTROL); 563 if (rdev->flags & RADEON_IS_PCIE) 564 bus_cntl = RREG32(RV370_BUS_CNTL); 565 else 566 bus_cntl = RREG32(RADEON_BUS_CNTL); 567 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 568 crtc2_gen_cntl = 0; 569 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 570 fp2_gen_cntl = 0; 571 572 #define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 573 574 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { 575 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 576 } 577 578 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 579 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 580 } 581 582 WREG32(RADEON_SEPROM_CNTL1, 583 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 584 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 585 586 /* disable VIP */ 587 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 588 589 /* enable the rom */ 590 if (rdev->flags & RADEON_IS_PCIE) 591 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 592 else 593 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 594 595 /* Turn off mem requests and CRTC for both controllers */ 596 WREG32(RADEON_CRTC_GEN_CNTL, 597 ((crtc_gen_cntl & ~RADEON_CRTC_EN) | 598 (RADEON_CRTC_DISP_REQ_EN_B | 599 RADEON_CRTC_EXT_DISP_EN))); 600 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 601 WREG32(RADEON_CRTC2_GEN_CNTL, 602 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | 603 RADEON_CRTC2_DISP_REQ_EN_B)); 604 } 605 /* Turn off CRTC */ 606 WREG32(RADEON_CRTC_EXT_CNTL, 607 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | 608 (RADEON_CRTC_SYNC_TRISTAT | 609 RADEON_CRTC_DISPLAY_DIS))); 610 611 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { 612 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); 613 } 614 615 r = radeon_read_bios(rdev); 616 617 /* restore regs */ 618 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 619 WREG32(RADEON_VIPH_CONTROL, viph_control); 620 if (rdev->flags & RADEON_IS_PCIE) 621 WREG32(RV370_BUS_CNTL, bus_cntl); 622 else 623 WREG32(RADEON_BUS_CNTL, bus_cntl); 624 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 625 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 626 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 627 } 628 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 629 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { 630 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 631 } 632 return r; 633 } 634 635 static bool radeon_read_disabled_bios(struct radeon_device *rdev) 636 { 637 if (rdev->flags & RADEON_IS_IGP) 638 return igp_read_bios_from_vram(rdev); 639 else if (rdev->family >= CHIP_BARTS) 640 return ni_read_disabled_bios(rdev); 641 else if (rdev->family >= CHIP_RV770) 642 return r700_read_disabled_bios(rdev); 643 else if (rdev->family >= CHIP_R600) 644 return r600_read_disabled_bios(rdev); 645 else if (rdev->family >= CHIP_RS600) 646 return avivo_read_disabled_bios(rdev); 647 else 648 return legacy_read_disabled_bios(rdev); 649 } 650 651 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 652 { 653 bool ret = false; 654 ACPI_TABLE_HEADER *hdr; 655 ACPI_SIZE tbl_size; 656 UEFI_ACPI_VFCT *vfct; 657 GOP_VBIOS_CONTENT *vbios; 658 VFCT_IMAGE_HEADER *vhdr; 659 ACPI_STATUS status; 660 661 DRM_INFO("%s: ===> Try VFCT...\n", __func__); 662 663 DRM_INFO("%s: Get \"VFCT\" ACPI table\n", __func__); 664 status = AcpiGetTable("VFCT", 1, &hdr); 665 if (!ACPI_SUCCESS(status)) { 666 DRM_INFO("%s: Failed to get \"VFCT\" table: %s\n", 667 __func__, AcpiFormatException(status)); 668 return false; 669 } 670 tbl_size = hdr->Length; 671 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { 672 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); 673 goto out_unmap; 674 } 675 676 vfct = (UEFI_ACPI_VFCT *)hdr; 677 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) { 678 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); 679 goto out_unmap; 680 } 681 682 vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset); 683 vhdr = &vbios->VbiosHeader; 684 DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n", 685 vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction, 686 vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength); 687 688 if (vhdr->PCIBus != rdev->ddev->pci_bus || 689 vhdr->PCIDevice != rdev->ddev->pci_slot || 690 vhdr->PCIFunction != rdev->ddev->pci_func || 691 vhdr->VendorID != rdev->ddev->pci_vendor || 692 vhdr->DeviceID != rdev->ddev->pci_device) { 693 DRM_INFO("ACPI VFCT table is not for this card\n"); 694 goto out_unmap; 695 } 696 697 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) { 698 DRM_ERROR("ACPI VFCT image truncated\n"); 699 goto out_unmap; 700 } 701 702 rdev->bios = kmalloc(vhdr->ImageLength, M_DRM, M_WAITOK); 703 memcpy(rdev->bios, &vbios->VbiosContent, vhdr->ImageLength); 704 ret = !!rdev->bios; 705 706 out_unmap: 707 return ret; 708 } 709 710 bool radeon_get_bios(struct radeon_device *rdev) 711 { 712 bool r; 713 uint16_t tmp; 714 715 r = radeon_atrm_get_bios(rdev); 716 if (r == false) 717 r = radeon_acpi_vfct_bios(rdev); 718 if (r == false) 719 r = igp_read_bios_from_vram(rdev); 720 if (r == false) 721 r = radeon_read_bios(rdev); 722 if (r == false) { 723 r = radeon_read_disabled_bios(rdev); 724 } 725 if (r == false) { 726 r = radeon_read_platform_bios(rdev); 727 } 728 if (r == false || rdev->bios == NULL) { 729 DRM_ERROR("Unable to locate a BIOS ROM\n"); 730 rdev->bios = NULL; 731 return false; 732 } 733 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 734 DRM_ERROR("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); 735 goto free_bios; 736 } 737 738 tmp = RBIOS16(0x18); 739 if (RBIOS8(tmp + 0x14) != 0x0) { 740 DRM_INFO("Not an x86 BIOS ROM, not using.\n"); 741 goto free_bios; 742 } 743 744 rdev->bios_header_start = RBIOS16(0x48); 745 if (!rdev->bios_header_start) { 746 goto free_bios; 747 } 748 tmp = rdev->bios_header_start + 4; 749 if (!memcmp(rdev->bios + tmp, "ATOM", 4) || 750 !memcmp(rdev->bios + tmp, "MOTA", 4)) { 751 rdev->is_atom_bios = true; 752 } else { 753 rdev->is_atom_bios = false; 754 } 755 756 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); 757 return true; 758 free_bios: 759 drm_free(rdev->bios, M_DRM); 760 rdev->bios = NULL; 761 return false; 762 } 763