1 /* 2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario 3 * Copyright 2007-8 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * 27 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_combios.c 254885 2013-08-25 19:37:15Z dumbbell $ 28 */ 29 30 #include <drm/drmP.h> 31 #include <uapi_drm/radeon_drm.h> 32 #include "radeon.h" 33 #include "atom.h" 34 35 #ifdef CONFIG_PPC_PMAC 36 /* not sure which of these are needed */ 37 #include <asm/machdep.h> 38 #include <asm/pmac_feature.h> 39 #include <asm/prom.h> 40 #include <asm/pci-bridge.h> 41 #endif /* CONFIG_PPC_PMAC */ 42 43 /* old legacy ATI BIOS routines */ 44 45 /* COMBIOS table offsets */ 46 enum radeon_combios_table_offset { 47 /* absolute offset tables */ 48 COMBIOS_ASIC_INIT_1_TABLE, 49 COMBIOS_BIOS_SUPPORT_TABLE, 50 COMBIOS_DAC_PROGRAMMING_TABLE, 51 COMBIOS_MAX_COLOR_DEPTH_TABLE, 52 COMBIOS_CRTC_INFO_TABLE, 53 COMBIOS_PLL_INFO_TABLE, 54 COMBIOS_TV_INFO_TABLE, 55 COMBIOS_DFP_INFO_TABLE, 56 COMBIOS_HW_CONFIG_INFO_TABLE, 57 COMBIOS_MULTIMEDIA_INFO_TABLE, 58 COMBIOS_TV_STD_PATCH_TABLE, 59 COMBIOS_LCD_INFO_TABLE, 60 COMBIOS_MOBILE_INFO_TABLE, 61 COMBIOS_PLL_INIT_TABLE, 62 COMBIOS_MEM_CONFIG_TABLE, 63 COMBIOS_SAVE_MASK_TABLE, 64 COMBIOS_HARDCODED_EDID_TABLE, 65 COMBIOS_ASIC_INIT_2_TABLE, 66 COMBIOS_CONNECTOR_INFO_TABLE, 67 COMBIOS_DYN_CLK_1_TABLE, 68 COMBIOS_RESERVED_MEM_TABLE, 69 COMBIOS_EXT_TMDS_INFO_TABLE, 70 COMBIOS_MEM_CLK_INFO_TABLE, 71 COMBIOS_EXT_DAC_INFO_TABLE, 72 COMBIOS_MISC_INFO_TABLE, 73 COMBIOS_CRT_INFO_TABLE, 74 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE, 75 COMBIOS_COMPONENT_VIDEO_INFO_TABLE, 76 COMBIOS_FAN_SPEED_INFO_TABLE, 77 COMBIOS_OVERDRIVE_INFO_TABLE, 78 COMBIOS_OEM_INFO_TABLE, 79 COMBIOS_DYN_CLK_2_TABLE, 80 COMBIOS_POWER_CONNECTOR_INFO_TABLE, 81 COMBIOS_I2C_INFO_TABLE, 82 /* relative offset tables */ 83 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */ 84 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */ 85 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */ 86 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */ 87 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */ 88 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */ 89 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */ 90 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */ 91 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */ 92 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */ 93 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */ 94 }; 95 96 enum radeon_combios_ddc { 97 DDC_NONE_DETECTED, 98 DDC_MONID, 99 DDC_DVI, 100 DDC_VGA, 101 DDC_CRT2, 102 DDC_LCD, 103 DDC_GPIO, 104 }; 105 106 enum radeon_combios_connector { 107 CONNECTOR_NONE_LEGACY, 108 CONNECTOR_PROPRIETARY_LEGACY, 109 CONNECTOR_CRT_LEGACY, 110 CONNECTOR_DVI_I_LEGACY, 111 CONNECTOR_DVI_D_LEGACY, 112 CONNECTOR_CTV_LEGACY, 113 CONNECTOR_STV_LEGACY, 114 CONNECTOR_UNSUPPORTED_LEGACY 115 }; 116 117 const int legacy_connector_convert[] = { 118 DRM_MODE_CONNECTOR_Unknown, 119 DRM_MODE_CONNECTOR_DVID, 120 DRM_MODE_CONNECTOR_VGA, 121 DRM_MODE_CONNECTOR_DVII, 122 DRM_MODE_CONNECTOR_DVID, 123 DRM_MODE_CONNECTOR_Composite, 124 DRM_MODE_CONNECTOR_SVIDEO, 125 DRM_MODE_CONNECTOR_Unknown, 126 }; 127 128 static uint16_t combios_get_table_offset(struct drm_device *dev, 129 enum radeon_combios_table_offset table) 130 { 131 struct radeon_device *rdev = dev->dev_private; 132 int rev; 133 uint16_t offset = 0, check_offset; 134 135 if (!rdev->bios) 136 return 0; 137 138 switch (table) { 139 /* absolute offset tables */ 140 case COMBIOS_ASIC_INIT_1_TABLE: 141 check_offset = RBIOS16(rdev->bios_header_start + 0xc); 142 if (check_offset) 143 offset = check_offset; 144 break; 145 case COMBIOS_BIOS_SUPPORT_TABLE: 146 check_offset = RBIOS16(rdev->bios_header_start + 0x14); 147 if (check_offset) 148 offset = check_offset; 149 break; 150 case COMBIOS_DAC_PROGRAMMING_TABLE: 151 check_offset = RBIOS16(rdev->bios_header_start + 0x2a); 152 if (check_offset) 153 offset = check_offset; 154 break; 155 case COMBIOS_MAX_COLOR_DEPTH_TABLE: 156 check_offset = RBIOS16(rdev->bios_header_start + 0x2c); 157 if (check_offset) 158 offset = check_offset; 159 break; 160 case COMBIOS_CRTC_INFO_TABLE: 161 check_offset = RBIOS16(rdev->bios_header_start + 0x2e); 162 if (check_offset) 163 offset = check_offset; 164 break; 165 case COMBIOS_PLL_INFO_TABLE: 166 check_offset = RBIOS16(rdev->bios_header_start + 0x30); 167 if (check_offset) 168 offset = check_offset; 169 break; 170 case COMBIOS_TV_INFO_TABLE: 171 check_offset = RBIOS16(rdev->bios_header_start + 0x32); 172 if (check_offset) 173 offset = check_offset; 174 break; 175 case COMBIOS_DFP_INFO_TABLE: 176 check_offset = RBIOS16(rdev->bios_header_start + 0x34); 177 if (check_offset) 178 offset = check_offset; 179 break; 180 case COMBIOS_HW_CONFIG_INFO_TABLE: 181 check_offset = RBIOS16(rdev->bios_header_start + 0x36); 182 if (check_offset) 183 offset = check_offset; 184 break; 185 case COMBIOS_MULTIMEDIA_INFO_TABLE: 186 check_offset = RBIOS16(rdev->bios_header_start + 0x38); 187 if (check_offset) 188 offset = check_offset; 189 break; 190 case COMBIOS_TV_STD_PATCH_TABLE: 191 check_offset = RBIOS16(rdev->bios_header_start + 0x3e); 192 if (check_offset) 193 offset = check_offset; 194 break; 195 case COMBIOS_LCD_INFO_TABLE: 196 check_offset = RBIOS16(rdev->bios_header_start + 0x40); 197 if (check_offset) 198 offset = check_offset; 199 break; 200 case COMBIOS_MOBILE_INFO_TABLE: 201 check_offset = RBIOS16(rdev->bios_header_start + 0x42); 202 if (check_offset) 203 offset = check_offset; 204 break; 205 case COMBIOS_PLL_INIT_TABLE: 206 check_offset = RBIOS16(rdev->bios_header_start + 0x46); 207 if (check_offset) 208 offset = check_offset; 209 break; 210 case COMBIOS_MEM_CONFIG_TABLE: 211 check_offset = RBIOS16(rdev->bios_header_start + 0x48); 212 if (check_offset) 213 offset = check_offset; 214 break; 215 case COMBIOS_SAVE_MASK_TABLE: 216 check_offset = RBIOS16(rdev->bios_header_start + 0x4a); 217 if (check_offset) 218 offset = check_offset; 219 break; 220 case COMBIOS_HARDCODED_EDID_TABLE: 221 check_offset = RBIOS16(rdev->bios_header_start + 0x4c); 222 if (check_offset) 223 offset = check_offset; 224 break; 225 case COMBIOS_ASIC_INIT_2_TABLE: 226 check_offset = RBIOS16(rdev->bios_header_start + 0x4e); 227 if (check_offset) 228 offset = check_offset; 229 break; 230 case COMBIOS_CONNECTOR_INFO_TABLE: 231 check_offset = RBIOS16(rdev->bios_header_start + 0x50); 232 if (check_offset) 233 offset = check_offset; 234 break; 235 case COMBIOS_DYN_CLK_1_TABLE: 236 check_offset = RBIOS16(rdev->bios_header_start + 0x52); 237 if (check_offset) 238 offset = check_offset; 239 break; 240 case COMBIOS_RESERVED_MEM_TABLE: 241 check_offset = RBIOS16(rdev->bios_header_start + 0x54); 242 if (check_offset) 243 offset = check_offset; 244 break; 245 case COMBIOS_EXT_TMDS_INFO_TABLE: 246 check_offset = RBIOS16(rdev->bios_header_start + 0x58); 247 if (check_offset) 248 offset = check_offset; 249 break; 250 case COMBIOS_MEM_CLK_INFO_TABLE: 251 check_offset = RBIOS16(rdev->bios_header_start + 0x5a); 252 if (check_offset) 253 offset = check_offset; 254 break; 255 case COMBIOS_EXT_DAC_INFO_TABLE: 256 check_offset = RBIOS16(rdev->bios_header_start + 0x5c); 257 if (check_offset) 258 offset = check_offset; 259 break; 260 case COMBIOS_MISC_INFO_TABLE: 261 check_offset = RBIOS16(rdev->bios_header_start + 0x5e); 262 if (check_offset) 263 offset = check_offset; 264 break; 265 case COMBIOS_CRT_INFO_TABLE: 266 check_offset = RBIOS16(rdev->bios_header_start + 0x60); 267 if (check_offset) 268 offset = check_offset; 269 break; 270 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE: 271 check_offset = RBIOS16(rdev->bios_header_start + 0x62); 272 if (check_offset) 273 offset = check_offset; 274 break; 275 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE: 276 check_offset = RBIOS16(rdev->bios_header_start + 0x64); 277 if (check_offset) 278 offset = check_offset; 279 break; 280 case COMBIOS_FAN_SPEED_INFO_TABLE: 281 check_offset = RBIOS16(rdev->bios_header_start + 0x66); 282 if (check_offset) 283 offset = check_offset; 284 break; 285 case COMBIOS_OVERDRIVE_INFO_TABLE: 286 check_offset = RBIOS16(rdev->bios_header_start + 0x68); 287 if (check_offset) 288 offset = check_offset; 289 break; 290 case COMBIOS_OEM_INFO_TABLE: 291 check_offset = RBIOS16(rdev->bios_header_start + 0x6a); 292 if (check_offset) 293 offset = check_offset; 294 break; 295 case COMBIOS_DYN_CLK_2_TABLE: 296 check_offset = RBIOS16(rdev->bios_header_start + 0x6c); 297 if (check_offset) 298 offset = check_offset; 299 break; 300 case COMBIOS_POWER_CONNECTOR_INFO_TABLE: 301 check_offset = RBIOS16(rdev->bios_header_start + 0x6e); 302 if (check_offset) 303 offset = check_offset; 304 break; 305 case COMBIOS_I2C_INFO_TABLE: 306 check_offset = RBIOS16(rdev->bios_header_start + 0x70); 307 if (check_offset) 308 offset = check_offset; 309 break; 310 /* relative offset tables */ 311 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */ 312 check_offset = 313 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 314 if (check_offset) { 315 rev = RBIOS8(check_offset); 316 if (rev > 0) { 317 check_offset = RBIOS16(check_offset + 0x3); 318 if (check_offset) 319 offset = check_offset; 320 } 321 } 322 break; 323 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */ 324 check_offset = 325 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 326 if (check_offset) { 327 rev = RBIOS8(check_offset); 328 if (rev > 0) { 329 check_offset = RBIOS16(check_offset + 0x5); 330 if (check_offset) 331 offset = check_offset; 332 } 333 } 334 break; 335 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */ 336 check_offset = 337 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 338 if (check_offset) { 339 rev = RBIOS8(check_offset); 340 if (rev > 0) { 341 check_offset = RBIOS16(check_offset + 0x7); 342 if (check_offset) 343 offset = check_offset; 344 } 345 } 346 break; 347 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */ 348 check_offset = 349 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 350 if (check_offset) { 351 rev = RBIOS8(check_offset); 352 if (rev == 2) { 353 check_offset = RBIOS16(check_offset + 0x9); 354 if (check_offset) 355 offset = check_offset; 356 } 357 } 358 break; 359 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */ 360 check_offset = 361 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 362 if (check_offset) { 363 while (RBIOS8(check_offset++)); 364 check_offset += 2; 365 if (check_offset) 366 offset = check_offset; 367 } 368 break; 369 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */ 370 check_offset = 371 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 372 if (check_offset) { 373 check_offset = RBIOS16(check_offset + 0x11); 374 if (check_offset) 375 offset = check_offset; 376 } 377 break; 378 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */ 379 check_offset = 380 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 381 if (check_offset) { 382 check_offset = RBIOS16(check_offset + 0x13); 383 if (check_offset) 384 offset = check_offset; 385 } 386 break; 387 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */ 388 check_offset = 389 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 390 if (check_offset) { 391 check_offset = RBIOS16(check_offset + 0x15); 392 if (check_offset) 393 offset = check_offset; 394 } 395 break; 396 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */ 397 check_offset = 398 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 399 if (check_offset) { 400 check_offset = RBIOS16(check_offset + 0x17); 401 if (check_offset) 402 offset = check_offset; 403 } 404 break; 405 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */ 406 check_offset = 407 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 408 if (check_offset) { 409 check_offset = RBIOS16(check_offset + 0x2); 410 if (check_offset) 411 offset = check_offset; 412 } 413 break; 414 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */ 415 check_offset = 416 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 417 if (check_offset) { 418 check_offset = RBIOS16(check_offset + 0x4); 419 if (check_offset) 420 offset = check_offset; 421 } 422 break; 423 default: 424 break; 425 } 426 427 return offset; 428 429 } 430 431 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev) 432 { 433 int edid_info, size; 434 struct edid *edid; 435 unsigned char *raw; 436 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE); 437 if (!edid_info) 438 return false; 439 440 raw = rdev->bios + edid_info; 441 size = EDID_LENGTH * (raw[0x7e] + 1); 442 edid = kmalloc(size, DRM_MEM_KMS, M_WAITOK); 443 if (edid == NULL) 444 return false; 445 446 memcpy((unsigned char *)edid, raw, size); 447 448 if (!drm_edid_is_valid(edid)) { 449 drm_free(edid, DRM_MEM_KMS); 450 return false; 451 } 452 453 rdev->mode_info.bios_hardcoded_edid = edid; 454 rdev->mode_info.bios_hardcoded_edid_size = size; 455 return true; 456 } 457 458 /* this is used for atom LCDs as well */ 459 struct edid * 460 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev) 461 { 462 struct edid *edid; 463 464 if (rdev->mode_info.bios_hardcoded_edid) { 465 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, 466 DRM_MEM_KMS, M_WAITOK); 467 if (edid) { 468 memcpy((unsigned char *)edid, 469 (unsigned char *)rdev->mode_info.bios_hardcoded_edid, 470 rdev->mode_info.bios_hardcoded_edid_size); 471 return edid; 472 } 473 } 474 return NULL; 475 } 476 477 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev, 478 enum radeon_combios_ddc ddc, 479 u32 clk_mask, 480 u32 data_mask) 481 { 482 struct radeon_i2c_bus_rec i2c; 483 int ddc_line = 0; 484 485 /* ddc id = mask reg 486 * DDC_NONE_DETECTED = none 487 * DDC_DVI = RADEON_GPIO_DVI_DDC 488 * DDC_VGA = RADEON_GPIO_VGA_DDC 489 * DDC_LCD = RADEON_GPIOPAD_MASK 490 * DDC_GPIO = RADEON_MDGPIO_MASK 491 * r1xx 492 * DDC_MONID = RADEON_GPIO_MONID 493 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC 494 * r200 495 * DDC_MONID = RADEON_GPIO_MONID 496 * DDC_CRT2 = RADEON_GPIO_DVI_DDC 497 * r300/r350 498 * DDC_MONID = RADEON_GPIO_DVI_DDC 499 * DDC_CRT2 = RADEON_GPIO_DVI_DDC 500 * rv2xx/rv3xx 501 * DDC_MONID = RADEON_GPIO_MONID 502 * DDC_CRT2 = RADEON_GPIO_MONID 503 * rs3xx/rs4xx 504 * DDC_MONID = RADEON_GPIOPAD_MASK 505 * DDC_CRT2 = RADEON_GPIO_MONID 506 */ 507 switch (ddc) { 508 case DDC_NONE_DETECTED: 509 default: 510 ddc_line = 0; 511 break; 512 case DDC_DVI: 513 ddc_line = RADEON_GPIO_DVI_DDC; 514 break; 515 case DDC_VGA: 516 ddc_line = RADEON_GPIO_VGA_DDC; 517 break; 518 case DDC_LCD: 519 ddc_line = RADEON_GPIOPAD_MASK; 520 break; 521 case DDC_GPIO: 522 ddc_line = RADEON_MDGPIO_MASK; 523 break; 524 case DDC_MONID: 525 if (rdev->family == CHIP_RS300 || 526 rdev->family == CHIP_RS400 || 527 rdev->family == CHIP_RS480) 528 ddc_line = RADEON_GPIOPAD_MASK; 529 else if (rdev->family == CHIP_R300 || 530 rdev->family == CHIP_R350) { 531 ddc_line = RADEON_GPIO_DVI_DDC; 532 ddc = DDC_DVI; 533 } else 534 ddc_line = RADEON_GPIO_MONID; 535 break; 536 case DDC_CRT2: 537 if (rdev->family == CHIP_R200 || 538 rdev->family == CHIP_R300 || 539 rdev->family == CHIP_R350) { 540 ddc_line = RADEON_GPIO_DVI_DDC; 541 ddc = DDC_DVI; 542 } else if (rdev->family == CHIP_RS300 || 543 rdev->family == CHIP_RS400 || 544 rdev->family == CHIP_RS480) 545 ddc_line = RADEON_GPIO_MONID; 546 else if (rdev->family >= CHIP_RV350) { 547 ddc_line = RADEON_GPIO_MONID; 548 ddc = DDC_MONID; 549 } else 550 ddc_line = RADEON_GPIO_CRT2_DDC; 551 break; 552 } 553 554 if (ddc_line == RADEON_GPIOPAD_MASK) { 555 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; 556 i2c.mask_data_reg = RADEON_GPIOPAD_MASK; 557 i2c.a_clk_reg = RADEON_GPIOPAD_A; 558 i2c.a_data_reg = RADEON_GPIOPAD_A; 559 i2c.en_clk_reg = RADEON_GPIOPAD_EN; 560 i2c.en_data_reg = RADEON_GPIOPAD_EN; 561 i2c.y_clk_reg = RADEON_GPIOPAD_Y; 562 i2c.y_data_reg = RADEON_GPIOPAD_Y; 563 } else if (ddc_line == RADEON_MDGPIO_MASK) { 564 i2c.mask_clk_reg = RADEON_MDGPIO_MASK; 565 i2c.mask_data_reg = RADEON_MDGPIO_MASK; 566 i2c.a_clk_reg = RADEON_MDGPIO_A; 567 i2c.a_data_reg = RADEON_MDGPIO_A; 568 i2c.en_clk_reg = RADEON_MDGPIO_EN; 569 i2c.en_data_reg = RADEON_MDGPIO_EN; 570 i2c.y_clk_reg = RADEON_MDGPIO_Y; 571 i2c.y_data_reg = RADEON_MDGPIO_Y; 572 } else { 573 i2c.mask_clk_reg = ddc_line; 574 i2c.mask_data_reg = ddc_line; 575 i2c.a_clk_reg = ddc_line; 576 i2c.a_data_reg = ddc_line; 577 i2c.en_clk_reg = ddc_line; 578 i2c.en_data_reg = ddc_line; 579 i2c.y_clk_reg = ddc_line; 580 i2c.y_data_reg = ddc_line; 581 } 582 583 if (clk_mask && data_mask) { 584 /* system specific masks */ 585 i2c.mask_clk_mask = clk_mask; 586 i2c.mask_data_mask = data_mask; 587 i2c.a_clk_mask = clk_mask; 588 i2c.a_data_mask = data_mask; 589 i2c.en_clk_mask = clk_mask; 590 i2c.en_data_mask = data_mask; 591 i2c.y_clk_mask = clk_mask; 592 i2c.y_data_mask = data_mask; 593 } else if ((ddc_line == RADEON_GPIOPAD_MASK) || 594 (ddc_line == RADEON_MDGPIO_MASK)) { 595 /* default gpiopad masks */ 596 i2c.mask_clk_mask = (0x20 << 8); 597 i2c.mask_data_mask = 0x80; 598 i2c.a_clk_mask = (0x20 << 8); 599 i2c.a_data_mask = 0x80; 600 i2c.en_clk_mask = (0x20 << 8); 601 i2c.en_data_mask = 0x80; 602 i2c.y_clk_mask = (0x20 << 8); 603 i2c.y_data_mask = 0x80; 604 } else { 605 /* default masks for ddc pads */ 606 i2c.mask_clk_mask = RADEON_GPIO_MASK_1; 607 i2c.mask_data_mask = RADEON_GPIO_MASK_0; 608 i2c.a_clk_mask = RADEON_GPIO_A_1; 609 i2c.a_data_mask = RADEON_GPIO_A_0; 610 i2c.en_clk_mask = RADEON_GPIO_EN_1; 611 i2c.en_data_mask = RADEON_GPIO_EN_0; 612 i2c.y_clk_mask = RADEON_GPIO_Y_1; 613 i2c.y_data_mask = RADEON_GPIO_Y_0; 614 } 615 616 switch (rdev->family) { 617 case CHIP_R100: 618 case CHIP_RV100: 619 case CHIP_RS100: 620 case CHIP_RV200: 621 case CHIP_RS200: 622 case CHIP_RS300: 623 switch (ddc_line) { 624 case RADEON_GPIO_DVI_DDC: 625 i2c.hw_capable = true; 626 break; 627 default: 628 i2c.hw_capable = false; 629 break; 630 } 631 break; 632 case CHIP_R200: 633 switch (ddc_line) { 634 case RADEON_GPIO_DVI_DDC: 635 case RADEON_GPIO_MONID: 636 i2c.hw_capable = true; 637 break; 638 default: 639 i2c.hw_capable = false; 640 break; 641 } 642 break; 643 case CHIP_RV250: 644 case CHIP_RV280: 645 switch (ddc_line) { 646 case RADEON_GPIO_VGA_DDC: 647 case RADEON_GPIO_DVI_DDC: 648 case RADEON_GPIO_CRT2_DDC: 649 i2c.hw_capable = true; 650 break; 651 default: 652 i2c.hw_capable = false; 653 break; 654 } 655 break; 656 case CHIP_R300: 657 case CHIP_R350: 658 switch (ddc_line) { 659 case RADEON_GPIO_VGA_DDC: 660 case RADEON_GPIO_DVI_DDC: 661 i2c.hw_capable = true; 662 break; 663 default: 664 i2c.hw_capable = false; 665 break; 666 } 667 break; 668 case CHIP_RV350: 669 case CHIP_RV380: 670 case CHIP_RS400: 671 case CHIP_RS480: 672 switch (ddc_line) { 673 case RADEON_GPIO_VGA_DDC: 674 case RADEON_GPIO_DVI_DDC: 675 i2c.hw_capable = true; 676 break; 677 case RADEON_GPIO_MONID: 678 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work 679 * reliably on some pre-r4xx hardware; not sure why. 680 */ 681 i2c.hw_capable = false; 682 break; 683 default: 684 i2c.hw_capable = false; 685 break; 686 } 687 break; 688 default: 689 i2c.hw_capable = false; 690 break; 691 } 692 i2c.mm_i2c = false; 693 694 i2c.i2c_id = ddc; 695 i2c.hpd = RADEON_HPD_NONE; 696 697 if (ddc_line) 698 i2c.valid = true; 699 else 700 i2c.valid = false; 701 702 return i2c; 703 } 704 705 static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev) 706 { 707 struct drm_device *dev = rdev->ddev; 708 struct radeon_i2c_bus_rec i2c; 709 u16 offset; 710 u8 id, blocks, clk, data; 711 int i; 712 713 i2c.valid = false; 714 715 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE); 716 if (offset) { 717 blocks = RBIOS8(offset + 2); 718 for (i = 0; i < blocks; i++) { 719 id = RBIOS8(offset + 3 + (i * 5) + 0); 720 if (id == 136) { 721 clk = RBIOS8(offset + 3 + (i * 5) + 3); 722 data = RBIOS8(offset + 3 + (i * 5) + 4); 723 /* gpiopad */ 724 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 725 (1 << clk), (1 << data)); 726 break; 727 } 728 } 729 } 730 return i2c; 731 } 732 733 void radeon_combios_i2c_init(struct radeon_device *rdev) 734 { 735 struct drm_device *dev = rdev->ddev; 736 struct radeon_i2c_bus_rec i2c; 737 738 /* actual hw pads 739 * r1xx/rs2xx/rs3xx 740 * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm 741 * r200 742 * 0x60, 0x64, 0x68, mm 743 * r300/r350 744 * 0x60, 0x64, mm 745 * rv2xx/rv3xx/rs4xx 746 * 0x60, 0x64, 0x68, gpiopads, mm 747 */ 748 749 /* 0x60 */ 750 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 751 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC"); 752 /* 0x64 */ 753 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 754 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC"); 755 756 /* mm i2c */ 757 i2c.valid = true; 758 i2c.hw_capable = true; 759 i2c.mm_i2c = true; 760 i2c.i2c_id = 0xa0; 761 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C"); 762 763 if (rdev->family == CHIP_R300 || 764 rdev->family == CHIP_R350) { 765 /* only 2 sw i2c pads */ 766 } else if (rdev->family == CHIP_RS300 || 767 rdev->family == CHIP_RS400 || 768 rdev->family == CHIP_RS480) { 769 /* 0x68 */ 770 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 771 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 772 773 /* gpiopad */ 774 i2c = radeon_combios_get_i2c_info_from_table(rdev); 775 if (i2c.valid) 776 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK"); 777 } else if ((rdev->family == CHIP_R200) || 778 (rdev->family >= CHIP_R300)) { 779 /* 0x68 */ 780 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 781 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 782 } else { 783 /* 0x68 */ 784 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 785 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 786 /* 0x6c */ 787 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 788 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC"); 789 } 790 } 791 792 bool radeon_combios_get_clock_info(struct drm_device *dev) 793 { 794 struct radeon_device *rdev = dev->dev_private; 795 uint16_t pll_info; 796 struct radeon_pll *p1pll = &rdev->clock.p1pll; 797 struct radeon_pll *p2pll = &rdev->clock.p2pll; 798 struct radeon_pll *spll = &rdev->clock.spll; 799 struct radeon_pll *mpll = &rdev->clock.mpll; 800 int8_t rev; 801 uint16_t sclk, mclk; 802 803 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE); 804 if (pll_info) { 805 rev = RBIOS8(pll_info); 806 807 /* pixel clocks */ 808 p1pll->reference_freq = RBIOS16(pll_info + 0xe); 809 p1pll->reference_div = RBIOS16(pll_info + 0x10); 810 p1pll->pll_out_min = RBIOS32(pll_info + 0x12); 811 p1pll->pll_out_max = RBIOS32(pll_info + 0x16); 812 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 813 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 814 815 if (rev > 9) { 816 p1pll->pll_in_min = RBIOS32(pll_info + 0x36); 817 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a); 818 } else { 819 p1pll->pll_in_min = 40; 820 p1pll->pll_in_max = 500; 821 } 822 *p2pll = *p1pll; 823 824 /* system clock */ 825 spll->reference_freq = RBIOS16(pll_info + 0x1a); 826 spll->reference_div = RBIOS16(pll_info + 0x1c); 827 spll->pll_out_min = RBIOS32(pll_info + 0x1e); 828 spll->pll_out_max = RBIOS32(pll_info + 0x22); 829 830 if (rev > 10) { 831 spll->pll_in_min = RBIOS32(pll_info + 0x48); 832 spll->pll_in_max = RBIOS32(pll_info + 0x4c); 833 } else { 834 /* ??? */ 835 spll->pll_in_min = 40; 836 spll->pll_in_max = 500; 837 } 838 839 /* memory clock */ 840 mpll->reference_freq = RBIOS16(pll_info + 0x26); 841 mpll->reference_div = RBIOS16(pll_info + 0x28); 842 mpll->pll_out_min = RBIOS32(pll_info + 0x2a); 843 mpll->pll_out_max = RBIOS32(pll_info + 0x2e); 844 845 if (rev > 10) { 846 mpll->pll_in_min = RBIOS32(pll_info + 0x5a); 847 mpll->pll_in_max = RBIOS32(pll_info + 0x5e); 848 } else { 849 /* ??? */ 850 mpll->pll_in_min = 40; 851 mpll->pll_in_max = 500; 852 } 853 854 /* default sclk/mclk */ 855 sclk = RBIOS16(pll_info + 0xa); 856 mclk = RBIOS16(pll_info + 0x8); 857 if (sclk == 0) 858 sclk = 200 * 100; 859 if (mclk == 0) 860 mclk = 200 * 100; 861 862 rdev->clock.default_sclk = sclk; 863 rdev->clock.default_mclk = mclk; 864 865 if (RBIOS32(pll_info + 0x16)) 866 rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16); 867 else 868 rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */ 869 870 return true; 871 } 872 return false; 873 } 874 875 bool radeon_combios_sideport_present(struct radeon_device *rdev) 876 { 877 struct drm_device *dev = rdev->ddev; 878 u16 igp_info; 879 880 /* sideport is AMD only */ 881 if (rdev->family == CHIP_RS400) 882 return false; 883 884 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE); 885 886 if (igp_info) { 887 if (RBIOS16(igp_info + 0x4)) 888 return true; 889 } 890 return false; 891 } 892 893 static const uint32_t default_primarydac_adj[CHIP_LAST] = { 894 0x00000808, /* r100 */ 895 0x00000808, /* rv100 */ 896 0x00000808, /* rs100 */ 897 0x00000808, /* rv200 */ 898 0x00000808, /* rs200 */ 899 0x00000808, /* r200 */ 900 0x00000808, /* rv250 */ 901 0x00000000, /* rs300 */ 902 0x00000808, /* rv280 */ 903 0x00000808, /* r300 */ 904 0x00000808, /* r350 */ 905 0x00000808, /* rv350 */ 906 0x00000808, /* rv380 */ 907 0x00000808, /* r420 */ 908 0x00000808, /* r423 */ 909 0x00000808, /* rv410 */ 910 0x00000000, /* rs400 */ 911 0x00000000, /* rs480 */ 912 }; 913 914 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev, 915 struct radeon_encoder_primary_dac *p_dac) 916 { 917 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family]; 918 return; 919 } 920 921 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct 922 radeon_encoder 923 *encoder) 924 { 925 struct drm_device *dev = encoder->base.dev; 926 struct radeon_device *rdev = dev->dev_private; 927 uint16_t dac_info; 928 uint8_t rev, bg, dac; 929 struct radeon_encoder_primary_dac *p_dac = NULL; 930 int found = 0; 931 932 p_dac = kmalloc(sizeof(struct radeon_encoder_primary_dac), 933 DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 934 935 if (!p_dac) 936 return NULL; 937 938 /* check CRT table */ 939 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 940 if (dac_info) { 941 rev = RBIOS8(dac_info) & 0x3; 942 if (rev < 2) { 943 bg = RBIOS8(dac_info + 0x2) & 0xf; 944 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf; 945 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 946 } else { 947 bg = RBIOS8(dac_info + 0x2) & 0xf; 948 dac = RBIOS8(dac_info + 0x3) & 0xf; 949 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 950 } 951 /* if the values are all zeros, use the table */ 952 if (p_dac->ps2_pdac_adj) 953 found = 1; 954 } 955 956 if (!found) /* fallback to defaults */ 957 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac); 958 959 return p_dac; 960 } 961 962 enum radeon_tv_std 963 radeon_combios_get_tv_info(struct radeon_device *rdev) 964 { 965 struct drm_device *dev = rdev->ddev; 966 uint16_t tv_info; 967 enum radeon_tv_std tv_std = TV_STD_NTSC; 968 969 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 970 if (tv_info) { 971 if (RBIOS8(tv_info + 6) == 'T') { 972 switch (RBIOS8(tv_info + 7) & 0xf) { 973 case 1: 974 tv_std = TV_STD_NTSC; 975 DRM_DEBUG_KMS("Default TV standard: NTSC\n"); 976 break; 977 case 2: 978 tv_std = TV_STD_PAL; 979 DRM_DEBUG_KMS("Default TV standard: PAL\n"); 980 break; 981 case 3: 982 tv_std = TV_STD_PAL_M; 983 DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); 984 break; 985 case 4: 986 tv_std = TV_STD_PAL_60; 987 DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); 988 break; 989 case 5: 990 tv_std = TV_STD_NTSC_J; 991 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); 992 break; 993 case 6: 994 tv_std = TV_STD_SCART_PAL; 995 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n"); 996 break; 997 default: 998 tv_std = TV_STD_NTSC; 999 DRM_DEBUG_KMS 1000 ("Unknown TV standard; defaulting to NTSC\n"); 1001 break; 1002 } 1003 1004 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) { 1005 case 0: 1006 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n"); 1007 break; 1008 case 1: 1009 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n"); 1010 break; 1011 case 2: 1012 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n"); 1013 break; 1014 case 3: 1015 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n"); 1016 break; 1017 default: 1018 break; 1019 } 1020 } 1021 } 1022 return tv_std; 1023 } 1024 1025 static const uint32_t default_tvdac_adj[CHIP_LAST] = { 1026 0x00000000, /* r100 */ 1027 0x00280000, /* rv100 */ 1028 0x00000000, /* rs100 */ 1029 0x00880000, /* rv200 */ 1030 0x00000000, /* rs200 */ 1031 0x00000000, /* r200 */ 1032 0x00770000, /* rv250 */ 1033 0x00290000, /* rs300 */ 1034 0x00560000, /* rv280 */ 1035 0x00780000, /* r300 */ 1036 0x00770000, /* r350 */ 1037 0x00780000, /* rv350 */ 1038 0x00780000, /* rv380 */ 1039 0x01080000, /* r420 */ 1040 0x01080000, /* r423 */ 1041 0x01080000, /* rv410 */ 1042 0x00780000, /* rs400 */ 1043 0x00780000, /* rs480 */ 1044 }; 1045 1046 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev, 1047 struct radeon_encoder_tv_dac *tv_dac) 1048 { 1049 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family]; 1050 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250)) 1051 tv_dac->ps2_tvdac_adj = 0x00880000; 1052 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 1053 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 1054 return; 1055 } 1056 1057 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct 1058 radeon_encoder 1059 *encoder) 1060 { 1061 struct drm_device *dev = encoder->base.dev; 1062 struct radeon_device *rdev = dev->dev_private; 1063 uint16_t dac_info; 1064 uint8_t rev, bg, dac; 1065 struct radeon_encoder_tv_dac *tv_dac = NULL; 1066 int found = 0; 1067 1068 tv_dac = kmalloc(sizeof(struct radeon_encoder_tv_dac), 1069 DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 1070 if (!tv_dac) 1071 return NULL; 1072 1073 /* first check TV table */ 1074 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 1075 if (dac_info) { 1076 rev = RBIOS8(dac_info + 0x3); 1077 if (rev > 4) { 1078 bg = RBIOS8(dac_info + 0xc) & 0xf; 1079 dac = RBIOS8(dac_info + 0xd) & 0xf; 1080 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1081 1082 bg = RBIOS8(dac_info + 0xe) & 0xf; 1083 dac = RBIOS8(dac_info + 0xf) & 0xf; 1084 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1085 1086 bg = RBIOS8(dac_info + 0x10) & 0xf; 1087 dac = RBIOS8(dac_info + 0x11) & 0xf; 1088 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1089 /* if the values are all zeros, use the table */ 1090 if (tv_dac->ps2_tvdac_adj) 1091 found = 1; 1092 } else if (rev > 1) { 1093 bg = RBIOS8(dac_info + 0xc) & 0xf; 1094 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf; 1095 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1096 1097 bg = RBIOS8(dac_info + 0xd) & 0xf; 1098 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf; 1099 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1100 1101 bg = RBIOS8(dac_info + 0xe) & 0xf; 1102 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf; 1103 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1104 /* if the values are all zeros, use the table */ 1105 if (tv_dac->ps2_tvdac_adj) 1106 found = 1; 1107 } 1108 tv_dac->tv_std = radeon_combios_get_tv_info(rdev); 1109 } 1110 if (!found) { 1111 /* then check CRT table */ 1112 dac_info = 1113 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 1114 if (dac_info) { 1115 rev = RBIOS8(dac_info) & 0x3; 1116 if (rev < 2) { 1117 bg = RBIOS8(dac_info + 0x3) & 0xf; 1118 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf; 1119 tv_dac->ps2_tvdac_adj = 1120 (bg << 16) | (dac << 20); 1121 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 1122 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 1123 /* if the values are all zeros, use the table */ 1124 if (tv_dac->ps2_tvdac_adj) 1125 found = 1; 1126 } else { 1127 bg = RBIOS8(dac_info + 0x4) & 0xf; 1128 dac = RBIOS8(dac_info + 0x5) & 0xf; 1129 tv_dac->ps2_tvdac_adj = 1130 (bg << 16) | (dac << 20); 1131 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 1132 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 1133 /* if the values are all zeros, use the table */ 1134 if (tv_dac->ps2_tvdac_adj) 1135 found = 1; 1136 } 1137 } else { 1138 DRM_INFO("No TV DAC info found in BIOS\n"); 1139 } 1140 } 1141 1142 if (!found) /* fallback to defaults */ 1143 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac); 1144 1145 return tv_dac; 1146 } 1147 1148 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct 1149 radeon_device 1150 *rdev) 1151 { 1152 struct radeon_encoder_lvds *lvds = NULL; 1153 uint32_t fp_vert_stretch, fp_horz_stretch; 1154 uint32_t ppll_div_sel, ppll_val; 1155 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); 1156 1157 lvds = kmalloc(sizeof(struct radeon_encoder_lvds), DRM_MEM_DRIVER, 1158 M_WAITOK | M_ZERO); 1159 1160 if (!lvds) 1161 return NULL; 1162 1163 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH); 1164 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH); 1165 1166 /* These should be fail-safe defaults, fingers crossed */ 1167 lvds->panel_pwr_delay = 200; 1168 lvds->panel_vcc_delay = 2000; 1169 1170 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 1171 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf; 1172 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf; 1173 1174 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) 1175 lvds->native_mode.vdisplay = 1176 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >> 1177 RADEON_VERT_PANEL_SHIFT) + 1; 1178 else 1179 lvds->native_mode.vdisplay = 1180 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1; 1181 1182 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE) 1183 lvds->native_mode.hdisplay = 1184 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >> 1185 RADEON_HORZ_PANEL_SHIFT) + 1) * 8; 1186 else 1187 lvds->native_mode.hdisplay = 1188 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8; 1189 1190 if ((lvds->native_mode.hdisplay < 640) || 1191 (lvds->native_mode.vdisplay < 480)) { 1192 lvds->native_mode.hdisplay = 640; 1193 lvds->native_mode.vdisplay = 480; 1194 } 1195 1196 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; 1197 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel); 1198 if ((ppll_val & 0x000707ff) == 0x1bb) 1199 lvds->use_bios_dividers = false; 1200 else { 1201 lvds->panel_ref_divider = 1202 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; 1203 lvds->panel_post_divider = (ppll_val >> 16) & 0x7; 1204 lvds->panel_fb_divider = ppll_val & 0x7ff; 1205 1206 if ((lvds->panel_ref_divider != 0) && 1207 (lvds->panel_fb_divider > 3)) 1208 lvds->use_bios_dividers = true; 1209 } 1210 lvds->panel_vcc_delay = 200; 1211 1212 DRM_INFO("Panel info derived from registers\n"); 1213 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 1214 lvds->native_mode.vdisplay); 1215 1216 return lvds; 1217 } 1218 1219 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder 1220 *encoder) 1221 { 1222 struct drm_device *dev = encoder->base.dev; 1223 struct radeon_device *rdev = dev->dev_private; 1224 uint16_t lcd_info; 1225 uint32_t panel_setup; 1226 char stmp[30]; 1227 int tmp, i; 1228 struct radeon_encoder_lvds *lvds = NULL; 1229 1230 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 1231 1232 if (lcd_info) { 1233 lvds = kmalloc(sizeof(struct radeon_encoder_lvds), 1234 DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 1235 1236 if (!lvds) 1237 return NULL; 1238 1239 for (i = 0; i < 24; i++) 1240 stmp[i] = RBIOS8(lcd_info + i + 1); 1241 stmp[24] = 0; 1242 1243 DRM_INFO("Panel ID String: %s\n", stmp); 1244 1245 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19); 1246 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b); 1247 1248 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 1249 lvds->native_mode.vdisplay); 1250 1251 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c); 1252 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000); 1253 1254 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24); 1255 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf; 1256 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf; 1257 1258 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e); 1259 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30); 1260 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31); 1261 if ((lvds->panel_ref_divider != 0) && 1262 (lvds->panel_fb_divider > 3)) 1263 lvds->use_bios_dividers = true; 1264 1265 panel_setup = RBIOS32(lcd_info + 0x39); 1266 lvds->lvds_gen_cntl = 0xff00; 1267 if (panel_setup & 0x1) 1268 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT; 1269 1270 if ((panel_setup >> 4) & 0x1) 1271 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE; 1272 1273 switch ((panel_setup >> 8) & 0x7) { 1274 case 0: 1275 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM; 1276 break; 1277 case 1: 1278 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY; 1279 break; 1280 case 2: 1281 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY; 1282 break; 1283 default: 1284 break; 1285 } 1286 1287 if ((panel_setup >> 16) & 0x1) 1288 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW; 1289 1290 if ((panel_setup >> 17) & 0x1) 1291 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW; 1292 1293 if ((panel_setup >> 18) & 0x1) 1294 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW; 1295 1296 if ((panel_setup >> 23) & 0x1) 1297 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL; 1298 1299 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000); 1300 1301 for (i = 0; i < 32; i++) { 1302 tmp = RBIOS16(lcd_info + 64 + i * 2); 1303 if (tmp == 0) 1304 break; 1305 1306 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) && 1307 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) { 1308 lvds->native_mode.htotal = lvds->native_mode.hdisplay + 1309 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8; 1310 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + 1311 (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8; 1312 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + 1313 (RBIOS8(tmp + 23) * 8); 1314 1315 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + 1316 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26)); 1317 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + 1318 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26)); 1319 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + 1320 ((RBIOS16(tmp + 28) & 0xf800) >> 11); 1321 1322 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10; 1323 lvds->native_mode.flags = 0; 1324 /* set crtc values */ 1325 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); 1326 1327 } 1328 } 1329 } else { 1330 DRM_INFO("No panel info found in BIOS\n"); 1331 lvds = radeon_legacy_get_lvds_info_from_regs(rdev); 1332 } 1333 1334 if (lvds) 1335 encoder->native_mode = lvds->native_mode; 1336 return lvds; 1337 } 1338 1339 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = { 1340 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */ 1341 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */ 1342 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */ 1343 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */ 1344 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */ 1345 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */ 1346 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */ 1347 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */ 1348 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */ 1349 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */ 1350 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */ 1351 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */ 1352 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */ 1353 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */ 1354 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */ 1355 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */ 1356 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */ 1357 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */ 1358 }; 1359 1360 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 1361 struct radeon_encoder_int_tmds *tmds) 1362 { 1363 struct drm_device *dev = encoder->base.dev; 1364 struct radeon_device *rdev = dev->dev_private; 1365 int i; 1366 1367 for (i = 0; i < 4; i++) { 1368 tmds->tmds_pll[i].value = 1369 default_tmds_pll[rdev->family][i].value; 1370 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq; 1371 } 1372 1373 return true; 1374 } 1375 1376 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 1377 struct radeon_encoder_int_tmds *tmds) 1378 { 1379 struct drm_device *dev = encoder->base.dev; 1380 struct radeon_device *rdev = dev->dev_private; 1381 uint16_t tmds_info; 1382 int i, n; 1383 uint8_t ver; 1384 1385 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 1386 1387 if (tmds_info) { 1388 ver = RBIOS8(tmds_info); 1389 DRM_DEBUG_KMS("DFP table revision: %d\n", ver); 1390 if (ver == 3) { 1391 n = RBIOS8(tmds_info + 5) + 1; 1392 if (n > 4) 1393 n = 4; 1394 for (i = 0; i < n; i++) { 1395 tmds->tmds_pll[i].value = 1396 RBIOS32(tmds_info + i * 10 + 0x08); 1397 tmds->tmds_pll[i].freq = 1398 RBIOS16(tmds_info + i * 10 + 0x10); 1399 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", 1400 tmds->tmds_pll[i].freq, 1401 tmds->tmds_pll[i].value); 1402 } 1403 } else if (ver == 4) { 1404 int stride = 0; 1405 n = RBIOS8(tmds_info + 5) + 1; 1406 if (n > 4) 1407 n = 4; 1408 for (i = 0; i < n; i++) { 1409 tmds->tmds_pll[i].value = 1410 RBIOS32(tmds_info + stride + 0x08); 1411 tmds->tmds_pll[i].freq = 1412 RBIOS16(tmds_info + stride + 0x10); 1413 if (i == 0) 1414 stride += 10; 1415 else 1416 stride += 6; 1417 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", 1418 tmds->tmds_pll[i].freq, 1419 tmds->tmds_pll[i].value); 1420 } 1421 } 1422 } else { 1423 DRM_INFO("No TMDS info found in BIOS\n"); 1424 return false; 1425 } 1426 return true; 1427 } 1428 1429 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 1430 struct radeon_encoder_ext_tmds *tmds) 1431 { 1432 struct drm_device *dev = encoder->base.dev; 1433 struct radeon_device *rdev = dev->dev_private; 1434 struct radeon_i2c_bus_rec i2c_bus; 1435 1436 /* default for macs */ 1437 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1438 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1439 1440 /* XXX some macs have duallink chips */ 1441 switch (rdev->mode_info.connector_table) { 1442 case CT_POWERBOOK_EXTERNAL: 1443 case CT_MINI_EXTERNAL: 1444 default: 1445 tmds->dvo_chip = DVO_SIL164; 1446 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1447 break; 1448 } 1449 1450 return true; 1451 } 1452 1453 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 1454 struct radeon_encoder_ext_tmds *tmds) 1455 { 1456 struct drm_device *dev = encoder->base.dev; 1457 struct radeon_device *rdev = dev->dev_private; 1458 uint16_t offset; 1459 uint8_t ver; 1460 enum radeon_combios_ddc gpio; 1461 struct radeon_i2c_bus_rec i2c_bus; 1462 1463 tmds->i2c_bus = NULL; 1464 if (rdev->flags & RADEON_IS_IGP) { 1465 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1466 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1467 tmds->dvo_chip = DVO_SIL164; 1468 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1469 } else { 1470 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 1471 if (offset) { 1472 ver = RBIOS8(offset); 1473 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver); 1474 tmds->slave_addr = RBIOS8(offset + 4 + 2); 1475 tmds->slave_addr >>= 1; /* 7 bit addressing */ 1476 gpio = RBIOS8(offset + 4 + 3); 1477 if (gpio == DDC_LCD) { 1478 /* MM i2c */ 1479 i2c_bus.valid = true; 1480 i2c_bus.hw_capable = true; 1481 i2c_bus.mm_i2c = true; 1482 i2c_bus.i2c_id = 0xa0; 1483 } else 1484 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); 1485 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1486 } 1487 } 1488 1489 if (!tmds->i2c_bus) { 1490 DRM_INFO("No valid Ext TMDS info found in BIOS\n"); 1491 return false; 1492 } 1493 1494 return true; 1495 } 1496 1497 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) 1498 { 1499 struct radeon_device *rdev = dev->dev_private; 1500 struct radeon_i2c_bus_rec ddc_i2c; 1501 struct radeon_hpd hpd; 1502 1503 rdev->mode_info.connector_table = radeon_connector_table; 1504 if (rdev->mode_info.connector_table == CT_NONE) { 1505 #ifdef CONFIG_PPC_PMAC 1506 if (of_machine_is_compatible("PowerBook3,3")) { 1507 /* powerbook with VGA */ 1508 rdev->mode_info.connector_table = CT_POWERBOOK_VGA; 1509 } else if (of_machine_is_compatible("PowerBook3,4") || 1510 of_machine_is_compatible("PowerBook3,5")) { 1511 /* powerbook with internal tmds */ 1512 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL; 1513 } else if (of_machine_is_compatible("PowerBook5,1") || 1514 of_machine_is_compatible("PowerBook5,2") || 1515 of_machine_is_compatible("PowerBook5,3") || 1516 of_machine_is_compatible("PowerBook5,4") || 1517 of_machine_is_compatible("PowerBook5,5")) { 1518 /* powerbook with external single link tmds (sil164) */ 1519 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1520 } else if (of_machine_is_compatible("PowerBook5,6")) { 1521 /* powerbook with external dual or single link tmds */ 1522 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1523 } else if (of_machine_is_compatible("PowerBook5,7") || 1524 of_machine_is_compatible("PowerBook5,8") || 1525 of_machine_is_compatible("PowerBook5,9")) { 1526 /* PowerBook6,2 ? */ 1527 /* powerbook with external dual link tmds (sil1178?) */ 1528 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1529 } else if (of_machine_is_compatible("PowerBook4,1") || 1530 of_machine_is_compatible("PowerBook4,2") || 1531 of_machine_is_compatible("PowerBook4,3") || 1532 of_machine_is_compatible("PowerBook6,3") || 1533 of_machine_is_compatible("PowerBook6,5") || 1534 of_machine_is_compatible("PowerBook6,7")) { 1535 /* ibook */ 1536 rdev->mode_info.connector_table = CT_IBOOK; 1537 } else if (of_machine_is_compatible("PowerMac3,5")) { 1538 /* PowerMac G4 Silver radeon 7500 */ 1539 rdev->mode_info.connector_table = CT_MAC_G4_SILVER; 1540 } else if (of_machine_is_compatible("PowerMac4,4")) { 1541 /* emac */ 1542 rdev->mode_info.connector_table = CT_EMAC; 1543 } else if (of_machine_is_compatible("PowerMac10,1")) { 1544 /* mini with internal tmds */ 1545 rdev->mode_info.connector_table = CT_MINI_INTERNAL; 1546 } else if (of_machine_is_compatible("PowerMac10,2")) { 1547 /* mini with external tmds */ 1548 rdev->mode_info.connector_table = CT_MINI_EXTERNAL; 1549 } else if (of_machine_is_compatible("PowerMac12,1")) { 1550 /* PowerMac8,1 ? */ 1551 /* imac g5 isight */ 1552 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT; 1553 } else if ((dev->pci_device == 0x4a48) && 1554 (dev->pci_subvendor == 0x1002) && 1555 (dev->pci_subdevice == 0x4a48)) { 1556 /* Mac X800 */ 1557 rdev->mode_info.connector_table = CT_MAC_X800; 1558 } else if ((of_machine_is_compatible("PowerMac7,2") || 1559 of_machine_is_compatible("PowerMac7,3")) && 1560 (dev->pci_device == 0x4150) && 1561 (dev->pci_subvendor == 0x1002) && 1562 (dev->pci_subdevice == 0x4150)) { 1563 /* Mac G5 tower 9600 */ 1564 rdev->mode_info.connector_table = CT_MAC_G5_9600; 1565 } else if ((dev->pci_device == 0x4c66) && 1566 (dev->pci_subvendor == 0x1002) && 1567 (dev->pci_subdevice == 0x4c66)) { 1568 /* SAM440ep RV250 embedded board */ 1569 rdev->mode_info.connector_table = CT_SAM440EP; 1570 } else 1571 #endif /* CONFIG_PPC_PMAC */ 1572 #ifdef CONFIG_PPC64 1573 if (ASIC_IS_RN50(rdev)) 1574 rdev->mode_info.connector_table = CT_RN50_POWER; 1575 else 1576 #endif 1577 rdev->mode_info.connector_table = CT_GENERIC; 1578 } 1579 1580 switch (rdev->mode_info.connector_table) { 1581 case CT_GENERIC: 1582 DRM_INFO("Connector Table: %d (generic)\n", 1583 rdev->mode_info.connector_table); 1584 /* these are the most common settings */ 1585 if (rdev->flags & RADEON_SINGLE_CRTC) { 1586 /* VGA - primary dac */ 1587 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1588 hpd.hpd = RADEON_HPD_NONE; 1589 radeon_add_legacy_encoder(dev, 1590 radeon_get_encoder_enum(dev, 1591 ATOM_DEVICE_CRT1_SUPPORT, 1592 1), 1593 ATOM_DEVICE_CRT1_SUPPORT); 1594 radeon_add_legacy_connector(dev, 0, 1595 ATOM_DEVICE_CRT1_SUPPORT, 1596 DRM_MODE_CONNECTOR_VGA, 1597 &ddc_i2c, 1598 CONNECTOR_OBJECT_ID_VGA, 1599 &hpd); 1600 } else if (rdev->flags & RADEON_IS_MOBILITY) { 1601 /* LVDS */ 1602 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); 1603 hpd.hpd = RADEON_HPD_NONE; 1604 radeon_add_legacy_encoder(dev, 1605 radeon_get_encoder_enum(dev, 1606 ATOM_DEVICE_LCD1_SUPPORT, 1607 0), 1608 ATOM_DEVICE_LCD1_SUPPORT); 1609 radeon_add_legacy_connector(dev, 0, 1610 ATOM_DEVICE_LCD1_SUPPORT, 1611 DRM_MODE_CONNECTOR_LVDS, 1612 &ddc_i2c, 1613 CONNECTOR_OBJECT_ID_LVDS, 1614 &hpd); 1615 1616 /* VGA - primary dac */ 1617 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1618 hpd.hpd = RADEON_HPD_NONE; 1619 radeon_add_legacy_encoder(dev, 1620 radeon_get_encoder_enum(dev, 1621 ATOM_DEVICE_CRT1_SUPPORT, 1622 1), 1623 ATOM_DEVICE_CRT1_SUPPORT); 1624 radeon_add_legacy_connector(dev, 1, 1625 ATOM_DEVICE_CRT1_SUPPORT, 1626 DRM_MODE_CONNECTOR_VGA, 1627 &ddc_i2c, 1628 CONNECTOR_OBJECT_ID_VGA, 1629 &hpd); 1630 } else { 1631 /* DVI-I - tv dac, int tmds */ 1632 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1633 hpd.hpd = RADEON_HPD_1; 1634 radeon_add_legacy_encoder(dev, 1635 radeon_get_encoder_enum(dev, 1636 ATOM_DEVICE_DFP1_SUPPORT, 1637 0), 1638 ATOM_DEVICE_DFP1_SUPPORT); 1639 radeon_add_legacy_encoder(dev, 1640 radeon_get_encoder_enum(dev, 1641 ATOM_DEVICE_CRT2_SUPPORT, 1642 2), 1643 ATOM_DEVICE_CRT2_SUPPORT); 1644 radeon_add_legacy_connector(dev, 0, 1645 ATOM_DEVICE_DFP1_SUPPORT | 1646 ATOM_DEVICE_CRT2_SUPPORT, 1647 DRM_MODE_CONNECTOR_DVII, 1648 &ddc_i2c, 1649 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1650 &hpd); 1651 1652 /* VGA - primary dac */ 1653 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1654 hpd.hpd = RADEON_HPD_NONE; 1655 radeon_add_legacy_encoder(dev, 1656 radeon_get_encoder_enum(dev, 1657 ATOM_DEVICE_CRT1_SUPPORT, 1658 1), 1659 ATOM_DEVICE_CRT1_SUPPORT); 1660 radeon_add_legacy_connector(dev, 1, 1661 ATOM_DEVICE_CRT1_SUPPORT, 1662 DRM_MODE_CONNECTOR_VGA, 1663 &ddc_i2c, 1664 CONNECTOR_OBJECT_ID_VGA, 1665 &hpd); 1666 } 1667 1668 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 1669 /* TV - tv dac */ 1670 ddc_i2c.valid = false; 1671 hpd.hpd = RADEON_HPD_NONE; 1672 radeon_add_legacy_encoder(dev, 1673 radeon_get_encoder_enum(dev, 1674 ATOM_DEVICE_TV1_SUPPORT, 1675 2), 1676 ATOM_DEVICE_TV1_SUPPORT); 1677 radeon_add_legacy_connector(dev, 2, 1678 ATOM_DEVICE_TV1_SUPPORT, 1679 DRM_MODE_CONNECTOR_SVIDEO, 1680 &ddc_i2c, 1681 CONNECTOR_OBJECT_ID_SVIDEO, 1682 &hpd); 1683 } 1684 break; 1685 case CT_IBOOK: 1686 DRM_INFO("Connector Table: %d (ibook)\n", 1687 rdev->mode_info.connector_table); 1688 /* LVDS */ 1689 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1690 hpd.hpd = RADEON_HPD_NONE; 1691 radeon_add_legacy_encoder(dev, 1692 radeon_get_encoder_enum(dev, 1693 ATOM_DEVICE_LCD1_SUPPORT, 1694 0), 1695 ATOM_DEVICE_LCD1_SUPPORT); 1696 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1697 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1698 CONNECTOR_OBJECT_ID_LVDS, 1699 &hpd); 1700 /* VGA - TV DAC */ 1701 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1702 hpd.hpd = RADEON_HPD_NONE; 1703 radeon_add_legacy_encoder(dev, 1704 radeon_get_encoder_enum(dev, 1705 ATOM_DEVICE_CRT2_SUPPORT, 1706 2), 1707 ATOM_DEVICE_CRT2_SUPPORT); 1708 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1709 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1710 CONNECTOR_OBJECT_ID_VGA, 1711 &hpd); 1712 /* TV - TV DAC */ 1713 ddc_i2c.valid = false; 1714 hpd.hpd = RADEON_HPD_NONE; 1715 radeon_add_legacy_encoder(dev, 1716 radeon_get_encoder_enum(dev, 1717 ATOM_DEVICE_TV1_SUPPORT, 1718 2), 1719 ATOM_DEVICE_TV1_SUPPORT); 1720 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1721 DRM_MODE_CONNECTOR_SVIDEO, 1722 &ddc_i2c, 1723 CONNECTOR_OBJECT_ID_SVIDEO, 1724 &hpd); 1725 break; 1726 case CT_POWERBOOK_EXTERNAL: 1727 DRM_INFO("Connector Table: %d (powerbook external tmds)\n", 1728 rdev->mode_info.connector_table); 1729 /* LVDS */ 1730 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1731 hpd.hpd = RADEON_HPD_NONE; 1732 radeon_add_legacy_encoder(dev, 1733 radeon_get_encoder_enum(dev, 1734 ATOM_DEVICE_LCD1_SUPPORT, 1735 0), 1736 ATOM_DEVICE_LCD1_SUPPORT); 1737 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1738 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1739 CONNECTOR_OBJECT_ID_LVDS, 1740 &hpd); 1741 /* DVI-I - primary dac, ext tmds */ 1742 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1743 hpd.hpd = RADEON_HPD_2; /* ??? */ 1744 radeon_add_legacy_encoder(dev, 1745 radeon_get_encoder_enum(dev, 1746 ATOM_DEVICE_DFP2_SUPPORT, 1747 0), 1748 ATOM_DEVICE_DFP2_SUPPORT); 1749 radeon_add_legacy_encoder(dev, 1750 radeon_get_encoder_enum(dev, 1751 ATOM_DEVICE_CRT1_SUPPORT, 1752 1), 1753 ATOM_DEVICE_CRT1_SUPPORT); 1754 /* XXX some are SL */ 1755 radeon_add_legacy_connector(dev, 1, 1756 ATOM_DEVICE_DFP2_SUPPORT | 1757 ATOM_DEVICE_CRT1_SUPPORT, 1758 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1759 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, 1760 &hpd); 1761 /* TV - TV DAC */ 1762 ddc_i2c.valid = false; 1763 hpd.hpd = RADEON_HPD_NONE; 1764 radeon_add_legacy_encoder(dev, 1765 radeon_get_encoder_enum(dev, 1766 ATOM_DEVICE_TV1_SUPPORT, 1767 2), 1768 ATOM_DEVICE_TV1_SUPPORT); 1769 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1770 DRM_MODE_CONNECTOR_SVIDEO, 1771 &ddc_i2c, 1772 CONNECTOR_OBJECT_ID_SVIDEO, 1773 &hpd); 1774 break; 1775 case CT_POWERBOOK_INTERNAL: 1776 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n", 1777 rdev->mode_info.connector_table); 1778 /* LVDS */ 1779 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1780 hpd.hpd = RADEON_HPD_NONE; 1781 radeon_add_legacy_encoder(dev, 1782 radeon_get_encoder_enum(dev, 1783 ATOM_DEVICE_LCD1_SUPPORT, 1784 0), 1785 ATOM_DEVICE_LCD1_SUPPORT); 1786 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1787 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1788 CONNECTOR_OBJECT_ID_LVDS, 1789 &hpd); 1790 /* DVI-I - primary dac, int tmds */ 1791 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1792 hpd.hpd = RADEON_HPD_1; /* ??? */ 1793 radeon_add_legacy_encoder(dev, 1794 radeon_get_encoder_enum(dev, 1795 ATOM_DEVICE_DFP1_SUPPORT, 1796 0), 1797 ATOM_DEVICE_DFP1_SUPPORT); 1798 radeon_add_legacy_encoder(dev, 1799 radeon_get_encoder_enum(dev, 1800 ATOM_DEVICE_CRT1_SUPPORT, 1801 1), 1802 ATOM_DEVICE_CRT1_SUPPORT); 1803 radeon_add_legacy_connector(dev, 1, 1804 ATOM_DEVICE_DFP1_SUPPORT | 1805 ATOM_DEVICE_CRT1_SUPPORT, 1806 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1807 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1808 &hpd); 1809 /* TV - TV DAC */ 1810 ddc_i2c.valid = false; 1811 hpd.hpd = RADEON_HPD_NONE; 1812 radeon_add_legacy_encoder(dev, 1813 radeon_get_encoder_enum(dev, 1814 ATOM_DEVICE_TV1_SUPPORT, 1815 2), 1816 ATOM_DEVICE_TV1_SUPPORT); 1817 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1818 DRM_MODE_CONNECTOR_SVIDEO, 1819 &ddc_i2c, 1820 CONNECTOR_OBJECT_ID_SVIDEO, 1821 &hpd); 1822 break; 1823 case CT_POWERBOOK_VGA: 1824 DRM_INFO("Connector Table: %d (powerbook vga)\n", 1825 rdev->mode_info.connector_table); 1826 /* LVDS */ 1827 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1828 hpd.hpd = RADEON_HPD_NONE; 1829 radeon_add_legacy_encoder(dev, 1830 radeon_get_encoder_enum(dev, 1831 ATOM_DEVICE_LCD1_SUPPORT, 1832 0), 1833 ATOM_DEVICE_LCD1_SUPPORT); 1834 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1835 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1836 CONNECTOR_OBJECT_ID_LVDS, 1837 &hpd); 1838 /* VGA - primary dac */ 1839 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1840 hpd.hpd = RADEON_HPD_NONE; 1841 radeon_add_legacy_encoder(dev, 1842 radeon_get_encoder_enum(dev, 1843 ATOM_DEVICE_CRT1_SUPPORT, 1844 1), 1845 ATOM_DEVICE_CRT1_SUPPORT); 1846 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, 1847 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1848 CONNECTOR_OBJECT_ID_VGA, 1849 &hpd); 1850 /* TV - TV DAC */ 1851 ddc_i2c.valid = false; 1852 hpd.hpd = RADEON_HPD_NONE; 1853 radeon_add_legacy_encoder(dev, 1854 radeon_get_encoder_enum(dev, 1855 ATOM_DEVICE_TV1_SUPPORT, 1856 2), 1857 ATOM_DEVICE_TV1_SUPPORT); 1858 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1859 DRM_MODE_CONNECTOR_SVIDEO, 1860 &ddc_i2c, 1861 CONNECTOR_OBJECT_ID_SVIDEO, 1862 &hpd); 1863 break; 1864 case CT_MINI_EXTERNAL: 1865 DRM_INFO("Connector Table: %d (mini external tmds)\n", 1866 rdev->mode_info.connector_table); 1867 /* DVI-I - tv dac, ext tmds */ 1868 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1869 hpd.hpd = RADEON_HPD_2; /* ??? */ 1870 radeon_add_legacy_encoder(dev, 1871 radeon_get_encoder_enum(dev, 1872 ATOM_DEVICE_DFP2_SUPPORT, 1873 0), 1874 ATOM_DEVICE_DFP2_SUPPORT); 1875 radeon_add_legacy_encoder(dev, 1876 radeon_get_encoder_enum(dev, 1877 ATOM_DEVICE_CRT2_SUPPORT, 1878 2), 1879 ATOM_DEVICE_CRT2_SUPPORT); 1880 /* XXX are any DL? */ 1881 radeon_add_legacy_connector(dev, 0, 1882 ATOM_DEVICE_DFP2_SUPPORT | 1883 ATOM_DEVICE_CRT2_SUPPORT, 1884 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1885 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1886 &hpd); 1887 /* TV - TV DAC */ 1888 ddc_i2c.valid = false; 1889 hpd.hpd = RADEON_HPD_NONE; 1890 radeon_add_legacy_encoder(dev, 1891 radeon_get_encoder_enum(dev, 1892 ATOM_DEVICE_TV1_SUPPORT, 1893 2), 1894 ATOM_DEVICE_TV1_SUPPORT); 1895 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1896 DRM_MODE_CONNECTOR_SVIDEO, 1897 &ddc_i2c, 1898 CONNECTOR_OBJECT_ID_SVIDEO, 1899 &hpd); 1900 break; 1901 case CT_MINI_INTERNAL: 1902 DRM_INFO("Connector Table: %d (mini internal tmds)\n", 1903 rdev->mode_info.connector_table); 1904 /* DVI-I - tv dac, int tmds */ 1905 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1906 hpd.hpd = RADEON_HPD_1; /* ??? */ 1907 radeon_add_legacy_encoder(dev, 1908 radeon_get_encoder_enum(dev, 1909 ATOM_DEVICE_DFP1_SUPPORT, 1910 0), 1911 ATOM_DEVICE_DFP1_SUPPORT); 1912 radeon_add_legacy_encoder(dev, 1913 radeon_get_encoder_enum(dev, 1914 ATOM_DEVICE_CRT2_SUPPORT, 1915 2), 1916 ATOM_DEVICE_CRT2_SUPPORT); 1917 radeon_add_legacy_connector(dev, 0, 1918 ATOM_DEVICE_DFP1_SUPPORT | 1919 ATOM_DEVICE_CRT2_SUPPORT, 1920 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1921 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1922 &hpd); 1923 /* TV - TV DAC */ 1924 ddc_i2c.valid = false; 1925 hpd.hpd = RADEON_HPD_NONE; 1926 radeon_add_legacy_encoder(dev, 1927 radeon_get_encoder_enum(dev, 1928 ATOM_DEVICE_TV1_SUPPORT, 1929 2), 1930 ATOM_DEVICE_TV1_SUPPORT); 1931 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1932 DRM_MODE_CONNECTOR_SVIDEO, 1933 &ddc_i2c, 1934 CONNECTOR_OBJECT_ID_SVIDEO, 1935 &hpd); 1936 break; 1937 case CT_IMAC_G5_ISIGHT: 1938 DRM_INFO("Connector Table: %d (imac g5 isight)\n", 1939 rdev->mode_info.connector_table); 1940 /* DVI-D - int tmds */ 1941 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1942 hpd.hpd = RADEON_HPD_1; /* ??? */ 1943 radeon_add_legacy_encoder(dev, 1944 radeon_get_encoder_enum(dev, 1945 ATOM_DEVICE_DFP1_SUPPORT, 1946 0), 1947 ATOM_DEVICE_DFP1_SUPPORT); 1948 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT, 1949 DRM_MODE_CONNECTOR_DVID, &ddc_i2c, 1950 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 1951 &hpd); 1952 /* VGA - tv dac */ 1953 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1954 hpd.hpd = RADEON_HPD_NONE; 1955 radeon_add_legacy_encoder(dev, 1956 radeon_get_encoder_enum(dev, 1957 ATOM_DEVICE_CRT2_SUPPORT, 1958 2), 1959 ATOM_DEVICE_CRT2_SUPPORT); 1960 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1961 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1962 CONNECTOR_OBJECT_ID_VGA, 1963 &hpd); 1964 /* TV - TV DAC */ 1965 ddc_i2c.valid = false; 1966 hpd.hpd = RADEON_HPD_NONE; 1967 radeon_add_legacy_encoder(dev, 1968 radeon_get_encoder_enum(dev, 1969 ATOM_DEVICE_TV1_SUPPORT, 1970 2), 1971 ATOM_DEVICE_TV1_SUPPORT); 1972 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1973 DRM_MODE_CONNECTOR_SVIDEO, 1974 &ddc_i2c, 1975 CONNECTOR_OBJECT_ID_SVIDEO, 1976 &hpd); 1977 break; 1978 case CT_EMAC: 1979 DRM_INFO("Connector Table: %d (emac)\n", 1980 rdev->mode_info.connector_table); 1981 /* VGA - primary dac */ 1982 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1983 hpd.hpd = RADEON_HPD_NONE; 1984 radeon_add_legacy_encoder(dev, 1985 radeon_get_encoder_enum(dev, 1986 ATOM_DEVICE_CRT1_SUPPORT, 1987 1), 1988 ATOM_DEVICE_CRT1_SUPPORT); 1989 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, 1990 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1991 CONNECTOR_OBJECT_ID_VGA, 1992 &hpd); 1993 /* VGA - tv dac */ 1994 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1995 hpd.hpd = RADEON_HPD_NONE; 1996 radeon_add_legacy_encoder(dev, 1997 radeon_get_encoder_enum(dev, 1998 ATOM_DEVICE_CRT2_SUPPORT, 1999 2), 2000 ATOM_DEVICE_CRT2_SUPPORT); 2001 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 2002 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 2003 CONNECTOR_OBJECT_ID_VGA, 2004 &hpd); 2005 /* TV - TV DAC */ 2006 ddc_i2c.valid = false; 2007 hpd.hpd = RADEON_HPD_NONE; 2008 radeon_add_legacy_encoder(dev, 2009 radeon_get_encoder_enum(dev, 2010 ATOM_DEVICE_TV1_SUPPORT, 2011 2), 2012 ATOM_DEVICE_TV1_SUPPORT); 2013 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 2014 DRM_MODE_CONNECTOR_SVIDEO, 2015 &ddc_i2c, 2016 CONNECTOR_OBJECT_ID_SVIDEO, 2017 &hpd); 2018 break; 2019 case CT_RN50_POWER: 2020 DRM_INFO("Connector Table: %d (rn50-power)\n", 2021 rdev->mode_info.connector_table); 2022 /* VGA - primary dac */ 2023 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2024 hpd.hpd = RADEON_HPD_NONE; 2025 radeon_add_legacy_encoder(dev, 2026 radeon_get_encoder_enum(dev, 2027 ATOM_DEVICE_CRT1_SUPPORT, 2028 1), 2029 ATOM_DEVICE_CRT1_SUPPORT); 2030 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, 2031 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 2032 CONNECTOR_OBJECT_ID_VGA, 2033 &hpd); 2034 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 2035 hpd.hpd = RADEON_HPD_NONE; 2036 radeon_add_legacy_encoder(dev, 2037 radeon_get_encoder_enum(dev, 2038 ATOM_DEVICE_CRT2_SUPPORT, 2039 2), 2040 ATOM_DEVICE_CRT2_SUPPORT); 2041 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 2042 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 2043 CONNECTOR_OBJECT_ID_VGA, 2044 &hpd); 2045 break; 2046 case CT_MAC_X800: 2047 DRM_INFO("Connector Table: %d (mac x800)\n", 2048 rdev->mode_info.connector_table); 2049 /* DVI - primary dac, internal tmds */ 2050 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2051 hpd.hpd = RADEON_HPD_1; /* ??? */ 2052 radeon_add_legacy_encoder(dev, 2053 radeon_get_encoder_enum(dev, 2054 ATOM_DEVICE_DFP1_SUPPORT, 2055 0), 2056 ATOM_DEVICE_DFP1_SUPPORT); 2057 radeon_add_legacy_encoder(dev, 2058 radeon_get_encoder_enum(dev, 2059 ATOM_DEVICE_CRT1_SUPPORT, 2060 1), 2061 ATOM_DEVICE_CRT1_SUPPORT); 2062 radeon_add_legacy_connector(dev, 0, 2063 ATOM_DEVICE_DFP1_SUPPORT | 2064 ATOM_DEVICE_CRT1_SUPPORT, 2065 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2066 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2067 &hpd); 2068 /* DVI - tv dac, dvo */ 2069 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 2070 hpd.hpd = RADEON_HPD_2; /* ??? */ 2071 radeon_add_legacy_encoder(dev, 2072 radeon_get_encoder_enum(dev, 2073 ATOM_DEVICE_DFP2_SUPPORT, 2074 0), 2075 ATOM_DEVICE_DFP2_SUPPORT); 2076 radeon_add_legacy_encoder(dev, 2077 radeon_get_encoder_enum(dev, 2078 ATOM_DEVICE_CRT2_SUPPORT, 2079 2), 2080 ATOM_DEVICE_CRT2_SUPPORT); 2081 radeon_add_legacy_connector(dev, 1, 2082 ATOM_DEVICE_DFP2_SUPPORT | 2083 ATOM_DEVICE_CRT2_SUPPORT, 2084 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2085 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, 2086 &hpd); 2087 break; 2088 case CT_MAC_G5_9600: 2089 DRM_INFO("Connector Table: %d (mac g5 9600)\n", 2090 rdev->mode_info.connector_table); 2091 /* DVI - tv dac, dvo */ 2092 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2093 hpd.hpd = RADEON_HPD_1; /* ??? */ 2094 radeon_add_legacy_encoder(dev, 2095 radeon_get_encoder_enum(dev, 2096 ATOM_DEVICE_DFP2_SUPPORT, 2097 0), 2098 ATOM_DEVICE_DFP2_SUPPORT); 2099 radeon_add_legacy_encoder(dev, 2100 radeon_get_encoder_enum(dev, 2101 ATOM_DEVICE_CRT2_SUPPORT, 2102 2), 2103 ATOM_DEVICE_CRT2_SUPPORT); 2104 radeon_add_legacy_connector(dev, 0, 2105 ATOM_DEVICE_DFP2_SUPPORT | 2106 ATOM_DEVICE_CRT2_SUPPORT, 2107 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2108 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2109 &hpd); 2110 /* ADC - primary dac, internal tmds */ 2111 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2112 hpd.hpd = RADEON_HPD_2; /* ??? */ 2113 radeon_add_legacy_encoder(dev, 2114 radeon_get_encoder_enum(dev, 2115 ATOM_DEVICE_DFP1_SUPPORT, 2116 0), 2117 ATOM_DEVICE_DFP1_SUPPORT); 2118 radeon_add_legacy_encoder(dev, 2119 radeon_get_encoder_enum(dev, 2120 ATOM_DEVICE_CRT1_SUPPORT, 2121 1), 2122 ATOM_DEVICE_CRT1_SUPPORT); 2123 radeon_add_legacy_connector(dev, 1, 2124 ATOM_DEVICE_DFP1_SUPPORT | 2125 ATOM_DEVICE_CRT1_SUPPORT, 2126 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2127 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2128 &hpd); 2129 /* TV - TV DAC */ 2130 ddc_i2c.valid = false; 2131 hpd.hpd = RADEON_HPD_NONE; 2132 radeon_add_legacy_encoder(dev, 2133 radeon_get_encoder_enum(dev, 2134 ATOM_DEVICE_TV1_SUPPORT, 2135 2), 2136 ATOM_DEVICE_TV1_SUPPORT); 2137 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 2138 DRM_MODE_CONNECTOR_SVIDEO, 2139 &ddc_i2c, 2140 CONNECTOR_OBJECT_ID_SVIDEO, 2141 &hpd); 2142 break; 2143 case CT_SAM440EP: 2144 DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n", 2145 rdev->mode_info.connector_table); 2146 /* LVDS */ 2147 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); 2148 hpd.hpd = RADEON_HPD_NONE; 2149 radeon_add_legacy_encoder(dev, 2150 radeon_get_encoder_enum(dev, 2151 ATOM_DEVICE_LCD1_SUPPORT, 2152 0), 2153 ATOM_DEVICE_LCD1_SUPPORT); 2154 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 2155 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 2156 CONNECTOR_OBJECT_ID_LVDS, 2157 &hpd); 2158 /* DVI-I - secondary dac, int tmds */ 2159 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2160 hpd.hpd = RADEON_HPD_1; /* ??? */ 2161 radeon_add_legacy_encoder(dev, 2162 radeon_get_encoder_enum(dev, 2163 ATOM_DEVICE_DFP1_SUPPORT, 2164 0), 2165 ATOM_DEVICE_DFP1_SUPPORT); 2166 radeon_add_legacy_encoder(dev, 2167 radeon_get_encoder_enum(dev, 2168 ATOM_DEVICE_CRT2_SUPPORT, 2169 2), 2170 ATOM_DEVICE_CRT2_SUPPORT); 2171 radeon_add_legacy_connector(dev, 1, 2172 ATOM_DEVICE_DFP1_SUPPORT | 2173 ATOM_DEVICE_CRT2_SUPPORT, 2174 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2175 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2176 &hpd); 2177 /* VGA - primary dac */ 2178 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2179 hpd.hpd = RADEON_HPD_NONE; 2180 radeon_add_legacy_encoder(dev, 2181 radeon_get_encoder_enum(dev, 2182 ATOM_DEVICE_CRT1_SUPPORT, 2183 1), 2184 ATOM_DEVICE_CRT1_SUPPORT); 2185 radeon_add_legacy_connector(dev, 2, 2186 ATOM_DEVICE_CRT1_SUPPORT, 2187 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 2188 CONNECTOR_OBJECT_ID_VGA, 2189 &hpd); 2190 /* TV - TV DAC */ 2191 ddc_i2c.valid = false; 2192 hpd.hpd = RADEON_HPD_NONE; 2193 radeon_add_legacy_encoder(dev, 2194 radeon_get_encoder_enum(dev, 2195 ATOM_DEVICE_TV1_SUPPORT, 2196 2), 2197 ATOM_DEVICE_TV1_SUPPORT); 2198 radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT, 2199 DRM_MODE_CONNECTOR_SVIDEO, 2200 &ddc_i2c, 2201 CONNECTOR_OBJECT_ID_SVIDEO, 2202 &hpd); 2203 break; 2204 case CT_MAC_G4_SILVER: 2205 DRM_INFO("Connector Table: %d (mac g4 silver)\n", 2206 rdev->mode_info.connector_table); 2207 /* DVI-I - tv dac, int tmds */ 2208 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2209 hpd.hpd = RADEON_HPD_1; /* ??? */ 2210 radeon_add_legacy_encoder(dev, 2211 radeon_get_encoder_enum(dev, 2212 ATOM_DEVICE_DFP1_SUPPORT, 2213 0), 2214 ATOM_DEVICE_DFP1_SUPPORT); 2215 radeon_add_legacy_encoder(dev, 2216 radeon_get_encoder_enum(dev, 2217 ATOM_DEVICE_CRT2_SUPPORT, 2218 2), 2219 ATOM_DEVICE_CRT2_SUPPORT); 2220 radeon_add_legacy_connector(dev, 0, 2221 ATOM_DEVICE_DFP1_SUPPORT | 2222 ATOM_DEVICE_CRT2_SUPPORT, 2223 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2224 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2225 &hpd); 2226 /* VGA - primary dac */ 2227 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2228 hpd.hpd = RADEON_HPD_NONE; 2229 radeon_add_legacy_encoder(dev, 2230 radeon_get_encoder_enum(dev, 2231 ATOM_DEVICE_CRT1_SUPPORT, 2232 1), 2233 ATOM_DEVICE_CRT1_SUPPORT); 2234 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, 2235 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 2236 CONNECTOR_OBJECT_ID_VGA, 2237 &hpd); 2238 /* TV - TV DAC */ 2239 ddc_i2c.valid = false; 2240 hpd.hpd = RADEON_HPD_NONE; 2241 radeon_add_legacy_encoder(dev, 2242 radeon_get_encoder_enum(dev, 2243 ATOM_DEVICE_TV1_SUPPORT, 2244 2), 2245 ATOM_DEVICE_TV1_SUPPORT); 2246 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 2247 DRM_MODE_CONNECTOR_SVIDEO, 2248 &ddc_i2c, 2249 CONNECTOR_OBJECT_ID_SVIDEO, 2250 &hpd); 2251 break; 2252 default: 2253 DRM_INFO("Connector table: %d (invalid)\n", 2254 rdev->mode_info.connector_table); 2255 return false; 2256 } 2257 2258 radeon_link_encoder_connector(dev); 2259 2260 return true; 2261 } 2262 2263 static bool radeon_apply_legacy_quirks(struct drm_device *dev, 2264 int bios_index, 2265 enum radeon_combios_connector 2266 *legacy_connector, 2267 struct radeon_i2c_bus_rec *ddc_i2c, 2268 struct radeon_hpd *hpd) 2269 { 2270 2271 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, 2272 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ 2273 if (dev->pci_device == 0x515e && 2274 dev->pci_subvendor == 0x1014) { 2275 if (*legacy_connector == CONNECTOR_CRT_LEGACY && 2276 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) 2277 return false; 2278 } 2279 2280 /* X300 card with extra non-existent DVI port */ 2281 if (dev->pci_device == 0x5B60 && 2282 dev->pci_subvendor == 0x17af && 2283 dev->pci_subdevice == 0x201e && bios_index == 2) { 2284 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY) 2285 return false; 2286 } 2287 2288 return true; 2289 } 2290 2291 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev) 2292 { 2293 /* Acer 5102 has non-existent TV port */ 2294 if (dev->pci_device == 0x5975 && 2295 dev->pci_subvendor == 0x1025 && 2296 dev->pci_subdevice == 0x009f) 2297 return false; 2298 2299 /* HP dc5750 has non-existent TV port */ 2300 if (dev->pci_device == 0x5974 && 2301 dev->pci_subvendor == 0x103c && 2302 dev->pci_subdevice == 0x280a) 2303 return false; 2304 2305 /* MSI S270 has non-existent TV port */ 2306 if (dev->pci_device == 0x5955 && 2307 dev->pci_subvendor == 0x1462 && 2308 dev->pci_subdevice == 0x0131) 2309 return false; 2310 2311 return true; 2312 } 2313 2314 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d) 2315 { 2316 struct radeon_device *rdev = dev->dev_private; 2317 uint32_t ext_tmds_info; 2318 2319 if (rdev->flags & RADEON_IS_IGP) { 2320 if (is_dvi_d) 2321 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 2322 else 2323 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2324 } 2325 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 2326 if (ext_tmds_info) { 2327 uint8_t rev = RBIOS8(ext_tmds_info); 2328 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5); 2329 if (rev >= 3) { 2330 if (is_dvi_d) 2331 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 2332 else 2333 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 2334 } else { 2335 if (flags & 1) { 2336 if (is_dvi_d) 2337 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 2338 else 2339 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 2340 } 2341 } 2342 } 2343 if (is_dvi_d) 2344 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 2345 else 2346 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2347 } 2348 2349 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) 2350 { 2351 struct radeon_device *rdev = dev->dev_private; 2352 uint32_t conn_info, entry, devices; 2353 uint16_t tmp, connector_object_id; 2354 enum radeon_combios_ddc ddc_type; 2355 enum radeon_combios_connector connector; 2356 int i = 0; 2357 struct radeon_i2c_bus_rec ddc_i2c; 2358 struct radeon_hpd hpd; 2359 2360 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE); 2361 if (conn_info) { 2362 for (i = 0; i < 4; i++) { 2363 entry = conn_info + 2 + i * 2; 2364 2365 if (!RBIOS16(entry)) 2366 break; 2367 2368 tmp = RBIOS16(entry); 2369 2370 connector = (tmp >> 12) & 0xf; 2371 2372 ddc_type = (tmp >> 8) & 0xf; 2373 if (ddc_type == 5) 2374 ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev); 2375 else 2376 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0); 2377 2378 switch (connector) { 2379 case CONNECTOR_PROPRIETARY_LEGACY: 2380 case CONNECTOR_DVI_I_LEGACY: 2381 case CONNECTOR_DVI_D_LEGACY: 2382 if ((tmp >> 4) & 0x1) 2383 hpd.hpd = RADEON_HPD_2; 2384 else 2385 hpd.hpd = RADEON_HPD_1; 2386 break; 2387 default: 2388 hpd.hpd = RADEON_HPD_NONE; 2389 break; 2390 } 2391 2392 if (!radeon_apply_legacy_quirks(dev, i, &connector, 2393 &ddc_i2c, &hpd)) 2394 continue; 2395 2396 switch (connector) { 2397 case CONNECTOR_PROPRIETARY_LEGACY: 2398 if ((tmp >> 4) & 0x1) 2399 devices = ATOM_DEVICE_DFP2_SUPPORT; 2400 else 2401 devices = ATOM_DEVICE_DFP1_SUPPORT; 2402 radeon_add_legacy_encoder(dev, 2403 radeon_get_encoder_enum 2404 (dev, devices, 0), 2405 devices); 2406 radeon_add_legacy_connector(dev, i, devices, 2407 legacy_connector_convert 2408 [connector], 2409 &ddc_i2c, 2410 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 2411 &hpd); 2412 break; 2413 case CONNECTOR_CRT_LEGACY: 2414 if (tmp & 0x1) { 2415 devices = ATOM_DEVICE_CRT2_SUPPORT; 2416 radeon_add_legacy_encoder(dev, 2417 radeon_get_encoder_enum 2418 (dev, 2419 ATOM_DEVICE_CRT2_SUPPORT, 2420 2), 2421 ATOM_DEVICE_CRT2_SUPPORT); 2422 } else { 2423 devices = ATOM_DEVICE_CRT1_SUPPORT; 2424 radeon_add_legacy_encoder(dev, 2425 radeon_get_encoder_enum 2426 (dev, 2427 ATOM_DEVICE_CRT1_SUPPORT, 2428 1), 2429 ATOM_DEVICE_CRT1_SUPPORT); 2430 } 2431 radeon_add_legacy_connector(dev, 2432 i, 2433 devices, 2434 legacy_connector_convert 2435 [connector], 2436 &ddc_i2c, 2437 CONNECTOR_OBJECT_ID_VGA, 2438 &hpd); 2439 break; 2440 case CONNECTOR_DVI_I_LEGACY: 2441 devices = 0; 2442 if (tmp & 0x1) { 2443 devices |= ATOM_DEVICE_CRT2_SUPPORT; 2444 radeon_add_legacy_encoder(dev, 2445 radeon_get_encoder_enum 2446 (dev, 2447 ATOM_DEVICE_CRT2_SUPPORT, 2448 2), 2449 ATOM_DEVICE_CRT2_SUPPORT); 2450 } else { 2451 devices |= ATOM_DEVICE_CRT1_SUPPORT; 2452 radeon_add_legacy_encoder(dev, 2453 radeon_get_encoder_enum 2454 (dev, 2455 ATOM_DEVICE_CRT1_SUPPORT, 2456 1), 2457 ATOM_DEVICE_CRT1_SUPPORT); 2458 } 2459 /* RV100 board with external TDMS bit mis-set. 2460 * Actually uses internal TMDS, clear the bit. 2461 */ 2462 if (dev->pci_device == 0x5159 && 2463 dev->pci_subvendor == 0x1014 && 2464 dev->pci_subdevice == 0x029A) { 2465 tmp &= ~(1 << 4); 2466 } 2467 if ((tmp >> 4) & 0x1) { 2468 devices |= ATOM_DEVICE_DFP2_SUPPORT; 2469 radeon_add_legacy_encoder(dev, 2470 radeon_get_encoder_enum 2471 (dev, 2472 ATOM_DEVICE_DFP2_SUPPORT, 2473 0), 2474 ATOM_DEVICE_DFP2_SUPPORT); 2475 connector_object_id = combios_check_dl_dvi(dev, 0); 2476 } else { 2477 devices |= ATOM_DEVICE_DFP1_SUPPORT; 2478 radeon_add_legacy_encoder(dev, 2479 radeon_get_encoder_enum 2480 (dev, 2481 ATOM_DEVICE_DFP1_SUPPORT, 2482 0), 2483 ATOM_DEVICE_DFP1_SUPPORT); 2484 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2485 } 2486 radeon_add_legacy_connector(dev, 2487 i, 2488 devices, 2489 legacy_connector_convert 2490 [connector], 2491 &ddc_i2c, 2492 connector_object_id, 2493 &hpd); 2494 break; 2495 case CONNECTOR_DVI_D_LEGACY: 2496 if ((tmp >> 4) & 0x1) { 2497 devices = ATOM_DEVICE_DFP2_SUPPORT; 2498 connector_object_id = combios_check_dl_dvi(dev, 1); 2499 } else { 2500 devices = ATOM_DEVICE_DFP1_SUPPORT; 2501 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2502 } 2503 radeon_add_legacy_encoder(dev, 2504 radeon_get_encoder_enum 2505 (dev, devices, 0), 2506 devices); 2507 radeon_add_legacy_connector(dev, i, devices, 2508 legacy_connector_convert 2509 [connector], 2510 &ddc_i2c, 2511 connector_object_id, 2512 &hpd); 2513 break; 2514 case CONNECTOR_CTV_LEGACY: 2515 case CONNECTOR_STV_LEGACY: 2516 radeon_add_legacy_encoder(dev, 2517 radeon_get_encoder_enum 2518 (dev, 2519 ATOM_DEVICE_TV1_SUPPORT, 2520 2), 2521 ATOM_DEVICE_TV1_SUPPORT); 2522 radeon_add_legacy_connector(dev, i, 2523 ATOM_DEVICE_TV1_SUPPORT, 2524 legacy_connector_convert 2525 [connector], 2526 &ddc_i2c, 2527 CONNECTOR_OBJECT_ID_SVIDEO, 2528 &hpd); 2529 break; 2530 default: 2531 DRM_ERROR("Unknown connector type: %d\n", 2532 connector); 2533 continue; 2534 } 2535 2536 } 2537 } else { 2538 uint16_t tmds_info = 2539 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 2540 if (tmds_info) { 2541 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n"); 2542 2543 radeon_add_legacy_encoder(dev, 2544 radeon_get_encoder_enum(dev, 2545 ATOM_DEVICE_CRT1_SUPPORT, 2546 1), 2547 ATOM_DEVICE_CRT1_SUPPORT); 2548 radeon_add_legacy_encoder(dev, 2549 radeon_get_encoder_enum(dev, 2550 ATOM_DEVICE_DFP1_SUPPORT, 2551 0), 2552 ATOM_DEVICE_DFP1_SUPPORT); 2553 2554 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2555 hpd.hpd = RADEON_HPD_1; 2556 radeon_add_legacy_connector(dev, 2557 0, 2558 ATOM_DEVICE_CRT1_SUPPORT | 2559 ATOM_DEVICE_DFP1_SUPPORT, 2560 DRM_MODE_CONNECTOR_DVII, 2561 &ddc_i2c, 2562 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2563 &hpd); 2564 } else { 2565 uint16_t crt_info = 2566 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 2567 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n"); 2568 if (crt_info) { 2569 radeon_add_legacy_encoder(dev, 2570 radeon_get_encoder_enum(dev, 2571 ATOM_DEVICE_CRT1_SUPPORT, 2572 1), 2573 ATOM_DEVICE_CRT1_SUPPORT); 2574 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2575 hpd.hpd = RADEON_HPD_NONE; 2576 radeon_add_legacy_connector(dev, 2577 0, 2578 ATOM_DEVICE_CRT1_SUPPORT, 2579 DRM_MODE_CONNECTOR_VGA, 2580 &ddc_i2c, 2581 CONNECTOR_OBJECT_ID_VGA, 2582 &hpd); 2583 } else { 2584 DRM_DEBUG_KMS("No connector info found\n"); 2585 return false; 2586 } 2587 } 2588 } 2589 2590 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) { 2591 uint16_t lcd_info = 2592 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 2593 if (lcd_info) { 2594 uint16_t lcd_ddc_info = 2595 combios_get_table_offset(dev, 2596 COMBIOS_LCD_DDC_INFO_TABLE); 2597 2598 radeon_add_legacy_encoder(dev, 2599 radeon_get_encoder_enum(dev, 2600 ATOM_DEVICE_LCD1_SUPPORT, 2601 0), 2602 ATOM_DEVICE_LCD1_SUPPORT); 2603 2604 if (lcd_ddc_info) { 2605 ddc_type = RBIOS8(lcd_ddc_info + 2); 2606 switch (ddc_type) { 2607 case DDC_LCD: 2608 ddc_i2c = 2609 combios_setup_i2c_bus(rdev, 2610 DDC_LCD, 2611 RBIOS32(lcd_ddc_info + 3), 2612 RBIOS32(lcd_ddc_info + 7)); 2613 radeon_i2c_add(rdev, &ddc_i2c, "LCD"); 2614 break; 2615 case DDC_GPIO: 2616 ddc_i2c = 2617 combios_setup_i2c_bus(rdev, 2618 DDC_GPIO, 2619 RBIOS32(lcd_ddc_info + 3), 2620 RBIOS32(lcd_ddc_info + 7)); 2621 radeon_i2c_add(rdev, &ddc_i2c, "LCD"); 2622 break; 2623 default: 2624 ddc_i2c = 2625 combios_setup_i2c_bus(rdev, ddc_type, 0, 0); 2626 break; 2627 } 2628 DRM_DEBUG_KMS("LCD DDC Info Table found!\n"); 2629 } else 2630 ddc_i2c.valid = false; 2631 2632 hpd.hpd = RADEON_HPD_NONE; 2633 radeon_add_legacy_connector(dev, 2634 5, 2635 ATOM_DEVICE_LCD1_SUPPORT, 2636 DRM_MODE_CONNECTOR_LVDS, 2637 &ddc_i2c, 2638 CONNECTOR_OBJECT_ID_LVDS, 2639 &hpd); 2640 } 2641 } 2642 2643 /* check TV table */ 2644 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 2645 uint32_t tv_info = 2646 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 2647 if (tv_info) { 2648 if (RBIOS8(tv_info + 6) == 'T') { 2649 if (radeon_apply_legacy_tv_quirks(dev)) { 2650 hpd.hpd = RADEON_HPD_NONE; 2651 ddc_i2c.valid = false; 2652 radeon_add_legacy_encoder(dev, 2653 radeon_get_encoder_enum 2654 (dev, 2655 ATOM_DEVICE_TV1_SUPPORT, 2656 2), 2657 ATOM_DEVICE_TV1_SUPPORT); 2658 radeon_add_legacy_connector(dev, 6, 2659 ATOM_DEVICE_TV1_SUPPORT, 2660 DRM_MODE_CONNECTOR_SVIDEO, 2661 &ddc_i2c, 2662 CONNECTOR_OBJECT_ID_SVIDEO, 2663 &hpd); 2664 } 2665 } 2666 } 2667 } 2668 2669 radeon_link_encoder_connector(dev); 2670 2671 return true; 2672 } 2673 2674 static const char *thermal_controller_names[] = { 2675 "NONE", 2676 "lm63", 2677 "adm1032", 2678 }; 2679 2680 void radeon_combios_get_power_modes(struct radeon_device *rdev) 2681 { 2682 struct drm_device *dev = rdev->ddev; 2683 u16 offset, misc, misc2 = 0; 2684 u8 rev, blocks, tmp; 2685 int state_index = 0; 2686 struct radeon_i2c_bus_rec i2c_bus; 2687 2688 rdev->pm.default_power_state_index = -1; 2689 2690 /* allocate 2 power states */ 2691 rdev->pm.power_state = kmalloc(sizeof(struct radeon_power_state) * 2, 2692 DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 2693 if (rdev->pm.power_state) { 2694 /* allocate 1 clock mode per state */ 2695 rdev->pm.power_state[0].clock_info = 2696 kmalloc(sizeof(struct radeon_pm_clock_info) * 1, 2697 DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 2698 rdev->pm.power_state[1].clock_info = 2699 kmalloc(sizeof(struct radeon_pm_clock_info) * 1, 2700 DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 2701 if (!rdev->pm.power_state[0].clock_info || 2702 !rdev->pm.power_state[1].clock_info) 2703 goto pm_failed; 2704 } else 2705 goto pm_failed; 2706 2707 /* check for a thermal chip */ 2708 offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE); 2709 if (offset) { 2710 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0; 2711 2712 rev = RBIOS8(offset); 2713 2714 if (rev == 0) { 2715 thermal_controller = RBIOS8(offset + 3); 2716 gpio = RBIOS8(offset + 4) & 0x3f; 2717 i2c_addr = RBIOS8(offset + 5); 2718 } else if (rev == 1) { 2719 thermal_controller = RBIOS8(offset + 4); 2720 gpio = RBIOS8(offset + 5) & 0x3f; 2721 i2c_addr = RBIOS8(offset + 6); 2722 } else if (rev == 2) { 2723 thermal_controller = RBIOS8(offset + 4); 2724 gpio = RBIOS8(offset + 5) & 0x3f; 2725 i2c_addr = RBIOS8(offset + 6); 2726 clk_bit = RBIOS8(offset + 0xa); 2727 data_bit = RBIOS8(offset + 0xb); 2728 } 2729 if ((thermal_controller > 0) && (thermal_controller < 3)) { 2730 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 2731 thermal_controller_names[thermal_controller], 2732 i2c_addr >> 1); 2733 if (gpio == DDC_LCD) { 2734 /* MM i2c */ 2735 i2c_bus.valid = true; 2736 i2c_bus.hw_capable = true; 2737 i2c_bus.mm_i2c = true; 2738 i2c_bus.i2c_id = 0xa0; 2739 } else if (gpio == DDC_GPIO) 2740 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit); 2741 else 2742 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); 2743 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2744 if (rdev->pm.i2c_bus) { 2745 #ifdef DUMBBELL_WIP 2746 struct i2c_board_info info = { }; 2747 const char *name = thermal_controller_names[thermal_controller]; 2748 info.addr = i2c_addr >> 1; 2749 strlcpy(info.type, name, sizeof(info.type)); 2750 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); 2751 #endif /* DUMBBELL_WIP */ 2752 } 2753 } 2754 } else { 2755 /* boards with a thermal chip, but no overdrive table */ 2756 2757 /* Asus 9600xt has an f75375 on the monid bus */ 2758 if ((dev->pci_device == 0x4152) && 2759 (dev->pci_subvendor == 0x1043) && 2760 (dev->pci_subdevice == 0xc002)) { 2761 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 2762 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2763 if (rdev->pm.i2c_bus) { 2764 #ifdef DUMBBELL_WIP 2765 struct i2c_board_info info = { }; 2766 const char *name = "f75375"; 2767 info.addr = 0x28; 2768 strlcpy(info.type, name, sizeof(info.type)); 2769 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); 2770 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 2771 name, info.addr); 2772 #endif /* DUMBBELL_WIP */ 2773 } 2774 } 2775 } 2776 2777 if (rdev->flags & RADEON_IS_MOBILITY) { 2778 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE); 2779 if (offset) { 2780 rev = RBIOS8(offset); 2781 blocks = RBIOS8(offset + 0x2); 2782 /* power mode 0 tends to be the only valid one */ 2783 rdev->pm.power_state[state_index].num_clock_modes = 1; 2784 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2); 2785 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6); 2786 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2787 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2788 goto default_mode; 2789 rdev->pm.power_state[state_index].type = 2790 POWER_STATE_TYPE_BATTERY; 2791 misc = RBIOS16(offset + 0x5 + 0x0); 2792 if (rev > 4) 2793 misc2 = RBIOS16(offset + 0x5 + 0xe); 2794 rdev->pm.power_state[state_index].misc = misc; 2795 rdev->pm.power_state[state_index].misc2 = misc2; 2796 if (misc & 0x4) { 2797 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO; 2798 if (misc & 0x8) 2799 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2800 true; 2801 else 2802 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2803 false; 2804 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true; 2805 if (rev < 6) { 2806 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = 2807 RBIOS16(offset + 0x5 + 0xb) * 4; 2808 tmp = RBIOS8(offset + 0x5 + 0xd); 2809 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); 2810 } else { 2811 u8 entries = RBIOS8(offset + 0x5 + 0xb); 2812 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc); 2813 if (entries && voltage_table_offset) { 2814 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = 2815 RBIOS16(voltage_table_offset) * 4; 2816 tmp = RBIOS8(voltage_table_offset + 0x2); 2817 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); 2818 } else 2819 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false; 2820 } 2821 switch ((misc2 & 0x700) >> 8) { 2822 case 0: 2823 default: 2824 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0; 2825 break; 2826 case 1: 2827 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33; 2828 break; 2829 case 2: 2830 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66; 2831 break; 2832 case 3: 2833 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99; 2834 break; 2835 case 4: 2836 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132; 2837 break; 2838 } 2839 } else 2840 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2841 if (rev > 6) 2842 rdev->pm.power_state[state_index].pcie_lanes = 2843 RBIOS8(offset + 0x5 + 0x10); 2844 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2845 state_index++; 2846 } else { 2847 /* XXX figure out some good default low power mode for mobility cards w/out power tables */ 2848 } 2849 } else { 2850 /* XXX figure out some good default low power mode for desktop cards */ 2851 } 2852 2853 default_mode: 2854 /* add the default mode */ 2855 rdev->pm.power_state[state_index].type = 2856 POWER_STATE_TYPE_DEFAULT; 2857 rdev->pm.power_state[state_index].num_clock_modes = 1; 2858 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; 2859 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; 2860 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; 2861 if ((state_index > 0) && 2862 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO)) 2863 rdev->pm.power_state[state_index].clock_info[0].voltage = 2864 rdev->pm.power_state[0].clock_info[0].voltage; 2865 else 2866 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2867 rdev->pm.power_state[state_index].pcie_lanes = 16; 2868 rdev->pm.power_state[state_index].flags = 0; 2869 rdev->pm.default_power_state_index = state_index; 2870 rdev->pm.num_power_states = state_index + 1; 2871 2872 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2873 rdev->pm.current_clock_mode_index = 0; 2874 return; 2875 2876 pm_failed: 2877 rdev->pm.default_power_state_index = state_index; 2878 rdev->pm.num_power_states = 0; 2879 2880 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2881 rdev->pm.current_clock_mode_index = 0; 2882 } 2883 2884 void radeon_external_tmds_setup(struct drm_encoder *encoder) 2885 { 2886 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2887 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2888 2889 if (!tmds) 2890 return; 2891 2892 switch (tmds->dvo_chip) { 2893 case DVO_SIL164: 2894 /* sil 164 */ 2895 radeon_i2c_put_byte(tmds->i2c_bus, 2896 tmds->slave_addr, 2897 0x08, 0x30); 2898 radeon_i2c_put_byte(tmds->i2c_bus, 2899 tmds->slave_addr, 2900 0x09, 0x00); 2901 radeon_i2c_put_byte(tmds->i2c_bus, 2902 tmds->slave_addr, 2903 0x0a, 0x90); 2904 radeon_i2c_put_byte(tmds->i2c_bus, 2905 tmds->slave_addr, 2906 0x0c, 0x89); 2907 radeon_i2c_put_byte(tmds->i2c_bus, 2908 tmds->slave_addr, 2909 0x08, 0x3b); 2910 break; 2911 case DVO_SIL1178: 2912 /* sil 1178 - untested */ 2913 /* 2914 * 0x0f, 0x44 2915 * 0x0f, 0x4c 2916 * 0x0e, 0x01 2917 * 0x0a, 0x80 2918 * 0x09, 0x30 2919 * 0x0c, 0xc9 2920 * 0x0d, 0x70 2921 * 0x08, 0x32 2922 * 0x08, 0x33 2923 */ 2924 break; 2925 default: 2926 break; 2927 } 2928 2929 } 2930 2931 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder) 2932 { 2933 struct drm_device *dev = encoder->dev; 2934 struct radeon_device *rdev = dev->dev_private; 2935 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2936 uint16_t offset; 2937 uint8_t blocks, slave_addr, rev; 2938 uint32_t index, id; 2939 uint32_t reg, val, and_mask, or_mask; 2940 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2941 2942 if (!tmds) 2943 return false; 2944 2945 if (rdev->flags & RADEON_IS_IGP) { 2946 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE); 2947 rev = RBIOS8(offset); 2948 if (offset) { 2949 rev = RBIOS8(offset); 2950 if (rev > 1) { 2951 blocks = RBIOS8(offset + 3); 2952 index = offset + 4; 2953 while (blocks > 0) { 2954 id = RBIOS16(index); 2955 index += 2; 2956 switch (id >> 13) { 2957 case 0: 2958 reg = (id & 0x1fff) * 4; 2959 val = RBIOS32(index); 2960 index += 4; 2961 WREG32(reg, val); 2962 break; 2963 case 2: 2964 reg = (id & 0x1fff) * 4; 2965 and_mask = RBIOS32(index); 2966 index += 4; 2967 or_mask = RBIOS32(index); 2968 index += 4; 2969 val = RREG32(reg); 2970 val = (val & and_mask) | or_mask; 2971 WREG32(reg, val); 2972 break; 2973 case 3: 2974 val = RBIOS16(index); 2975 index += 2; 2976 DRM_UDELAY(val); 2977 break; 2978 case 4: 2979 val = RBIOS16(index); 2980 index += 2; 2981 DRM_MDELAY(val); 2982 break; 2983 case 6: 2984 slave_addr = id & 0xff; 2985 slave_addr >>= 1; /* 7 bit addressing */ 2986 index++; 2987 reg = RBIOS8(index); 2988 index++; 2989 val = RBIOS8(index); 2990 index++; 2991 radeon_i2c_put_byte(tmds->i2c_bus, 2992 slave_addr, 2993 reg, val); 2994 break; 2995 default: 2996 DRM_ERROR("Unknown id %d\n", id >> 13); 2997 break; 2998 } 2999 blocks--; 3000 } 3001 return true; 3002 } 3003 } 3004 } else { 3005 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 3006 if (offset) { 3007 index = offset + 10; 3008 id = RBIOS16(index); 3009 while (id != 0xffff) { 3010 index += 2; 3011 switch (id >> 13) { 3012 case 0: 3013 reg = (id & 0x1fff) * 4; 3014 val = RBIOS32(index); 3015 WREG32(reg, val); 3016 break; 3017 case 2: 3018 reg = (id & 0x1fff) * 4; 3019 and_mask = RBIOS32(index); 3020 index += 4; 3021 or_mask = RBIOS32(index); 3022 index += 4; 3023 val = RREG32(reg); 3024 val = (val & and_mask) | or_mask; 3025 WREG32(reg, val); 3026 break; 3027 case 4: 3028 val = RBIOS16(index); 3029 index += 2; 3030 DRM_UDELAY(val); 3031 break; 3032 case 5: 3033 reg = id & 0x1fff; 3034 and_mask = RBIOS32(index); 3035 index += 4; 3036 or_mask = RBIOS32(index); 3037 index += 4; 3038 val = RREG32_PLL(reg); 3039 val = (val & and_mask) | or_mask; 3040 WREG32_PLL(reg, val); 3041 break; 3042 case 6: 3043 reg = id & 0x1fff; 3044 val = RBIOS8(index); 3045 index += 1; 3046 radeon_i2c_put_byte(tmds->i2c_bus, 3047 tmds->slave_addr, 3048 reg, val); 3049 break; 3050 default: 3051 DRM_ERROR("Unknown id %d\n", id >> 13); 3052 break; 3053 } 3054 id = RBIOS16(index); 3055 } 3056 return true; 3057 } 3058 } 3059 return false; 3060 } 3061 3062 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset) 3063 { 3064 struct radeon_device *rdev = dev->dev_private; 3065 3066 if (offset) { 3067 while (RBIOS16(offset)) { 3068 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13); 3069 uint32_t addr = (RBIOS16(offset) & 0x1fff); 3070 uint32_t val, and_mask, or_mask; 3071 uint32_t tmp; 3072 3073 offset += 2; 3074 switch (cmd) { 3075 case 0: 3076 val = RBIOS32(offset); 3077 offset += 4; 3078 WREG32(addr, val); 3079 break; 3080 case 1: 3081 val = RBIOS32(offset); 3082 offset += 4; 3083 WREG32(addr, val); 3084 break; 3085 case 2: 3086 and_mask = RBIOS32(offset); 3087 offset += 4; 3088 or_mask = RBIOS32(offset); 3089 offset += 4; 3090 tmp = RREG32(addr); 3091 tmp &= and_mask; 3092 tmp |= or_mask; 3093 WREG32(addr, tmp); 3094 break; 3095 case 3: 3096 and_mask = RBIOS32(offset); 3097 offset += 4; 3098 or_mask = RBIOS32(offset); 3099 offset += 4; 3100 tmp = RREG32(addr); 3101 tmp &= and_mask; 3102 tmp |= or_mask; 3103 WREG32(addr, tmp); 3104 break; 3105 case 4: 3106 val = RBIOS16(offset); 3107 offset += 2; 3108 DRM_UDELAY(val); 3109 break; 3110 case 5: 3111 val = RBIOS16(offset); 3112 offset += 2; 3113 switch (addr) { 3114 case 8: 3115 while (val--) { 3116 if (! 3117 (RREG32_PLL 3118 (RADEON_CLK_PWRMGT_CNTL) & 3119 RADEON_MC_BUSY)) 3120 break; 3121 } 3122 break; 3123 case 9: 3124 while (val--) { 3125 if ((RREG32(RADEON_MC_STATUS) & 3126 RADEON_MC_IDLE)) 3127 break; 3128 } 3129 break; 3130 default: 3131 break; 3132 } 3133 break; 3134 default: 3135 break; 3136 } 3137 } 3138 } 3139 } 3140 3141 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset) 3142 { 3143 struct radeon_device *rdev = dev->dev_private; 3144 3145 if (offset) { 3146 while (RBIOS8(offset)) { 3147 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6); 3148 uint8_t addr = (RBIOS8(offset) & 0x3f); 3149 uint32_t val, shift, tmp; 3150 uint32_t and_mask, or_mask; 3151 3152 offset++; 3153 switch (cmd) { 3154 case 0: 3155 val = RBIOS32(offset); 3156 offset += 4; 3157 WREG32_PLL(addr, val); 3158 break; 3159 case 1: 3160 shift = RBIOS8(offset) * 8; 3161 offset++; 3162 and_mask = RBIOS8(offset) << shift; 3163 and_mask |= ~(0xff << shift); 3164 offset++; 3165 or_mask = RBIOS8(offset) << shift; 3166 offset++; 3167 tmp = RREG32_PLL(addr); 3168 tmp &= and_mask; 3169 tmp |= or_mask; 3170 WREG32_PLL(addr, tmp); 3171 break; 3172 case 2: 3173 case 3: 3174 tmp = 1000; 3175 switch (addr) { 3176 case 1: 3177 DRM_UDELAY(150); 3178 break; 3179 case 2: 3180 DRM_MDELAY(1); 3181 break; 3182 case 3: 3183 while (tmp--) { 3184 if (! 3185 (RREG32_PLL 3186 (RADEON_CLK_PWRMGT_CNTL) & 3187 RADEON_MC_BUSY)) 3188 break; 3189 } 3190 break; 3191 case 4: 3192 while (tmp--) { 3193 if (RREG32_PLL 3194 (RADEON_CLK_PWRMGT_CNTL) & 3195 RADEON_DLL_READY) 3196 break; 3197 } 3198 break; 3199 case 5: 3200 tmp = 3201 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); 3202 if (tmp & RADEON_CG_NO1_DEBUG_0) { 3203 #if 0 3204 uint32_t mclk_cntl = 3205 RREG32_PLL 3206 (RADEON_MCLK_CNTL); 3207 mclk_cntl &= 0xffff0000; 3208 /*mclk_cntl |= 0x00001111;*//* ??? */ 3209 WREG32_PLL(RADEON_MCLK_CNTL, 3210 mclk_cntl); 3211 DRM_MDELAY(10); 3212 #endif 3213 WREG32_PLL 3214 (RADEON_CLK_PWRMGT_CNTL, 3215 tmp & 3216 ~RADEON_CG_NO1_DEBUG_0); 3217 DRM_MDELAY(10); 3218 } 3219 break; 3220 default: 3221 break; 3222 } 3223 break; 3224 default: 3225 break; 3226 } 3227 } 3228 } 3229 } 3230 3231 static void combios_parse_ram_reset_table(struct drm_device *dev, 3232 uint16_t offset) 3233 { 3234 struct radeon_device *rdev = dev->dev_private; 3235 uint32_t tmp; 3236 3237 if (offset) { 3238 uint8_t val = RBIOS8(offset); 3239 while (val != 0xff) { 3240 offset++; 3241 3242 if (val == 0x0f) { 3243 uint32_t channel_complete_mask; 3244 3245 if (ASIC_IS_R300(rdev)) 3246 channel_complete_mask = 3247 R300_MEM_PWRUP_COMPLETE; 3248 else 3249 channel_complete_mask = 3250 RADEON_MEM_PWRUP_COMPLETE; 3251 tmp = 20000; 3252 while (tmp--) { 3253 if ((RREG32(RADEON_MEM_STR_CNTL) & 3254 channel_complete_mask) == 3255 channel_complete_mask) 3256 break; 3257 } 3258 } else { 3259 uint32_t or_mask = RBIOS16(offset); 3260 offset += 2; 3261 3262 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 3263 tmp &= RADEON_SDRAM_MODE_MASK; 3264 tmp |= or_mask; 3265 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 3266 3267 or_mask = val << 24; 3268 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 3269 tmp &= RADEON_B3MEM_RESET_MASK; 3270 tmp |= or_mask; 3271 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 3272 } 3273 val = RBIOS8(offset); 3274 } 3275 } 3276 } 3277 3278 static uint32_t combios_detect_ram(struct drm_device *dev, int ram, 3279 int mem_addr_mapping) 3280 { 3281 struct radeon_device *rdev = dev->dev_private; 3282 uint32_t mem_cntl; 3283 uint32_t mem_size; 3284 uint32_t addr = 0; 3285 3286 mem_cntl = RREG32(RADEON_MEM_CNTL); 3287 if (mem_cntl & RV100_HALF_MODE) 3288 ram /= 2; 3289 mem_size = ram; 3290 mem_cntl &= ~(0xff << 8); 3291 mem_cntl |= (mem_addr_mapping & 0xff) << 8; 3292 WREG32(RADEON_MEM_CNTL, mem_cntl); 3293 RREG32(RADEON_MEM_CNTL); 3294 3295 /* sdram reset ? */ 3296 3297 /* something like this???? */ 3298 while (ram--) { 3299 addr = ram * 1024 * 1024; 3300 /* write to each page */ 3301 WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef); 3302 /* read back and verify */ 3303 if (RREG32_IDX((addr) | RADEON_MM_APER) != 0xdeadbeef) 3304 return 0; 3305 } 3306 3307 return mem_size; 3308 } 3309 3310 static void combios_write_ram_size(struct drm_device *dev) 3311 { 3312 struct radeon_device *rdev = dev->dev_private; 3313 uint8_t rev; 3314 uint16_t offset; 3315 uint32_t mem_size = 0; 3316 uint32_t mem_cntl = 0; 3317 3318 /* should do something smarter here I guess... */ 3319 if (rdev->flags & RADEON_IS_IGP) 3320 return; 3321 3322 /* first check detected mem table */ 3323 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE); 3324 if (offset) { 3325 rev = RBIOS8(offset); 3326 if (rev < 3) { 3327 mem_cntl = RBIOS32(offset + 1); 3328 mem_size = RBIOS16(offset + 5); 3329 if ((rdev->family < CHIP_R200) && 3330 !ASIC_IS_RN50(rdev)) 3331 WREG32(RADEON_MEM_CNTL, mem_cntl); 3332 } 3333 } 3334 3335 if (!mem_size) { 3336 offset = 3337 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 3338 if (offset) { 3339 rev = RBIOS8(offset - 1); 3340 if (rev < 1) { 3341 if ((rdev->family < CHIP_R200) 3342 && !ASIC_IS_RN50(rdev)) { 3343 int ram = 0; 3344 int mem_addr_mapping = 0; 3345 3346 while (RBIOS8(offset)) { 3347 ram = RBIOS8(offset); 3348 mem_addr_mapping = 3349 RBIOS8(offset + 1); 3350 if (mem_addr_mapping != 0x25) 3351 ram *= 2; 3352 mem_size = 3353 combios_detect_ram(dev, ram, 3354 mem_addr_mapping); 3355 if (mem_size) 3356 break; 3357 offset += 2; 3358 } 3359 } else 3360 mem_size = RBIOS8(offset); 3361 } else { 3362 mem_size = RBIOS8(offset); 3363 mem_size *= 2; /* convert to MB */ 3364 } 3365 } 3366 } 3367 3368 mem_size *= (1024 * 1024); /* convert to bytes */ 3369 WREG32(RADEON_CONFIG_MEMSIZE, mem_size); 3370 } 3371 3372 void radeon_combios_asic_init(struct drm_device *dev) 3373 { 3374 struct radeon_device *rdev = dev->dev_private; 3375 uint16_t table; 3376 3377 /* port hardcoded mac stuff from radeonfb */ 3378 if (rdev->bios == NULL) 3379 return; 3380 3381 /* ASIC INIT 1 */ 3382 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE); 3383 if (table) 3384 combios_parse_mmio_table(dev, table); 3385 3386 /* PLL INIT */ 3387 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE); 3388 if (table) 3389 combios_parse_pll_table(dev, table); 3390 3391 /* ASIC INIT 2 */ 3392 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE); 3393 if (table) 3394 combios_parse_mmio_table(dev, table); 3395 3396 if (!(rdev->flags & RADEON_IS_IGP)) { 3397 /* ASIC INIT 4 */ 3398 table = 3399 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE); 3400 if (table) 3401 combios_parse_mmio_table(dev, table); 3402 3403 /* RAM RESET */ 3404 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE); 3405 if (table) 3406 combios_parse_ram_reset_table(dev, table); 3407 3408 /* ASIC INIT 3 */ 3409 table = 3410 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE); 3411 if (table) 3412 combios_parse_mmio_table(dev, table); 3413 3414 /* write CONFIG_MEMSIZE */ 3415 combios_write_ram_size(dev); 3416 } 3417 3418 /* quirk for rs4xx HP nx6125 laptop to make it resume 3419 * - it hangs on resume inside the dynclk 1 table. 3420 */ 3421 if (rdev->family == CHIP_RS480 && 3422 dev->pci_subvendor == 0x103c && 3423 dev->pci_subdevice == 0x308b) 3424 return; 3425 3426 /* quirk for rs4xx HP dv5000 laptop to make it resume 3427 * - it hangs on resume inside the dynclk 1 table. 3428 */ 3429 if (rdev->family == CHIP_RS480 && 3430 dev->pci_subvendor == 0x103c && 3431 dev->pci_subdevice == 0x30a4) 3432 return; 3433 3434 /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume 3435 * - it hangs on resume inside the dynclk 1 table. 3436 */ 3437 if (rdev->family == CHIP_RS480 && 3438 dev->pci_subvendor == 0x103c && 3439 dev->pci_subdevice == 0x30ae) 3440 return; 3441 3442 /* DYN CLK 1 */ 3443 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); 3444 if (table) 3445 combios_parse_pll_table(dev, table); 3446 3447 } 3448 3449 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev) 3450 { 3451 struct radeon_device *rdev = dev->dev_private; 3452 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch; 3453 3454 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 3455 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3456 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH); 3457 3458 /* let the bios control the backlight */ 3459 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN; 3460 3461 /* tell the bios not to handle mode switching */ 3462 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS | 3463 RADEON_ACC_MODE_CHANGE); 3464 3465 /* tell the bios a driver is loaded */ 3466 bios_7_scratch |= RADEON_DRV_LOADED; 3467 3468 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); 3469 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3470 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch); 3471 } 3472 3473 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock) 3474 { 3475 struct drm_device *dev = encoder->dev; 3476 struct radeon_device *rdev = dev->dev_private; 3477 uint32_t bios_6_scratch; 3478 3479 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3480 3481 if (lock) 3482 bios_6_scratch |= RADEON_DRIVER_CRITICAL; 3483 else 3484 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL; 3485 3486 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3487 } 3488 3489 void 3490 radeon_combios_connected_scratch_regs(struct drm_connector *connector, 3491 struct drm_encoder *encoder, 3492 bool connected) 3493 { 3494 struct drm_device *dev = connector->dev; 3495 struct radeon_device *rdev = dev->dev_private; 3496 struct radeon_connector *radeon_connector = 3497 to_radeon_connector(connector); 3498 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3499 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH); 3500 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 3501 3502 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 3503 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 3504 if (connected) { 3505 DRM_DEBUG_KMS("TV1 connected\n"); 3506 /* fix me */ 3507 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO; 3508 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */ 3509 bios_5_scratch |= RADEON_TV1_ON; 3510 bios_5_scratch |= RADEON_ACC_REQ_TV1; 3511 } else { 3512 DRM_DEBUG_KMS("TV1 disconnected\n"); 3513 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK; 3514 bios_5_scratch &= ~RADEON_TV1_ON; 3515 bios_5_scratch &= ~RADEON_ACC_REQ_TV1; 3516 } 3517 } 3518 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 3519 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 3520 if (connected) { 3521 DRM_DEBUG_KMS("LCD1 connected\n"); 3522 bios_4_scratch |= RADEON_LCD1_ATTACHED; 3523 bios_5_scratch |= RADEON_LCD1_ON; 3524 bios_5_scratch |= RADEON_ACC_REQ_LCD1; 3525 } else { 3526 DRM_DEBUG_KMS("LCD1 disconnected\n"); 3527 bios_4_scratch &= ~RADEON_LCD1_ATTACHED; 3528 bios_5_scratch &= ~RADEON_LCD1_ON; 3529 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1; 3530 } 3531 } 3532 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 3533 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 3534 if (connected) { 3535 DRM_DEBUG_KMS("CRT1 connected\n"); 3536 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR; 3537 bios_5_scratch |= RADEON_CRT1_ON; 3538 bios_5_scratch |= RADEON_ACC_REQ_CRT1; 3539 } else { 3540 DRM_DEBUG_KMS("CRT1 disconnected\n"); 3541 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK; 3542 bios_5_scratch &= ~RADEON_CRT1_ON; 3543 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1; 3544 } 3545 } 3546 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 3547 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 3548 if (connected) { 3549 DRM_DEBUG_KMS("CRT2 connected\n"); 3550 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR; 3551 bios_5_scratch |= RADEON_CRT2_ON; 3552 bios_5_scratch |= RADEON_ACC_REQ_CRT2; 3553 } else { 3554 DRM_DEBUG_KMS("CRT2 disconnected\n"); 3555 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK; 3556 bios_5_scratch &= ~RADEON_CRT2_ON; 3557 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2; 3558 } 3559 } 3560 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 3561 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 3562 if (connected) { 3563 DRM_DEBUG_KMS("DFP1 connected\n"); 3564 bios_4_scratch |= RADEON_DFP1_ATTACHED; 3565 bios_5_scratch |= RADEON_DFP1_ON; 3566 bios_5_scratch |= RADEON_ACC_REQ_DFP1; 3567 } else { 3568 DRM_DEBUG_KMS("DFP1 disconnected\n"); 3569 bios_4_scratch &= ~RADEON_DFP1_ATTACHED; 3570 bios_5_scratch &= ~RADEON_DFP1_ON; 3571 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1; 3572 } 3573 } 3574 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 3575 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 3576 if (connected) { 3577 DRM_DEBUG_KMS("DFP2 connected\n"); 3578 bios_4_scratch |= RADEON_DFP2_ATTACHED; 3579 bios_5_scratch |= RADEON_DFP2_ON; 3580 bios_5_scratch |= RADEON_ACC_REQ_DFP2; 3581 } else { 3582 DRM_DEBUG_KMS("DFP2 disconnected\n"); 3583 bios_4_scratch &= ~RADEON_DFP2_ATTACHED; 3584 bios_5_scratch &= ~RADEON_DFP2_ON; 3585 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2; 3586 } 3587 } 3588 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch); 3589 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 3590 } 3591 3592 void 3593 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) 3594 { 3595 struct drm_device *dev = encoder->dev; 3596 struct radeon_device *rdev = dev->dev_private; 3597 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3598 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 3599 3600 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 3601 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK; 3602 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT); 3603 } 3604 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 3605 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK; 3606 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT); 3607 } 3608 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 3609 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK; 3610 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT); 3611 } 3612 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 3613 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK; 3614 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT); 3615 } 3616 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 3617 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK; 3618 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT); 3619 } 3620 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 3621 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK; 3622 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT); 3623 } 3624 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 3625 } 3626 3627 void 3628 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) 3629 { 3630 struct drm_device *dev = encoder->dev; 3631 struct radeon_device *rdev = dev->dev_private; 3632 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3633 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3634 3635 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 3636 if (on) 3637 bios_6_scratch |= RADEON_TV_DPMS_ON; 3638 else 3639 bios_6_scratch &= ~RADEON_TV_DPMS_ON; 3640 } 3641 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3642 if (on) 3643 bios_6_scratch |= RADEON_CRT_DPMS_ON; 3644 else 3645 bios_6_scratch &= ~RADEON_CRT_DPMS_ON; 3646 } 3647 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3648 if (on) 3649 bios_6_scratch |= RADEON_LCD_DPMS_ON; 3650 else 3651 bios_6_scratch &= ~RADEON_LCD_DPMS_ON; 3652 } 3653 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 3654 if (on) 3655 bios_6_scratch |= RADEON_DFP_DPMS_ON; 3656 else 3657 bios_6_scratch &= ~RADEON_DFP_DPMS_ON; 3658 } 3659 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3660 } 3661