1 /* 2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario 3 * Copyright 2007-8 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * 27 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_combios.c 254885 2013-08-25 19:37:15Z dumbbell $ 28 */ 29 30 #include <drm/drmP.h> 31 #include <uapi_drm/radeon_drm.h> 32 #include "radeon.h" 33 #include "atom.h" 34 35 #ifdef CONFIG_PPC_PMAC 36 /* not sure which of these are needed */ 37 #include <asm/machdep.h> 38 #include <asm/pmac_feature.h> 39 #include <asm/prom.h> 40 #include <asm/pci-bridge.h> 41 #endif /* CONFIG_PPC_PMAC */ 42 43 /* old legacy ATI BIOS routines */ 44 45 /* COMBIOS table offsets */ 46 enum radeon_combios_table_offset { 47 /* absolute offset tables */ 48 COMBIOS_ASIC_INIT_1_TABLE, 49 COMBIOS_BIOS_SUPPORT_TABLE, 50 COMBIOS_DAC_PROGRAMMING_TABLE, 51 COMBIOS_MAX_COLOR_DEPTH_TABLE, 52 COMBIOS_CRTC_INFO_TABLE, 53 COMBIOS_PLL_INFO_TABLE, 54 COMBIOS_TV_INFO_TABLE, 55 COMBIOS_DFP_INFO_TABLE, 56 COMBIOS_HW_CONFIG_INFO_TABLE, 57 COMBIOS_MULTIMEDIA_INFO_TABLE, 58 COMBIOS_TV_STD_PATCH_TABLE, 59 COMBIOS_LCD_INFO_TABLE, 60 COMBIOS_MOBILE_INFO_TABLE, 61 COMBIOS_PLL_INIT_TABLE, 62 COMBIOS_MEM_CONFIG_TABLE, 63 COMBIOS_SAVE_MASK_TABLE, 64 COMBIOS_HARDCODED_EDID_TABLE, 65 COMBIOS_ASIC_INIT_2_TABLE, 66 COMBIOS_CONNECTOR_INFO_TABLE, 67 COMBIOS_DYN_CLK_1_TABLE, 68 COMBIOS_RESERVED_MEM_TABLE, 69 COMBIOS_EXT_TMDS_INFO_TABLE, 70 COMBIOS_MEM_CLK_INFO_TABLE, 71 COMBIOS_EXT_DAC_INFO_TABLE, 72 COMBIOS_MISC_INFO_TABLE, 73 COMBIOS_CRT_INFO_TABLE, 74 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE, 75 COMBIOS_COMPONENT_VIDEO_INFO_TABLE, 76 COMBIOS_FAN_SPEED_INFO_TABLE, 77 COMBIOS_OVERDRIVE_INFO_TABLE, 78 COMBIOS_OEM_INFO_TABLE, 79 COMBIOS_DYN_CLK_2_TABLE, 80 COMBIOS_POWER_CONNECTOR_INFO_TABLE, 81 COMBIOS_I2C_INFO_TABLE, 82 /* relative offset tables */ 83 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */ 84 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */ 85 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */ 86 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */ 87 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */ 88 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */ 89 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */ 90 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */ 91 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */ 92 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */ 93 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */ 94 }; 95 96 enum radeon_combios_ddc { 97 DDC_NONE_DETECTED, 98 DDC_MONID, 99 DDC_DVI, 100 DDC_VGA, 101 DDC_CRT2, 102 DDC_LCD, 103 DDC_GPIO, 104 }; 105 106 enum radeon_combios_connector { 107 CONNECTOR_NONE_LEGACY, 108 CONNECTOR_PROPRIETARY_LEGACY, 109 CONNECTOR_CRT_LEGACY, 110 CONNECTOR_DVI_I_LEGACY, 111 CONNECTOR_DVI_D_LEGACY, 112 CONNECTOR_CTV_LEGACY, 113 CONNECTOR_STV_LEGACY, 114 CONNECTOR_UNSUPPORTED_LEGACY 115 }; 116 117 const int legacy_connector_convert[] = { 118 DRM_MODE_CONNECTOR_Unknown, 119 DRM_MODE_CONNECTOR_DVID, 120 DRM_MODE_CONNECTOR_VGA, 121 DRM_MODE_CONNECTOR_DVII, 122 DRM_MODE_CONNECTOR_DVID, 123 DRM_MODE_CONNECTOR_Composite, 124 DRM_MODE_CONNECTOR_SVIDEO, 125 DRM_MODE_CONNECTOR_Unknown, 126 }; 127 128 static uint16_t combios_get_table_offset(struct drm_device *dev, 129 enum radeon_combios_table_offset table) 130 { 131 struct radeon_device *rdev = dev->dev_private; 132 int rev, size; 133 uint16_t offset = 0, check_offset; 134 135 if (!rdev->bios) 136 return 0; 137 138 switch (table) { 139 /* absolute offset tables */ 140 case COMBIOS_ASIC_INIT_1_TABLE: 141 check_offset = 0xc; 142 break; 143 case COMBIOS_BIOS_SUPPORT_TABLE: 144 check_offset = 0x14; 145 break; 146 case COMBIOS_DAC_PROGRAMMING_TABLE: 147 check_offset = 0x2a; 148 break; 149 case COMBIOS_MAX_COLOR_DEPTH_TABLE: 150 check_offset = 0x2c; 151 break; 152 case COMBIOS_CRTC_INFO_TABLE: 153 check_offset = 0x2e; 154 break; 155 case COMBIOS_PLL_INFO_TABLE: 156 check_offset = 0x30; 157 break; 158 case COMBIOS_TV_INFO_TABLE: 159 check_offset = 0x32; 160 break; 161 case COMBIOS_DFP_INFO_TABLE: 162 check_offset = 0x34; 163 break; 164 case COMBIOS_HW_CONFIG_INFO_TABLE: 165 check_offset = 0x36; 166 break; 167 case COMBIOS_MULTIMEDIA_INFO_TABLE: 168 check_offset = 0x38; 169 break; 170 case COMBIOS_TV_STD_PATCH_TABLE: 171 check_offset = 0x3e; 172 break; 173 case COMBIOS_LCD_INFO_TABLE: 174 check_offset = 0x40; 175 break; 176 case COMBIOS_MOBILE_INFO_TABLE: 177 check_offset = 0x42; 178 break; 179 case COMBIOS_PLL_INIT_TABLE: 180 check_offset = 0x46; 181 break; 182 case COMBIOS_MEM_CONFIG_TABLE: 183 check_offset = 0x48; 184 break; 185 case COMBIOS_SAVE_MASK_TABLE: 186 check_offset = 0x4a; 187 break; 188 case COMBIOS_HARDCODED_EDID_TABLE: 189 check_offset = 0x4c; 190 break; 191 case COMBIOS_ASIC_INIT_2_TABLE: 192 check_offset = 0x4e; 193 break; 194 case COMBIOS_CONNECTOR_INFO_TABLE: 195 check_offset = 0x50; 196 break; 197 case COMBIOS_DYN_CLK_1_TABLE: 198 check_offset = 0x52; 199 break; 200 case COMBIOS_RESERVED_MEM_TABLE: 201 check_offset = 0x54; 202 break; 203 case COMBIOS_EXT_TMDS_INFO_TABLE: 204 check_offset = 0x58; 205 break; 206 case COMBIOS_MEM_CLK_INFO_TABLE: 207 check_offset = 0x5a; 208 break; 209 case COMBIOS_EXT_DAC_INFO_TABLE: 210 check_offset = 0x5c; 211 break; 212 case COMBIOS_MISC_INFO_TABLE: 213 check_offset = 0x5e; 214 break; 215 case COMBIOS_CRT_INFO_TABLE: 216 check_offset = 0x60; 217 break; 218 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE: 219 check_offset = 0x62; 220 break; 221 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE: 222 check_offset = 0x64; 223 break; 224 case COMBIOS_FAN_SPEED_INFO_TABLE: 225 check_offset = 0x66; 226 break; 227 case COMBIOS_OVERDRIVE_INFO_TABLE: 228 check_offset = 0x68; 229 break; 230 case COMBIOS_OEM_INFO_TABLE: 231 check_offset = 0x6a; 232 break; 233 case COMBIOS_DYN_CLK_2_TABLE: 234 check_offset = 0x6c; 235 break; 236 case COMBIOS_POWER_CONNECTOR_INFO_TABLE: 237 check_offset = 0x6e; 238 break; 239 case COMBIOS_I2C_INFO_TABLE: 240 check_offset = 0x70; 241 break; 242 /* relative offset tables */ 243 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */ 244 check_offset = 245 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 246 if (check_offset) { 247 rev = RBIOS8(check_offset); 248 if (rev > 0) { 249 check_offset = RBIOS16(check_offset + 0x3); 250 if (check_offset) 251 offset = check_offset; 252 } 253 } 254 break; 255 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */ 256 check_offset = 257 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 258 if (check_offset) { 259 rev = RBIOS8(check_offset); 260 if (rev > 0) { 261 check_offset = RBIOS16(check_offset + 0x5); 262 if (check_offset) 263 offset = check_offset; 264 } 265 } 266 break; 267 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */ 268 check_offset = 269 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 270 if (check_offset) { 271 rev = RBIOS8(check_offset); 272 if (rev > 0) { 273 check_offset = RBIOS16(check_offset + 0x7); 274 if (check_offset) 275 offset = check_offset; 276 } 277 } 278 break; 279 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */ 280 check_offset = 281 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 282 if (check_offset) { 283 rev = RBIOS8(check_offset); 284 if (rev == 2) { 285 check_offset = RBIOS16(check_offset + 0x9); 286 if (check_offset) 287 offset = check_offset; 288 } 289 } 290 break; 291 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */ 292 check_offset = 293 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 294 if (check_offset) { 295 while (RBIOS8(check_offset++)); 296 check_offset += 2; 297 if (check_offset) 298 offset = check_offset; 299 } 300 break; 301 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */ 302 check_offset = 303 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 304 if (check_offset) { 305 check_offset = RBIOS16(check_offset + 0x11); 306 if (check_offset) 307 offset = check_offset; 308 } 309 break; 310 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */ 311 check_offset = 312 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 313 if (check_offset) { 314 check_offset = RBIOS16(check_offset + 0x13); 315 if (check_offset) 316 offset = check_offset; 317 } 318 break; 319 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */ 320 check_offset = 321 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 322 if (check_offset) { 323 check_offset = RBIOS16(check_offset + 0x15); 324 if (check_offset) 325 offset = check_offset; 326 } 327 break; 328 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */ 329 check_offset = 330 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 331 if (check_offset) { 332 check_offset = RBIOS16(check_offset + 0x17); 333 if (check_offset) 334 offset = check_offset; 335 } 336 break; 337 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */ 338 check_offset = 339 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 340 if (check_offset) { 341 check_offset = RBIOS16(check_offset + 0x2); 342 if (check_offset) 343 offset = check_offset; 344 } 345 break; 346 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */ 347 check_offset = 348 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 349 if (check_offset) { 350 check_offset = RBIOS16(check_offset + 0x4); 351 if (check_offset) 352 offset = check_offset; 353 } 354 break; 355 default: 356 check_offset = 0; 357 break; 358 } 359 360 size = RBIOS8(rdev->bios_header_start + 0x6); 361 /* check absolute offset tables */ 362 if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size) 363 offset = RBIOS16(rdev->bios_header_start + check_offset); 364 365 return offset; 366 } 367 368 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev) 369 { 370 int edid_info, size; 371 struct edid *edid; 372 unsigned char *raw; 373 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE); 374 if (!edid_info) 375 return false; 376 377 raw = rdev->bios + edid_info; 378 size = EDID_LENGTH * (raw[0x7e] + 1); 379 edid = kmalloc(size, M_DRM, M_WAITOK); 380 if (edid == NULL) 381 return false; 382 383 memcpy((unsigned char *)edid, raw, size); 384 385 if (!drm_edid_is_valid(edid)) { 386 kfree(edid); 387 return false; 388 } 389 390 rdev->mode_info.bios_hardcoded_edid = edid; 391 rdev->mode_info.bios_hardcoded_edid_size = size; 392 return true; 393 } 394 395 /* this is used for atom LCDs as well */ 396 struct edid * 397 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev) 398 { 399 struct edid *edid; 400 401 if (rdev->mode_info.bios_hardcoded_edid) { 402 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, 403 M_DRM, M_WAITOK); 404 if (edid) { 405 memcpy((unsigned char *)edid, 406 (unsigned char *)rdev->mode_info.bios_hardcoded_edid, 407 rdev->mode_info.bios_hardcoded_edid_size); 408 return edid; 409 } 410 } 411 return NULL; 412 } 413 414 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev, 415 enum radeon_combios_ddc ddc, 416 u32 clk_mask, 417 u32 data_mask) 418 { 419 struct radeon_i2c_bus_rec i2c; 420 int ddc_line = 0; 421 422 /* ddc id = mask reg 423 * DDC_NONE_DETECTED = none 424 * DDC_DVI = RADEON_GPIO_DVI_DDC 425 * DDC_VGA = RADEON_GPIO_VGA_DDC 426 * DDC_LCD = RADEON_GPIOPAD_MASK 427 * DDC_GPIO = RADEON_MDGPIO_MASK 428 * r1xx 429 * DDC_MONID = RADEON_GPIO_MONID 430 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC 431 * r200 432 * DDC_MONID = RADEON_GPIO_MONID 433 * DDC_CRT2 = RADEON_GPIO_DVI_DDC 434 * r300/r350 435 * DDC_MONID = RADEON_GPIO_DVI_DDC 436 * DDC_CRT2 = RADEON_GPIO_DVI_DDC 437 * rv2xx/rv3xx 438 * DDC_MONID = RADEON_GPIO_MONID 439 * DDC_CRT2 = RADEON_GPIO_MONID 440 * rs3xx/rs4xx 441 * DDC_MONID = RADEON_GPIOPAD_MASK 442 * DDC_CRT2 = RADEON_GPIO_MONID 443 */ 444 switch (ddc) { 445 case DDC_NONE_DETECTED: 446 default: 447 ddc_line = 0; 448 break; 449 case DDC_DVI: 450 ddc_line = RADEON_GPIO_DVI_DDC; 451 break; 452 case DDC_VGA: 453 ddc_line = RADEON_GPIO_VGA_DDC; 454 break; 455 case DDC_LCD: 456 ddc_line = RADEON_GPIOPAD_MASK; 457 break; 458 case DDC_GPIO: 459 ddc_line = RADEON_MDGPIO_MASK; 460 break; 461 case DDC_MONID: 462 if (rdev->family == CHIP_RS300 || 463 rdev->family == CHIP_RS400 || 464 rdev->family == CHIP_RS480) 465 ddc_line = RADEON_GPIOPAD_MASK; 466 else if (rdev->family == CHIP_R300 || 467 rdev->family == CHIP_R350) { 468 ddc_line = RADEON_GPIO_DVI_DDC; 469 ddc = DDC_DVI; 470 } else 471 ddc_line = RADEON_GPIO_MONID; 472 break; 473 case DDC_CRT2: 474 if (rdev->family == CHIP_R200 || 475 rdev->family == CHIP_R300 || 476 rdev->family == CHIP_R350) { 477 ddc_line = RADEON_GPIO_DVI_DDC; 478 ddc = DDC_DVI; 479 } else if (rdev->family == CHIP_RS300 || 480 rdev->family == CHIP_RS400 || 481 rdev->family == CHIP_RS480) 482 ddc_line = RADEON_GPIO_MONID; 483 else if (rdev->family >= CHIP_RV350) { 484 ddc_line = RADEON_GPIO_MONID; 485 ddc = DDC_MONID; 486 } else 487 ddc_line = RADEON_GPIO_CRT2_DDC; 488 break; 489 } 490 491 if (ddc_line == RADEON_GPIOPAD_MASK) { 492 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; 493 i2c.mask_data_reg = RADEON_GPIOPAD_MASK; 494 i2c.a_clk_reg = RADEON_GPIOPAD_A; 495 i2c.a_data_reg = RADEON_GPIOPAD_A; 496 i2c.en_clk_reg = RADEON_GPIOPAD_EN; 497 i2c.en_data_reg = RADEON_GPIOPAD_EN; 498 i2c.y_clk_reg = RADEON_GPIOPAD_Y; 499 i2c.y_data_reg = RADEON_GPIOPAD_Y; 500 } else if (ddc_line == RADEON_MDGPIO_MASK) { 501 i2c.mask_clk_reg = RADEON_MDGPIO_MASK; 502 i2c.mask_data_reg = RADEON_MDGPIO_MASK; 503 i2c.a_clk_reg = RADEON_MDGPIO_A; 504 i2c.a_data_reg = RADEON_MDGPIO_A; 505 i2c.en_clk_reg = RADEON_MDGPIO_EN; 506 i2c.en_data_reg = RADEON_MDGPIO_EN; 507 i2c.y_clk_reg = RADEON_MDGPIO_Y; 508 i2c.y_data_reg = RADEON_MDGPIO_Y; 509 } else { 510 i2c.mask_clk_reg = ddc_line; 511 i2c.mask_data_reg = ddc_line; 512 i2c.a_clk_reg = ddc_line; 513 i2c.a_data_reg = ddc_line; 514 i2c.en_clk_reg = ddc_line; 515 i2c.en_data_reg = ddc_line; 516 i2c.y_clk_reg = ddc_line; 517 i2c.y_data_reg = ddc_line; 518 } 519 520 if (clk_mask && data_mask) { 521 /* system specific masks */ 522 i2c.mask_clk_mask = clk_mask; 523 i2c.mask_data_mask = data_mask; 524 i2c.a_clk_mask = clk_mask; 525 i2c.a_data_mask = data_mask; 526 i2c.en_clk_mask = clk_mask; 527 i2c.en_data_mask = data_mask; 528 i2c.y_clk_mask = clk_mask; 529 i2c.y_data_mask = data_mask; 530 } else if ((ddc_line == RADEON_GPIOPAD_MASK) || 531 (ddc_line == RADEON_MDGPIO_MASK)) { 532 /* default gpiopad masks */ 533 i2c.mask_clk_mask = (0x20 << 8); 534 i2c.mask_data_mask = 0x80; 535 i2c.a_clk_mask = (0x20 << 8); 536 i2c.a_data_mask = 0x80; 537 i2c.en_clk_mask = (0x20 << 8); 538 i2c.en_data_mask = 0x80; 539 i2c.y_clk_mask = (0x20 << 8); 540 i2c.y_data_mask = 0x80; 541 } else { 542 /* default masks for ddc pads */ 543 i2c.mask_clk_mask = RADEON_GPIO_MASK_1; 544 i2c.mask_data_mask = RADEON_GPIO_MASK_0; 545 i2c.a_clk_mask = RADEON_GPIO_A_1; 546 i2c.a_data_mask = RADEON_GPIO_A_0; 547 i2c.en_clk_mask = RADEON_GPIO_EN_1; 548 i2c.en_data_mask = RADEON_GPIO_EN_0; 549 i2c.y_clk_mask = RADEON_GPIO_Y_1; 550 i2c.y_data_mask = RADEON_GPIO_Y_0; 551 } 552 553 switch (rdev->family) { 554 case CHIP_R100: 555 case CHIP_RV100: 556 case CHIP_RS100: 557 case CHIP_RV200: 558 case CHIP_RS200: 559 case CHIP_RS300: 560 switch (ddc_line) { 561 case RADEON_GPIO_DVI_DDC: 562 i2c.hw_capable = true; 563 break; 564 default: 565 i2c.hw_capable = false; 566 break; 567 } 568 break; 569 case CHIP_R200: 570 switch (ddc_line) { 571 case RADEON_GPIO_DVI_DDC: 572 case RADEON_GPIO_MONID: 573 i2c.hw_capable = true; 574 break; 575 default: 576 i2c.hw_capable = false; 577 break; 578 } 579 break; 580 case CHIP_RV250: 581 case CHIP_RV280: 582 switch (ddc_line) { 583 case RADEON_GPIO_VGA_DDC: 584 case RADEON_GPIO_DVI_DDC: 585 case RADEON_GPIO_CRT2_DDC: 586 i2c.hw_capable = true; 587 break; 588 default: 589 i2c.hw_capable = false; 590 break; 591 } 592 break; 593 case CHIP_R300: 594 case CHIP_R350: 595 switch (ddc_line) { 596 case RADEON_GPIO_VGA_DDC: 597 case RADEON_GPIO_DVI_DDC: 598 i2c.hw_capable = true; 599 break; 600 default: 601 i2c.hw_capable = false; 602 break; 603 } 604 break; 605 case CHIP_RV350: 606 case CHIP_RV380: 607 case CHIP_RS400: 608 case CHIP_RS480: 609 switch (ddc_line) { 610 case RADEON_GPIO_VGA_DDC: 611 case RADEON_GPIO_DVI_DDC: 612 i2c.hw_capable = true; 613 break; 614 case RADEON_GPIO_MONID: 615 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work 616 * reliably on some pre-r4xx hardware; not sure why. 617 */ 618 i2c.hw_capable = false; 619 break; 620 default: 621 i2c.hw_capable = false; 622 break; 623 } 624 break; 625 default: 626 i2c.hw_capable = false; 627 break; 628 } 629 i2c.mm_i2c = false; 630 631 i2c.i2c_id = ddc; 632 i2c.hpd = RADEON_HPD_NONE; 633 634 if (ddc_line) 635 i2c.valid = true; 636 else 637 i2c.valid = false; 638 639 return i2c; 640 } 641 642 static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev) 643 { 644 struct drm_device *dev = rdev->ddev; 645 struct radeon_i2c_bus_rec i2c; 646 u16 offset; 647 u8 id, blocks, clk, data; 648 int i; 649 650 i2c.valid = false; 651 652 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE); 653 if (offset) { 654 blocks = RBIOS8(offset + 2); 655 for (i = 0; i < blocks; i++) { 656 id = RBIOS8(offset + 3 + (i * 5) + 0); 657 if (id == 136) { 658 clk = RBIOS8(offset + 3 + (i * 5) + 3); 659 data = RBIOS8(offset + 3 + (i * 5) + 4); 660 /* gpiopad */ 661 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 662 (1 << clk), (1 << data)); 663 break; 664 } 665 } 666 } 667 return i2c; 668 } 669 670 void radeon_combios_i2c_init(struct radeon_device *rdev) 671 { 672 struct drm_device *dev = rdev->ddev; 673 struct radeon_i2c_bus_rec i2c; 674 675 /* actual hw pads 676 * r1xx/rs2xx/rs3xx 677 * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm 678 * r200 679 * 0x60, 0x64, 0x68, mm 680 * r300/r350 681 * 0x60, 0x64, mm 682 * rv2xx/rv3xx/rs4xx 683 * 0x60, 0x64, 0x68, gpiopads, mm 684 */ 685 686 /* 0x60 */ 687 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 688 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC"); 689 /* 0x64 */ 690 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 691 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC"); 692 693 /* mm i2c */ 694 i2c.valid = true; 695 i2c.hw_capable = true; 696 i2c.mm_i2c = true; 697 i2c.i2c_id = 0xa0; 698 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C"); 699 700 if (rdev->family == CHIP_R300 || 701 rdev->family == CHIP_R350) { 702 /* only 2 sw i2c pads */ 703 } else if (rdev->family == CHIP_RS300 || 704 rdev->family == CHIP_RS400 || 705 rdev->family == CHIP_RS480) { 706 /* 0x68 */ 707 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 708 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 709 710 /* gpiopad */ 711 i2c = radeon_combios_get_i2c_info_from_table(rdev); 712 if (i2c.valid) 713 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK"); 714 } else if ((rdev->family == CHIP_R200) || 715 (rdev->family >= CHIP_R300)) { 716 /* 0x68 */ 717 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 718 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 719 } else { 720 /* 0x68 */ 721 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 722 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 723 /* 0x6c */ 724 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 725 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC"); 726 } 727 } 728 729 bool radeon_combios_get_clock_info(struct drm_device *dev) 730 { 731 struct radeon_device *rdev = dev->dev_private; 732 uint16_t pll_info; 733 struct radeon_pll *p1pll = &rdev->clock.p1pll; 734 struct radeon_pll *p2pll = &rdev->clock.p2pll; 735 struct radeon_pll *spll = &rdev->clock.spll; 736 struct radeon_pll *mpll = &rdev->clock.mpll; 737 int8_t rev; 738 uint16_t sclk, mclk; 739 740 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE); 741 if (pll_info) { 742 rev = RBIOS8(pll_info); 743 744 /* pixel clocks */ 745 p1pll->reference_freq = RBIOS16(pll_info + 0xe); 746 p1pll->reference_div = RBIOS16(pll_info + 0x10); 747 p1pll->pll_out_min = RBIOS32(pll_info + 0x12); 748 p1pll->pll_out_max = RBIOS32(pll_info + 0x16); 749 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 750 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 751 752 if (rev > 9) { 753 p1pll->pll_in_min = RBIOS32(pll_info + 0x36); 754 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a); 755 } else { 756 p1pll->pll_in_min = 40; 757 p1pll->pll_in_max = 500; 758 } 759 *p2pll = *p1pll; 760 761 /* system clock */ 762 spll->reference_freq = RBIOS16(pll_info + 0x1a); 763 spll->reference_div = RBIOS16(pll_info + 0x1c); 764 spll->pll_out_min = RBIOS32(pll_info + 0x1e); 765 spll->pll_out_max = RBIOS32(pll_info + 0x22); 766 767 if (rev > 10) { 768 spll->pll_in_min = RBIOS32(pll_info + 0x48); 769 spll->pll_in_max = RBIOS32(pll_info + 0x4c); 770 } else { 771 /* ??? */ 772 spll->pll_in_min = 40; 773 spll->pll_in_max = 500; 774 } 775 776 /* memory clock */ 777 mpll->reference_freq = RBIOS16(pll_info + 0x26); 778 mpll->reference_div = RBIOS16(pll_info + 0x28); 779 mpll->pll_out_min = RBIOS32(pll_info + 0x2a); 780 mpll->pll_out_max = RBIOS32(pll_info + 0x2e); 781 782 if (rev > 10) { 783 mpll->pll_in_min = RBIOS32(pll_info + 0x5a); 784 mpll->pll_in_max = RBIOS32(pll_info + 0x5e); 785 } else { 786 /* ??? */ 787 mpll->pll_in_min = 40; 788 mpll->pll_in_max = 500; 789 } 790 791 /* default sclk/mclk */ 792 sclk = RBIOS16(pll_info + 0xa); 793 mclk = RBIOS16(pll_info + 0x8); 794 if (sclk == 0) 795 sclk = 200 * 100; 796 if (mclk == 0) 797 mclk = 200 * 100; 798 799 rdev->clock.default_sclk = sclk; 800 rdev->clock.default_mclk = mclk; 801 802 if (RBIOS32(pll_info + 0x16)) 803 rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16); 804 else 805 rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */ 806 807 return true; 808 } 809 return false; 810 } 811 812 bool radeon_combios_sideport_present(struct radeon_device *rdev) 813 { 814 struct drm_device *dev = rdev->ddev; 815 u16 igp_info; 816 817 /* sideport is AMD only */ 818 if (rdev->family == CHIP_RS400) 819 return false; 820 821 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE); 822 823 if (igp_info) { 824 if (RBIOS16(igp_info + 0x4)) 825 return true; 826 } 827 return false; 828 } 829 830 static const uint32_t default_primarydac_adj[CHIP_LAST] = { 831 0x00000808, /* r100 */ 832 0x00000808, /* rv100 */ 833 0x00000808, /* rs100 */ 834 0x00000808, /* rv200 */ 835 0x00000808, /* rs200 */ 836 0x00000808, /* r200 */ 837 0x00000808, /* rv250 */ 838 0x00000000, /* rs300 */ 839 0x00000808, /* rv280 */ 840 0x00000808, /* r300 */ 841 0x00000808, /* r350 */ 842 0x00000808, /* rv350 */ 843 0x00000808, /* rv380 */ 844 0x00000808, /* r420 */ 845 0x00000808, /* r423 */ 846 0x00000808, /* rv410 */ 847 0x00000000, /* rs400 */ 848 0x00000000, /* rs480 */ 849 }; 850 851 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev, 852 struct radeon_encoder_primary_dac *p_dac) 853 { 854 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family]; 855 return; 856 } 857 858 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct 859 radeon_encoder 860 *encoder) 861 { 862 struct drm_device *dev = encoder->base.dev; 863 struct radeon_device *rdev = dev->dev_private; 864 uint16_t dac_info; 865 uint8_t rev, bg, dac; 866 struct radeon_encoder_primary_dac *p_dac = NULL; 867 int found = 0; 868 869 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), 870 GFP_KERNEL); 871 872 if (!p_dac) 873 return NULL; 874 875 /* check CRT table */ 876 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 877 if (dac_info) { 878 rev = RBIOS8(dac_info) & 0x3; 879 if (rev < 2) { 880 bg = RBIOS8(dac_info + 0x2) & 0xf; 881 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf; 882 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 883 } else { 884 bg = RBIOS8(dac_info + 0x2) & 0xf; 885 dac = RBIOS8(dac_info + 0x3) & 0xf; 886 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 887 } 888 /* if the values are zeros, use the table */ 889 if ((dac == 0) || (bg == 0)) 890 found = 0; 891 else 892 found = 1; 893 } 894 895 /* quirks */ 896 /* Radeon 7000 (RV100) */ 897 if (((dev->pdev->device == 0x5159) && 898 (dev->pdev->subsystem_vendor == 0x174B) && 899 (dev->pdev->subsystem_device == 0x7c28)) || 900 /* Radeon 9100 (R200) */ 901 ((dev->pdev->device == 0x514D) && 902 (dev->pdev->subsystem_vendor == 0x174B) && 903 (dev->pdev->subsystem_device == 0x7149))) { 904 /* vbios value is bad, use the default */ 905 found = 0; 906 } 907 908 if (!found) /* fallback to defaults */ 909 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac); 910 911 return p_dac; 912 } 913 914 enum radeon_tv_std 915 radeon_combios_get_tv_info(struct radeon_device *rdev) 916 { 917 struct drm_device *dev = rdev->ddev; 918 uint16_t tv_info; 919 enum radeon_tv_std tv_std = TV_STD_NTSC; 920 921 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 922 if (tv_info) { 923 if (RBIOS8(tv_info + 6) == 'T') { 924 switch (RBIOS8(tv_info + 7) & 0xf) { 925 case 1: 926 tv_std = TV_STD_NTSC; 927 DRM_DEBUG_KMS("Default TV standard: NTSC\n"); 928 break; 929 case 2: 930 tv_std = TV_STD_PAL; 931 DRM_DEBUG_KMS("Default TV standard: PAL\n"); 932 break; 933 case 3: 934 tv_std = TV_STD_PAL_M; 935 DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); 936 break; 937 case 4: 938 tv_std = TV_STD_PAL_60; 939 DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); 940 break; 941 case 5: 942 tv_std = TV_STD_NTSC_J; 943 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); 944 break; 945 case 6: 946 tv_std = TV_STD_SCART_PAL; 947 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n"); 948 break; 949 default: 950 tv_std = TV_STD_NTSC; 951 DRM_DEBUG_KMS 952 ("Unknown TV standard; defaulting to NTSC\n"); 953 break; 954 } 955 956 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) { 957 case 0: 958 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n"); 959 break; 960 case 1: 961 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n"); 962 break; 963 case 2: 964 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n"); 965 break; 966 case 3: 967 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n"); 968 break; 969 default: 970 break; 971 } 972 } 973 } 974 return tv_std; 975 } 976 977 static const uint32_t default_tvdac_adj[CHIP_LAST] = { 978 0x00000000, /* r100 */ 979 0x00280000, /* rv100 */ 980 0x00000000, /* rs100 */ 981 0x00880000, /* rv200 */ 982 0x00000000, /* rs200 */ 983 0x00000000, /* r200 */ 984 0x00770000, /* rv250 */ 985 0x00290000, /* rs300 */ 986 0x00560000, /* rv280 */ 987 0x00780000, /* r300 */ 988 0x00770000, /* r350 */ 989 0x00780000, /* rv350 */ 990 0x00780000, /* rv380 */ 991 0x01080000, /* r420 */ 992 0x01080000, /* r423 */ 993 0x01080000, /* rv410 */ 994 0x00780000, /* rs400 */ 995 0x00780000, /* rs480 */ 996 }; 997 998 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev, 999 struct radeon_encoder_tv_dac *tv_dac) 1000 { 1001 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family]; 1002 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250)) 1003 tv_dac->ps2_tvdac_adj = 0x00880000; 1004 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 1005 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 1006 return; 1007 } 1008 1009 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct 1010 radeon_encoder 1011 *encoder) 1012 { 1013 struct drm_device *dev = encoder->base.dev; 1014 struct radeon_device *rdev = dev->dev_private; 1015 uint16_t dac_info; 1016 uint8_t rev, bg, dac; 1017 struct radeon_encoder_tv_dac *tv_dac = NULL; 1018 int found = 0; 1019 1020 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); 1021 if (!tv_dac) 1022 return NULL; 1023 1024 /* first check TV table */ 1025 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 1026 if (dac_info) { 1027 rev = RBIOS8(dac_info + 0x3); 1028 if (rev > 4) { 1029 bg = RBIOS8(dac_info + 0xc) & 0xf; 1030 dac = RBIOS8(dac_info + 0xd) & 0xf; 1031 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1032 1033 bg = RBIOS8(dac_info + 0xe) & 0xf; 1034 dac = RBIOS8(dac_info + 0xf) & 0xf; 1035 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1036 1037 bg = RBIOS8(dac_info + 0x10) & 0xf; 1038 dac = RBIOS8(dac_info + 0x11) & 0xf; 1039 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1040 /* if the values are all zeros, use the table */ 1041 if (tv_dac->ps2_tvdac_adj) 1042 found = 1; 1043 } else if (rev > 1) { 1044 bg = RBIOS8(dac_info + 0xc) & 0xf; 1045 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf; 1046 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1047 1048 bg = RBIOS8(dac_info + 0xd) & 0xf; 1049 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf; 1050 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1051 1052 bg = RBIOS8(dac_info + 0xe) & 0xf; 1053 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf; 1054 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1055 /* if the values are all zeros, use the table */ 1056 if (tv_dac->ps2_tvdac_adj) 1057 found = 1; 1058 } 1059 tv_dac->tv_std = radeon_combios_get_tv_info(rdev); 1060 } 1061 if (!found) { 1062 /* then check CRT table */ 1063 dac_info = 1064 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 1065 if (dac_info) { 1066 rev = RBIOS8(dac_info) & 0x3; 1067 if (rev < 2) { 1068 bg = RBIOS8(dac_info + 0x3) & 0xf; 1069 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf; 1070 tv_dac->ps2_tvdac_adj = 1071 (bg << 16) | (dac << 20); 1072 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 1073 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 1074 /* if the values are all zeros, use the table */ 1075 if (tv_dac->ps2_tvdac_adj) 1076 found = 1; 1077 } else { 1078 bg = RBIOS8(dac_info + 0x4) & 0xf; 1079 dac = RBIOS8(dac_info + 0x5) & 0xf; 1080 tv_dac->ps2_tvdac_adj = 1081 (bg << 16) | (dac << 20); 1082 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 1083 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 1084 /* if the values are all zeros, use the table */ 1085 if (tv_dac->ps2_tvdac_adj) 1086 found = 1; 1087 } 1088 } else { 1089 DRM_INFO("No TV DAC info found in BIOS\n"); 1090 } 1091 } 1092 1093 if (!found) /* fallback to defaults */ 1094 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac); 1095 1096 return tv_dac; 1097 } 1098 1099 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct 1100 radeon_device 1101 *rdev) 1102 { 1103 struct radeon_encoder_lvds *lvds = NULL; 1104 uint32_t fp_vert_stretch, fp_horz_stretch; 1105 uint32_t ppll_div_sel, ppll_val; 1106 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); 1107 1108 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); 1109 1110 if (!lvds) 1111 return NULL; 1112 1113 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH); 1114 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH); 1115 1116 /* These should be fail-safe defaults, fingers crossed */ 1117 lvds->panel_pwr_delay = 200; 1118 lvds->panel_vcc_delay = 2000; 1119 1120 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 1121 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf; 1122 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf; 1123 1124 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) 1125 lvds->native_mode.vdisplay = 1126 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >> 1127 RADEON_VERT_PANEL_SHIFT) + 1; 1128 else 1129 lvds->native_mode.vdisplay = 1130 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1; 1131 1132 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE) 1133 lvds->native_mode.hdisplay = 1134 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >> 1135 RADEON_HORZ_PANEL_SHIFT) + 1) * 8; 1136 else 1137 lvds->native_mode.hdisplay = 1138 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8; 1139 1140 if ((lvds->native_mode.hdisplay < 640) || 1141 (lvds->native_mode.vdisplay < 480)) { 1142 lvds->native_mode.hdisplay = 640; 1143 lvds->native_mode.vdisplay = 480; 1144 } 1145 1146 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; 1147 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel); 1148 if ((ppll_val & 0x000707ff) == 0x1bb) 1149 lvds->use_bios_dividers = false; 1150 else { 1151 lvds->panel_ref_divider = 1152 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; 1153 lvds->panel_post_divider = (ppll_val >> 16) & 0x7; 1154 lvds->panel_fb_divider = ppll_val & 0x7ff; 1155 1156 if ((lvds->panel_ref_divider != 0) && 1157 (lvds->panel_fb_divider > 3)) 1158 lvds->use_bios_dividers = true; 1159 } 1160 lvds->panel_vcc_delay = 200; 1161 1162 DRM_INFO("Panel info derived from registers\n"); 1163 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 1164 lvds->native_mode.vdisplay); 1165 1166 return lvds; 1167 } 1168 1169 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder 1170 *encoder) 1171 { 1172 struct drm_device *dev = encoder->base.dev; 1173 struct radeon_device *rdev = dev->dev_private; 1174 uint16_t lcd_info; 1175 uint32_t panel_setup; 1176 char stmp[30]; 1177 int tmp, i; 1178 struct radeon_encoder_lvds *lvds = NULL; 1179 1180 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 1181 1182 if (lcd_info) { 1183 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); 1184 1185 if (!lvds) 1186 return NULL; 1187 1188 for (i = 0; i < 24; i++) 1189 stmp[i] = RBIOS8(lcd_info + i + 1); 1190 stmp[24] = 0; 1191 1192 DRM_INFO("Panel ID String: %s\n", stmp); 1193 1194 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19); 1195 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b); 1196 1197 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 1198 lvds->native_mode.vdisplay); 1199 1200 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c); 1201 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000); 1202 1203 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24); 1204 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf; 1205 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf; 1206 1207 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e); 1208 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30); 1209 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31); 1210 if ((lvds->panel_ref_divider != 0) && 1211 (lvds->panel_fb_divider > 3)) 1212 lvds->use_bios_dividers = true; 1213 1214 panel_setup = RBIOS32(lcd_info + 0x39); 1215 lvds->lvds_gen_cntl = 0xff00; 1216 if (panel_setup & 0x1) 1217 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT; 1218 1219 if ((panel_setup >> 4) & 0x1) 1220 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE; 1221 1222 switch ((panel_setup >> 8) & 0x7) { 1223 case 0: 1224 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM; 1225 break; 1226 case 1: 1227 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY; 1228 break; 1229 case 2: 1230 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY; 1231 break; 1232 default: 1233 break; 1234 } 1235 1236 if ((panel_setup >> 16) & 0x1) 1237 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW; 1238 1239 if ((panel_setup >> 17) & 0x1) 1240 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW; 1241 1242 if ((panel_setup >> 18) & 0x1) 1243 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW; 1244 1245 if ((panel_setup >> 23) & 0x1) 1246 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL; 1247 1248 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000); 1249 1250 for (i = 0; i < 32; i++) { 1251 tmp = RBIOS16(lcd_info + 64 + i * 2); 1252 if (tmp == 0) 1253 break; 1254 1255 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) && 1256 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) { 1257 lvds->native_mode.htotal = lvds->native_mode.hdisplay + 1258 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8; 1259 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + 1260 (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8; 1261 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + 1262 (RBIOS8(tmp + 23) * 8); 1263 1264 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + 1265 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26)); 1266 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + 1267 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26)); 1268 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + 1269 ((RBIOS16(tmp + 28) & 0xf800) >> 11); 1270 1271 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10; 1272 lvds->native_mode.flags = 0; 1273 /* set crtc values */ 1274 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); 1275 1276 } 1277 } 1278 } else { 1279 DRM_INFO("No panel info found in BIOS\n"); 1280 lvds = radeon_legacy_get_lvds_info_from_regs(rdev); 1281 } 1282 1283 if (lvds) 1284 encoder->native_mode = lvds->native_mode; 1285 return lvds; 1286 } 1287 1288 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = { 1289 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */ 1290 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */ 1291 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */ 1292 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */ 1293 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */ 1294 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */ 1295 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */ 1296 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */ 1297 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */ 1298 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */ 1299 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */ 1300 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */ 1301 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */ 1302 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */ 1303 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */ 1304 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */ 1305 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */ 1306 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */ 1307 }; 1308 1309 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 1310 struct radeon_encoder_int_tmds *tmds) 1311 { 1312 struct drm_device *dev = encoder->base.dev; 1313 struct radeon_device *rdev = dev->dev_private; 1314 int i; 1315 1316 for (i = 0; i < 4; i++) { 1317 tmds->tmds_pll[i].value = 1318 default_tmds_pll[rdev->family][i].value; 1319 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq; 1320 } 1321 1322 return true; 1323 } 1324 1325 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 1326 struct radeon_encoder_int_tmds *tmds) 1327 { 1328 struct drm_device *dev = encoder->base.dev; 1329 struct radeon_device *rdev = dev->dev_private; 1330 uint16_t tmds_info; 1331 int i, n; 1332 uint8_t ver; 1333 1334 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 1335 1336 if (tmds_info) { 1337 ver = RBIOS8(tmds_info); 1338 DRM_DEBUG_KMS("DFP table revision: %d\n", ver); 1339 if (ver == 3) { 1340 n = RBIOS8(tmds_info + 5) + 1; 1341 if (n > 4) 1342 n = 4; 1343 for (i = 0; i < n; i++) { 1344 tmds->tmds_pll[i].value = 1345 RBIOS32(tmds_info + i * 10 + 0x08); 1346 tmds->tmds_pll[i].freq = 1347 RBIOS16(tmds_info + i * 10 + 0x10); 1348 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", 1349 tmds->tmds_pll[i].freq, 1350 tmds->tmds_pll[i].value); 1351 } 1352 } else if (ver == 4) { 1353 int stride = 0; 1354 n = RBIOS8(tmds_info + 5) + 1; 1355 if (n > 4) 1356 n = 4; 1357 for (i = 0; i < n; i++) { 1358 tmds->tmds_pll[i].value = 1359 RBIOS32(tmds_info + stride + 0x08); 1360 tmds->tmds_pll[i].freq = 1361 RBIOS16(tmds_info + stride + 0x10); 1362 if (i == 0) 1363 stride += 10; 1364 else 1365 stride += 6; 1366 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", 1367 tmds->tmds_pll[i].freq, 1368 tmds->tmds_pll[i].value); 1369 } 1370 } 1371 } else { 1372 DRM_INFO("No TMDS info found in BIOS\n"); 1373 return false; 1374 } 1375 return true; 1376 } 1377 1378 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 1379 struct radeon_encoder_ext_tmds *tmds) 1380 { 1381 struct drm_device *dev = encoder->base.dev; 1382 struct radeon_device *rdev = dev->dev_private; 1383 struct radeon_i2c_bus_rec i2c_bus; 1384 1385 /* default for macs */ 1386 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1387 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1388 1389 /* XXX some macs have duallink chips */ 1390 switch (rdev->mode_info.connector_table) { 1391 case CT_POWERBOOK_EXTERNAL: 1392 case CT_MINI_EXTERNAL: 1393 default: 1394 tmds->dvo_chip = DVO_SIL164; 1395 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1396 break; 1397 } 1398 1399 return true; 1400 } 1401 1402 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 1403 struct radeon_encoder_ext_tmds *tmds) 1404 { 1405 struct drm_device *dev = encoder->base.dev; 1406 struct radeon_device *rdev = dev->dev_private; 1407 uint16_t offset; 1408 uint8_t ver; 1409 enum radeon_combios_ddc gpio; 1410 struct radeon_i2c_bus_rec i2c_bus; 1411 1412 tmds->i2c_bus = NULL; 1413 if (rdev->flags & RADEON_IS_IGP) { 1414 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1415 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1416 tmds->dvo_chip = DVO_SIL164; 1417 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1418 } else { 1419 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 1420 if (offset) { 1421 ver = RBIOS8(offset); 1422 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver); 1423 tmds->slave_addr = RBIOS8(offset + 4 + 2); 1424 tmds->slave_addr >>= 1; /* 7 bit addressing */ 1425 gpio = RBIOS8(offset + 4 + 3); 1426 if (gpio == DDC_LCD) { 1427 /* MM i2c */ 1428 i2c_bus.valid = true; 1429 i2c_bus.hw_capable = true; 1430 i2c_bus.mm_i2c = true; 1431 i2c_bus.i2c_id = 0xa0; 1432 } else 1433 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); 1434 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1435 } 1436 } 1437 1438 if (!tmds->i2c_bus) { 1439 DRM_INFO("No valid Ext TMDS info found in BIOS\n"); 1440 return false; 1441 } 1442 1443 return true; 1444 } 1445 1446 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) 1447 { 1448 struct radeon_device *rdev = dev->dev_private; 1449 struct radeon_i2c_bus_rec ddc_i2c; 1450 struct radeon_hpd hpd; 1451 1452 rdev->mode_info.connector_table = radeon_connector_table; 1453 if (rdev->mode_info.connector_table == CT_NONE) { 1454 #ifdef CONFIG_PPC_PMAC 1455 if (of_machine_is_compatible("PowerBook3,3")) { 1456 /* powerbook with VGA */ 1457 rdev->mode_info.connector_table = CT_POWERBOOK_VGA; 1458 } else if (of_machine_is_compatible("PowerBook3,4") || 1459 of_machine_is_compatible("PowerBook3,5")) { 1460 /* powerbook with internal tmds */ 1461 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL; 1462 } else if (of_machine_is_compatible("PowerBook5,1") || 1463 of_machine_is_compatible("PowerBook5,2") || 1464 of_machine_is_compatible("PowerBook5,3") || 1465 of_machine_is_compatible("PowerBook5,4") || 1466 of_machine_is_compatible("PowerBook5,5")) { 1467 /* powerbook with external single link tmds (sil164) */ 1468 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1469 } else if (of_machine_is_compatible("PowerBook5,6")) { 1470 /* powerbook with external dual or single link tmds */ 1471 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1472 } else if (of_machine_is_compatible("PowerBook5,7") || 1473 of_machine_is_compatible("PowerBook5,8") || 1474 of_machine_is_compatible("PowerBook5,9")) { 1475 /* PowerBook6,2 ? */ 1476 /* powerbook with external dual link tmds (sil1178?) */ 1477 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1478 } else if (of_machine_is_compatible("PowerBook4,1") || 1479 of_machine_is_compatible("PowerBook4,2") || 1480 of_machine_is_compatible("PowerBook4,3") || 1481 of_machine_is_compatible("PowerBook6,3") || 1482 of_machine_is_compatible("PowerBook6,5") || 1483 of_machine_is_compatible("PowerBook6,7")) { 1484 /* ibook */ 1485 rdev->mode_info.connector_table = CT_IBOOK; 1486 } else if (of_machine_is_compatible("PowerMac3,5")) { 1487 /* PowerMac G4 Silver radeon 7500 */ 1488 rdev->mode_info.connector_table = CT_MAC_G4_SILVER; 1489 } else if (of_machine_is_compatible("PowerMac4,4")) { 1490 /* emac */ 1491 rdev->mode_info.connector_table = CT_EMAC; 1492 } else if (of_machine_is_compatible("PowerMac10,1")) { 1493 /* mini with internal tmds */ 1494 rdev->mode_info.connector_table = CT_MINI_INTERNAL; 1495 } else if (of_machine_is_compatible("PowerMac10,2")) { 1496 /* mini with external tmds */ 1497 rdev->mode_info.connector_table = CT_MINI_EXTERNAL; 1498 } else if (of_machine_is_compatible("PowerMac12,1")) { 1499 /* PowerMac8,1 ? */ 1500 /* imac g5 isight */ 1501 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT; 1502 } else if ((rdev->pdev->device == 0x4a48) && 1503 (rdev->pdev->subsystem_vendor == 0x1002) && 1504 (rdev->pdev->subsystem_device == 0x4a48)) { 1505 /* Mac X800 */ 1506 rdev->mode_info.connector_table = CT_MAC_X800; 1507 } else if ((of_machine_is_compatible("PowerMac7,2") || 1508 of_machine_is_compatible("PowerMac7,3")) && 1509 (rdev->pdev->device == 0x4150) && 1510 (rdev->pdev->subsystem_vendor == 0x1002) && 1511 (rdev->pdev->subsystem_device == 0x4150)) { 1512 /* Mac G5 tower 9600 */ 1513 rdev->mode_info.connector_table = CT_MAC_G5_9600; 1514 } else if ((rdev->pdev->device == 0x4c66) && 1515 (rdev->pdev->subsystem_vendor == 0x1002) && 1516 (rdev->pdev->subsystem_device == 0x4c66)) { 1517 /* SAM440ep RV250 embedded board */ 1518 rdev->mode_info.connector_table = CT_SAM440EP; 1519 } else 1520 #endif /* CONFIG_PPC_PMAC */ 1521 #ifdef CONFIG_PPC64 1522 if (ASIC_IS_RN50(rdev)) 1523 rdev->mode_info.connector_table = CT_RN50_POWER; 1524 else 1525 #endif 1526 rdev->mode_info.connector_table = CT_GENERIC; 1527 } 1528 1529 switch (rdev->mode_info.connector_table) { 1530 case CT_GENERIC: 1531 DRM_INFO("Connector Table: %d (generic)\n", 1532 rdev->mode_info.connector_table); 1533 /* these are the most common settings */ 1534 if (rdev->flags & RADEON_SINGLE_CRTC) { 1535 /* VGA - primary dac */ 1536 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1537 hpd.hpd = RADEON_HPD_NONE; 1538 radeon_add_legacy_encoder(dev, 1539 radeon_get_encoder_enum(dev, 1540 ATOM_DEVICE_CRT1_SUPPORT, 1541 1), 1542 ATOM_DEVICE_CRT1_SUPPORT); 1543 radeon_add_legacy_connector(dev, 0, 1544 ATOM_DEVICE_CRT1_SUPPORT, 1545 DRM_MODE_CONNECTOR_VGA, 1546 &ddc_i2c, 1547 CONNECTOR_OBJECT_ID_VGA, 1548 &hpd); 1549 } else if (rdev->flags & RADEON_IS_MOBILITY) { 1550 /* LVDS */ 1551 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); 1552 hpd.hpd = RADEON_HPD_NONE; 1553 radeon_add_legacy_encoder(dev, 1554 radeon_get_encoder_enum(dev, 1555 ATOM_DEVICE_LCD1_SUPPORT, 1556 0), 1557 ATOM_DEVICE_LCD1_SUPPORT); 1558 radeon_add_legacy_connector(dev, 0, 1559 ATOM_DEVICE_LCD1_SUPPORT, 1560 DRM_MODE_CONNECTOR_LVDS, 1561 &ddc_i2c, 1562 CONNECTOR_OBJECT_ID_LVDS, 1563 &hpd); 1564 1565 /* VGA - primary dac */ 1566 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1567 hpd.hpd = RADEON_HPD_NONE; 1568 radeon_add_legacy_encoder(dev, 1569 radeon_get_encoder_enum(dev, 1570 ATOM_DEVICE_CRT1_SUPPORT, 1571 1), 1572 ATOM_DEVICE_CRT1_SUPPORT); 1573 radeon_add_legacy_connector(dev, 1, 1574 ATOM_DEVICE_CRT1_SUPPORT, 1575 DRM_MODE_CONNECTOR_VGA, 1576 &ddc_i2c, 1577 CONNECTOR_OBJECT_ID_VGA, 1578 &hpd); 1579 } else { 1580 /* DVI-I - tv dac, int tmds */ 1581 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1582 hpd.hpd = RADEON_HPD_1; 1583 radeon_add_legacy_encoder(dev, 1584 radeon_get_encoder_enum(dev, 1585 ATOM_DEVICE_DFP1_SUPPORT, 1586 0), 1587 ATOM_DEVICE_DFP1_SUPPORT); 1588 radeon_add_legacy_encoder(dev, 1589 radeon_get_encoder_enum(dev, 1590 ATOM_DEVICE_CRT2_SUPPORT, 1591 2), 1592 ATOM_DEVICE_CRT2_SUPPORT); 1593 radeon_add_legacy_connector(dev, 0, 1594 ATOM_DEVICE_DFP1_SUPPORT | 1595 ATOM_DEVICE_CRT2_SUPPORT, 1596 DRM_MODE_CONNECTOR_DVII, 1597 &ddc_i2c, 1598 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1599 &hpd); 1600 1601 /* VGA - primary dac */ 1602 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1603 hpd.hpd = RADEON_HPD_NONE; 1604 radeon_add_legacy_encoder(dev, 1605 radeon_get_encoder_enum(dev, 1606 ATOM_DEVICE_CRT1_SUPPORT, 1607 1), 1608 ATOM_DEVICE_CRT1_SUPPORT); 1609 radeon_add_legacy_connector(dev, 1, 1610 ATOM_DEVICE_CRT1_SUPPORT, 1611 DRM_MODE_CONNECTOR_VGA, 1612 &ddc_i2c, 1613 CONNECTOR_OBJECT_ID_VGA, 1614 &hpd); 1615 } 1616 1617 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 1618 /* TV - tv dac */ 1619 ddc_i2c.valid = false; 1620 hpd.hpd = RADEON_HPD_NONE; 1621 radeon_add_legacy_encoder(dev, 1622 radeon_get_encoder_enum(dev, 1623 ATOM_DEVICE_TV1_SUPPORT, 1624 2), 1625 ATOM_DEVICE_TV1_SUPPORT); 1626 radeon_add_legacy_connector(dev, 2, 1627 ATOM_DEVICE_TV1_SUPPORT, 1628 DRM_MODE_CONNECTOR_SVIDEO, 1629 &ddc_i2c, 1630 CONNECTOR_OBJECT_ID_SVIDEO, 1631 &hpd); 1632 } 1633 break; 1634 case CT_IBOOK: 1635 DRM_INFO("Connector Table: %d (ibook)\n", 1636 rdev->mode_info.connector_table); 1637 /* LVDS */ 1638 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1639 hpd.hpd = RADEON_HPD_NONE; 1640 radeon_add_legacy_encoder(dev, 1641 radeon_get_encoder_enum(dev, 1642 ATOM_DEVICE_LCD1_SUPPORT, 1643 0), 1644 ATOM_DEVICE_LCD1_SUPPORT); 1645 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1646 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1647 CONNECTOR_OBJECT_ID_LVDS, 1648 &hpd); 1649 /* VGA - TV DAC */ 1650 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1651 hpd.hpd = RADEON_HPD_NONE; 1652 radeon_add_legacy_encoder(dev, 1653 radeon_get_encoder_enum(dev, 1654 ATOM_DEVICE_CRT2_SUPPORT, 1655 2), 1656 ATOM_DEVICE_CRT2_SUPPORT); 1657 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1658 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1659 CONNECTOR_OBJECT_ID_VGA, 1660 &hpd); 1661 /* TV - TV DAC */ 1662 ddc_i2c.valid = false; 1663 hpd.hpd = RADEON_HPD_NONE; 1664 radeon_add_legacy_encoder(dev, 1665 radeon_get_encoder_enum(dev, 1666 ATOM_DEVICE_TV1_SUPPORT, 1667 2), 1668 ATOM_DEVICE_TV1_SUPPORT); 1669 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1670 DRM_MODE_CONNECTOR_SVIDEO, 1671 &ddc_i2c, 1672 CONNECTOR_OBJECT_ID_SVIDEO, 1673 &hpd); 1674 break; 1675 case CT_POWERBOOK_EXTERNAL: 1676 DRM_INFO("Connector Table: %d (powerbook external tmds)\n", 1677 rdev->mode_info.connector_table); 1678 /* LVDS */ 1679 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1680 hpd.hpd = RADEON_HPD_NONE; 1681 radeon_add_legacy_encoder(dev, 1682 radeon_get_encoder_enum(dev, 1683 ATOM_DEVICE_LCD1_SUPPORT, 1684 0), 1685 ATOM_DEVICE_LCD1_SUPPORT); 1686 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1687 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1688 CONNECTOR_OBJECT_ID_LVDS, 1689 &hpd); 1690 /* DVI-I - primary dac, ext tmds */ 1691 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1692 hpd.hpd = RADEON_HPD_2; /* ??? */ 1693 radeon_add_legacy_encoder(dev, 1694 radeon_get_encoder_enum(dev, 1695 ATOM_DEVICE_DFP2_SUPPORT, 1696 0), 1697 ATOM_DEVICE_DFP2_SUPPORT); 1698 radeon_add_legacy_encoder(dev, 1699 radeon_get_encoder_enum(dev, 1700 ATOM_DEVICE_CRT1_SUPPORT, 1701 1), 1702 ATOM_DEVICE_CRT1_SUPPORT); 1703 /* XXX some are SL */ 1704 radeon_add_legacy_connector(dev, 1, 1705 ATOM_DEVICE_DFP2_SUPPORT | 1706 ATOM_DEVICE_CRT1_SUPPORT, 1707 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1708 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, 1709 &hpd); 1710 /* TV - TV DAC */ 1711 ddc_i2c.valid = false; 1712 hpd.hpd = RADEON_HPD_NONE; 1713 radeon_add_legacy_encoder(dev, 1714 radeon_get_encoder_enum(dev, 1715 ATOM_DEVICE_TV1_SUPPORT, 1716 2), 1717 ATOM_DEVICE_TV1_SUPPORT); 1718 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1719 DRM_MODE_CONNECTOR_SVIDEO, 1720 &ddc_i2c, 1721 CONNECTOR_OBJECT_ID_SVIDEO, 1722 &hpd); 1723 break; 1724 case CT_POWERBOOK_INTERNAL: 1725 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n", 1726 rdev->mode_info.connector_table); 1727 /* LVDS */ 1728 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1729 hpd.hpd = RADEON_HPD_NONE; 1730 radeon_add_legacy_encoder(dev, 1731 radeon_get_encoder_enum(dev, 1732 ATOM_DEVICE_LCD1_SUPPORT, 1733 0), 1734 ATOM_DEVICE_LCD1_SUPPORT); 1735 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1736 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1737 CONNECTOR_OBJECT_ID_LVDS, 1738 &hpd); 1739 /* DVI-I - primary dac, int tmds */ 1740 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1741 hpd.hpd = RADEON_HPD_1; /* ??? */ 1742 radeon_add_legacy_encoder(dev, 1743 radeon_get_encoder_enum(dev, 1744 ATOM_DEVICE_DFP1_SUPPORT, 1745 0), 1746 ATOM_DEVICE_DFP1_SUPPORT); 1747 radeon_add_legacy_encoder(dev, 1748 radeon_get_encoder_enum(dev, 1749 ATOM_DEVICE_CRT1_SUPPORT, 1750 1), 1751 ATOM_DEVICE_CRT1_SUPPORT); 1752 radeon_add_legacy_connector(dev, 1, 1753 ATOM_DEVICE_DFP1_SUPPORT | 1754 ATOM_DEVICE_CRT1_SUPPORT, 1755 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1756 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1757 &hpd); 1758 /* TV - TV DAC */ 1759 ddc_i2c.valid = false; 1760 hpd.hpd = RADEON_HPD_NONE; 1761 radeon_add_legacy_encoder(dev, 1762 radeon_get_encoder_enum(dev, 1763 ATOM_DEVICE_TV1_SUPPORT, 1764 2), 1765 ATOM_DEVICE_TV1_SUPPORT); 1766 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1767 DRM_MODE_CONNECTOR_SVIDEO, 1768 &ddc_i2c, 1769 CONNECTOR_OBJECT_ID_SVIDEO, 1770 &hpd); 1771 break; 1772 case CT_POWERBOOK_VGA: 1773 DRM_INFO("Connector Table: %d (powerbook vga)\n", 1774 rdev->mode_info.connector_table); 1775 /* LVDS */ 1776 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1777 hpd.hpd = RADEON_HPD_NONE; 1778 radeon_add_legacy_encoder(dev, 1779 radeon_get_encoder_enum(dev, 1780 ATOM_DEVICE_LCD1_SUPPORT, 1781 0), 1782 ATOM_DEVICE_LCD1_SUPPORT); 1783 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1784 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1785 CONNECTOR_OBJECT_ID_LVDS, 1786 &hpd); 1787 /* VGA - primary dac */ 1788 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1789 hpd.hpd = RADEON_HPD_NONE; 1790 radeon_add_legacy_encoder(dev, 1791 radeon_get_encoder_enum(dev, 1792 ATOM_DEVICE_CRT1_SUPPORT, 1793 1), 1794 ATOM_DEVICE_CRT1_SUPPORT); 1795 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, 1796 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1797 CONNECTOR_OBJECT_ID_VGA, 1798 &hpd); 1799 /* TV - TV DAC */ 1800 ddc_i2c.valid = false; 1801 hpd.hpd = RADEON_HPD_NONE; 1802 radeon_add_legacy_encoder(dev, 1803 radeon_get_encoder_enum(dev, 1804 ATOM_DEVICE_TV1_SUPPORT, 1805 2), 1806 ATOM_DEVICE_TV1_SUPPORT); 1807 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1808 DRM_MODE_CONNECTOR_SVIDEO, 1809 &ddc_i2c, 1810 CONNECTOR_OBJECT_ID_SVIDEO, 1811 &hpd); 1812 break; 1813 case CT_MINI_EXTERNAL: 1814 DRM_INFO("Connector Table: %d (mini external tmds)\n", 1815 rdev->mode_info.connector_table); 1816 /* DVI-I - tv dac, ext tmds */ 1817 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1818 hpd.hpd = RADEON_HPD_2; /* ??? */ 1819 radeon_add_legacy_encoder(dev, 1820 radeon_get_encoder_enum(dev, 1821 ATOM_DEVICE_DFP2_SUPPORT, 1822 0), 1823 ATOM_DEVICE_DFP2_SUPPORT); 1824 radeon_add_legacy_encoder(dev, 1825 radeon_get_encoder_enum(dev, 1826 ATOM_DEVICE_CRT2_SUPPORT, 1827 2), 1828 ATOM_DEVICE_CRT2_SUPPORT); 1829 /* XXX are any DL? */ 1830 radeon_add_legacy_connector(dev, 0, 1831 ATOM_DEVICE_DFP2_SUPPORT | 1832 ATOM_DEVICE_CRT2_SUPPORT, 1833 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1834 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1835 &hpd); 1836 /* TV - TV DAC */ 1837 ddc_i2c.valid = false; 1838 hpd.hpd = RADEON_HPD_NONE; 1839 radeon_add_legacy_encoder(dev, 1840 radeon_get_encoder_enum(dev, 1841 ATOM_DEVICE_TV1_SUPPORT, 1842 2), 1843 ATOM_DEVICE_TV1_SUPPORT); 1844 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1845 DRM_MODE_CONNECTOR_SVIDEO, 1846 &ddc_i2c, 1847 CONNECTOR_OBJECT_ID_SVIDEO, 1848 &hpd); 1849 break; 1850 case CT_MINI_INTERNAL: 1851 DRM_INFO("Connector Table: %d (mini internal tmds)\n", 1852 rdev->mode_info.connector_table); 1853 /* DVI-I - tv dac, int tmds */ 1854 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1855 hpd.hpd = RADEON_HPD_1; /* ??? */ 1856 radeon_add_legacy_encoder(dev, 1857 radeon_get_encoder_enum(dev, 1858 ATOM_DEVICE_DFP1_SUPPORT, 1859 0), 1860 ATOM_DEVICE_DFP1_SUPPORT); 1861 radeon_add_legacy_encoder(dev, 1862 radeon_get_encoder_enum(dev, 1863 ATOM_DEVICE_CRT2_SUPPORT, 1864 2), 1865 ATOM_DEVICE_CRT2_SUPPORT); 1866 radeon_add_legacy_connector(dev, 0, 1867 ATOM_DEVICE_DFP1_SUPPORT | 1868 ATOM_DEVICE_CRT2_SUPPORT, 1869 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1870 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1871 &hpd); 1872 /* TV - TV DAC */ 1873 ddc_i2c.valid = false; 1874 hpd.hpd = RADEON_HPD_NONE; 1875 radeon_add_legacy_encoder(dev, 1876 radeon_get_encoder_enum(dev, 1877 ATOM_DEVICE_TV1_SUPPORT, 1878 2), 1879 ATOM_DEVICE_TV1_SUPPORT); 1880 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1881 DRM_MODE_CONNECTOR_SVIDEO, 1882 &ddc_i2c, 1883 CONNECTOR_OBJECT_ID_SVIDEO, 1884 &hpd); 1885 break; 1886 case CT_IMAC_G5_ISIGHT: 1887 DRM_INFO("Connector Table: %d (imac g5 isight)\n", 1888 rdev->mode_info.connector_table); 1889 /* DVI-D - int tmds */ 1890 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1891 hpd.hpd = RADEON_HPD_1; /* ??? */ 1892 radeon_add_legacy_encoder(dev, 1893 radeon_get_encoder_enum(dev, 1894 ATOM_DEVICE_DFP1_SUPPORT, 1895 0), 1896 ATOM_DEVICE_DFP1_SUPPORT); 1897 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT, 1898 DRM_MODE_CONNECTOR_DVID, &ddc_i2c, 1899 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 1900 &hpd); 1901 /* VGA - tv dac */ 1902 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1903 hpd.hpd = RADEON_HPD_NONE; 1904 radeon_add_legacy_encoder(dev, 1905 radeon_get_encoder_enum(dev, 1906 ATOM_DEVICE_CRT2_SUPPORT, 1907 2), 1908 ATOM_DEVICE_CRT2_SUPPORT); 1909 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1910 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1911 CONNECTOR_OBJECT_ID_VGA, 1912 &hpd); 1913 /* TV - TV DAC */ 1914 ddc_i2c.valid = false; 1915 hpd.hpd = RADEON_HPD_NONE; 1916 radeon_add_legacy_encoder(dev, 1917 radeon_get_encoder_enum(dev, 1918 ATOM_DEVICE_TV1_SUPPORT, 1919 2), 1920 ATOM_DEVICE_TV1_SUPPORT); 1921 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1922 DRM_MODE_CONNECTOR_SVIDEO, 1923 &ddc_i2c, 1924 CONNECTOR_OBJECT_ID_SVIDEO, 1925 &hpd); 1926 break; 1927 case CT_EMAC: 1928 DRM_INFO("Connector Table: %d (emac)\n", 1929 rdev->mode_info.connector_table); 1930 /* VGA - primary dac */ 1931 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1932 hpd.hpd = RADEON_HPD_NONE; 1933 radeon_add_legacy_encoder(dev, 1934 radeon_get_encoder_enum(dev, 1935 ATOM_DEVICE_CRT1_SUPPORT, 1936 1), 1937 ATOM_DEVICE_CRT1_SUPPORT); 1938 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, 1939 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1940 CONNECTOR_OBJECT_ID_VGA, 1941 &hpd); 1942 /* VGA - tv dac */ 1943 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1944 hpd.hpd = RADEON_HPD_NONE; 1945 radeon_add_legacy_encoder(dev, 1946 radeon_get_encoder_enum(dev, 1947 ATOM_DEVICE_CRT2_SUPPORT, 1948 2), 1949 ATOM_DEVICE_CRT2_SUPPORT); 1950 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1951 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1952 CONNECTOR_OBJECT_ID_VGA, 1953 &hpd); 1954 /* TV - TV DAC */ 1955 ddc_i2c.valid = false; 1956 hpd.hpd = RADEON_HPD_NONE; 1957 radeon_add_legacy_encoder(dev, 1958 radeon_get_encoder_enum(dev, 1959 ATOM_DEVICE_TV1_SUPPORT, 1960 2), 1961 ATOM_DEVICE_TV1_SUPPORT); 1962 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1963 DRM_MODE_CONNECTOR_SVIDEO, 1964 &ddc_i2c, 1965 CONNECTOR_OBJECT_ID_SVIDEO, 1966 &hpd); 1967 break; 1968 case CT_RN50_POWER: 1969 DRM_INFO("Connector Table: %d (rn50-power)\n", 1970 rdev->mode_info.connector_table); 1971 /* VGA - primary dac */ 1972 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1973 hpd.hpd = RADEON_HPD_NONE; 1974 radeon_add_legacy_encoder(dev, 1975 radeon_get_encoder_enum(dev, 1976 ATOM_DEVICE_CRT1_SUPPORT, 1977 1), 1978 ATOM_DEVICE_CRT1_SUPPORT); 1979 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, 1980 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1981 CONNECTOR_OBJECT_ID_VGA, 1982 &hpd); 1983 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1984 hpd.hpd = RADEON_HPD_NONE; 1985 radeon_add_legacy_encoder(dev, 1986 radeon_get_encoder_enum(dev, 1987 ATOM_DEVICE_CRT2_SUPPORT, 1988 2), 1989 ATOM_DEVICE_CRT2_SUPPORT); 1990 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1991 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1992 CONNECTOR_OBJECT_ID_VGA, 1993 &hpd); 1994 break; 1995 case CT_MAC_X800: 1996 DRM_INFO("Connector Table: %d (mac x800)\n", 1997 rdev->mode_info.connector_table); 1998 /* DVI - primary dac, internal tmds */ 1999 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2000 hpd.hpd = RADEON_HPD_1; /* ??? */ 2001 radeon_add_legacy_encoder(dev, 2002 radeon_get_encoder_enum(dev, 2003 ATOM_DEVICE_DFP1_SUPPORT, 2004 0), 2005 ATOM_DEVICE_DFP1_SUPPORT); 2006 radeon_add_legacy_encoder(dev, 2007 radeon_get_encoder_enum(dev, 2008 ATOM_DEVICE_CRT1_SUPPORT, 2009 1), 2010 ATOM_DEVICE_CRT1_SUPPORT); 2011 radeon_add_legacy_connector(dev, 0, 2012 ATOM_DEVICE_DFP1_SUPPORT | 2013 ATOM_DEVICE_CRT1_SUPPORT, 2014 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2015 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2016 &hpd); 2017 /* DVI - tv dac, dvo */ 2018 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 2019 hpd.hpd = RADEON_HPD_2; /* ??? */ 2020 radeon_add_legacy_encoder(dev, 2021 radeon_get_encoder_enum(dev, 2022 ATOM_DEVICE_DFP2_SUPPORT, 2023 0), 2024 ATOM_DEVICE_DFP2_SUPPORT); 2025 radeon_add_legacy_encoder(dev, 2026 radeon_get_encoder_enum(dev, 2027 ATOM_DEVICE_CRT2_SUPPORT, 2028 2), 2029 ATOM_DEVICE_CRT2_SUPPORT); 2030 radeon_add_legacy_connector(dev, 1, 2031 ATOM_DEVICE_DFP2_SUPPORT | 2032 ATOM_DEVICE_CRT2_SUPPORT, 2033 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2034 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, 2035 &hpd); 2036 break; 2037 case CT_MAC_G5_9600: 2038 DRM_INFO("Connector Table: %d (mac g5 9600)\n", 2039 rdev->mode_info.connector_table); 2040 /* DVI - tv dac, dvo */ 2041 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2042 hpd.hpd = RADEON_HPD_1; /* ??? */ 2043 radeon_add_legacy_encoder(dev, 2044 radeon_get_encoder_enum(dev, 2045 ATOM_DEVICE_DFP2_SUPPORT, 2046 0), 2047 ATOM_DEVICE_DFP2_SUPPORT); 2048 radeon_add_legacy_encoder(dev, 2049 radeon_get_encoder_enum(dev, 2050 ATOM_DEVICE_CRT2_SUPPORT, 2051 2), 2052 ATOM_DEVICE_CRT2_SUPPORT); 2053 radeon_add_legacy_connector(dev, 0, 2054 ATOM_DEVICE_DFP2_SUPPORT | 2055 ATOM_DEVICE_CRT2_SUPPORT, 2056 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2057 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2058 &hpd); 2059 /* ADC - primary dac, internal tmds */ 2060 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2061 hpd.hpd = RADEON_HPD_2; /* ??? */ 2062 radeon_add_legacy_encoder(dev, 2063 radeon_get_encoder_enum(dev, 2064 ATOM_DEVICE_DFP1_SUPPORT, 2065 0), 2066 ATOM_DEVICE_DFP1_SUPPORT); 2067 radeon_add_legacy_encoder(dev, 2068 radeon_get_encoder_enum(dev, 2069 ATOM_DEVICE_CRT1_SUPPORT, 2070 1), 2071 ATOM_DEVICE_CRT1_SUPPORT); 2072 radeon_add_legacy_connector(dev, 1, 2073 ATOM_DEVICE_DFP1_SUPPORT | 2074 ATOM_DEVICE_CRT1_SUPPORT, 2075 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2076 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2077 &hpd); 2078 /* TV - TV DAC */ 2079 ddc_i2c.valid = false; 2080 hpd.hpd = RADEON_HPD_NONE; 2081 radeon_add_legacy_encoder(dev, 2082 radeon_get_encoder_enum(dev, 2083 ATOM_DEVICE_TV1_SUPPORT, 2084 2), 2085 ATOM_DEVICE_TV1_SUPPORT); 2086 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 2087 DRM_MODE_CONNECTOR_SVIDEO, 2088 &ddc_i2c, 2089 CONNECTOR_OBJECT_ID_SVIDEO, 2090 &hpd); 2091 break; 2092 case CT_SAM440EP: 2093 DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n", 2094 rdev->mode_info.connector_table); 2095 /* LVDS */ 2096 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); 2097 hpd.hpd = RADEON_HPD_NONE; 2098 radeon_add_legacy_encoder(dev, 2099 radeon_get_encoder_enum(dev, 2100 ATOM_DEVICE_LCD1_SUPPORT, 2101 0), 2102 ATOM_DEVICE_LCD1_SUPPORT); 2103 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 2104 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 2105 CONNECTOR_OBJECT_ID_LVDS, 2106 &hpd); 2107 /* DVI-I - secondary dac, int tmds */ 2108 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2109 hpd.hpd = RADEON_HPD_1; /* ??? */ 2110 radeon_add_legacy_encoder(dev, 2111 radeon_get_encoder_enum(dev, 2112 ATOM_DEVICE_DFP1_SUPPORT, 2113 0), 2114 ATOM_DEVICE_DFP1_SUPPORT); 2115 radeon_add_legacy_encoder(dev, 2116 radeon_get_encoder_enum(dev, 2117 ATOM_DEVICE_CRT2_SUPPORT, 2118 2), 2119 ATOM_DEVICE_CRT2_SUPPORT); 2120 radeon_add_legacy_connector(dev, 1, 2121 ATOM_DEVICE_DFP1_SUPPORT | 2122 ATOM_DEVICE_CRT2_SUPPORT, 2123 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2124 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2125 &hpd); 2126 /* VGA - primary dac */ 2127 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2128 hpd.hpd = RADEON_HPD_NONE; 2129 radeon_add_legacy_encoder(dev, 2130 radeon_get_encoder_enum(dev, 2131 ATOM_DEVICE_CRT1_SUPPORT, 2132 1), 2133 ATOM_DEVICE_CRT1_SUPPORT); 2134 radeon_add_legacy_connector(dev, 2, 2135 ATOM_DEVICE_CRT1_SUPPORT, 2136 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 2137 CONNECTOR_OBJECT_ID_VGA, 2138 &hpd); 2139 /* TV - TV DAC */ 2140 ddc_i2c.valid = false; 2141 hpd.hpd = RADEON_HPD_NONE; 2142 radeon_add_legacy_encoder(dev, 2143 radeon_get_encoder_enum(dev, 2144 ATOM_DEVICE_TV1_SUPPORT, 2145 2), 2146 ATOM_DEVICE_TV1_SUPPORT); 2147 radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT, 2148 DRM_MODE_CONNECTOR_SVIDEO, 2149 &ddc_i2c, 2150 CONNECTOR_OBJECT_ID_SVIDEO, 2151 &hpd); 2152 break; 2153 case CT_MAC_G4_SILVER: 2154 DRM_INFO("Connector Table: %d (mac g4 silver)\n", 2155 rdev->mode_info.connector_table); 2156 /* DVI-I - tv dac, int tmds */ 2157 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2158 hpd.hpd = RADEON_HPD_1; /* ??? */ 2159 radeon_add_legacy_encoder(dev, 2160 radeon_get_encoder_enum(dev, 2161 ATOM_DEVICE_DFP1_SUPPORT, 2162 0), 2163 ATOM_DEVICE_DFP1_SUPPORT); 2164 radeon_add_legacy_encoder(dev, 2165 radeon_get_encoder_enum(dev, 2166 ATOM_DEVICE_CRT2_SUPPORT, 2167 2), 2168 ATOM_DEVICE_CRT2_SUPPORT); 2169 radeon_add_legacy_connector(dev, 0, 2170 ATOM_DEVICE_DFP1_SUPPORT | 2171 ATOM_DEVICE_CRT2_SUPPORT, 2172 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2173 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2174 &hpd); 2175 /* VGA - primary dac */ 2176 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2177 hpd.hpd = RADEON_HPD_NONE; 2178 radeon_add_legacy_encoder(dev, 2179 radeon_get_encoder_enum(dev, 2180 ATOM_DEVICE_CRT1_SUPPORT, 2181 1), 2182 ATOM_DEVICE_CRT1_SUPPORT); 2183 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, 2184 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 2185 CONNECTOR_OBJECT_ID_VGA, 2186 &hpd); 2187 /* TV - TV DAC */ 2188 ddc_i2c.valid = false; 2189 hpd.hpd = RADEON_HPD_NONE; 2190 radeon_add_legacy_encoder(dev, 2191 radeon_get_encoder_enum(dev, 2192 ATOM_DEVICE_TV1_SUPPORT, 2193 2), 2194 ATOM_DEVICE_TV1_SUPPORT); 2195 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 2196 DRM_MODE_CONNECTOR_SVIDEO, 2197 &ddc_i2c, 2198 CONNECTOR_OBJECT_ID_SVIDEO, 2199 &hpd); 2200 break; 2201 default: 2202 DRM_INFO("Connector table: %d (invalid)\n", 2203 rdev->mode_info.connector_table); 2204 return false; 2205 } 2206 2207 radeon_link_encoder_connector(dev); 2208 2209 return true; 2210 } 2211 2212 static bool radeon_apply_legacy_quirks(struct drm_device *dev, 2213 int bios_index, 2214 enum radeon_combios_connector 2215 *legacy_connector, 2216 struct radeon_i2c_bus_rec *ddc_i2c, 2217 struct radeon_hpd *hpd) 2218 { 2219 2220 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, 2221 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ 2222 if (dev->pdev->device == 0x515e && 2223 dev->pdev->subsystem_vendor == 0x1014) { 2224 if (*legacy_connector == CONNECTOR_CRT_LEGACY && 2225 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) 2226 return false; 2227 } 2228 2229 /* X300 card with extra non-existent DVI port */ 2230 if (dev->pdev->device == 0x5B60 && 2231 dev->pdev->subsystem_vendor == 0x17af && 2232 dev->pdev->subsystem_device == 0x201e && bios_index == 2) { 2233 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY) 2234 return false; 2235 } 2236 2237 return true; 2238 } 2239 2240 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev) 2241 { 2242 /* Acer 5102 has non-existent TV port */ 2243 if (dev->pdev->device == 0x5975 && 2244 dev->pdev->subsystem_vendor == 0x1025 && 2245 dev->pdev->subsystem_device == 0x009f) 2246 return false; 2247 2248 /* HP dc5750 has non-existent TV port */ 2249 if (dev->pdev->device == 0x5974 && 2250 dev->pdev->subsystem_vendor == 0x103c && 2251 dev->pdev->subsystem_device == 0x280a) 2252 return false; 2253 2254 /* MSI S270 has non-existent TV port */ 2255 if (dev->pdev->device == 0x5955 && 2256 dev->pdev->subsystem_vendor == 0x1462 && 2257 dev->pdev->subsystem_device == 0x0131) 2258 return false; 2259 2260 return true; 2261 } 2262 2263 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d) 2264 { 2265 struct radeon_device *rdev = dev->dev_private; 2266 uint32_t ext_tmds_info; 2267 2268 if (rdev->flags & RADEON_IS_IGP) { 2269 if (is_dvi_d) 2270 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 2271 else 2272 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2273 } 2274 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 2275 if (ext_tmds_info) { 2276 uint8_t rev = RBIOS8(ext_tmds_info); 2277 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5); 2278 if (rev >= 3) { 2279 if (is_dvi_d) 2280 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 2281 else 2282 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 2283 } else { 2284 if (flags & 1) { 2285 if (is_dvi_d) 2286 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 2287 else 2288 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 2289 } 2290 } 2291 } 2292 if (is_dvi_d) 2293 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 2294 else 2295 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2296 } 2297 2298 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) 2299 { 2300 struct radeon_device *rdev = dev->dev_private; 2301 uint32_t conn_info, entry, devices; 2302 uint16_t tmp, connector_object_id; 2303 enum radeon_combios_ddc ddc_type; 2304 enum radeon_combios_connector connector; 2305 int i = 0; 2306 struct radeon_i2c_bus_rec ddc_i2c; 2307 struct radeon_hpd hpd; 2308 2309 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE); 2310 if (conn_info) { 2311 for (i = 0; i < 4; i++) { 2312 entry = conn_info + 2 + i * 2; 2313 2314 if (!RBIOS16(entry)) 2315 break; 2316 2317 tmp = RBIOS16(entry); 2318 2319 connector = (tmp >> 12) & 0xf; 2320 2321 ddc_type = (tmp >> 8) & 0xf; 2322 if (ddc_type == 5) 2323 ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev); 2324 else 2325 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0); 2326 2327 switch (connector) { 2328 case CONNECTOR_PROPRIETARY_LEGACY: 2329 case CONNECTOR_DVI_I_LEGACY: 2330 case CONNECTOR_DVI_D_LEGACY: 2331 if ((tmp >> 4) & 0x1) 2332 hpd.hpd = RADEON_HPD_2; 2333 else 2334 hpd.hpd = RADEON_HPD_1; 2335 break; 2336 default: 2337 hpd.hpd = RADEON_HPD_NONE; 2338 break; 2339 } 2340 2341 if (!radeon_apply_legacy_quirks(dev, i, &connector, 2342 &ddc_i2c, &hpd)) 2343 continue; 2344 2345 switch (connector) { 2346 case CONNECTOR_PROPRIETARY_LEGACY: 2347 if ((tmp >> 4) & 0x1) 2348 devices = ATOM_DEVICE_DFP2_SUPPORT; 2349 else 2350 devices = ATOM_DEVICE_DFP1_SUPPORT; 2351 radeon_add_legacy_encoder(dev, 2352 radeon_get_encoder_enum 2353 (dev, devices, 0), 2354 devices); 2355 radeon_add_legacy_connector(dev, i, devices, 2356 legacy_connector_convert 2357 [connector], 2358 &ddc_i2c, 2359 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 2360 &hpd); 2361 break; 2362 case CONNECTOR_CRT_LEGACY: 2363 if (tmp & 0x1) { 2364 devices = ATOM_DEVICE_CRT2_SUPPORT; 2365 radeon_add_legacy_encoder(dev, 2366 radeon_get_encoder_enum 2367 (dev, 2368 ATOM_DEVICE_CRT2_SUPPORT, 2369 2), 2370 ATOM_DEVICE_CRT2_SUPPORT); 2371 } else { 2372 devices = ATOM_DEVICE_CRT1_SUPPORT; 2373 radeon_add_legacy_encoder(dev, 2374 radeon_get_encoder_enum 2375 (dev, 2376 ATOM_DEVICE_CRT1_SUPPORT, 2377 1), 2378 ATOM_DEVICE_CRT1_SUPPORT); 2379 } 2380 radeon_add_legacy_connector(dev, 2381 i, 2382 devices, 2383 legacy_connector_convert 2384 [connector], 2385 &ddc_i2c, 2386 CONNECTOR_OBJECT_ID_VGA, 2387 &hpd); 2388 break; 2389 case CONNECTOR_DVI_I_LEGACY: 2390 devices = 0; 2391 if (tmp & 0x1) { 2392 devices |= ATOM_DEVICE_CRT2_SUPPORT; 2393 radeon_add_legacy_encoder(dev, 2394 radeon_get_encoder_enum 2395 (dev, 2396 ATOM_DEVICE_CRT2_SUPPORT, 2397 2), 2398 ATOM_DEVICE_CRT2_SUPPORT); 2399 } else { 2400 devices |= ATOM_DEVICE_CRT1_SUPPORT; 2401 radeon_add_legacy_encoder(dev, 2402 radeon_get_encoder_enum 2403 (dev, 2404 ATOM_DEVICE_CRT1_SUPPORT, 2405 1), 2406 ATOM_DEVICE_CRT1_SUPPORT); 2407 } 2408 /* RV100 board with external TDMS bit mis-set. 2409 * Actually uses internal TMDS, clear the bit. 2410 */ 2411 if (dev->pdev->device == 0x5159 && 2412 dev->pdev->subsystem_vendor == 0x1014 && 2413 dev->pdev->subsystem_device == 0x029A) { 2414 tmp &= ~(1 << 4); 2415 } 2416 if ((tmp >> 4) & 0x1) { 2417 devices |= ATOM_DEVICE_DFP2_SUPPORT; 2418 radeon_add_legacy_encoder(dev, 2419 radeon_get_encoder_enum 2420 (dev, 2421 ATOM_DEVICE_DFP2_SUPPORT, 2422 0), 2423 ATOM_DEVICE_DFP2_SUPPORT); 2424 connector_object_id = combios_check_dl_dvi(dev, 0); 2425 } else { 2426 devices |= ATOM_DEVICE_DFP1_SUPPORT; 2427 radeon_add_legacy_encoder(dev, 2428 radeon_get_encoder_enum 2429 (dev, 2430 ATOM_DEVICE_DFP1_SUPPORT, 2431 0), 2432 ATOM_DEVICE_DFP1_SUPPORT); 2433 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2434 } 2435 radeon_add_legacy_connector(dev, 2436 i, 2437 devices, 2438 legacy_connector_convert 2439 [connector], 2440 &ddc_i2c, 2441 connector_object_id, 2442 &hpd); 2443 break; 2444 case CONNECTOR_DVI_D_LEGACY: 2445 if ((tmp >> 4) & 0x1) { 2446 devices = ATOM_DEVICE_DFP2_SUPPORT; 2447 connector_object_id = combios_check_dl_dvi(dev, 1); 2448 } else { 2449 devices = ATOM_DEVICE_DFP1_SUPPORT; 2450 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2451 } 2452 radeon_add_legacy_encoder(dev, 2453 radeon_get_encoder_enum 2454 (dev, devices, 0), 2455 devices); 2456 radeon_add_legacy_connector(dev, i, devices, 2457 legacy_connector_convert 2458 [connector], 2459 &ddc_i2c, 2460 connector_object_id, 2461 &hpd); 2462 break; 2463 case CONNECTOR_CTV_LEGACY: 2464 case CONNECTOR_STV_LEGACY: 2465 radeon_add_legacy_encoder(dev, 2466 radeon_get_encoder_enum 2467 (dev, 2468 ATOM_DEVICE_TV1_SUPPORT, 2469 2), 2470 ATOM_DEVICE_TV1_SUPPORT); 2471 radeon_add_legacy_connector(dev, i, 2472 ATOM_DEVICE_TV1_SUPPORT, 2473 legacy_connector_convert 2474 [connector], 2475 &ddc_i2c, 2476 CONNECTOR_OBJECT_ID_SVIDEO, 2477 &hpd); 2478 break; 2479 default: 2480 DRM_ERROR("Unknown connector type: %d\n", 2481 connector); 2482 continue; 2483 } 2484 2485 } 2486 } else { 2487 uint16_t tmds_info = 2488 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 2489 if (tmds_info) { 2490 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n"); 2491 2492 radeon_add_legacy_encoder(dev, 2493 radeon_get_encoder_enum(dev, 2494 ATOM_DEVICE_CRT1_SUPPORT, 2495 1), 2496 ATOM_DEVICE_CRT1_SUPPORT); 2497 radeon_add_legacy_encoder(dev, 2498 radeon_get_encoder_enum(dev, 2499 ATOM_DEVICE_DFP1_SUPPORT, 2500 0), 2501 ATOM_DEVICE_DFP1_SUPPORT); 2502 2503 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2504 hpd.hpd = RADEON_HPD_1; 2505 radeon_add_legacy_connector(dev, 2506 0, 2507 ATOM_DEVICE_CRT1_SUPPORT | 2508 ATOM_DEVICE_DFP1_SUPPORT, 2509 DRM_MODE_CONNECTOR_DVII, 2510 &ddc_i2c, 2511 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2512 &hpd); 2513 } else { 2514 uint16_t crt_info = 2515 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 2516 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n"); 2517 if (crt_info) { 2518 radeon_add_legacy_encoder(dev, 2519 radeon_get_encoder_enum(dev, 2520 ATOM_DEVICE_CRT1_SUPPORT, 2521 1), 2522 ATOM_DEVICE_CRT1_SUPPORT); 2523 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2524 hpd.hpd = RADEON_HPD_NONE; 2525 radeon_add_legacy_connector(dev, 2526 0, 2527 ATOM_DEVICE_CRT1_SUPPORT, 2528 DRM_MODE_CONNECTOR_VGA, 2529 &ddc_i2c, 2530 CONNECTOR_OBJECT_ID_VGA, 2531 &hpd); 2532 } else { 2533 DRM_DEBUG_KMS("No connector info found\n"); 2534 return false; 2535 } 2536 } 2537 } 2538 2539 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) { 2540 uint16_t lcd_info = 2541 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 2542 if (lcd_info) { 2543 uint16_t lcd_ddc_info = 2544 combios_get_table_offset(dev, 2545 COMBIOS_LCD_DDC_INFO_TABLE); 2546 2547 radeon_add_legacy_encoder(dev, 2548 radeon_get_encoder_enum(dev, 2549 ATOM_DEVICE_LCD1_SUPPORT, 2550 0), 2551 ATOM_DEVICE_LCD1_SUPPORT); 2552 2553 if (lcd_ddc_info) { 2554 ddc_type = RBIOS8(lcd_ddc_info + 2); 2555 switch (ddc_type) { 2556 case DDC_LCD: 2557 ddc_i2c = 2558 combios_setup_i2c_bus(rdev, 2559 DDC_LCD, 2560 RBIOS32(lcd_ddc_info + 3), 2561 RBIOS32(lcd_ddc_info + 7)); 2562 radeon_i2c_add(rdev, &ddc_i2c, "LCD"); 2563 break; 2564 case DDC_GPIO: 2565 ddc_i2c = 2566 combios_setup_i2c_bus(rdev, 2567 DDC_GPIO, 2568 RBIOS32(lcd_ddc_info + 3), 2569 RBIOS32(lcd_ddc_info + 7)); 2570 radeon_i2c_add(rdev, &ddc_i2c, "LCD"); 2571 break; 2572 default: 2573 ddc_i2c = 2574 combios_setup_i2c_bus(rdev, ddc_type, 0, 0); 2575 break; 2576 } 2577 DRM_DEBUG_KMS("LCD DDC Info Table found!\n"); 2578 } else 2579 ddc_i2c.valid = false; 2580 2581 hpd.hpd = RADEON_HPD_NONE; 2582 radeon_add_legacy_connector(dev, 2583 5, 2584 ATOM_DEVICE_LCD1_SUPPORT, 2585 DRM_MODE_CONNECTOR_LVDS, 2586 &ddc_i2c, 2587 CONNECTOR_OBJECT_ID_LVDS, 2588 &hpd); 2589 } 2590 } 2591 2592 /* check TV table */ 2593 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 2594 uint32_t tv_info = 2595 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 2596 if (tv_info) { 2597 if (RBIOS8(tv_info + 6) == 'T') { 2598 if (radeon_apply_legacy_tv_quirks(dev)) { 2599 hpd.hpd = RADEON_HPD_NONE; 2600 ddc_i2c.valid = false; 2601 radeon_add_legacy_encoder(dev, 2602 radeon_get_encoder_enum 2603 (dev, 2604 ATOM_DEVICE_TV1_SUPPORT, 2605 2), 2606 ATOM_DEVICE_TV1_SUPPORT); 2607 radeon_add_legacy_connector(dev, 6, 2608 ATOM_DEVICE_TV1_SUPPORT, 2609 DRM_MODE_CONNECTOR_SVIDEO, 2610 &ddc_i2c, 2611 CONNECTOR_OBJECT_ID_SVIDEO, 2612 &hpd); 2613 } 2614 } 2615 } 2616 } 2617 2618 radeon_link_encoder_connector(dev); 2619 2620 return true; 2621 } 2622 2623 static const char *thermal_controller_names[] = { 2624 "NONE", 2625 "lm63", 2626 "adm1032", 2627 }; 2628 2629 void radeon_combios_get_power_modes(struct radeon_device *rdev) 2630 { 2631 struct drm_device *dev = rdev->ddev; 2632 u16 offset, misc, misc2 = 0; 2633 u8 rev, blocks, tmp; 2634 int state_index = 0; 2635 struct radeon_i2c_bus_rec i2c_bus; 2636 2637 rdev->pm.default_power_state_index = -1; 2638 2639 /* allocate 2 power states */ 2640 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL); 2641 if (rdev->pm.power_state) { 2642 /* allocate 1 clock mode per state */ 2643 rdev->pm.power_state[0].clock_info = 2644 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); 2645 rdev->pm.power_state[1].clock_info = 2646 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); 2647 if (!rdev->pm.power_state[0].clock_info || 2648 !rdev->pm.power_state[1].clock_info) 2649 goto pm_failed; 2650 } else 2651 goto pm_failed; 2652 2653 /* check for a thermal chip */ 2654 offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE); 2655 if (offset) { 2656 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0; 2657 2658 rev = RBIOS8(offset); 2659 2660 if (rev == 0) { 2661 thermal_controller = RBIOS8(offset + 3); 2662 gpio = RBIOS8(offset + 4) & 0x3f; 2663 i2c_addr = RBIOS8(offset + 5); 2664 } else if (rev == 1) { 2665 thermal_controller = RBIOS8(offset + 4); 2666 gpio = RBIOS8(offset + 5) & 0x3f; 2667 i2c_addr = RBIOS8(offset + 6); 2668 } else if (rev == 2) { 2669 thermal_controller = RBIOS8(offset + 4); 2670 gpio = RBIOS8(offset + 5) & 0x3f; 2671 i2c_addr = RBIOS8(offset + 6); 2672 clk_bit = RBIOS8(offset + 0xa); 2673 data_bit = RBIOS8(offset + 0xb); 2674 } 2675 if ((thermal_controller > 0) && (thermal_controller < 3)) { 2676 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 2677 thermal_controller_names[thermal_controller], 2678 i2c_addr >> 1); 2679 if (gpio == DDC_LCD) { 2680 /* MM i2c */ 2681 i2c_bus.valid = true; 2682 i2c_bus.hw_capable = true; 2683 i2c_bus.mm_i2c = true; 2684 i2c_bus.i2c_id = 0xa0; 2685 } else if (gpio == DDC_GPIO) 2686 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit); 2687 else 2688 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); 2689 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2690 if (rdev->pm.i2c_bus) { 2691 #ifdef DUMBBELL_WIP 2692 struct i2c_board_info info = { }; 2693 const char *name = thermal_controller_names[thermal_controller]; 2694 info.addr = i2c_addr >> 1; 2695 strlcpy(info.type, name, sizeof(info.type)); 2696 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); 2697 #endif /* DUMBBELL_WIP */ 2698 } 2699 } 2700 } else { 2701 /* boards with a thermal chip, but no overdrive table */ 2702 2703 /* Asus 9600xt has an f75375 on the monid bus */ 2704 if ((dev->pdev->device == 0x4152) && 2705 (dev->pdev->subsystem_vendor == 0x1043) && 2706 (dev->pdev->subsystem_device == 0xc002)) { 2707 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 2708 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2709 if (rdev->pm.i2c_bus) { 2710 #ifdef DUMBBELL_WIP 2711 struct i2c_board_info info = { }; 2712 const char *name = "f75375"; 2713 info.addr = 0x28; 2714 strlcpy(info.type, name, sizeof(info.type)); 2715 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); 2716 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 2717 name, info.addr); 2718 #endif /* DUMBBELL_WIP */ 2719 } 2720 } 2721 } 2722 2723 if (rdev->flags & RADEON_IS_MOBILITY) { 2724 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE); 2725 if (offset) { 2726 rev = RBIOS8(offset); 2727 blocks = RBIOS8(offset + 0x2); 2728 /* power mode 0 tends to be the only valid one */ 2729 rdev->pm.power_state[state_index].num_clock_modes = 1; 2730 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2); 2731 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6); 2732 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2733 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2734 goto default_mode; 2735 rdev->pm.power_state[state_index].type = 2736 POWER_STATE_TYPE_BATTERY; 2737 misc = RBIOS16(offset + 0x5 + 0x0); 2738 if (rev > 4) 2739 misc2 = RBIOS16(offset + 0x5 + 0xe); 2740 rdev->pm.power_state[state_index].misc = misc; 2741 rdev->pm.power_state[state_index].misc2 = misc2; 2742 if (misc & 0x4) { 2743 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO; 2744 if (misc & 0x8) 2745 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2746 true; 2747 else 2748 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2749 false; 2750 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true; 2751 if (rev < 6) { 2752 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = 2753 RBIOS16(offset + 0x5 + 0xb) * 4; 2754 tmp = RBIOS8(offset + 0x5 + 0xd); 2755 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); 2756 } else { 2757 u8 entries = RBIOS8(offset + 0x5 + 0xb); 2758 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc); 2759 if (entries && voltage_table_offset) { 2760 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = 2761 RBIOS16(voltage_table_offset) * 4; 2762 tmp = RBIOS8(voltage_table_offset + 0x2); 2763 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); 2764 } else 2765 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false; 2766 } 2767 switch ((misc2 & 0x700) >> 8) { 2768 case 0: 2769 default: 2770 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0; 2771 break; 2772 case 1: 2773 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33; 2774 break; 2775 case 2: 2776 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66; 2777 break; 2778 case 3: 2779 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99; 2780 break; 2781 case 4: 2782 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132; 2783 break; 2784 } 2785 } else 2786 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2787 if (rev > 6) 2788 rdev->pm.power_state[state_index].pcie_lanes = 2789 RBIOS8(offset + 0x5 + 0x10); 2790 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2791 state_index++; 2792 } else { 2793 /* XXX figure out some good default low power mode for mobility cards w/out power tables */ 2794 } 2795 } else { 2796 /* XXX figure out some good default low power mode for desktop cards */ 2797 } 2798 2799 default_mode: 2800 /* add the default mode */ 2801 rdev->pm.power_state[state_index].type = 2802 POWER_STATE_TYPE_DEFAULT; 2803 rdev->pm.power_state[state_index].num_clock_modes = 1; 2804 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; 2805 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; 2806 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; 2807 if ((state_index > 0) && 2808 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO)) 2809 rdev->pm.power_state[state_index].clock_info[0].voltage = 2810 rdev->pm.power_state[0].clock_info[0].voltage; 2811 else 2812 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2813 rdev->pm.power_state[state_index].pcie_lanes = 16; 2814 rdev->pm.power_state[state_index].flags = 0; 2815 rdev->pm.default_power_state_index = state_index; 2816 rdev->pm.num_power_states = state_index + 1; 2817 2818 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2819 rdev->pm.current_clock_mode_index = 0; 2820 return; 2821 2822 pm_failed: 2823 rdev->pm.default_power_state_index = state_index; 2824 rdev->pm.num_power_states = 0; 2825 2826 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2827 rdev->pm.current_clock_mode_index = 0; 2828 } 2829 2830 void radeon_external_tmds_setup(struct drm_encoder *encoder) 2831 { 2832 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2833 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2834 2835 if (!tmds) 2836 return; 2837 2838 switch (tmds->dvo_chip) { 2839 case DVO_SIL164: 2840 /* sil 164 */ 2841 radeon_i2c_put_byte(tmds->i2c_bus, 2842 tmds->slave_addr, 2843 0x08, 0x30); 2844 radeon_i2c_put_byte(tmds->i2c_bus, 2845 tmds->slave_addr, 2846 0x09, 0x00); 2847 radeon_i2c_put_byte(tmds->i2c_bus, 2848 tmds->slave_addr, 2849 0x0a, 0x90); 2850 radeon_i2c_put_byte(tmds->i2c_bus, 2851 tmds->slave_addr, 2852 0x0c, 0x89); 2853 radeon_i2c_put_byte(tmds->i2c_bus, 2854 tmds->slave_addr, 2855 0x08, 0x3b); 2856 break; 2857 case DVO_SIL1178: 2858 /* sil 1178 - untested */ 2859 /* 2860 * 0x0f, 0x44 2861 * 0x0f, 0x4c 2862 * 0x0e, 0x01 2863 * 0x0a, 0x80 2864 * 0x09, 0x30 2865 * 0x0c, 0xc9 2866 * 0x0d, 0x70 2867 * 0x08, 0x32 2868 * 0x08, 0x33 2869 */ 2870 break; 2871 default: 2872 break; 2873 } 2874 2875 } 2876 2877 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder) 2878 { 2879 struct drm_device *dev = encoder->dev; 2880 struct radeon_device *rdev = dev->dev_private; 2881 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2882 uint16_t offset; 2883 uint8_t blocks, slave_addr, rev; 2884 uint32_t index, id; 2885 uint32_t reg, val, and_mask, or_mask; 2886 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2887 2888 if (!tmds) 2889 return false; 2890 2891 if (rdev->flags & RADEON_IS_IGP) { 2892 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE); 2893 rev = RBIOS8(offset); 2894 if (offset) { 2895 rev = RBIOS8(offset); 2896 if (rev > 1) { 2897 blocks = RBIOS8(offset + 3); 2898 index = offset + 4; 2899 while (blocks > 0) { 2900 id = RBIOS16(index); 2901 index += 2; 2902 switch (id >> 13) { 2903 case 0: 2904 reg = (id & 0x1fff) * 4; 2905 val = RBIOS32(index); 2906 index += 4; 2907 WREG32(reg, val); 2908 break; 2909 case 2: 2910 reg = (id & 0x1fff) * 4; 2911 and_mask = RBIOS32(index); 2912 index += 4; 2913 or_mask = RBIOS32(index); 2914 index += 4; 2915 val = RREG32(reg); 2916 val = (val & and_mask) | or_mask; 2917 WREG32(reg, val); 2918 break; 2919 case 3: 2920 val = RBIOS16(index); 2921 index += 2; 2922 udelay(val); 2923 break; 2924 case 4: 2925 val = RBIOS16(index); 2926 index += 2; 2927 mdelay(val); 2928 break; 2929 case 6: 2930 slave_addr = id & 0xff; 2931 slave_addr >>= 1; /* 7 bit addressing */ 2932 index++; 2933 reg = RBIOS8(index); 2934 index++; 2935 val = RBIOS8(index); 2936 index++; 2937 radeon_i2c_put_byte(tmds->i2c_bus, 2938 slave_addr, 2939 reg, val); 2940 break; 2941 default: 2942 DRM_ERROR("Unknown id %d\n", id >> 13); 2943 break; 2944 } 2945 blocks--; 2946 } 2947 return true; 2948 } 2949 } 2950 } else { 2951 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 2952 if (offset) { 2953 index = offset + 10; 2954 id = RBIOS16(index); 2955 while (id != 0xffff) { 2956 index += 2; 2957 switch (id >> 13) { 2958 case 0: 2959 reg = (id & 0x1fff) * 4; 2960 val = RBIOS32(index); 2961 WREG32(reg, val); 2962 break; 2963 case 2: 2964 reg = (id & 0x1fff) * 4; 2965 and_mask = RBIOS32(index); 2966 index += 4; 2967 or_mask = RBIOS32(index); 2968 index += 4; 2969 val = RREG32(reg); 2970 val = (val & and_mask) | or_mask; 2971 WREG32(reg, val); 2972 break; 2973 case 4: 2974 val = RBIOS16(index); 2975 index += 2; 2976 udelay(val); 2977 break; 2978 case 5: 2979 reg = id & 0x1fff; 2980 and_mask = RBIOS32(index); 2981 index += 4; 2982 or_mask = RBIOS32(index); 2983 index += 4; 2984 val = RREG32_PLL(reg); 2985 val = (val & and_mask) | or_mask; 2986 WREG32_PLL(reg, val); 2987 break; 2988 case 6: 2989 reg = id & 0x1fff; 2990 val = RBIOS8(index); 2991 index += 1; 2992 radeon_i2c_put_byte(tmds->i2c_bus, 2993 tmds->slave_addr, 2994 reg, val); 2995 break; 2996 default: 2997 DRM_ERROR("Unknown id %d\n", id >> 13); 2998 break; 2999 } 3000 id = RBIOS16(index); 3001 } 3002 return true; 3003 } 3004 } 3005 return false; 3006 } 3007 3008 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset) 3009 { 3010 struct radeon_device *rdev = dev->dev_private; 3011 3012 if (offset) { 3013 while (RBIOS16(offset)) { 3014 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13); 3015 uint32_t addr = (RBIOS16(offset) & 0x1fff); 3016 uint32_t val, and_mask, or_mask; 3017 uint32_t tmp; 3018 3019 offset += 2; 3020 switch (cmd) { 3021 case 0: 3022 val = RBIOS32(offset); 3023 offset += 4; 3024 WREG32(addr, val); 3025 break; 3026 case 1: 3027 val = RBIOS32(offset); 3028 offset += 4; 3029 WREG32(addr, val); 3030 break; 3031 case 2: 3032 and_mask = RBIOS32(offset); 3033 offset += 4; 3034 or_mask = RBIOS32(offset); 3035 offset += 4; 3036 tmp = RREG32(addr); 3037 tmp &= and_mask; 3038 tmp |= or_mask; 3039 WREG32(addr, tmp); 3040 break; 3041 case 3: 3042 and_mask = RBIOS32(offset); 3043 offset += 4; 3044 or_mask = RBIOS32(offset); 3045 offset += 4; 3046 tmp = RREG32(addr); 3047 tmp &= and_mask; 3048 tmp |= or_mask; 3049 WREG32(addr, tmp); 3050 break; 3051 case 4: 3052 val = RBIOS16(offset); 3053 offset += 2; 3054 udelay(val); 3055 break; 3056 case 5: 3057 val = RBIOS16(offset); 3058 offset += 2; 3059 switch (addr) { 3060 case 8: 3061 while (val--) { 3062 if (! 3063 (RREG32_PLL 3064 (RADEON_CLK_PWRMGT_CNTL) & 3065 RADEON_MC_BUSY)) 3066 break; 3067 } 3068 break; 3069 case 9: 3070 while (val--) { 3071 if ((RREG32(RADEON_MC_STATUS) & 3072 RADEON_MC_IDLE)) 3073 break; 3074 } 3075 break; 3076 default: 3077 break; 3078 } 3079 break; 3080 default: 3081 break; 3082 } 3083 } 3084 } 3085 } 3086 3087 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset) 3088 { 3089 struct radeon_device *rdev = dev->dev_private; 3090 3091 if (offset) { 3092 while (RBIOS8(offset)) { 3093 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6); 3094 uint8_t addr = (RBIOS8(offset) & 0x3f); 3095 uint32_t val, shift, tmp; 3096 uint32_t and_mask, or_mask; 3097 3098 offset++; 3099 switch (cmd) { 3100 case 0: 3101 val = RBIOS32(offset); 3102 offset += 4; 3103 WREG32_PLL(addr, val); 3104 break; 3105 case 1: 3106 shift = RBIOS8(offset) * 8; 3107 offset++; 3108 and_mask = RBIOS8(offset) << shift; 3109 and_mask |= ~(0xff << shift); 3110 offset++; 3111 or_mask = RBIOS8(offset) << shift; 3112 offset++; 3113 tmp = RREG32_PLL(addr); 3114 tmp &= and_mask; 3115 tmp |= or_mask; 3116 WREG32_PLL(addr, tmp); 3117 break; 3118 case 2: 3119 case 3: 3120 tmp = 1000; 3121 switch (addr) { 3122 case 1: 3123 udelay(150); 3124 break; 3125 case 2: 3126 mdelay(1); 3127 break; 3128 case 3: 3129 while (tmp--) { 3130 if (! 3131 (RREG32_PLL 3132 (RADEON_CLK_PWRMGT_CNTL) & 3133 RADEON_MC_BUSY)) 3134 break; 3135 } 3136 break; 3137 case 4: 3138 while (tmp--) { 3139 if (RREG32_PLL 3140 (RADEON_CLK_PWRMGT_CNTL) & 3141 RADEON_DLL_READY) 3142 break; 3143 } 3144 break; 3145 case 5: 3146 tmp = 3147 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); 3148 if (tmp & RADEON_CG_NO1_DEBUG_0) { 3149 #if 0 3150 uint32_t mclk_cntl = 3151 RREG32_PLL 3152 (RADEON_MCLK_CNTL); 3153 mclk_cntl &= 0xffff0000; 3154 /*mclk_cntl |= 0x00001111;*//* ??? */ 3155 WREG32_PLL(RADEON_MCLK_CNTL, 3156 mclk_cntl); 3157 mdelay(10); 3158 #endif 3159 WREG32_PLL 3160 (RADEON_CLK_PWRMGT_CNTL, 3161 tmp & 3162 ~RADEON_CG_NO1_DEBUG_0); 3163 mdelay(10); 3164 } 3165 break; 3166 default: 3167 break; 3168 } 3169 break; 3170 default: 3171 break; 3172 } 3173 } 3174 } 3175 } 3176 3177 static void combios_parse_ram_reset_table(struct drm_device *dev, 3178 uint16_t offset) 3179 { 3180 struct radeon_device *rdev = dev->dev_private; 3181 uint32_t tmp; 3182 3183 if (offset) { 3184 uint8_t val = RBIOS8(offset); 3185 while (val != 0xff) { 3186 offset++; 3187 3188 if (val == 0x0f) { 3189 uint32_t channel_complete_mask; 3190 3191 if (ASIC_IS_R300(rdev)) 3192 channel_complete_mask = 3193 R300_MEM_PWRUP_COMPLETE; 3194 else 3195 channel_complete_mask = 3196 RADEON_MEM_PWRUP_COMPLETE; 3197 tmp = 20000; 3198 while (tmp--) { 3199 if ((RREG32(RADEON_MEM_STR_CNTL) & 3200 channel_complete_mask) == 3201 channel_complete_mask) 3202 break; 3203 } 3204 } else { 3205 uint32_t or_mask = RBIOS16(offset); 3206 offset += 2; 3207 3208 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 3209 tmp &= RADEON_SDRAM_MODE_MASK; 3210 tmp |= or_mask; 3211 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 3212 3213 or_mask = val << 24; 3214 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 3215 tmp &= RADEON_B3MEM_RESET_MASK; 3216 tmp |= or_mask; 3217 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 3218 } 3219 val = RBIOS8(offset); 3220 } 3221 } 3222 } 3223 3224 static uint32_t combios_detect_ram(struct drm_device *dev, int ram, 3225 int mem_addr_mapping) 3226 { 3227 struct radeon_device *rdev = dev->dev_private; 3228 uint32_t mem_cntl; 3229 uint32_t mem_size; 3230 uint32_t addr = 0; 3231 3232 mem_cntl = RREG32(RADEON_MEM_CNTL); 3233 if (mem_cntl & RV100_HALF_MODE) 3234 ram /= 2; 3235 mem_size = ram; 3236 mem_cntl &= ~(0xff << 8); 3237 mem_cntl |= (mem_addr_mapping & 0xff) << 8; 3238 WREG32(RADEON_MEM_CNTL, mem_cntl); 3239 RREG32(RADEON_MEM_CNTL); 3240 3241 /* sdram reset ? */ 3242 3243 /* something like this???? */ 3244 while (ram--) { 3245 addr = ram * 1024 * 1024; 3246 /* write to each page */ 3247 WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef); 3248 /* read back and verify */ 3249 if (RREG32_IDX((addr) | RADEON_MM_APER) != 0xdeadbeef) 3250 return 0; 3251 } 3252 3253 return mem_size; 3254 } 3255 3256 static void combios_write_ram_size(struct drm_device *dev) 3257 { 3258 struct radeon_device *rdev = dev->dev_private; 3259 uint8_t rev; 3260 uint16_t offset; 3261 uint32_t mem_size = 0; 3262 uint32_t mem_cntl = 0; 3263 3264 /* should do something smarter here I guess... */ 3265 if (rdev->flags & RADEON_IS_IGP) 3266 return; 3267 3268 /* first check detected mem table */ 3269 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE); 3270 if (offset) { 3271 rev = RBIOS8(offset); 3272 if (rev < 3) { 3273 mem_cntl = RBIOS32(offset + 1); 3274 mem_size = RBIOS16(offset + 5); 3275 if ((rdev->family < CHIP_R200) && 3276 !ASIC_IS_RN50(rdev)) 3277 WREG32(RADEON_MEM_CNTL, mem_cntl); 3278 } 3279 } 3280 3281 if (!mem_size) { 3282 offset = 3283 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 3284 if (offset) { 3285 rev = RBIOS8(offset - 1); 3286 if (rev < 1) { 3287 if ((rdev->family < CHIP_R200) 3288 && !ASIC_IS_RN50(rdev)) { 3289 int ram = 0; 3290 int mem_addr_mapping = 0; 3291 3292 while (RBIOS8(offset)) { 3293 ram = RBIOS8(offset); 3294 mem_addr_mapping = 3295 RBIOS8(offset + 1); 3296 if (mem_addr_mapping != 0x25) 3297 ram *= 2; 3298 mem_size = 3299 combios_detect_ram(dev, ram, 3300 mem_addr_mapping); 3301 if (mem_size) 3302 break; 3303 offset += 2; 3304 } 3305 } else 3306 mem_size = RBIOS8(offset); 3307 } else { 3308 mem_size = RBIOS8(offset); 3309 mem_size *= 2; /* convert to MB */ 3310 } 3311 } 3312 } 3313 3314 mem_size *= (1024 * 1024); /* convert to bytes */ 3315 WREG32(RADEON_CONFIG_MEMSIZE, mem_size); 3316 } 3317 3318 void radeon_combios_asic_init(struct drm_device *dev) 3319 { 3320 struct radeon_device *rdev = dev->dev_private; 3321 uint16_t table; 3322 3323 /* port hardcoded mac stuff from radeonfb */ 3324 if (rdev->bios == NULL) 3325 return; 3326 3327 /* ASIC INIT 1 */ 3328 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE); 3329 if (table) 3330 combios_parse_mmio_table(dev, table); 3331 3332 /* PLL INIT */ 3333 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE); 3334 if (table) 3335 combios_parse_pll_table(dev, table); 3336 3337 /* ASIC INIT 2 */ 3338 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE); 3339 if (table) 3340 combios_parse_mmio_table(dev, table); 3341 3342 if (!(rdev->flags & RADEON_IS_IGP)) { 3343 /* ASIC INIT 4 */ 3344 table = 3345 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE); 3346 if (table) 3347 combios_parse_mmio_table(dev, table); 3348 3349 /* RAM RESET */ 3350 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE); 3351 if (table) 3352 combios_parse_ram_reset_table(dev, table); 3353 3354 /* ASIC INIT 3 */ 3355 table = 3356 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE); 3357 if (table) 3358 combios_parse_mmio_table(dev, table); 3359 3360 /* write CONFIG_MEMSIZE */ 3361 combios_write_ram_size(dev); 3362 } 3363 3364 /* quirk for rs4xx HP nx6125 laptop to make it resume 3365 * - it hangs on resume inside the dynclk 1 table. 3366 */ 3367 if (rdev->family == CHIP_RS480 && 3368 rdev->pdev->subsystem_vendor == 0x103c && 3369 rdev->pdev->subsystem_device == 0x308b) 3370 return; 3371 3372 /* quirk for rs4xx HP dv5000 laptop to make it resume 3373 * - it hangs on resume inside the dynclk 1 table. 3374 */ 3375 if (rdev->family == CHIP_RS480 && 3376 rdev->pdev->subsystem_vendor == 0x103c && 3377 rdev->pdev->subsystem_device == 0x30a4) 3378 return; 3379 3380 /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume 3381 * - it hangs on resume inside the dynclk 1 table. 3382 */ 3383 if (rdev->family == CHIP_RS480 && 3384 rdev->pdev->subsystem_vendor == 0x103c && 3385 rdev->pdev->subsystem_device == 0x30ae) 3386 return; 3387 3388 /* DYN CLK 1 */ 3389 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); 3390 if (table) 3391 combios_parse_pll_table(dev, table); 3392 3393 } 3394 3395 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev) 3396 { 3397 struct radeon_device *rdev = dev->dev_private; 3398 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch; 3399 3400 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 3401 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3402 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH); 3403 3404 /* let the bios control the backlight */ 3405 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN; 3406 3407 /* tell the bios not to handle mode switching */ 3408 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS | 3409 RADEON_ACC_MODE_CHANGE); 3410 3411 /* tell the bios a driver is loaded */ 3412 bios_7_scratch |= RADEON_DRV_LOADED; 3413 3414 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); 3415 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3416 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch); 3417 } 3418 3419 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock) 3420 { 3421 struct drm_device *dev = encoder->dev; 3422 struct radeon_device *rdev = dev->dev_private; 3423 uint32_t bios_6_scratch; 3424 3425 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3426 3427 if (lock) 3428 bios_6_scratch |= RADEON_DRIVER_CRITICAL; 3429 else 3430 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL; 3431 3432 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3433 } 3434 3435 void 3436 radeon_combios_connected_scratch_regs(struct drm_connector *connector, 3437 struct drm_encoder *encoder, 3438 bool connected) 3439 { 3440 struct drm_device *dev = connector->dev; 3441 struct radeon_device *rdev = dev->dev_private; 3442 struct radeon_connector *radeon_connector = 3443 to_radeon_connector(connector); 3444 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3445 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH); 3446 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 3447 3448 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 3449 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 3450 if (connected) { 3451 DRM_DEBUG_KMS("TV1 connected\n"); 3452 /* fix me */ 3453 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO; 3454 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */ 3455 bios_5_scratch |= RADEON_TV1_ON; 3456 bios_5_scratch |= RADEON_ACC_REQ_TV1; 3457 } else { 3458 DRM_DEBUG_KMS("TV1 disconnected\n"); 3459 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK; 3460 bios_5_scratch &= ~RADEON_TV1_ON; 3461 bios_5_scratch &= ~RADEON_ACC_REQ_TV1; 3462 } 3463 } 3464 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 3465 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 3466 if (connected) { 3467 DRM_DEBUG_KMS("LCD1 connected\n"); 3468 bios_4_scratch |= RADEON_LCD1_ATTACHED; 3469 bios_5_scratch |= RADEON_LCD1_ON; 3470 bios_5_scratch |= RADEON_ACC_REQ_LCD1; 3471 } else { 3472 DRM_DEBUG_KMS("LCD1 disconnected\n"); 3473 bios_4_scratch &= ~RADEON_LCD1_ATTACHED; 3474 bios_5_scratch &= ~RADEON_LCD1_ON; 3475 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1; 3476 } 3477 } 3478 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 3479 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 3480 if (connected) { 3481 DRM_DEBUG_KMS("CRT1 connected\n"); 3482 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR; 3483 bios_5_scratch |= RADEON_CRT1_ON; 3484 bios_5_scratch |= RADEON_ACC_REQ_CRT1; 3485 } else { 3486 DRM_DEBUG_KMS("CRT1 disconnected\n"); 3487 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK; 3488 bios_5_scratch &= ~RADEON_CRT1_ON; 3489 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1; 3490 } 3491 } 3492 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 3493 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 3494 if (connected) { 3495 DRM_DEBUG_KMS("CRT2 connected\n"); 3496 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR; 3497 bios_5_scratch |= RADEON_CRT2_ON; 3498 bios_5_scratch |= RADEON_ACC_REQ_CRT2; 3499 } else { 3500 DRM_DEBUG_KMS("CRT2 disconnected\n"); 3501 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK; 3502 bios_5_scratch &= ~RADEON_CRT2_ON; 3503 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2; 3504 } 3505 } 3506 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 3507 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 3508 if (connected) { 3509 DRM_DEBUG_KMS("DFP1 connected\n"); 3510 bios_4_scratch |= RADEON_DFP1_ATTACHED; 3511 bios_5_scratch |= RADEON_DFP1_ON; 3512 bios_5_scratch |= RADEON_ACC_REQ_DFP1; 3513 } else { 3514 DRM_DEBUG_KMS("DFP1 disconnected\n"); 3515 bios_4_scratch &= ~RADEON_DFP1_ATTACHED; 3516 bios_5_scratch &= ~RADEON_DFP1_ON; 3517 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1; 3518 } 3519 } 3520 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 3521 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 3522 if (connected) { 3523 DRM_DEBUG_KMS("DFP2 connected\n"); 3524 bios_4_scratch |= RADEON_DFP2_ATTACHED; 3525 bios_5_scratch |= RADEON_DFP2_ON; 3526 bios_5_scratch |= RADEON_ACC_REQ_DFP2; 3527 } else { 3528 DRM_DEBUG_KMS("DFP2 disconnected\n"); 3529 bios_4_scratch &= ~RADEON_DFP2_ATTACHED; 3530 bios_5_scratch &= ~RADEON_DFP2_ON; 3531 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2; 3532 } 3533 } 3534 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch); 3535 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 3536 } 3537 3538 void 3539 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) 3540 { 3541 struct drm_device *dev = encoder->dev; 3542 struct radeon_device *rdev = dev->dev_private; 3543 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3544 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 3545 3546 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 3547 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK; 3548 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT); 3549 } 3550 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 3551 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK; 3552 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT); 3553 } 3554 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 3555 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK; 3556 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT); 3557 } 3558 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 3559 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK; 3560 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT); 3561 } 3562 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 3563 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK; 3564 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT); 3565 } 3566 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 3567 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK; 3568 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT); 3569 } 3570 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 3571 } 3572 3573 void 3574 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) 3575 { 3576 struct drm_device *dev = encoder->dev; 3577 struct radeon_device *rdev = dev->dev_private; 3578 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3579 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3580 3581 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 3582 if (on) 3583 bios_6_scratch |= RADEON_TV_DPMS_ON; 3584 else 3585 bios_6_scratch &= ~RADEON_TV_DPMS_ON; 3586 } 3587 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3588 if (on) 3589 bios_6_scratch |= RADEON_CRT_DPMS_ON; 3590 else 3591 bios_6_scratch &= ~RADEON_CRT_DPMS_ON; 3592 } 3593 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3594 if (on) 3595 bios_6_scratch |= RADEON_LCD_DPMS_ON; 3596 else 3597 bios_6_scratch &= ~RADEON_LCD_DPMS_ON; 3598 } 3599 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 3600 if (on) 3601 bios_6_scratch |= RADEON_DFP_DPMS_ON; 3602 else 3603 bios_6_scratch &= ~RADEON_DFP_DPMS_ON; 3604 } 3605 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3606 } 3607