1 /* 2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario 3 * Copyright 2007-8 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 */ 27 #include <drm/drmP.h> 28 #include <drm/radeon_drm.h> 29 #include "radeon.h" 30 #include "atom.h" 31 32 #ifdef CONFIG_PPC_PMAC 33 /* not sure which of these are needed */ 34 #include <asm/machdep.h> 35 #include <asm/pmac_feature.h> 36 #include <asm/prom.h> 37 #include <asm/pci-bridge.h> 38 #endif /* CONFIG_PPC_PMAC */ 39 40 /* old legacy ATI BIOS routines */ 41 42 /* COMBIOS table offsets */ 43 enum radeon_combios_table_offset { 44 /* absolute offset tables */ 45 COMBIOS_ASIC_INIT_1_TABLE, 46 COMBIOS_BIOS_SUPPORT_TABLE, 47 COMBIOS_DAC_PROGRAMMING_TABLE, 48 COMBIOS_MAX_COLOR_DEPTH_TABLE, 49 COMBIOS_CRTC_INFO_TABLE, 50 COMBIOS_PLL_INFO_TABLE, 51 COMBIOS_TV_INFO_TABLE, 52 COMBIOS_DFP_INFO_TABLE, 53 COMBIOS_HW_CONFIG_INFO_TABLE, 54 COMBIOS_MULTIMEDIA_INFO_TABLE, 55 COMBIOS_TV_STD_PATCH_TABLE, 56 COMBIOS_LCD_INFO_TABLE, 57 COMBIOS_MOBILE_INFO_TABLE, 58 COMBIOS_PLL_INIT_TABLE, 59 COMBIOS_MEM_CONFIG_TABLE, 60 COMBIOS_SAVE_MASK_TABLE, 61 COMBIOS_HARDCODED_EDID_TABLE, 62 COMBIOS_ASIC_INIT_2_TABLE, 63 COMBIOS_CONNECTOR_INFO_TABLE, 64 COMBIOS_DYN_CLK_1_TABLE, 65 COMBIOS_RESERVED_MEM_TABLE, 66 COMBIOS_EXT_TMDS_INFO_TABLE, 67 COMBIOS_MEM_CLK_INFO_TABLE, 68 COMBIOS_EXT_DAC_INFO_TABLE, 69 COMBIOS_MISC_INFO_TABLE, 70 COMBIOS_CRT_INFO_TABLE, 71 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE, 72 COMBIOS_COMPONENT_VIDEO_INFO_TABLE, 73 COMBIOS_FAN_SPEED_INFO_TABLE, 74 COMBIOS_OVERDRIVE_INFO_TABLE, 75 COMBIOS_OEM_INFO_TABLE, 76 COMBIOS_DYN_CLK_2_TABLE, 77 COMBIOS_POWER_CONNECTOR_INFO_TABLE, 78 COMBIOS_I2C_INFO_TABLE, 79 /* relative offset tables */ 80 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */ 81 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */ 82 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */ 83 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */ 84 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */ 85 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */ 86 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */ 87 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */ 88 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */ 89 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */ 90 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */ 91 }; 92 93 enum radeon_combios_ddc { 94 DDC_NONE_DETECTED, 95 DDC_MONID, 96 DDC_DVI, 97 DDC_VGA, 98 DDC_CRT2, 99 DDC_LCD, 100 DDC_GPIO, 101 }; 102 103 enum radeon_combios_connector { 104 CONNECTOR_NONE_LEGACY, 105 CONNECTOR_PROPRIETARY_LEGACY, 106 CONNECTOR_CRT_LEGACY, 107 CONNECTOR_DVI_I_LEGACY, 108 CONNECTOR_DVI_D_LEGACY, 109 CONNECTOR_CTV_LEGACY, 110 CONNECTOR_STV_LEGACY, 111 CONNECTOR_UNSUPPORTED_LEGACY 112 }; 113 114 static const int legacy_connector_convert[] = { 115 DRM_MODE_CONNECTOR_Unknown, 116 DRM_MODE_CONNECTOR_DVID, 117 DRM_MODE_CONNECTOR_VGA, 118 DRM_MODE_CONNECTOR_DVII, 119 DRM_MODE_CONNECTOR_DVID, 120 DRM_MODE_CONNECTOR_Composite, 121 DRM_MODE_CONNECTOR_SVIDEO, 122 DRM_MODE_CONNECTOR_Unknown, 123 }; 124 125 static uint16_t combios_get_table_offset(struct drm_device *dev, 126 enum radeon_combios_table_offset table) 127 { 128 struct radeon_device *rdev = dev->dev_private; 129 int rev, size; 130 uint16_t offset = 0, check_offset; 131 132 if (!rdev->bios) 133 return 0; 134 135 switch (table) { 136 /* absolute offset tables */ 137 case COMBIOS_ASIC_INIT_1_TABLE: 138 check_offset = 0xc; 139 break; 140 case COMBIOS_BIOS_SUPPORT_TABLE: 141 check_offset = 0x14; 142 break; 143 case COMBIOS_DAC_PROGRAMMING_TABLE: 144 check_offset = 0x2a; 145 break; 146 case COMBIOS_MAX_COLOR_DEPTH_TABLE: 147 check_offset = 0x2c; 148 break; 149 case COMBIOS_CRTC_INFO_TABLE: 150 check_offset = 0x2e; 151 break; 152 case COMBIOS_PLL_INFO_TABLE: 153 check_offset = 0x30; 154 break; 155 case COMBIOS_TV_INFO_TABLE: 156 check_offset = 0x32; 157 break; 158 case COMBIOS_DFP_INFO_TABLE: 159 check_offset = 0x34; 160 break; 161 case COMBIOS_HW_CONFIG_INFO_TABLE: 162 check_offset = 0x36; 163 break; 164 case COMBIOS_MULTIMEDIA_INFO_TABLE: 165 check_offset = 0x38; 166 break; 167 case COMBIOS_TV_STD_PATCH_TABLE: 168 check_offset = 0x3e; 169 break; 170 case COMBIOS_LCD_INFO_TABLE: 171 check_offset = 0x40; 172 break; 173 case COMBIOS_MOBILE_INFO_TABLE: 174 check_offset = 0x42; 175 break; 176 case COMBIOS_PLL_INIT_TABLE: 177 check_offset = 0x46; 178 break; 179 case COMBIOS_MEM_CONFIG_TABLE: 180 check_offset = 0x48; 181 break; 182 case COMBIOS_SAVE_MASK_TABLE: 183 check_offset = 0x4a; 184 break; 185 case COMBIOS_HARDCODED_EDID_TABLE: 186 check_offset = 0x4c; 187 break; 188 case COMBIOS_ASIC_INIT_2_TABLE: 189 check_offset = 0x4e; 190 break; 191 case COMBIOS_CONNECTOR_INFO_TABLE: 192 check_offset = 0x50; 193 break; 194 case COMBIOS_DYN_CLK_1_TABLE: 195 check_offset = 0x52; 196 break; 197 case COMBIOS_RESERVED_MEM_TABLE: 198 check_offset = 0x54; 199 break; 200 case COMBIOS_EXT_TMDS_INFO_TABLE: 201 check_offset = 0x58; 202 break; 203 case COMBIOS_MEM_CLK_INFO_TABLE: 204 check_offset = 0x5a; 205 break; 206 case COMBIOS_EXT_DAC_INFO_TABLE: 207 check_offset = 0x5c; 208 break; 209 case COMBIOS_MISC_INFO_TABLE: 210 check_offset = 0x5e; 211 break; 212 case COMBIOS_CRT_INFO_TABLE: 213 check_offset = 0x60; 214 break; 215 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE: 216 check_offset = 0x62; 217 break; 218 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE: 219 check_offset = 0x64; 220 break; 221 case COMBIOS_FAN_SPEED_INFO_TABLE: 222 check_offset = 0x66; 223 break; 224 case COMBIOS_OVERDRIVE_INFO_TABLE: 225 check_offset = 0x68; 226 break; 227 case COMBIOS_OEM_INFO_TABLE: 228 check_offset = 0x6a; 229 break; 230 case COMBIOS_DYN_CLK_2_TABLE: 231 check_offset = 0x6c; 232 break; 233 case COMBIOS_POWER_CONNECTOR_INFO_TABLE: 234 check_offset = 0x6e; 235 break; 236 case COMBIOS_I2C_INFO_TABLE: 237 check_offset = 0x70; 238 break; 239 /* relative offset tables */ 240 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */ 241 check_offset = 242 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 243 if (check_offset) { 244 rev = RBIOS8(check_offset); 245 if (rev > 0) { 246 check_offset = RBIOS16(check_offset + 0x3); 247 if (check_offset) 248 offset = check_offset; 249 } 250 } 251 break; 252 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */ 253 check_offset = 254 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 255 if (check_offset) { 256 rev = RBIOS8(check_offset); 257 if (rev > 0) { 258 check_offset = RBIOS16(check_offset + 0x5); 259 if (check_offset) 260 offset = check_offset; 261 } 262 } 263 break; 264 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */ 265 check_offset = 266 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 267 if (check_offset) { 268 rev = RBIOS8(check_offset); 269 if (rev > 0) { 270 check_offset = RBIOS16(check_offset + 0x7); 271 if (check_offset) 272 offset = check_offset; 273 } 274 } 275 break; 276 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */ 277 check_offset = 278 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 279 if (check_offset) { 280 rev = RBIOS8(check_offset); 281 if (rev == 2) { 282 check_offset = RBIOS16(check_offset + 0x9); 283 if (check_offset) 284 offset = check_offset; 285 } 286 } 287 break; 288 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */ 289 check_offset = 290 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 291 if (check_offset) { 292 while (RBIOS8(check_offset++)); 293 check_offset += 2; 294 if (check_offset) 295 offset = check_offset; 296 } 297 break; 298 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */ 299 check_offset = 300 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 301 if (check_offset) { 302 check_offset = RBIOS16(check_offset + 0x11); 303 if (check_offset) 304 offset = check_offset; 305 } 306 break; 307 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */ 308 check_offset = 309 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 310 if (check_offset) { 311 check_offset = RBIOS16(check_offset + 0x13); 312 if (check_offset) 313 offset = check_offset; 314 } 315 break; 316 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */ 317 check_offset = 318 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 319 if (check_offset) { 320 check_offset = RBIOS16(check_offset + 0x15); 321 if (check_offset) 322 offset = check_offset; 323 } 324 break; 325 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */ 326 check_offset = 327 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 328 if (check_offset) { 329 check_offset = RBIOS16(check_offset + 0x17); 330 if (check_offset) 331 offset = check_offset; 332 } 333 break; 334 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */ 335 check_offset = 336 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 337 if (check_offset) { 338 check_offset = RBIOS16(check_offset + 0x2); 339 if (check_offset) 340 offset = check_offset; 341 } 342 break; 343 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */ 344 check_offset = 345 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 346 if (check_offset) { 347 check_offset = RBIOS16(check_offset + 0x4); 348 if (check_offset) 349 offset = check_offset; 350 } 351 break; 352 default: 353 check_offset = 0; 354 break; 355 } 356 357 size = RBIOS8(rdev->bios_header_start + 0x6); 358 /* check absolute offset tables */ 359 if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size) 360 offset = RBIOS16(rdev->bios_header_start + check_offset); 361 362 return offset; 363 } 364 365 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev) 366 { 367 int edid_info, size; 368 struct edid *edid; 369 unsigned char *raw; 370 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE); 371 if (!edid_info) 372 return false; 373 374 raw = rdev->bios + edid_info; 375 size = EDID_LENGTH * (raw[0x7e] + 1); 376 edid = kmalloc(size, M_DRM, M_WAITOK); 377 if (edid == NULL) 378 return false; 379 380 memcpy((unsigned char *)edid, raw, size); 381 382 if (!drm_edid_is_valid(edid)) { 383 kfree(edid); 384 return false; 385 } 386 387 rdev->mode_info.bios_hardcoded_edid = edid; 388 rdev->mode_info.bios_hardcoded_edid_size = size; 389 return true; 390 } 391 392 /* this is used for atom LCDs as well */ 393 struct edid * 394 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev) 395 { 396 struct edid *edid; 397 398 if (rdev->mode_info.bios_hardcoded_edid) { 399 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, 400 M_DRM, M_WAITOK); 401 if (edid) { 402 memcpy((unsigned char *)edid, 403 (unsigned char *)rdev->mode_info.bios_hardcoded_edid, 404 rdev->mode_info.bios_hardcoded_edid_size); 405 return edid; 406 } 407 } 408 return NULL; 409 } 410 411 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev, 412 enum radeon_combios_ddc ddc, 413 u32 clk_mask, 414 u32 data_mask) 415 { 416 struct radeon_i2c_bus_rec i2c; 417 int ddc_line = 0; 418 419 /* ddc id = mask reg 420 * DDC_NONE_DETECTED = none 421 * DDC_DVI = RADEON_GPIO_DVI_DDC 422 * DDC_VGA = RADEON_GPIO_VGA_DDC 423 * DDC_LCD = RADEON_GPIOPAD_MASK 424 * DDC_GPIO = RADEON_MDGPIO_MASK 425 * r1xx 426 * DDC_MONID = RADEON_GPIO_MONID 427 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC 428 * r200 429 * DDC_MONID = RADEON_GPIO_MONID 430 * DDC_CRT2 = RADEON_GPIO_DVI_DDC 431 * r300/r350 432 * DDC_MONID = RADEON_GPIO_DVI_DDC 433 * DDC_CRT2 = RADEON_GPIO_DVI_DDC 434 * rv2xx/rv3xx 435 * DDC_MONID = RADEON_GPIO_MONID 436 * DDC_CRT2 = RADEON_GPIO_MONID 437 * rs3xx/rs4xx 438 * DDC_MONID = RADEON_GPIOPAD_MASK 439 * DDC_CRT2 = RADEON_GPIO_MONID 440 */ 441 switch (ddc) { 442 case DDC_NONE_DETECTED: 443 default: 444 ddc_line = 0; 445 break; 446 case DDC_DVI: 447 ddc_line = RADEON_GPIO_DVI_DDC; 448 break; 449 case DDC_VGA: 450 ddc_line = RADEON_GPIO_VGA_DDC; 451 break; 452 case DDC_LCD: 453 ddc_line = RADEON_GPIOPAD_MASK; 454 break; 455 case DDC_GPIO: 456 ddc_line = RADEON_MDGPIO_MASK; 457 break; 458 case DDC_MONID: 459 if (rdev->family == CHIP_RS300 || 460 rdev->family == CHIP_RS400 || 461 rdev->family == CHIP_RS480) 462 ddc_line = RADEON_GPIOPAD_MASK; 463 else if (rdev->family == CHIP_R300 || 464 rdev->family == CHIP_R350) { 465 ddc_line = RADEON_GPIO_DVI_DDC; 466 ddc = DDC_DVI; 467 } else 468 ddc_line = RADEON_GPIO_MONID; 469 break; 470 case DDC_CRT2: 471 if (rdev->family == CHIP_R200 || 472 rdev->family == CHIP_R300 || 473 rdev->family == CHIP_R350) { 474 ddc_line = RADEON_GPIO_DVI_DDC; 475 ddc = DDC_DVI; 476 } else if (rdev->family == CHIP_RS300 || 477 rdev->family == CHIP_RS400 || 478 rdev->family == CHIP_RS480) 479 ddc_line = RADEON_GPIO_MONID; 480 else if (rdev->family >= CHIP_RV350) { 481 ddc_line = RADEON_GPIO_MONID; 482 ddc = DDC_MONID; 483 } else 484 ddc_line = RADEON_GPIO_CRT2_DDC; 485 break; 486 } 487 488 if (ddc_line == RADEON_GPIOPAD_MASK) { 489 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; 490 i2c.mask_data_reg = RADEON_GPIOPAD_MASK; 491 i2c.a_clk_reg = RADEON_GPIOPAD_A; 492 i2c.a_data_reg = RADEON_GPIOPAD_A; 493 i2c.en_clk_reg = RADEON_GPIOPAD_EN; 494 i2c.en_data_reg = RADEON_GPIOPAD_EN; 495 i2c.y_clk_reg = RADEON_GPIOPAD_Y; 496 i2c.y_data_reg = RADEON_GPIOPAD_Y; 497 } else if (ddc_line == RADEON_MDGPIO_MASK) { 498 i2c.mask_clk_reg = RADEON_MDGPIO_MASK; 499 i2c.mask_data_reg = RADEON_MDGPIO_MASK; 500 i2c.a_clk_reg = RADEON_MDGPIO_A; 501 i2c.a_data_reg = RADEON_MDGPIO_A; 502 i2c.en_clk_reg = RADEON_MDGPIO_EN; 503 i2c.en_data_reg = RADEON_MDGPIO_EN; 504 i2c.y_clk_reg = RADEON_MDGPIO_Y; 505 i2c.y_data_reg = RADEON_MDGPIO_Y; 506 } else { 507 i2c.mask_clk_reg = ddc_line; 508 i2c.mask_data_reg = ddc_line; 509 i2c.a_clk_reg = ddc_line; 510 i2c.a_data_reg = ddc_line; 511 i2c.en_clk_reg = ddc_line; 512 i2c.en_data_reg = ddc_line; 513 i2c.y_clk_reg = ddc_line; 514 i2c.y_data_reg = ddc_line; 515 } 516 517 if (clk_mask && data_mask) { 518 /* system specific masks */ 519 i2c.mask_clk_mask = clk_mask; 520 i2c.mask_data_mask = data_mask; 521 i2c.a_clk_mask = clk_mask; 522 i2c.a_data_mask = data_mask; 523 i2c.en_clk_mask = clk_mask; 524 i2c.en_data_mask = data_mask; 525 i2c.y_clk_mask = clk_mask; 526 i2c.y_data_mask = data_mask; 527 } else if ((ddc_line == RADEON_GPIOPAD_MASK) || 528 (ddc_line == RADEON_MDGPIO_MASK)) { 529 /* default gpiopad masks */ 530 i2c.mask_clk_mask = (0x20 << 8); 531 i2c.mask_data_mask = 0x80; 532 i2c.a_clk_mask = (0x20 << 8); 533 i2c.a_data_mask = 0x80; 534 i2c.en_clk_mask = (0x20 << 8); 535 i2c.en_data_mask = 0x80; 536 i2c.y_clk_mask = (0x20 << 8); 537 i2c.y_data_mask = 0x80; 538 } else { 539 /* default masks for ddc pads */ 540 i2c.mask_clk_mask = RADEON_GPIO_MASK_1; 541 i2c.mask_data_mask = RADEON_GPIO_MASK_0; 542 i2c.a_clk_mask = RADEON_GPIO_A_1; 543 i2c.a_data_mask = RADEON_GPIO_A_0; 544 i2c.en_clk_mask = RADEON_GPIO_EN_1; 545 i2c.en_data_mask = RADEON_GPIO_EN_0; 546 i2c.y_clk_mask = RADEON_GPIO_Y_1; 547 i2c.y_data_mask = RADEON_GPIO_Y_0; 548 } 549 550 switch (rdev->family) { 551 case CHIP_R100: 552 case CHIP_RV100: 553 case CHIP_RS100: 554 case CHIP_RV200: 555 case CHIP_RS200: 556 case CHIP_RS300: 557 switch (ddc_line) { 558 case RADEON_GPIO_DVI_DDC: 559 i2c.hw_capable = true; 560 break; 561 default: 562 i2c.hw_capable = false; 563 break; 564 } 565 break; 566 case CHIP_R200: 567 switch (ddc_line) { 568 case RADEON_GPIO_DVI_DDC: 569 case RADEON_GPIO_MONID: 570 i2c.hw_capable = true; 571 break; 572 default: 573 i2c.hw_capable = false; 574 break; 575 } 576 break; 577 case CHIP_RV250: 578 case CHIP_RV280: 579 switch (ddc_line) { 580 case RADEON_GPIO_VGA_DDC: 581 case RADEON_GPIO_DVI_DDC: 582 case RADEON_GPIO_CRT2_DDC: 583 i2c.hw_capable = true; 584 break; 585 default: 586 i2c.hw_capable = false; 587 break; 588 } 589 break; 590 case CHIP_R300: 591 case CHIP_R350: 592 switch (ddc_line) { 593 case RADEON_GPIO_VGA_DDC: 594 case RADEON_GPIO_DVI_DDC: 595 i2c.hw_capable = true; 596 break; 597 default: 598 i2c.hw_capable = false; 599 break; 600 } 601 break; 602 case CHIP_RV350: 603 case CHIP_RV380: 604 case CHIP_RS400: 605 case CHIP_RS480: 606 switch (ddc_line) { 607 case RADEON_GPIO_VGA_DDC: 608 case RADEON_GPIO_DVI_DDC: 609 i2c.hw_capable = true; 610 break; 611 case RADEON_GPIO_MONID: 612 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work 613 * reliably on some pre-r4xx hardware; not sure why. 614 */ 615 i2c.hw_capable = false; 616 break; 617 default: 618 i2c.hw_capable = false; 619 break; 620 } 621 break; 622 default: 623 i2c.hw_capable = false; 624 break; 625 } 626 i2c.mm_i2c = false; 627 628 i2c.i2c_id = ddc; 629 i2c.hpd = RADEON_HPD_NONE; 630 631 if (ddc_line) 632 i2c.valid = true; 633 else 634 i2c.valid = false; 635 636 return i2c; 637 } 638 639 static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev) 640 { 641 struct drm_device *dev = rdev->ddev; 642 struct radeon_i2c_bus_rec i2c; 643 u16 offset; 644 u8 id, blocks, clk, data; 645 int i; 646 647 i2c.valid = false; 648 649 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE); 650 if (offset) { 651 blocks = RBIOS8(offset + 2); 652 for (i = 0; i < blocks; i++) { 653 id = RBIOS8(offset + 3 + (i * 5) + 0); 654 if (id == 136) { 655 clk = RBIOS8(offset + 3 + (i * 5) + 3); 656 data = RBIOS8(offset + 3 + (i * 5) + 4); 657 /* gpiopad */ 658 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 659 (1 << clk), (1 << data)); 660 break; 661 } 662 } 663 } 664 return i2c; 665 } 666 667 void radeon_combios_i2c_init(struct radeon_device *rdev) 668 { 669 struct drm_device *dev = rdev->ddev; 670 struct radeon_i2c_bus_rec i2c; 671 672 /* actual hw pads 673 * r1xx/rs2xx/rs3xx 674 * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm 675 * r200 676 * 0x60, 0x64, 0x68, mm 677 * r300/r350 678 * 0x60, 0x64, mm 679 * rv2xx/rv3xx/rs4xx 680 * 0x60, 0x64, 0x68, gpiopads, mm 681 */ 682 683 /* 0x60 */ 684 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 685 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC"); 686 /* 0x64 */ 687 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 688 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC"); 689 690 /* mm i2c */ 691 i2c.valid = true; 692 i2c.hw_capable = true; 693 i2c.mm_i2c = true; 694 i2c.i2c_id = 0xa0; 695 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C"); 696 697 if (rdev->family == CHIP_R300 || 698 rdev->family == CHIP_R350) { 699 /* only 2 sw i2c pads */ 700 } else if (rdev->family == CHIP_RS300 || 701 rdev->family == CHIP_RS400 || 702 rdev->family == CHIP_RS480) { 703 /* 0x68 */ 704 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 705 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 706 707 /* gpiopad */ 708 i2c = radeon_combios_get_i2c_info_from_table(rdev); 709 if (i2c.valid) 710 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK"); 711 } else if ((rdev->family == CHIP_R200) || 712 (rdev->family >= CHIP_R300)) { 713 /* 0x68 */ 714 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 715 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 716 } else { 717 /* 0x68 */ 718 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 719 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 720 /* 0x6c */ 721 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 722 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC"); 723 } 724 } 725 726 bool radeon_combios_get_clock_info(struct drm_device *dev) 727 { 728 struct radeon_device *rdev = dev->dev_private; 729 uint16_t pll_info; 730 struct radeon_pll *p1pll = &rdev->clock.p1pll; 731 struct radeon_pll *p2pll = &rdev->clock.p2pll; 732 struct radeon_pll *spll = &rdev->clock.spll; 733 struct radeon_pll *mpll = &rdev->clock.mpll; 734 int8_t rev; 735 uint16_t sclk, mclk; 736 737 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE); 738 if (pll_info) { 739 rev = RBIOS8(pll_info); 740 741 /* pixel clocks */ 742 p1pll->reference_freq = RBIOS16(pll_info + 0xe); 743 p1pll->reference_div = RBIOS16(pll_info + 0x10); 744 p1pll->pll_out_min = RBIOS32(pll_info + 0x12); 745 p1pll->pll_out_max = RBIOS32(pll_info + 0x16); 746 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 747 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 748 749 if (rev > 9) { 750 p1pll->pll_in_min = RBIOS32(pll_info + 0x36); 751 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a); 752 } else { 753 p1pll->pll_in_min = 40; 754 p1pll->pll_in_max = 500; 755 } 756 *p2pll = *p1pll; 757 758 /* system clock */ 759 spll->reference_freq = RBIOS16(pll_info + 0x1a); 760 spll->reference_div = RBIOS16(pll_info + 0x1c); 761 spll->pll_out_min = RBIOS32(pll_info + 0x1e); 762 spll->pll_out_max = RBIOS32(pll_info + 0x22); 763 764 if (rev > 10) { 765 spll->pll_in_min = RBIOS32(pll_info + 0x48); 766 spll->pll_in_max = RBIOS32(pll_info + 0x4c); 767 } else { 768 /* ??? */ 769 spll->pll_in_min = 40; 770 spll->pll_in_max = 500; 771 } 772 773 /* memory clock */ 774 mpll->reference_freq = RBIOS16(pll_info + 0x26); 775 mpll->reference_div = RBIOS16(pll_info + 0x28); 776 mpll->pll_out_min = RBIOS32(pll_info + 0x2a); 777 mpll->pll_out_max = RBIOS32(pll_info + 0x2e); 778 779 if (rev > 10) { 780 mpll->pll_in_min = RBIOS32(pll_info + 0x5a); 781 mpll->pll_in_max = RBIOS32(pll_info + 0x5e); 782 } else { 783 /* ??? */ 784 mpll->pll_in_min = 40; 785 mpll->pll_in_max = 500; 786 } 787 788 /* default sclk/mclk */ 789 sclk = RBIOS16(pll_info + 0xa); 790 mclk = RBIOS16(pll_info + 0x8); 791 if (sclk == 0) 792 sclk = 200 * 100; 793 if (mclk == 0) 794 mclk = 200 * 100; 795 796 rdev->clock.default_sclk = sclk; 797 rdev->clock.default_mclk = mclk; 798 799 if (RBIOS32(pll_info + 0x16)) 800 rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16); 801 else 802 rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */ 803 804 return true; 805 } 806 return false; 807 } 808 809 bool radeon_combios_sideport_present(struct radeon_device *rdev) 810 { 811 struct drm_device *dev = rdev->ddev; 812 u16 igp_info; 813 814 /* sideport is AMD only */ 815 if (rdev->family == CHIP_RS400) 816 return false; 817 818 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE); 819 820 if (igp_info) { 821 if (RBIOS16(igp_info + 0x4)) 822 return true; 823 } 824 return false; 825 } 826 827 static const uint32_t default_primarydac_adj[CHIP_LAST] = { 828 0x00000808, /* r100 */ 829 0x00000808, /* rv100 */ 830 0x00000808, /* rs100 */ 831 0x00000808, /* rv200 */ 832 0x00000808, /* rs200 */ 833 0x00000808, /* r200 */ 834 0x00000808, /* rv250 */ 835 0x00000000, /* rs300 */ 836 0x00000808, /* rv280 */ 837 0x00000808, /* r300 */ 838 0x00000808, /* r350 */ 839 0x00000808, /* rv350 */ 840 0x00000808, /* rv380 */ 841 0x00000808, /* r420 */ 842 0x00000808, /* r423 */ 843 0x00000808, /* rv410 */ 844 0x00000000, /* rs400 */ 845 0x00000000, /* rs480 */ 846 }; 847 848 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev, 849 struct radeon_encoder_primary_dac *p_dac) 850 { 851 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family]; 852 return; 853 } 854 855 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct 856 radeon_encoder 857 *encoder) 858 { 859 struct drm_device *dev = encoder->base.dev; 860 struct radeon_device *rdev = dev->dev_private; 861 uint16_t dac_info; 862 uint8_t rev, bg, dac; 863 struct radeon_encoder_primary_dac *p_dac = NULL; 864 int found = 0; 865 866 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), 867 GFP_KERNEL); 868 869 if (!p_dac) 870 return NULL; 871 872 /* check CRT table */ 873 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 874 if (dac_info) { 875 rev = RBIOS8(dac_info) & 0x3; 876 if (rev < 2) { 877 bg = RBIOS8(dac_info + 0x2) & 0xf; 878 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf; 879 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 880 } else { 881 bg = RBIOS8(dac_info + 0x2) & 0xf; 882 dac = RBIOS8(dac_info + 0x3) & 0xf; 883 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 884 } 885 /* if the values are zeros, use the table */ 886 if ((dac == 0) || (bg == 0)) 887 found = 0; 888 else 889 found = 1; 890 } 891 892 /* quirks */ 893 /* Radeon 7000 (RV100) */ 894 if (((dev->pdev->device == 0x5159) && 895 (dev->pdev->subsystem_vendor == 0x174B) && 896 (dev->pdev->subsystem_device == 0x7c28)) || 897 /* Radeon 9100 (R200) */ 898 ((dev->pdev->device == 0x514D) && 899 (dev->pdev->subsystem_vendor == 0x174B) && 900 (dev->pdev->subsystem_device == 0x7149))) { 901 /* vbios value is bad, use the default */ 902 found = 0; 903 } 904 905 if (!found) /* fallback to defaults */ 906 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac); 907 908 return p_dac; 909 } 910 911 enum radeon_tv_std 912 radeon_combios_get_tv_info(struct radeon_device *rdev) 913 { 914 struct drm_device *dev = rdev->ddev; 915 uint16_t tv_info; 916 enum radeon_tv_std tv_std = TV_STD_NTSC; 917 918 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 919 if (tv_info) { 920 if (RBIOS8(tv_info + 6) == 'T') { 921 switch (RBIOS8(tv_info + 7) & 0xf) { 922 case 1: 923 tv_std = TV_STD_NTSC; 924 DRM_DEBUG_KMS("Default TV standard: NTSC\n"); 925 break; 926 case 2: 927 tv_std = TV_STD_PAL; 928 DRM_DEBUG_KMS("Default TV standard: PAL\n"); 929 break; 930 case 3: 931 tv_std = TV_STD_PAL_M; 932 DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); 933 break; 934 case 4: 935 tv_std = TV_STD_PAL_60; 936 DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); 937 break; 938 case 5: 939 tv_std = TV_STD_NTSC_J; 940 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); 941 break; 942 case 6: 943 tv_std = TV_STD_SCART_PAL; 944 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n"); 945 break; 946 default: 947 tv_std = TV_STD_NTSC; 948 DRM_DEBUG_KMS 949 ("Unknown TV standard; defaulting to NTSC\n"); 950 break; 951 } 952 953 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) { 954 case 0: 955 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n"); 956 break; 957 case 1: 958 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n"); 959 break; 960 case 2: 961 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n"); 962 break; 963 case 3: 964 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n"); 965 break; 966 default: 967 break; 968 } 969 } 970 } 971 return tv_std; 972 } 973 974 static const uint32_t default_tvdac_adj[CHIP_LAST] = { 975 0x00000000, /* r100 */ 976 0x00280000, /* rv100 */ 977 0x00000000, /* rs100 */ 978 0x00880000, /* rv200 */ 979 0x00000000, /* rs200 */ 980 0x00000000, /* r200 */ 981 0x00770000, /* rv250 */ 982 0x00290000, /* rs300 */ 983 0x00560000, /* rv280 */ 984 0x00780000, /* r300 */ 985 0x00770000, /* r350 */ 986 0x00780000, /* rv350 */ 987 0x00780000, /* rv380 */ 988 0x01080000, /* r420 */ 989 0x01080000, /* r423 */ 990 0x01080000, /* rv410 */ 991 0x00780000, /* rs400 */ 992 0x00780000, /* rs480 */ 993 }; 994 995 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev, 996 struct radeon_encoder_tv_dac *tv_dac) 997 { 998 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family]; 999 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250)) 1000 tv_dac->ps2_tvdac_adj = 0x00880000; 1001 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 1002 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 1003 return; 1004 } 1005 1006 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct 1007 radeon_encoder 1008 *encoder) 1009 { 1010 struct drm_device *dev = encoder->base.dev; 1011 struct radeon_device *rdev = dev->dev_private; 1012 uint16_t dac_info; 1013 uint8_t rev, bg, dac; 1014 struct radeon_encoder_tv_dac *tv_dac = NULL; 1015 int found = 0; 1016 1017 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); 1018 if (!tv_dac) 1019 return NULL; 1020 1021 /* first check TV table */ 1022 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 1023 if (dac_info) { 1024 rev = RBIOS8(dac_info + 0x3); 1025 if (rev > 4) { 1026 bg = RBIOS8(dac_info + 0xc) & 0xf; 1027 dac = RBIOS8(dac_info + 0xd) & 0xf; 1028 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1029 1030 bg = RBIOS8(dac_info + 0xe) & 0xf; 1031 dac = RBIOS8(dac_info + 0xf) & 0xf; 1032 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1033 1034 bg = RBIOS8(dac_info + 0x10) & 0xf; 1035 dac = RBIOS8(dac_info + 0x11) & 0xf; 1036 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1037 /* if the values are all zeros, use the table */ 1038 if (tv_dac->ps2_tvdac_adj) 1039 found = 1; 1040 } else if (rev > 1) { 1041 bg = RBIOS8(dac_info + 0xc) & 0xf; 1042 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf; 1043 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1044 1045 bg = RBIOS8(dac_info + 0xd) & 0xf; 1046 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf; 1047 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1048 1049 bg = RBIOS8(dac_info + 0xe) & 0xf; 1050 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf; 1051 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1052 /* if the values are all zeros, use the table */ 1053 if (tv_dac->ps2_tvdac_adj) 1054 found = 1; 1055 } 1056 tv_dac->tv_std = radeon_combios_get_tv_info(rdev); 1057 } 1058 if (!found) { 1059 /* then check CRT table */ 1060 dac_info = 1061 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 1062 if (dac_info) { 1063 rev = RBIOS8(dac_info) & 0x3; 1064 if (rev < 2) { 1065 bg = RBIOS8(dac_info + 0x3) & 0xf; 1066 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf; 1067 tv_dac->ps2_tvdac_adj = 1068 (bg << 16) | (dac << 20); 1069 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 1070 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 1071 /* if the values are all zeros, use the table */ 1072 if (tv_dac->ps2_tvdac_adj) 1073 found = 1; 1074 } else { 1075 bg = RBIOS8(dac_info + 0x4) & 0xf; 1076 dac = RBIOS8(dac_info + 0x5) & 0xf; 1077 tv_dac->ps2_tvdac_adj = 1078 (bg << 16) | (dac << 20); 1079 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 1080 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 1081 /* if the values are all zeros, use the table */ 1082 if (tv_dac->ps2_tvdac_adj) 1083 found = 1; 1084 } 1085 } else { 1086 DRM_INFO("No TV DAC info found in BIOS\n"); 1087 } 1088 } 1089 1090 if (!found) /* fallback to defaults */ 1091 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac); 1092 1093 return tv_dac; 1094 } 1095 1096 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct 1097 radeon_device 1098 *rdev) 1099 { 1100 struct radeon_encoder_lvds *lvds = NULL; 1101 uint32_t fp_vert_stretch, fp_horz_stretch; 1102 uint32_t ppll_div_sel, ppll_val; 1103 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); 1104 1105 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); 1106 1107 if (!lvds) 1108 return NULL; 1109 1110 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH); 1111 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH); 1112 1113 /* These should be fail-safe defaults, fingers crossed */ 1114 lvds->panel_pwr_delay = 200; 1115 lvds->panel_vcc_delay = 2000; 1116 1117 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 1118 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf; 1119 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf; 1120 1121 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) 1122 lvds->native_mode.vdisplay = 1123 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >> 1124 RADEON_VERT_PANEL_SHIFT) + 1; 1125 else 1126 lvds->native_mode.vdisplay = 1127 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1; 1128 1129 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE) 1130 lvds->native_mode.hdisplay = 1131 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >> 1132 RADEON_HORZ_PANEL_SHIFT) + 1) * 8; 1133 else 1134 lvds->native_mode.hdisplay = 1135 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8; 1136 1137 if ((lvds->native_mode.hdisplay < 640) || 1138 (lvds->native_mode.vdisplay < 480)) { 1139 lvds->native_mode.hdisplay = 640; 1140 lvds->native_mode.vdisplay = 480; 1141 } 1142 1143 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; 1144 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel); 1145 if ((ppll_val & 0x000707ff) == 0x1bb) 1146 lvds->use_bios_dividers = false; 1147 else { 1148 lvds->panel_ref_divider = 1149 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; 1150 lvds->panel_post_divider = (ppll_val >> 16) & 0x7; 1151 lvds->panel_fb_divider = ppll_val & 0x7ff; 1152 1153 if ((lvds->panel_ref_divider != 0) && 1154 (lvds->panel_fb_divider > 3)) 1155 lvds->use_bios_dividers = true; 1156 } 1157 lvds->panel_vcc_delay = 200; 1158 1159 DRM_INFO("Panel info derived from registers\n"); 1160 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 1161 lvds->native_mode.vdisplay); 1162 1163 return lvds; 1164 } 1165 1166 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder 1167 *encoder) 1168 { 1169 struct drm_device *dev = encoder->base.dev; 1170 struct radeon_device *rdev = dev->dev_private; 1171 uint16_t lcd_info; 1172 uint32_t panel_setup; 1173 char stmp[30]; 1174 int tmp, i; 1175 struct radeon_encoder_lvds *lvds = NULL; 1176 1177 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 1178 1179 if (lcd_info) { 1180 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); 1181 1182 if (!lvds) 1183 return NULL; 1184 1185 for (i = 0; i < 24; i++) 1186 stmp[i] = RBIOS8(lcd_info + i + 1); 1187 stmp[24] = 0; 1188 1189 DRM_INFO("Panel ID String: %s\n", stmp); 1190 1191 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19); 1192 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b); 1193 1194 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 1195 lvds->native_mode.vdisplay); 1196 1197 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c); 1198 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000); 1199 1200 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24); 1201 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf; 1202 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf; 1203 1204 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e); 1205 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30); 1206 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31); 1207 if ((lvds->panel_ref_divider != 0) && 1208 (lvds->panel_fb_divider > 3)) 1209 lvds->use_bios_dividers = true; 1210 1211 panel_setup = RBIOS32(lcd_info + 0x39); 1212 lvds->lvds_gen_cntl = 0xff00; 1213 if (panel_setup & 0x1) 1214 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT; 1215 1216 if ((panel_setup >> 4) & 0x1) 1217 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE; 1218 1219 switch ((panel_setup >> 8) & 0x7) { 1220 case 0: 1221 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM; 1222 break; 1223 case 1: 1224 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY; 1225 break; 1226 case 2: 1227 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY; 1228 break; 1229 default: 1230 break; 1231 } 1232 1233 if ((panel_setup >> 16) & 0x1) 1234 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW; 1235 1236 if ((panel_setup >> 17) & 0x1) 1237 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW; 1238 1239 if ((panel_setup >> 18) & 0x1) 1240 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW; 1241 1242 if ((panel_setup >> 23) & 0x1) 1243 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL; 1244 1245 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000); 1246 1247 for (i = 0; i < 32; i++) { 1248 tmp = RBIOS16(lcd_info + 64 + i * 2); 1249 if (tmp == 0) 1250 break; 1251 1252 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) && 1253 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) { 1254 u32 hss = (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8; 1255 1256 if (hss > lvds->native_mode.hdisplay) 1257 hss = (10 - 1) * 8; 1258 1259 lvds->native_mode.htotal = lvds->native_mode.hdisplay + 1260 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8; 1261 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + 1262 hss; 1263 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + 1264 (RBIOS8(tmp + 23) * 8); 1265 1266 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + 1267 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26)); 1268 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + 1269 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26)); 1270 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + 1271 ((RBIOS16(tmp + 28) & 0xf800) >> 11); 1272 1273 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10; 1274 lvds->native_mode.flags = 0; 1275 /* set crtc values */ 1276 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); 1277 1278 } 1279 } 1280 } else { 1281 DRM_INFO("No panel info found in BIOS\n"); 1282 lvds = radeon_legacy_get_lvds_info_from_regs(rdev); 1283 } 1284 1285 if (lvds) 1286 encoder->native_mode = lvds->native_mode; 1287 return lvds; 1288 } 1289 1290 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = { 1291 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */ 1292 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */ 1293 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */ 1294 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */ 1295 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */ 1296 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */ 1297 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */ 1298 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */ 1299 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */ 1300 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */ 1301 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */ 1302 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */ 1303 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */ 1304 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */ 1305 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */ 1306 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */ 1307 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */ 1308 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */ 1309 }; 1310 1311 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 1312 struct radeon_encoder_int_tmds *tmds) 1313 { 1314 struct drm_device *dev = encoder->base.dev; 1315 struct radeon_device *rdev = dev->dev_private; 1316 int i; 1317 1318 for (i = 0; i < 4; i++) { 1319 tmds->tmds_pll[i].value = 1320 default_tmds_pll[rdev->family][i].value; 1321 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq; 1322 } 1323 1324 return true; 1325 } 1326 1327 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 1328 struct radeon_encoder_int_tmds *tmds) 1329 { 1330 struct drm_device *dev = encoder->base.dev; 1331 struct radeon_device *rdev = dev->dev_private; 1332 uint16_t tmds_info; 1333 int i, n; 1334 uint8_t ver; 1335 1336 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 1337 1338 if (tmds_info) { 1339 ver = RBIOS8(tmds_info); 1340 DRM_DEBUG_KMS("DFP table revision: %d\n", ver); 1341 if (ver == 3) { 1342 n = RBIOS8(tmds_info + 5) + 1; 1343 if (n > 4) 1344 n = 4; 1345 for (i = 0; i < n; i++) { 1346 tmds->tmds_pll[i].value = 1347 RBIOS32(tmds_info + i * 10 + 0x08); 1348 tmds->tmds_pll[i].freq = 1349 RBIOS16(tmds_info + i * 10 + 0x10); 1350 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", 1351 tmds->tmds_pll[i].freq, 1352 tmds->tmds_pll[i].value); 1353 } 1354 } else if (ver == 4) { 1355 int stride = 0; 1356 n = RBIOS8(tmds_info + 5) + 1; 1357 if (n > 4) 1358 n = 4; 1359 for (i = 0; i < n; i++) { 1360 tmds->tmds_pll[i].value = 1361 RBIOS32(tmds_info + stride + 0x08); 1362 tmds->tmds_pll[i].freq = 1363 RBIOS16(tmds_info + stride + 0x10); 1364 if (i == 0) 1365 stride += 10; 1366 else 1367 stride += 6; 1368 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", 1369 tmds->tmds_pll[i].freq, 1370 tmds->tmds_pll[i].value); 1371 } 1372 } 1373 } else { 1374 DRM_INFO("No TMDS info found in BIOS\n"); 1375 return false; 1376 } 1377 return true; 1378 } 1379 1380 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 1381 struct radeon_encoder_ext_tmds *tmds) 1382 { 1383 struct drm_device *dev = encoder->base.dev; 1384 struct radeon_device *rdev = dev->dev_private; 1385 struct radeon_i2c_bus_rec i2c_bus; 1386 1387 /* default for macs */ 1388 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1389 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1390 1391 /* XXX some macs have duallink chips */ 1392 switch (rdev->mode_info.connector_table) { 1393 case CT_POWERBOOK_EXTERNAL: 1394 case CT_MINI_EXTERNAL: 1395 default: 1396 tmds->dvo_chip = DVO_SIL164; 1397 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1398 break; 1399 } 1400 1401 return true; 1402 } 1403 1404 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 1405 struct radeon_encoder_ext_tmds *tmds) 1406 { 1407 struct drm_device *dev = encoder->base.dev; 1408 struct radeon_device *rdev = dev->dev_private; 1409 uint16_t offset; 1410 uint8_t ver; 1411 enum radeon_combios_ddc gpio; 1412 struct radeon_i2c_bus_rec i2c_bus; 1413 1414 tmds->i2c_bus = NULL; 1415 if (rdev->flags & RADEON_IS_IGP) { 1416 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1417 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1418 tmds->dvo_chip = DVO_SIL164; 1419 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1420 } else { 1421 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 1422 if (offset) { 1423 ver = RBIOS8(offset); 1424 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver); 1425 tmds->slave_addr = RBIOS8(offset + 4 + 2); 1426 tmds->slave_addr >>= 1; /* 7 bit addressing */ 1427 gpio = RBIOS8(offset + 4 + 3); 1428 if (gpio == DDC_LCD) { 1429 /* MM i2c */ 1430 i2c_bus.valid = true; 1431 i2c_bus.hw_capable = true; 1432 i2c_bus.mm_i2c = true; 1433 i2c_bus.i2c_id = 0xa0; 1434 } else 1435 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); 1436 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1437 } 1438 } 1439 1440 if (!tmds->i2c_bus) { 1441 DRM_INFO("No valid Ext TMDS info found in BIOS\n"); 1442 return false; 1443 } 1444 1445 return true; 1446 } 1447 1448 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) 1449 { 1450 struct radeon_device *rdev = dev->dev_private; 1451 struct radeon_i2c_bus_rec ddc_i2c; 1452 struct radeon_hpd hpd; 1453 1454 rdev->mode_info.connector_table = radeon_connector_table; 1455 if (rdev->mode_info.connector_table == CT_NONE) { 1456 #ifdef CONFIG_PPC_PMAC 1457 if (of_machine_is_compatible("PowerBook3,3")) { 1458 /* powerbook with VGA */ 1459 rdev->mode_info.connector_table = CT_POWERBOOK_VGA; 1460 } else if (of_machine_is_compatible("PowerBook3,4") || 1461 of_machine_is_compatible("PowerBook3,5")) { 1462 /* powerbook with internal tmds */ 1463 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL; 1464 } else if (of_machine_is_compatible("PowerBook5,1") || 1465 of_machine_is_compatible("PowerBook5,2") || 1466 of_machine_is_compatible("PowerBook5,3") || 1467 of_machine_is_compatible("PowerBook5,4") || 1468 of_machine_is_compatible("PowerBook5,5")) { 1469 /* powerbook with external single link tmds (sil164) */ 1470 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1471 } else if (of_machine_is_compatible("PowerBook5,6")) { 1472 /* powerbook with external dual or single link tmds */ 1473 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1474 } else if (of_machine_is_compatible("PowerBook5,7") || 1475 of_machine_is_compatible("PowerBook5,8") || 1476 of_machine_is_compatible("PowerBook5,9")) { 1477 /* PowerBook6,2 ? */ 1478 /* powerbook with external dual link tmds (sil1178?) */ 1479 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1480 } else if (of_machine_is_compatible("PowerBook4,1") || 1481 of_machine_is_compatible("PowerBook4,2") || 1482 of_machine_is_compatible("PowerBook4,3") || 1483 of_machine_is_compatible("PowerBook6,3") || 1484 of_machine_is_compatible("PowerBook6,5") || 1485 of_machine_is_compatible("PowerBook6,7")) { 1486 /* ibook */ 1487 rdev->mode_info.connector_table = CT_IBOOK; 1488 } else if (of_machine_is_compatible("PowerMac3,5")) { 1489 /* PowerMac G4 Silver radeon 7500 */ 1490 rdev->mode_info.connector_table = CT_MAC_G4_SILVER; 1491 } else if (of_machine_is_compatible("PowerMac4,4")) { 1492 /* emac */ 1493 rdev->mode_info.connector_table = CT_EMAC; 1494 } else if (of_machine_is_compatible("PowerMac10,1")) { 1495 /* mini with internal tmds */ 1496 rdev->mode_info.connector_table = CT_MINI_INTERNAL; 1497 } else if (of_machine_is_compatible("PowerMac10,2")) { 1498 /* mini with external tmds */ 1499 rdev->mode_info.connector_table = CT_MINI_EXTERNAL; 1500 } else if (of_machine_is_compatible("PowerMac12,1")) { 1501 /* PowerMac8,1 ? */ 1502 /* imac g5 isight */ 1503 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT; 1504 } else if ((rdev->pdev->device == 0x4a48) && 1505 (rdev->pdev->subsystem_vendor == 0x1002) && 1506 (rdev->pdev->subsystem_device == 0x4a48)) { 1507 /* Mac X800 */ 1508 rdev->mode_info.connector_table = CT_MAC_X800; 1509 } else if ((of_machine_is_compatible("PowerMac7,2") || 1510 of_machine_is_compatible("PowerMac7,3")) && 1511 (rdev->pdev->device == 0x4150) && 1512 (rdev->pdev->subsystem_vendor == 0x1002) && 1513 (rdev->pdev->subsystem_device == 0x4150)) { 1514 /* Mac G5 tower 9600 */ 1515 rdev->mode_info.connector_table = CT_MAC_G5_9600; 1516 } else if ((rdev->pdev->device == 0x4c66) && 1517 (rdev->pdev->subsystem_vendor == 0x1002) && 1518 (rdev->pdev->subsystem_device == 0x4c66)) { 1519 /* SAM440ep RV250 embedded board */ 1520 rdev->mode_info.connector_table = CT_SAM440EP; 1521 } else 1522 #endif /* CONFIG_PPC_PMAC */ 1523 #ifdef CONFIG_PPC64 1524 if (ASIC_IS_RN50(rdev)) 1525 rdev->mode_info.connector_table = CT_RN50_POWER; 1526 else 1527 #endif 1528 rdev->mode_info.connector_table = CT_GENERIC; 1529 } 1530 1531 switch (rdev->mode_info.connector_table) { 1532 case CT_GENERIC: 1533 DRM_INFO("Connector Table: %d (generic)\n", 1534 rdev->mode_info.connector_table); 1535 /* these are the most common settings */ 1536 if (rdev->flags & RADEON_SINGLE_CRTC) { 1537 /* VGA - primary dac */ 1538 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1539 hpd.hpd = RADEON_HPD_NONE; 1540 radeon_add_legacy_encoder(dev, 1541 radeon_get_encoder_enum(dev, 1542 ATOM_DEVICE_CRT1_SUPPORT, 1543 1), 1544 ATOM_DEVICE_CRT1_SUPPORT); 1545 radeon_add_legacy_connector(dev, 0, 1546 ATOM_DEVICE_CRT1_SUPPORT, 1547 DRM_MODE_CONNECTOR_VGA, 1548 &ddc_i2c, 1549 CONNECTOR_OBJECT_ID_VGA, 1550 &hpd); 1551 } else if (rdev->flags & RADEON_IS_MOBILITY) { 1552 /* LVDS */ 1553 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); 1554 hpd.hpd = RADEON_HPD_NONE; 1555 radeon_add_legacy_encoder(dev, 1556 radeon_get_encoder_enum(dev, 1557 ATOM_DEVICE_LCD1_SUPPORT, 1558 0), 1559 ATOM_DEVICE_LCD1_SUPPORT); 1560 radeon_add_legacy_connector(dev, 0, 1561 ATOM_DEVICE_LCD1_SUPPORT, 1562 DRM_MODE_CONNECTOR_LVDS, 1563 &ddc_i2c, 1564 CONNECTOR_OBJECT_ID_LVDS, 1565 &hpd); 1566 1567 /* VGA - primary dac */ 1568 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1569 hpd.hpd = RADEON_HPD_NONE; 1570 radeon_add_legacy_encoder(dev, 1571 radeon_get_encoder_enum(dev, 1572 ATOM_DEVICE_CRT1_SUPPORT, 1573 1), 1574 ATOM_DEVICE_CRT1_SUPPORT); 1575 radeon_add_legacy_connector(dev, 1, 1576 ATOM_DEVICE_CRT1_SUPPORT, 1577 DRM_MODE_CONNECTOR_VGA, 1578 &ddc_i2c, 1579 CONNECTOR_OBJECT_ID_VGA, 1580 &hpd); 1581 } else { 1582 /* DVI-I - tv dac, int tmds */ 1583 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1584 hpd.hpd = RADEON_HPD_1; 1585 radeon_add_legacy_encoder(dev, 1586 radeon_get_encoder_enum(dev, 1587 ATOM_DEVICE_DFP1_SUPPORT, 1588 0), 1589 ATOM_DEVICE_DFP1_SUPPORT); 1590 radeon_add_legacy_encoder(dev, 1591 radeon_get_encoder_enum(dev, 1592 ATOM_DEVICE_CRT2_SUPPORT, 1593 2), 1594 ATOM_DEVICE_CRT2_SUPPORT); 1595 radeon_add_legacy_connector(dev, 0, 1596 ATOM_DEVICE_DFP1_SUPPORT | 1597 ATOM_DEVICE_CRT2_SUPPORT, 1598 DRM_MODE_CONNECTOR_DVII, 1599 &ddc_i2c, 1600 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1601 &hpd); 1602 1603 /* VGA - primary dac */ 1604 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1605 hpd.hpd = RADEON_HPD_NONE; 1606 radeon_add_legacy_encoder(dev, 1607 radeon_get_encoder_enum(dev, 1608 ATOM_DEVICE_CRT1_SUPPORT, 1609 1), 1610 ATOM_DEVICE_CRT1_SUPPORT); 1611 radeon_add_legacy_connector(dev, 1, 1612 ATOM_DEVICE_CRT1_SUPPORT, 1613 DRM_MODE_CONNECTOR_VGA, 1614 &ddc_i2c, 1615 CONNECTOR_OBJECT_ID_VGA, 1616 &hpd); 1617 } 1618 1619 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 1620 /* TV - tv dac */ 1621 ddc_i2c.valid = false; 1622 hpd.hpd = RADEON_HPD_NONE; 1623 radeon_add_legacy_encoder(dev, 1624 radeon_get_encoder_enum(dev, 1625 ATOM_DEVICE_TV1_SUPPORT, 1626 2), 1627 ATOM_DEVICE_TV1_SUPPORT); 1628 radeon_add_legacy_connector(dev, 2, 1629 ATOM_DEVICE_TV1_SUPPORT, 1630 DRM_MODE_CONNECTOR_SVIDEO, 1631 &ddc_i2c, 1632 CONNECTOR_OBJECT_ID_SVIDEO, 1633 &hpd); 1634 } 1635 break; 1636 case CT_IBOOK: 1637 DRM_INFO("Connector Table: %d (ibook)\n", 1638 rdev->mode_info.connector_table); 1639 /* LVDS */ 1640 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1641 hpd.hpd = RADEON_HPD_NONE; 1642 radeon_add_legacy_encoder(dev, 1643 radeon_get_encoder_enum(dev, 1644 ATOM_DEVICE_LCD1_SUPPORT, 1645 0), 1646 ATOM_DEVICE_LCD1_SUPPORT); 1647 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1648 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1649 CONNECTOR_OBJECT_ID_LVDS, 1650 &hpd); 1651 /* VGA - TV DAC */ 1652 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1653 hpd.hpd = RADEON_HPD_NONE; 1654 radeon_add_legacy_encoder(dev, 1655 radeon_get_encoder_enum(dev, 1656 ATOM_DEVICE_CRT2_SUPPORT, 1657 2), 1658 ATOM_DEVICE_CRT2_SUPPORT); 1659 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1660 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1661 CONNECTOR_OBJECT_ID_VGA, 1662 &hpd); 1663 /* TV - TV DAC */ 1664 ddc_i2c.valid = false; 1665 hpd.hpd = RADEON_HPD_NONE; 1666 radeon_add_legacy_encoder(dev, 1667 radeon_get_encoder_enum(dev, 1668 ATOM_DEVICE_TV1_SUPPORT, 1669 2), 1670 ATOM_DEVICE_TV1_SUPPORT); 1671 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1672 DRM_MODE_CONNECTOR_SVIDEO, 1673 &ddc_i2c, 1674 CONNECTOR_OBJECT_ID_SVIDEO, 1675 &hpd); 1676 break; 1677 case CT_POWERBOOK_EXTERNAL: 1678 DRM_INFO("Connector Table: %d (powerbook external tmds)\n", 1679 rdev->mode_info.connector_table); 1680 /* LVDS */ 1681 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1682 hpd.hpd = RADEON_HPD_NONE; 1683 radeon_add_legacy_encoder(dev, 1684 radeon_get_encoder_enum(dev, 1685 ATOM_DEVICE_LCD1_SUPPORT, 1686 0), 1687 ATOM_DEVICE_LCD1_SUPPORT); 1688 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1689 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1690 CONNECTOR_OBJECT_ID_LVDS, 1691 &hpd); 1692 /* DVI-I - primary dac, ext tmds */ 1693 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1694 hpd.hpd = RADEON_HPD_2; /* ??? */ 1695 radeon_add_legacy_encoder(dev, 1696 radeon_get_encoder_enum(dev, 1697 ATOM_DEVICE_DFP2_SUPPORT, 1698 0), 1699 ATOM_DEVICE_DFP2_SUPPORT); 1700 radeon_add_legacy_encoder(dev, 1701 radeon_get_encoder_enum(dev, 1702 ATOM_DEVICE_CRT1_SUPPORT, 1703 1), 1704 ATOM_DEVICE_CRT1_SUPPORT); 1705 /* XXX some are SL */ 1706 radeon_add_legacy_connector(dev, 1, 1707 ATOM_DEVICE_DFP2_SUPPORT | 1708 ATOM_DEVICE_CRT1_SUPPORT, 1709 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1710 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, 1711 &hpd); 1712 /* TV - TV DAC */ 1713 ddc_i2c.valid = false; 1714 hpd.hpd = RADEON_HPD_NONE; 1715 radeon_add_legacy_encoder(dev, 1716 radeon_get_encoder_enum(dev, 1717 ATOM_DEVICE_TV1_SUPPORT, 1718 2), 1719 ATOM_DEVICE_TV1_SUPPORT); 1720 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1721 DRM_MODE_CONNECTOR_SVIDEO, 1722 &ddc_i2c, 1723 CONNECTOR_OBJECT_ID_SVIDEO, 1724 &hpd); 1725 break; 1726 case CT_POWERBOOK_INTERNAL: 1727 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n", 1728 rdev->mode_info.connector_table); 1729 /* LVDS */ 1730 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1731 hpd.hpd = RADEON_HPD_NONE; 1732 radeon_add_legacy_encoder(dev, 1733 radeon_get_encoder_enum(dev, 1734 ATOM_DEVICE_LCD1_SUPPORT, 1735 0), 1736 ATOM_DEVICE_LCD1_SUPPORT); 1737 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1738 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1739 CONNECTOR_OBJECT_ID_LVDS, 1740 &hpd); 1741 /* DVI-I - primary dac, int tmds */ 1742 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1743 hpd.hpd = RADEON_HPD_1; /* ??? */ 1744 radeon_add_legacy_encoder(dev, 1745 radeon_get_encoder_enum(dev, 1746 ATOM_DEVICE_DFP1_SUPPORT, 1747 0), 1748 ATOM_DEVICE_DFP1_SUPPORT); 1749 radeon_add_legacy_encoder(dev, 1750 radeon_get_encoder_enum(dev, 1751 ATOM_DEVICE_CRT1_SUPPORT, 1752 1), 1753 ATOM_DEVICE_CRT1_SUPPORT); 1754 radeon_add_legacy_connector(dev, 1, 1755 ATOM_DEVICE_DFP1_SUPPORT | 1756 ATOM_DEVICE_CRT1_SUPPORT, 1757 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1758 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1759 &hpd); 1760 /* TV - TV DAC */ 1761 ddc_i2c.valid = false; 1762 hpd.hpd = RADEON_HPD_NONE; 1763 radeon_add_legacy_encoder(dev, 1764 radeon_get_encoder_enum(dev, 1765 ATOM_DEVICE_TV1_SUPPORT, 1766 2), 1767 ATOM_DEVICE_TV1_SUPPORT); 1768 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1769 DRM_MODE_CONNECTOR_SVIDEO, 1770 &ddc_i2c, 1771 CONNECTOR_OBJECT_ID_SVIDEO, 1772 &hpd); 1773 break; 1774 case CT_POWERBOOK_VGA: 1775 DRM_INFO("Connector Table: %d (powerbook vga)\n", 1776 rdev->mode_info.connector_table); 1777 /* LVDS */ 1778 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1779 hpd.hpd = RADEON_HPD_NONE; 1780 radeon_add_legacy_encoder(dev, 1781 radeon_get_encoder_enum(dev, 1782 ATOM_DEVICE_LCD1_SUPPORT, 1783 0), 1784 ATOM_DEVICE_LCD1_SUPPORT); 1785 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1786 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1787 CONNECTOR_OBJECT_ID_LVDS, 1788 &hpd); 1789 /* VGA - primary dac */ 1790 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1791 hpd.hpd = RADEON_HPD_NONE; 1792 radeon_add_legacy_encoder(dev, 1793 radeon_get_encoder_enum(dev, 1794 ATOM_DEVICE_CRT1_SUPPORT, 1795 1), 1796 ATOM_DEVICE_CRT1_SUPPORT); 1797 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, 1798 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1799 CONNECTOR_OBJECT_ID_VGA, 1800 &hpd); 1801 /* TV - TV DAC */ 1802 ddc_i2c.valid = false; 1803 hpd.hpd = RADEON_HPD_NONE; 1804 radeon_add_legacy_encoder(dev, 1805 radeon_get_encoder_enum(dev, 1806 ATOM_DEVICE_TV1_SUPPORT, 1807 2), 1808 ATOM_DEVICE_TV1_SUPPORT); 1809 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1810 DRM_MODE_CONNECTOR_SVIDEO, 1811 &ddc_i2c, 1812 CONNECTOR_OBJECT_ID_SVIDEO, 1813 &hpd); 1814 break; 1815 case CT_MINI_EXTERNAL: 1816 DRM_INFO("Connector Table: %d (mini external tmds)\n", 1817 rdev->mode_info.connector_table); 1818 /* DVI-I - tv dac, ext tmds */ 1819 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1820 hpd.hpd = RADEON_HPD_2; /* ??? */ 1821 radeon_add_legacy_encoder(dev, 1822 radeon_get_encoder_enum(dev, 1823 ATOM_DEVICE_DFP2_SUPPORT, 1824 0), 1825 ATOM_DEVICE_DFP2_SUPPORT); 1826 radeon_add_legacy_encoder(dev, 1827 radeon_get_encoder_enum(dev, 1828 ATOM_DEVICE_CRT2_SUPPORT, 1829 2), 1830 ATOM_DEVICE_CRT2_SUPPORT); 1831 /* XXX are any DL? */ 1832 radeon_add_legacy_connector(dev, 0, 1833 ATOM_DEVICE_DFP2_SUPPORT | 1834 ATOM_DEVICE_CRT2_SUPPORT, 1835 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1836 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1837 &hpd); 1838 /* TV - TV DAC */ 1839 ddc_i2c.valid = false; 1840 hpd.hpd = RADEON_HPD_NONE; 1841 radeon_add_legacy_encoder(dev, 1842 radeon_get_encoder_enum(dev, 1843 ATOM_DEVICE_TV1_SUPPORT, 1844 2), 1845 ATOM_DEVICE_TV1_SUPPORT); 1846 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1847 DRM_MODE_CONNECTOR_SVIDEO, 1848 &ddc_i2c, 1849 CONNECTOR_OBJECT_ID_SVIDEO, 1850 &hpd); 1851 break; 1852 case CT_MINI_INTERNAL: 1853 DRM_INFO("Connector Table: %d (mini internal tmds)\n", 1854 rdev->mode_info.connector_table); 1855 /* DVI-I - tv dac, int tmds */ 1856 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1857 hpd.hpd = RADEON_HPD_1; /* ??? */ 1858 radeon_add_legacy_encoder(dev, 1859 radeon_get_encoder_enum(dev, 1860 ATOM_DEVICE_DFP1_SUPPORT, 1861 0), 1862 ATOM_DEVICE_DFP1_SUPPORT); 1863 radeon_add_legacy_encoder(dev, 1864 radeon_get_encoder_enum(dev, 1865 ATOM_DEVICE_CRT2_SUPPORT, 1866 2), 1867 ATOM_DEVICE_CRT2_SUPPORT); 1868 radeon_add_legacy_connector(dev, 0, 1869 ATOM_DEVICE_DFP1_SUPPORT | 1870 ATOM_DEVICE_CRT2_SUPPORT, 1871 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1872 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1873 &hpd); 1874 /* TV - TV DAC */ 1875 ddc_i2c.valid = false; 1876 hpd.hpd = RADEON_HPD_NONE; 1877 radeon_add_legacy_encoder(dev, 1878 radeon_get_encoder_enum(dev, 1879 ATOM_DEVICE_TV1_SUPPORT, 1880 2), 1881 ATOM_DEVICE_TV1_SUPPORT); 1882 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1883 DRM_MODE_CONNECTOR_SVIDEO, 1884 &ddc_i2c, 1885 CONNECTOR_OBJECT_ID_SVIDEO, 1886 &hpd); 1887 break; 1888 case CT_IMAC_G5_ISIGHT: 1889 DRM_INFO("Connector Table: %d (imac g5 isight)\n", 1890 rdev->mode_info.connector_table); 1891 /* DVI-D - int tmds */ 1892 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1893 hpd.hpd = RADEON_HPD_1; /* ??? */ 1894 radeon_add_legacy_encoder(dev, 1895 radeon_get_encoder_enum(dev, 1896 ATOM_DEVICE_DFP1_SUPPORT, 1897 0), 1898 ATOM_DEVICE_DFP1_SUPPORT); 1899 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT, 1900 DRM_MODE_CONNECTOR_DVID, &ddc_i2c, 1901 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 1902 &hpd); 1903 /* VGA - tv dac */ 1904 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1905 hpd.hpd = RADEON_HPD_NONE; 1906 radeon_add_legacy_encoder(dev, 1907 radeon_get_encoder_enum(dev, 1908 ATOM_DEVICE_CRT2_SUPPORT, 1909 2), 1910 ATOM_DEVICE_CRT2_SUPPORT); 1911 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1912 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1913 CONNECTOR_OBJECT_ID_VGA, 1914 &hpd); 1915 /* TV - TV DAC */ 1916 ddc_i2c.valid = false; 1917 hpd.hpd = RADEON_HPD_NONE; 1918 radeon_add_legacy_encoder(dev, 1919 radeon_get_encoder_enum(dev, 1920 ATOM_DEVICE_TV1_SUPPORT, 1921 2), 1922 ATOM_DEVICE_TV1_SUPPORT); 1923 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1924 DRM_MODE_CONNECTOR_SVIDEO, 1925 &ddc_i2c, 1926 CONNECTOR_OBJECT_ID_SVIDEO, 1927 &hpd); 1928 break; 1929 case CT_EMAC: 1930 DRM_INFO("Connector Table: %d (emac)\n", 1931 rdev->mode_info.connector_table); 1932 /* VGA - primary dac */ 1933 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1934 hpd.hpd = RADEON_HPD_NONE; 1935 radeon_add_legacy_encoder(dev, 1936 radeon_get_encoder_enum(dev, 1937 ATOM_DEVICE_CRT1_SUPPORT, 1938 1), 1939 ATOM_DEVICE_CRT1_SUPPORT); 1940 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, 1941 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1942 CONNECTOR_OBJECT_ID_VGA, 1943 &hpd); 1944 /* VGA - tv dac */ 1945 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1946 hpd.hpd = RADEON_HPD_NONE; 1947 radeon_add_legacy_encoder(dev, 1948 radeon_get_encoder_enum(dev, 1949 ATOM_DEVICE_CRT2_SUPPORT, 1950 2), 1951 ATOM_DEVICE_CRT2_SUPPORT); 1952 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1953 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1954 CONNECTOR_OBJECT_ID_VGA, 1955 &hpd); 1956 /* TV - TV DAC */ 1957 ddc_i2c.valid = false; 1958 hpd.hpd = RADEON_HPD_NONE; 1959 radeon_add_legacy_encoder(dev, 1960 radeon_get_encoder_enum(dev, 1961 ATOM_DEVICE_TV1_SUPPORT, 1962 2), 1963 ATOM_DEVICE_TV1_SUPPORT); 1964 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1965 DRM_MODE_CONNECTOR_SVIDEO, 1966 &ddc_i2c, 1967 CONNECTOR_OBJECT_ID_SVIDEO, 1968 &hpd); 1969 break; 1970 case CT_RN50_POWER: 1971 DRM_INFO("Connector Table: %d (rn50-power)\n", 1972 rdev->mode_info.connector_table); 1973 /* VGA - primary dac */ 1974 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1975 hpd.hpd = RADEON_HPD_NONE; 1976 radeon_add_legacy_encoder(dev, 1977 radeon_get_encoder_enum(dev, 1978 ATOM_DEVICE_CRT1_SUPPORT, 1979 1), 1980 ATOM_DEVICE_CRT1_SUPPORT); 1981 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, 1982 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1983 CONNECTOR_OBJECT_ID_VGA, 1984 &hpd); 1985 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1986 hpd.hpd = RADEON_HPD_NONE; 1987 radeon_add_legacy_encoder(dev, 1988 radeon_get_encoder_enum(dev, 1989 ATOM_DEVICE_CRT2_SUPPORT, 1990 2), 1991 ATOM_DEVICE_CRT2_SUPPORT); 1992 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1993 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1994 CONNECTOR_OBJECT_ID_VGA, 1995 &hpd); 1996 break; 1997 case CT_MAC_X800: 1998 DRM_INFO("Connector Table: %d (mac x800)\n", 1999 rdev->mode_info.connector_table); 2000 /* DVI - primary dac, internal tmds */ 2001 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2002 hpd.hpd = RADEON_HPD_1; /* ??? */ 2003 radeon_add_legacy_encoder(dev, 2004 radeon_get_encoder_enum(dev, 2005 ATOM_DEVICE_DFP1_SUPPORT, 2006 0), 2007 ATOM_DEVICE_DFP1_SUPPORT); 2008 radeon_add_legacy_encoder(dev, 2009 radeon_get_encoder_enum(dev, 2010 ATOM_DEVICE_CRT1_SUPPORT, 2011 1), 2012 ATOM_DEVICE_CRT1_SUPPORT); 2013 radeon_add_legacy_connector(dev, 0, 2014 ATOM_DEVICE_DFP1_SUPPORT | 2015 ATOM_DEVICE_CRT1_SUPPORT, 2016 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2017 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2018 &hpd); 2019 /* DVI - tv dac, dvo */ 2020 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 2021 hpd.hpd = RADEON_HPD_2; /* ??? */ 2022 radeon_add_legacy_encoder(dev, 2023 radeon_get_encoder_enum(dev, 2024 ATOM_DEVICE_DFP2_SUPPORT, 2025 0), 2026 ATOM_DEVICE_DFP2_SUPPORT); 2027 radeon_add_legacy_encoder(dev, 2028 radeon_get_encoder_enum(dev, 2029 ATOM_DEVICE_CRT2_SUPPORT, 2030 2), 2031 ATOM_DEVICE_CRT2_SUPPORT); 2032 radeon_add_legacy_connector(dev, 1, 2033 ATOM_DEVICE_DFP2_SUPPORT | 2034 ATOM_DEVICE_CRT2_SUPPORT, 2035 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2036 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, 2037 &hpd); 2038 break; 2039 case CT_MAC_G5_9600: 2040 DRM_INFO("Connector Table: %d (mac g5 9600)\n", 2041 rdev->mode_info.connector_table); 2042 /* DVI - tv dac, dvo */ 2043 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2044 hpd.hpd = RADEON_HPD_1; /* ??? */ 2045 radeon_add_legacy_encoder(dev, 2046 radeon_get_encoder_enum(dev, 2047 ATOM_DEVICE_DFP2_SUPPORT, 2048 0), 2049 ATOM_DEVICE_DFP2_SUPPORT); 2050 radeon_add_legacy_encoder(dev, 2051 radeon_get_encoder_enum(dev, 2052 ATOM_DEVICE_CRT2_SUPPORT, 2053 2), 2054 ATOM_DEVICE_CRT2_SUPPORT); 2055 radeon_add_legacy_connector(dev, 0, 2056 ATOM_DEVICE_DFP2_SUPPORT | 2057 ATOM_DEVICE_CRT2_SUPPORT, 2058 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2059 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2060 &hpd); 2061 /* ADC - primary dac, internal tmds */ 2062 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2063 hpd.hpd = RADEON_HPD_2; /* ??? */ 2064 radeon_add_legacy_encoder(dev, 2065 radeon_get_encoder_enum(dev, 2066 ATOM_DEVICE_DFP1_SUPPORT, 2067 0), 2068 ATOM_DEVICE_DFP1_SUPPORT); 2069 radeon_add_legacy_encoder(dev, 2070 radeon_get_encoder_enum(dev, 2071 ATOM_DEVICE_CRT1_SUPPORT, 2072 1), 2073 ATOM_DEVICE_CRT1_SUPPORT); 2074 radeon_add_legacy_connector(dev, 1, 2075 ATOM_DEVICE_DFP1_SUPPORT | 2076 ATOM_DEVICE_CRT1_SUPPORT, 2077 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2078 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2079 &hpd); 2080 /* TV - TV DAC */ 2081 ddc_i2c.valid = false; 2082 hpd.hpd = RADEON_HPD_NONE; 2083 radeon_add_legacy_encoder(dev, 2084 radeon_get_encoder_enum(dev, 2085 ATOM_DEVICE_TV1_SUPPORT, 2086 2), 2087 ATOM_DEVICE_TV1_SUPPORT); 2088 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 2089 DRM_MODE_CONNECTOR_SVIDEO, 2090 &ddc_i2c, 2091 CONNECTOR_OBJECT_ID_SVIDEO, 2092 &hpd); 2093 break; 2094 case CT_SAM440EP: 2095 DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n", 2096 rdev->mode_info.connector_table); 2097 /* LVDS */ 2098 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); 2099 hpd.hpd = RADEON_HPD_NONE; 2100 radeon_add_legacy_encoder(dev, 2101 radeon_get_encoder_enum(dev, 2102 ATOM_DEVICE_LCD1_SUPPORT, 2103 0), 2104 ATOM_DEVICE_LCD1_SUPPORT); 2105 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 2106 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 2107 CONNECTOR_OBJECT_ID_LVDS, 2108 &hpd); 2109 /* DVI-I - secondary dac, int tmds */ 2110 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2111 hpd.hpd = RADEON_HPD_1; /* ??? */ 2112 radeon_add_legacy_encoder(dev, 2113 radeon_get_encoder_enum(dev, 2114 ATOM_DEVICE_DFP1_SUPPORT, 2115 0), 2116 ATOM_DEVICE_DFP1_SUPPORT); 2117 radeon_add_legacy_encoder(dev, 2118 radeon_get_encoder_enum(dev, 2119 ATOM_DEVICE_CRT2_SUPPORT, 2120 2), 2121 ATOM_DEVICE_CRT2_SUPPORT); 2122 radeon_add_legacy_connector(dev, 1, 2123 ATOM_DEVICE_DFP1_SUPPORT | 2124 ATOM_DEVICE_CRT2_SUPPORT, 2125 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2126 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2127 &hpd); 2128 /* VGA - primary dac */ 2129 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2130 hpd.hpd = RADEON_HPD_NONE; 2131 radeon_add_legacy_encoder(dev, 2132 radeon_get_encoder_enum(dev, 2133 ATOM_DEVICE_CRT1_SUPPORT, 2134 1), 2135 ATOM_DEVICE_CRT1_SUPPORT); 2136 radeon_add_legacy_connector(dev, 2, 2137 ATOM_DEVICE_CRT1_SUPPORT, 2138 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 2139 CONNECTOR_OBJECT_ID_VGA, 2140 &hpd); 2141 /* TV - TV DAC */ 2142 ddc_i2c.valid = false; 2143 hpd.hpd = RADEON_HPD_NONE; 2144 radeon_add_legacy_encoder(dev, 2145 radeon_get_encoder_enum(dev, 2146 ATOM_DEVICE_TV1_SUPPORT, 2147 2), 2148 ATOM_DEVICE_TV1_SUPPORT); 2149 radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT, 2150 DRM_MODE_CONNECTOR_SVIDEO, 2151 &ddc_i2c, 2152 CONNECTOR_OBJECT_ID_SVIDEO, 2153 &hpd); 2154 break; 2155 case CT_MAC_G4_SILVER: 2156 DRM_INFO("Connector Table: %d (mac g4 silver)\n", 2157 rdev->mode_info.connector_table); 2158 /* DVI-I - tv dac, int tmds */ 2159 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2160 hpd.hpd = RADEON_HPD_1; /* ??? */ 2161 radeon_add_legacy_encoder(dev, 2162 radeon_get_encoder_enum(dev, 2163 ATOM_DEVICE_DFP1_SUPPORT, 2164 0), 2165 ATOM_DEVICE_DFP1_SUPPORT); 2166 radeon_add_legacy_encoder(dev, 2167 radeon_get_encoder_enum(dev, 2168 ATOM_DEVICE_CRT2_SUPPORT, 2169 2), 2170 ATOM_DEVICE_CRT2_SUPPORT); 2171 radeon_add_legacy_connector(dev, 0, 2172 ATOM_DEVICE_DFP1_SUPPORT | 2173 ATOM_DEVICE_CRT2_SUPPORT, 2174 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2175 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2176 &hpd); 2177 /* VGA - primary dac */ 2178 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2179 hpd.hpd = RADEON_HPD_NONE; 2180 radeon_add_legacy_encoder(dev, 2181 radeon_get_encoder_enum(dev, 2182 ATOM_DEVICE_CRT1_SUPPORT, 2183 1), 2184 ATOM_DEVICE_CRT1_SUPPORT); 2185 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, 2186 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 2187 CONNECTOR_OBJECT_ID_VGA, 2188 &hpd); 2189 /* TV - TV DAC */ 2190 ddc_i2c.valid = false; 2191 hpd.hpd = RADEON_HPD_NONE; 2192 radeon_add_legacy_encoder(dev, 2193 radeon_get_encoder_enum(dev, 2194 ATOM_DEVICE_TV1_SUPPORT, 2195 2), 2196 ATOM_DEVICE_TV1_SUPPORT); 2197 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 2198 DRM_MODE_CONNECTOR_SVIDEO, 2199 &ddc_i2c, 2200 CONNECTOR_OBJECT_ID_SVIDEO, 2201 &hpd); 2202 break; 2203 default: 2204 DRM_INFO("Connector table: %d (invalid)\n", 2205 rdev->mode_info.connector_table); 2206 return false; 2207 } 2208 2209 radeon_link_encoder_connector(dev); 2210 2211 return true; 2212 } 2213 2214 static bool radeon_apply_legacy_quirks(struct drm_device *dev, 2215 int bios_index, 2216 enum radeon_combios_connector 2217 *legacy_connector, 2218 struct radeon_i2c_bus_rec *ddc_i2c, 2219 struct radeon_hpd *hpd) 2220 { 2221 2222 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, 2223 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ 2224 if (dev->pdev->device == 0x515e && 2225 dev->pdev->subsystem_vendor == 0x1014) { 2226 if (*legacy_connector == CONNECTOR_CRT_LEGACY && 2227 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) 2228 return false; 2229 } 2230 2231 /* X300 card with extra non-existent DVI port */ 2232 if (dev->pdev->device == 0x5B60 && 2233 dev->pdev->subsystem_vendor == 0x17af && 2234 dev->pdev->subsystem_device == 0x201e && bios_index == 2) { 2235 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY) 2236 return false; 2237 } 2238 2239 return true; 2240 } 2241 2242 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev) 2243 { 2244 /* Acer 5102 has non-existent TV port */ 2245 if (dev->pdev->device == 0x5975 && 2246 dev->pdev->subsystem_vendor == 0x1025 && 2247 dev->pdev->subsystem_device == 0x009f) 2248 return false; 2249 2250 /* HP dc5750 has non-existent TV port */ 2251 if (dev->pdev->device == 0x5974 && 2252 dev->pdev->subsystem_vendor == 0x103c && 2253 dev->pdev->subsystem_device == 0x280a) 2254 return false; 2255 2256 /* MSI S270 has non-existent TV port */ 2257 if (dev->pdev->device == 0x5955 && 2258 dev->pdev->subsystem_vendor == 0x1462 && 2259 dev->pdev->subsystem_device == 0x0131) 2260 return false; 2261 2262 return true; 2263 } 2264 2265 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d) 2266 { 2267 struct radeon_device *rdev = dev->dev_private; 2268 uint32_t ext_tmds_info; 2269 2270 if (rdev->flags & RADEON_IS_IGP) { 2271 if (is_dvi_d) 2272 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 2273 else 2274 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2275 } 2276 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 2277 if (ext_tmds_info) { 2278 uint8_t rev = RBIOS8(ext_tmds_info); 2279 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5); 2280 if (rev >= 3) { 2281 if (is_dvi_d) 2282 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 2283 else 2284 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 2285 } else { 2286 if (flags & 1) { 2287 if (is_dvi_d) 2288 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 2289 else 2290 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 2291 } 2292 } 2293 } 2294 if (is_dvi_d) 2295 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 2296 else 2297 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2298 } 2299 2300 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) 2301 { 2302 struct radeon_device *rdev = dev->dev_private; 2303 uint32_t conn_info, entry, devices; 2304 uint16_t tmp, connector_object_id; 2305 enum radeon_combios_ddc ddc_type; 2306 enum radeon_combios_connector connector; 2307 int i = 0; 2308 struct radeon_i2c_bus_rec ddc_i2c; 2309 struct radeon_hpd hpd; 2310 2311 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE); 2312 if (conn_info) { 2313 for (i = 0; i < 4; i++) { 2314 entry = conn_info + 2 + i * 2; 2315 2316 if (!RBIOS16(entry)) 2317 break; 2318 2319 tmp = RBIOS16(entry); 2320 2321 connector = (tmp >> 12) & 0xf; 2322 2323 ddc_type = (tmp >> 8) & 0xf; 2324 if (ddc_type == 5) 2325 ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev); 2326 else 2327 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0); 2328 2329 switch (connector) { 2330 case CONNECTOR_PROPRIETARY_LEGACY: 2331 case CONNECTOR_DVI_I_LEGACY: 2332 case CONNECTOR_DVI_D_LEGACY: 2333 if ((tmp >> 4) & 0x1) 2334 hpd.hpd = RADEON_HPD_2; 2335 else 2336 hpd.hpd = RADEON_HPD_1; 2337 break; 2338 default: 2339 hpd.hpd = RADEON_HPD_NONE; 2340 break; 2341 } 2342 2343 if (!radeon_apply_legacy_quirks(dev, i, &connector, 2344 &ddc_i2c, &hpd)) 2345 continue; 2346 2347 switch (connector) { 2348 case CONNECTOR_PROPRIETARY_LEGACY: 2349 if ((tmp >> 4) & 0x1) 2350 devices = ATOM_DEVICE_DFP2_SUPPORT; 2351 else 2352 devices = ATOM_DEVICE_DFP1_SUPPORT; 2353 radeon_add_legacy_encoder(dev, 2354 radeon_get_encoder_enum 2355 (dev, devices, 0), 2356 devices); 2357 radeon_add_legacy_connector(dev, i, devices, 2358 legacy_connector_convert 2359 [connector], 2360 &ddc_i2c, 2361 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 2362 &hpd); 2363 break; 2364 case CONNECTOR_CRT_LEGACY: 2365 if (tmp & 0x1) { 2366 devices = ATOM_DEVICE_CRT2_SUPPORT; 2367 radeon_add_legacy_encoder(dev, 2368 radeon_get_encoder_enum 2369 (dev, 2370 ATOM_DEVICE_CRT2_SUPPORT, 2371 2), 2372 ATOM_DEVICE_CRT2_SUPPORT); 2373 } else { 2374 devices = ATOM_DEVICE_CRT1_SUPPORT; 2375 radeon_add_legacy_encoder(dev, 2376 radeon_get_encoder_enum 2377 (dev, 2378 ATOM_DEVICE_CRT1_SUPPORT, 2379 1), 2380 ATOM_DEVICE_CRT1_SUPPORT); 2381 } 2382 radeon_add_legacy_connector(dev, 2383 i, 2384 devices, 2385 legacy_connector_convert 2386 [connector], 2387 &ddc_i2c, 2388 CONNECTOR_OBJECT_ID_VGA, 2389 &hpd); 2390 break; 2391 case CONNECTOR_DVI_I_LEGACY: 2392 devices = 0; 2393 if (tmp & 0x1) { 2394 devices |= ATOM_DEVICE_CRT2_SUPPORT; 2395 radeon_add_legacy_encoder(dev, 2396 radeon_get_encoder_enum 2397 (dev, 2398 ATOM_DEVICE_CRT2_SUPPORT, 2399 2), 2400 ATOM_DEVICE_CRT2_SUPPORT); 2401 } else { 2402 devices |= ATOM_DEVICE_CRT1_SUPPORT; 2403 radeon_add_legacy_encoder(dev, 2404 radeon_get_encoder_enum 2405 (dev, 2406 ATOM_DEVICE_CRT1_SUPPORT, 2407 1), 2408 ATOM_DEVICE_CRT1_SUPPORT); 2409 } 2410 /* RV100 board with external TDMS bit mis-set. 2411 * Actually uses internal TMDS, clear the bit. 2412 */ 2413 if (dev->pdev->device == 0x5159 && 2414 dev->pdev->subsystem_vendor == 0x1014 && 2415 dev->pdev->subsystem_device == 0x029A) { 2416 tmp &= ~(1 << 4); 2417 } 2418 if ((tmp >> 4) & 0x1) { 2419 devices |= ATOM_DEVICE_DFP2_SUPPORT; 2420 radeon_add_legacy_encoder(dev, 2421 radeon_get_encoder_enum 2422 (dev, 2423 ATOM_DEVICE_DFP2_SUPPORT, 2424 0), 2425 ATOM_DEVICE_DFP2_SUPPORT); 2426 connector_object_id = combios_check_dl_dvi(dev, 0); 2427 } else { 2428 devices |= ATOM_DEVICE_DFP1_SUPPORT; 2429 radeon_add_legacy_encoder(dev, 2430 radeon_get_encoder_enum 2431 (dev, 2432 ATOM_DEVICE_DFP1_SUPPORT, 2433 0), 2434 ATOM_DEVICE_DFP1_SUPPORT); 2435 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2436 } 2437 radeon_add_legacy_connector(dev, 2438 i, 2439 devices, 2440 legacy_connector_convert 2441 [connector], 2442 &ddc_i2c, 2443 connector_object_id, 2444 &hpd); 2445 break; 2446 case CONNECTOR_DVI_D_LEGACY: 2447 if ((tmp >> 4) & 0x1) { 2448 devices = ATOM_DEVICE_DFP2_SUPPORT; 2449 connector_object_id = combios_check_dl_dvi(dev, 1); 2450 } else { 2451 devices = ATOM_DEVICE_DFP1_SUPPORT; 2452 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2453 } 2454 radeon_add_legacy_encoder(dev, 2455 radeon_get_encoder_enum 2456 (dev, devices, 0), 2457 devices); 2458 radeon_add_legacy_connector(dev, i, devices, 2459 legacy_connector_convert 2460 [connector], 2461 &ddc_i2c, 2462 connector_object_id, 2463 &hpd); 2464 break; 2465 case CONNECTOR_CTV_LEGACY: 2466 case CONNECTOR_STV_LEGACY: 2467 radeon_add_legacy_encoder(dev, 2468 radeon_get_encoder_enum 2469 (dev, 2470 ATOM_DEVICE_TV1_SUPPORT, 2471 2), 2472 ATOM_DEVICE_TV1_SUPPORT); 2473 radeon_add_legacy_connector(dev, i, 2474 ATOM_DEVICE_TV1_SUPPORT, 2475 legacy_connector_convert 2476 [connector], 2477 &ddc_i2c, 2478 CONNECTOR_OBJECT_ID_SVIDEO, 2479 &hpd); 2480 break; 2481 default: 2482 DRM_ERROR("Unknown connector type: %d\n", 2483 connector); 2484 continue; 2485 } 2486 2487 } 2488 } else { 2489 uint16_t tmds_info = 2490 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 2491 if (tmds_info) { 2492 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n"); 2493 2494 radeon_add_legacy_encoder(dev, 2495 radeon_get_encoder_enum(dev, 2496 ATOM_DEVICE_CRT1_SUPPORT, 2497 1), 2498 ATOM_DEVICE_CRT1_SUPPORT); 2499 radeon_add_legacy_encoder(dev, 2500 radeon_get_encoder_enum(dev, 2501 ATOM_DEVICE_DFP1_SUPPORT, 2502 0), 2503 ATOM_DEVICE_DFP1_SUPPORT); 2504 2505 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2506 hpd.hpd = RADEON_HPD_1; 2507 radeon_add_legacy_connector(dev, 2508 0, 2509 ATOM_DEVICE_CRT1_SUPPORT | 2510 ATOM_DEVICE_DFP1_SUPPORT, 2511 DRM_MODE_CONNECTOR_DVII, 2512 &ddc_i2c, 2513 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2514 &hpd); 2515 } else { 2516 uint16_t crt_info = 2517 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 2518 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n"); 2519 if (crt_info) { 2520 radeon_add_legacy_encoder(dev, 2521 radeon_get_encoder_enum(dev, 2522 ATOM_DEVICE_CRT1_SUPPORT, 2523 1), 2524 ATOM_DEVICE_CRT1_SUPPORT); 2525 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2526 hpd.hpd = RADEON_HPD_NONE; 2527 radeon_add_legacy_connector(dev, 2528 0, 2529 ATOM_DEVICE_CRT1_SUPPORT, 2530 DRM_MODE_CONNECTOR_VGA, 2531 &ddc_i2c, 2532 CONNECTOR_OBJECT_ID_VGA, 2533 &hpd); 2534 } else { 2535 DRM_DEBUG_KMS("No connector info found\n"); 2536 return false; 2537 } 2538 } 2539 } 2540 2541 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) { 2542 uint16_t lcd_info = 2543 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 2544 if (lcd_info) { 2545 uint16_t lcd_ddc_info = 2546 combios_get_table_offset(dev, 2547 COMBIOS_LCD_DDC_INFO_TABLE); 2548 2549 radeon_add_legacy_encoder(dev, 2550 radeon_get_encoder_enum(dev, 2551 ATOM_DEVICE_LCD1_SUPPORT, 2552 0), 2553 ATOM_DEVICE_LCD1_SUPPORT); 2554 2555 if (lcd_ddc_info) { 2556 ddc_type = RBIOS8(lcd_ddc_info + 2); 2557 switch (ddc_type) { 2558 case DDC_LCD: 2559 ddc_i2c = 2560 combios_setup_i2c_bus(rdev, 2561 DDC_LCD, 2562 RBIOS32(lcd_ddc_info + 3), 2563 RBIOS32(lcd_ddc_info + 7)); 2564 radeon_i2c_add(rdev, &ddc_i2c, "LCD"); 2565 break; 2566 case DDC_GPIO: 2567 ddc_i2c = 2568 combios_setup_i2c_bus(rdev, 2569 DDC_GPIO, 2570 RBIOS32(lcd_ddc_info + 3), 2571 RBIOS32(lcd_ddc_info + 7)); 2572 radeon_i2c_add(rdev, &ddc_i2c, "LCD"); 2573 break; 2574 default: 2575 ddc_i2c = 2576 combios_setup_i2c_bus(rdev, ddc_type, 0, 0); 2577 break; 2578 } 2579 DRM_DEBUG_KMS("LCD DDC Info Table found!\n"); 2580 } else 2581 ddc_i2c.valid = false; 2582 2583 hpd.hpd = RADEON_HPD_NONE; 2584 radeon_add_legacy_connector(dev, 2585 5, 2586 ATOM_DEVICE_LCD1_SUPPORT, 2587 DRM_MODE_CONNECTOR_LVDS, 2588 &ddc_i2c, 2589 CONNECTOR_OBJECT_ID_LVDS, 2590 &hpd); 2591 } 2592 } 2593 2594 /* check TV table */ 2595 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 2596 uint32_t tv_info = 2597 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 2598 if (tv_info) { 2599 if (RBIOS8(tv_info + 6) == 'T') { 2600 if (radeon_apply_legacy_tv_quirks(dev)) { 2601 hpd.hpd = RADEON_HPD_NONE; 2602 ddc_i2c.valid = false; 2603 radeon_add_legacy_encoder(dev, 2604 radeon_get_encoder_enum 2605 (dev, 2606 ATOM_DEVICE_TV1_SUPPORT, 2607 2), 2608 ATOM_DEVICE_TV1_SUPPORT); 2609 radeon_add_legacy_connector(dev, 6, 2610 ATOM_DEVICE_TV1_SUPPORT, 2611 DRM_MODE_CONNECTOR_SVIDEO, 2612 &ddc_i2c, 2613 CONNECTOR_OBJECT_ID_SVIDEO, 2614 &hpd); 2615 } 2616 } 2617 } 2618 } 2619 2620 radeon_link_encoder_connector(dev); 2621 2622 return true; 2623 } 2624 2625 static const char *thermal_controller_names[] = { 2626 "NONE", 2627 "lm63", 2628 "adm1032", 2629 }; 2630 2631 void radeon_combios_get_power_modes(struct radeon_device *rdev) 2632 { 2633 struct drm_device *dev = rdev->ddev; 2634 u16 offset, misc, misc2 = 0; 2635 u8 rev, blocks, tmp; 2636 int state_index = 0; 2637 struct radeon_i2c_bus_rec i2c_bus; 2638 2639 rdev->pm.default_power_state_index = -1; 2640 2641 /* allocate 2 power states */ 2642 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL); 2643 if (rdev->pm.power_state) { 2644 /* allocate 1 clock mode per state */ 2645 rdev->pm.power_state[0].clock_info = 2646 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); 2647 rdev->pm.power_state[1].clock_info = 2648 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); 2649 if (!rdev->pm.power_state[0].clock_info || 2650 !rdev->pm.power_state[1].clock_info) 2651 goto pm_failed; 2652 } else 2653 goto pm_failed; 2654 2655 /* check for a thermal chip */ 2656 offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE); 2657 if (offset) { 2658 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0; 2659 2660 rev = RBIOS8(offset); 2661 2662 if (rev == 0) { 2663 thermal_controller = RBIOS8(offset + 3); 2664 gpio = RBIOS8(offset + 4) & 0x3f; 2665 i2c_addr = RBIOS8(offset + 5); 2666 } else if (rev == 1) { 2667 thermal_controller = RBIOS8(offset + 4); 2668 gpio = RBIOS8(offset + 5) & 0x3f; 2669 i2c_addr = RBIOS8(offset + 6); 2670 } else if (rev == 2) { 2671 thermal_controller = RBIOS8(offset + 4); 2672 gpio = RBIOS8(offset + 5) & 0x3f; 2673 i2c_addr = RBIOS8(offset + 6); 2674 clk_bit = RBIOS8(offset + 0xa); 2675 data_bit = RBIOS8(offset + 0xb); 2676 } 2677 if ((thermal_controller > 0) && (thermal_controller < 3)) { 2678 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 2679 thermal_controller_names[thermal_controller], 2680 i2c_addr >> 1); 2681 if (gpio == DDC_LCD) { 2682 /* MM i2c */ 2683 i2c_bus.valid = true; 2684 i2c_bus.hw_capable = true; 2685 i2c_bus.mm_i2c = true; 2686 i2c_bus.i2c_id = 0xa0; 2687 } else if (gpio == DDC_GPIO) 2688 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit); 2689 else 2690 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); 2691 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2692 if (rdev->pm.i2c_bus) { 2693 struct i2c_board_info info = { }; 2694 const char *name = thermal_controller_names[thermal_controller]; 2695 info.addr = i2c_addr >> 1; 2696 strlcpy(info.type, name, sizeof(info.type)); 2697 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); 2698 } 2699 } 2700 } else { 2701 /* boards with a thermal chip, but no overdrive table */ 2702 2703 /* Asus 9600xt has an f75375 on the monid bus */ 2704 if ((dev->pdev->device == 0x4152) && 2705 (dev->pdev->subsystem_vendor == 0x1043) && 2706 (dev->pdev->subsystem_device == 0xc002)) { 2707 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 2708 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2709 if (rdev->pm.i2c_bus) { 2710 struct i2c_board_info info = { }; 2711 const char *name = "f75375"; 2712 info.addr = 0x28; 2713 strlcpy(info.type, name, sizeof(info.type)); 2714 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); 2715 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 2716 name, info.addr); 2717 } 2718 } 2719 } 2720 2721 if (rdev->flags & RADEON_IS_MOBILITY) { 2722 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE); 2723 if (offset) { 2724 rev = RBIOS8(offset); 2725 blocks = RBIOS8(offset + 0x2); 2726 /* power mode 0 tends to be the only valid one */ 2727 rdev->pm.power_state[state_index].num_clock_modes = 1; 2728 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2); 2729 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6); 2730 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2731 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2732 goto default_mode; 2733 rdev->pm.power_state[state_index].type = 2734 POWER_STATE_TYPE_BATTERY; 2735 misc = RBIOS16(offset + 0x5 + 0x0); 2736 if (rev > 4) 2737 misc2 = RBIOS16(offset + 0x5 + 0xe); 2738 rdev->pm.power_state[state_index].misc = misc; 2739 rdev->pm.power_state[state_index].misc2 = misc2; 2740 if (misc & 0x4) { 2741 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO; 2742 if (misc & 0x8) 2743 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2744 true; 2745 else 2746 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2747 false; 2748 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true; 2749 if (rev < 6) { 2750 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = 2751 RBIOS16(offset + 0x5 + 0xb) * 4; 2752 tmp = RBIOS8(offset + 0x5 + 0xd); 2753 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); 2754 } else { 2755 u8 entries = RBIOS8(offset + 0x5 + 0xb); 2756 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc); 2757 if (entries && voltage_table_offset) { 2758 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = 2759 RBIOS16(voltage_table_offset) * 4; 2760 tmp = RBIOS8(voltage_table_offset + 0x2); 2761 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); 2762 } else 2763 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false; 2764 } 2765 switch ((misc2 & 0x700) >> 8) { 2766 case 0: 2767 default: 2768 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0; 2769 break; 2770 case 1: 2771 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33; 2772 break; 2773 case 2: 2774 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66; 2775 break; 2776 case 3: 2777 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99; 2778 break; 2779 case 4: 2780 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132; 2781 break; 2782 } 2783 } else 2784 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2785 if (rev > 6) 2786 rdev->pm.power_state[state_index].pcie_lanes = 2787 RBIOS8(offset + 0x5 + 0x10); 2788 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2789 state_index++; 2790 } else { 2791 /* XXX figure out some good default low power mode for mobility cards w/out power tables */ 2792 } 2793 } else { 2794 /* XXX figure out some good default low power mode for desktop cards */ 2795 } 2796 2797 default_mode: 2798 /* add the default mode */ 2799 rdev->pm.power_state[state_index].type = 2800 POWER_STATE_TYPE_DEFAULT; 2801 rdev->pm.power_state[state_index].num_clock_modes = 1; 2802 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; 2803 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; 2804 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; 2805 if ((state_index > 0) && 2806 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO)) 2807 rdev->pm.power_state[state_index].clock_info[0].voltage = 2808 rdev->pm.power_state[0].clock_info[0].voltage; 2809 else 2810 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2811 rdev->pm.power_state[state_index].pcie_lanes = 16; 2812 rdev->pm.power_state[state_index].flags = 0; 2813 rdev->pm.default_power_state_index = state_index; 2814 rdev->pm.num_power_states = state_index + 1; 2815 2816 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2817 rdev->pm.current_clock_mode_index = 0; 2818 return; 2819 2820 pm_failed: 2821 rdev->pm.default_power_state_index = state_index; 2822 rdev->pm.num_power_states = 0; 2823 2824 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2825 rdev->pm.current_clock_mode_index = 0; 2826 } 2827 2828 void radeon_external_tmds_setup(struct drm_encoder *encoder) 2829 { 2830 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2831 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2832 2833 if (!tmds) 2834 return; 2835 2836 switch (tmds->dvo_chip) { 2837 case DVO_SIL164: 2838 /* sil 164 */ 2839 radeon_i2c_put_byte(tmds->i2c_bus, 2840 tmds->slave_addr, 2841 0x08, 0x30); 2842 radeon_i2c_put_byte(tmds->i2c_bus, 2843 tmds->slave_addr, 2844 0x09, 0x00); 2845 radeon_i2c_put_byte(tmds->i2c_bus, 2846 tmds->slave_addr, 2847 0x0a, 0x90); 2848 radeon_i2c_put_byte(tmds->i2c_bus, 2849 tmds->slave_addr, 2850 0x0c, 0x89); 2851 radeon_i2c_put_byte(tmds->i2c_bus, 2852 tmds->slave_addr, 2853 0x08, 0x3b); 2854 break; 2855 case DVO_SIL1178: 2856 /* sil 1178 - untested */ 2857 /* 2858 * 0x0f, 0x44 2859 * 0x0f, 0x4c 2860 * 0x0e, 0x01 2861 * 0x0a, 0x80 2862 * 0x09, 0x30 2863 * 0x0c, 0xc9 2864 * 0x0d, 0x70 2865 * 0x08, 0x32 2866 * 0x08, 0x33 2867 */ 2868 break; 2869 default: 2870 break; 2871 } 2872 2873 } 2874 2875 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder) 2876 { 2877 struct drm_device *dev = encoder->dev; 2878 struct radeon_device *rdev = dev->dev_private; 2879 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2880 uint16_t offset; 2881 uint8_t blocks, slave_addr, rev; 2882 uint32_t index, id; 2883 uint32_t reg, val, and_mask, or_mask; 2884 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2885 2886 if (!tmds) 2887 return false; 2888 2889 if (rdev->flags & RADEON_IS_IGP) { 2890 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE); 2891 rev = RBIOS8(offset); 2892 if (offset) { 2893 rev = RBIOS8(offset); 2894 if (rev > 1) { 2895 blocks = RBIOS8(offset + 3); 2896 index = offset + 4; 2897 while (blocks > 0) { 2898 id = RBIOS16(index); 2899 index += 2; 2900 switch (id >> 13) { 2901 case 0: 2902 reg = (id & 0x1fff) * 4; 2903 val = RBIOS32(index); 2904 index += 4; 2905 WREG32(reg, val); 2906 break; 2907 case 2: 2908 reg = (id & 0x1fff) * 4; 2909 and_mask = RBIOS32(index); 2910 index += 4; 2911 or_mask = RBIOS32(index); 2912 index += 4; 2913 val = RREG32(reg); 2914 val = (val & and_mask) | or_mask; 2915 WREG32(reg, val); 2916 break; 2917 case 3: 2918 val = RBIOS16(index); 2919 index += 2; 2920 udelay(val); 2921 break; 2922 case 4: 2923 val = RBIOS16(index); 2924 index += 2; 2925 mdelay(val); 2926 break; 2927 case 6: 2928 slave_addr = id & 0xff; 2929 slave_addr >>= 1; /* 7 bit addressing */ 2930 index++; 2931 reg = RBIOS8(index); 2932 index++; 2933 val = RBIOS8(index); 2934 index++; 2935 radeon_i2c_put_byte(tmds->i2c_bus, 2936 slave_addr, 2937 reg, val); 2938 break; 2939 default: 2940 DRM_ERROR("Unknown id %d\n", id >> 13); 2941 break; 2942 } 2943 blocks--; 2944 } 2945 return true; 2946 } 2947 } 2948 } else { 2949 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 2950 if (offset) { 2951 index = offset + 10; 2952 id = RBIOS16(index); 2953 while (id != 0xffff) { 2954 index += 2; 2955 switch (id >> 13) { 2956 case 0: 2957 reg = (id & 0x1fff) * 4; 2958 val = RBIOS32(index); 2959 WREG32(reg, val); 2960 break; 2961 case 2: 2962 reg = (id & 0x1fff) * 4; 2963 and_mask = RBIOS32(index); 2964 index += 4; 2965 or_mask = RBIOS32(index); 2966 index += 4; 2967 val = RREG32(reg); 2968 val = (val & and_mask) | or_mask; 2969 WREG32(reg, val); 2970 break; 2971 case 4: 2972 val = RBIOS16(index); 2973 index += 2; 2974 udelay(val); 2975 break; 2976 case 5: 2977 reg = id & 0x1fff; 2978 and_mask = RBIOS32(index); 2979 index += 4; 2980 or_mask = RBIOS32(index); 2981 index += 4; 2982 val = RREG32_PLL(reg); 2983 val = (val & and_mask) | or_mask; 2984 WREG32_PLL(reg, val); 2985 break; 2986 case 6: 2987 reg = id & 0x1fff; 2988 val = RBIOS8(index); 2989 index += 1; 2990 radeon_i2c_put_byte(tmds->i2c_bus, 2991 tmds->slave_addr, 2992 reg, val); 2993 break; 2994 default: 2995 DRM_ERROR("Unknown id %d\n", id >> 13); 2996 break; 2997 } 2998 id = RBIOS16(index); 2999 } 3000 return true; 3001 } 3002 } 3003 return false; 3004 } 3005 3006 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset) 3007 { 3008 struct radeon_device *rdev = dev->dev_private; 3009 3010 if (offset) { 3011 while (RBIOS16(offset)) { 3012 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13); 3013 uint32_t addr = (RBIOS16(offset) & 0x1fff); 3014 uint32_t val, and_mask, or_mask; 3015 uint32_t tmp; 3016 3017 offset += 2; 3018 switch (cmd) { 3019 case 0: 3020 val = RBIOS32(offset); 3021 offset += 4; 3022 WREG32(addr, val); 3023 break; 3024 case 1: 3025 val = RBIOS32(offset); 3026 offset += 4; 3027 WREG32(addr, val); 3028 break; 3029 case 2: 3030 and_mask = RBIOS32(offset); 3031 offset += 4; 3032 or_mask = RBIOS32(offset); 3033 offset += 4; 3034 tmp = RREG32(addr); 3035 tmp &= and_mask; 3036 tmp |= or_mask; 3037 WREG32(addr, tmp); 3038 break; 3039 case 3: 3040 and_mask = RBIOS32(offset); 3041 offset += 4; 3042 or_mask = RBIOS32(offset); 3043 offset += 4; 3044 tmp = RREG32(addr); 3045 tmp &= and_mask; 3046 tmp |= or_mask; 3047 WREG32(addr, tmp); 3048 break; 3049 case 4: 3050 val = RBIOS16(offset); 3051 offset += 2; 3052 udelay(val); 3053 break; 3054 case 5: 3055 val = RBIOS16(offset); 3056 offset += 2; 3057 switch (addr) { 3058 case 8: 3059 while (val--) { 3060 if (! 3061 (RREG32_PLL 3062 (RADEON_CLK_PWRMGT_CNTL) & 3063 RADEON_MC_BUSY)) 3064 break; 3065 } 3066 break; 3067 case 9: 3068 while (val--) { 3069 if ((RREG32(RADEON_MC_STATUS) & 3070 RADEON_MC_IDLE)) 3071 break; 3072 } 3073 break; 3074 default: 3075 break; 3076 } 3077 break; 3078 default: 3079 break; 3080 } 3081 } 3082 } 3083 } 3084 3085 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset) 3086 { 3087 struct radeon_device *rdev = dev->dev_private; 3088 3089 if (offset) { 3090 while (RBIOS8(offset)) { 3091 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6); 3092 uint8_t addr = (RBIOS8(offset) & 0x3f); 3093 uint32_t val, shift, tmp; 3094 uint32_t and_mask, or_mask; 3095 3096 offset++; 3097 switch (cmd) { 3098 case 0: 3099 val = RBIOS32(offset); 3100 offset += 4; 3101 WREG32_PLL(addr, val); 3102 break; 3103 case 1: 3104 shift = RBIOS8(offset) * 8; 3105 offset++; 3106 and_mask = RBIOS8(offset) << shift; 3107 and_mask |= ~(0xff << shift); 3108 offset++; 3109 or_mask = RBIOS8(offset) << shift; 3110 offset++; 3111 tmp = RREG32_PLL(addr); 3112 tmp &= and_mask; 3113 tmp |= or_mask; 3114 WREG32_PLL(addr, tmp); 3115 break; 3116 case 2: 3117 case 3: 3118 tmp = 1000; 3119 switch (addr) { 3120 case 1: 3121 udelay(150); 3122 break; 3123 case 2: 3124 mdelay(1); 3125 break; 3126 case 3: 3127 while (tmp--) { 3128 if (! 3129 (RREG32_PLL 3130 (RADEON_CLK_PWRMGT_CNTL) & 3131 RADEON_MC_BUSY)) 3132 break; 3133 } 3134 break; 3135 case 4: 3136 while (tmp--) { 3137 if (RREG32_PLL 3138 (RADEON_CLK_PWRMGT_CNTL) & 3139 RADEON_DLL_READY) 3140 break; 3141 } 3142 break; 3143 case 5: 3144 tmp = 3145 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); 3146 if (tmp & RADEON_CG_NO1_DEBUG_0) { 3147 #if 0 3148 uint32_t mclk_cntl = 3149 RREG32_PLL 3150 (RADEON_MCLK_CNTL); 3151 mclk_cntl &= 0xffff0000; 3152 /*mclk_cntl |= 0x00001111;*//* ??? */ 3153 WREG32_PLL(RADEON_MCLK_CNTL, 3154 mclk_cntl); 3155 mdelay(10); 3156 #endif 3157 WREG32_PLL 3158 (RADEON_CLK_PWRMGT_CNTL, 3159 tmp & 3160 ~RADEON_CG_NO1_DEBUG_0); 3161 mdelay(10); 3162 } 3163 break; 3164 default: 3165 break; 3166 } 3167 break; 3168 default: 3169 break; 3170 } 3171 } 3172 } 3173 } 3174 3175 static void combios_parse_ram_reset_table(struct drm_device *dev, 3176 uint16_t offset) 3177 { 3178 struct radeon_device *rdev = dev->dev_private; 3179 uint32_t tmp; 3180 3181 if (offset) { 3182 uint8_t val = RBIOS8(offset); 3183 while (val != 0xff) { 3184 offset++; 3185 3186 if (val == 0x0f) { 3187 uint32_t channel_complete_mask; 3188 3189 if (ASIC_IS_R300(rdev)) 3190 channel_complete_mask = 3191 R300_MEM_PWRUP_COMPLETE; 3192 else 3193 channel_complete_mask = 3194 RADEON_MEM_PWRUP_COMPLETE; 3195 tmp = 20000; 3196 while (tmp--) { 3197 if ((RREG32(RADEON_MEM_STR_CNTL) & 3198 channel_complete_mask) == 3199 channel_complete_mask) 3200 break; 3201 } 3202 } else { 3203 uint32_t or_mask = RBIOS16(offset); 3204 offset += 2; 3205 3206 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 3207 tmp &= RADEON_SDRAM_MODE_MASK; 3208 tmp |= or_mask; 3209 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 3210 3211 or_mask = val << 24; 3212 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 3213 tmp &= RADEON_B3MEM_RESET_MASK; 3214 tmp |= or_mask; 3215 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 3216 } 3217 val = RBIOS8(offset); 3218 } 3219 } 3220 } 3221 3222 static uint32_t combios_detect_ram(struct drm_device *dev, int ram, 3223 int mem_addr_mapping) 3224 { 3225 struct radeon_device *rdev = dev->dev_private; 3226 uint32_t mem_cntl; 3227 uint32_t mem_size; 3228 uint32_t addr = 0; 3229 3230 mem_cntl = RREG32(RADEON_MEM_CNTL); 3231 if (mem_cntl & RV100_HALF_MODE) 3232 ram /= 2; 3233 mem_size = ram; 3234 mem_cntl &= ~(0xff << 8); 3235 mem_cntl |= (mem_addr_mapping & 0xff) << 8; 3236 WREG32(RADEON_MEM_CNTL, mem_cntl); 3237 RREG32(RADEON_MEM_CNTL); 3238 3239 /* sdram reset ? */ 3240 3241 /* something like this???? */ 3242 while (ram--) { 3243 addr = ram * 1024 * 1024; 3244 /* write to each page */ 3245 WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef); 3246 /* read back and verify */ 3247 if (RREG32_IDX((addr) | RADEON_MM_APER) != 0xdeadbeef) 3248 return 0; 3249 } 3250 3251 return mem_size; 3252 } 3253 3254 static void combios_write_ram_size(struct drm_device *dev) 3255 { 3256 struct radeon_device *rdev = dev->dev_private; 3257 uint8_t rev; 3258 uint16_t offset; 3259 uint32_t mem_size = 0; 3260 uint32_t mem_cntl = 0; 3261 3262 /* should do something smarter here I guess... */ 3263 if (rdev->flags & RADEON_IS_IGP) 3264 return; 3265 3266 /* first check detected mem table */ 3267 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE); 3268 if (offset) { 3269 rev = RBIOS8(offset); 3270 if (rev < 3) { 3271 mem_cntl = RBIOS32(offset + 1); 3272 mem_size = RBIOS16(offset + 5); 3273 if ((rdev->family < CHIP_R200) && 3274 !ASIC_IS_RN50(rdev)) 3275 WREG32(RADEON_MEM_CNTL, mem_cntl); 3276 } 3277 } 3278 3279 if (!mem_size) { 3280 offset = 3281 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 3282 if (offset) { 3283 rev = RBIOS8(offset - 1); 3284 if (rev < 1) { 3285 if ((rdev->family < CHIP_R200) 3286 && !ASIC_IS_RN50(rdev)) { 3287 int ram = 0; 3288 int mem_addr_mapping = 0; 3289 3290 while (RBIOS8(offset)) { 3291 ram = RBIOS8(offset); 3292 mem_addr_mapping = 3293 RBIOS8(offset + 1); 3294 if (mem_addr_mapping != 0x25) 3295 ram *= 2; 3296 mem_size = 3297 combios_detect_ram(dev, ram, 3298 mem_addr_mapping); 3299 if (mem_size) 3300 break; 3301 offset += 2; 3302 } 3303 } else 3304 mem_size = RBIOS8(offset); 3305 } else { 3306 mem_size = RBIOS8(offset); 3307 mem_size *= 2; /* convert to MB */ 3308 } 3309 } 3310 } 3311 3312 mem_size *= (1024 * 1024); /* convert to bytes */ 3313 WREG32(RADEON_CONFIG_MEMSIZE, mem_size); 3314 } 3315 3316 void radeon_combios_asic_init(struct drm_device *dev) 3317 { 3318 struct radeon_device *rdev = dev->dev_private; 3319 uint16_t table; 3320 3321 /* port hardcoded mac stuff from radeonfb */ 3322 if (rdev->bios == NULL) 3323 return; 3324 3325 /* ASIC INIT 1 */ 3326 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE); 3327 if (table) 3328 combios_parse_mmio_table(dev, table); 3329 3330 /* PLL INIT */ 3331 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE); 3332 if (table) 3333 combios_parse_pll_table(dev, table); 3334 3335 /* ASIC INIT 2 */ 3336 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE); 3337 if (table) 3338 combios_parse_mmio_table(dev, table); 3339 3340 if (!(rdev->flags & RADEON_IS_IGP)) { 3341 /* ASIC INIT 4 */ 3342 table = 3343 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE); 3344 if (table) 3345 combios_parse_mmio_table(dev, table); 3346 3347 /* RAM RESET */ 3348 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE); 3349 if (table) 3350 combios_parse_ram_reset_table(dev, table); 3351 3352 /* ASIC INIT 3 */ 3353 table = 3354 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE); 3355 if (table) 3356 combios_parse_mmio_table(dev, table); 3357 3358 /* write CONFIG_MEMSIZE */ 3359 combios_write_ram_size(dev); 3360 } 3361 3362 /* quirk for rs4xx HP nx6125 laptop to make it resume 3363 * - it hangs on resume inside the dynclk 1 table. 3364 */ 3365 if (rdev->family == CHIP_RS480 && 3366 rdev->pdev->subsystem_vendor == 0x103c && 3367 rdev->pdev->subsystem_device == 0x308b) 3368 return; 3369 3370 /* quirk for rs4xx HP dv5000 laptop to make it resume 3371 * - it hangs on resume inside the dynclk 1 table. 3372 */ 3373 if (rdev->family == CHIP_RS480 && 3374 rdev->pdev->subsystem_vendor == 0x103c && 3375 rdev->pdev->subsystem_device == 0x30a4) 3376 return; 3377 3378 /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume 3379 * - it hangs on resume inside the dynclk 1 table. 3380 */ 3381 if (rdev->family == CHIP_RS480 && 3382 rdev->pdev->subsystem_vendor == 0x103c && 3383 rdev->pdev->subsystem_device == 0x30ae) 3384 return; 3385 3386 /* quirk for rs4xx HP Compaq dc5750 Small Form Factor to make it resume 3387 * - it hangs on resume inside the dynclk 1 table. 3388 */ 3389 if (rdev->family == CHIP_RS480 && 3390 rdev->pdev->subsystem_vendor == 0x103c && 3391 rdev->pdev->subsystem_device == 0x280a) 3392 return; 3393 /* quirk for rs4xx Toshiba Sattellite L20-183 latop to make it resume 3394 * - it hangs on resume inside the dynclk 1 table. 3395 */ 3396 if (rdev->family == CHIP_RS400 && 3397 rdev->pdev->subsystem_vendor == 0x1179 && 3398 rdev->pdev->subsystem_device == 0xff31) 3399 return; 3400 3401 /* DYN CLK 1 */ 3402 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); 3403 if (table) 3404 combios_parse_pll_table(dev, table); 3405 3406 } 3407 3408 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev) 3409 { 3410 struct radeon_device *rdev = dev->dev_private; 3411 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch; 3412 3413 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 3414 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3415 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH); 3416 3417 /* let the bios control the backlight */ 3418 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN; 3419 3420 /* tell the bios not to handle mode switching */ 3421 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS | 3422 RADEON_ACC_MODE_CHANGE); 3423 3424 /* tell the bios a driver is loaded */ 3425 bios_7_scratch |= RADEON_DRV_LOADED; 3426 3427 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); 3428 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3429 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch); 3430 } 3431 3432 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock) 3433 { 3434 struct drm_device *dev = encoder->dev; 3435 struct radeon_device *rdev = dev->dev_private; 3436 uint32_t bios_6_scratch; 3437 3438 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3439 3440 if (lock) 3441 bios_6_scratch |= RADEON_DRIVER_CRITICAL; 3442 else 3443 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL; 3444 3445 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3446 } 3447 3448 void 3449 radeon_combios_connected_scratch_regs(struct drm_connector *connector, 3450 struct drm_encoder *encoder, 3451 bool connected) 3452 { 3453 struct drm_device *dev = connector->dev; 3454 struct radeon_device *rdev = dev->dev_private; 3455 struct radeon_connector *radeon_connector = 3456 to_radeon_connector(connector); 3457 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3458 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH); 3459 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 3460 3461 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 3462 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 3463 if (connected) { 3464 DRM_DEBUG_KMS("TV1 connected\n"); 3465 /* fix me */ 3466 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO; 3467 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */ 3468 bios_5_scratch |= RADEON_TV1_ON; 3469 bios_5_scratch |= RADEON_ACC_REQ_TV1; 3470 } else { 3471 DRM_DEBUG_KMS("TV1 disconnected\n"); 3472 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK; 3473 bios_5_scratch &= ~RADEON_TV1_ON; 3474 bios_5_scratch &= ~RADEON_ACC_REQ_TV1; 3475 } 3476 } 3477 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 3478 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 3479 if (connected) { 3480 DRM_DEBUG_KMS("LCD1 connected\n"); 3481 bios_4_scratch |= RADEON_LCD1_ATTACHED; 3482 bios_5_scratch |= RADEON_LCD1_ON; 3483 bios_5_scratch |= RADEON_ACC_REQ_LCD1; 3484 } else { 3485 DRM_DEBUG_KMS("LCD1 disconnected\n"); 3486 bios_4_scratch &= ~RADEON_LCD1_ATTACHED; 3487 bios_5_scratch &= ~RADEON_LCD1_ON; 3488 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1; 3489 } 3490 } 3491 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 3492 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 3493 if (connected) { 3494 DRM_DEBUG_KMS("CRT1 connected\n"); 3495 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR; 3496 bios_5_scratch |= RADEON_CRT1_ON; 3497 bios_5_scratch |= RADEON_ACC_REQ_CRT1; 3498 } else { 3499 DRM_DEBUG_KMS("CRT1 disconnected\n"); 3500 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK; 3501 bios_5_scratch &= ~RADEON_CRT1_ON; 3502 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1; 3503 } 3504 } 3505 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 3506 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 3507 if (connected) { 3508 DRM_DEBUG_KMS("CRT2 connected\n"); 3509 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR; 3510 bios_5_scratch |= RADEON_CRT2_ON; 3511 bios_5_scratch |= RADEON_ACC_REQ_CRT2; 3512 } else { 3513 DRM_DEBUG_KMS("CRT2 disconnected\n"); 3514 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK; 3515 bios_5_scratch &= ~RADEON_CRT2_ON; 3516 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2; 3517 } 3518 } 3519 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 3520 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 3521 if (connected) { 3522 DRM_DEBUG_KMS("DFP1 connected\n"); 3523 bios_4_scratch |= RADEON_DFP1_ATTACHED; 3524 bios_5_scratch |= RADEON_DFP1_ON; 3525 bios_5_scratch |= RADEON_ACC_REQ_DFP1; 3526 } else { 3527 DRM_DEBUG_KMS("DFP1 disconnected\n"); 3528 bios_4_scratch &= ~RADEON_DFP1_ATTACHED; 3529 bios_5_scratch &= ~RADEON_DFP1_ON; 3530 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1; 3531 } 3532 } 3533 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 3534 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 3535 if (connected) { 3536 DRM_DEBUG_KMS("DFP2 connected\n"); 3537 bios_4_scratch |= RADEON_DFP2_ATTACHED; 3538 bios_5_scratch |= RADEON_DFP2_ON; 3539 bios_5_scratch |= RADEON_ACC_REQ_DFP2; 3540 } else { 3541 DRM_DEBUG_KMS("DFP2 disconnected\n"); 3542 bios_4_scratch &= ~RADEON_DFP2_ATTACHED; 3543 bios_5_scratch &= ~RADEON_DFP2_ON; 3544 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2; 3545 } 3546 } 3547 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch); 3548 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 3549 } 3550 3551 void 3552 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) 3553 { 3554 struct drm_device *dev = encoder->dev; 3555 struct radeon_device *rdev = dev->dev_private; 3556 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3557 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 3558 3559 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 3560 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK; 3561 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT); 3562 } 3563 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 3564 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK; 3565 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT); 3566 } 3567 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 3568 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK; 3569 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT); 3570 } 3571 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 3572 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK; 3573 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT); 3574 } 3575 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 3576 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK; 3577 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT); 3578 } 3579 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 3580 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK; 3581 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT); 3582 } 3583 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 3584 } 3585 3586 void 3587 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) 3588 { 3589 struct drm_device *dev = encoder->dev; 3590 struct radeon_device *rdev = dev->dev_private; 3591 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3592 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3593 3594 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 3595 if (on) 3596 bios_6_scratch |= RADEON_TV_DPMS_ON; 3597 else 3598 bios_6_scratch &= ~RADEON_TV_DPMS_ON; 3599 } 3600 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3601 if (on) 3602 bios_6_scratch |= RADEON_CRT_DPMS_ON; 3603 else 3604 bios_6_scratch &= ~RADEON_CRT_DPMS_ON; 3605 } 3606 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3607 if (on) 3608 bios_6_scratch |= RADEON_LCD_DPMS_ON; 3609 else 3610 bios_6_scratch &= ~RADEON_LCD_DPMS_ON; 3611 } 3612 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 3613 if (on) 3614 bios_6_scratch |= RADEON_DFP_DPMS_ON; 3615 else 3616 bios_6_scratch &= ~RADEON_DFP_DPMS_ON; 3617 } 3618 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3619 } 3620