1 /* 2 * Copyright 2008 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Jerome Glisse <glisse@freedesktop.org> 26 * 27 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_cs.c 254885 2013-08-25 19:37:15Z dumbbell $ 28 */ 29 30 #include <drm/drmP.h> 31 #include <uapi_drm/radeon_drm.h> 32 #include "radeon_reg.h" 33 #include "radeon.h" 34 35 static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) 36 { 37 struct drm_device *ddev = p->rdev->ddev; 38 struct radeon_cs_chunk *chunk; 39 unsigned i, j; 40 bool duplicate; 41 42 if (p->chunk_relocs_idx == -1) { 43 return 0; 44 } 45 chunk = &p->chunks[p->chunk_relocs_idx]; 46 p->dma_reloc_idx = 0; 47 /* FIXME: we assume that each relocs use 4 dwords */ 48 p->nrelocs = chunk->length_dw / 4; 49 p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL); 50 if (p->relocs_ptr == NULL) { 51 return -ENOMEM; 52 } 53 p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL); 54 if (p->relocs == NULL) { 55 return -ENOMEM; 56 } 57 for (i = 0; i < p->nrelocs; i++) { 58 struct drm_radeon_cs_reloc *r; 59 60 duplicate = false; 61 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4]; 62 for (j = 0; j < i; j++) { 63 if (r->handle == p->relocs[j].handle) { 64 p->relocs_ptr[i] = &p->relocs[j]; 65 duplicate = true; 66 break; 67 } 68 } 69 if (duplicate) { 70 p->relocs[i].handle = 0; 71 continue; 72 } 73 74 p->relocs[i].gobj = drm_gem_object_lookup(ddev, p->filp, 75 r->handle); 76 if (p->relocs[i].gobj == NULL) { 77 DRM_ERROR("gem object lookup failed 0x%x\n", 78 r->handle); 79 return -ENOENT; 80 } 81 p->relocs_ptr[i] = &p->relocs[i]; 82 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj); 83 p->relocs[i].lobj.bo = p->relocs[i].robj; 84 p->relocs[i].lobj.written = !!r->write_domain; 85 86 /* the first reloc of an UVD job is the 87 msg and that must be in VRAM */ 88 if (p->ring == R600_RING_TYPE_UVD_INDEX && i == 0) { 89 /* TODO: is this still needed for NI+ ? */ 90 p->relocs[i].lobj.domain = 91 RADEON_GEM_DOMAIN_VRAM; 92 93 p->relocs[i].lobj.alt_domain = 94 RADEON_GEM_DOMAIN_VRAM; 95 96 } else { 97 uint32_t domain = r->write_domain ? 98 r->write_domain : r->read_domains; 99 100 p->relocs[i].lobj.domain = domain; 101 if (domain == RADEON_GEM_DOMAIN_VRAM) 102 domain |= RADEON_GEM_DOMAIN_GTT; 103 p->relocs[i].lobj.alt_domain = domain; 104 } 105 106 p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo; 107 p->relocs[i].handle = r->handle; 108 109 radeon_bo_list_add_object(&p->relocs[i].lobj, 110 &p->validated); 111 } 112 return radeon_bo_list_validate(&p->validated, p->ring); 113 } 114 115 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority) 116 { 117 p->priority = priority; 118 119 switch (ring) { 120 default: 121 DRM_ERROR("unknown ring id: %d\n", ring); 122 return -EINVAL; 123 case RADEON_CS_RING_GFX: 124 p->ring = RADEON_RING_TYPE_GFX_INDEX; 125 break; 126 case RADEON_CS_RING_COMPUTE: 127 if (p->rdev->family >= CHIP_TAHITI) { 128 if (p->priority > 0) 129 p->ring = CAYMAN_RING_TYPE_CP1_INDEX; 130 else 131 p->ring = CAYMAN_RING_TYPE_CP2_INDEX; 132 } else 133 p->ring = RADEON_RING_TYPE_GFX_INDEX; 134 break; 135 case RADEON_CS_RING_DMA: 136 if (p->rdev->family >= CHIP_CAYMAN) { 137 if (p->priority > 0) 138 p->ring = R600_RING_TYPE_DMA_INDEX; 139 else 140 p->ring = CAYMAN_RING_TYPE_DMA1_INDEX; 141 } else if (p->rdev->family >= CHIP_R600) { 142 p->ring = R600_RING_TYPE_DMA_INDEX; 143 } else { 144 return -EINVAL; 145 } 146 break; 147 case RADEON_CS_RING_UVD: 148 p->ring = R600_RING_TYPE_UVD_INDEX; 149 break; 150 } 151 return 0; 152 } 153 154 static void radeon_cs_sync_rings(struct radeon_cs_parser *p) 155 { 156 int i; 157 158 for (i = 0; i < p->nrelocs; i++) { 159 if (!p->relocs[i].robj) 160 continue; 161 162 radeon_ib_sync_to(&p->ib, p->relocs[i].robj->tbo.sync_obj); 163 } 164 } 165 166 /* XXX: note that this is called from the legacy UMS CS ioctl as well */ 167 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) 168 { 169 struct drm_radeon_cs *cs = data; 170 uint64_t *chunk_array_ptr; 171 unsigned size, i; 172 u32 ring = RADEON_CS_RING_GFX; 173 s32 priority = 0; 174 175 if (!cs->num_chunks) { 176 return 0; 177 } 178 /* get chunks */ 179 INIT_LIST_HEAD(&p->validated); 180 p->idx = 0; 181 p->ib.sa_bo = NULL; 182 p->ib.semaphore = NULL; 183 p->const_ib.sa_bo = NULL; 184 p->const_ib.semaphore = NULL; 185 p->chunk_ib_idx = -1; 186 p->chunk_relocs_idx = -1; 187 p->chunk_flags_idx = -1; 188 p->chunk_const_ib_idx = -1; 189 p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL); 190 if (p->chunks_array == NULL) { 191 return -ENOMEM; 192 } 193 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks); 194 if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr, 195 sizeof(uint64_t)*cs->num_chunks)) { 196 return -EFAULT; 197 } 198 p->cs_flags = 0; 199 p->nchunks = cs->num_chunks; 200 p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL); 201 if (p->chunks == NULL) { 202 return -ENOMEM; 203 } 204 for (i = 0; i < p->nchunks; i++) { 205 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL; 206 struct drm_radeon_cs_chunk user_chunk; 207 uint32_t __user *cdata; 208 209 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i]; 210 if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr, 211 sizeof(struct drm_radeon_cs_chunk))) { 212 return -EFAULT; 213 } 214 p->chunks[i].length_dw = user_chunk.length_dw; 215 p->chunks[i].kdata = NULL; 216 p->chunks[i].chunk_id = user_chunk.chunk_id; 217 p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data; 218 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) { 219 p->chunk_relocs_idx = i; 220 } 221 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) { 222 p->chunk_ib_idx = i; 223 /* zero length IB isn't useful */ 224 if (p->chunks[i].length_dw == 0) 225 return -EINVAL; 226 } 227 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) { 228 p->chunk_const_ib_idx = i; 229 /* zero length CONST IB isn't useful */ 230 if (p->chunks[i].length_dw == 0) 231 return -EINVAL; 232 } 233 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) { 234 p->chunk_flags_idx = i; 235 /* zero length flags aren't useful */ 236 if (p->chunks[i].length_dw == 0) 237 return -EINVAL; 238 } 239 240 cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data; 241 if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) || 242 (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) { 243 size = p->chunks[i].length_dw * sizeof(uint32_t); 244 p->chunks[i].kdata = kmalloc(size, M_DRM, 245 M_WAITOK); 246 if (p->chunks[i].kdata == NULL) { 247 return -ENOMEM; 248 } 249 if (DRM_COPY_FROM_USER(p->chunks[i].kdata, 250 p->chunks[i].user_ptr, size)) { 251 return -EFAULT; 252 } 253 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) { 254 p->cs_flags = p->chunks[i].kdata[0]; 255 if (p->chunks[i].length_dw > 1) 256 ring = p->chunks[i].kdata[1]; 257 if (p->chunks[i].length_dw > 2) 258 priority = (s32)p->chunks[i].kdata[2]; 259 } 260 } 261 } 262 263 /* these are KMS only */ 264 if (p->rdev) { 265 if ((p->cs_flags & RADEON_CS_USE_VM) && 266 !p->rdev->vm_manager.enabled) { 267 DRM_ERROR("VM not active on asic!\n"); 268 return -EINVAL; 269 } 270 271 if (radeon_cs_get_ring(p, ring, priority)) 272 return -EINVAL; 273 274 /* we only support VM on some SI+ rings */ 275 if ((p->rdev->asic->ring[p->ring].cs_parse == NULL) && 276 ((p->cs_flags & RADEON_CS_USE_VM) == 0)) { 277 DRM_ERROR("Ring %d requires VM!\n", p->ring); 278 return -EINVAL; 279 } 280 } 281 282 /* deal with non-vm */ 283 if ((p->chunk_ib_idx != -1) && 284 ((p->cs_flags & RADEON_CS_USE_VM) == 0) && 285 (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) { 286 if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) { 287 DRM_ERROR("cs IB too big: %d\n", 288 p->chunks[p->chunk_ib_idx].length_dw); 289 return -EINVAL; 290 } 291 if (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) { 292 p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, 293 M_DRM, 294 M_WAITOK); 295 p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, 296 M_DRM, 297 M_WAITOK); 298 if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL || 299 p->chunks[p->chunk_ib_idx].kpage[1] == NULL) { 300 kfree(p->chunks[p->chunk_ib_idx].kpage[0]); 301 kfree(p->chunks[p->chunk_ib_idx].kpage[1]); 302 p->chunks[p->chunk_ib_idx].kpage[0] = NULL; 303 p->chunks[p->chunk_ib_idx].kpage[1] = NULL; 304 return -ENOMEM; 305 } 306 } 307 p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1; 308 p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1; 309 p->chunks[p->chunk_ib_idx].last_copied_page = -1; 310 p->chunks[p->chunk_ib_idx].last_page_index = 311 ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE; 312 } 313 314 return 0; 315 } 316 317 /** 318 * cs_parser_fini() - clean parser states 319 * @parser: parser structure holding parsing context. 320 * @error: error number 321 * 322 * If error is set than unvalidate buffer, otherwise just free memory 323 * used by parsing context. 324 **/ 325 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error) 326 { 327 unsigned i; 328 329 if (!error) { 330 ttm_eu_fence_buffer_objects(&parser->validated, 331 parser->ib.fence); 332 } else { 333 ttm_eu_backoff_reservation(&parser->validated); 334 } 335 336 if (parser->relocs != NULL) { 337 for (i = 0; i < parser->nrelocs; i++) { 338 if (parser->relocs[i].gobj) 339 drm_gem_object_unreference_unlocked(parser->relocs[i].gobj); 340 } 341 } 342 kfree(parser->track); 343 kfree(parser->relocs); 344 kfree(parser->relocs_ptr); 345 for (i = 0; i < parser->nchunks; i++) { 346 kfree(parser->chunks[i].kdata); 347 if ((parser->rdev->flags & RADEON_IS_AGP)) { 348 kfree(parser->chunks[i].kpage[0]); 349 kfree(parser->chunks[i].kpage[1]); 350 } 351 } 352 kfree(parser->chunks); 353 kfree(parser->chunks_array); 354 radeon_ib_free(parser->rdev, &parser->ib); 355 radeon_ib_free(parser->rdev, &parser->const_ib); 356 } 357 358 static int radeon_cs_ib_chunk(struct radeon_device *rdev, 359 struct radeon_cs_parser *parser) 360 { 361 struct radeon_cs_chunk *ib_chunk; 362 int r; 363 364 if (parser->chunk_ib_idx == -1) 365 return 0; 366 367 if (parser->cs_flags & RADEON_CS_USE_VM) 368 return 0; 369 370 ib_chunk = &parser->chunks[parser->chunk_ib_idx]; 371 /* Copy the packet into the IB, the parser will read from the 372 * input memory (cached) and write to the IB (which can be 373 * uncached). 374 */ 375 r = radeon_ib_get(rdev, parser->ring, &parser->ib, 376 NULL, ib_chunk->length_dw * 4); 377 if (r) { 378 DRM_ERROR("Failed to get ib !\n"); 379 return r; 380 } 381 parser->ib.length_dw = ib_chunk->length_dw; 382 r = radeon_cs_parse(rdev, parser->ring, parser); 383 if (r || parser->parser_error) { 384 DRM_ERROR("Invalid command stream !\n"); 385 return r; 386 } 387 r = radeon_cs_finish_pages(parser); 388 if (r) { 389 DRM_ERROR("Invalid command stream !\n"); 390 return r; 391 } 392 radeon_cs_sync_rings(parser); 393 r = radeon_ib_schedule(rdev, &parser->ib, NULL); 394 if (r) { 395 DRM_ERROR("Failed to schedule IB !\n"); 396 } 397 return r; 398 } 399 400 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser, 401 struct radeon_vm *vm) 402 { 403 struct radeon_device *rdev = parser->rdev; 404 struct radeon_bo_list *lobj; 405 struct radeon_bo *bo; 406 int r; 407 408 r = radeon_vm_bo_update_pte(rdev, vm, rdev->ring_tmp_bo.bo, &rdev->ring_tmp_bo.bo->tbo.mem); 409 if (r) { 410 return r; 411 } 412 list_for_each_entry(lobj, &parser->validated, tv.head) { 413 bo = lobj->bo; 414 r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem); 415 if (r) { 416 return r; 417 } 418 } 419 return 0; 420 } 421 422 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev, 423 struct radeon_cs_parser *parser) 424 { 425 struct radeon_cs_chunk *ib_chunk; 426 struct radeon_fpriv *fpriv = parser->filp->driver_priv; 427 struct radeon_vm *vm = &fpriv->vm; 428 int r; 429 430 if (parser->chunk_ib_idx == -1) 431 return 0; 432 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0) 433 return 0; 434 435 if ((rdev->family >= CHIP_TAHITI) && 436 (parser->chunk_const_ib_idx != -1)) { 437 ib_chunk = &parser->chunks[parser->chunk_const_ib_idx]; 438 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) { 439 DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw); 440 return -EINVAL; 441 } 442 r = radeon_ib_get(rdev, parser->ring, &parser->const_ib, 443 vm, ib_chunk->length_dw * 4); 444 if (r) { 445 DRM_ERROR("Failed to get const ib !\n"); 446 return r; 447 } 448 parser->const_ib.is_const_ib = true; 449 parser->const_ib.length_dw = ib_chunk->length_dw; 450 /* Copy the packet into the IB */ 451 if (DRM_COPY_FROM_USER(parser->const_ib.ptr, ib_chunk->user_ptr, 452 ib_chunk->length_dw * 4)) { 453 return -EFAULT; 454 } 455 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib); 456 if (r) { 457 return r; 458 } 459 } 460 461 ib_chunk = &parser->chunks[parser->chunk_ib_idx]; 462 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) { 463 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw); 464 return -EINVAL; 465 } 466 r = radeon_ib_get(rdev, parser->ring, &parser->ib, 467 vm, ib_chunk->length_dw * 4); 468 if (r) { 469 DRM_ERROR("Failed to get ib !\n"); 470 return r; 471 } 472 parser->ib.length_dw = ib_chunk->length_dw; 473 /* Copy the packet into the IB */ 474 if (DRM_COPY_FROM_USER(parser->ib.ptr, ib_chunk->user_ptr, 475 ib_chunk->length_dw * 4)) { 476 return -EFAULT; 477 } 478 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib); 479 if (r) { 480 return r; 481 } 482 483 lockmgr(&rdev->vm_manager.lock, LK_EXCLUSIVE); 484 lockmgr(&vm->mutex, LK_EXCLUSIVE); 485 r = radeon_vm_alloc_pt(rdev, vm); 486 if (r) { 487 goto out; 488 } 489 r = radeon_bo_vm_update_pte(parser, vm); 490 if (r) { 491 goto out; 492 } 493 radeon_cs_sync_rings(parser); 494 radeon_ib_sync_to(&parser->ib, vm->fence); 495 radeon_ib_sync_to(&parser->ib, radeon_vm_grab_id( 496 rdev, vm, parser->ring)); 497 498 if ((rdev->family >= CHIP_TAHITI) && 499 (parser->chunk_const_ib_idx != -1)) { 500 r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib); 501 } else { 502 r = radeon_ib_schedule(rdev, &parser->ib, NULL); 503 } 504 505 if (!r) { 506 radeon_vm_fence(rdev, vm, parser->ib.fence); 507 } 508 509 out: 510 radeon_vm_add_to_lru(rdev, vm); 511 lockmgr(&vm->mutex, LK_RELEASE); 512 lockmgr(&rdev->vm_manager.lock, LK_RELEASE); 513 return r; 514 } 515 516 static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r) 517 { 518 if (r == -EDEADLK) { 519 r = radeon_gpu_reset(rdev); 520 if (!r) 521 r = -EAGAIN; 522 } 523 return r; 524 } 525 526 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 527 { 528 struct radeon_device *rdev = dev->dev_private; 529 struct radeon_cs_parser parser; 530 int r; 531 532 lockmgr(&rdev->exclusive_lock, LK_EXCLUSIVE); 533 if (!rdev->accel_working) { 534 lockmgr(&rdev->exclusive_lock, LK_RELEASE); 535 return -EBUSY; 536 } 537 /* initialize parser */ 538 memset(&parser, 0, sizeof(struct radeon_cs_parser)); 539 parser.filp = filp; 540 parser.rdev = rdev; 541 parser.dev = rdev->dev; 542 parser.family = rdev->family; 543 r = radeon_cs_parser_init(&parser, data); 544 if (r) { 545 DRM_ERROR("Failed to initialize parser !\n"); 546 radeon_cs_parser_fini(&parser, r); 547 lockmgr(&rdev->exclusive_lock, LK_RELEASE); 548 r = radeon_cs_handle_lockup(rdev, r); 549 return r; 550 } 551 r = radeon_cs_parser_relocs(&parser); 552 if (r) { 553 if (r != -ERESTARTSYS) 554 DRM_ERROR("Failed to parse relocation %d!\n", r); 555 radeon_cs_parser_fini(&parser, r); 556 lockmgr(&rdev->exclusive_lock, LK_RELEASE); 557 r = radeon_cs_handle_lockup(rdev, r); 558 return r; 559 } 560 561 /* XXX pick SD/HD/MVC */ 562 if (parser.ring == R600_RING_TYPE_UVD_INDEX) 563 radeon_uvd_note_usage(rdev); 564 565 r = radeon_cs_ib_chunk(rdev, &parser); 566 if (r) { 567 goto out; 568 } 569 r = radeon_cs_ib_vm_chunk(rdev, &parser); 570 if (r) { 571 goto out; 572 } 573 out: 574 radeon_cs_parser_fini(&parser, r); 575 lockmgr(&rdev->exclusive_lock, LK_RELEASE); 576 r = radeon_cs_handle_lockup(rdev, r); 577 return r; 578 } 579 580 int radeon_cs_finish_pages(struct radeon_cs_parser *p) 581 { 582 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 583 int i; 584 int size = PAGE_SIZE; 585 586 for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) { 587 if (i == ibc->last_page_index) { 588 size = (ibc->length_dw * 4) % PAGE_SIZE; 589 if (size == 0) 590 size = PAGE_SIZE; 591 } 592 593 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)), 594 (char *)ibc->user_ptr + (i * PAGE_SIZE), 595 size)) 596 return -EFAULT; 597 } 598 return 0; 599 } 600 601 static int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx) 602 { 603 int new_page; 604 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 605 int i; 606 int size = PAGE_SIZE; 607 bool copy1 = (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) ? 608 false : true; 609 610 for (i = ibc->last_copied_page + 1; i < pg_idx; i++) { 611 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)), 612 (char *)ibc->user_ptr + (i * PAGE_SIZE), 613 PAGE_SIZE)) { 614 p->parser_error = -EFAULT; 615 return 0; 616 } 617 } 618 619 if (pg_idx == ibc->last_page_index) { 620 size = (ibc->length_dw * 4) % PAGE_SIZE; 621 if (size == 0) 622 size = PAGE_SIZE; 623 } 624 625 new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1; 626 if (copy1) 627 ibc->kpage[new_page] = p->ib.ptr + (pg_idx * (PAGE_SIZE / 4)); 628 629 if (DRM_COPY_FROM_USER(ibc->kpage[new_page], 630 (char *)ibc->user_ptr + (pg_idx * PAGE_SIZE), 631 size)) { 632 p->parser_error = -EFAULT; 633 return 0; 634 } 635 636 /* copy to IB for non single case */ 637 if (!copy1) 638 memcpy((void *)(p->ib.ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size); 639 640 ibc->last_copied_page = pg_idx; 641 ibc->kpage_idx[new_page] = pg_idx; 642 643 return new_page; 644 } 645 646 u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 647 { 648 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 649 u32 pg_idx, pg_offset; 650 u32 idx_value = 0; 651 int new_page; 652 653 pg_idx = (idx * 4) / PAGE_SIZE; 654 pg_offset = (idx * 4) % PAGE_SIZE; 655 656 if (ibc->kpage_idx[0] == pg_idx) 657 return ibc->kpage[0][pg_offset/4]; 658 if (ibc->kpage_idx[1] == pg_idx) 659 return ibc->kpage[1][pg_offset/4]; 660 661 new_page = radeon_cs_update_pages(p, pg_idx); 662 if (new_page < 0) { 663 p->parser_error = new_page; 664 return 0; 665 } 666 667 idx_value = ibc->kpage[new_page][pg_offset/4]; 668 return idx_value; 669 } 670 671 /** 672 * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet 673 * @parser: parser structure holding parsing context. 674 * @pkt: where to store packet information 675 * 676 * Assume that chunk_ib_index is properly set. Will return -EINVAL 677 * if packet is bigger than remaining ib size. or if packets is unknown. 678 **/ 679 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 680 struct radeon_cs_packet *pkt, 681 unsigned idx) 682 { 683 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; 684 struct radeon_device *rdev = p->rdev; 685 uint32_t header; 686 687 if (idx >= ib_chunk->length_dw) { 688 DRM_ERROR("Can not parse packet at %d after CS end %d !\n", 689 idx, ib_chunk->length_dw); 690 return -EINVAL; 691 } 692 header = radeon_get_ib_value(p, idx); 693 pkt->idx = idx; 694 pkt->type = RADEON_CP_PACKET_GET_TYPE(header); 695 pkt->count = RADEON_CP_PACKET_GET_COUNT(header); 696 pkt->one_reg_wr = 0; 697 switch (pkt->type) { 698 case RADEON_PACKET_TYPE0: 699 if (rdev->family < CHIP_R600) { 700 pkt->reg = R100_CP_PACKET0_GET_REG(header); 701 pkt->one_reg_wr = 702 RADEON_CP_PACKET0_GET_ONE_REG_WR(header); 703 } else 704 pkt->reg = R600_CP_PACKET0_GET_REG(header); 705 break; 706 case RADEON_PACKET_TYPE3: 707 pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header); 708 break; 709 case RADEON_PACKET_TYPE2: 710 pkt->count = -1; 711 break; 712 default: 713 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); 714 return -EINVAL; 715 } 716 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { 717 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", 718 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); 719 return -EINVAL; 720 } 721 return 0; 722 } 723 724 /** 725 * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP 726 * @p: structure holding the parser context. 727 * 728 * Check if the next packet is NOP relocation packet3. 729 **/ 730 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p) 731 { 732 struct radeon_cs_packet p3reloc; 733 int r; 734 735 r = radeon_cs_packet_parse(p, &p3reloc, p->idx); 736 if (r) 737 return false; 738 if (p3reloc.type != RADEON_PACKET_TYPE3) 739 return false; 740 if (p3reloc.opcode != RADEON_PACKET3_NOP) 741 return false; 742 return true; 743 } 744 745 /** 746 * radeon_cs_dump_packet() - dump raw packet context 747 * @p: structure holding the parser context. 748 * @pkt: structure holding the packet. 749 * 750 * Used mostly for debugging and error reporting. 751 **/ 752 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 753 struct radeon_cs_packet *pkt) 754 { 755 volatile uint32_t *ib; 756 unsigned i; 757 unsigned idx; 758 759 ib = p->ib.ptr; 760 idx = pkt->idx; 761 for (i = 0; i <= (pkt->count + 1); i++, idx++) 762 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); 763 } 764 765 /** 766 * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet 767 * @parser: parser structure holding parsing context. 768 * @data: pointer to relocation data 769 * @offset_start: starting offset 770 * @offset_mask: offset mask (to align start offset on) 771 * @reloc: reloc informations 772 * 773 * Check if next packet is relocation packet3, do bo validation and compute 774 * GPU offset using the provided start. 775 **/ 776 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 777 struct radeon_cs_reloc **cs_reloc, 778 int nomm) 779 { 780 struct radeon_cs_chunk *relocs_chunk; 781 struct radeon_cs_packet p3reloc; 782 unsigned idx; 783 int r; 784 785 if (p->chunk_relocs_idx == -1) { 786 DRM_ERROR("No relocation chunk !\n"); 787 return -EINVAL; 788 } 789 *cs_reloc = NULL; 790 relocs_chunk = &p->chunks[p->chunk_relocs_idx]; 791 r = radeon_cs_packet_parse(p, &p3reloc, p->idx); 792 if (r) 793 return r; 794 p->idx += p3reloc.count + 2; 795 if (p3reloc.type != RADEON_PACKET_TYPE3 || 796 p3reloc.opcode != RADEON_PACKET3_NOP) { 797 DRM_ERROR("No packet3 for relocation for packet at %d.\n", 798 p3reloc.idx); 799 radeon_cs_dump_packet(p, &p3reloc); 800 return -EINVAL; 801 } 802 idx = radeon_get_ib_value(p, p3reloc.idx + 1); 803 if (idx >= relocs_chunk->length_dw) { 804 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 805 idx, relocs_chunk->length_dw); 806 radeon_cs_dump_packet(p, &p3reloc); 807 return -EINVAL; 808 } 809 /* FIXME: we assume reloc size is 4 dwords */ 810 if (nomm) { 811 *cs_reloc = p->relocs; 812 (*cs_reloc)->lobj.gpu_offset = 813 (u64)relocs_chunk->kdata[idx + 3] << 32; 814 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0]; 815 } else 816 *cs_reloc = p->relocs_ptr[(idx / 4)]; 817 return 0; 818 } 819