1 /* 2 * Copyright 2008 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Jerome Glisse <glisse@freedesktop.org> 26 */ 27 #include <drm/drmP.h> 28 #include <uapi_drm/radeon_drm.h> 29 #include "radeon_reg.h" 30 #include "radeon.h" 31 32 static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) 33 { 34 struct drm_device *ddev = p->rdev->ddev; 35 struct radeon_cs_chunk *chunk; 36 unsigned i, j; 37 bool duplicate; 38 39 if (p->chunk_relocs_idx == -1) { 40 return 0; 41 } 42 chunk = &p->chunks[p->chunk_relocs_idx]; 43 p->dma_reloc_idx = 0; 44 /* FIXME: we assume that each relocs use 4 dwords */ 45 p->nrelocs = chunk->length_dw / 4; 46 p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL); 47 if (p->relocs_ptr == NULL) { 48 return -ENOMEM; 49 } 50 p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL); 51 if (p->relocs == NULL) { 52 return -ENOMEM; 53 } 54 for (i = 0; i < p->nrelocs; i++) { 55 struct drm_radeon_cs_reloc *r; 56 57 duplicate = false; 58 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4]; 59 for (j = 0; j < i; j++) { 60 if (r->handle == p->relocs[j].handle) { 61 p->relocs_ptr[i] = &p->relocs[j]; 62 duplicate = true; 63 break; 64 } 65 } 66 if (duplicate) { 67 p->relocs[i].handle = 0; 68 continue; 69 } 70 71 p->relocs[i].gobj = drm_gem_object_lookup(ddev, p->filp, 72 r->handle); 73 if (p->relocs[i].gobj == NULL) { 74 DRM_ERROR("gem object lookup failed 0x%x\n", 75 r->handle); 76 return -ENOENT; 77 } 78 p->relocs_ptr[i] = &p->relocs[i]; 79 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj); 80 p->relocs[i].lobj.bo = p->relocs[i].robj; 81 p->relocs[i].lobj.written = !!r->write_domain; 82 83 /* the first reloc of an UVD job is the msg and that must be in 84 VRAM, also but everything into VRAM on AGP cards to avoid 85 image corruptions */ 86 if (p->ring == R600_RING_TYPE_UVD_INDEX && 87 (i == 0 || p->rdev->flags & RADEON_IS_AGP)) { 88 /* TODO: is this still needed for NI+ ? */ 89 p->relocs[i].lobj.domain = 90 RADEON_GEM_DOMAIN_VRAM; 91 92 p->relocs[i].lobj.alt_domain = 93 RADEON_GEM_DOMAIN_VRAM; 94 95 } else { 96 uint32_t domain = r->write_domain ? 97 r->write_domain : r->read_domains; 98 99 p->relocs[i].lobj.domain = domain; 100 if (domain == RADEON_GEM_DOMAIN_VRAM) 101 domain |= RADEON_GEM_DOMAIN_GTT; 102 p->relocs[i].lobj.alt_domain = domain; 103 } 104 105 p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo; 106 p->relocs[i].handle = r->handle; 107 108 radeon_bo_list_add_object(&p->relocs[i].lobj, 109 &p->validated); 110 } 111 return radeon_bo_list_validate(&p->ticket, &p->validated, p->ring); 112 } 113 114 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority) 115 { 116 p->priority = priority; 117 118 switch (ring) { 119 default: 120 DRM_ERROR("unknown ring id: %d\n", ring); 121 return -EINVAL; 122 case RADEON_CS_RING_GFX: 123 p->ring = RADEON_RING_TYPE_GFX_INDEX; 124 break; 125 case RADEON_CS_RING_COMPUTE: 126 if (p->rdev->family >= CHIP_TAHITI) { 127 if (p->priority > 0) 128 p->ring = CAYMAN_RING_TYPE_CP1_INDEX; 129 else 130 p->ring = CAYMAN_RING_TYPE_CP2_INDEX; 131 } else 132 p->ring = RADEON_RING_TYPE_GFX_INDEX; 133 break; 134 case RADEON_CS_RING_DMA: 135 if (p->rdev->family >= CHIP_CAYMAN) { 136 if (p->priority > 0) 137 p->ring = R600_RING_TYPE_DMA_INDEX; 138 else 139 p->ring = CAYMAN_RING_TYPE_DMA1_INDEX; 140 } else if (p->rdev->family >= CHIP_R600) { 141 p->ring = R600_RING_TYPE_DMA_INDEX; 142 } else { 143 return -EINVAL; 144 } 145 break; 146 case RADEON_CS_RING_UVD: 147 p->ring = R600_RING_TYPE_UVD_INDEX; 148 break; 149 } 150 return 0; 151 } 152 153 static void radeon_cs_sync_rings(struct radeon_cs_parser *p) 154 { 155 int i; 156 157 for (i = 0; i < p->nrelocs; i++) { 158 if (!p->relocs[i].robj) 159 continue; 160 161 radeon_ib_sync_to(&p->ib, p->relocs[i].robj->tbo.sync_obj); 162 } 163 } 164 165 /* XXX: note that this is called from the legacy UMS CS ioctl as well */ 166 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) 167 { 168 struct drm_radeon_cs *cs = data; 169 uint64_t *chunk_array_ptr; 170 unsigned size, i; 171 u32 ring = RADEON_CS_RING_GFX; 172 s32 priority = 0; 173 174 if (!cs->num_chunks) { 175 return 0; 176 } 177 /* get chunks */ 178 INIT_LIST_HEAD(&p->validated); 179 p->idx = 0; 180 p->ib.sa_bo = NULL; 181 p->ib.semaphore = NULL; 182 p->const_ib.sa_bo = NULL; 183 p->const_ib.semaphore = NULL; 184 p->chunk_ib_idx = -1; 185 p->chunk_relocs_idx = -1; 186 p->chunk_flags_idx = -1; 187 p->chunk_const_ib_idx = -1; 188 p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL); 189 if (p->chunks_array == NULL) { 190 return -ENOMEM; 191 } 192 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks); 193 if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr, 194 sizeof(uint64_t)*cs->num_chunks)) { 195 return -EFAULT; 196 } 197 p->cs_flags = 0; 198 p->nchunks = cs->num_chunks; 199 p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL); 200 if (p->chunks == NULL) { 201 return -ENOMEM; 202 } 203 for (i = 0; i < p->nchunks; i++) { 204 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL; 205 struct drm_radeon_cs_chunk user_chunk; 206 uint32_t __user *cdata; 207 208 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i]; 209 if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr, 210 sizeof(struct drm_radeon_cs_chunk))) { 211 return -EFAULT; 212 } 213 p->chunks[i].length_dw = user_chunk.length_dw; 214 p->chunks[i].kdata = NULL; 215 p->chunks[i].chunk_id = user_chunk.chunk_id; 216 p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data; 217 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) { 218 p->chunk_relocs_idx = i; 219 } 220 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) { 221 p->chunk_ib_idx = i; 222 /* zero length IB isn't useful */ 223 if (p->chunks[i].length_dw == 0) 224 return -EINVAL; 225 } 226 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) { 227 p->chunk_const_ib_idx = i; 228 /* zero length CONST IB isn't useful */ 229 if (p->chunks[i].length_dw == 0) 230 return -EINVAL; 231 } 232 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) { 233 p->chunk_flags_idx = i; 234 /* zero length flags aren't useful */ 235 if (p->chunks[i].length_dw == 0) 236 return -EINVAL; 237 } 238 239 cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data; 240 if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) || 241 (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) { 242 size = p->chunks[i].length_dw * sizeof(uint32_t); 243 p->chunks[i].kdata = kmalloc(size, M_DRM, 244 M_WAITOK); 245 if (p->chunks[i].kdata == NULL) { 246 return -ENOMEM; 247 } 248 if (DRM_COPY_FROM_USER(p->chunks[i].kdata, 249 p->chunks[i].user_ptr, size)) { 250 return -EFAULT; 251 } 252 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) { 253 p->cs_flags = p->chunks[i].kdata[0]; 254 if (p->chunks[i].length_dw > 1) 255 ring = p->chunks[i].kdata[1]; 256 if (p->chunks[i].length_dw > 2) 257 priority = (s32)p->chunks[i].kdata[2]; 258 } 259 } 260 } 261 262 /* these are KMS only */ 263 if (p->rdev) { 264 if ((p->cs_flags & RADEON_CS_USE_VM) && 265 !p->rdev->vm_manager.enabled) { 266 DRM_ERROR("VM not active on asic!\n"); 267 return -EINVAL; 268 } 269 270 if (radeon_cs_get_ring(p, ring, priority)) 271 return -EINVAL; 272 273 /* we only support VM on some SI+ rings */ 274 if ((p->rdev->asic->ring[p->ring]->cs_parse == NULL) && 275 ((p->cs_flags & RADEON_CS_USE_VM) == 0)) { 276 DRM_ERROR("Ring %d requires VM!\n", p->ring); 277 return -EINVAL; 278 } 279 } 280 281 /* deal with non-vm */ 282 if ((p->chunk_ib_idx != -1) && 283 ((p->cs_flags & RADEON_CS_USE_VM) == 0) && 284 (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) { 285 if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) { 286 DRM_ERROR("cs IB too big: %d\n", 287 p->chunks[p->chunk_ib_idx].length_dw); 288 return -EINVAL; 289 } 290 if (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) { 291 p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, 292 M_DRM, 293 M_WAITOK); 294 p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, 295 M_DRM, 296 M_WAITOK); 297 if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL || 298 p->chunks[p->chunk_ib_idx].kpage[1] == NULL) { 299 kfree(p->chunks[p->chunk_ib_idx].kpage[0]); 300 kfree(p->chunks[p->chunk_ib_idx].kpage[1]); 301 p->chunks[p->chunk_ib_idx].kpage[0] = NULL; 302 p->chunks[p->chunk_ib_idx].kpage[1] = NULL; 303 return -ENOMEM; 304 } 305 } 306 p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1; 307 p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1; 308 p->chunks[p->chunk_ib_idx].last_copied_page = -1; 309 p->chunks[p->chunk_ib_idx].last_page_index = 310 ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE; 311 } 312 313 return 0; 314 } 315 316 /** 317 * cs_parser_fini() - clean parser states 318 * @parser: parser structure holding parsing context. 319 * @error: error number 320 * 321 * If error is set than unvalidate buffer, otherwise just free memory 322 * used by parsing context. 323 **/ 324 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error, bool backoff) 325 { 326 unsigned i; 327 328 if (!error) { 329 ttm_eu_fence_buffer_objects(&parser->ticket, 330 &parser->validated, 331 parser->ib.fence); 332 } else if (backoff) { 333 ttm_eu_backoff_reservation(&parser->ticket, 334 &parser->validated); 335 } 336 337 if (parser->relocs != NULL) { 338 for (i = 0; i < parser->nrelocs; i++) { 339 if (parser->relocs[i].gobj) 340 drm_gem_object_unreference_unlocked(parser->relocs[i].gobj); 341 } 342 } 343 kfree(parser->track); 344 kfree(parser->relocs); 345 kfree(parser->relocs_ptr); 346 for (i = 0; i < parser->nchunks; i++) { 347 kfree(parser->chunks[i].kdata); 348 if ((parser->rdev->flags & RADEON_IS_AGP)) { 349 kfree(parser->chunks[i].kpage[0]); 350 kfree(parser->chunks[i].kpage[1]); 351 } 352 } 353 kfree(parser->chunks); 354 kfree(parser->chunks_array); 355 radeon_ib_free(parser->rdev, &parser->ib); 356 radeon_ib_free(parser->rdev, &parser->const_ib); 357 } 358 359 static int radeon_cs_ib_chunk(struct radeon_device *rdev, 360 struct radeon_cs_parser *parser) 361 { 362 struct radeon_cs_chunk *ib_chunk; 363 int r; 364 365 if (parser->chunk_ib_idx == -1) 366 return 0; 367 368 if (parser->cs_flags & RADEON_CS_USE_VM) 369 return 0; 370 371 ib_chunk = &parser->chunks[parser->chunk_ib_idx]; 372 /* Copy the packet into the IB, the parser will read from the 373 * input memory (cached) and write to the IB (which can be 374 * uncached). 375 */ 376 r = radeon_ib_get(rdev, parser->ring, &parser->ib, 377 NULL, ib_chunk->length_dw * 4); 378 if (r) { 379 DRM_ERROR("Failed to get ib !\n"); 380 return r; 381 } 382 parser->ib.length_dw = ib_chunk->length_dw; 383 r = radeon_cs_parse(rdev, parser->ring, parser); 384 if (r || parser->parser_error) { 385 DRM_ERROR("Invalid command stream !\n"); 386 return r; 387 } 388 r = radeon_cs_finish_pages(parser); 389 if (r) { 390 DRM_ERROR("Invalid command stream !\n"); 391 return r; 392 } 393 394 if (parser->ring == R600_RING_TYPE_UVD_INDEX) 395 radeon_uvd_note_usage(rdev); 396 397 radeon_cs_sync_rings(parser); 398 r = radeon_ib_schedule(rdev, &parser->ib, NULL); 399 if (r) { 400 DRM_ERROR("Failed to schedule IB !\n"); 401 } 402 return r; 403 } 404 405 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser, 406 struct radeon_vm *vm) 407 { 408 struct radeon_device *rdev = parser->rdev; 409 struct radeon_bo_list *lobj; 410 struct radeon_bo *bo; 411 int r; 412 413 r = radeon_vm_bo_update_pte(rdev, vm, rdev->ring_tmp_bo.bo, &rdev->ring_tmp_bo.bo->tbo.mem); 414 if (r) { 415 return r; 416 } 417 list_for_each_entry(lobj, &parser->validated, tv.head) { 418 bo = lobj->bo; 419 r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem); 420 if (r) { 421 return r; 422 } 423 } 424 return 0; 425 } 426 427 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev, 428 struct radeon_cs_parser *parser) 429 { 430 struct radeon_cs_chunk *ib_chunk; 431 struct radeon_fpriv *fpriv = parser->filp->driver_priv; 432 struct radeon_vm *vm = &fpriv->vm; 433 int r; 434 435 if (parser->chunk_ib_idx == -1) 436 return 0; 437 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0) 438 return 0; 439 440 if ((rdev->family >= CHIP_TAHITI) && 441 (parser->chunk_const_ib_idx != -1)) { 442 ib_chunk = &parser->chunks[parser->chunk_const_ib_idx]; 443 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) { 444 DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw); 445 return -EINVAL; 446 } 447 r = radeon_ib_get(rdev, parser->ring, &parser->const_ib, 448 vm, ib_chunk->length_dw * 4); 449 if (r) { 450 DRM_ERROR("Failed to get const ib !\n"); 451 return r; 452 } 453 parser->const_ib.is_const_ib = true; 454 parser->const_ib.length_dw = ib_chunk->length_dw; 455 /* Copy the packet into the IB */ 456 if (DRM_COPY_FROM_USER(parser->const_ib.ptr, ib_chunk->user_ptr, 457 ib_chunk->length_dw * 4)) { 458 return -EFAULT; 459 } 460 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib); 461 if (r) { 462 return r; 463 } 464 } 465 466 ib_chunk = &parser->chunks[parser->chunk_ib_idx]; 467 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) { 468 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw); 469 return -EINVAL; 470 } 471 r = radeon_ib_get(rdev, parser->ring, &parser->ib, 472 vm, ib_chunk->length_dw * 4); 473 if (r) { 474 DRM_ERROR("Failed to get ib !\n"); 475 return r; 476 } 477 parser->ib.length_dw = ib_chunk->length_dw; 478 /* Copy the packet into the IB */ 479 if (DRM_COPY_FROM_USER(parser->ib.ptr, ib_chunk->user_ptr, 480 ib_chunk->length_dw * 4)) { 481 return -EFAULT; 482 } 483 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib); 484 if (r) { 485 return r; 486 } 487 488 if (parser->ring == R600_RING_TYPE_UVD_INDEX) 489 radeon_uvd_note_usage(rdev); 490 491 lockmgr(&rdev->vm_manager.lock, LK_EXCLUSIVE); 492 lockmgr(&vm->mutex, LK_EXCLUSIVE); 493 r = radeon_vm_alloc_pt(rdev, vm); 494 if (r) { 495 goto out; 496 } 497 r = radeon_bo_vm_update_pte(parser, vm); 498 if (r) { 499 goto out; 500 } 501 radeon_cs_sync_rings(parser); 502 radeon_ib_sync_to(&parser->ib, vm->fence); 503 radeon_ib_sync_to(&parser->ib, radeon_vm_grab_id( 504 rdev, vm, parser->ring)); 505 506 if ((rdev->family >= CHIP_TAHITI) && 507 (parser->chunk_const_ib_idx != -1)) { 508 r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib); 509 } else { 510 r = radeon_ib_schedule(rdev, &parser->ib, NULL); 511 } 512 513 if (!r) { 514 radeon_vm_fence(rdev, vm, parser->ib.fence); 515 } 516 517 out: 518 radeon_vm_add_to_lru(rdev, vm); 519 lockmgr(&vm->mutex, LK_RELEASE); 520 lockmgr(&rdev->vm_manager.lock, LK_RELEASE); 521 return r; 522 } 523 524 static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r) 525 { 526 if (r == -EDEADLK) { 527 r = radeon_gpu_reset(rdev); 528 if (!r) 529 r = -EAGAIN; 530 } 531 return r; 532 } 533 534 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 535 { 536 struct radeon_device *rdev = dev->dev_private; 537 struct radeon_cs_parser parser; 538 int r; 539 540 lockmgr(&rdev->exclusive_lock, LK_EXCLUSIVE); 541 if (!rdev->accel_working) { 542 lockmgr(&rdev->exclusive_lock, LK_RELEASE); 543 return -EBUSY; 544 } 545 /* initialize parser */ 546 memset(&parser, 0, sizeof(struct radeon_cs_parser)); 547 parser.filp = filp; 548 parser.rdev = rdev; 549 parser.dev = rdev->dev; 550 parser.family = rdev->family; 551 r = radeon_cs_parser_init(&parser, data); 552 if (r) { 553 DRM_ERROR("Failed to initialize parser !\n"); 554 radeon_cs_parser_fini(&parser, r, false); 555 lockmgr(&rdev->exclusive_lock, LK_RELEASE); 556 r = radeon_cs_handle_lockup(rdev, r); 557 return r; 558 } 559 r = radeon_cs_parser_relocs(&parser); 560 if (r) { 561 if (r != -ERESTARTSYS) 562 DRM_ERROR("Failed to parse relocation %d!\n", r); 563 radeon_cs_parser_fini(&parser, r, false); 564 lockmgr(&rdev->exclusive_lock, LK_RELEASE); 565 r = radeon_cs_handle_lockup(rdev, r); 566 return r; 567 } 568 569 #if 0 570 trace_radeon_cs(&parser); 571 #endif 572 573 r = radeon_cs_ib_chunk(rdev, &parser); 574 if (r) { 575 goto out; 576 } 577 r = radeon_cs_ib_vm_chunk(rdev, &parser); 578 if (r) { 579 goto out; 580 } 581 out: 582 radeon_cs_parser_fini(&parser, r, true); 583 lockmgr(&rdev->exclusive_lock, LK_RELEASE); 584 r = radeon_cs_handle_lockup(rdev, r); 585 return r; 586 } 587 588 int radeon_cs_finish_pages(struct radeon_cs_parser *p) 589 { 590 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 591 int i; 592 int size = PAGE_SIZE; 593 594 for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) { 595 if (i == ibc->last_page_index) { 596 size = (ibc->length_dw * 4) % PAGE_SIZE; 597 if (size == 0) 598 size = PAGE_SIZE; 599 } 600 601 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)), 602 (char *)ibc->user_ptr + (i * PAGE_SIZE), 603 size)) 604 return -EFAULT; 605 } 606 return 0; 607 } 608 609 static int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx) 610 { 611 int new_page; 612 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 613 int i; 614 int size = PAGE_SIZE; 615 bool copy1 = (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) ? 616 false : true; 617 618 for (i = ibc->last_copied_page + 1; i < pg_idx; i++) { 619 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)), 620 (char *)ibc->user_ptr + (i * PAGE_SIZE), 621 PAGE_SIZE)) { 622 p->parser_error = -EFAULT; 623 return 0; 624 } 625 } 626 627 if (pg_idx == ibc->last_page_index) { 628 size = (ibc->length_dw * 4) % PAGE_SIZE; 629 if (size == 0) 630 size = PAGE_SIZE; 631 } 632 633 new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1; 634 if (copy1) 635 ibc->kpage[new_page] = p->ib.ptr + (pg_idx * (PAGE_SIZE / 4)); 636 637 if (DRM_COPY_FROM_USER(ibc->kpage[new_page], 638 (char *)ibc->user_ptr + (pg_idx * PAGE_SIZE), 639 size)) { 640 p->parser_error = -EFAULT; 641 return 0; 642 } 643 644 /* copy to IB for non single case */ 645 if (!copy1) 646 memcpy((void *)(p->ib.ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size); 647 648 ibc->last_copied_page = pg_idx; 649 ibc->kpage_idx[new_page] = pg_idx; 650 651 return new_page; 652 } 653 654 u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 655 { 656 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 657 u32 pg_idx, pg_offset; 658 u32 idx_value = 0; 659 int new_page; 660 661 pg_idx = (idx * 4) / PAGE_SIZE; 662 pg_offset = (idx * 4) % PAGE_SIZE; 663 664 if (ibc->kpage_idx[0] == pg_idx) 665 return ibc->kpage[0][pg_offset/4]; 666 if (ibc->kpage_idx[1] == pg_idx) 667 return ibc->kpage[1][pg_offset/4]; 668 669 new_page = radeon_cs_update_pages(p, pg_idx); 670 if (new_page < 0) { 671 p->parser_error = new_page; 672 return 0; 673 } 674 675 idx_value = ibc->kpage[new_page][pg_offset/4]; 676 return idx_value; 677 } 678 679 /** 680 * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet 681 * @parser: parser structure holding parsing context. 682 * @pkt: where to store packet information 683 * 684 * Assume that chunk_ib_index is properly set. Will return -EINVAL 685 * if packet is bigger than remaining ib size. or if packets is unknown. 686 **/ 687 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 688 struct radeon_cs_packet *pkt, 689 unsigned idx) 690 { 691 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; 692 struct radeon_device *rdev = p->rdev; 693 uint32_t header; 694 695 if (idx >= ib_chunk->length_dw) { 696 DRM_ERROR("Can not parse packet at %d after CS end %d !\n", 697 idx, ib_chunk->length_dw); 698 return -EINVAL; 699 } 700 header = radeon_get_ib_value(p, idx); 701 pkt->idx = idx; 702 pkt->type = RADEON_CP_PACKET_GET_TYPE(header); 703 pkt->count = RADEON_CP_PACKET_GET_COUNT(header); 704 pkt->one_reg_wr = 0; 705 switch (pkt->type) { 706 case RADEON_PACKET_TYPE0: 707 if (rdev->family < CHIP_R600) { 708 pkt->reg = R100_CP_PACKET0_GET_REG(header); 709 pkt->one_reg_wr = 710 RADEON_CP_PACKET0_GET_ONE_REG_WR(header); 711 } else 712 pkt->reg = R600_CP_PACKET0_GET_REG(header); 713 break; 714 case RADEON_PACKET_TYPE3: 715 pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header); 716 break; 717 case RADEON_PACKET_TYPE2: 718 pkt->count = -1; 719 break; 720 default: 721 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); 722 return -EINVAL; 723 } 724 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { 725 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", 726 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); 727 return -EINVAL; 728 } 729 return 0; 730 } 731 732 /** 733 * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP 734 * @p: structure holding the parser context. 735 * 736 * Check if the next packet is NOP relocation packet3. 737 **/ 738 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p) 739 { 740 struct radeon_cs_packet p3reloc; 741 int r; 742 743 r = radeon_cs_packet_parse(p, &p3reloc, p->idx); 744 if (r) 745 return false; 746 if (p3reloc.type != RADEON_PACKET_TYPE3) 747 return false; 748 if (p3reloc.opcode != RADEON_PACKET3_NOP) 749 return false; 750 return true; 751 } 752 753 /** 754 * radeon_cs_dump_packet() - dump raw packet context 755 * @p: structure holding the parser context. 756 * @pkt: structure holding the packet. 757 * 758 * Used mostly for debugging and error reporting. 759 **/ 760 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 761 struct radeon_cs_packet *pkt) 762 { 763 volatile uint32_t *ib; 764 unsigned i; 765 unsigned idx; 766 767 ib = p->ib.ptr; 768 idx = pkt->idx; 769 for (i = 0; i <= (pkt->count + 1); i++, idx++) 770 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); 771 } 772 773 /** 774 * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet 775 * @parser: parser structure holding parsing context. 776 * @data: pointer to relocation data 777 * @offset_start: starting offset 778 * @offset_mask: offset mask (to align start offset on) 779 * @reloc: reloc informations 780 * 781 * Check if next packet is relocation packet3, do bo validation and compute 782 * GPU offset using the provided start. 783 **/ 784 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 785 struct radeon_cs_reloc **cs_reloc, 786 int nomm) 787 { 788 struct radeon_cs_chunk *relocs_chunk; 789 struct radeon_cs_packet p3reloc; 790 unsigned idx; 791 int r; 792 793 if (p->chunk_relocs_idx == -1) { 794 DRM_ERROR("No relocation chunk !\n"); 795 return -EINVAL; 796 } 797 *cs_reloc = NULL; 798 relocs_chunk = &p->chunks[p->chunk_relocs_idx]; 799 r = radeon_cs_packet_parse(p, &p3reloc, p->idx); 800 if (r) 801 return r; 802 p->idx += p3reloc.count + 2; 803 if (p3reloc.type != RADEON_PACKET_TYPE3 || 804 p3reloc.opcode != RADEON_PACKET3_NOP) { 805 DRM_ERROR("No packet3 for relocation for packet at %d.\n", 806 p3reloc.idx); 807 radeon_cs_dump_packet(p, &p3reloc); 808 return -EINVAL; 809 } 810 idx = radeon_get_ib_value(p, p3reloc.idx + 1); 811 if (idx >= relocs_chunk->length_dw) { 812 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 813 idx, relocs_chunk->length_dw); 814 radeon_cs_dump_packet(p, &p3reloc); 815 return -EINVAL; 816 } 817 /* FIXME: we assume reloc size is 4 dwords */ 818 if (nomm) { 819 *cs_reloc = p->relocs; 820 (*cs_reloc)->lobj.gpu_offset = 821 (u64)relocs_chunk->kdata[idx + 3] << 32; 822 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0]; 823 } else 824 *cs_reloc = p->relocs_ptr[(idx / 4)]; 825 return 0; 826 } 827