1 /* 2 * Copyright 2008 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Jerome Glisse <glisse@freedesktop.org> 26 */ 27 #include <linux/list_sort.h> 28 #include <drm/drmP.h> 29 #include <drm/radeon_drm.h> 30 #include "radeon_reg.h" 31 #include "radeon.h" 32 #include "radeon_trace.h" 33 34 #define RADEON_CS_MAX_PRIORITY 32u 35 #define RADEON_CS_NUM_BUCKETS (RADEON_CS_MAX_PRIORITY + 1) 36 37 /* This is based on the bucket sort with O(n) time complexity. 38 * An item with priority "i" is added to bucket[i]. The lists are then 39 * concatenated in descending order. 40 */ 41 struct radeon_cs_buckets { 42 struct list_head bucket[RADEON_CS_NUM_BUCKETS]; 43 }; 44 45 static void radeon_cs_buckets_init(struct radeon_cs_buckets *b) 46 { 47 unsigned i; 48 49 for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++) 50 INIT_LIST_HEAD(&b->bucket[i]); 51 } 52 53 static void radeon_cs_buckets_add(struct radeon_cs_buckets *b, 54 struct list_head *item, unsigned priority) 55 { 56 /* Since buffers which appear sooner in the relocation list are 57 * likely to be used more often than buffers which appear later 58 * in the list, the sort mustn't change the ordering of buffers 59 * with the same priority, i.e. it must be stable. 60 */ 61 list_add_tail(item, &b->bucket[min(priority, RADEON_CS_MAX_PRIORITY)]); 62 } 63 64 static void radeon_cs_buckets_get_list(struct radeon_cs_buckets *b, 65 struct list_head *out_list) 66 { 67 unsigned i; 68 69 /* Connect the sorted buckets in the output list. */ 70 for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++) { 71 list_splice(&b->bucket[i], out_list); 72 } 73 } 74 75 static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) 76 { 77 struct radeon_cs_chunk *chunk; 78 struct radeon_cs_buckets buckets; 79 unsigned i; 80 bool need_mmap_lock = false; 81 int r; 82 83 if (p->chunk_relocs == NULL) { 84 return 0; 85 } 86 chunk = p->chunk_relocs; 87 p->dma_reloc_idx = 0; 88 /* FIXME: we assume that each relocs use 4 dwords */ 89 p->nrelocs = chunk->length_dw / 4; 90 p->relocs = kvmalloc_array(p->nrelocs, sizeof(struct radeon_bo_list), 91 GFP_KERNEL | __GFP_ZERO); 92 if (p->relocs == NULL) { 93 return -ENOMEM; 94 } 95 96 radeon_cs_buckets_init(&buckets); 97 98 for (i = 0; i < p->nrelocs; i++) { 99 struct drm_radeon_cs_reloc *r; 100 struct drm_gem_object *gobj; 101 unsigned priority; 102 103 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4]; 104 gobj = drm_gem_object_lookup(p->filp, r->handle); 105 if (gobj == NULL) { 106 DRM_ERROR("gem object lookup failed 0x%x\n", 107 r->handle); 108 return -ENOENT; 109 } 110 p->relocs[i].robj = gem_to_radeon_bo(gobj); 111 112 /* The userspace buffer priorities are from 0 to 15. A higher 113 * number means the buffer is more important. 114 * Also, the buffers used for write have a higher priority than 115 * the buffers used for read only, which doubles the range 116 * to 0 to 31. 32 is reserved for the kernel driver. 117 */ 118 priority = (r->flags & RADEON_RELOC_PRIO_MASK) * 2 119 + !!r->write_domain; 120 121 /* The first reloc of an UVD job is the msg and that must be in 122 * VRAM, the second reloc is the DPB and for WMV that must be in 123 * VRAM as well. Also put everything into VRAM on AGP cards and older 124 * IGP chips to avoid image corruptions 125 */ 126 if (p->ring == R600_RING_TYPE_UVD_INDEX && 127 (i <= 0 || drm_pci_device_is_agp(p->rdev->ddev) || 128 p->rdev->family == CHIP_RS780 || 129 p->rdev->family == CHIP_RS880)) { 130 131 /* TODO: is this still needed for NI+ ? */ 132 p->relocs[i].preferred_domains = 133 RADEON_GEM_DOMAIN_VRAM; 134 135 p->relocs[i].allowed_domains = 136 RADEON_GEM_DOMAIN_VRAM; 137 138 /* prioritize this over any other relocation */ 139 priority = RADEON_CS_MAX_PRIORITY; 140 } else { 141 uint32_t domain = r->write_domain ? 142 r->write_domain : r->read_domains; 143 144 if (domain & RADEON_GEM_DOMAIN_CPU) { 145 DRM_ERROR("RADEON_GEM_DOMAIN_CPU is not valid " 146 "for command submission\n"); 147 return -EINVAL; 148 } 149 150 p->relocs[i].preferred_domains = domain; 151 if (domain == RADEON_GEM_DOMAIN_VRAM) 152 domain |= RADEON_GEM_DOMAIN_GTT; 153 p->relocs[i].allowed_domains = domain; 154 } 155 156 #if 0 157 if (radeon_ttm_tt_has_userptr(p->relocs[i].robj->tbo.ttm)) { 158 uint32_t domain = p->relocs[i].prefered_domains; 159 if (!(domain & RADEON_GEM_DOMAIN_GTT)) { 160 DRM_ERROR("Only RADEON_GEM_DOMAIN_GTT is " 161 "allowed for userptr BOs\n"); 162 return -EINVAL; 163 } 164 need_mmap_lock = true; 165 domain = RADEON_GEM_DOMAIN_GTT; 166 p->relocs[i].preferred_domains = domain; 167 p->relocs[i].allowed_domains = domain; 168 } 169 #endif 170 171 /* Objects shared as dma-bufs cannot be moved to VRAM */ 172 if (p->relocs[i].robj->prime_shared_count) { 173 p->relocs[i].allowed_domains &= ~RADEON_GEM_DOMAIN_VRAM; 174 if (!p->relocs[i].allowed_domains) { 175 DRM_ERROR("BO associated with dma-buf cannot " 176 "be moved to VRAM\n"); 177 return -EINVAL; 178 } 179 } 180 181 p->relocs[i].tv.bo = &p->relocs[i].robj->tbo; 182 p->relocs[i].tv.shared = !r->write_domain; 183 184 radeon_cs_buckets_add(&buckets, &p->relocs[i].tv.head, 185 priority); 186 } 187 188 radeon_cs_buckets_get_list(&buckets, &p->validated); 189 190 if (p->cs_flags & RADEON_CS_USE_VM) 191 p->vm_bos = radeon_vm_get_bos(p->rdev, p->ib.vm, 192 &p->validated); 193 if (need_mmap_lock) 194 down_read(¤t->mm->mmap_sem); 195 196 r = radeon_bo_list_validate(p->rdev, &p->ticket, &p->validated, p->ring); 197 198 if (need_mmap_lock) 199 up_read(¤t->mm->mmap_sem); 200 201 return r; 202 } 203 204 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority) 205 { 206 p->priority = priority; 207 208 switch (ring) { 209 default: 210 DRM_ERROR("unknown ring id: %d\n", ring); 211 return -EINVAL; 212 case RADEON_CS_RING_GFX: 213 p->ring = RADEON_RING_TYPE_GFX_INDEX; 214 break; 215 case RADEON_CS_RING_COMPUTE: 216 if (p->rdev->family >= CHIP_TAHITI) { 217 if (p->priority > 0) 218 p->ring = CAYMAN_RING_TYPE_CP1_INDEX; 219 else 220 p->ring = CAYMAN_RING_TYPE_CP2_INDEX; 221 } else 222 p->ring = RADEON_RING_TYPE_GFX_INDEX; 223 break; 224 case RADEON_CS_RING_DMA: 225 if (p->rdev->family >= CHIP_CAYMAN) { 226 if (p->priority > 0) 227 p->ring = R600_RING_TYPE_DMA_INDEX; 228 else 229 p->ring = CAYMAN_RING_TYPE_DMA1_INDEX; 230 } else if (p->rdev->family >= CHIP_RV770) { 231 p->ring = R600_RING_TYPE_DMA_INDEX; 232 } else { 233 return -EINVAL; 234 } 235 break; 236 case RADEON_CS_RING_UVD: 237 p->ring = R600_RING_TYPE_UVD_INDEX; 238 break; 239 case RADEON_CS_RING_VCE: 240 /* TODO: only use the low priority ring for now */ 241 p->ring = TN_RING_TYPE_VCE1_INDEX; 242 break; 243 } 244 return 0; 245 } 246 247 static int radeon_cs_sync_rings(struct radeon_cs_parser *p) 248 { 249 struct radeon_bo_list *reloc; 250 int r; 251 252 list_for_each_entry(reloc, &p->validated, tv.head) { 253 struct reservation_object *resv; 254 255 resv = reloc->robj->tbo.resv; 256 r = radeon_sync_resv(p->rdev, &p->ib.sync, resv, 257 reloc->tv.shared); 258 if (r) 259 return r; 260 } 261 return 0; 262 } 263 264 /* XXX: note that this is called from the legacy UMS CS ioctl as well */ 265 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) 266 { 267 struct drm_radeon_cs *cs = data; 268 uint64_t *chunk_array_ptr; 269 unsigned size, i; 270 u32 ring = RADEON_CS_RING_GFX; 271 s32 priority = 0; 272 273 INIT_LIST_HEAD(&p->validated); 274 275 if (!cs->num_chunks) { 276 return 0; 277 } 278 279 /* get chunks */ 280 p->idx = 0; 281 p->ib.sa_bo = NULL; 282 p->const_ib.sa_bo = NULL; 283 p->chunk_ib = NULL; 284 p->chunk_relocs = NULL; 285 p->chunk_flags = NULL; 286 p->chunk_const_ib = NULL; 287 p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL); 288 if (p->chunks_array == NULL) { 289 return -ENOMEM; 290 } 291 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks); 292 if (copy_from_user(p->chunks_array, chunk_array_ptr, 293 sizeof(uint64_t)*cs->num_chunks)) { 294 return -EFAULT; 295 } 296 p->cs_flags = 0; 297 p->nchunks = cs->num_chunks; 298 p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL); 299 if (p->chunks == NULL) { 300 return -ENOMEM; 301 } 302 for (i = 0; i < p->nchunks; i++) { 303 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL; 304 struct drm_radeon_cs_chunk user_chunk; 305 uint32_t __user *cdata; 306 307 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i]; 308 if (copy_from_user(&user_chunk, chunk_ptr, 309 sizeof(struct drm_radeon_cs_chunk))) { 310 return -EFAULT; 311 } 312 p->chunks[i].length_dw = user_chunk.length_dw; 313 if (user_chunk.chunk_id == RADEON_CHUNK_ID_RELOCS) { 314 p->chunk_relocs = &p->chunks[i]; 315 } 316 if (user_chunk.chunk_id == RADEON_CHUNK_ID_IB) { 317 p->chunk_ib = &p->chunks[i]; 318 /* zero length IB isn't useful */ 319 if (p->chunks[i].length_dw == 0) 320 return -EINVAL; 321 } 322 if (user_chunk.chunk_id == RADEON_CHUNK_ID_CONST_IB) { 323 p->chunk_const_ib = &p->chunks[i]; 324 /* zero length CONST IB isn't useful */ 325 if (p->chunks[i].length_dw == 0) 326 return -EINVAL; 327 } 328 if (user_chunk.chunk_id == RADEON_CHUNK_ID_FLAGS) { 329 p->chunk_flags = &p->chunks[i]; 330 /* zero length flags aren't useful */ 331 if (p->chunks[i].length_dw == 0) 332 return -EINVAL; 333 } 334 335 size = p->chunks[i].length_dw; 336 cdata = (void __user *)(unsigned long)user_chunk.chunk_data; 337 p->chunks[i].user_ptr = cdata; 338 if (user_chunk.chunk_id == RADEON_CHUNK_ID_CONST_IB) 339 continue; 340 341 if (user_chunk.chunk_id == RADEON_CHUNK_ID_IB) { 342 if (!p->rdev || !(p->rdev->flags & RADEON_IS_AGP)) 343 continue; 344 } 345 346 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL); 347 size *= sizeof(uint32_t); 348 if (p->chunks[i].kdata == NULL) { 349 return -ENOMEM; 350 } 351 if (copy_from_user(p->chunks[i].kdata, cdata, size)) { 352 return -EFAULT; 353 } 354 if (user_chunk.chunk_id == RADEON_CHUNK_ID_FLAGS) { 355 p->cs_flags = p->chunks[i].kdata[0]; 356 if (p->chunks[i].length_dw > 1) 357 ring = p->chunks[i].kdata[1]; 358 if (p->chunks[i].length_dw > 2) 359 priority = (s32)p->chunks[i].kdata[2]; 360 } 361 } 362 363 /* these are KMS only */ 364 if (p->rdev) { 365 if ((p->cs_flags & RADEON_CS_USE_VM) && 366 !p->rdev->vm_manager.enabled) { 367 DRM_ERROR("VM not active on asic!\n"); 368 return -EINVAL; 369 } 370 371 if (radeon_cs_get_ring(p, ring, priority)) 372 return -EINVAL; 373 374 /* we only support VM on some SI+ rings */ 375 if ((p->cs_flags & RADEON_CS_USE_VM) == 0) { 376 if (p->rdev->asic->ring[p->ring]->cs_parse == NULL) { 377 DRM_ERROR("Ring %d requires VM!\n", p->ring); 378 return -EINVAL; 379 } 380 } else { 381 if (p->rdev->asic->ring[p->ring]->ib_parse == NULL) { 382 DRM_ERROR("VM not supported on ring %d!\n", 383 p->ring); 384 return -EINVAL; 385 } 386 } 387 } 388 389 return 0; 390 } 391 392 static int cmp_size_smaller_first(void *priv, struct list_head *a, 393 struct list_head *b) 394 { 395 struct radeon_bo_list *la = list_entry(a, struct radeon_bo_list, tv.head); 396 struct radeon_bo_list *lb = list_entry(b, struct radeon_bo_list, tv.head); 397 398 /* Sort A before B if A is smaller. */ 399 return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages; 400 } 401 402 /** 403 * cs_parser_fini() - clean parser states 404 * @parser: parser structure holding parsing context. 405 * @error: error number 406 * 407 * If error is set than unvalidate buffer, otherwise just free memory 408 * used by parsing context. 409 **/ 410 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error, bool backoff) 411 { 412 unsigned i; 413 414 if (!error) { 415 /* Sort the buffer list from the smallest to largest buffer, 416 * which affects the order of buffers in the LRU list. 417 * This assures that the smallest buffers are added first 418 * to the LRU list, so they are likely to be later evicted 419 * first, instead of large buffers whose eviction is more 420 * expensive. 421 * 422 * This slightly lowers the number of bytes moved by TTM 423 * per frame under memory pressure. 424 */ 425 list_sort(NULL, &parser->validated, cmp_size_smaller_first); 426 427 ttm_eu_fence_buffer_objects(&parser->ticket, 428 &parser->validated, 429 &parser->ib.fence->base); 430 } else if (backoff) { 431 ttm_eu_backoff_reservation(&parser->ticket, 432 &parser->validated); 433 } 434 435 if (parser->relocs != NULL) { 436 for (i = 0; i < parser->nrelocs; i++) { 437 struct radeon_bo *bo = parser->relocs[i].robj; 438 if (bo == NULL) 439 continue; 440 441 drm_gem_object_put_unlocked(&bo->gem_base); 442 } 443 } 444 kfree(parser->track); 445 kvfree(parser->relocs); 446 kvfree(parser->vm_bos); 447 for (i = 0; i < parser->nchunks; i++) 448 kvfree(parser->chunks[i].kdata); 449 kfree(parser->chunks); 450 kfree(parser->chunks_array); 451 radeon_ib_free(parser->rdev, &parser->ib); 452 radeon_ib_free(parser->rdev, &parser->const_ib); 453 } 454 455 static int radeon_cs_ib_chunk(struct radeon_device *rdev, 456 struct radeon_cs_parser *parser) 457 { 458 int r; 459 460 if (parser->chunk_ib == NULL) 461 return 0; 462 463 if (parser->cs_flags & RADEON_CS_USE_VM) 464 return 0; 465 466 r = radeon_cs_parse(rdev, parser->ring, parser); 467 if (r || parser->parser_error) { 468 DRM_ERROR("Invalid command stream !\n"); 469 return r; 470 } 471 472 r = radeon_cs_sync_rings(parser); 473 if (r) { 474 if (r != -ERESTARTSYS) 475 DRM_ERROR("Failed to sync rings: %i\n", r); 476 return r; 477 } 478 479 if (parser->ring == R600_RING_TYPE_UVD_INDEX) 480 radeon_uvd_note_usage(rdev); 481 else if ((parser->ring == TN_RING_TYPE_VCE1_INDEX) || 482 (parser->ring == TN_RING_TYPE_VCE2_INDEX)) 483 radeon_vce_note_usage(rdev); 484 485 r = radeon_ib_schedule(rdev, &parser->ib, NULL, true); 486 if (r) { 487 DRM_ERROR("Failed to schedule IB !\n"); 488 } 489 return r; 490 } 491 492 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *p, 493 struct radeon_vm *vm) 494 { 495 struct radeon_device *rdev = p->rdev; 496 struct radeon_bo_va *bo_va; 497 int i, r; 498 499 r = radeon_vm_update_page_directory(rdev, vm); 500 if (r) 501 return r; 502 503 r = radeon_vm_clear_freed(rdev, vm); 504 if (r) 505 return r; 506 507 if (vm->ib_bo_va == NULL) { 508 DRM_ERROR("Tmp BO not in VM!\n"); 509 return -EINVAL; 510 } 511 512 r = radeon_vm_bo_update(rdev, vm->ib_bo_va, 513 &rdev->ring_tmp_bo.bo->tbo.mem); 514 if (r) 515 return r; 516 517 for (i = 0; i < p->nrelocs; i++) { 518 struct radeon_bo *bo; 519 520 bo = p->relocs[i].robj; 521 bo_va = radeon_vm_bo_find(vm, bo); 522 if (bo_va == NULL) { 523 dev_err(rdev->dev, "bo %p not in vm %p\n", bo, vm); 524 return -EINVAL; 525 } 526 527 r = radeon_vm_bo_update(rdev, bo_va, &bo->tbo.mem); 528 if (r) 529 return r; 530 531 radeon_sync_fence(&p->ib.sync, bo_va->last_pt_update); 532 } 533 534 return radeon_vm_clear_invalids(rdev, vm); 535 } 536 537 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev, 538 struct radeon_cs_parser *parser) 539 { 540 struct radeon_fpriv *fpriv = parser->filp->driver_priv; 541 struct radeon_vm *vm = &fpriv->vm; 542 int r; 543 544 if (parser->chunk_ib == NULL) 545 return 0; 546 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0) 547 return 0; 548 549 if (parser->const_ib.length_dw) { 550 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib); 551 if (r) { 552 return r; 553 } 554 } 555 556 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib); 557 if (r) { 558 return r; 559 } 560 561 if (parser->ring == R600_RING_TYPE_UVD_INDEX) 562 radeon_uvd_note_usage(rdev); 563 564 mutex_lock(&vm->mutex); 565 r = radeon_bo_vm_update_pte(parser, vm); 566 if (r) { 567 goto out; 568 } 569 570 r = radeon_cs_sync_rings(parser); 571 if (r) { 572 if (r != -ERESTARTSYS) 573 DRM_ERROR("Failed to sync rings: %i\n", r); 574 goto out; 575 } 576 577 if ((rdev->family >= CHIP_TAHITI) && 578 (parser->chunk_const_ib != NULL)) { 579 r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib, true); 580 } else { 581 r = radeon_ib_schedule(rdev, &parser->ib, NULL, true); 582 } 583 584 out: 585 mutex_unlock(&vm->mutex); 586 return r; 587 } 588 589 static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r) 590 { 591 if (r == -EDEADLK) { 592 r = radeon_gpu_reset(rdev); 593 if (!r) 594 r = -EAGAIN; 595 } 596 return r; 597 } 598 599 static int radeon_cs_ib_fill(struct radeon_device *rdev, struct radeon_cs_parser *parser) 600 { 601 struct radeon_cs_chunk *ib_chunk; 602 struct radeon_vm *vm = NULL; 603 int r; 604 605 if (parser->chunk_ib == NULL) 606 return 0; 607 608 if (parser->cs_flags & RADEON_CS_USE_VM) { 609 struct radeon_fpriv *fpriv = parser->filp->driver_priv; 610 vm = &fpriv->vm; 611 612 if ((rdev->family >= CHIP_TAHITI) && 613 (parser->chunk_const_ib != NULL)) { 614 ib_chunk = parser->chunk_const_ib; 615 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) { 616 DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw); 617 return -EINVAL; 618 } 619 r = radeon_ib_get(rdev, parser->ring, &parser->const_ib, 620 vm, ib_chunk->length_dw * 4); 621 if (r) { 622 DRM_ERROR("Failed to get const ib !\n"); 623 return r; 624 } 625 parser->const_ib.is_const_ib = true; 626 parser->const_ib.length_dw = ib_chunk->length_dw; 627 if (copy_from_user(parser->const_ib.ptr, 628 ib_chunk->user_ptr, 629 ib_chunk->length_dw * 4)) 630 return -EFAULT; 631 } 632 633 ib_chunk = parser->chunk_ib; 634 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) { 635 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw); 636 return -EINVAL; 637 } 638 } 639 ib_chunk = parser->chunk_ib; 640 641 r = radeon_ib_get(rdev, parser->ring, &parser->ib, 642 vm, ib_chunk->length_dw * 4); 643 if (r) { 644 DRM_ERROR("Failed to get ib !\n"); 645 return r; 646 } 647 parser->ib.length_dw = ib_chunk->length_dw; 648 if (ib_chunk->kdata) 649 memcpy(parser->ib.ptr, ib_chunk->kdata, ib_chunk->length_dw * 4); 650 else if (copy_from_user(parser->ib.ptr, ib_chunk->user_ptr, ib_chunk->length_dw * 4)) 651 return -EFAULT; 652 return 0; 653 } 654 655 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 656 { 657 struct radeon_device *rdev = dev->dev_private; 658 struct radeon_cs_parser parser; 659 int r; 660 661 down_read(&rdev->exclusive_lock); 662 if (!rdev->accel_working) { 663 up_read(&rdev->exclusive_lock); 664 return -EBUSY; 665 } 666 if (rdev->in_reset) { 667 up_read(&rdev->exclusive_lock); 668 r = radeon_gpu_reset(rdev); 669 if (!r) 670 r = -EAGAIN; 671 return r; 672 } 673 /* initialize parser */ 674 memset(&parser, 0, sizeof(struct radeon_cs_parser)); 675 parser.filp = filp; 676 parser.rdev = rdev; 677 parser.dev = rdev->dev; 678 parser.family = rdev->family; 679 r = radeon_cs_parser_init(&parser, data); 680 if (r) { 681 DRM_ERROR("Failed to initialize parser !\n"); 682 radeon_cs_parser_fini(&parser, r, false); 683 up_read(&rdev->exclusive_lock); 684 r = radeon_cs_handle_lockup(rdev, r); 685 return r; 686 } 687 688 r = radeon_cs_ib_fill(rdev, &parser); 689 if (!r) { 690 r = radeon_cs_parser_relocs(&parser); 691 if (r && r != -ERESTARTSYS) 692 DRM_ERROR("Failed to parse relocation %d!\n", r); 693 } 694 695 if (r) { 696 radeon_cs_parser_fini(&parser, r, false); 697 up_read(&rdev->exclusive_lock); 698 r = radeon_cs_handle_lockup(rdev, r); 699 return r; 700 } 701 702 #ifdef TRACE_TODO 703 trace_radeon_cs(&parser); 704 #endif 705 706 r = radeon_cs_ib_chunk(rdev, &parser); 707 if (r) { 708 goto out; 709 } 710 r = radeon_cs_ib_vm_chunk(rdev, &parser); 711 if (r) { 712 goto out; 713 } 714 out: 715 radeon_cs_parser_fini(&parser, r, true); 716 up_read(&rdev->exclusive_lock); 717 r = radeon_cs_handle_lockup(rdev, r); 718 return r; 719 } 720 721 /** 722 * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet 723 * @parser: parser structure holding parsing context. 724 * @pkt: where to store packet information 725 * 726 * Assume that chunk_ib_index is properly set. Will return -EINVAL 727 * if packet is bigger than remaining ib size. or if packets is unknown. 728 **/ 729 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 730 struct radeon_cs_packet *pkt, 731 unsigned idx) 732 { 733 struct radeon_cs_chunk *ib_chunk = p->chunk_ib; 734 struct radeon_device *rdev = p->rdev; 735 uint32_t header; 736 int ret = 0, i; 737 738 if (idx >= ib_chunk->length_dw) { 739 DRM_ERROR("Can not parse packet at %d after CS end %d !\n", 740 idx, ib_chunk->length_dw); 741 return -EINVAL; 742 } 743 header = radeon_get_ib_value(p, idx); 744 pkt->idx = idx; 745 pkt->type = RADEON_CP_PACKET_GET_TYPE(header); 746 pkt->count = RADEON_CP_PACKET_GET_COUNT(header); 747 pkt->one_reg_wr = 0; 748 switch (pkt->type) { 749 case RADEON_PACKET_TYPE0: 750 if (rdev->family < CHIP_R600) { 751 pkt->reg = R100_CP_PACKET0_GET_REG(header); 752 pkt->one_reg_wr = 753 RADEON_CP_PACKET0_GET_ONE_REG_WR(header); 754 } else 755 pkt->reg = R600_CP_PACKET0_GET_REG(header); 756 break; 757 case RADEON_PACKET_TYPE3: 758 pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header); 759 break; 760 case RADEON_PACKET_TYPE2: 761 pkt->count = -1; 762 break; 763 default: 764 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); 765 ret = -EINVAL; 766 goto dump_ib; 767 } 768 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { 769 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", 770 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); 771 ret = -EINVAL; 772 goto dump_ib; 773 } 774 return 0; 775 776 dump_ib: 777 for (i = 0; i < ib_chunk->length_dw; i++) { 778 if (i == idx) 779 printk("\t0x%08x <---\n", radeon_get_ib_value(p, i)); 780 else 781 printk("\t0x%08x\n", radeon_get_ib_value(p, i)); 782 } 783 return ret; 784 } 785 786 /** 787 * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP 788 * @p: structure holding the parser context. 789 * 790 * Check if the next packet is NOP relocation packet3. 791 **/ 792 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p) 793 { 794 struct radeon_cs_packet p3reloc; 795 int r; 796 797 r = radeon_cs_packet_parse(p, &p3reloc, p->idx); 798 if (r) 799 return false; 800 if (p3reloc.type != RADEON_PACKET_TYPE3) 801 return false; 802 if (p3reloc.opcode != RADEON_PACKET3_NOP) 803 return false; 804 return true; 805 } 806 807 /** 808 * radeon_cs_dump_packet() - dump raw packet context 809 * @p: structure holding the parser context. 810 * @pkt: structure holding the packet. 811 * 812 * Used mostly for debugging and error reporting. 813 **/ 814 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 815 struct radeon_cs_packet *pkt) 816 { 817 volatile uint32_t *ib; 818 unsigned i; 819 unsigned idx; 820 821 ib = p->ib.ptr; 822 idx = pkt->idx; 823 for (i = 0; i <= (pkt->count + 1); i++, idx++) 824 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); 825 } 826 827 /** 828 * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet 829 * @parser: parser structure holding parsing context. 830 * @data: pointer to relocation data 831 * @offset_start: starting offset 832 * @offset_mask: offset mask (to align start offset on) 833 * @reloc: reloc informations 834 * 835 * Check if next packet is relocation packet3, do bo validation and compute 836 * GPU offset using the provided start. 837 **/ 838 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 839 struct radeon_bo_list **cs_reloc, 840 int nomm) 841 { 842 struct radeon_cs_chunk *relocs_chunk; 843 struct radeon_cs_packet p3reloc; 844 unsigned idx; 845 int r; 846 847 if (p->chunk_relocs == NULL) { 848 DRM_ERROR("No relocation chunk !\n"); 849 return -EINVAL; 850 } 851 *cs_reloc = NULL; 852 relocs_chunk = p->chunk_relocs; 853 r = radeon_cs_packet_parse(p, &p3reloc, p->idx); 854 if (r) 855 return r; 856 p->idx += p3reloc.count + 2; 857 if (p3reloc.type != RADEON_PACKET_TYPE3 || 858 p3reloc.opcode != RADEON_PACKET3_NOP) { 859 DRM_ERROR("No packet3 for relocation for packet at %d.\n", 860 p3reloc.idx); 861 radeon_cs_dump_packet(p, &p3reloc); 862 return -EINVAL; 863 } 864 idx = radeon_get_ib_value(p, p3reloc.idx + 1); 865 if (idx >= relocs_chunk->length_dw) { 866 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 867 idx, relocs_chunk->length_dw); 868 radeon_cs_dump_packet(p, &p3reloc); 869 return -EINVAL; 870 } 871 /* FIXME: we assume reloc size is 4 dwords */ 872 if (nomm) { 873 *cs_reloc = p->relocs; 874 (*cs_reloc)->gpu_offset = 875 (u64)relocs_chunk->kdata[idx + 3] << 32; 876 (*cs_reloc)->gpu_offset |= relocs_chunk->kdata[idx + 0]; 877 } else 878 *cs_reloc = &p->relocs[(idx / 4)]; 879 return 0; 880 } 881