1926deccbSFrançois Tigeot /* 2926deccbSFrançois Tigeot * Copyright 2007-8 Advanced Micro Devices, Inc. 3926deccbSFrançois Tigeot * Copyright 2008 Red Hat Inc. 4926deccbSFrançois Tigeot * 5926deccbSFrançois Tigeot * Permission is hereby granted, free of charge, to any person obtaining a 6926deccbSFrançois Tigeot * copy of this software and associated documentation files (the "Software"), 7926deccbSFrançois Tigeot * to deal in the Software without restriction, including without limitation 8926deccbSFrançois Tigeot * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9926deccbSFrançois Tigeot * and/or sell copies of the Software, and to permit persons to whom the 10926deccbSFrançois Tigeot * Software is furnished to do so, subject to the following conditions: 11926deccbSFrançois Tigeot * 12926deccbSFrançois Tigeot * The above copyright notice and this permission notice shall be included in 13926deccbSFrançois Tigeot * all copies or substantial portions of the Software. 14926deccbSFrançois Tigeot * 15926deccbSFrançois Tigeot * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16926deccbSFrançois Tigeot * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17926deccbSFrançois Tigeot * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18926deccbSFrançois Tigeot * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19926deccbSFrançois Tigeot * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20926deccbSFrançois Tigeot * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21926deccbSFrançois Tigeot * OTHER DEALINGS IN THE SOFTWARE. 22926deccbSFrançois Tigeot * 23926deccbSFrançois Tigeot * Authors: Dave Airlie 24926deccbSFrançois Tigeot * Alex Deucher 25926deccbSFrançois Tigeot * 26926deccbSFrançois Tigeot * $FreeBSD: head/sys/dev/drm2/radeon/radeon_cursor.c 254885 2013-08-25 19:37:15Z dumbbell $ 27926deccbSFrançois Tigeot */ 28926deccbSFrançois Tigeot 29926deccbSFrançois Tigeot #include <drm/drmP.h> 30926deccbSFrançois Tigeot #include <uapi_drm/radeon_drm.h> 31926deccbSFrançois Tigeot #include "radeon.h" 32926deccbSFrançois Tigeot 33926deccbSFrançois Tigeot #define CURSOR_WIDTH 64 34926deccbSFrançois Tigeot #define CURSOR_HEIGHT 64 35926deccbSFrançois Tigeot 36926deccbSFrançois Tigeot static void radeon_lock_cursor(struct drm_crtc *crtc, bool lock) 37926deccbSFrançois Tigeot { 38926deccbSFrançois Tigeot struct radeon_device *rdev = crtc->dev->dev_private; 39926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 40926deccbSFrançois Tigeot uint32_t cur_lock; 41926deccbSFrançois Tigeot 42926deccbSFrançois Tigeot if (ASIC_IS_DCE4(rdev)) { 43926deccbSFrançois Tigeot cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset); 44926deccbSFrançois Tigeot if (lock) 45926deccbSFrançois Tigeot cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK; 46926deccbSFrançois Tigeot else 47926deccbSFrançois Tigeot cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK; 48926deccbSFrançois Tigeot WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); 49926deccbSFrançois Tigeot } else if (ASIC_IS_AVIVO(rdev)) { 50926deccbSFrançois Tigeot cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); 51926deccbSFrançois Tigeot if (lock) 52926deccbSFrançois Tigeot cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK; 53926deccbSFrançois Tigeot else 54926deccbSFrançois Tigeot cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK; 55926deccbSFrançois Tigeot WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); 56926deccbSFrançois Tigeot } else { 57926deccbSFrançois Tigeot cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset); 58926deccbSFrançois Tigeot if (lock) 59926deccbSFrançois Tigeot cur_lock |= RADEON_CUR_LOCK; 60926deccbSFrançois Tigeot else 61926deccbSFrançois Tigeot cur_lock &= ~RADEON_CUR_LOCK; 62926deccbSFrançois Tigeot WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock); 63926deccbSFrançois Tigeot } 64926deccbSFrançois Tigeot } 65926deccbSFrançois Tigeot 66926deccbSFrançois Tigeot static void radeon_hide_cursor(struct drm_crtc *crtc) 67926deccbSFrançois Tigeot { 68926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 69926deccbSFrançois Tigeot struct radeon_device *rdev = crtc->dev->dev_private; 70926deccbSFrançois Tigeot 71926deccbSFrançois Tigeot if (ASIC_IS_DCE4(rdev)) { 72926deccbSFrançois Tigeot WREG32_IDX(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset, 73926deccbSFrançois Tigeot EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) | 74926deccbSFrançois Tigeot EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2)); 75926deccbSFrançois Tigeot } else if (ASIC_IS_AVIVO(rdev)) { 76926deccbSFrançois Tigeot WREG32_IDX(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, 77926deccbSFrançois Tigeot (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); 78926deccbSFrançois Tigeot } else { 79926deccbSFrançois Tigeot u32 reg; 80926deccbSFrançois Tigeot switch (radeon_crtc->crtc_id) { 81926deccbSFrançois Tigeot case 0: 82926deccbSFrançois Tigeot reg = RADEON_CRTC_GEN_CNTL; 83926deccbSFrançois Tigeot break; 84926deccbSFrançois Tigeot case 1: 85926deccbSFrançois Tigeot reg = RADEON_CRTC2_GEN_CNTL; 86926deccbSFrançois Tigeot break; 87926deccbSFrançois Tigeot default: 88926deccbSFrançois Tigeot return; 89926deccbSFrançois Tigeot } 90926deccbSFrançois Tigeot WREG32_IDX(reg, RREG32_IDX(reg) & ~RADEON_CRTC_CUR_EN); 91926deccbSFrançois Tigeot } 92926deccbSFrançois Tigeot } 93926deccbSFrançois Tigeot 94926deccbSFrançois Tigeot static void radeon_show_cursor(struct drm_crtc *crtc) 95926deccbSFrançois Tigeot { 96926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 97926deccbSFrançois Tigeot struct radeon_device *rdev = crtc->dev->dev_private; 98926deccbSFrançois Tigeot 99926deccbSFrançois Tigeot if (ASIC_IS_DCE4(rdev)) { 100926deccbSFrançois Tigeot WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); 101926deccbSFrançois Tigeot WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN | 102926deccbSFrançois Tigeot EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) | 103926deccbSFrançois Tigeot EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2)); 104926deccbSFrançois Tigeot } else if (ASIC_IS_AVIVO(rdev)) { 105926deccbSFrançois Tigeot WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); 106926deccbSFrançois Tigeot WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | 107926deccbSFrançois Tigeot (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); 108926deccbSFrançois Tigeot } else { 109926deccbSFrançois Tigeot switch (radeon_crtc->crtc_id) { 110926deccbSFrançois Tigeot case 0: 111926deccbSFrançois Tigeot WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); 112926deccbSFrançois Tigeot break; 113926deccbSFrançois Tigeot case 1: 114926deccbSFrançois Tigeot WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL); 115926deccbSFrançois Tigeot break; 116926deccbSFrançois Tigeot default: 117926deccbSFrançois Tigeot return; 118926deccbSFrançois Tigeot } 119926deccbSFrançois Tigeot 120926deccbSFrançois Tigeot WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN | 121926deccbSFrançois Tigeot (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)), 122926deccbSFrançois Tigeot ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK)); 123926deccbSFrançois Tigeot } 124926deccbSFrançois Tigeot } 125926deccbSFrançois Tigeot 126926deccbSFrançois Tigeot static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj, 127926deccbSFrançois Tigeot uint64_t gpu_addr) 128926deccbSFrançois Tigeot { 129926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 130926deccbSFrançois Tigeot struct radeon_device *rdev = crtc->dev->dev_private; 131926deccbSFrançois Tigeot 132926deccbSFrançois Tigeot if (ASIC_IS_DCE4(rdev)) { 133926deccbSFrançois Tigeot WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 134926deccbSFrançois Tigeot upper_32_bits(gpu_addr)); 135926deccbSFrançois Tigeot WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 136926deccbSFrançois Tigeot gpu_addr & 0xffffffff); 137926deccbSFrançois Tigeot } else if (ASIC_IS_AVIVO(rdev)) { 138926deccbSFrançois Tigeot if (rdev->family >= CHIP_RV770) { 139926deccbSFrançois Tigeot if (radeon_crtc->crtc_id) 140926deccbSFrançois Tigeot WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr)); 141926deccbSFrançois Tigeot else 142926deccbSFrançois Tigeot WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr)); 143926deccbSFrançois Tigeot } 144926deccbSFrançois Tigeot WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 145926deccbSFrançois Tigeot gpu_addr & 0xffffffff); 146926deccbSFrançois Tigeot } else { 147926deccbSFrançois Tigeot radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr; 148926deccbSFrançois Tigeot /* offset is from DISP(2)_BASE_ADDRESS */ 149926deccbSFrançois Tigeot WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset); 150926deccbSFrançois Tigeot } 151926deccbSFrançois Tigeot } 152926deccbSFrançois Tigeot 153926deccbSFrançois Tigeot int radeon_crtc_cursor_set(struct drm_crtc *crtc, 154926deccbSFrançois Tigeot struct drm_file *file_priv, 155926deccbSFrançois Tigeot uint32_t handle, 156926deccbSFrançois Tigeot uint32_t width, 157926deccbSFrançois Tigeot uint32_t height) 158926deccbSFrançois Tigeot { 159926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 160926deccbSFrançois Tigeot struct radeon_device *rdev = crtc->dev->dev_private; 161926deccbSFrançois Tigeot struct drm_gem_object *obj; 162926deccbSFrançois Tigeot struct radeon_bo *robj; 163926deccbSFrançois Tigeot uint64_t gpu_addr; 164926deccbSFrançois Tigeot int ret; 165926deccbSFrançois Tigeot 166926deccbSFrançois Tigeot if (!handle) { 167926deccbSFrançois Tigeot /* turn off cursor */ 168926deccbSFrançois Tigeot radeon_hide_cursor(crtc); 169926deccbSFrançois Tigeot obj = NULL; 170926deccbSFrançois Tigeot goto unpin; 171926deccbSFrançois Tigeot } 172926deccbSFrançois Tigeot 173926deccbSFrançois Tigeot if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) { 174926deccbSFrançois Tigeot DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 175926deccbSFrançois Tigeot return -EINVAL; 176926deccbSFrançois Tigeot } 177926deccbSFrançois Tigeot 178926deccbSFrançois Tigeot obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); 179926deccbSFrançois Tigeot if (!obj) { 180926deccbSFrançois Tigeot DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id); 181926deccbSFrançois Tigeot return -ENOENT; 182926deccbSFrançois Tigeot } 183926deccbSFrançois Tigeot 184926deccbSFrançois Tigeot robj = gem_to_radeon_bo(obj); 185926deccbSFrançois Tigeot ret = radeon_bo_reserve(robj, false); 186926deccbSFrançois Tigeot if (unlikely(ret != 0)) 187926deccbSFrançois Tigeot goto fail; 188926deccbSFrançois Tigeot /* Only 27 bit offset for legacy cursor */ 189926deccbSFrançois Tigeot ret = radeon_bo_pin_restricted(robj, RADEON_GEM_DOMAIN_VRAM, 190926deccbSFrançois Tigeot ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, 191926deccbSFrançois Tigeot &gpu_addr); 192926deccbSFrançois Tigeot radeon_bo_unreserve(robj); 193926deccbSFrançois Tigeot if (ret) 194926deccbSFrançois Tigeot goto fail; 195926deccbSFrançois Tigeot 196926deccbSFrançois Tigeot radeon_crtc->cursor_width = width; 197926deccbSFrançois Tigeot radeon_crtc->cursor_height = height; 198926deccbSFrançois Tigeot 199926deccbSFrançois Tigeot radeon_lock_cursor(crtc, true); 200926deccbSFrançois Tigeot radeon_set_cursor(crtc, obj, gpu_addr); 201926deccbSFrançois Tigeot radeon_show_cursor(crtc); 202926deccbSFrançois Tigeot radeon_lock_cursor(crtc, false); 203926deccbSFrançois Tigeot 204926deccbSFrançois Tigeot unpin: 205926deccbSFrançois Tigeot if (radeon_crtc->cursor_bo) { 206926deccbSFrançois Tigeot robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); 207926deccbSFrançois Tigeot ret = radeon_bo_reserve(robj, false); 208926deccbSFrançois Tigeot if (likely(ret == 0)) { 209926deccbSFrançois Tigeot radeon_bo_unpin(robj); 210926deccbSFrançois Tigeot radeon_bo_unreserve(robj); 211926deccbSFrançois Tigeot } 212926deccbSFrançois Tigeot drm_gem_object_unreference_unlocked(radeon_crtc->cursor_bo); 213926deccbSFrançois Tigeot } 214926deccbSFrançois Tigeot 215926deccbSFrançois Tigeot radeon_crtc->cursor_bo = obj; 216926deccbSFrançois Tigeot return 0; 217926deccbSFrançois Tigeot fail: 218926deccbSFrançois Tigeot drm_gem_object_unreference_unlocked(obj); 219926deccbSFrançois Tigeot 220926deccbSFrançois Tigeot return ret; 221926deccbSFrançois Tigeot } 222926deccbSFrançois Tigeot 223926deccbSFrançois Tigeot int radeon_crtc_cursor_move(struct drm_crtc *crtc, 224926deccbSFrançois Tigeot int x, int y) 225926deccbSFrançois Tigeot { 226926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 227926deccbSFrançois Tigeot struct radeon_device *rdev = crtc->dev->dev_private; 228926deccbSFrançois Tigeot int xorigin = 0, yorigin = 0; 229926deccbSFrançois Tigeot int w = radeon_crtc->cursor_width; 230926deccbSFrançois Tigeot 231926deccbSFrançois Tigeot if (ASIC_IS_AVIVO(rdev)) { 232926deccbSFrançois Tigeot /* avivo cursor are offset into the total surface */ 233926deccbSFrançois Tigeot x += crtc->x; 234926deccbSFrançois Tigeot y += crtc->y; 235926deccbSFrançois Tigeot } 236926deccbSFrançois Tigeot DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 237926deccbSFrançois Tigeot 238926deccbSFrançois Tigeot if (x < 0) { 239926deccbSFrançois Tigeot xorigin = min(-x, CURSOR_WIDTH - 1); 240926deccbSFrançois Tigeot x = 0; 241926deccbSFrançois Tigeot } 242926deccbSFrançois Tigeot if (y < 0) { 243926deccbSFrançois Tigeot yorigin = min(-y, CURSOR_HEIGHT - 1); 244926deccbSFrançois Tigeot y = 0; 245926deccbSFrançois Tigeot } 246926deccbSFrançois Tigeot 247926deccbSFrançois Tigeot /* fixed on DCE6 and newer */ 248926deccbSFrançois Tigeot if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE6(rdev)) { 249926deccbSFrançois Tigeot int i = 0; 250926deccbSFrançois Tigeot struct drm_crtc *crtc_p; 251926deccbSFrançois Tigeot 252*b403bed8SMichael Neumann /* 253*b403bed8SMichael Neumann * avivo cursor image can't end on 128 pixel boundary or 254926deccbSFrançois Tigeot * go past the end of the frame if both crtcs are enabled 255*b403bed8SMichael Neumann * 256*b403bed8SMichael Neumann * NOTE: It is safe to access crtc->enabled of other crtcs 257*b403bed8SMichael Neumann * without holding either the mode_config lock or the other 258*b403bed8SMichael Neumann * crtc's lock as long as write access to this flag _always_ 259*b403bed8SMichael Neumann * grabs all locks. 260926deccbSFrançois Tigeot */ 261926deccbSFrançois Tigeot list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) { 262926deccbSFrançois Tigeot if (crtc_p->enabled) 263926deccbSFrançois Tigeot i++; 264926deccbSFrançois Tigeot } 265926deccbSFrançois Tigeot if (i > 1) { 266926deccbSFrançois Tigeot int cursor_end, frame_end; 267926deccbSFrançois Tigeot 268926deccbSFrançois Tigeot cursor_end = x - xorigin + w; 269926deccbSFrançois Tigeot frame_end = crtc->x + crtc->mode.crtc_hdisplay; 270926deccbSFrançois Tigeot if (cursor_end >= frame_end) { 271926deccbSFrançois Tigeot w = w - (cursor_end - frame_end); 272926deccbSFrançois Tigeot if (!(frame_end & 0x7f)) 273926deccbSFrançois Tigeot w--; 274926deccbSFrançois Tigeot } else { 275926deccbSFrançois Tigeot if (!(cursor_end & 0x7f)) 276926deccbSFrançois Tigeot w--; 277926deccbSFrançois Tigeot } 278926deccbSFrançois Tigeot if (w <= 0) { 279926deccbSFrançois Tigeot w = 1; 280926deccbSFrançois Tigeot cursor_end = x - xorigin + w; 281926deccbSFrançois Tigeot if (!(cursor_end & 0x7f)) { 282926deccbSFrançois Tigeot x--; 283926deccbSFrançois Tigeot if (x < 0) { 284926deccbSFrançois Tigeot DRM_ERROR("%s: x(%d) < 0", __func__, x); 285926deccbSFrançois Tigeot } 286926deccbSFrançois Tigeot } 287926deccbSFrançois Tigeot } 288926deccbSFrançois Tigeot } 289926deccbSFrançois Tigeot } 290926deccbSFrançois Tigeot 291926deccbSFrançois Tigeot radeon_lock_cursor(crtc, true); 292926deccbSFrançois Tigeot if (ASIC_IS_DCE4(rdev)) { 293926deccbSFrançois Tigeot WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y); 294926deccbSFrançois Tigeot WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); 295926deccbSFrançois Tigeot WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset, 296926deccbSFrançois Tigeot ((w - 1) << 16) | (radeon_crtc->cursor_height - 1)); 297926deccbSFrançois Tigeot } else if (ASIC_IS_AVIVO(rdev)) { 298926deccbSFrançois Tigeot WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y); 299926deccbSFrançois Tigeot WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); 300926deccbSFrançois Tigeot WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, 301926deccbSFrançois Tigeot ((w - 1) << 16) | (radeon_crtc->cursor_height - 1)); 302926deccbSFrançois Tigeot } else { 303926deccbSFrançois Tigeot if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN) 304926deccbSFrançois Tigeot y *= 2; 305926deccbSFrançois Tigeot 306926deccbSFrançois Tigeot WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset, 307926deccbSFrançois Tigeot (RADEON_CUR_LOCK 308926deccbSFrançois Tigeot | (xorigin << 16) 309926deccbSFrançois Tigeot | yorigin)); 310926deccbSFrançois Tigeot WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset, 311926deccbSFrançois Tigeot (RADEON_CUR_LOCK 312926deccbSFrançois Tigeot | (x << 16) 313926deccbSFrançois Tigeot | y)); 314926deccbSFrançois Tigeot /* offset is from DISP(2)_BASE_ADDRESS */ 315926deccbSFrançois Tigeot WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset + 316926deccbSFrançois Tigeot (yorigin * 256))); 317926deccbSFrançois Tigeot } 318926deccbSFrançois Tigeot radeon_lock_cursor(crtc, false); 319926deccbSFrançois Tigeot 320926deccbSFrançois Tigeot return 0; 321926deccbSFrançois Tigeot } 322