1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * 28 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_device.c 255573 2013-09-14 17:24:41Z dumbbell $ 29 */ 30 #include <drm/drmP.h> 31 #include "drm/drm_legacy.h" /* for drm_dma_handle_t */ 32 #include <drm/drm_crtc_helper.h> 33 #include <drm/radeon_drm.h> 34 #include <asm/io.h> 35 #include "radeon_reg.h" 36 #include "radeon.h" 37 #include "atom.h" 38 39 static const char radeon_family_name[][16] = { 40 "R100", 41 "RV100", 42 "RS100", 43 "RV200", 44 "RS200", 45 "R200", 46 "RV250", 47 "RS300", 48 "RV280", 49 "R300", 50 "R350", 51 "RV350", 52 "RV380", 53 "R420", 54 "R423", 55 "RV410", 56 "RS400", 57 "RS480", 58 "RS600", 59 "RS690", 60 "RS740", 61 "RV515", 62 "R520", 63 "RV530", 64 "RV560", 65 "RV570", 66 "R580", 67 "R600", 68 "RV610", 69 "RV630", 70 "RV670", 71 "RV620", 72 "RV635", 73 "RS780", 74 "RS880", 75 "RV770", 76 "RV730", 77 "RV710", 78 "RV740", 79 "CEDAR", 80 "REDWOOD", 81 "JUNIPER", 82 "CYPRESS", 83 "HEMLOCK", 84 "PALM", 85 "SUMO", 86 "SUMO2", 87 "BARTS", 88 "TURKS", 89 "CAICOS", 90 "CAYMAN", 91 "ARUBA", 92 "TAHITI", 93 "PITCAIRN", 94 "VERDE", 95 "OLAND", 96 "HAINAN", 97 "BONAIRE", 98 "KAVERI", 99 "KABINI", 100 "HAWAII", 101 "MULLINS", 102 "LAST", 103 }; 104 105 #define RADEON_PX_QUIRK_DISABLE_PX (1 << 0) 106 #define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1) 107 108 struct radeon_px_quirk { 109 u32 chip_vendor; 110 u32 chip_device; 111 u32 subsys_vendor; 112 u32 subsys_device; 113 u32 px_quirk_flags; 114 }; 115 116 static struct radeon_px_quirk radeon_px_quirk_list[] = { 117 /* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m) 118 * https://bugzilla.kernel.org/show_bug.cgi?id=74551 119 */ 120 { PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX }, 121 /* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU 122 * https://bugzilla.kernel.org/show_bug.cgi?id=51381 123 */ 124 { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX }, 125 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU 126 * https://bugzilla.kernel.org/show_bug.cgi?id=51381 127 */ 128 { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX }, 129 /* macbook pro 8.2 */ 130 { PCI_VENDOR_ID_ATI, 0x6741, PCI_VENDOR_ID_APPLE, 0x00e2, RADEON_PX_QUIRK_LONG_WAKEUP }, 131 { 0, 0, 0, 0, 0 }, 132 }; 133 134 bool radeon_is_px(struct drm_device *dev) 135 { 136 struct radeon_device *rdev = dev->dev_private; 137 138 if (rdev->flags & RADEON_IS_PX) 139 return true; 140 return false; 141 } 142 143 static void radeon_device_handle_px_quirks(struct radeon_device *rdev) 144 { 145 struct radeon_px_quirk *p = radeon_px_quirk_list; 146 147 /* Apply PX quirks */ 148 while (p && p->chip_device != 0) { 149 if (rdev->pdev->vendor == p->chip_vendor && 150 rdev->pdev->device == p->chip_device && 151 rdev->pdev->subsystem_vendor == p->subsys_vendor && 152 rdev->pdev->subsystem_device == p->subsys_device) { 153 rdev->px_quirk_flags = p->px_quirk_flags; 154 break; 155 } 156 ++p; 157 } 158 159 if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX) 160 rdev->flags &= ~RADEON_IS_PX; 161 } 162 163 /** 164 * radeon_program_register_sequence - program an array of registers. 165 * 166 * @rdev: radeon_device pointer 167 * @registers: pointer to the register array 168 * @array_size: size of the register array 169 * 170 * Programs an array or registers with and and or masks. 171 * This is a helper for setting golden registers. 172 */ 173 void radeon_program_register_sequence(struct radeon_device *rdev, 174 const u32 *registers, 175 const u32 array_size) 176 { 177 u32 tmp, reg, and_mask, or_mask; 178 int i; 179 180 if (array_size % 3) 181 return; 182 183 for (i = 0; i < array_size; i +=3) { 184 reg = registers[i + 0]; 185 and_mask = registers[i + 1]; 186 or_mask = registers[i + 2]; 187 188 if (and_mask == 0xffffffff) { 189 tmp = or_mask; 190 } else { 191 tmp = RREG32(reg); 192 tmp &= ~and_mask; 193 tmp |= or_mask; 194 } 195 WREG32(reg, tmp); 196 } 197 } 198 199 void radeon_pci_config_reset(struct radeon_device *rdev) 200 { 201 pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA); 202 } 203 204 /** 205 * radeon_surface_init - Clear GPU surface registers. 206 * 207 * @rdev: radeon_device pointer 208 * 209 * Clear GPU surface registers (r1xx-r5xx). 210 */ 211 void radeon_surface_init(struct radeon_device *rdev) 212 { 213 /* FIXME: check this out */ 214 if (rdev->family < CHIP_R600) { 215 int i; 216 217 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 218 if (rdev->surface_regs[i].bo) 219 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); 220 else 221 radeon_clear_surface_reg(rdev, i); 222 } 223 /* enable surfaces */ 224 WREG32(RADEON_SURFACE_CNTL, 0); 225 } 226 } 227 228 /* 229 * GPU scratch registers helpers function. 230 */ 231 /** 232 * radeon_scratch_init - Init scratch register driver information. 233 * 234 * @rdev: radeon_device pointer 235 * 236 * Init CP scratch register driver information (r1xx-r5xx) 237 */ 238 void radeon_scratch_init(struct radeon_device *rdev) 239 { 240 int i; 241 242 /* FIXME: check this out */ 243 if (rdev->family < CHIP_R300) { 244 rdev->scratch.num_reg = 5; 245 } else { 246 rdev->scratch.num_reg = 7; 247 } 248 rdev->scratch.reg_base = RADEON_SCRATCH_REG0; 249 for (i = 0; i < rdev->scratch.num_reg; i++) { 250 rdev->scratch.free[i] = true; 251 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 252 } 253 } 254 255 /** 256 * radeon_scratch_get - Allocate a scratch register 257 * 258 * @rdev: radeon_device pointer 259 * @reg: scratch register mmio offset 260 * 261 * Allocate a CP scratch register for use by the driver (all asics). 262 * Returns 0 on success or -EINVAL on failure. 263 */ 264 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) 265 { 266 int i; 267 268 for (i = 0; i < rdev->scratch.num_reg; i++) { 269 if (rdev->scratch.free[i]) { 270 rdev->scratch.free[i] = false; 271 *reg = rdev->scratch.reg[i]; 272 return 0; 273 } 274 } 275 return -EINVAL; 276 } 277 278 /** 279 * radeon_scratch_free - Free a scratch register 280 * 281 * @rdev: radeon_device pointer 282 * @reg: scratch register mmio offset 283 * 284 * Free a CP scratch register allocated for use by the driver (all asics) 285 */ 286 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) 287 { 288 int i; 289 290 for (i = 0; i < rdev->scratch.num_reg; i++) { 291 if (rdev->scratch.reg[i] == reg) { 292 rdev->scratch.free[i] = true; 293 return; 294 } 295 } 296 } 297 298 /* 299 * GPU doorbell aperture helpers function. 300 */ 301 /** 302 * radeon_doorbell_init - Init doorbell driver information. 303 * 304 * @rdev: radeon_device pointer 305 * 306 * Init doorbell driver information (CIK) 307 * Returns 0 on success, error on failure. 308 */ 309 static int radeon_doorbell_init(struct radeon_device *rdev) 310 { 311 /* doorbell bar mapping */ 312 rdev->doorbell.base = pci_resource_start(rdev->pdev, 2); 313 rdev->doorbell.size = pci_resource_len(rdev->pdev, 2); 314 315 rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS); 316 if (rdev->doorbell.num_doorbells == 0) 317 return -EINVAL; 318 319 rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32)); 320 if (rdev->doorbell.ptr == NULL) { 321 return -ENOMEM; 322 } 323 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base); 324 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size); 325 326 memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used)); 327 328 return 0; 329 } 330 331 /** 332 * radeon_doorbell_fini - Tear down doorbell driver information. 333 * 334 * @rdev: radeon_device pointer 335 * 336 * Tear down doorbell driver information (CIK) 337 */ 338 static void radeon_doorbell_fini(struct radeon_device *rdev) 339 { 340 iounmap(rdev->doorbell.ptr); 341 rdev->doorbell.ptr = NULL; 342 } 343 344 /** 345 * radeon_doorbell_get - Allocate a doorbell entry 346 * 347 * @rdev: radeon_device pointer 348 * @doorbell: doorbell index 349 * 350 * Allocate a doorbell for use by the driver (all asics). 351 * Returns 0 on success or -EINVAL on failure. 352 */ 353 int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell) 354 { 355 unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells); 356 if (offset < rdev->doorbell.num_doorbells) { 357 __set_bit(offset, rdev->doorbell.used); 358 *doorbell = offset; 359 return 0; 360 } else { 361 return -EINVAL; 362 } 363 } 364 365 /** 366 * radeon_doorbell_free - Free a doorbell entry 367 * 368 * @rdev: radeon_device pointer 369 * @doorbell: doorbell index 370 * 371 * Free a doorbell allocated for use by the driver (all asics) 372 */ 373 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell) 374 { 375 if (doorbell < rdev->doorbell.num_doorbells) 376 __clear_bit(doorbell, rdev->doorbell.used); 377 } 378 379 /* 380 * radeon_wb_*() 381 * Writeback is the the method by which the the GPU updates special pages 382 * in memory with the status of certain GPU events (fences, ring pointers, 383 * etc.). 384 */ 385 386 /** 387 * radeon_wb_disable - Disable Writeback 388 * 389 * @rdev: radeon_device pointer 390 * 391 * Disables Writeback (all asics). Used for suspend. 392 */ 393 void radeon_wb_disable(struct radeon_device *rdev) 394 { 395 rdev->wb.enabled = false; 396 } 397 398 /** 399 * radeon_wb_fini - Disable Writeback and free memory 400 * 401 * @rdev: radeon_device pointer 402 * 403 * Disables Writeback and frees the Writeback memory (all asics). 404 * Used at driver shutdown. 405 */ 406 void radeon_wb_fini(struct radeon_device *rdev) 407 { 408 radeon_wb_disable(rdev); 409 if (rdev->wb.wb_obj) { 410 if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) { 411 radeon_bo_kunmap(rdev->wb.wb_obj); 412 radeon_bo_unpin(rdev->wb.wb_obj); 413 radeon_bo_unreserve(rdev->wb.wb_obj); 414 } 415 radeon_bo_unref(&rdev->wb.wb_obj); 416 rdev->wb.wb = NULL; 417 rdev->wb.wb_obj = NULL; 418 } 419 } 420 421 /** 422 * radeon_wb_init- Init Writeback driver info and allocate memory 423 * 424 * @rdev: radeon_device pointer 425 * 426 * Disables Writeback and frees the Writeback memory (all asics). 427 * Used at driver startup. 428 * Returns 0 on success or an -error on failure. 429 */ 430 int radeon_wb_init(struct radeon_device *rdev) 431 { 432 int r; 433 void *wb_ptr; 434 435 if (rdev->wb.wb_obj == NULL) { 436 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, 437 RADEON_GEM_DOMAIN_GTT, 0, NULL, 438 &rdev->wb.wb_obj); 439 if (r) { 440 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); 441 return r; 442 } 443 r = radeon_bo_reserve(rdev->wb.wb_obj, false); 444 if (unlikely(r != 0)) { 445 radeon_wb_fini(rdev); 446 return r; 447 } 448 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, 449 (u64 *)&rdev->wb.gpu_addr); 450 if (r) { 451 radeon_bo_unreserve(rdev->wb.wb_obj); 452 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); 453 radeon_wb_fini(rdev); 454 return r; 455 } 456 wb_ptr = &rdev->wb.wb; 457 r = radeon_bo_kmap(rdev->wb.wb_obj, wb_ptr); 458 radeon_bo_unreserve(rdev->wb.wb_obj); 459 if (r) { 460 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); 461 radeon_wb_fini(rdev); 462 return r; 463 } 464 /* clear wb memory */ 465 memset(*(void **)wb_ptr, 0, RADEON_GPU_PAGE_SIZE); 466 } 467 468 /* disable event_write fences */ 469 rdev->wb.use_event = false; 470 /* disabled via module param */ 471 if (radeon_no_wb == 1) { 472 rdev->wb.enabled = false; 473 } else { 474 if (rdev->flags & RADEON_IS_AGP) { 475 /* often unreliable on AGP */ 476 rdev->wb.enabled = false; 477 } else if (rdev->family < CHIP_R300) { 478 /* often unreliable on pre-r300 */ 479 rdev->wb.enabled = false; 480 } else { 481 rdev->wb.enabled = true; 482 /* event_write fences are only available on r600+ */ 483 if (rdev->family >= CHIP_R600) { 484 rdev->wb.use_event = true; 485 } 486 } 487 } 488 /* always use writeback/events on NI, APUs */ 489 if (rdev->family >= CHIP_PALM) { 490 rdev->wb.enabled = true; 491 rdev->wb.use_event = true; 492 } 493 494 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis"); 495 496 return 0; 497 } 498 499 /** 500 * radeon_vram_location - try to find VRAM location 501 * @rdev: radeon device structure holding all necessary informations 502 * @mc: memory controller structure holding memory informations 503 * @base: base address at which to put VRAM 504 * 505 * Function will place try to place VRAM at base address provided 506 * as parameter (which is so far either PCI aperture address or 507 * for IGP TOM base address). 508 * 509 * If there is not enough space to fit the unvisible VRAM in the 32bits 510 * address space then we limit the VRAM size to the aperture. 511 * 512 * If we are using AGP and if the AGP aperture doesn't allow us to have 513 * room for all the VRAM than we restrict the VRAM to the PCI aperture 514 * size and print a warning. 515 * 516 * This function will never fails, worst case are limiting VRAM. 517 * 518 * Note: GTT start, end, size should be initialized before calling this 519 * function on AGP platform. 520 * 521 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, 522 * this shouldn't be a problem as we are using the PCI aperture as a reference. 523 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but 524 * not IGP. 525 * 526 * Note: we use mc_vram_size as on some board we need to program the mc to 527 * cover the whole aperture even if VRAM size is inferior to aperture size 528 * Novell bug 204882 + along with lots of ubuntu ones 529 * 530 * Note: when limiting vram it's safe to overwritte real_vram_size because 531 * we are not in case where real_vram_size is inferior to mc_vram_size (ie 532 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu 533 * ones) 534 * 535 * Note: IGP TOM addr should be the same as the aperture addr, we don't 536 * explicitly check for that thought. 537 * 538 * FIXME: when reducing VRAM size align new size on power of 2. 539 */ 540 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) 541 { 542 uint64_t limit = (uint64_t)radeon_vram_limit << 20; 543 544 mc->vram_start = base; 545 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) { 546 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 547 mc->real_vram_size = mc->aper_size; 548 mc->mc_vram_size = mc->aper_size; 549 } 550 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 551 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { 552 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 553 mc->real_vram_size = mc->aper_size; 554 mc->mc_vram_size = mc->aper_size; 555 } 556 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 557 if (limit && limit < mc->real_vram_size) 558 mc->real_vram_size = limit; 559 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 560 mc->mc_vram_size >> 20, mc->vram_start, 561 mc->vram_end, mc->real_vram_size >> 20); 562 } 563 564 /** 565 * radeon_gtt_location - try to find GTT location 566 * @rdev: radeon device structure holding all necessary informations 567 * @mc: memory controller structure holding memory informations 568 * 569 * Function will place try to place GTT before or after VRAM. 570 * 571 * If GTT size is bigger than space left then we ajust GTT size. 572 * Thus function will never fails. 573 * 574 * FIXME: when reducing GTT size align new size on power of 2. 575 */ 576 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 577 { 578 u64 size_af, size_bf; 579 580 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; 581 size_bf = mc->vram_start & ~mc->gtt_base_align; 582 if (size_bf > size_af) { 583 if (mc->gtt_size > size_bf) { 584 dev_warn(rdev->dev, "limiting GTT\n"); 585 mc->gtt_size = size_bf; 586 } 587 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; 588 } else { 589 if (mc->gtt_size > size_af) { 590 dev_warn(rdev->dev, "limiting GTT\n"); 591 mc->gtt_size = size_af; 592 } 593 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; 594 } 595 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; 596 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", 597 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); 598 } 599 600 /* 601 * GPU helpers function. 602 */ 603 /** 604 * radeon_card_posted - check if the hw has already been initialized 605 * 606 * @rdev: radeon_device pointer 607 * 608 * Check if the asic has been initialized (all asics). 609 * Used at driver startup. 610 * Returns true if initialized or false if not. 611 */ 612 bool radeon_card_posted(struct radeon_device *rdev) 613 { 614 uint32_t reg; 615 616 #ifdef DUMBBELL_WIP 617 /* required for EFI mode on macbook2,1 which uses an r5xx asic */ 618 if (efi_enabled(EFI_BOOT) && 619 (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && 620 (rdev->family < CHIP_R600)) 621 return false; 622 #endif /* DUMBBELL_WIP */ 623 624 if (ASIC_IS_NODCE(rdev)) 625 goto check_memsize; 626 627 /* first check CRTCs */ 628 if (ASIC_IS_DCE4(rdev)) { 629 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | 630 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 631 if (rdev->num_crtc >= 4) { 632 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | 633 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 634 } 635 if (rdev->num_crtc >= 6) { 636 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | 637 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 638 } 639 if (reg & EVERGREEN_CRTC_MASTER_EN) 640 return true; 641 } else if (ASIC_IS_AVIVO(rdev)) { 642 reg = RREG32(AVIVO_D1CRTC_CONTROL) | 643 RREG32(AVIVO_D2CRTC_CONTROL); 644 if (reg & AVIVO_CRTC_EN) { 645 return true; 646 } 647 } else { 648 reg = RREG32(RADEON_CRTC_GEN_CNTL) | 649 RREG32(RADEON_CRTC2_GEN_CNTL); 650 if (reg & RADEON_CRTC_EN) { 651 return true; 652 } 653 } 654 655 check_memsize: 656 /* then check MEM_SIZE, in case the crtcs are off */ 657 if (rdev->family >= CHIP_R600) 658 reg = RREG32(R600_CONFIG_MEMSIZE); 659 else 660 reg = RREG32(RADEON_CONFIG_MEMSIZE); 661 662 if (reg) 663 return true; 664 665 return false; 666 667 } 668 669 /** 670 * radeon_update_bandwidth_info - update display bandwidth params 671 * 672 * @rdev: radeon_device pointer 673 * 674 * Used when sclk/mclk are switched or display modes are set. 675 * params are used to calculate display watermarks (all asics) 676 */ 677 void radeon_update_bandwidth_info(struct radeon_device *rdev) 678 { 679 fixed20_12 a; 680 u32 sclk = rdev->pm.current_sclk; 681 u32 mclk = rdev->pm.current_mclk; 682 683 /* sclk/mclk in Mhz */ 684 a.full = dfixed_const(100); 685 rdev->pm.sclk.full = dfixed_const(sclk); 686 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); 687 rdev->pm.mclk.full = dfixed_const(mclk); 688 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); 689 690 if (rdev->flags & RADEON_IS_IGP) { 691 a.full = dfixed_const(16); 692 /* core_bandwidth = sclk(Mhz) * 16 */ 693 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); 694 } 695 } 696 697 /** 698 * radeon_boot_test_post_card - check and possibly initialize the hw 699 * 700 * @rdev: radeon_device pointer 701 * 702 * Check if the asic is initialized and if not, attempt to initialize 703 * it (all asics). 704 * Returns true if initialized or false if not. 705 */ 706 bool radeon_boot_test_post_card(struct radeon_device *rdev) 707 { 708 if (radeon_card_posted(rdev)) 709 return true; 710 711 if (rdev->bios) { 712 DRM_INFO("GPU not posted. posting now...\n"); 713 if (rdev->is_atom_bios) 714 atom_asic_init(rdev->mode_info.atom_context); 715 else 716 radeon_combios_asic_init(rdev->ddev); 717 return true; 718 } else { 719 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 720 return false; 721 } 722 } 723 724 /** 725 * radeon_dummy_page_init - init dummy page used by the driver 726 * 727 * @rdev: radeon_device pointer 728 * 729 * Allocate the dummy page used by the driver (all asics). 730 * This dummy page is used by the driver as a filler for gart entries 731 * when pages are taken out of the GART 732 * Returns 0 on sucess, -ENOMEM on failure. 733 */ 734 int radeon_dummy_page_init(struct radeon_device *rdev) 735 { 736 if (rdev->dummy_page.dmah) 737 return 0; 738 rdev->dummy_page.dmah = drm_pci_alloc(rdev->ddev, 739 PAGE_SIZE, PAGE_SIZE); 740 if (rdev->dummy_page.dmah == NULL) 741 return -ENOMEM; 742 rdev->dummy_page.addr = 743 (dma_addr_t)rdev->dummy_page.dmah->busaddr; 744 return 0; 745 } 746 747 /** 748 * radeon_dummy_page_fini - free dummy page used by the driver 749 * 750 * @rdev: radeon_device pointer 751 * 752 * Frees the dummy page used by the driver (all asics). 753 */ 754 void radeon_dummy_page_fini(struct radeon_device *rdev) 755 { 756 if (rdev->dummy_page.dmah == NULL) 757 return; 758 drm_pci_free(rdev->ddev, rdev->dummy_page.dmah); 759 rdev->dummy_page.dmah = NULL; 760 rdev->dummy_page.addr = 0; 761 } 762 763 764 /* ATOM accessor methods */ 765 /* 766 * ATOM is an interpreted byte code stored in tables in the vbios. The 767 * driver registers callbacks to access registers and the interpreter 768 * in the driver parses the tables and executes then to program specific 769 * actions (set display modes, asic init, etc.). See radeon_atombios.c, 770 * atombios.h, and atom.c 771 */ 772 773 /** 774 * cail_pll_read - read PLL register 775 * 776 * @info: atom card_info pointer 777 * @reg: PLL register offset 778 * 779 * Provides a PLL register accessor for the atom interpreter (r4xx+). 780 * Returns the value of the PLL register. 781 */ 782 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) 783 { 784 struct radeon_device *rdev = info->dev->dev_private; 785 uint32_t r; 786 787 r = rdev->pll_rreg(rdev, reg); 788 return r; 789 } 790 791 /** 792 * cail_pll_write - write PLL register 793 * 794 * @info: atom card_info pointer 795 * @reg: PLL register offset 796 * @val: value to write to the pll register 797 * 798 * Provides a PLL register accessor for the atom interpreter (r4xx+). 799 */ 800 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) 801 { 802 struct radeon_device *rdev = info->dev->dev_private; 803 804 rdev->pll_wreg(rdev, reg, val); 805 } 806 807 /** 808 * cail_mc_read - read MC (Memory Controller) register 809 * 810 * @info: atom card_info pointer 811 * @reg: MC register offset 812 * 813 * Provides an MC register accessor for the atom interpreter (r4xx+). 814 * Returns the value of the MC register. 815 */ 816 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) 817 { 818 struct radeon_device *rdev = info->dev->dev_private; 819 uint32_t r; 820 821 r = rdev->mc_rreg(rdev, reg); 822 return r; 823 } 824 825 /** 826 * cail_mc_write - write MC (Memory Controller) register 827 * 828 * @info: atom card_info pointer 829 * @reg: MC register offset 830 * @val: value to write to the pll register 831 * 832 * Provides a MC register accessor for the atom interpreter (r4xx+). 833 */ 834 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) 835 { 836 struct radeon_device *rdev = info->dev->dev_private; 837 838 rdev->mc_wreg(rdev, reg, val); 839 } 840 841 /** 842 * cail_reg_write - write MMIO register 843 * 844 * @info: atom card_info pointer 845 * @reg: MMIO register offset 846 * @val: value to write to the pll register 847 * 848 * Provides a MMIO register accessor for the atom interpreter (r4xx+). 849 */ 850 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) 851 { 852 struct radeon_device *rdev = info->dev->dev_private; 853 854 WREG32(reg*4, val); 855 } 856 857 /** 858 * cail_reg_read - read MMIO register 859 * 860 * @info: atom card_info pointer 861 * @reg: MMIO register offset 862 * 863 * Provides an MMIO register accessor for the atom interpreter (r4xx+). 864 * Returns the value of the MMIO register. 865 */ 866 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) 867 { 868 struct radeon_device *rdev = info->dev->dev_private; 869 uint32_t r; 870 871 r = RREG32(reg*4); 872 return r; 873 } 874 875 /** 876 * cail_ioreg_write - write IO register 877 * 878 * @info: atom card_info pointer 879 * @reg: IO register offset 880 * @val: value to write to the pll register 881 * 882 * Provides a IO register accessor for the atom interpreter (r4xx+). 883 */ 884 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) 885 { 886 struct radeon_device *rdev = info->dev->dev_private; 887 888 WREG32_IO(reg*4, val); 889 } 890 891 /** 892 * cail_ioreg_read - read IO register 893 * 894 * @info: atom card_info pointer 895 * @reg: IO register offset 896 * 897 * Provides an IO register accessor for the atom interpreter (r4xx+). 898 * Returns the value of the IO register. 899 */ 900 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) 901 { 902 struct radeon_device *rdev = info->dev->dev_private; 903 uint32_t r; 904 905 r = RREG32_IO(reg*4); 906 return r; 907 } 908 909 /** 910 * radeon_atombios_init - init the driver info and callbacks for atombios 911 * 912 * @rdev: radeon_device pointer 913 * 914 * Initializes the driver info and register access callbacks for the 915 * ATOM interpreter (r4xx+). 916 * Returns 0 on sucess, -ENOMEM on failure. 917 * Called at driver startup. 918 */ 919 int radeon_atombios_init(struct radeon_device *rdev) 920 { 921 struct card_info *atom_card_info = 922 kzalloc(sizeof(struct card_info), GFP_KERNEL); 923 924 if (!atom_card_info) 925 return -ENOMEM; 926 927 rdev->mode_info.atom_card_info = atom_card_info; 928 atom_card_info->dev = rdev->ddev; 929 atom_card_info->reg_read = cail_reg_read; 930 atom_card_info->reg_write = cail_reg_write; 931 /* needed for iio ops */ 932 if (rdev->rio_mem) { 933 atom_card_info->ioreg_read = cail_ioreg_read; 934 atom_card_info->ioreg_write = cail_ioreg_write; 935 } else { 936 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); 937 atom_card_info->ioreg_read = cail_reg_read; 938 atom_card_info->ioreg_write = cail_reg_write; 939 } 940 atom_card_info->mc_read = cail_mc_read; 941 atom_card_info->mc_write = cail_mc_write; 942 atom_card_info->pll_read = cail_pll_read; 943 atom_card_info->pll_write = cail_pll_write; 944 945 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); 946 if (!rdev->mode_info.atom_context) { 947 radeon_atombios_fini(rdev); 948 return -ENOMEM; 949 } 950 951 lockinit(&rdev->mode_info.atom_context->mutex, "rmiacmtx", 0, LK_CANRECURSE); 952 lockinit(&rdev->mode_info.atom_context->scratch_mutex, "rmiacsmtx", 0, LK_CANRECURSE); 953 radeon_atom_initialize_bios_scratch_regs(rdev->ddev); 954 atom_allocate_fb_scratch(rdev->mode_info.atom_context); 955 return 0; 956 } 957 958 /** 959 * radeon_atombios_fini - free the driver info and callbacks for atombios 960 * 961 * @rdev: radeon_device pointer 962 * 963 * Frees the driver info and register access callbacks for the ATOM 964 * interpreter (r4xx+). 965 * Called at driver shutdown. 966 */ 967 void radeon_atombios_fini(struct radeon_device *rdev) 968 { 969 if (rdev->mode_info.atom_context) { 970 /* prevents leaking 512 bytes */ 971 kfree(rdev->mode_info.atom_context->iio); 972 973 kfree(rdev->mode_info.atom_context->scratch); 974 } 975 kfree(rdev->mode_info.atom_context); 976 rdev->mode_info.atom_context = NULL; 977 kfree(rdev->mode_info.atom_card_info); 978 rdev->mode_info.atom_card_info = NULL; 979 } 980 981 /* COMBIOS */ 982 /* 983 * COMBIOS is the bios format prior to ATOM. It provides 984 * command tables similar to ATOM, but doesn't have a unified 985 * parser. See radeon_combios.c 986 */ 987 988 /** 989 * radeon_combios_init - init the driver info for combios 990 * 991 * @rdev: radeon_device pointer 992 * 993 * Initializes the driver info for combios (r1xx-r3xx). 994 * Returns 0 on sucess. 995 * Called at driver startup. 996 */ 997 int radeon_combios_init(struct radeon_device *rdev) 998 { 999 radeon_combios_initialize_bios_scratch_regs(rdev->ddev); 1000 return 0; 1001 } 1002 1003 /** 1004 * radeon_combios_fini - free the driver info for combios 1005 * 1006 * @rdev: radeon_device pointer 1007 * 1008 * Frees the driver info for combios (r1xx-r3xx). 1009 * Called at driver shutdown. 1010 */ 1011 void radeon_combios_fini(struct radeon_device *rdev) 1012 { 1013 } 1014 1015 #ifdef DUMBBELL_WIP 1016 /* if we get transitioned to only one device, take VGA back */ 1017 /** 1018 * radeon_vga_set_decode - enable/disable vga decode 1019 * 1020 * @cookie: radeon_device pointer 1021 * @state: enable/disable vga decode 1022 * 1023 * Enable/disable vga decode (all asics). 1024 * Returns VGA resource flags. 1025 */ 1026 static unsigned int radeon_vga_set_decode(void *cookie, bool state) 1027 { 1028 struct radeon_device *rdev = cookie; 1029 radeon_vga_set_state(rdev, state); 1030 if (state) 1031 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | 1032 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 1033 else 1034 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 1035 } 1036 #endif /* DUMBBELL_WIP */ 1037 1038 /** 1039 * radeon_check_pot_argument - check that argument is a power of two 1040 * 1041 * @arg: value to check 1042 * 1043 * Validates that a certain argument is a power of two (all asics). 1044 * Returns true if argument is valid. 1045 */ 1046 static bool radeon_check_pot_argument(int arg) 1047 { 1048 return (arg & (arg - 1)) == 0; 1049 } 1050 1051 /** 1052 * radeon_check_arguments - validate module params 1053 * 1054 * @rdev: radeon_device pointer 1055 * 1056 * Validates certain module parameters and updates 1057 * the associated values used by the driver (all asics). 1058 */ 1059 static void radeon_check_arguments(struct radeon_device *rdev) 1060 { 1061 /* vramlimit must be a power of two */ 1062 if (!radeon_check_pot_argument(radeon_vram_limit)) { 1063 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", 1064 radeon_vram_limit); 1065 radeon_vram_limit = 0; 1066 } 1067 1068 if (radeon_gart_size == -1) { 1069 /* default to a larger gart size on newer asics */ 1070 if (rdev->family >= CHIP_RV770) 1071 radeon_gart_size = 1024; 1072 else 1073 radeon_gart_size = 512; 1074 } 1075 /* gtt size must be power of two and greater or equal to 32M */ 1076 if (radeon_gart_size < 32) { 1077 dev_warn(rdev->dev, "gart size (%d) too small\n", 1078 radeon_gart_size); 1079 if (rdev->family >= CHIP_RV770) 1080 radeon_gart_size = 1024; 1081 else 1082 radeon_gart_size = 512; 1083 } else if (!radeon_check_pot_argument(radeon_gart_size)) { 1084 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", 1085 radeon_gart_size); 1086 if (rdev->family >= CHIP_RV770) 1087 radeon_gart_size = 1024; 1088 else 1089 radeon_gart_size = 512; 1090 } 1091 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20; 1092 1093 /* AGP mode can only be -1, 1, 2, 4, 8 */ 1094 switch (radeon_agpmode) { 1095 case -1: 1096 case 0: 1097 case 1: 1098 case 2: 1099 case 4: 1100 case 8: 1101 break; 1102 default: 1103 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " 1104 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); 1105 radeon_agpmode = 0; 1106 break; 1107 } 1108 1109 if (!radeon_check_pot_argument(radeon_vm_size)) { 1110 dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n", 1111 radeon_vm_size); 1112 radeon_vm_size = 4; 1113 } 1114 1115 if (radeon_vm_size < 1) { 1116 dev_warn(rdev->dev, "VM size (%d) to small, min is 1GB\n", 1117 radeon_vm_size); 1118 radeon_vm_size = 4; 1119 } 1120 1121 /* 1122 * Max GPUVM size for Cayman, SI and CI are 40 bits. 1123 */ 1124 if (radeon_vm_size > 1024) { 1125 dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n", 1126 radeon_vm_size); 1127 radeon_vm_size = 4; 1128 } 1129 1130 /* defines number of bits in page table versus page directory, 1131 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the 1132 * page table and the remaining bits are in the page directory */ 1133 if (radeon_vm_block_size == -1) { 1134 1135 /* Total bits covered by PD + PTs */ 1136 unsigned bits = ilog2(radeon_vm_size) + 18; 1137 1138 /* Make sure the PD is 4K in size up to 8GB address space. 1139 Above that split equal between PD and PTs */ 1140 if (radeon_vm_size <= 8) 1141 radeon_vm_block_size = bits - 9; 1142 else 1143 radeon_vm_block_size = (bits + 3) / 2; 1144 1145 } else if (radeon_vm_block_size < 9) { 1146 dev_warn(rdev->dev, "VM page table size (%d) too small\n", 1147 radeon_vm_block_size); 1148 radeon_vm_block_size = 9; 1149 } 1150 1151 if (radeon_vm_block_size > 24 || 1152 (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) { 1153 dev_warn(rdev->dev, "VM page table size (%d) too large\n", 1154 radeon_vm_block_size); 1155 radeon_vm_block_size = 9; 1156 } 1157 } 1158 1159 /** 1160 * radeon_switcheroo_set_state - set switcheroo state 1161 * 1162 * @pdev: pci dev pointer 1163 * @state: vga switcheroo state 1164 * 1165 * Callback for the switcheroo driver. Suspends or resumes the 1166 * the asics before or after it is powered up using ACPI methods. 1167 */ 1168 #ifdef DUMBBELL_WIP 1169 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) 1170 { 1171 struct drm_device *dev = pci_get_drvdata(pdev); 1172 struct radeon_device *rdev = dev->dev_private; 1173 1174 if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF) 1175 return; 1176 1177 if (state == VGA_SWITCHEROO_ON) { 1178 unsigned d3_delay = dev->pdev->d3_delay; 1179 1180 printk(KERN_INFO "radeon: switched on\n"); 1181 /* don't suspend or resume card normally */ 1182 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1183 1184 if (d3_delay < 20 && (rdev->px_quirk_flags & RADEON_PX_QUIRK_LONG_WAKEUP)) 1185 dev->pdev->d3_delay = 20; 1186 1187 radeon_resume_kms(dev, true, true); 1188 1189 dev->pdev->d3_delay = d3_delay; 1190 1191 dev->switch_power_state = DRM_SWITCH_POWER_ON; 1192 drm_kms_helper_poll_enable(dev); 1193 } else { 1194 printk(KERN_INFO "radeon: switched off\n"); 1195 drm_kms_helper_poll_disable(dev); 1196 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1197 radeon_suspend_kms(dev, true, true); 1198 dev->switch_power_state = DRM_SWITCH_POWER_OFF; 1199 } 1200 } 1201 #endif /* DUMBBELL_WIP */ 1202 1203 /** 1204 * radeon_switcheroo_can_switch - see if switcheroo state can change 1205 * 1206 * @pdev: pci dev pointer 1207 * 1208 * Callback for the switcheroo driver. Check of the switcheroo 1209 * state can be changed. 1210 * Returns true if the state can be changed, false if not. 1211 */ 1212 #ifdef DUMBBELL_WIP 1213 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev) 1214 { 1215 struct drm_device *dev = pci_get_drvdata(pdev); 1216 1217 /* 1218 * FIXME: open_count is protected by drm_global_mutex but that would lead to 1219 * locking inversion with the driver load path. And the access here is 1220 * completely racy anyway. So don't bother with locking for now. 1221 */ 1222 return dev->open_count == 0; 1223 } 1224 1225 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = { 1226 .set_gpu_state = radeon_switcheroo_set_state, 1227 .reprobe = NULL, 1228 .can_switch = radeon_switcheroo_can_switch, 1229 }; 1230 #endif /* DUMBBELL_WIP */ 1231 1232 /** 1233 * radeon_device_init - initialize the driver 1234 * 1235 * @rdev: radeon_device pointer 1236 * @pdev: drm dev pointer 1237 * @pdev: pci dev pointer 1238 * @flags: driver flags 1239 * 1240 * Initializes the driver info and hw (all asics). 1241 * Returns 0 for success or an error on failure. 1242 * Called at driver startup. 1243 */ 1244 int radeon_device_init(struct radeon_device *rdev, 1245 struct drm_device *ddev, 1246 struct pci_dev *pdev, 1247 uint32_t flags) 1248 { 1249 int r, i; 1250 int dma_bits; 1251 #ifdef PM_TODO 1252 bool runtime = false; 1253 #endif 1254 1255 rdev->shutdown = false; 1256 rdev->dev = &pdev->dev; 1257 rdev->ddev = ddev; 1258 rdev->pdev = pdev; 1259 rdev->flags = flags; 1260 rdev->family = flags & RADEON_FAMILY_MASK; 1261 rdev->is_atom_bios = false; 1262 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; 1263 rdev->mc.gtt_size = 512 * 1024 * 1024; 1264 rdev->accel_working = false; 1265 rdev->fictitious_range_registered = false; 1266 /* set up ring ids */ 1267 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1268 rdev->ring[i].idx = i; 1269 } 1270 rdev->fence_context = fence_context_alloc(RADEON_NUM_RINGS); 1271 1272 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n", 1273 radeon_family_name[rdev->family], pdev->vendor, pdev->device, 1274 pdev->subsystem_vendor, pdev->subsystem_device); 1275 1276 /* mutex initialization are all done here so we 1277 * can recall function without having locking issues */ 1278 lockinit(&rdev->ring_lock, "drdrl", 0, LK_CANRECURSE); 1279 lockinit(&rdev->dc_hw_i2c_mutex, "drddi2cm", 0, LK_CANRECURSE); 1280 atomic_set(&rdev->ih.lock, 0); 1281 lockinit(&rdev->gem.mutex, "radeon_gemmtx", 0, LK_CANRECURSE); 1282 lockinit(&rdev->pm.mutex, "drdpmm", 0, LK_CANRECURSE); 1283 1284 lockinit(&rdev->gpu_clock_mutex, "radeon_clockmtx", 0, LK_CANRECURSE); 1285 lockinit(&rdev->srbm_mutex, "radeon_srbm_mutex", 0, LK_CANRECURSE); 1286 lockinit(&rdev->pm.mclk_lock, "drpmml", 0, LK_CANRECURSE); 1287 lockinit(&rdev->exclusive_lock, "drdel", 0, LK_CANRECURSE); 1288 init_waitqueue_head(&rdev->irq.vblank_queue); 1289 lockinit(&rdev->mn_lock, "drrml", 0, LK_CANRECURSE); 1290 hash_init(rdev->mn_hash); 1291 r = radeon_gem_init(rdev); 1292 if (r) 1293 return r; 1294 1295 radeon_check_arguments(rdev); 1296 /* Adjust VM size here. 1297 * Max GPUVM size for cayman+ is 40 bits. 1298 */ 1299 rdev->vm_manager.max_pfn = radeon_vm_size << 18; 1300 1301 /* Set asic functions */ 1302 r = radeon_asic_init(rdev); 1303 if (r) 1304 return r; 1305 1306 /* all of the newer IGP chips have an internal gart 1307 * However some rs4xx report as AGP, so remove that here. 1308 */ 1309 if ((rdev->family >= CHIP_RS400) && 1310 (rdev->flags & RADEON_IS_IGP)) { 1311 rdev->flags &= ~RADEON_IS_AGP; 1312 } 1313 1314 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { 1315 radeon_agp_disable(rdev); 1316 } 1317 1318 /* Set the internal MC address mask 1319 * This is the max address of the GPU's 1320 * internal address space. 1321 */ 1322 if (rdev->family >= CHIP_CAYMAN) 1323 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1324 else if (rdev->family >= CHIP_CEDAR) 1325 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */ 1326 else 1327 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */ 1328 1329 /* set DMA mask + need_dma32 flags. 1330 * PCIE - can handle 40-bits. 1331 * IGP - can handle 40-bits 1332 * AGP - generally dma32 is safest 1333 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 1334 */ 1335 rdev->need_dma32 = false; 1336 if (rdev->flags & RADEON_IS_AGP) 1337 rdev->need_dma32 = true; 1338 if ((rdev->flags & RADEON_IS_PCI) && 1339 (rdev->family <= CHIP_RS740)) 1340 rdev->need_dma32 = true; 1341 1342 dma_bits = rdev->need_dma32 ? 32 : 40; 1343 #ifdef DUMBBELL_WIP 1344 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 1345 if (r) { 1346 rdev->need_dma32 = true; 1347 dma_bits = 32; 1348 printk(KERN_WARNING "radeon: No suitable DMA available.\n"); 1349 } 1350 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 1351 if (r) { 1352 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32)); 1353 printk(KERN_WARNING "radeon: No coherent DMA available.\n"); 1354 } 1355 #endif /* DUMBBELL_WIP */ 1356 1357 /* Registers mapping */ 1358 /* TODO: block userspace mapping of io register */ 1359 spin_init(&rdev->mmio_idx_lock, "radeon_mpio"); 1360 spin_init(&rdev->smc_idx_lock, "radeon_smc"); 1361 spin_init(&rdev->pll_idx_lock, "radeon_pll"); 1362 spin_init(&rdev->mc_idx_lock, "radeon_mc"); 1363 spin_init(&rdev->pcie_idx_lock, "radeon_pcie"); 1364 spin_init(&rdev->pciep_idx_lock, "radeon_pciep"); 1365 spin_init(&rdev->pif_idx_lock, "radeon_pif"); 1366 spin_init(&rdev->cg_idx_lock, "radeon_cg"); 1367 spin_init(&rdev->uvd_idx_lock, "radeon_uvd"); 1368 spin_init(&rdev->rcu_idx_lock, "radeon_rcu"); 1369 spin_init(&rdev->didt_idx_lock, "radeon_didt"); 1370 spin_init(&rdev->end_idx_lock, "radeon_end"); 1371 if (rdev->family >= CHIP_BONAIRE) { 1372 rdev->rmmio_rid = PCIR_BAR(5); 1373 } else { 1374 rdev->rmmio_rid = PCIR_BAR(2); 1375 } 1376 rdev->rmmio = bus_alloc_resource_any(rdev->dev->bsddev, SYS_RES_MEMORY, 1377 &rdev->rmmio_rid, RF_ACTIVE | RF_SHAREABLE); 1378 if (rdev->rmmio == NULL) { 1379 return -ENOMEM; 1380 } 1381 rdev->rmmio_base = rman_get_start(rdev->rmmio); 1382 rdev->rmmio_size = rman_get_size(rdev->rmmio); 1383 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); 1384 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); 1385 1386 /* doorbell bar mapping */ 1387 if (rdev->family >= CHIP_BONAIRE) 1388 radeon_doorbell_init(rdev); 1389 1390 /* io port mapping */ 1391 for (i = 0; i < DRM_MAX_PCI_RESOURCE; i++) { 1392 uint32_t data; 1393 1394 data = pci_read_config(rdev->dev->bsddev, PCIR_BAR(i), 4); 1395 if (PCI_BAR_IO(data)) { 1396 rdev->rio_rid = PCIR_BAR(i); 1397 rdev->rio_mem = bus_alloc_resource_any(rdev->dev->bsddev, 1398 SYS_RES_IOPORT, &rdev->rio_rid, 1399 RF_ACTIVE | RF_SHAREABLE); 1400 break; 1401 } 1402 } 1403 if (rdev->rio_mem == NULL) 1404 DRM_ERROR("Unable to find PCI I/O BAR\n"); 1405 1406 if (rdev->flags & RADEON_IS_PX) 1407 radeon_device_handle_px_quirks(rdev); 1408 1409 #ifdef DUMBBELL_WIP 1410 /* if we have > 1 VGA cards, then disable the radeon VGA resources */ 1411 /* this will fail for cards that aren't VGA class devices, just 1412 * ignore it */ 1413 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); 1414 1415 #ifdef PM_TODO 1416 if (rdev->flags & RADEON_IS_PX) 1417 runtime = true; 1418 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime); 1419 if (runtime) 1420 vga_switcheroo_init_domain_pm_ops(rdev->dev->bsddev, &rdev->vga_pm_domain); 1421 #endif 1422 #endif /* DUMBBELL_WIP */ 1423 1424 r = radeon_init(rdev); 1425 if (r) 1426 goto failed; 1427 1428 r = radeon_gem_debugfs_init(rdev); 1429 if (r) { 1430 DRM_ERROR("registering gem debugfs failed (%d).\n", r); 1431 } 1432 1433 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { 1434 /* Acceleration not working on AGP card try again 1435 * with fallback to PCI or PCIE GART 1436 */ 1437 radeon_asic_reset(rdev); 1438 radeon_fini(rdev); 1439 radeon_agp_disable(rdev); 1440 r = radeon_init(rdev); 1441 if (r) 1442 goto failed; 1443 } 1444 1445 r = radeon_ib_ring_tests(rdev); 1446 if (r) 1447 DRM_ERROR("ib ring test failed (%d).\n", r); 1448 1449 DRM_INFO("%s: Taking over the fictitious range 0x%lx-0x%llx\n", 1450 __func__, (uintmax_t)rdev->mc.aper_base, 1451 (uintmax_t)rdev->mc.aper_base + rdev->mc.visible_vram_size); 1452 r = vm_phys_fictitious_reg_range( 1453 rdev->mc.aper_base, 1454 rdev->mc.aper_base + rdev->mc.visible_vram_size, 1455 VM_MEMATTR_WRITE_COMBINING); 1456 if (r != 0) { 1457 DRM_ERROR("Failed to register fictitious range " 1458 "0x%lx-0x%llx (%d).\n", (uintmax_t)rdev->mc.aper_base, 1459 (uintmax_t)rdev->mc.aper_base + rdev->mc.visible_vram_size, r); 1460 return (-r); 1461 } 1462 rdev->fictitious_range_registered = true; 1463 1464 if ((radeon_testing & 1)) { 1465 if (rdev->accel_working) 1466 radeon_test_moves(rdev); 1467 else 1468 DRM_INFO("radeon: acceleration disabled, skipping move tests\n"); 1469 } 1470 if ((radeon_testing & 2)) { 1471 if (rdev->accel_working) 1472 radeon_test_syncing(rdev); 1473 else 1474 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n"); 1475 } 1476 if (radeon_benchmarking) { 1477 if (rdev->accel_working) 1478 radeon_benchmark(rdev, radeon_benchmarking); 1479 else 1480 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n"); 1481 } 1482 return 0; 1483 1484 failed: 1485 #ifdef DRM_BDSM 1486 if (runtime) 1487 vga_switcheroo_fini_domain_pm_ops(rdev->dev); 1488 #endif 1489 return r; 1490 } 1491 1492 #ifdef DUMBBELL_WIP 1493 static void radeon_debugfs_remove_files(struct radeon_device *rdev); 1494 #endif /* DUMBBELL_WIP */ 1495 1496 /** 1497 * radeon_device_fini - tear down the driver 1498 * 1499 * @rdev: radeon_device pointer 1500 * 1501 * Tear down the driver info (all asics). 1502 * Called at driver shutdown. 1503 */ 1504 void radeon_device_fini(struct radeon_device *rdev) 1505 { 1506 DRM_INFO("radeon: finishing device.\n"); 1507 rdev->shutdown = true; 1508 /* evict vram memory */ 1509 radeon_bo_evict_vram(rdev); 1510 1511 if (rdev->fictitious_range_registered) { 1512 vm_phys_fictitious_unreg_range( 1513 rdev->mc.aper_base, 1514 rdev->mc.aper_base + rdev->mc.visible_vram_size); 1515 } 1516 1517 radeon_fini(rdev); 1518 #ifdef DUMBBELL_WIP 1519 vga_switcheroo_unregister_client(rdev->pdev); 1520 if (rdev->flags & RADEON_IS_PX) 1521 vga_switcheroo_fini_domain_pm_ops(rdev->dev); 1522 vga_client_register(rdev->pdev, NULL, NULL, NULL); 1523 #endif /* DUMBBELL_WIP */ 1524 1525 if (rdev->rio_mem) 1526 bus_release_resource(rdev->dev->bsddev, SYS_RES_IOPORT, rdev->rio_rid, 1527 rdev->rio_mem); 1528 rdev->rio_mem = NULL; 1529 bus_release_resource(rdev->dev->bsddev, SYS_RES_MEMORY, rdev->rmmio_rid, 1530 rdev->rmmio); 1531 rdev->rmmio = NULL; 1532 if (rdev->family >= CHIP_BONAIRE) 1533 radeon_doorbell_fini(rdev); 1534 #ifdef DUMBBELL_WIP 1535 radeon_debugfs_remove_files(rdev); 1536 #endif /* DUMBBELL_WIP */ 1537 } 1538 1539 1540 /* 1541 * Suspend & resume. 1542 */ 1543 /** 1544 * radeon_suspend_kms - initiate device suspend 1545 * 1546 * @pdev: drm dev pointer 1547 * @state: suspend state 1548 * 1549 * Puts the hw in the suspend state (all asics). 1550 * Returns 0 for success or an error on failure. 1551 * Called at driver suspend. 1552 */ 1553 int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon) 1554 { 1555 struct radeon_device *rdev; 1556 struct drm_crtc *crtc; 1557 struct drm_connector *connector; 1558 int i, r; 1559 1560 if (dev == NULL || dev->dev_private == NULL) { 1561 return -ENODEV; 1562 } 1563 1564 rdev = dev->dev_private; 1565 1566 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1567 return 0; 1568 1569 drm_kms_helper_poll_disable(dev); 1570 1571 /* turn off display hw */ 1572 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1573 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 1574 } 1575 1576 /* unpin the front buffers */ 1577 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1578 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->primary->fb); 1579 struct radeon_bo *robj; 1580 1581 if (rfb == NULL || rfb->obj == NULL) { 1582 continue; 1583 } 1584 robj = gem_to_radeon_bo(rfb->obj); 1585 /* don't unpin kernel fb objects */ 1586 if (!radeon_fbdev_robj_is_fb(rdev, robj)) { 1587 r = radeon_bo_reserve(robj, false); 1588 if (r == 0) { 1589 radeon_bo_unpin(robj); 1590 radeon_bo_unreserve(robj); 1591 } 1592 } 1593 } 1594 /* evict vram memory */ 1595 radeon_bo_evict_vram(rdev); 1596 1597 /* wait for gpu to finish processing current batch */ 1598 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1599 r = radeon_fence_wait_empty(rdev, i); 1600 if (r) { 1601 /* delay GPU reset to resume */ 1602 radeon_fence_driver_force_completion(rdev, i); 1603 } 1604 } 1605 1606 radeon_save_bios_scratch_regs(rdev); 1607 1608 radeon_suspend(rdev); 1609 radeon_hpd_fini(rdev); 1610 /* evict remaining vram memory */ 1611 radeon_bo_evict_vram(rdev); 1612 1613 radeon_agp_suspend(rdev); 1614 1615 pci_save_state(device_get_parent(rdev->dev->bsddev)); 1616 #ifdef DUMBBELL_WIP 1617 if (suspend) { 1618 /* Shut down the device */ 1619 pci_disable_device(dev->pdev); 1620 #endif /* DUMBBELL_WIP */ 1621 pci_set_powerstate(dev->dev->bsddev, PCI_POWERSTATE_D3); 1622 #ifdef DUMBBELL_WIP 1623 } 1624 #endif 1625 if (fbcon) { 1626 #ifdef DUMBBELL_WIP 1627 console_lock(); 1628 #endif /* DUMBBELL_WIP */ 1629 radeon_fbdev_set_suspend(rdev, 1); 1630 #ifdef DUMBBELL_WIP 1631 console_unlock(); 1632 #endif /* DUMBBELL_WIP */ 1633 } 1634 return 0; 1635 } 1636 1637 /** 1638 * radeon_resume_kms - initiate device resume 1639 * 1640 * @pdev: drm dev pointer 1641 * 1642 * Bring the hw back to operating state (all asics). 1643 * Returns 0 for success or an error on failure. 1644 * Called at driver resume. 1645 */ 1646 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon) 1647 { 1648 struct drm_connector *connector; 1649 struct radeon_device *rdev = dev->dev_private; 1650 int r; 1651 1652 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1653 return 0; 1654 1655 #ifdef DUMBBELL_WIP 1656 if (fbcon) { 1657 console_lock(); 1658 } 1659 #endif /* DUMBBELL_WIP */ 1660 if (resume) { 1661 pci_set_powerstate(dev->dev->bsddev, PCI_POWERSTATE_D0); 1662 pci_restore_state(device_get_parent(rdev->dev->bsddev)); 1663 #ifdef DUMBBELL_WIP 1664 if (pci_enable_device(dev->pdev)) { 1665 if (fbcon) 1666 console_unlock(); 1667 return -1; 1668 } 1669 #endif /* DUMBBELL_WIP */ 1670 } 1671 /* resume AGP if in use */ 1672 radeon_agp_resume(rdev); 1673 radeon_resume(rdev); 1674 1675 r = radeon_ib_ring_tests(rdev); 1676 if (r) 1677 DRM_ERROR("ib ring test failed (%d).\n", r); 1678 1679 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 1680 /* do dpm late init */ 1681 r = radeon_pm_late_init(rdev); 1682 if (r) { 1683 rdev->pm.dpm_enabled = false; 1684 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1685 } 1686 } else { 1687 /* resume old pm late */ 1688 radeon_pm_resume(rdev); 1689 } 1690 1691 radeon_restore_bios_scratch_regs(rdev); 1692 1693 /* init dig PHYs, disp eng pll */ 1694 if (rdev->is_atom_bios) { 1695 radeon_atom_encoder_init(rdev); 1696 radeon_atom_disp_eng_pll_init(rdev); 1697 /* turn on the BL */ 1698 if (rdev->mode_info.bl_encoder) { 1699 u8 bl_level = radeon_get_backlight_level(rdev, 1700 rdev->mode_info.bl_encoder); 1701 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, 1702 bl_level); 1703 } 1704 } 1705 /* reset hpd state */ 1706 radeon_hpd_init(rdev); 1707 /* blat the mode back in */ 1708 if (fbcon) { 1709 drm_helper_resume_force_mode(dev); 1710 /* turn on display hw */ 1711 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1712 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 1713 } 1714 } 1715 1716 drm_kms_helper_poll_enable(dev); 1717 1718 /* set the power state here in case we are a PX system or headless */ 1719 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 1720 radeon_pm_compute_clocks(rdev); 1721 1722 if (fbcon) { 1723 radeon_fbdev_set_suspend(rdev, 0); 1724 #ifdef DUMBBELL_WIP 1725 console_unlock(); 1726 #endif /* DUMBBELL_WIP */ 1727 } 1728 1729 return 0; 1730 } 1731 1732 /** 1733 * radeon_gpu_reset - reset the asic 1734 * 1735 * @rdev: radeon device pointer 1736 * 1737 * Attempt the reset the GPU if it has hung (all asics). 1738 * Returns 0 for success or an error on failure. 1739 */ 1740 int radeon_gpu_reset(struct radeon_device *rdev) 1741 { 1742 unsigned ring_sizes[RADEON_NUM_RINGS]; 1743 uint32_t *ring_data[RADEON_NUM_RINGS]; 1744 1745 bool saved = false; 1746 1747 int i, r; 1748 int resched; 1749 1750 lockmgr(&rdev->exclusive_lock, LK_EXCLUSIVE); 1751 1752 if (!rdev->needs_reset) { 1753 lockmgr(&rdev->exclusive_lock, LK_RELEASE); 1754 return 0; 1755 } 1756 1757 radeon_save_bios_scratch_regs(rdev); 1758 /* block TTM */ 1759 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); 1760 radeon_suspend(rdev); 1761 radeon_hpd_fini(rdev); 1762 1763 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1764 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i], 1765 &ring_data[i]); 1766 if (ring_sizes[i]) { 1767 saved = true; 1768 dev_info(rdev->dev, "Saved %d dwords of commands " 1769 "on ring %d.\n", ring_sizes[i], i); 1770 } 1771 } 1772 1773 r = radeon_asic_reset(rdev); 1774 if (!r) { 1775 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n"); 1776 radeon_resume(rdev); 1777 } 1778 1779 radeon_restore_bios_scratch_regs(rdev); 1780 1781 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1782 if (!r && ring_data[i]) { 1783 radeon_ring_restore(rdev, &rdev->ring[i], 1784 ring_sizes[i], ring_data[i]); 1785 } else { 1786 radeon_fence_driver_force_completion(rdev, i); 1787 kfree(ring_data[i]); 1788 } 1789 } 1790 1791 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 1792 /* do dpm late init */ 1793 r = radeon_pm_late_init(rdev); 1794 if (r) { 1795 rdev->pm.dpm_enabled = false; 1796 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1797 } 1798 } else { 1799 /* resume old pm late */ 1800 radeon_pm_resume(rdev); 1801 } 1802 1803 /* init dig PHYs, disp eng pll */ 1804 if (rdev->is_atom_bios) { 1805 radeon_atom_encoder_init(rdev); 1806 radeon_atom_disp_eng_pll_init(rdev); 1807 /* turn on the BL */ 1808 if (rdev->mode_info.bl_encoder) { 1809 u8 bl_level = radeon_get_backlight_level(rdev, 1810 rdev->mode_info.bl_encoder); 1811 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, 1812 bl_level); 1813 } 1814 } 1815 /* reset hpd state */ 1816 radeon_hpd_init(rdev); 1817 1818 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); 1819 1820 rdev->in_reset = true; 1821 rdev->needs_reset = false; 1822 1823 #if 0 1824 downgrade_write(&rdev->exclusive_lock); 1825 #endif 1826 1827 drm_helper_resume_force_mode(rdev->ddev); 1828 1829 /* set the power state here in case we are a PX system or headless */ 1830 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 1831 radeon_pm_compute_clocks(rdev); 1832 1833 if (!r) { 1834 r = radeon_ib_ring_tests(rdev); 1835 if (r && saved) 1836 r = -EAGAIN; 1837 } else { 1838 /* bad news, how to tell it to userspace ? */ 1839 dev_info(rdev->dev, "GPU reset failed\n"); 1840 } 1841 1842 rdev->needs_reset = r == -EAGAIN; 1843 rdev->in_reset = false; 1844 1845 lockmgr(&rdev->exclusive_lock, LK_RELEASE); 1846 return r; 1847 } 1848 1849 1850 /* 1851 * Debugfs 1852 */ 1853 #ifdef DUMBBELL_WIP 1854 int radeon_debugfs_add_files(struct radeon_device *rdev, 1855 struct drm_info_list *files, 1856 unsigned nfiles) 1857 { 1858 unsigned i; 1859 1860 for (i = 0; i < rdev->debugfs_count; i++) { 1861 if (rdev->debugfs[i].files == files) { 1862 /* Already registered */ 1863 return 0; 1864 } 1865 } 1866 1867 i = rdev->debugfs_count + 1; 1868 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) { 1869 DRM_ERROR("Reached maximum number of debugfs components.\n"); 1870 DRM_ERROR("Report so we increase " 1871 "RADEON_DEBUGFS_MAX_COMPONENTS.\n"); 1872 return -EINVAL; 1873 } 1874 rdev->debugfs[rdev->debugfs_count].files = files; 1875 rdev->debugfs[rdev->debugfs_count].num_files = nfiles; 1876 rdev->debugfs_count = i; 1877 #if defined(CONFIG_DEBUG_FS) 1878 drm_debugfs_create_files(files, nfiles, 1879 rdev->ddev->control->debugfs_root, 1880 rdev->ddev->control); 1881 drm_debugfs_create_files(files, nfiles, 1882 rdev->ddev->primary->debugfs_root, 1883 rdev->ddev->primary); 1884 #endif 1885 return 0; 1886 } 1887 1888 static void radeon_debugfs_remove_files(struct radeon_device *rdev) 1889 { 1890 #if defined(CONFIG_DEBUG_FS) 1891 unsigned i; 1892 1893 for (i = 0; i < rdev->debugfs_count; i++) { 1894 drm_debugfs_remove_files(rdev->debugfs[i].files, 1895 rdev->debugfs[i].num_files, 1896 rdev->ddev->control); 1897 drm_debugfs_remove_files(rdev->debugfs[i].files, 1898 rdev->debugfs[i].num_files, 1899 rdev->ddev->primary); 1900 } 1901 #endif 1902 } 1903 1904 #if defined(CONFIG_DEBUG_FS) 1905 int radeon_debugfs_init(struct drm_minor *minor) 1906 { 1907 return 0; 1908 } 1909 1910 void radeon_debugfs_cleanup(struct drm_minor *minor) 1911 { 1912 } 1913 #endif 1914 #endif /* DUMBBELL_WIP */ 1915