1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/console.h> 29 #include <drm/drmP.h> 30 #include "drm/drm_legacy.h" /* for drm_dma_handle_t */ 31 #include <drm/drm_crtc_helper.h> 32 #include <drm/radeon_drm.h> 33 #include <linux/vgaarb.h> 34 #include <linux/vga_switcheroo.h> 35 #include "radeon_reg.h" 36 #include "radeon.h" 37 #include "atom.h" 38 39 #include <asm/cpufeature.h> 40 41 static const char radeon_family_name[][16] = { 42 "R100", 43 "RV100", 44 "RS100", 45 "RV200", 46 "RS200", 47 "R200", 48 "RV250", 49 "RS300", 50 "RV280", 51 "R300", 52 "R350", 53 "RV350", 54 "RV380", 55 "R420", 56 "R423", 57 "RV410", 58 "RS400", 59 "RS480", 60 "RS600", 61 "RS690", 62 "RS740", 63 "RV515", 64 "R520", 65 "RV530", 66 "RV560", 67 "RV570", 68 "R580", 69 "R600", 70 "RV610", 71 "RV630", 72 "RV670", 73 "RV620", 74 "RV635", 75 "RS780", 76 "RS880", 77 "RV770", 78 "RV730", 79 "RV710", 80 "RV740", 81 "CEDAR", 82 "REDWOOD", 83 "JUNIPER", 84 "CYPRESS", 85 "HEMLOCK", 86 "PALM", 87 "SUMO", 88 "SUMO2", 89 "BARTS", 90 "TURKS", 91 "CAICOS", 92 "CAYMAN", 93 "ARUBA", 94 "TAHITI", 95 "PITCAIRN", 96 "VERDE", 97 "OLAND", 98 "HAINAN", 99 "BONAIRE", 100 "KAVERI", 101 "KABINI", 102 "HAWAII", 103 "MULLINS", 104 "LAST", 105 }; 106 107 #if defined(CONFIG_VGA_SWITCHEROO) 108 bool radeon_has_atpx_dgpu_power_cntl(void); 109 bool radeon_is_atpx_hybrid(void); 110 #else 111 static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; } 112 static inline bool radeon_is_atpx_hybrid(void) { return false; } 113 #endif 114 115 #define RADEON_PX_QUIRK_DISABLE_PX (1 << 0) 116 117 struct radeon_px_quirk { 118 u32 chip_vendor; 119 u32 chip_device; 120 u32 subsys_vendor; 121 u32 subsys_device; 122 u32 px_quirk_flags; 123 }; 124 125 static struct radeon_px_quirk radeon_px_quirk_list[] = { 126 /* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m) 127 * https://bugzilla.kernel.org/show_bug.cgi?id=74551 128 */ 129 { PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX }, 130 /* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU 131 * https://bugzilla.kernel.org/show_bug.cgi?id=51381 132 */ 133 { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX }, 134 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU 135 * https://bugzilla.kernel.org/show_bug.cgi?id=51381 136 */ 137 { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX }, 138 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU 139 * https://bugs.freedesktop.org/show_bug.cgi?id=101491 140 */ 141 { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX }, 142 { 0, 0, 0, 0, 0 }, 143 }; 144 145 bool radeon_is_px(struct drm_device *dev) 146 { 147 struct radeon_device *rdev = dev->dev_private; 148 149 if (rdev->flags & RADEON_IS_PX) 150 return true; 151 return false; 152 } 153 154 static void radeon_device_handle_px_quirks(struct radeon_device *rdev) 155 { 156 struct radeon_px_quirk *p = radeon_px_quirk_list; 157 158 /* Apply PX quirks */ 159 while (p && p->chip_device != 0) { 160 if (rdev->pdev->vendor == p->chip_vendor && 161 rdev->pdev->device == p->chip_device && 162 rdev->pdev->subsystem_vendor == p->subsys_vendor && 163 rdev->pdev->subsystem_device == p->subsys_device) { 164 rdev->px_quirk_flags = p->px_quirk_flags; 165 break; 166 } 167 ++p; 168 } 169 170 if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX) 171 rdev->flags &= ~RADEON_IS_PX; 172 173 /* disable PX is the system doesn't support dGPU power control or hybrid gfx */ 174 if (!radeon_is_atpx_hybrid() && 175 !radeon_has_atpx_dgpu_power_cntl()) 176 rdev->flags &= ~RADEON_IS_PX; 177 } 178 179 /** 180 * radeon_program_register_sequence - program an array of registers. 181 * 182 * @rdev: radeon_device pointer 183 * @registers: pointer to the register array 184 * @array_size: size of the register array 185 * 186 * Programs an array or registers with and and or masks. 187 * This is a helper for setting golden registers. 188 */ 189 void radeon_program_register_sequence(struct radeon_device *rdev, 190 const u32 *registers, 191 const u32 array_size) 192 { 193 u32 tmp, reg, and_mask, or_mask; 194 int i; 195 196 if (array_size % 3) 197 return; 198 199 for (i = 0; i < array_size; i +=3) { 200 reg = registers[i + 0]; 201 and_mask = registers[i + 1]; 202 or_mask = registers[i + 2]; 203 204 if (and_mask == 0xffffffff) { 205 tmp = or_mask; 206 } else { 207 tmp = RREG32(reg); 208 tmp &= ~and_mask; 209 tmp |= or_mask; 210 } 211 WREG32(reg, tmp); 212 } 213 } 214 215 void radeon_pci_config_reset(struct radeon_device *rdev) 216 { 217 pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA); 218 } 219 220 /** 221 * radeon_surface_init - Clear GPU surface registers. 222 * 223 * @rdev: radeon_device pointer 224 * 225 * Clear GPU surface registers (r1xx-r5xx). 226 */ 227 void radeon_surface_init(struct radeon_device *rdev) 228 { 229 /* FIXME: check this out */ 230 if (rdev->family < CHIP_R600) { 231 int i; 232 233 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 234 if (rdev->surface_regs[i].bo) 235 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); 236 else 237 radeon_clear_surface_reg(rdev, i); 238 } 239 /* enable surfaces */ 240 WREG32(RADEON_SURFACE_CNTL, 0); 241 } 242 } 243 244 /* 245 * GPU scratch registers helpers function. 246 */ 247 /** 248 * radeon_scratch_init - Init scratch register driver information. 249 * 250 * @rdev: radeon_device pointer 251 * 252 * Init CP scratch register driver information (r1xx-r5xx) 253 */ 254 void radeon_scratch_init(struct radeon_device *rdev) 255 { 256 int i; 257 258 /* FIXME: check this out */ 259 if (rdev->family < CHIP_R300) { 260 rdev->scratch.num_reg = 5; 261 } else { 262 rdev->scratch.num_reg = 7; 263 } 264 rdev->scratch.reg_base = RADEON_SCRATCH_REG0; 265 for (i = 0; i < rdev->scratch.num_reg; i++) { 266 rdev->scratch.free[i] = true; 267 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 268 } 269 } 270 271 /** 272 * radeon_scratch_get - Allocate a scratch register 273 * 274 * @rdev: radeon_device pointer 275 * @reg: scratch register mmio offset 276 * 277 * Allocate a CP scratch register for use by the driver (all asics). 278 * Returns 0 on success or -EINVAL on failure. 279 */ 280 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) 281 { 282 int i; 283 284 for (i = 0; i < rdev->scratch.num_reg; i++) { 285 if (rdev->scratch.free[i]) { 286 rdev->scratch.free[i] = false; 287 *reg = rdev->scratch.reg[i]; 288 return 0; 289 } 290 } 291 return -EINVAL; 292 } 293 294 /** 295 * radeon_scratch_free - Free a scratch register 296 * 297 * @rdev: radeon_device pointer 298 * @reg: scratch register mmio offset 299 * 300 * Free a CP scratch register allocated for use by the driver (all asics) 301 */ 302 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) 303 { 304 int i; 305 306 for (i = 0; i < rdev->scratch.num_reg; i++) { 307 if (rdev->scratch.reg[i] == reg) { 308 rdev->scratch.free[i] = true; 309 return; 310 } 311 } 312 } 313 314 /* 315 * GPU doorbell aperture helpers function. 316 */ 317 /** 318 * radeon_doorbell_init - Init doorbell driver information. 319 * 320 * @rdev: radeon_device pointer 321 * 322 * Init doorbell driver information (CIK) 323 * Returns 0 on success, error on failure. 324 */ 325 static int radeon_doorbell_init(struct radeon_device *rdev) 326 { 327 /* doorbell bar mapping */ 328 rdev->doorbell.base = pci_resource_start(rdev->pdev, 2); 329 rdev->doorbell.size = pci_resource_len(rdev->pdev, 2); 330 331 rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS); 332 if (rdev->doorbell.num_doorbells == 0) 333 return -EINVAL; 334 335 rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32)); 336 if (rdev->doorbell.ptr == NULL) { 337 return -ENOMEM; 338 } 339 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base); 340 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size); 341 342 memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used)); 343 344 return 0; 345 } 346 347 /** 348 * radeon_doorbell_fini - Tear down doorbell driver information. 349 * 350 * @rdev: radeon_device pointer 351 * 352 * Tear down doorbell driver information (CIK) 353 */ 354 static void radeon_doorbell_fini(struct radeon_device *rdev) 355 { 356 iounmap(rdev->doorbell.ptr); 357 rdev->doorbell.ptr = NULL; 358 } 359 360 /** 361 * radeon_doorbell_get - Allocate a doorbell entry 362 * 363 * @rdev: radeon_device pointer 364 * @doorbell: doorbell index 365 * 366 * Allocate a doorbell for use by the driver (all asics). 367 * Returns 0 on success or -EINVAL on failure. 368 */ 369 int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell) 370 { 371 unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells); 372 if (offset < rdev->doorbell.num_doorbells) { 373 __set_bit(offset, rdev->doorbell.used); 374 *doorbell = offset; 375 return 0; 376 } else { 377 return -EINVAL; 378 } 379 } 380 381 /** 382 * radeon_doorbell_free - Free a doorbell entry 383 * 384 * @rdev: radeon_device pointer 385 * @doorbell: doorbell index 386 * 387 * Free a doorbell allocated for use by the driver (all asics) 388 */ 389 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell) 390 { 391 if (doorbell < rdev->doorbell.num_doorbells) 392 __clear_bit(doorbell, rdev->doorbell.used); 393 } 394 395 /** 396 * radeon_doorbell_get_kfd_info - Report doorbell configuration required to 397 * setup KFD 398 * 399 * @rdev: radeon_device pointer 400 * @aperture_base: output returning doorbell aperture base physical address 401 * @aperture_size: output returning doorbell aperture size in bytes 402 * @start_offset: output returning # of doorbell bytes reserved for radeon. 403 * 404 * Radeon and the KFD share the doorbell aperture. Radeon sets it up, 405 * takes doorbells required for its own rings and reports the setup to KFD. 406 * Radeon reserved doorbells are at the start of the doorbell aperture. 407 */ 408 void radeon_doorbell_get_kfd_info(struct radeon_device *rdev, 409 phys_addr_t *aperture_base, 410 size_t *aperture_size, 411 size_t *start_offset) 412 { 413 /* The first num_doorbells are used by radeon. 414 * KFD takes whatever's left in the aperture. */ 415 if (rdev->doorbell.size > rdev->doorbell.num_doorbells * sizeof(u32)) { 416 *aperture_base = rdev->doorbell.base; 417 *aperture_size = rdev->doorbell.size; 418 *start_offset = rdev->doorbell.num_doorbells * sizeof(u32); 419 } else { 420 *aperture_base = 0; 421 *aperture_size = 0; 422 *start_offset = 0; 423 } 424 } 425 426 /* 427 * radeon_wb_*() 428 * Writeback is the the method by which the the GPU updates special pages 429 * in memory with the status of certain GPU events (fences, ring pointers, 430 * etc.). 431 */ 432 433 /** 434 * radeon_wb_disable - Disable Writeback 435 * 436 * @rdev: radeon_device pointer 437 * 438 * Disables Writeback (all asics). Used for suspend. 439 */ 440 void radeon_wb_disable(struct radeon_device *rdev) 441 { 442 rdev->wb.enabled = false; 443 } 444 445 /** 446 * radeon_wb_fini - Disable Writeback and free memory 447 * 448 * @rdev: radeon_device pointer 449 * 450 * Disables Writeback and frees the Writeback memory (all asics). 451 * Used at driver shutdown. 452 */ 453 void radeon_wb_fini(struct radeon_device *rdev) 454 { 455 radeon_wb_disable(rdev); 456 if (rdev->wb.wb_obj) { 457 if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) { 458 radeon_bo_kunmap(rdev->wb.wb_obj); 459 radeon_bo_unpin(rdev->wb.wb_obj); 460 radeon_bo_unreserve(rdev->wb.wb_obj); 461 } 462 radeon_bo_unref(&rdev->wb.wb_obj); 463 rdev->wb.wb = NULL; 464 rdev->wb.wb_obj = NULL; 465 } 466 } 467 468 /** 469 * radeon_wb_init- Init Writeback driver info and allocate memory 470 * 471 * @rdev: radeon_device pointer 472 * 473 * Disables Writeback and frees the Writeback memory (all asics). 474 * Used at driver startup. 475 * Returns 0 on success or an -error on failure. 476 */ 477 int radeon_wb_init(struct radeon_device *rdev) 478 { 479 int r; 480 void *wb_ptr = NULL; 481 482 if (rdev->wb.wb_obj == NULL) { 483 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, 484 RADEON_GEM_DOMAIN_GTT, 0, NULL, NULL, 485 &rdev->wb.wb_obj); 486 if (r) { 487 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); 488 return r; 489 } 490 r = radeon_bo_reserve(rdev->wb.wb_obj, false); 491 if (unlikely(r != 0)) { 492 radeon_wb_fini(rdev); 493 return r; 494 } 495 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, 496 (u64 *)&rdev->wb.gpu_addr); 497 if (r) { 498 radeon_bo_unreserve(rdev->wb.wb_obj); 499 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); 500 radeon_wb_fini(rdev); 501 return r; 502 } 503 wb_ptr = &rdev->wb.wb; 504 r = radeon_bo_kmap(rdev->wb.wb_obj, wb_ptr); 505 radeon_bo_unreserve(rdev->wb.wb_obj); 506 if (r) { 507 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); 508 radeon_wb_fini(rdev); 509 return r; 510 } 511 } 512 513 /* clear wb memory */ 514 memset(*(void **)wb_ptr, 0, RADEON_GPU_PAGE_SIZE); 515 /* disable event_write fences */ 516 rdev->wb.use_event = false; 517 /* disabled via module param */ 518 if (radeon_no_wb == 1) { 519 rdev->wb.enabled = false; 520 } else { 521 if (rdev->flags & RADEON_IS_AGP) { 522 /* often unreliable on AGP */ 523 rdev->wb.enabled = false; 524 } else if (rdev->family < CHIP_R300) { 525 /* often unreliable on pre-r300 */ 526 rdev->wb.enabled = false; 527 } else { 528 rdev->wb.enabled = true; 529 /* event_write fences are only available on r600+ */ 530 if (rdev->family >= CHIP_R600) { 531 rdev->wb.use_event = true; 532 } 533 } 534 } 535 /* always use writeback/events on NI, APUs */ 536 if (rdev->family >= CHIP_PALM) { 537 rdev->wb.enabled = true; 538 rdev->wb.use_event = true; 539 } 540 541 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis"); 542 543 return 0; 544 } 545 546 /** 547 * radeon_vram_location - try to find VRAM location 548 * @rdev: radeon device structure holding all necessary informations 549 * @mc: memory controller structure holding memory informations 550 * @base: base address at which to put VRAM 551 * 552 * Function will place try to place VRAM at base address provided 553 * as parameter (which is so far either PCI aperture address or 554 * for IGP TOM base address). 555 * 556 * If there is not enough space to fit the unvisible VRAM in the 32bits 557 * address space then we limit the VRAM size to the aperture. 558 * 559 * If we are using AGP and if the AGP aperture doesn't allow us to have 560 * room for all the VRAM than we restrict the VRAM to the PCI aperture 561 * size and print a warning. 562 * 563 * This function will never fails, worst case are limiting VRAM. 564 * 565 * Note: GTT start, end, size should be initialized before calling this 566 * function on AGP platform. 567 * 568 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, 569 * this shouldn't be a problem as we are using the PCI aperture as a reference. 570 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but 571 * not IGP. 572 * 573 * Note: we use mc_vram_size as on some board we need to program the mc to 574 * cover the whole aperture even if VRAM size is inferior to aperture size 575 * Novell bug 204882 + along with lots of ubuntu ones 576 * 577 * Note: when limiting vram it's safe to overwritte real_vram_size because 578 * we are not in case where real_vram_size is inferior to mc_vram_size (ie 579 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu 580 * ones) 581 * 582 * Note: IGP TOM addr should be the same as the aperture addr, we don't 583 * explicitly check for that thought. 584 * 585 * FIXME: when reducing VRAM size align new size on power of 2. 586 */ 587 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) 588 { 589 uint64_t limit = (uint64_t)radeon_vram_limit << 20; 590 591 mc->vram_start = base; 592 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) { 593 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 594 mc->real_vram_size = mc->aper_size; 595 mc->mc_vram_size = mc->aper_size; 596 } 597 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 598 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { 599 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 600 mc->real_vram_size = mc->aper_size; 601 mc->mc_vram_size = mc->aper_size; 602 } 603 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 604 if (limit && limit < mc->real_vram_size) 605 mc->real_vram_size = limit; 606 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 607 mc->mc_vram_size >> 20, mc->vram_start, 608 mc->vram_end, mc->real_vram_size >> 20); 609 } 610 611 /** 612 * radeon_gtt_location - try to find GTT location 613 * @rdev: radeon device structure holding all necessary informations 614 * @mc: memory controller structure holding memory informations 615 * 616 * Function will place try to place GTT before or after VRAM. 617 * 618 * If GTT size is bigger than space left then we ajust GTT size. 619 * Thus function will never fails. 620 * 621 * FIXME: when reducing GTT size align new size on power of 2. 622 */ 623 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 624 { 625 u64 size_af, size_bf; 626 627 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; 628 size_bf = mc->vram_start & ~mc->gtt_base_align; 629 if (size_bf > size_af) { 630 if (mc->gtt_size > size_bf) { 631 dev_warn(rdev->dev, "limiting GTT\n"); 632 mc->gtt_size = size_bf; 633 } 634 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; 635 } else { 636 if (mc->gtt_size > size_af) { 637 dev_warn(rdev->dev, "limiting GTT\n"); 638 mc->gtt_size = size_af; 639 } 640 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; 641 } 642 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; 643 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", 644 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); 645 } 646 647 /* 648 * GPU helpers function. 649 */ 650 651 /** 652 * radeon_device_is_virtual - check if we are running is a virtual environment 653 * 654 * Check if the asic has been passed through to a VM (all asics). 655 * Used at driver startup. 656 * Returns true if virtual or false if not. 657 */ 658 bool radeon_device_is_virtual(void); 659 bool radeon_device_is_virtual(void) 660 { 661 #ifdef CONFIG_X86 662 return boot_cpu_has(X86_FEATURE_HYPERVISOR); 663 #else 664 return false; 665 #endif 666 } 667 668 /** 669 * radeon_card_posted - check if the hw has already been initialized 670 * 671 * @rdev: radeon_device pointer 672 * 673 * Check if the asic has been initialized (all asics). 674 * Used at driver startup. 675 * Returns true if initialized or false if not. 676 */ 677 bool radeon_card_posted(struct radeon_device *rdev) 678 { 679 uint32_t reg; 680 681 /* for pass through, always force asic_init for CI */ 682 if (rdev->family >= CHIP_BONAIRE && 683 radeon_device_is_virtual()) 684 return false; 685 686 #ifdef DUMBBELL_WIP 687 /* required for EFI mode on macbook2,1 which uses an r5xx asic */ 688 if (efi_enabled(EFI_BOOT) && 689 (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && 690 (rdev->family < CHIP_R600)) 691 return false; 692 #endif /* DUMBBELL_WIP */ 693 694 if (ASIC_IS_NODCE(rdev)) 695 goto check_memsize; 696 697 /* first check CRTCs */ 698 if (ASIC_IS_DCE4(rdev)) { 699 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | 700 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 701 if (rdev->num_crtc >= 4) { 702 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | 703 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 704 } 705 if (rdev->num_crtc >= 6) { 706 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | 707 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 708 } 709 if (reg & EVERGREEN_CRTC_MASTER_EN) 710 return true; 711 } else if (ASIC_IS_AVIVO(rdev)) { 712 reg = RREG32(AVIVO_D1CRTC_CONTROL) | 713 RREG32(AVIVO_D2CRTC_CONTROL); 714 if (reg & AVIVO_CRTC_EN) { 715 return true; 716 } 717 } else { 718 reg = RREG32(RADEON_CRTC_GEN_CNTL) | 719 RREG32(RADEON_CRTC2_GEN_CNTL); 720 if (reg & RADEON_CRTC_EN) { 721 return true; 722 } 723 } 724 725 check_memsize: 726 /* then check MEM_SIZE, in case the crtcs are off */ 727 if (rdev->family >= CHIP_R600) 728 reg = RREG32(R600_CONFIG_MEMSIZE); 729 else 730 reg = RREG32(RADEON_CONFIG_MEMSIZE); 731 732 if (reg) 733 return true; 734 735 return false; 736 737 } 738 739 /** 740 * radeon_update_bandwidth_info - update display bandwidth params 741 * 742 * @rdev: radeon_device pointer 743 * 744 * Used when sclk/mclk are switched or display modes are set. 745 * params are used to calculate display watermarks (all asics) 746 */ 747 void radeon_update_bandwidth_info(struct radeon_device *rdev) 748 { 749 fixed20_12 a; 750 u32 sclk = rdev->pm.current_sclk; 751 u32 mclk = rdev->pm.current_mclk; 752 753 /* sclk/mclk in Mhz */ 754 a.full = dfixed_const(100); 755 rdev->pm.sclk.full = dfixed_const(sclk); 756 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); 757 rdev->pm.mclk.full = dfixed_const(mclk); 758 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); 759 760 if (rdev->flags & RADEON_IS_IGP) { 761 a.full = dfixed_const(16); 762 /* core_bandwidth = sclk(Mhz) * 16 */ 763 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); 764 } 765 } 766 767 /** 768 * radeon_boot_test_post_card - check and possibly initialize the hw 769 * 770 * @rdev: radeon_device pointer 771 * 772 * Check if the asic is initialized and if not, attempt to initialize 773 * it (all asics). 774 * Returns true if initialized or false if not. 775 */ 776 bool radeon_boot_test_post_card(struct radeon_device *rdev) 777 { 778 if (radeon_card_posted(rdev)) 779 return true; 780 781 if (rdev->bios) { 782 DRM_INFO("GPU not posted. posting now...\n"); 783 if (rdev->is_atom_bios) 784 atom_asic_init(rdev->mode_info.atom_context); 785 else 786 radeon_combios_asic_init(rdev->ddev); 787 return true; 788 } else { 789 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 790 return false; 791 } 792 } 793 794 /** 795 * radeon_dummy_page_init - init dummy page used by the driver 796 * 797 * @rdev: radeon_device pointer 798 * 799 * Allocate the dummy page used by the driver (all asics). 800 * This dummy page is used by the driver as a filler for gart entries 801 * when pages are taken out of the GART 802 * Returns 0 on sucess, -ENOMEM on failure. 803 */ 804 int radeon_dummy_page_init(struct radeon_device *rdev) 805 { 806 if (rdev->dummy_page.dmah) 807 return 0; 808 rdev->dummy_page.dmah = drm_pci_alloc(rdev->ddev, PAGE_SIZE, PAGE_SIZE); 809 if (rdev->dummy_page.dmah == NULL) 810 return -ENOMEM; 811 rdev->dummy_page.addr = (dma_addr_t)rdev->dummy_page.dmah->busaddr; 812 return 0; 813 } 814 815 /** 816 * radeon_dummy_page_fini - free dummy page used by the driver 817 * 818 * @rdev: radeon_device pointer 819 * 820 * Frees the dummy page used by the driver (all asics). 821 */ 822 void radeon_dummy_page_fini(struct radeon_device *rdev) 823 { 824 if (rdev->dummy_page.dmah == NULL) 825 return; 826 drm_pci_free(rdev->ddev, rdev->dummy_page.dmah); 827 rdev->dummy_page.addr = 0; 828 rdev->dummy_page.dmah = NULL; 829 } 830 831 832 /* ATOM accessor methods */ 833 /* 834 * ATOM is an interpreted byte code stored in tables in the vbios. The 835 * driver registers callbacks to access registers and the interpreter 836 * in the driver parses the tables and executes then to program specific 837 * actions (set display modes, asic init, etc.). See radeon_atombios.c, 838 * atombios.h, and atom.c 839 */ 840 841 /** 842 * cail_pll_read - read PLL register 843 * 844 * @info: atom card_info pointer 845 * @reg: PLL register offset 846 * 847 * Provides a PLL register accessor for the atom interpreter (r4xx+). 848 * Returns the value of the PLL register. 849 */ 850 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) 851 { 852 struct radeon_device *rdev = info->dev->dev_private; 853 uint32_t r; 854 855 r = rdev->pll_rreg(rdev, reg); 856 return r; 857 } 858 859 /** 860 * cail_pll_write - write PLL register 861 * 862 * @info: atom card_info pointer 863 * @reg: PLL register offset 864 * @val: value to write to the pll register 865 * 866 * Provides a PLL register accessor for the atom interpreter (r4xx+). 867 */ 868 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) 869 { 870 struct radeon_device *rdev = info->dev->dev_private; 871 872 rdev->pll_wreg(rdev, reg, val); 873 } 874 875 /** 876 * cail_mc_read - read MC (Memory Controller) register 877 * 878 * @info: atom card_info pointer 879 * @reg: MC register offset 880 * 881 * Provides an MC register accessor for the atom interpreter (r4xx+). 882 * Returns the value of the MC register. 883 */ 884 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) 885 { 886 struct radeon_device *rdev = info->dev->dev_private; 887 uint32_t r; 888 889 r = rdev->mc_rreg(rdev, reg); 890 return r; 891 } 892 893 /** 894 * cail_mc_write - write MC (Memory Controller) register 895 * 896 * @info: atom card_info pointer 897 * @reg: MC register offset 898 * @val: value to write to the pll register 899 * 900 * Provides a MC register accessor for the atom interpreter (r4xx+). 901 */ 902 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) 903 { 904 struct radeon_device *rdev = info->dev->dev_private; 905 906 rdev->mc_wreg(rdev, reg, val); 907 } 908 909 /** 910 * cail_reg_write - write MMIO register 911 * 912 * @info: atom card_info pointer 913 * @reg: MMIO register offset 914 * @val: value to write to the pll register 915 * 916 * Provides a MMIO register accessor for the atom interpreter (r4xx+). 917 */ 918 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) 919 { 920 struct radeon_device *rdev = info->dev->dev_private; 921 922 WREG32(reg*4, val); 923 } 924 925 /** 926 * cail_reg_read - read MMIO register 927 * 928 * @info: atom card_info pointer 929 * @reg: MMIO register offset 930 * 931 * Provides an MMIO register accessor for the atom interpreter (r4xx+). 932 * Returns the value of the MMIO register. 933 */ 934 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) 935 { 936 struct radeon_device *rdev = info->dev->dev_private; 937 uint32_t r; 938 939 r = RREG32(reg*4); 940 return r; 941 } 942 943 /** 944 * cail_ioreg_write - write IO register 945 * 946 * @info: atom card_info pointer 947 * @reg: IO register offset 948 * @val: value to write to the pll register 949 * 950 * Provides a IO register accessor for the atom interpreter (r4xx+). 951 */ 952 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) 953 { 954 struct radeon_device *rdev = info->dev->dev_private; 955 956 WREG32_IO(reg*4, val); 957 } 958 959 /** 960 * cail_ioreg_read - read IO register 961 * 962 * @info: atom card_info pointer 963 * @reg: IO register offset 964 * 965 * Provides an IO register accessor for the atom interpreter (r4xx+). 966 * Returns the value of the IO register. 967 */ 968 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) 969 { 970 struct radeon_device *rdev = info->dev->dev_private; 971 uint32_t r; 972 973 r = RREG32_IO(reg*4); 974 return r; 975 } 976 977 /** 978 * radeon_atombios_init - init the driver info and callbacks for atombios 979 * 980 * @rdev: radeon_device pointer 981 * 982 * Initializes the driver info and register access callbacks for the 983 * ATOM interpreter (r4xx+). 984 * Returns 0 on sucess, -ENOMEM on failure. 985 * Called at driver startup. 986 */ 987 int radeon_atombios_init(struct radeon_device *rdev) 988 { 989 struct card_info *atom_card_info = 990 kzalloc(sizeof(struct card_info), GFP_KERNEL); 991 992 if (!atom_card_info) 993 return -ENOMEM; 994 995 rdev->mode_info.atom_card_info = atom_card_info; 996 atom_card_info->dev = rdev->ddev; 997 atom_card_info->reg_read = cail_reg_read; 998 atom_card_info->reg_write = cail_reg_write; 999 /* needed for iio ops */ 1000 if (rdev->rio_mem) { 1001 atom_card_info->ioreg_read = cail_ioreg_read; 1002 atom_card_info->ioreg_write = cail_ioreg_write; 1003 } else { 1004 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); 1005 atom_card_info->ioreg_read = cail_reg_read; 1006 atom_card_info->ioreg_write = cail_reg_write; 1007 } 1008 atom_card_info->mc_read = cail_mc_read; 1009 atom_card_info->mc_write = cail_mc_write; 1010 atom_card_info->pll_read = cail_pll_read; 1011 atom_card_info->pll_write = cail_pll_write; 1012 1013 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); 1014 if (!rdev->mode_info.atom_context) { 1015 radeon_atombios_fini(rdev); 1016 return -ENOMEM; 1017 } 1018 1019 lockinit(&rdev->mode_info.atom_context->mutex, "rmiacmtx", 0, LK_CANRECURSE); 1020 lockinit(&rdev->mode_info.atom_context->scratch_mutex, "rmiacsmtx", 0, LK_CANRECURSE); 1021 radeon_atom_initialize_bios_scratch_regs(rdev->ddev); 1022 atom_allocate_fb_scratch(rdev->mode_info.atom_context); 1023 return 0; 1024 } 1025 1026 /** 1027 * radeon_atombios_fini - free the driver info and callbacks for atombios 1028 * 1029 * @rdev: radeon_device pointer 1030 * 1031 * Frees the driver info and register access callbacks for the ATOM 1032 * interpreter (r4xx+). 1033 * Called at driver shutdown. 1034 */ 1035 void radeon_atombios_fini(struct radeon_device *rdev) 1036 { 1037 if (rdev->mode_info.atom_context) { 1038 kfree(rdev->mode_info.atom_context->scratch); 1039 } 1040 kfree(rdev->mode_info.atom_context); 1041 rdev->mode_info.atom_context = NULL; 1042 kfree(rdev->mode_info.atom_card_info); 1043 rdev->mode_info.atom_card_info = NULL; 1044 } 1045 1046 /* COMBIOS */ 1047 /* 1048 * COMBIOS is the bios format prior to ATOM. It provides 1049 * command tables similar to ATOM, but doesn't have a unified 1050 * parser. See radeon_combios.c 1051 */ 1052 1053 /** 1054 * radeon_combios_init - init the driver info for combios 1055 * 1056 * @rdev: radeon_device pointer 1057 * 1058 * Initializes the driver info for combios (r1xx-r3xx). 1059 * Returns 0 on sucess. 1060 * Called at driver startup. 1061 */ 1062 int radeon_combios_init(struct radeon_device *rdev) 1063 { 1064 radeon_combios_initialize_bios_scratch_regs(rdev->ddev); 1065 return 0; 1066 } 1067 1068 /** 1069 * radeon_combios_fini - free the driver info for combios 1070 * 1071 * @rdev: radeon_device pointer 1072 * 1073 * Frees the driver info for combios (r1xx-r3xx). 1074 * Called at driver shutdown. 1075 */ 1076 void radeon_combios_fini(struct radeon_device *rdev) 1077 { 1078 } 1079 1080 #ifdef DUMBBELL_WIP 1081 /* if we get transitioned to only one device, take VGA back */ 1082 /** 1083 * radeon_vga_set_decode - enable/disable vga decode 1084 * 1085 * @cookie: radeon_device pointer 1086 * @state: enable/disable vga decode 1087 * 1088 * Enable/disable vga decode (all asics). 1089 * Returns VGA resource flags. 1090 */ 1091 static unsigned int radeon_vga_set_decode(void *cookie, bool state) 1092 { 1093 struct radeon_device *rdev = cookie; 1094 radeon_vga_set_state(rdev, state); 1095 if (state) 1096 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | 1097 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 1098 else 1099 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 1100 } 1101 #endif /* DUMBBELL_WIP */ 1102 1103 /** 1104 * radeon_check_pot_argument - check that argument is a power of two 1105 * 1106 * @arg: value to check 1107 * 1108 * Validates that a certain argument is a power of two (all asics). 1109 * Returns true if argument is valid. 1110 */ 1111 static bool radeon_check_pot_argument(int arg) 1112 { 1113 return (arg & (arg - 1)) == 0; 1114 } 1115 1116 /** 1117 * Determine a sensible default GART size according to ASIC family. 1118 * 1119 * @family ASIC family name 1120 */ 1121 static int radeon_gart_size_auto(enum radeon_family family) 1122 { 1123 /* default to a larger gart size on newer asics */ 1124 if (family >= CHIP_TAHITI) 1125 return 2048; 1126 else if (family >= CHIP_RV770) 1127 return 1024; 1128 else 1129 return 512; 1130 } 1131 1132 /** 1133 * radeon_check_arguments - validate module params 1134 * 1135 * @rdev: radeon_device pointer 1136 * 1137 * Validates certain module parameters and updates 1138 * the associated values used by the driver (all asics). 1139 */ 1140 static void radeon_check_arguments(struct radeon_device *rdev) 1141 { 1142 /* vramlimit must be a power of two */ 1143 if (!radeon_check_pot_argument(radeon_vram_limit)) { 1144 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", 1145 radeon_vram_limit); 1146 radeon_vram_limit = 0; 1147 } 1148 1149 if (radeon_gart_size == -1) { 1150 radeon_gart_size = radeon_gart_size_auto(rdev->family); 1151 } 1152 /* gtt size must be power of two and greater or equal to 32M */ 1153 if (radeon_gart_size < 32) { 1154 dev_warn(rdev->dev, "gart size (%d) too small\n", 1155 radeon_gart_size); 1156 radeon_gart_size = radeon_gart_size_auto(rdev->family); 1157 } else if (!radeon_check_pot_argument(radeon_gart_size)) { 1158 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", 1159 radeon_gart_size); 1160 radeon_gart_size = radeon_gart_size_auto(rdev->family); 1161 } 1162 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20; 1163 1164 /* AGP mode can only be -1, 1, 2, 4, 8 */ 1165 switch (radeon_agpmode) { 1166 case -1: 1167 case 0: 1168 case 1: 1169 case 2: 1170 case 4: 1171 case 8: 1172 break; 1173 default: 1174 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " 1175 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); 1176 radeon_agpmode = 0; 1177 break; 1178 } 1179 1180 if (!radeon_check_pot_argument(radeon_vm_size)) { 1181 dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n", 1182 radeon_vm_size); 1183 radeon_vm_size = 4; 1184 } 1185 1186 if (radeon_vm_size < 1) { 1187 dev_warn(rdev->dev, "VM size (%d) too small, min is 1GB\n", 1188 radeon_vm_size); 1189 radeon_vm_size = 4; 1190 } 1191 1192 /* 1193 * Max GPUVM size for Cayman, SI and CI are 40 bits. 1194 */ 1195 if (radeon_vm_size > 1024) { 1196 dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n", 1197 radeon_vm_size); 1198 radeon_vm_size = 4; 1199 } 1200 1201 /* defines number of bits in page table versus page directory, 1202 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the 1203 * page table and the remaining bits are in the page directory */ 1204 if (radeon_vm_block_size == -1) { 1205 1206 /* Total bits covered by PD + PTs */ 1207 unsigned bits = ilog2(radeon_vm_size) + 18; 1208 1209 /* Make sure the PD is 4K in size up to 8GB address space. 1210 Above that split equal between PD and PTs */ 1211 if (radeon_vm_size <= 8) 1212 radeon_vm_block_size = bits - 9; 1213 else 1214 radeon_vm_block_size = (bits + 3) / 2; 1215 1216 } else if (radeon_vm_block_size < 9) { 1217 dev_warn(rdev->dev, "VM page table size (%d) too small\n", 1218 radeon_vm_block_size); 1219 radeon_vm_block_size = 9; 1220 } 1221 1222 if (radeon_vm_block_size > 24 || 1223 (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) { 1224 dev_warn(rdev->dev, "VM page table size (%d) too large\n", 1225 radeon_vm_block_size); 1226 radeon_vm_block_size = 9; 1227 } 1228 } 1229 1230 /** 1231 * radeon_switcheroo_set_state - set switcheroo state 1232 * 1233 * @pdev: pci dev pointer 1234 * @state: vga_switcheroo state 1235 * 1236 * Callback for the switcheroo driver. Suspends or resumes the 1237 * the asics before or after it is powered up using ACPI methods. 1238 */ 1239 #ifdef DUMBBELL_WIP 1240 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) 1241 { 1242 struct drm_device *dev = pci_get_drvdata(pdev); 1243 1244 if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF) 1245 return; 1246 1247 if (state == VGA_SWITCHEROO_ON) { 1248 pr_info("radeon: switched on\n"); 1249 /* don't suspend or resume card normally */ 1250 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1251 1252 radeon_resume_kms(dev, true, true); 1253 1254 dev->switch_power_state = DRM_SWITCH_POWER_ON; 1255 drm_kms_helper_poll_enable(dev); 1256 } else { 1257 pr_info("radeon: switched off\n"); 1258 drm_kms_helper_poll_disable(dev); 1259 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1260 radeon_suspend_kms(dev, true, true, false); 1261 dev->switch_power_state = DRM_SWITCH_POWER_OFF; 1262 } 1263 } 1264 #endif /* DUMBBELL_WIP */ 1265 1266 /** 1267 * radeon_switcheroo_can_switch - see if switcheroo state can change 1268 * 1269 * @pdev: pci dev pointer 1270 * 1271 * Callback for the switcheroo driver. Check of the switcheroo 1272 * state can be changed. 1273 * Returns true if the state can be changed, false if not. 1274 */ 1275 #ifdef DUMBBELL_WIP 1276 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev) 1277 { 1278 struct drm_device *dev = pci_get_drvdata(pdev); 1279 1280 /* 1281 * FIXME: open_count is protected by drm_global_mutex but that would lead to 1282 * locking inversion with the driver load path. And the access here is 1283 * completely racy anyway. So don't bother with locking for now. 1284 */ 1285 return dev->open_count == 0; 1286 } 1287 1288 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = { 1289 .set_gpu_state = radeon_switcheroo_set_state, 1290 .reprobe = NULL, 1291 .can_switch = radeon_switcheroo_can_switch, 1292 }; 1293 #endif /* DUMBBELL_WIP */ 1294 1295 /** 1296 * radeon_device_init - initialize the driver 1297 * 1298 * @rdev: radeon_device pointer 1299 * @pdev: drm dev pointer 1300 * @pdev: pci dev pointer 1301 * @flags: driver flags 1302 * 1303 * Initializes the driver info and hw (all asics). 1304 * Returns 0 for success or an error on failure. 1305 * Called at driver startup. 1306 */ 1307 int radeon_device_init(struct radeon_device *rdev, 1308 struct drm_device *ddev, 1309 struct pci_dev *pdev, 1310 uint32_t flags) 1311 { 1312 int r, i; 1313 int dma_bits; 1314 #ifdef PM_TODO 1315 bool runtime = false; 1316 #endif 1317 1318 rdev->shutdown = false; 1319 rdev->dev = &pdev->dev; 1320 rdev->ddev = ddev; 1321 rdev->pdev = pdev; 1322 rdev->flags = flags; 1323 rdev->family = flags & RADEON_FAMILY_MASK; 1324 rdev->is_atom_bios = false; 1325 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; 1326 rdev->mc.gtt_size = 512 * 1024 * 1024; 1327 rdev->accel_working = false; 1328 rdev->fictitious_range_registered = false; 1329 /* set up ring ids */ 1330 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1331 rdev->ring[i].idx = i; 1332 } 1333 rdev->fence_context = dma_fence_context_alloc(RADEON_NUM_RINGS); 1334 1335 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", 1336 radeon_family_name[rdev->family], pdev->vendor, pdev->device, 1337 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); 1338 1339 /* mutex initialization are all done here so we 1340 * can recall function without having locking issues */ 1341 lockinit(&rdev->ring_lock, "drdrl", 0, LK_CANRECURSE); 1342 lockinit(&rdev->dc_hw_i2c_mutex, "drddi2cm", 0, LK_CANRECURSE); 1343 atomic_set(&rdev->ih.lock, 0); 1344 lockinit(&rdev->gem.mutex, "radeon_gemmtx", 0, LK_CANRECURSE); 1345 lockinit(&rdev->pm.mutex, "drdpmm", 0, LK_CANRECURSE); 1346 lockinit(&rdev->gpu_clock_mutex, "radeon_clockmtx", 0, LK_CANRECURSE); 1347 lockinit(&rdev->srbm_mutex, "radeon_srbm_mutex", 0, LK_CANRECURSE); 1348 lockinit(&rdev->grbm_idx_mutex, "drgim", 0, LK_CANRECURSE); 1349 lockinit(&rdev->pm.mclk_lock, "drpmml", 0, LK_CANRECURSE); 1350 lockinit(&rdev->exclusive_lock, "drdel", 0, LK_CANRECURSE); 1351 init_waitqueue_head(&rdev->irq.vblank_queue); 1352 lockinit(&rdev->mn_lock, "drrml", 0, LK_CANRECURSE); 1353 r = radeon_gem_init(rdev); 1354 if (r) 1355 return r; 1356 1357 radeon_check_arguments(rdev); 1358 /* Adjust VM size here. 1359 * Max GPUVM size for cayman+ is 40 bits. 1360 */ 1361 rdev->vm_manager.max_pfn = radeon_vm_size << 18; 1362 1363 /* Set asic functions */ 1364 r = radeon_asic_init(rdev); 1365 if (r) 1366 return r; 1367 1368 /* all of the newer IGP chips have an internal gart 1369 * However some rs4xx report as AGP, so remove that here. 1370 */ 1371 if ((rdev->family >= CHIP_RS400) && 1372 (rdev->flags & RADEON_IS_IGP)) { 1373 rdev->flags &= ~RADEON_IS_AGP; 1374 } 1375 1376 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { 1377 radeon_agp_disable(rdev); 1378 } 1379 1380 /* Set the internal MC address mask 1381 * This is the max address of the GPU's 1382 * internal address space. 1383 */ 1384 if (rdev->family >= CHIP_CAYMAN) 1385 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1386 else if (rdev->family >= CHIP_CEDAR) 1387 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */ 1388 else 1389 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */ 1390 1391 /* set DMA mask + need_dma32 flags. 1392 * PCIE - can handle 40-bits. 1393 * IGP - can handle 40-bits 1394 * AGP - generally dma32 is safest 1395 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 1396 */ 1397 rdev->need_dma32 = false; 1398 if (rdev->flags & RADEON_IS_AGP) 1399 rdev->need_dma32 = true; 1400 if ((rdev->flags & RADEON_IS_PCI) && 1401 (rdev->family <= CHIP_RS740)) 1402 rdev->need_dma32 = true; 1403 #ifdef CONFIG_PPC64 1404 if (rdev->family == CHIP_CEDAR) 1405 rdev->need_dma32 = true; 1406 #endif 1407 1408 dma_bits = rdev->need_dma32 ? 32 : 40; 1409 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 1410 if (r) { 1411 rdev->need_dma32 = true; 1412 dma_bits = 32; 1413 pr_warn("radeon: No suitable DMA available\n"); 1414 } 1415 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 1416 if (r) { 1417 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32)); 1418 pr_warn("radeon: No coherent DMA available\n"); 1419 } 1420 1421 /* Registers mapping */ 1422 /* TODO: block userspace mapping of io register */ 1423 lockinit(&rdev->mmio_idx_lock, "rdnmidl", 0, 0); 1424 lockinit(&rdev->smc_idx_lock, "rdnsil", 0, 0); 1425 lockinit(&rdev->pll_idx_lock, "rdnpll", 0, 0); 1426 lockinit(&rdev->mc_idx_lock, "rdnmcil", 0, 0); 1427 lockinit(&rdev->pcie_idx_lock, "rdnpil", 0, 0); 1428 lockinit(&rdev->pciep_idx_lock, "rdnppil", 0, 0); 1429 lockinit(&rdev->pif_idx_lock, "rdnpif", 0, 0); 1430 lockinit(&rdev->cg_idx_lock, "rdncgil", 0, 0); 1431 lockinit(&rdev->uvd_idx_lock, "rdnuvd", 0, 0); 1432 lockinit(&rdev->rcu_idx_lock, "rdnrcu", 0, 0); 1433 lockinit(&rdev->didt_idx_lock, "rdndidt", 0, 0); 1434 lockinit(&rdev->end_idx_lock, "rdneil", 0, 0); 1435 if (rdev->family >= CHIP_BONAIRE) { 1436 rdev->rmmio_base = pci_resource_start(rdev->pdev, 5); 1437 rdev->rmmio_size = pci_resource_len(rdev->pdev, 5); 1438 } else { 1439 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); 1440 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); 1441 } 1442 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); 1443 if (rdev->rmmio == NULL) 1444 return -ENOMEM; 1445 1446 /* doorbell bar mapping */ 1447 if (rdev->family >= CHIP_BONAIRE) 1448 radeon_doorbell_init(rdev); 1449 1450 /* io port mapping */ 1451 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 1452 uint32_t data; 1453 1454 data = pci_read_config(rdev->dev->bsddev, PCIR_BAR(i), 4); 1455 if (PCI_BAR_IO(data)) { 1456 rdev->rio_rid = PCIR_BAR(i); 1457 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i); 1458 rdev->rio_mem = bus_alloc_resource_any(rdev->dev->bsddev, 1459 SYS_RES_IOPORT, &rdev->rio_rid, 1460 RF_ACTIVE | RF_SHAREABLE); 1461 break; 1462 } 1463 } 1464 if (rdev->rio_mem == NULL) 1465 DRM_ERROR("Unable to find PCI I/O BAR\n"); 1466 1467 if (rdev->flags & RADEON_IS_PX) 1468 radeon_device_handle_px_quirks(rdev); 1469 1470 #ifdef DUMBBELL_WIP 1471 /* if we have > 1 VGA cards, then disable the radeon VGA resources */ 1472 /* this will fail for cards that aren't VGA class devices, just 1473 * ignore it */ 1474 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); 1475 1476 if (rdev->flags & RADEON_IS_PX) 1477 runtime = true; 1478 if (!pci_is_thunderbolt_attached(rdev->pdev)) 1479 vga_switcheroo_register_client(rdev->pdev, 1480 &radeon_switcheroo_ops, runtime); 1481 if (runtime) 1482 vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain); 1483 #endif 1484 1485 r = radeon_init(rdev); 1486 if (r) 1487 goto failed; 1488 1489 r = radeon_gem_debugfs_init(rdev); 1490 if (r) { 1491 DRM_ERROR("registering gem debugfs failed (%d).\n", r); 1492 } 1493 1494 r = radeon_mst_debugfs_init(rdev); 1495 if (r) { 1496 DRM_ERROR("registering mst debugfs failed (%d).\n", r); 1497 } 1498 1499 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { 1500 /* Acceleration not working on AGP card try again 1501 * with fallback to PCI or PCIE GART 1502 */ 1503 radeon_asic_reset(rdev); 1504 radeon_fini(rdev); 1505 radeon_agp_disable(rdev); 1506 r = radeon_init(rdev); 1507 if (r) 1508 goto failed; 1509 } 1510 1511 r = radeon_ib_ring_tests(rdev); 1512 if (r) 1513 DRM_ERROR("ib ring test failed (%d).\n", r); 1514 1515 DRM_INFO("%s: Taking over the fictitious range 0x%lx-0x%llx\n", 1516 __func__, (uintmax_t)rdev->mc.aper_base, 1517 (uintmax_t)rdev->mc.aper_base + rdev->mc.visible_vram_size); 1518 r = vm_phys_fictitious_reg_range( 1519 rdev->mc.aper_base, 1520 rdev->mc.aper_base + rdev->mc.visible_vram_size, 1521 VM_MEMATTR_WRITE_COMBINING); 1522 if (r != 0) { 1523 DRM_ERROR("Failed to register fictitious range " 1524 "0x%lx-0x%llx (%d).\n", (uintmax_t)rdev->mc.aper_base, 1525 (uintmax_t)rdev->mc.aper_base + rdev->mc.visible_vram_size, r); 1526 return (-r); 1527 } 1528 rdev->fictitious_range_registered = true; 1529 1530 /* 1531 * Turks/Thames GPU will freeze whole laptop if DPM is not restarted 1532 * after the CP ring have chew one packet at least. Hence here we stop 1533 * and restart DPM after the radeon_ib_ring_tests(). 1534 */ 1535 if (rdev->pm.dpm_enabled && 1536 (rdev->pm.pm_method == PM_METHOD_DPM) && 1537 (rdev->family == CHIP_TURKS) && 1538 (rdev->flags & RADEON_IS_MOBILITY)) { 1539 mutex_lock(&rdev->pm.mutex); 1540 radeon_dpm_disable(rdev); 1541 radeon_dpm_enable(rdev); 1542 mutex_unlock(&rdev->pm.mutex); 1543 } 1544 1545 if ((radeon_testing & 1)) { 1546 if (rdev->accel_working) 1547 radeon_test_moves(rdev); 1548 else 1549 DRM_INFO("radeon: acceleration disabled, skipping move tests\n"); 1550 } 1551 if ((radeon_testing & 2)) { 1552 if (rdev->accel_working) 1553 radeon_test_syncing(rdev); 1554 else 1555 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n"); 1556 } 1557 if (radeon_benchmarking) { 1558 if (rdev->accel_working) 1559 radeon_benchmark(rdev, radeon_benchmarking); 1560 else 1561 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n"); 1562 } 1563 rdev->dummy_page.entry = radeon_gart_get_page_entry(rdev->dummy_page.addr, 1564 RADEON_GART_PAGE_DUMMY); 1565 return 0; 1566 1567 failed: 1568 #if 0 1569 if (runtime) 1570 vga_switcheroo_fini_domain_pm_ops(rdev->dev); 1571 #endif 1572 return r; 1573 } 1574 1575 /** 1576 * radeon_device_fini - tear down the driver 1577 * 1578 * @rdev: radeon_device pointer 1579 * 1580 * Tear down the driver info (all asics). 1581 * Called at driver shutdown. 1582 */ 1583 void radeon_device_fini(struct radeon_device *rdev) 1584 { 1585 DRM_INFO("radeon: finishing device.\n"); 1586 rdev->shutdown = true; 1587 /* evict vram memory */ 1588 radeon_bo_evict_vram(rdev); 1589 1590 if (rdev->fictitious_range_registered) { 1591 vm_phys_fictitious_unreg_range( 1592 rdev->mc.aper_base, 1593 rdev->mc.aper_base + rdev->mc.visible_vram_size); 1594 } 1595 1596 radeon_fini(rdev); 1597 #ifdef DUMBBELL_WIP 1598 if (!pci_is_thunderbolt_attached(rdev->pdev)) 1599 vga_switcheroo_unregister_client(rdev->pdev); 1600 if (rdev->flags & RADEON_IS_PX) 1601 vga_switcheroo_fini_domain_pm_ops(rdev->dev); 1602 vga_client_register(rdev->pdev, NULL, NULL, NULL); 1603 #endif /* DUMBBELL_WIP */ 1604 if (rdev->rio_mem) 1605 bus_release_resource(rdev->dev->bsddev, SYS_RES_IOPORT, rdev->rio_rid, 1606 rdev->rio_mem); 1607 rdev->rio_mem = NULL; 1608 iounmap(rdev->rmmio); 1609 rdev->rmmio = NULL; 1610 if (rdev->family >= CHIP_BONAIRE) 1611 radeon_doorbell_fini(rdev); 1612 } 1613 1614 1615 /* 1616 * Suspend & resume. 1617 */ 1618 /** 1619 * radeon_suspend_kms - initiate device suspend 1620 * 1621 * @pdev: drm dev pointer 1622 * @state: suspend state 1623 * 1624 * Puts the hw in the suspend state (all asics). 1625 * Returns 0 for success or an error on failure. 1626 * Called at driver suspend. 1627 */ 1628 int radeon_suspend_kms(struct drm_device *dev, bool suspend, 1629 bool fbcon, bool freeze) 1630 { 1631 struct radeon_device *rdev; 1632 struct drm_crtc *crtc; 1633 struct drm_connector *connector; 1634 int i, r; 1635 1636 if (dev == NULL || dev->dev_private == NULL) { 1637 return -ENODEV; 1638 } 1639 1640 rdev = dev->dev_private; 1641 1642 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1643 return 0; 1644 1645 drm_kms_helper_poll_disable(dev); 1646 1647 drm_modeset_lock_all(dev); 1648 /* turn off display hw */ 1649 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1650 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 1651 } 1652 drm_modeset_unlock_all(dev); 1653 1654 /* unpin the front buffers and cursors */ 1655 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1656 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1657 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->primary->fb); 1658 struct radeon_bo *robj; 1659 1660 if (radeon_crtc->cursor_bo) { 1661 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); 1662 r = radeon_bo_reserve(robj, false); 1663 if (r == 0) { 1664 radeon_bo_unpin(robj); 1665 radeon_bo_unreserve(robj); 1666 } 1667 } 1668 1669 if (rfb == NULL || rfb->obj == NULL) { 1670 continue; 1671 } 1672 robj = gem_to_radeon_bo(rfb->obj); 1673 /* don't unpin kernel fb objects */ 1674 if (!radeon_fbdev_robj_is_fb(rdev, robj)) { 1675 r = radeon_bo_reserve(robj, false); 1676 if (r == 0) { 1677 radeon_bo_unpin(robj); 1678 radeon_bo_unreserve(robj); 1679 } 1680 } 1681 } 1682 /* evict vram memory */ 1683 radeon_bo_evict_vram(rdev); 1684 1685 /* wait for gpu to finish processing current batch */ 1686 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1687 r = radeon_fence_wait_empty(rdev, i); 1688 if (r) { 1689 /* delay GPU reset to resume */ 1690 radeon_fence_driver_force_completion(rdev, i); 1691 } 1692 } 1693 1694 radeon_save_bios_scratch_regs(rdev); 1695 1696 radeon_suspend(rdev); 1697 radeon_hpd_fini(rdev); 1698 /* evict remaining vram memory 1699 * This second call to evict vram is to evict the gart page table 1700 * using the CPU. 1701 */ 1702 radeon_bo_evict_vram(rdev); 1703 1704 radeon_agp_suspend(rdev); 1705 1706 pci_save_state(device_get_parent(rdev->dev->bsddev)); 1707 if (freeze && rdev->family >= CHIP_CEDAR && !(rdev->flags & RADEON_IS_IGP)) { 1708 rdev->asic->asic_reset(rdev, true); 1709 #if 0 1710 pci_restore_state(dev->pdev); 1711 #endif 1712 } else if (suspend) { 1713 /* Shut down the device */ 1714 #if 0 1715 pci_disable_device(dev->pdev); 1716 pci_set_power_state(dev->pdev, PCI_D3hot); 1717 #endif 1718 } 1719 1720 if (fbcon) { 1721 #ifdef DUMBBELL_WIP 1722 console_lock(); 1723 #endif /* DUMBBELL_WIP */ 1724 radeon_fbdev_set_suspend(rdev, 1); 1725 #ifdef DUMBBELL_WIP 1726 console_unlock(); 1727 #endif /* DUMBBELL_WIP */ 1728 } 1729 rdev->dummy_page.entry = radeon_gart_get_page_entry(rdev->dummy_page.addr, 1730 RADEON_GART_PAGE_DUMMY); 1731 return 0; 1732 } 1733 1734 /** 1735 * radeon_resume_kms - initiate device resume 1736 * 1737 * @pdev: drm dev pointer 1738 * 1739 * Bring the hw back to operating state (all asics). 1740 * Returns 0 for success or an error on failure. 1741 * Called at driver resume. 1742 */ 1743 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon) 1744 { 1745 struct drm_connector *connector; 1746 struct radeon_device *rdev = dev->dev_private; 1747 struct drm_crtc *crtc; 1748 int r; 1749 1750 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1751 return 0; 1752 1753 #ifdef DUMBBELL_WIP 1754 if (fbcon) { 1755 console_lock(); 1756 } 1757 #endif /* DUMBBELL_WIP */ 1758 if (resume) { 1759 #ifdef DUMBBELL_WIP 1760 pci_set_power_state(dev->pdev, PCI_D0); 1761 pci_restore_state(dev->pdev); 1762 if (pci_enable_device(dev->pdev)) { 1763 if (fbcon) 1764 console_unlock(); 1765 return -1; 1766 } 1767 #endif /* DUMBBELL_WIP */ 1768 } 1769 /* resume AGP if in use */ 1770 radeon_agp_resume(rdev); 1771 radeon_resume(rdev); 1772 1773 r = radeon_ib_ring_tests(rdev); 1774 if (r) 1775 DRM_ERROR("ib ring test failed (%d).\n", r); 1776 1777 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 1778 /* do dpm late init */ 1779 r = radeon_pm_late_init(rdev); 1780 if (r) { 1781 rdev->pm.dpm_enabled = false; 1782 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1783 } 1784 } else { 1785 /* resume old pm late */ 1786 radeon_pm_resume(rdev); 1787 } 1788 1789 radeon_restore_bios_scratch_regs(rdev); 1790 1791 /* pin cursors */ 1792 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1793 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1794 1795 if (radeon_crtc->cursor_bo) { 1796 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); 1797 r = radeon_bo_reserve(robj, false); 1798 if (r == 0) { 1799 /* Only 27 bit offset for legacy cursor */ 1800 r = radeon_bo_pin_restricted(robj, 1801 RADEON_GEM_DOMAIN_VRAM, 1802 ASIC_IS_AVIVO(rdev) ? 1803 0 : 1 << 27, 1804 (u64 *)&radeon_crtc->cursor_addr); 1805 if (r != 0) 1806 DRM_ERROR("Failed to pin cursor BO (%d)\n", r); 1807 radeon_bo_unreserve(robj); 1808 } 1809 } 1810 } 1811 1812 /* init dig PHYs, disp eng pll */ 1813 if (rdev->is_atom_bios) { 1814 radeon_atom_encoder_init(rdev); 1815 radeon_atom_disp_eng_pll_init(rdev); 1816 /* turn on the BL */ 1817 if (rdev->mode_info.bl_encoder) { 1818 u8 bl_level = radeon_get_backlight_level(rdev, 1819 rdev->mode_info.bl_encoder); 1820 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, 1821 bl_level); 1822 } 1823 } 1824 /* reset hpd state */ 1825 radeon_hpd_init(rdev); 1826 /* blat the mode back in */ 1827 if (fbcon) { 1828 drm_helper_resume_force_mode(dev); 1829 /* turn on display hw */ 1830 drm_modeset_lock_all(dev); 1831 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1832 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 1833 } 1834 drm_modeset_unlock_all(dev); 1835 } 1836 1837 drm_kms_helper_poll_enable(dev); 1838 1839 /* set the power state here in case we are a PX system or headless */ 1840 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 1841 radeon_pm_compute_clocks(rdev); 1842 1843 if (fbcon) { 1844 radeon_fbdev_set_suspend(rdev, 0); 1845 #ifdef DUMBBELL_WIP 1846 console_unlock(); 1847 #endif /* DUMBBELL_WIP */ 1848 } 1849 1850 return 0; 1851 } 1852 1853 /** 1854 * radeon_gpu_reset - reset the asic 1855 * 1856 * @rdev: radeon device pointer 1857 * 1858 * Attempt the reset the GPU if it has hung (all asics). 1859 * Returns 0 for success or an error on failure. 1860 */ 1861 int radeon_gpu_reset(struct radeon_device *rdev) 1862 { 1863 unsigned ring_sizes[RADEON_NUM_RINGS]; 1864 uint32_t *ring_data[RADEON_NUM_RINGS]; 1865 1866 bool saved = false; 1867 1868 int i, r; 1869 int resched; 1870 1871 down_write(&rdev->exclusive_lock); 1872 1873 if (!rdev->needs_reset) { 1874 up_write(&rdev->exclusive_lock); 1875 return 0; 1876 } 1877 1878 atomic_inc(&rdev->gpu_reset_counter); 1879 1880 radeon_save_bios_scratch_regs(rdev); 1881 /* block TTM */ 1882 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); 1883 radeon_suspend(rdev); 1884 radeon_hpd_fini(rdev); 1885 1886 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1887 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i], 1888 &ring_data[i]); 1889 if (ring_sizes[i]) { 1890 saved = true; 1891 dev_info(rdev->dev, "Saved %d dwords of commands " 1892 "on ring %d.\n", ring_sizes[i], i); 1893 } 1894 } 1895 1896 r = radeon_asic_reset(rdev); 1897 if (!r) { 1898 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n"); 1899 radeon_resume(rdev); 1900 } 1901 1902 radeon_restore_bios_scratch_regs(rdev); 1903 1904 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1905 if (!r && ring_data[i]) { 1906 radeon_ring_restore(rdev, &rdev->ring[i], 1907 ring_sizes[i], ring_data[i]); 1908 } else { 1909 radeon_fence_driver_force_completion(rdev, i); 1910 kfree(ring_data[i]); 1911 } 1912 } 1913 1914 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 1915 /* do dpm late init */ 1916 r = radeon_pm_late_init(rdev); 1917 if (r) { 1918 rdev->pm.dpm_enabled = false; 1919 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1920 } 1921 } else { 1922 /* resume old pm late */ 1923 radeon_pm_resume(rdev); 1924 } 1925 1926 /* init dig PHYs, disp eng pll */ 1927 if (rdev->is_atom_bios) { 1928 radeon_atom_encoder_init(rdev); 1929 radeon_atom_disp_eng_pll_init(rdev); 1930 /* turn on the BL */ 1931 if (rdev->mode_info.bl_encoder) { 1932 u8 bl_level = radeon_get_backlight_level(rdev, 1933 rdev->mode_info.bl_encoder); 1934 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, 1935 bl_level); 1936 } 1937 } 1938 /* reset hpd state */ 1939 radeon_hpd_init(rdev); 1940 1941 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); 1942 1943 rdev->in_reset = true; 1944 rdev->needs_reset = false; 1945 1946 #if 0 1947 downgrade_write(&rdev->exclusive_lock); 1948 #endif 1949 1950 drm_helper_resume_force_mode(rdev->ddev); 1951 1952 /* set the power state here in case we are a PX system or headless */ 1953 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 1954 radeon_pm_compute_clocks(rdev); 1955 1956 if (!r) { 1957 r = radeon_ib_ring_tests(rdev); 1958 if (r && saved) 1959 r = -EAGAIN; 1960 } else { 1961 /* bad news, how to tell it to userspace ? */ 1962 dev_info(rdev->dev, "GPU reset failed\n"); 1963 } 1964 1965 rdev->needs_reset = r == -EAGAIN; 1966 rdev->in_reset = false; 1967 1968 up_read(&rdev->exclusive_lock); 1969 return r; 1970 } 1971 1972 1973 /* 1974 * Debugfs 1975 */ 1976 int radeon_debugfs_add_files(struct radeon_device *rdev, 1977 struct drm_info_list *files, 1978 unsigned nfiles) 1979 { 1980 unsigned i; 1981 1982 for (i = 0; i < rdev->debugfs_count; i++) { 1983 if (rdev->debugfs[i].files == files) { 1984 /* Already registered */ 1985 return 0; 1986 } 1987 } 1988 1989 i = rdev->debugfs_count + 1; 1990 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) { 1991 DRM_ERROR("Reached maximum number of debugfs components.\n"); 1992 DRM_ERROR("Report so we increase " 1993 "RADEON_DEBUGFS_MAX_COMPONENTS.\n"); 1994 return -EINVAL; 1995 } 1996 rdev->debugfs[rdev->debugfs_count].files = files; 1997 rdev->debugfs[rdev->debugfs_count].num_files = nfiles; 1998 rdev->debugfs_count = i; 1999 #if defined(CONFIG_DEBUG_FS) 2000 drm_debugfs_create_files(files, nfiles, 2001 rdev->ddev->primary->debugfs_root, 2002 rdev->ddev->primary); 2003 #endif 2004 return 0; 2005 } 2006