1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * 28 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_device.c 255573 2013-09-14 17:24:41Z dumbbell $ 29 */ 30 #include <drm/drmP.h> 31 #include <drm/drm_crtc_helper.h> 32 #include <uapi_drm/radeon_drm.h> 33 #include <asm/io.h> 34 #include "radeon_reg.h" 35 #include "radeon.h" 36 #include "atom.h" 37 38 static const char radeon_family_name[][16] = { 39 "R100", 40 "RV100", 41 "RS100", 42 "RV200", 43 "RS200", 44 "R200", 45 "RV250", 46 "RS300", 47 "RV280", 48 "R300", 49 "R350", 50 "RV350", 51 "RV380", 52 "R420", 53 "R423", 54 "RV410", 55 "RS400", 56 "RS480", 57 "RS600", 58 "RS690", 59 "RS740", 60 "RV515", 61 "R520", 62 "RV530", 63 "RV560", 64 "RV570", 65 "R580", 66 "R600", 67 "RV610", 68 "RV630", 69 "RV670", 70 "RV620", 71 "RV635", 72 "RS780", 73 "RS880", 74 "RV770", 75 "RV730", 76 "RV710", 77 "RV740", 78 "CEDAR", 79 "REDWOOD", 80 "JUNIPER", 81 "CYPRESS", 82 "HEMLOCK", 83 "PALM", 84 "SUMO", 85 "SUMO2", 86 "BARTS", 87 "TURKS", 88 "CAICOS", 89 "CAYMAN", 90 "ARUBA", 91 "TAHITI", 92 "PITCAIRN", 93 "VERDE", 94 "OLAND", 95 "HAINAN", 96 "BONAIRE", 97 "KAVERI", 98 "KABINI", 99 "HAWAII", 100 "MULLINS", 101 "LAST", 102 }; 103 104 #define RADEON_PX_QUIRK_DISABLE_PX (1 << 0) 105 #define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1) 106 107 struct radeon_px_quirk { 108 u32 chip_vendor; 109 u32 chip_device; 110 u32 subsys_vendor; 111 u32 subsys_device; 112 u32 px_quirk_flags; 113 }; 114 115 static struct radeon_px_quirk radeon_px_quirk_list[] = { 116 /* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m) 117 * https://bugzilla.kernel.org/show_bug.cgi?id=74551 118 */ 119 { PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX }, 120 /* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU 121 * https://bugzilla.kernel.org/show_bug.cgi?id=51381 122 */ 123 { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX }, 124 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU 125 * https://bugzilla.kernel.org/show_bug.cgi?id=51381 126 */ 127 { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX }, 128 /* macbook pro 8.2 */ 129 { PCI_VENDOR_ID_ATI, 0x6741, PCI_VENDOR_ID_APPLE, 0x00e2, RADEON_PX_QUIRK_LONG_WAKEUP }, 130 { 0, 0, 0, 0, 0 }, 131 }; 132 133 bool radeon_is_px(struct drm_device *dev) 134 { 135 struct radeon_device *rdev = dev->dev_private; 136 137 if (rdev->flags & RADEON_IS_PX) 138 return true; 139 return false; 140 } 141 142 static void radeon_device_handle_px_quirks(struct radeon_device *rdev) 143 { 144 struct radeon_px_quirk *p = radeon_px_quirk_list; 145 146 /* Apply PX quirks */ 147 while (p && p->chip_device != 0) { 148 if (rdev->pdev->vendor == p->chip_vendor && 149 rdev->pdev->device == p->chip_device && 150 rdev->pdev->subsystem_vendor == p->subsys_vendor && 151 rdev->pdev->subsystem_device == p->subsys_device) { 152 rdev->px_quirk_flags = p->px_quirk_flags; 153 break; 154 } 155 ++p; 156 } 157 158 if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX) 159 rdev->flags &= ~RADEON_IS_PX; 160 } 161 162 /** 163 * radeon_program_register_sequence - program an array of registers. 164 * 165 * @rdev: radeon_device pointer 166 * @registers: pointer to the register array 167 * @array_size: size of the register array 168 * 169 * Programs an array or registers with and and or masks. 170 * This is a helper for setting golden registers. 171 */ 172 void radeon_program_register_sequence(struct radeon_device *rdev, 173 const u32 *registers, 174 const u32 array_size) 175 { 176 u32 tmp, reg, and_mask, or_mask; 177 int i; 178 179 if (array_size % 3) 180 return; 181 182 for (i = 0; i < array_size; i +=3) { 183 reg = registers[i + 0]; 184 and_mask = registers[i + 1]; 185 or_mask = registers[i + 2]; 186 187 if (and_mask == 0xffffffff) { 188 tmp = or_mask; 189 } else { 190 tmp = RREG32(reg); 191 tmp &= ~and_mask; 192 tmp |= or_mask; 193 } 194 WREG32(reg, tmp); 195 } 196 } 197 198 void radeon_pci_config_reset(struct radeon_device *rdev) 199 { 200 pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA); 201 } 202 203 /** 204 * radeon_surface_init - Clear GPU surface registers. 205 * 206 * @rdev: radeon_device pointer 207 * 208 * Clear GPU surface registers (r1xx-r5xx). 209 */ 210 void radeon_surface_init(struct radeon_device *rdev) 211 { 212 /* FIXME: check this out */ 213 if (rdev->family < CHIP_R600) { 214 int i; 215 216 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 217 if (rdev->surface_regs[i].bo) 218 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); 219 else 220 radeon_clear_surface_reg(rdev, i); 221 } 222 /* enable surfaces */ 223 WREG32(RADEON_SURFACE_CNTL, 0); 224 } 225 } 226 227 /* 228 * GPU scratch registers helpers function. 229 */ 230 /** 231 * radeon_scratch_init - Init scratch register driver information. 232 * 233 * @rdev: radeon_device pointer 234 * 235 * Init CP scratch register driver information (r1xx-r5xx) 236 */ 237 void radeon_scratch_init(struct radeon_device *rdev) 238 { 239 int i; 240 241 /* FIXME: check this out */ 242 if (rdev->family < CHIP_R300) { 243 rdev->scratch.num_reg = 5; 244 } else { 245 rdev->scratch.num_reg = 7; 246 } 247 rdev->scratch.reg_base = RADEON_SCRATCH_REG0; 248 for (i = 0; i < rdev->scratch.num_reg; i++) { 249 rdev->scratch.free[i] = true; 250 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 251 } 252 } 253 254 /** 255 * radeon_scratch_get - Allocate a scratch register 256 * 257 * @rdev: radeon_device pointer 258 * @reg: scratch register mmio offset 259 * 260 * Allocate a CP scratch register for use by the driver (all asics). 261 * Returns 0 on success or -EINVAL on failure. 262 */ 263 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) 264 { 265 int i; 266 267 for (i = 0; i < rdev->scratch.num_reg; i++) { 268 if (rdev->scratch.free[i]) { 269 rdev->scratch.free[i] = false; 270 *reg = rdev->scratch.reg[i]; 271 return 0; 272 } 273 } 274 return -EINVAL; 275 } 276 277 /** 278 * radeon_scratch_free - Free a scratch register 279 * 280 * @rdev: radeon_device pointer 281 * @reg: scratch register mmio offset 282 * 283 * Free a CP scratch register allocated for use by the driver (all asics) 284 */ 285 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) 286 { 287 int i; 288 289 for (i = 0; i < rdev->scratch.num_reg; i++) { 290 if (rdev->scratch.reg[i] == reg) { 291 rdev->scratch.free[i] = true; 292 return; 293 } 294 } 295 } 296 297 /* 298 * GPU doorbell aperture helpers function. 299 */ 300 /** 301 * radeon_doorbell_init - Init doorbell driver information. 302 * 303 * @rdev: radeon_device pointer 304 * 305 * Init doorbell driver information (CIK) 306 * Returns 0 on success, error on failure. 307 */ 308 static int radeon_doorbell_init(struct radeon_device *rdev) 309 { 310 /* doorbell bar mapping */ 311 rdev->doorbell.base = pci_resource_start(rdev->pdev, 2); 312 rdev->doorbell.size = pci_resource_len(rdev->pdev, 2); 313 314 rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS); 315 if (rdev->doorbell.num_doorbells == 0) 316 return -EINVAL; 317 318 rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32)); 319 if (rdev->doorbell.ptr == NULL) { 320 return -ENOMEM; 321 } 322 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base); 323 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size); 324 325 memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used)); 326 327 return 0; 328 } 329 330 /** 331 * radeon_doorbell_fini - Tear down doorbell driver information. 332 * 333 * @rdev: radeon_device pointer 334 * 335 * Tear down doorbell driver information (CIK) 336 */ 337 static void radeon_doorbell_fini(struct radeon_device *rdev) 338 { 339 iounmap(rdev->doorbell.ptr, rdev->doorbell.size); 340 rdev->doorbell.ptr = NULL; 341 } 342 343 /** 344 * radeon_doorbell_get - Allocate a doorbell entry 345 * 346 * @rdev: radeon_device pointer 347 * @doorbell: doorbell index 348 * 349 * Allocate a doorbell for use by the driver (all asics). 350 * Returns 0 on success or -EINVAL on failure. 351 */ 352 int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell) 353 { 354 unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells); 355 if (offset < rdev->doorbell.num_doorbells) { 356 __set_bit(offset, rdev->doorbell.used); 357 *doorbell = offset; 358 return 0; 359 } else { 360 return -EINVAL; 361 } 362 } 363 364 /** 365 * radeon_doorbell_free - Free a doorbell entry 366 * 367 * @rdev: radeon_device pointer 368 * @doorbell: doorbell index 369 * 370 * Free a doorbell allocated for use by the driver (all asics) 371 */ 372 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell) 373 { 374 if (doorbell < rdev->doorbell.num_doorbells) 375 __clear_bit(doorbell, rdev->doorbell.used); 376 } 377 378 /* 379 * radeon_wb_*() 380 * Writeback is the the method by which the the GPU updates special pages 381 * in memory with the status of certain GPU events (fences, ring pointers, 382 * etc.). 383 */ 384 385 /** 386 * radeon_wb_disable - Disable Writeback 387 * 388 * @rdev: radeon_device pointer 389 * 390 * Disables Writeback (all asics). Used for suspend. 391 */ 392 void radeon_wb_disable(struct radeon_device *rdev) 393 { 394 rdev->wb.enabled = false; 395 } 396 397 /** 398 * radeon_wb_fini - Disable Writeback and free memory 399 * 400 * @rdev: radeon_device pointer 401 * 402 * Disables Writeback and frees the Writeback memory (all asics). 403 * Used at driver shutdown. 404 */ 405 void radeon_wb_fini(struct radeon_device *rdev) 406 { 407 radeon_wb_disable(rdev); 408 if (rdev->wb.wb_obj) { 409 if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) { 410 radeon_bo_kunmap(rdev->wb.wb_obj); 411 radeon_bo_unpin(rdev->wb.wb_obj); 412 radeon_bo_unreserve(rdev->wb.wb_obj); 413 } 414 radeon_bo_unref(&rdev->wb.wb_obj); 415 rdev->wb.wb = NULL; 416 rdev->wb.wb_obj = NULL; 417 } 418 } 419 420 /** 421 * radeon_wb_init- Init Writeback driver info and allocate memory 422 * 423 * @rdev: radeon_device pointer 424 * 425 * Disables Writeback and frees the Writeback memory (all asics). 426 * Used at driver startup. 427 * Returns 0 on success or an -error on failure. 428 */ 429 int radeon_wb_init(struct radeon_device *rdev) 430 { 431 int r; 432 void *wb_ptr; 433 434 if (rdev->wb.wb_obj == NULL) { 435 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, 436 RADEON_GEM_DOMAIN_GTT, 0, NULL, 437 &rdev->wb.wb_obj); 438 if (r) { 439 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); 440 return r; 441 } 442 r = radeon_bo_reserve(rdev->wb.wb_obj, false); 443 if (unlikely(r != 0)) { 444 radeon_wb_fini(rdev); 445 return r; 446 } 447 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, 448 &rdev->wb.gpu_addr); 449 if (r) { 450 radeon_bo_unreserve(rdev->wb.wb_obj); 451 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); 452 radeon_wb_fini(rdev); 453 return r; 454 } 455 wb_ptr = &rdev->wb.wb; 456 r = radeon_bo_kmap(rdev->wb.wb_obj, wb_ptr); 457 radeon_bo_unreserve(rdev->wb.wb_obj); 458 if (r) { 459 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); 460 radeon_wb_fini(rdev); 461 return r; 462 } 463 /* clear wb memory */ 464 memset(*(void **)wb_ptr, 0, RADEON_GPU_PAGE_SIZE); 465 } 466 467 /* disable event_write fences */ 468 rdev->wb.use_event = false; 469 /* disabled via module param */ 470 if (radeon_no_wb == 1) { 471 rdev->wb.enabled = false; 472 } else { 473 if (rdev->flags & RADEON_IS_AGP) { 474 /* often unreliable on AGP */ 475 rdev->wb.enabled = false; 476 } else if (rdev->family < CHIP_R300) { 477 /* often unreliable on pre-r300 */ 478 rdev->wb.enabled = false; 479 } else { 480 rdev->wb.enabled = true; 481 /* event_write fences are only available on r600+ */ 482 if (rdev->family >= CHIP_R600) { 483 rdev->wb.use_event = true; 484 } 485 } 486 } 487 /* always use writeback/events on NI, APUs */ 488 if (rdev->family >= CHIP_PALM) { 489 rdev->wb.enabled = true; 490 rdev->wb.use_event = true; 491 } 492 493 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis"); 494 495 return 0; 496 } 497 498 /** 499 * radeon_vram_location - try to find VRAM location 500 * @rdev: radeon device structure holding all necessary informations 501 * @mc: memory controller structure holding memory informations 502 * @base: base address at which to put VRAM 503 * 504 * Function will place try to place VRAM at base address provided 505 * as parameter (which is so far either PCI aperture address or 506 * for IGP TOM base address). 507 * 508 * If there is not enough space to fit the unvisible VRAM in the 32bits 509 * address space then we limit the VRAM size to the aperture. 510 * 511 * If we are using AGP and if the AGP aperture doesn't allow us to have 512 * room for all the VRAM than we restrict the VRAM to the PCI aperture 513 * size and print a warning. 514 * 515 * This function will never fails, worst case are limiting VRAM. 516 * 517 * Note: GTT start, end, size should be initialized before calling this 518 * function on AGP platform. 519 * 520 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, 521 * this shouldn't be a problem as we are using the PCI aperture as a reference. 522 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but 523 * not IGP. 524 * 525 * Note: we use mc_vram_size as on some board we need to program the mc to 526 * cover the whole aperture even if VRAM size is inferior to aperture size 527 * Novell bug 204882 + along with lots of ubuntu ones 528 * 529 * Note: when limiting vram it's safe to overwritte real_vram_size because 530 * we are not in case where real_vram_size is inferior to mc_vram_size (ie 531 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu 532 * ones) 533 * 534 * Note: IGP TOM addr should be the same as the aperture addr, we don't 535 * explicitly check for that thought. 536 * 537 * FIXME: when reducing VRAM size align new size on power of 2. 538 */ 539 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) 540 { 541 uint64_t limit = (uint64_t)radeon_vram_limit << 20; 542 543 mc->vram_start = base; 544 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) { 545 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 546 mc->real_vram_size = mc->aper_size; 547 mc->mc_vram_size = mc->aper_size; 548 } 549 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 550 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { 551 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 552 mc->real_vram_size = mc->aper_size; 553 mc->mc_vram_size = mc->aper_size; 554 } 555 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 556 if (limit && limit < mc->real_vram_size) 557 mc->real_vram_size = limit; 558 dev_info(rdev->dev, "VRAM: %juM 0x%016jX - 0x%016jX (%juM used)\n", 559 mc->mc_vram_size >> 20, mc->vram_start, 560 mc->vram_end, mc->real_vram_size >> 20); 561 } 562 563 /** 564 * radeon_gtt_location - try to find GTT location 565 * @rdev: radeon device structure holding all necessary informations 566 * @mc: memory controller structure holding memory informations 567 * 568 * Function will place try to place GTT before or after VRAM. 569 * 570 * If GTT size is bigger than space left then we ajust GTT size. 571 * Thus function will never fails. 572 * 573 * FIXME: when reducing GTT size align new size on power of 2. 574 */ 575 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 576 { 577 u64 size_af, size_bf; 578 579 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; 580 size_bf = mc->vram_start & ~mc->gtt_base_align; 581 if (size_bf > size_af) { 582 if (mc->gtt_size > size_bf) { 583 dev_warn(rdev->dev, "limiting GTT\n"); 584 mc->gtt_size = size_bf; 585 } 586 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; 587 } else { 588 if (mc->gtt_size > size_af) { 589 dev_warn(rdev->dev, "limiting GTT\n"); 590 mc->gtt_size = size_af; 591 } 592 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; 593 } 594 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; 595 dev_info(rdev->dev, "GTT: %juM 0x%016jX - 0x%016jX\n", 596 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); 597 } 598 599 /* 600 * GPU helpers function. 601 */ 602 /** 603 * radeon_card_posted - check if the hw has already been initialized 604 * 605 * @rdev: radeon_device pointer 606 * 607 * Check if the asic has been initialized (all asics). 608 * Used at driver startup. 609 * Returns true if initialized or false if not. 610 */ 611 bool radeon_card_posted(struct radeon_device *rdev) 612 { 613 uint32_t reg; 614 615 #ifdef DUMBBELL_WIP 616 /* required for EFI mode on macbook2,1 which uses an r5xx asic */ 617 if (efi_enabled(EFI_BOOT) && 618 (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && 619 (rdev->family < CHIP_R600)) 620 return false; 621 #endif /* DUMBBELL_WIP */ 622 623 if (ASIC_IS_NODCE(rdev)) 624 goto check_memsize; 625 626 /* first check CRTCs */ 627 if (ASIC_IS_DCE4(rdev)) { 628 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | 629 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 630 if (rdev->num_crtc >= 4) { 631 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | 632 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 633 } 634 if (rdev->num_crtc >= 6) { 635 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | 636 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 637 } 638 if (reg & EVERGREEN_CRTC_MASTER_EN) 639 return true; 640 } else if (ASIC_IS_AVIVO(rdev)) { 641 reg = RREG32(AVIVO_D1CRTC_CONTROL) | 642 RREG32(AVIVO_D2CRTC_CONTROL); 643 if (reg & AVIVO_CRTC_EN) { 644 return true; 645 } 646 } else { 647 reg = RREG32(RADEON_CRTC_GEN_CNTL) | 648 RREG32(RADEON_CRTC2_GEN_CNTL); 649 if (reg & RADEON_CRTC_EN) { 650 return true; 651 } 652 } 653 654 check_memsize: 655 /* then check MEM_SIZE, in case the crtcs are off */ 656 if (rdev->family >= CHIP_R600) 657 reg = RREG32(R600_CONFIG_MEMSIZE); 658 else 659 reg = RREG32(RADEON_CONFIG_MEMSIZE); 660 661 if (reg) 662 return true; 663 664 return false; 665 666 } 667 668 /** 669 * radeon_update_bandwidth_info - update display bandwidth params 670 * 671 * @rdev: radeon_device pointer 672 * 673 * Used when sclk/mclk are switched or display modes are set. 674 * params are used to calculate display watermarks (all asics) 675 */ 676 void radeon_update_bandwidth_info(struct radeon_device *rdev) 677 { 678 fixed20_12 a; 679 u32 sclk = rdev->pm.current_sclk; 680 u32 mclk = rdev->pm.current_mclk; 681 682 /* sclk/mclk in Mhz */ 683 a.full = dfixed_const(100); 684 rdev->pm.sclk.full = dfixed_const(sclk); 685 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); 686 rdev->pm.mclk.full = dfixed_const(mclk); 687 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); 688 689 if (rdev->flags & RADEON_IS_IGP) { 690 a.full = dfixed_const(16); 691 /* core_bandwidth = sclk(Mhz) * 16 */ 692 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); 693 } 694 } 695 696 /** 697 * radeon_boot_test_post_card - check and possibly initialize the hw 698 * 699 * @rdev: radeon_device pointer 700 * 701 * Check if the asic is initialized and if not, attempt to initialize 702 * it (all asics). 703 * Returns true if initialized or false if not. 704 */ 705 bool radeon_boot_test_post_card(struct radeon_device *rdev) 706 { 707 if (radeon_card_posted(rdev)) 708 return true; 709 710 if (rdev->bios) { 711 DRM_INFO("GPU not posted. posting now...\n"); 712 if (rdev->is_atom_bios) 713 atom_asic_init(rdev->mode_info.atom_context); 714 else 715 radeon_combios_asic_init(rdev->ddev); 716 return true; 717 } else { 718 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 719 return false; 720 } 721 } 722 723 /** 724 * radeon_dummy_page_init - init dummy page used by the driver 725 * 726 * @rdev: radeon_device pointer 727 * 728 * Allocate the dummy page used by the driver (all asics). 729 * This dummy page is used by the driver as a filler for gart entries 730 * when pages are taken out of the GART 731 * Returns 0 on sucess, -ENOMEM on failure. 732 */ 733 int radeon_dummy_page_init(struct radeon_device *rdev) 734 { 735 if (rdev->dummy_page.dmah) 736 return 0; 737 rdev->dummy_page.dmah = drm_pci_alloc(rdev->ddev, 738 PAGE_SIZE, PAGE_SIZE); 739 if (rdev->dummy_page.dmah == NULL) 740 return -ENOMEM; 741 rdev->dummy_page.addr = 742 (dma_addr_t)(uintptr_t)rdev->dummy_page.dmah->vaddr; 743 return 0; 744 } 745 746 /** 747 * radeon_dummy_page_fini - free dummy page used by the driver 748 * 749 * @rdev: radeon_device pointer 750 * 751 * Frees the dummy page used by the driver (all asics). 752 */ 753 void radeon_dummy_page_fini(struct radeon_device *rdev) 754 { 755 if (rdev->dummy_page.dmah == NULL) 756 return; 757 drm_pci_free(rdev->ddev, rdev->dummy_page.dmah); 758 rdev->dummy_page.dmah = NULL; 759 rdev->dummy_page.addr = 0; 760 } 761 762 763 /* ATOM accessor methods */ 764 /* 765 * ATOM is an interpreted byte code stored in tables in the vbios. The 766 * driver registers callbacks to access registers and the interpreter 767 * in the driver parses the tables and executes then to program specific 768 * actions (set display modes, asic init, etc.). See radeon_atombios.c, 769 * atombios.h, and atom.c 770 */ 771 772 /** 773 * cail_pll_read - read PLL register 774 * 775 * @info: atom card_info pointer 776 * @reg: PLL register offset 777 * 778 * Provides a PLL register accessor for the atom interpreter (r4xx+). 779 * Returns the value of the PLL register. 780 */ 781 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) 782 { 783 struct radeon_device *rdev = info->dev->dev_private; 784 uint32_t r; 785 786 r = rdev->pll_rreg(rdev, reg); 787 return r; 788 } 789 790 /** 791 * cail_pll_write - write PLL register 792 * 793 * @info: atom card_info pointer 794 * @reg: PLL register offset 795 * @val: value to write to the pll register 796 * 797 * Provides a PLL register accessor for the atom interpreter (r4xx+). 798 */ 799 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) 800 { 801 struct radeon_device *rdev = info->dev->dev_private; 802 803 rdev->pll_wreg(rdev, reg, val); 804 } 805 806 /** 807 * cail_mc_read - read MC (Memory Controller) register 808 * 809 * @info: atom card_info pointer 810 * @reg: MC register offset 811 * 812 * Provides an MC register accessor for the atom interpreter (r4xx+). 813 * Returns the value of the MC register. 814 */ 815 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) 816 { 817 struct radeon_device *rdev = info->dev->dev_private; 818 uint32_t r; 819 820 r = rdev->mc_rreg(rdev, reg); 821 return r; 822 } 823 824 /** 825 * cail_mc_write - write MC (Memory Controller) register 826 * 827 * @info: atom card_info pointer 828 * @reg: MC register offset 829 * @val: value to write to the pll register 830 * 831 * Provides a MC register accessor for the atom interpreter (r4xx+). 832 */ 833 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) 834 { 835 struct radeon_device *rdev = info->dev->dev_private; 836 837 rdev->mc_wreg(rdev, reg, val); 838 } 839 840 /** 841 * cail_reg_write - write MMIO register 842 * 843 * @info: atom card_info pointer 844 * @reg: MMIO register offset 845 * @val: value to write to the pll register 846 * 847 * Provides a MMIO register accessor for the atom interpreter (r4xx+). 848 */ 849 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) 850 { 851 struct radeon_device *rdev = info->dev->dev_private; 852 853 WREG32(reg*4, val); 854 } 855 856 /** 857 * cail_reg_read - read MMIO register 858 * 859 * @info: atom card_info pointer 860 * @reg: MMIO register offset 861 * 862 * Provides an MMIO register accessor for the atom interpreter (r4xx+). 863 * Returns the value of the MMIO register. 864 */ 865 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) 866 { 867 struct radeon_device *rdev = info->dev->dev_private; 868 uint32_t r; 869 870 r = RREG32(reg*4); 871 return r; 872 } 873 874 /** 875 * cail_ioreg_write - write IO register 876 * 877 * @info: atom card_info pointer 878 * @reg: IO register offset 879 * @val: value to write to the pll register 880 * 881 * Provides a IO register accessor for the atom interpreter (r4xx+). 882 */ 883 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) 884 { 885 struct radeon_device *rdev = info->dev->dev_private; 886 887 WREG32_IO(reg*4, val); 888 } 889 890 /** 891 * cail_ioreg_read - read IO register 892 * 893 * @info: atom card_info pointer 894 * @reg: IO register offset 895 * 896 * Provides an IO register accessor for the atom interpreter (r4xx+). 897 * Returns the value of the IO register. 898 */ 899 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) 900 { 901 struct radeon_device *rdev = info->dev->dev_private; 902 uint32_t r; 903 904 r = RREG32_IO(reg*4); 905 return r; 906 } 907 908 /** 909 * radeon_atombios_init - init the driver info and callbacks for atombios 910 * 911 * @rdev: radeon_device pointer 912 * 913 * Initializes the driver info and register access callbacks for the 914 * ATOM interpreter (r4xx+). 915 * Returns 0 on sucess, -ENOMEM on failure. 916 * Called at driver startup. 917 */ 918 int radeon_atombios_init(struct radeon_device *rdev) 919 { 920 struct card_info *atom_card_info = 921 kzalloc(sizeof(struct card_info), GFP_KERNEL); 922 923 if (!atom_card_info) 924 return -ENOMEM; 925 926 rdev->mode_info.atom_card_info = atom_card_info; 927 atom_card_info->dev = rdev->ddev; 928 atom_card_info->reg_read = cail_reg_read; 929 atom_card_info->reg_write = cail_reg_write; 930 /* needed for iio ops */ 931 if (rdev->rio_mem) { 932 atom_card_info->ioreg_read = cail_ioreg_read; 933 atom_card_info->ioreg_write = cail_ioreg_write; 934 } else { 935 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); 936 atom_card_info->ioreg_read = cail_reg_read; 937 atom_card_info->ioreg_write = cail_reg_write; 938 } 939 atom_card_info->mc_read = cail_mc_read; 940 atom_card_info->mc_write = cail_mc_write; 941 atom_card_info->pll_read = cail_pll_read; 942 atom_card_info->pll_write = cail_pll_write; 943 944 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); 945 if (!rdev->mode_info.atom_context) { 946 radeon_atombios_fini(rdev); 947 return -ENOMEM; 948 } 949 950 lockinit(&rdev->mode_info.atom_context->mutex, "rmiacmtx", 0, LK_CANRECURSE); 951 lockinit(&rdev->mode_info.atom_context->scratch_mutex, "rmiacsmtx", 0, LK_CANRECURSE); 952 radeon_atom_initialize_bios_scratch_regs(rdev->ddev); 953 atom_allocate_fb_scratch(rdev->mode_info.atom_context); 954 return 0; 955 } 956 957 /** 958 * radeon_atombios_fini - free the driver info and callbacks for atombios 959 * 960 * @rdev: radeon_device pointer 961 * 962 * Frees the driver info and register access callbacks for the ATOM 963 * interpreter (r4xx+). 964 * Called at driver shutdown. 965 */ 966 void radeon_atombios_fini(struct radeon_device *rdev) 967 { 968 if (rdev->mode_info.atom_context) { 969 kfree(rdev->mode_info.atom_context->scratch); 970 } 971 kfree(rdev->mode_info.atom_context); 972 rdev->mode_info.atom_context = NULL; 973 kfree(rdev->mode_info.atom_card_info); 974 rdev->mode_info.atom_card_info = NULL; 975 } 976 977 /* COMBIOS */ 978 /* 979 * COMBIOS is the bios format prior to ATOM. It provides 980 * command tables similar to ATOM, but doesn't have a unified 981 * parser. See radeon_combios.c 982 */ 983 984 /** 985 * radeon_combios_init - init the driver info for combios 986 * 987 * @rdev: radeon_device pointer 988 * 989 * Initializes the driver info for combios (r1xx-r3xx). 990 * Returns 0 on sucess. 991 * Called at driver startup. 992 */ 993 int radeon_combios_init(struct radeon_device *rdev) 994 { 995 radeon_combios_initialize_bios_scratch_regs(rdev->ddev); 996 return 0; 997 } 998 999 /** 1000 * radeon_combios_fini - free the driver info for combios 1001 * 1002 * @rdev: radeon_device pointer 1003 * 1004 * Frees the driver info for combios (r1xx-r3xx). 1005 * Called at driver shutdown. 1006 */ 1007 void radeon_combios_fini(struct radeon_device *rdev) 1008 { 1009 } 1010 1011 #ifdef DUMBBELL_WIP 1012 /* if we get transitioned to only one device, take VGA back */ 1013 /** 1014 * radeon_vga_set_decode - enable/disable vga decode 1015 * 1016 * @cookie: radeon_device pointer 1017 * @state: enable/disable vga decode 1018 * 1019 * Enable/disable vga decode (all asics). 1020 * Returns VGA resource flags. 1021 */ 1022 static unsigned int radeon_vga_set_decode(void *cookie, bool state) 1023 { 1024 struct radeon_device *rdev = cookie; 1025 radeon_vga_set_state(rdev, state); 1026 if (state) 1027 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | 1028 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 1029 else 1030 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 1031 } 1032 #endif /* DUMBBELL_WIP */ 1033 1034 /** 1035 * radeon_check_pot_argument - check that argument is a power of two 1036 * 1037 * @arg: value to check 1038 * 1039 * Validates that a certain argument is a power of two (all asics). 1040 * Returns true if argument is valid. 1041 */ 1042 static bool radeon_check_pot_argument(int arg) 1043 { 1044 return (arg & (arg - 1)) == 0; 1045 } 1046 1047 /** 1048 * radeon_check_arguments - validate module params 1049 * 1050 * @rdev: radeon_device pointer 1051 * 1052 * Validates certain module parameters and updates 1053 * the associated values used by the driver (all asics). 1054 */ 1055 static void radeon_check_arguments(struct radeon_device *rdev) 1056 { 1057 /* vramlimit must be a power of two */ 1058 if (!radeon_check_pot_argument(radeon_vram_limit)) { 1059 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", 1060 radeon_vram_limit); 1061 radeon_vram_limit = 0; 1062 } 1063 1064 if (radeon_gart_size == -1) { 1065 /* default to a larger gart size on newer asics */ 1066 if (rdev->family >= CHIP_RV770) 1067 radeon_gart_size = 1024; 1068 else 1069 radeon_gart_size = 512; 1070 } 1071 /* gtt size must be power of two and greater or equal to 32M */ 1072 if (radeon_gart_size < 32) { 1073 dev_warn(rdev->dev, "gart size (%d) too small\n", 1074 radeon_gart_size); 1075 if (rdev->family >= CHIP_RV770) 1076 radeon_gart_size = 1024; 1077 else 1078 radeon_gart_size = 512; 1079 } else if (!radeon_check_pot_argument(radeon_gart_size)) { 1080 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", 1081 radeon_gart_size); 1082 if (rdev->family >= CHIP_RV770) 1083 radeon_gart_size = 1024; 1084 else 1085 radeon_gart_size = 512; 1086 } 1087 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20; 1088 1089 /* AGP mode can only be -1, 1, 2, 4, 8 */ 1090 switch (radeon_agpmode) { 1091 case -1: 1092 case 0: 1093 case 1: 1094 case 2: 1095 case 4: 1096 case 8: 1097 break; 1098 default: 1099 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " 1100 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); 1101 radeon_agpmode = 0; 1102 break; 1103 } 1104 1105 if (!radeon_check_pot_argument(radeon_vm_size)) { 1106 dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n", 1107 radeon_vm_size); 1108 radeon_vm_size = 4; 1109 } 1110 1111 if (radeon_vm_size < 1) { 1112 dev_warn(rdev->dev, "VM size (%d) to small, min is 1GB\n", 1113 radeon_vm_size); 1114 radeon_vm_size = 4; 1115 } 1116 1117 /* 1118 * Max GPUVM size for Cayman, SI and CI are 40 bits. 1119 */ 1120 if (radeon_vm_size > 1024) { 1121 dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n", 1122 radeon_vm_size); 1123 radeon_vm_size = 4; 1124 } 1125 1126 /* defines number of bits in page table versus page directory, 1127 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the 1128 * page table and the remaining bits are in the page directory */ 1129 if (radeon_vm_block_size == -1) { 1130 1131 /* Total bits covered by PD + PTs */ 1132 unsigned bits = ilog2(radeon_vm_size) + 18; 1133 1134 /* Make sure the PD is 4K in size up to 8GB address space. 1135 Above that split equal between PD and PTs */ 1136 if (radeon_vm_size <= 8) 1137 radeon_vm_block_size = bits - 9; 1138 else 1139 radeon_vm_block_size = (bits + 3) / 2; 1140 1141 } else if (radeon_vm_block_size < 9) { 1142 dev_warn(rdev->dev, "VM page table size (%d) too small\n", 1143 radeon_vm_block_size); 1144 radeon_vm_block_size = 9; 1145 } 1146 1147 if (radeon_vm_block_size > 24 || 1148 (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) { 1149 dev_warn(rdev->dev, "VM page table size (%d) too large\n", 1150 radeon_vm_block_size); 1151 radeon_vm_block_size = 9; 1152 } 1153 } 1154 1155 /** 1156 * radeon_switcheroo_set_state - set switcheroo state 1157 * 1158 * @pdev: pci dev pointer 1159 * @state: vga switcheroo state 1160 * 1161 * Callback for the switcheroo driver. Suspends or resumes the 1162 * the asics before or after it is powered up using ACPI methods. 1163 */ 1164 #ifdef DUMBBELL_WIP 1165 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) 1166 { 1167 struct drm_device *dev = pci_get_drvdata(pdev); 1168 struct radeon_device *rdev = dev->dev_private; 1169 1170 if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF) 1171 return; 1172 1173 if (state == VGA_SWITCHEROO_ON) { 1174 unsigned d3_delay = dev->pdev->d3_delay; 1175 1176 printk(KERN_INFO "radeon: switched on\n"); 1177 /* don't suspend or resume card normally */ 1178 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1179 1180 if (d3_delay < 20 && (rdev->px_quirk_flags & RADEON_PX_QUIRK_LONG_WAKEUP)) 1181 dev->pdev->d3_delay = 20; 1182 1183 radeon_resume_kms(dev, true, true); 1184 1185 dev->pdev->d3_delay = d3_delay; 1186 1187 dev->switch_power_state = DRM_SWITCH_POWER_ON; 1188 drm_kms_helper_poll_enable(dev); 1189 } else { 1190 printk(KERN_INFO "radeon: switched off\n"); 1191 drm_kms_helper_poll_disable(dev); 1192 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1193 radeon_suspend_kms(dev, true, true); 1194 dev->switch_power_state = DRM_SWITCH_POWER_OFF; 1195 } 1196 } 1197 #endif /* DUMBBELL_WIP */ 1198 1199 /** 1200 * radeon_switcheroo_can_switch - see if switcheroo state can change 1201 * 1202 * @pdev: pci dev pointer 1203 * 1204 * Callback for the switcheroo driver. Check of the switcheroo 1205 * state can be changed. 1206 * Returns true if the state can be changed, false if not. 1207 */ 1208 #ifdef DUMBBELL_WIP 1209 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev) 1210 { 1211 struct drm_device *dev = pci_get_drvdata(pdev); 1212 1213 /* 1214 * FIXME: open_count is protected by drm_global_mutex but that would lead to 1215 * locking inversion with the driver load path. And the access here is 1216 * completely racy anyway. So don't bother with locking for now. 1217 */ 1218 return dev->open_count == 0; 1219 } 1220 1221 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = { 1222 .set_gpu_state = radeon_switcheroo_set_state, 1223 .reprobe = NULL, 1224 .can_switch = radeon_switcheroo_can_switch, 1225 }; 1226 #endif /* DUMBBELL_WIP */ 1227 1228 /** 1229 * radeon_device_init - initialize the driver 1230 * 1231 * @rdev: radeon_device pointer 1232 * @pdev: drm dev pointer 1233 * @pdev: pci dev pointer 1234 * @flags: driver flags 1235 * 1236 * Initializes the driver info and hw (all asics). 1237 * Returns 0 for success or an error on failure. 1238 * Called at driver startup. 1239 */ 1240 int radeon_device_init(struct radeon_device *rdev, 1241 struct drm_device *ddev, 1242 struct pci_dev *pdev, 1243 uint32_t flags) 1244 { 1245 int r, i; 1246 int dma_bits; 1247 #ifdef PM_TODO 1248 bool runtime = false; 1249 #endif 1250 1251 rdev->shutdown = false; 1252 rdev->dev = pdev->dev; 1253 rdev->ddev = ddev; 1254 rdev->pdev = pdev; 1255 rdev->flags = flags; 1256 rdev->family = flags & RADEON_FAMILY_MASK; 1257 rdev->is_atom_bios = false; 1258 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; 1259 rdev->mc.gtt_size = 512 * 1024 * 1024; 1260 rdev->accel_working = false; 1261 rdev->fictitious_range_registered = false; 1262 /* set up ring ids */ 1263 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1264 rdev->ring[i].idx = i; 1265 } 1266 1267 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n", 1268 radeon_family_name[rdev->family], pdev->vendor, pdev->device, 1269 pdev->subsystem_vendor, pdev->subsystem_device); 1270 1271 /* mutex initialization are all done here so we 1272 * can recall function without having locking issues */ 1273 lockinit(&rdev->ring_lock, "drm__radeon_device__ring_lock", 0, 1274 LK_CANRECURSE); 1275 lockinit(&rdev->dc_hw_i2c_mutex, 1276 "drm__radeon_device__dc_hw_i2c_mutex", 0, LK_CANRECURSE); 1277 atomic_set(&rdev->ih.lock, 0); 1278 spin_init(&rdev->gem.mutex, "radeon_gemmtx"); 1279 lockinit(&rdev->pm.mutex, "drm__radeon_device__pm__mutex", 0, 1280 LK_CANRECURSE); 1281 spin_init(&rdev->gpu_clock_mutex, "radeon_clockmtx"); 1282 spin_init(&rdev->srbm_mutex, "radeon_srbm_mutex"); 1283 lockinit(&rdev->pm.mclk_lock, "drm__radeon_device__pm__mclk_lock", 0, 1284 LK_CANRECURSE); 1285 lockinit(&rdev->exclusive_lock, "drm__radeon_device__exclusive_lock", 1286 0, LK_CANRECURSE); 1287 init_waitqueue_head(&rdev->irq.vblank_queue); 1288 r = radeon_gem_init(rdev); 1289 if (r) 1290 return r; 1291 1292 radeon_check_arguments(rdev); 1293 /* Adjust VM size here. 1294 * Max GPUVM size for cayman+ is 40 bits. 1295 */ 1296 rdev->vm_manager.max_pfn = radeon_vm_size << 18; 1297 1298 /* Set asic functions */ 1299 r = radeon_asic_init(rdev); 1300 if (r) 1301 return r; 1302 1303 /* all of the newer IGP chips have an internal gart 1304 * However some rs4xx report as AGP, so remove that here. 1305 */ 1306 if ((rdev->family >= CHIP_RS400) && 1307 (rdev->flags & RADEON_IS_IGP)) { 1308 rdev->flags &= ~RADEON_IS_AGP; 1309 } 1310 1311 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { 1312 radeon_agp_disable(rdev); 1313 } 1314 1315 /* Set the internal MC address mask 1316 * This is the max address of the GPU's 1317 * internal address space. 1318 */ 1319 if (rdev->family >= CHIP_CAYMAN) 1320 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1321 else if (rdev->family >= CHIP_CEDAR) 1322 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */ 1323 else 1324 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */ 1325 1326 /* set DMA mask + need_dma32 flags. 1327 * PCIE - can handle 40-bits. 1328 * IGP - can handle 40-bits 1329 * AGP - generally dma32 is safest 1330 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 1331 */ 1332 rdev->need_dma32 = false; 1333 if (rdev->flags & RADEON_IS_AGP) 1334 rdev->need_dma32 = true; 1335 if ((rdev->flags & RADEON_IS_PCI) && 1336 (rdev->family <= CHIP_RS740)) 1337 rdev->need_dma32 = true; 1338 1339 dma_bits = rdev->need_dma32 ? 32 : 40; 1340 #ifdef DUMBBELL_WIP 1341 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 1342 if (r) { 1343 rdev->need_dma32 = true; 1344 dma_bits = 32; 1345 printk(KERN_WARNING "radeon: No suitable DMA available.\n"); 1346 } 1347 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 1348 if (r) { 1349 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32)); 1350 printk(KERN_WARNING "radeon: No coherent DMA available.\n"); 1351 } 1352 #endif /* DUMBBELL_WIP */ 1353 1354 /* Registers mapping */ 1355 /* TODO: block userspace mapping of io register */ 1356 spin_init(&rdev->mmio_idx_lock, "radeon_mpio"); 1357 spin_init(&rdev->smc_idx_lock, "radeon_smc"); 1358 spin_init(&rdev->pll_idx_lock, "radeon_pll"); 1359 spin_init(&rdev->mc_idx_lock, "radeon_mc"); 1360 spin_init(&rdev->pcie_idx_lock, "radeon_pcie"); 1361 spin_init(&rdev->pciep_idx_lock, "radeon_pciep"); 1362 spin_init(&rdev->pif_idx_lock, "radeon_pif"); 1363 spin_init(&rdev->cg_idx_lock, "radeon_cg"); 1364 spin_init(&rdev->uvd_idx_lock, "radeon_uvd"); 1365 spin_init(&rdev->rcu_idx_lock, "radeon_rcu"); 1366 spin_init(&rdev->didt_idx_lock, "radeon_didt"); 1367 spin_init(&rdev->end_idx_lock, "radeon_end"); 1368 if (rdev->family >= CHIP_BONAIRE) { 1369 rdev->rmmio_rid = PCIR_BAR(5); 1370 } else { 1371 rdev->rmmio_rid = PCIR_BAR(2); 1372 } 1373 rdev->rmmio = bus_alloc_resource_any(rdev->dev, SYS_RES_MEMORY, 1374 &rdev->rmmio_rid, RF_ACTIVE | RF_SHAREABLE); 1375 if (rdev->rmmio == NULL) { 1376 return -ENOMEM; 1377 } 1378 rdev->rmmio_base = rman_get_start(rdev->rmmio); 1379 rdev->rmmio_size = rman_get_size(rdev->rmmio); 1380 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); 1381 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); 1382 1383 /* doorbell bar mapping */ 1384 if (rdev->family >= CHIP_BONAIRE) 1385 radeon_doorbell_init(rdev); 1386 1387 /* io port mapping */ 1388 for (i = 0; i < DRM_MAX_PCI_RESOURCE; i++) { 1389 uint32_t data; 1390 1391 data = pci_read_config(rdev->dev, PCIR_BAR(i), 4); 1392 if (PCI_BAR_IO(data)) { 1393 rdev->rio_rid = PCIR_BAR(i); 1394 rdev->rio_mem = bus_alloc_resource_any(rdev->dev, 1395 SYS_RES_IOPORT, &rdev->rio_rid, 1396 RF_ACTIVE | RF_SHAREABLE); 1397 break; 1398 } 1399 } 1400 if (rdev->rio_mem == NULL) 1401 DRM_ERROR("Unable to find PCI I/O BAR\n"); 1402 1403 rdev->tq = taskqueue_create("radeonkms", M_WAITOK, 1404 taskqueue_thread_enqueue, &rdev->tq); 1405 taskqueue_start_threads(&rdev->tq, 1, 0, -1, "radeon taskq"); 1406 1407 if (rdev->flags & RADEON_IS_PX) 1408 radeon_device_handle_px_quirks(rdev); 1409 1410 #ifdef DUMBBELL_WIP 1411 /* if we have > 1 VGA cards, then disable the radeon VGA resources */ 1412 /* this will fail for cards that aren't VGA class devices, just 1413 * ignore it */ 1414 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); 1415 1416 #ifdef PM_TODO 1417 if (rdev->flags & RADEON_IS_PX) 1418 runtime = true; 1419 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime); 1420 if (runtime) 1421 vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain); 1422 #endif 1423 #endif /* DUMBBELL_WIP */ 1424 1425 r = radeon_init(rdev); 1426 if (r) 1427 goto failed; 1428 1429 r = radeon_gem_debugfs_init(rdev); 1430 if (r) { 1431 DRM_ERROR("registering gem debugfs failed (%d).\n", r); 1432 } 1433 1434 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { 1435 /* Acceleration not working on AGP card try again 1436 * with fallback to PCI or PCIE GART 1437 */ 1438 radeon_asic_reset(rdev); 1439 radeon_fini(rdev); 1440 radeon_agp_disable(rdev); 1441 r = radeon_init(rdev); 1442 if (r) 1443 goto failed; 1444 } 1445 1446 r = radeon_ib_ring_tests(rdev); 1447 if (r) 1448 DRM_ERROR("ib ring test failed (%d).\n", r); 1449 1450 DRM_INFO("%s: Taking over the fictitious range 0x%jx-0x%jx\n", 1451 __func__, (uintmax_t)rdev->mc.aper_base, 1452 (uintmax_t)rdev->mc.aper_base + rdev->mc.visible_vram_size); 1453 r = vm_phys_fictitious_reg_range( 1454 rdev->mc.aper_base, 1455 rdev->mc.aper_base + rdev->mc.visible_vram_size, 1456 VM_MEMATTR_WRITE_COMBINING); 1457 if (r != 0) { 1458 DRM_ERROR("Failed to register fictitious range " 1459 "0x%jx-0x%jx (%d).\n", (uintmax_t)rdev->mc.aper_base, 1460 (uintmax_t)rdev->mc.aper_base + rdev->mc.visible_vram_size, r); 1461 return (-r); 1462 } 1463 rdev->fictitious_range_registered = true; 1464 1465 if ((radeon_testing & 1)) { 1466 if (rdev->accel_working) 1467 radeon_test_moves(rdev); 1468 else 1469 DRM_INFO("radeon: acceleration disabled, skipping move tests\n"); 1470 } 1471 if ((radeon_testing & 2)) { 1472 if (rdev->accel_working) 1473 radeon_test_syncing(rdev); 1474 else 1475 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n"); 1476 } 1477 if (radeon_benchmarking) { 1478 if (rdev->accel_working) 1479 radeon_benchmark(rdev, radeon_benchmarking); 1480 else 1481 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n"); 1482 } 1483 return 0; 1484 1485 failed: 1486 #ifdef DRM_BDSM 1487 if (runtime) 1488 vga_switcheroo_fini_domain_pm_ops(rdev->dev); 1489 #endif 1490 return r; 1491 } 1492 1493 #ifdef DUMBBELL_WIP 1494 static void radeon_debugfs_remove_files(struct radeon_device *rdev); 1495 #endif /* DUMBBELL_WIP */ 1496 1497 /** 1498 * radeon_device_fini - tear down the driver 1499 * 1500 * @rdev: radeon_device pointer 1501 * 1502 * Tear down the driver info (all asics). 1503 * Called at driver shutdown. 1504 */ 1505 void radeon_device_fini(struct radeon_device *rdev) 1506 { 1507 DRM_INFO("radeon: finishing device.\n"); 1508 rdev->shutdown = true; 1509 /* evict vram memory */ 1510 radeon_bo_evict_vram(rdev); 1511 1512 if (rdev->fictitious_range_registered) { 1513 vm_phys_fictitious_unreg_range( 1514 rdev->mc.aper_base, 1515 rdev->mc.aper_base + rdev->mc.visible_vram_size); 1516 } 1517 1518 radeon_fini(rdev); 1519 #ifdef DUMBBELL_WIP 1520 vga_switcheroo_unregister_client(rdev->pdev); 1521 if (rdev->flags & RADEON_IS_PX) 1522 vga_switcheroo_fini_domain_pm_ops(rdev->dev); 1523 vga_client_register(rdev->pdev, NULL, NULL, NULL); 1524 #endif /* DUMBBELL_WIP */ 1525 1526 if (rdev->tq != NULL) { 1527 taskqueue_free(rdev->tq); 1528 rdev->tq = NULL; 1529 } 1530 1531 if (rdev->rio_mem) 1532 bus_release_resource(rdev->dev, SYS_RES_IOPORT, rdev->rio_rid, 1533 rdev->rio_mem); 1534 rdev->rio_mem = NULL; 1535 bus_release_resource(rdev->dev, SYS_RES_MEMORY, rdev->rmmio_rid, 1536 rdev->rmmio); 1537 rdev->rmmio = NULL; 1538 if (rdev->family >= CHIP_BONAIRE) 1539 radeon_doorbell_fini(rdev); 1540 #ifdef DUMBBELL_WIP 1541 radeon_debugfs_remove_files(rdev); 1542 #endif /* DUMBBELL_WIP */ 1543 } 1544 1545 1546 /* 1547 * Suspend & resume. 1548 */ 1549 /** 1550 * radeon_suspend_kms - initiate device suspend 1551 * 1552 * @pdev: drm dev pointer 1553 * @state: suspend state 1554 * 1555 * Puts the hw in the suspend state (all asics). 1556 * Returns 0 for success or an error on failure. 1557 * Called at driver suspend. 1558 */ 1559 int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon) 1560 { 1561 struct radeon_device *rdev; 1562 struct drm_crtc *crtc; 1563 struct drm_connector *connector; 1564 int i, r; 1565 1566 if (dev == NULL || dev->dev_private == NULL) { 1567 return -ENODEV; 1568 } 1569 1570 rdev = dev->dev_private; 1571 1572 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1573 return 0; 1574 1575 drm_kms_helper_poll_disable(dev); 1576 1577 /* turn off display hw */ 1578 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1579 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 1580 } 1581 1582 /* unpin the front buffers */ 1583 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1584 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->primary->fb); 1585 struct radeon_bo *robj; 1586 1587 if (rfb == NULL || rfb->obj == NULL) { 1588 continue; 1589 } 1590 robj = gem_to_radeon_bo(rfb->obj); 1591 /* don't unpin kernel fb objects */ 1592 if (!radeon_fbdev_robj_is_fb(rdev, robj)) { 1593 r = radeon_bo_reserve(robj, false); 1594 if (r == 0) { 1595 radeon_bo_unpin(robj); 1596 radeon_bo_unreserve(robj); 1597 } 1598 } 1599 } 1600 /* evict vram memory */ 1601 radeon_bo_evict_vram(rdev); 1602 1603 /* wait for gpu to finish processing current batch */ 1604 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1605 r = radeon_fence_wait_empty(rdev, i); 1606 if (r) { 1607 /* delay GPU reset to resume */ 1608 radeon_fence_driver_force_completion(rdev, i); 1609 } 1610 } 1611 1612 radeon_save_bios_scratch_regs(rdev); 1613 1614 radeon_suspend(rdev); 1615 radeon_hpd_fini(rdev); 1616 /* evict remaining vram memory */ 1617 radeon_bo_evict_vram(rdev); 1618 1619 radeon_agp_suspend(rdev); 1620 1621 pci_save_state(device_get_parent(rdev->dev)); 1622 #ifdef DUMBBELL_WIP 1623 if (suspend) { 1624 /* Shut down the device */ 1625 pci_disable_device(dev->pdev); 1626 #endif /* DUMBBELL_WIP */ 1627 pci_set_powerstate(dev->dev, PCI_POWERSTATE_D3); 1628 #ifdef DUMBBELL_WIP 1629 } 1630 #endif 1631 if (fbcon) { 1632 #ifdef DUMBBELL_WIP 1633 console_lock(); 1634 #endif /* DUMBBELL_WIP */ 1635 radeon_fbdev_set_suspend(rdev, 1); 1636 #ifdef DUMBBELL_WIP 1637 console_unlock(); 1638 #endif /* DUMBBELL_WIP */ 1639 } 1640 return 0; 1641 } 1642 1643 /** 1644 * radeon_resume_kms - initiate device resume 1645 * 1646 * @pdev: drm dev pointer 1647 * 1648 * Bring the hw back to operating state (all asics). 1649 * Returns 0 for success or an error on failure. 1650 * Called at driver resume. 1651 */ 1652 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon) 1653 { 1654 struct drm_connector *connector; 1655 struct radeon_device *rdev = dev->dev_private; 1656 int r; 1657 1658 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1659 return 0; 1660 1661 #ifdef DUMBBELL_WIP 1662 if (fbcon) { 1663 console_lock(); 1664 } 1665 #endif /* DUMBBELL_WIP */ 1666 if (resume) { 1667 pci_set_powerstate(dev->dev, PCI_POWERSTATE_D0); 1668 pci_restore_state(device_get_parent(rdev->dev)); 1669 #ifdef DUMBBELL_WIP 1670 if (pci_enable_device(dev->pdev)) { 1671 if (fbcon) 1672 console_unlock(); 1673 return -1; 1674 } 1675 #endif /* DUMBBELL_WIP */ 1676 } 1677 /* resume AGP if in use */ 1678 radeon_agp_resume(rdev); 1679 radeon_resume(rdev); 1680 1681 r = radeon_ib_ring_tests(rdev); 1682 if (r) 1683 DRM_ERROR("ib ring test failed (%d).\n", r); 1684 1685 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 1686 /* do dpm late init */ 1687 r = radeon_pm_late_init(rdev); 1688 if (r) { 1689 rdev->pm.dpm_enabled = false; 1690 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1691 } 1692 } else { 1693 /* resume old pm late */ 1694 radeon_pm_resume(rdev); 1695 } 1696 1697 radeon_restore_bios_scratch_regs(rdev); 1698 1699 /* init dig PHYs, disp eng pll */ 1700 if (rdev->is_atom_bios) { 1701 radeon_atom_encoder_init(rdev); 1702 radeon_atom_disp_eng_pll_init(rdev); 1703 /* turn on the BL */ 1704 if (rdev->mode_info.bl_encoder) { 1705 u8 bl_level = radeon_get_backlight_level(rdev, 1706 rdev->mode_info.bl_encoder); 1707 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, 1708 bl_level); 1709 } 1710 } 1711 /* reset hpd state */ 1712 radeon_hpd_init(rdev); 1713 /* blat the mode back in */ 1714 if (fbcon) { 1715 drm_helper_resume_force_mode(dev); 1716 /* turn on display hw */ 1717 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1718 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 1719 } 1720 } 1721 1722 drm_kms_helper_poll_enable(dev); 1723 1724 /* set the power state here in case we are a PX system or headless */ 1725 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 1726 radeon_pm_compute_clocks(rdev); 1727 1728 if (fbcon) { 1729 radeon_fbdev_set_suspend(rdev, 0); 1730 #ifdef DUMBBELL_WIP 1731 console_unlock(); 1732 #endif /* DUMBBELL_WIP */ 1733 } 1734 1735 return 0; 1736 } 1737 1738 /** 1739 * radeon_gpu_reset - reset the asic 1740 * 1741 * @rdev: radeon device pointer 1742 * 1743 * Attempt the reset the GPU if it has hung (all asics). 1744 * Returns 0 for success or an error on failure. 1745 */ 1746 int radeon_gpu_reset(struct radeon_device *rdev) 1747 { 1748 unsigned ring_sizes[RADEON_NUM_RINGS]; 1749 uint32_t *ring_data[RADEON_NUM_RINGS]; 1750 1751 bool saved = false; 1752 1753 int i, r; 1754 int resched; 1755 1756 lockmgr(&rdev->exclusive_lock, LK_EXCLUSIVE); 1757 1758 if (!rdev->needs_reset) { 1759 lockmgr(&rdev->exclusive_lock, LK_RELEASE); 1760 return 0; 1761 } 1762 1763 radeon_save_bios_scratch_regs(rdev); 1764 /* block TTM */ 1765 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); 1766 radeon_suspend(rdev); 1767 radeon_hpd_fini(rdev); 1768 1769 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1770 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i], 1771 &ring_data[i]); 1772 if (ring_sizes[i]) { 1773 saved = true; 1774 dev_info(rdev->dev, "Saved %d dwords of commands " 1775 "on ring %d.\n", ring_sizes[i], i); 1776 } 1777 } 1778 1779 r = radeon_asic_reset(rdev); 1780 if (!r) { 1781 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n"); 1782 radeon_resume(rdev); 1783 } 1784 1785 radeon_restore_bios_scratch_regs(rdev); 1786 1787 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1788 if (!r && ring_data[i]) { 1789 radeon_ring_restore(rdev, &rdev->ring[i], 1790 ring_sizes[i], ring_data[i]); 1791 } else { 1792 radeon_fence_driver_force_completion(rdev, i); 1793 kfree(ring_data[i]); 1794 } 1795 } 1796 1797 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 1798 /* do dpm late init */ 1799 r = radeon_pm_late_init(rdev); 1800 if (r) { 1801 rdev->pm.dpm_enabled = false; 1802 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1803 } 1804 } else { 1805 /* resume old pm late */ 1806 radeon_pm_resume(rdev); 1807 } 1808 1809 /* init dig PHYs, disp eng pll */ 1810 if (rdev->is_atom_bios) { 1811 radeon_atom_encoder_init(rdev); 1812 radeon_atom_disp_eng_pll_init(rdev); 1813 /* turn on the BL */ 1814 if (rdev->mode_info.bl_encoder) { 1815 u8 bl_level = radeon_get_backlight_level(rdev, 1816 rdev->mode_info.bl_encoder); 1817 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, 1818 bl_level); 1819 } 1820 } 1821 /* reset hpd state */ 1822 radeon_hpd_init(rdev); 1823 1824 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); 1825 1826 rdev->in_reset = true; 1827 rdev->needs_reset = false; 1828 1829 #if 0 1830 downgrade_write(&rdev->exclusive_lock); 1831 #endif 1832 1833 drm_helper_resume_force_mode(rdev->ddev); 1834 1835 /* set the power state here in case we are a PX system or headless */ 1836 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 1837 radeon_pm_compute_clocks(rdev); 1838 1839 if (!r) { 1840 r = radeon_ib_ring_tests(rdev); 1841 if (r && saved) 1842 r = -EAGAIN; 1843 } else { 1844 /* bad news, how to tell it to userspace ? */ 1845 dev_info(rdev->dev, "GPU reset failed\n"); 1846 } 1847 1848 rdev->needs_reset = r == -EAGAIN; 1849 rdev->in_reset = false; 1850 1851 lockmgr(&rdev->exclusive_lock, LK_RELEASE); 1852 return r; 1853 } 1854 1855 1856 /* 1857 * Debugfs 1858 */ 1859 #ifdef DUMBBELL_WIP 1860 int radeon_debugfs_add_files(struct radeon_device *rdev, 1861 struct drm_info_list *files, 1862 unsigned nfiles) 1863 { 1864 unsigned i; 1865 1866 for (i = 0; i < rdev->debugfs_count; i++) { 1867 if (rdev->debugfs[i].files == files) { 1868 /* Already registered */ 1869 return 0; 1870 } 1871 } 1872 1873 i = rdev->debugfs_count + 1; 1874 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) { 1875 DRM_ERROR("Reached maximum number of debugfs components.\n"); 1876 DRM_ERROR("Report so we increase " 1877 "RADEON_DEBUGFS_MAX_COMPONENTS.\n"); 1878 return -EINVAL; 1879 } 1880 rdev->debugfs[rdev->debugfs_count].files = files; 1881 rdev->debugfs[rdev->debugfs_count].num_files = nfiles; 1882 rdev->debugfs_count = i; 1883 #if defined(CONFIG_DEBUG_FS) 1884 drm_debugfs_create_files(files, nfiles, 1885 rdev->ddev->control->debugfs_root, 1886 rdev->ddev->control); 1887 drm_debugfs_create_files(files, nfiles, 1888 rdev->ddev->primary->debugfs_root, 1889 rdev->ddev->primary); 1890 #endif 1891 return 0; 1892 } 1893 1894 static void radeon_debugfs_remove_files(struct radeon_device *rdev) 1895 { 1896 #if defined(CONFIG_DEBUG_FS) 1897 unsigned i; 1898 1899 for (i = 0; i < rdev->debugfs_count; i++) { 1900 drm_debugfs_remove_files(rdev->debugfs[i].files, 1901 rdev->debugfs[i].num_files, 1902 rdev->ddev->control); 1903 drm_debugfs_remove_files(rdev->debugfs[i].files, 1904 rdev->debugfs[i].num_files, 1905 rdev->ddev->primary); 1906 } 1907 #endif 1908 } 1909 1910 #if defined(CONFIG_DEBUG_FS) 1911 int radeon_debugfs_init(struct drm_minor *minor) 1912 { 1913 return 0; 1914 } 1915 1916 void radeon_debugfs_cleanup(struct drm_minor *minor) 1917 { 1918 } 1919 #endif /* DUMBBELL_WIP */ 1920 #endif 1921