1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * 28 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_device.c 255573 2013-09-14 17:24:41Z dumbbell $ 29 */ 30 #include <drm/drmP.h> 31 #include "drm/drm_legacy.h" /* for drm_dma_handle_t */ 32 #include <drm/drm_crtc_helper.h> 33 #include <uapi_drm/radeon_drm.h> 34 #include <asm/io.h> 35 #include "radeon_reg.h" 36 #include "radeon.h" 37 #include "atom.h" 38 39 static const char radeon_family_name[][16] = { 40 "R100", 41 "RV100", 42 "RS100", 43 "RV200", 44 "RS200", 45 "R200", 46 "RV250", 47 "RS300", 48 "RV280", 49 "R300", 50 "R350", 51 "RV350", 52 "RV380", 53 "R420", 54 "R423", 55 "RV410", 56 "RS400", 57 "RS480", 58 "RS600", 59 "RS690", 60 "RS740", 61 "RV515", 62 "R520", 63 "RV530", 64 "RV560", 65 "RV570", 66 "R580", 67 "R600", 68 "RV610", 69 "RV630", 70 "RV670", 71 "RV620", 72 "RV635", 73 "RS780", 74 "RS880", 75 "RV770", 76 "RV730", 77 "RV710", 78 "RV740", 79 "CEDAR", 80 "REDWOOD", 81 "JUNIPER", 82 "CYPRESS", 83 "HEMLOCK", 84 "PALM", 85 "SUMO", 86 "SUMO2", 87 "BARTS", 88 "TURKS", 89 "CAICOS", 90 "CAYMAN", 91 "ARUBA", 92 "TAHITI", 93 "PITCAIRN", 94 "VERDE", 95 "OLAND", 96 "HAINAN", 97 "BONAIRE", 98 "KAVERI", 99 "KABINI", 100 "HAWAII", 101 "MULLINS", 102 "LAST", 103 }; 104 105 #define RADEON_PX_QUIRK_DISABLE_PX (1 << 0) 106 #define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1) 107 108 struct radeon_px_quirk { 109 u32 chip_vendor; 110 u32 chip_device; 111 u32 subsys_vendor; 112 u32 subsys_device; 113 u32 px_quirk_flags; 114 }; 115 116 static struct radeon_px_quirk radeon_px_quirk_list[] = { 117 /* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m) 118 * https://bugzilla.kernel.org/show_bug.cgi?id=74551 119 */ 120 { PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX }, 121 /* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU 122 * https://bugzilla.kernel.org/show_bug.cgi?id=51381 123 */ 124 { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX }, 125 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU 126 * https://bugzilla.kernel.org/show_bug.cgi?id=51381 127 */ 128 { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX }, 129 /* macbook pro 8.2 */ 130 { PCI_VENDOR_ID_ATI, 0x6741, PCI_VENDOR_ID_APPLE, 0x00e2, RADEON_PX_QUIRK_LONG_WAKEUP }, 131 { 0, 0, 0, 0, 0 }, 132 }; 133 134 bool radeon_is_px(struct drm_device *dev) 135 { 136 struct radeon_device *rdev = dev->dev_private; 137 138 if (rdev->flags & RADEON_IS_PX) 139 return true; 140 return false; 141 } 142 143 static void radeon_device_handle_px_quirks(struct radeon_device *rdev) 144 { 145 struct radeon_px_quirk *p = radeon_px_quirk_list; 146 147 /* Apply PX quirks */ 148 while (p && p->chip_device != 0) { 149 if (rdev->pdev->vendor == p->chip_vendor && 150 rdev->pdev->device == p->chip_device && 151 rdev->pdev->subsystem_vendor == p->subsys_vendor && 152 rdev->pdev->subsystem_device == p->subsys_device) { 153 rdev->px_quirk_flags = p->px_quirk_flags; 154 break; 155 } 156 ++p; 157 } 158 159 if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX) 160 rdev->flags &= ~RADEON_IS_PX; 161 } 162 163 /** 164 * radeon_program_register_sequence - program an array of registers. 165 * 166 * @rdev: radeon_device pointer 167 * @registers: pointer to the register array 168 * @array_size: size of the register array 169 * 170 * Programs an array or registers with and and or masks. 171 * This is a helper for setting golden registers. 172 */ 173 void radeon_program_register_sequence(struct radeon_device *rdev, 174 const u32 *registers, 175 const u32 array_size) 176 { 177 u32 tmp, reg, and_mask, or_mask; 178 int i; 179 180 if (array_size % 3) 181 return; 182 183 for (i = 0; i < array_size; i +=3) { 184 reg = registers[i + 0]; 185 and_mask = registers[i + 1]; 186 or_mask = registers[i + 2]; 187 188 if (and_mask == 0xffffffff) { 189 tmp = or_mask; 190 } else { 191 tmp = RREG32(reg); 192 tmp &= ~and_mask; 193 tmp |= or_mask; 194 } 195 WREG32(reg, tmp); 196 } 197 } 198 199 void radeon_pci_config_reset(struct radeon_device *rdev) 200 { 201 pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA); 202 } 203 204 /** 205 * radeon_surface_init - Clear GPU surface registers. 206 * 207 * @rdev: radeon_device pointer 208 * 209 * Clear GPU surface registers (r1xx-r5xx). 210 */ 211 void radeon_surface_init(struct radeon_device *rdev) 212 { 213 /* FIXME: check this out */ 214 if (rdev->family < CHIP_R600) { 215 int i; 216 217 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 218 if (rdev->surface_regs[i].bo) 219 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); 220 else 221 radeon_clear_surface_reg(rdev, i); 222 } 223 /* enable surfaces */ 224 WREG32(RADEON_SURFACE_CNTL, 0); 225 } 226 } 227 228 /* 229 * GPU scratch registers helpers function. 230 */ 231 /** 232 * radeon_scratch_init - Init scratch register driver information. 233 * 234 * @rdev: radeon_device pointer 235 * 236 * Init CP scratch register driver information (r1xx-r5xx) 237 */ 238 void radeon_scratch_init(struct radeon_device *rdev) 239 { 240 int i; 241 242 /* FIXME: check this out */ 243 if (rdev->family < CHIP_R300) { 244 rdev->scratch.num_reg = 5; 245 } else { 246 rdev->scratch.num_reg = 7; 247 } 248 rdev->scratch.reg_base = RADEON_SCRATCH_REG0; 249 for (i = 0; i < rdev->scratch.num_reg; i++) { 250 rdev->scratch.free[i] = true; 251 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 252 } 253 } 254 255 /** 256 * radeon_scratch_get - Allocate a scratch register 257 * 258 * @rdev: radeon_device pointer 259 * @reg: scratch register mmio offset 260 * 261 * Allocate a CP scratch register for use by the driver (all asics). 262 * Returns 0 on success or -EINVAL on failure. 263 */ 264 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) 265 { 266 int i; 267 268 for (i = 0; i < rdev->scratch.num_reg; i++) { 269 if (rdev->scratch.free[i]) { 270 rdev->scratch.free[i] = false; 271 *reg = rdev->scratch.reg[i]; 272 return 0; 273 } 274 } 275 return -EINVAL; 276 } 277 278 /** 279 * radeon_scratch_free - Free a scratch register 280 * 281 * @rdev: radeon_device pointer 282 * @reg: scratch register mmio offset 283 * 284 * Free a CP scratch register allocated for use by the driver (all asics) 285 */ 286 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) 287 { 288 int i; 289 290 for (i = 0; i < rdev->scratch.num_reg; i++) { 291 if (rdev->scratch.reg[i] == reg) { 292 rdev->scratch.free[i] = true; 293 return; 294 } 295 } 296 } 297 298 /* 299 * GPU doorbell aperture helpers function. 300 */ 301 /** 302 * radeon_doorbell_init - Init doorbell driver information. 303 * 304 * @rdev: radeon_device pointer 305 * 306 * Init doorbell driver information (CIK) 307 * Returns 0 on success, error on failure. 308 */ 309 static int radeon_doorbell_init(struct radeon_device *rdev) 310 { 311 /* doorbell bar mapping */ 312 rdev->doorbell.base = pci_resource_start(rdev->pdev, 2); 313 rdev->doorbell.size = pci_resource_len(rdev->pdev, 2); 314 315 rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS); 316 if (rdev->doorbell.num_doorbells == 0) 317 return -EINVAL; 318 319 rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32)); 320 if (rdev->doorbell.ptr == NULL) { 321 return -ENOMEM; 322 } 323 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base); 324 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size); 325 326 memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used)); 327 328 return 0; 329 } 330 331 /** 332 * radeon_doorbell_fini - Tear down doorbell driver information. 333 * 334 * @rdev: radeon_device pointer 335 * 336 * Tear down doorbell driver information (CIK) 337 */ 338 static void radeon_doorbell_fini(struct radeon_device *rdev) 339 { 340 iounmap(rdev->doorbell.ptr); 341 rdev->doorbell.ptr = NULL; 342 } 343 344 /** 345 * radeon_doorbell_get - Allocate a doorbell entry 346 * 347 * @rdev: radeon_device pointer 348 * @doorbell: doorbell index 349 * 350 * Allocate a doorbell for use by the driver (all asics). 351 * Returns 0 on success or -EINVAL on failure. 352 */ 353 int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell) 354 { 355 unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells); 356 if (offset < rdev->doorbell.num_doorbells) { 357 __set_bit(offset, rdev->doorbell.used); 358 *doorbell = offset; 359 return 0; 360 } else { 361 return -EINVAL; 362 } 363 } 364 365 /** 366 * radeon_doorbell_free - Free a doorbell entry 367 * 368 * @rdev: radeon_device pointer 369 * @doorbell: doorbell index 370 * 371 * Free a doorbell allocated for use by the driver (all asics) 372 */ 373 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell) 374 { 375 if (doorbell < rdev->doorbell.num_doorbells) 376 __clear_bit(doorbell, rdev->doorbell.used); 377 } 378 379 /* 380 * radeon_wb_*() 381 * Writeback is the the method by which the the GPU updates special pages 382 * in memory with the status of certain GPU events (fences, ring pointers, 383 * etc.). 384 */ 385 386 /** 387 * radeon_wb_disable - Disable Writeback 388 * 389 * @rdev: radeon_device pointer 390 * 391 * Disables Writeback (all asics). Used for suspend. 392 */ 393 void radeon_wb_disable(struct radeon_device *rdev) 394 { 395 rdev->wb.enabled = false; 396 } 397 398 /** 399 * radeon_wb_fini - Disable Writeback and free memory 400 * 401 * @rdev: radeon_device pointer 402 * 403 * Disables Writeback and frees the Writeback memory (all asics). 404 * Used at driver shutdown. 405 */ 406 void radeon_wb_fini(struct radeon_device *rdev) 407 { 408 radeon_wb_disable(rdev); 409 if (rdev->wb.wb_obj) { 410 if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) { 411 radeon_bo_kunmap(rdev->wb.wb_obj); 412 radeon_bo_unpin(rdev->wb.wb_obj); 413 radeon_bo_unreserve(rdev->wb.wb_obj); 414 } 415 radeon_bo_unref(&rdev->wb.wb_obj); 416 rdev->wb.wb = NULL; 417 rdev->wb.wb_obj = NULL; 418 } 419 } 420 421 /** 422 * radeon_wb_init- Init Writeback driver info and allocate memory 423 * 424 * @rdev: radeon_device pointer 425 * 426 * Disables Writeback and frees the Writeback memory (all asics). 427 * Used at driver startup. 428 * Returns 0 on success or an -error on failure. 429 */ 430 int radeon_wb_init(struct radeon_device *rdev) 431 { 432 int r; 433 void *wb_ptr; 434 435 if (rdev->wb.wb_obj == NULL) { 436 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, 437 RADEON_GEM_DOMAIN_GTT, 0, NULL, 438 &rdev->wb.wb_obj); 439 if (r) { 440 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); 441 return r; 442 } 443 r = radeon_bo_reserve(rdev->wb.wb_obj, false); 444 if (unlikely(r != 0)) { 445 radeon_wb_fini(rdev); 446 return r; 447 } 448 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, 449 (u64 *)&rdev->wb.gpu_addr); 450 if (r) { 451 radeon_bo_unreserve(rdev->wb.wb_obj); 452 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); 453 radeon_wb_fini(rdev); 454 return r; 455 } 456 wb_ptr = &rdev->wb.wb; 457 r = radeon_bo_kmap(rdev->wb.wb_obj, wb_ptr); 458 radeon_bo_unreserve(rdev->wb.wb_obj); 459 if (r) { 460 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); 461 radeon_wb_fini(rdev); 462 return r; 463 } 464 } 465 466 /* clear wb memory */ 467 wb_ptr = &rdev->wb.wb; 468 memset(*(void **)wb_ptr, 0, RADEON_GPU_PAGE_SIZE); 469 /* disable event_write fences */ 470 rdev->wb.use_event = false; 471 /* disabled via module param */ 472 if (radeon_no_wb == 1) { 473 rdev->wb.enabled = false; 474 } else { 475 if (rdev->flags & RADEON_IS_AGP) { 476 /* often unreliable on AGP */ 477 rdev->wb.enabled = false; 478 } else if (rdev->family < CHIP_R300) { 479 /* often unreliable on pre-r300 */ 480 rdev->wb.enabled = false; 481 } else { 482 rdev->wb.enabled = true; 483 /* event_write fences are only available on r600+ */ 484 if (rdev->family >= CHIP_R600) { 485 rdev->wb.use_event = true; 486 } 487 } 488 } 489 /* always use writeback/events on NI, APUs */ 490 if (rdev->family >= CHIP_PALM) { 491 rdev->wb.enabled = true; 492 rdev->wb.use_event = true; 493 } 494 495 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis"); 496 497 return 0; 498 } 499 500 /** 501 * radeon_vram_location - try to find VRAM location 502 * @rdev: radeon device structure holding all necessary informations 503 * @mc: memory controller structure holding memory informations 504 * @base: base address at which to put VRAM 505 * 506 * Function will place try to place VRAM at base address provided 507 * as parameter (which is so far either PCI aperture address or 508 * for IGP TOM base address). 509 * 510 * If there is not enough space to fit the unvisible VRAM in the 32bits 511 * address space then we limit the VRAM size to the aperture. 512 * 513 * If we are using AGP and if the AGP aperture doesn't allow us to have 514 * room for all the VRAM than we restrict the VRAM to the PCI aperture 515 * size and print a warning. 516 * 517 * This function will never fails, worst case are limiting VRAM. 518 * 519 * Note: GTT start, end, size should be initialized before calling this 520 * function on AGP platform. 521 * 522 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, 523 * this shouldn't be a problem as we are using the PCI aperture as a reference. 524 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but 525 * not IGP. 526 * 527 * Note: we use mc_vram_size as on some board we need to program the mc to 528 * cover the whole aperture even if VRAM size is inferior to aperture size 529 * Novell bug 204882 + along with lots of ubuntu ones 530 * 531 * Note: when limiting vram it's safe to overwritte real_vram_size because 532 * we are not in case where real_vram_size is inferior to mc_vram_size (ie 533 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu 534 * ones) 535 * 536 * Note: IGP TOM addr should be the same as the aperture addr, we don't 537 * explicitly check for that thought. 538 * 539 * FIXME: when reducing VRAM size align new size on power of 2. 540 */ 541 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) 542 { 543 uint64_t limit = (uint64_t)radeon_vram_limit << 20; 544 545 mc->vram_start = base; 546 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) { 547 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 548 mc->real_vram_size = mc->aper_size; 549 mc->mc_vram_size = mc->aper_size; 550 } 551 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 552 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { 553 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 554 mc->real_vram_size = mc->aper_size; 555 mc->mc_vram_size = mc->aper_size; 556 } 557 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 558 if (limit && limit < mc->real_vram_size) 559 mc->real_vram_size = limit; 560 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 561 mc->mc_vram_size >> 20, mc->vram_start, 562 mc->vram_end, mc->real_vram_size >> 20); 563 } 564 565 /** 566 * radeon_gtt_location - try to find GTT location 567 * @rdev: radeon device structure holding all necessary informations 568 * @mc: memory controller structure holding memory informations 569 * 570 * Function will place try to place GTT before or after VRAM. 571 * 572 * If GTT size is bigger than space left then we ajust GTT size. 573 * Thus function will never fails. 574 * 575 * FIXME: when reducing GTT size align new size on power of 2. 576 */ 577 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 578 { 579 u64 size_af, size_bf; 580 581 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; 582 size_bf = mc->vram_start & ~mc->gtt_base_align; 583 if (size_bf > size_af) { 584 if (mc->gtt_size > size_bf) { 585 dev_warn(rdev->dev, "limiting GTT\n"); 586 mc->gtt_size = size_bf; 587 } 588 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; 589 } else { 590 if (mc->gtt_size > size_af) { 591 dev_warn(rdev->dev, "limiting GTT\n"); 592 mc->gtt_size = size_af; 593 } 594 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; 595 } 596 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; 597 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", 598 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); 599 } 600 601 /* 602 * GPU helpers function. 603 */ 604 /** 605 * radeon_card_posted - check if the hw has already been initialized 606 * 607 * @rdev: radeon_device pointer 608 * 609 * Check if the asic has been initialized (all asics). 610 * Used at driver startup. 611 * Returns true if initialized or false if not. 612 */ 613 bool radeon_card_posted(struct radeon_device *rdev) 614 { 615 uint32_t reg; 616 617 #ifdef DUMBBELL_WIP 618 /* required for EFI mode on macbook2,1 which uses an r5xx asic */ 619 if (efi_enabled(EFI_BOOT) && 620 (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && 621 (rdev->family < CHIP_R600)) 622 return false; 623 #endif /* DUMBBELL_WIP */ 624 625 if (ASIC_IS_NODCE(rdev)) 626 goto check_memsize; 627 628 /* first check CRTCs */ 629 if (ASIC_IS_DCE4(rdev)) { 630 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | 631 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 632 if (rdev->num_crtc >= 4) { 633 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | 634 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 635 } 636 if (rdev->num_crtc >= 6) { 637 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | 638 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 639 } 640 if (reg & EVERGREEN_CRTC_MASTER_EN) 641 return true; 642 } else if (ASIC_IS_AVIVO(rdev)) { 643 reg = RREG32(AVIVO_D1CRTC_CONTROL) | 644 RREG32(AVIVO_D2CRTC_CONTROL); 645 if (reg & AVIVO_CRTC_EN) { 646 return true; 647 } 648 } else { 649 reg = RREG32(RADEON_CRTC_GEN_CNTL) | 650 RREG32(RADEON_CRTC2_GEN_CNTL); 651 if (reg & RADEON_CRTC_EN) { 652 return true; 653 } 654 } 655 656 check_memsize: 657 /* then check MEM_SIZE, in case the crtcs are off */ 658 if (rdev->family >= CHIP_R600) 659 reg = RREG32(R600_CONFIG_MEMSIZE); 660 else 661 reg = RREG32(RADEON_CONFIG_MEMSIZE); 662 663 if (reg) 664 return true; 665 666 return false; 667 668 } 669 670 /** 671 * radeon_update_bandwidth_info - update display bandwidth params 672 * 673 * @rdev: radeon_device pointer 674 * 675 * Used when sclk/mclk are switched or display modes are set. 676 * params are used to calculate display watermarks (all asics) 677 */ 678 void radeon_update_bandwidth_info(struct radeon_device *rdev) 679 { 680 fixed20_12 a; 681 u32 sclk = rdev->pm.current_sclk; 682 u32 mclk = rdev->pm.current_mclk; 683 684 /* sclk/mclk in Mhz */ 685 a.full = dfixed_const(100); 686 rdev->pm.sclk.full = dfixed_const(sclk); 687 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); 688 rdev->pm.mclk.full = dfixed_const(mclk); 689 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); 690 691 if (rdev->flags & RADEON_IS_IGP) { 692 a.full = dfixed_const(16); 693 /* core_bandwidth = sclk(Mhz) * 16 */ 694 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); 695 } 696 } 697 698 /** 699 * radeon_boot_test_post_card - check and possibly initialize the hw 700 * 701 * @rdev: radeon_device pointer 702 * 703 * Check if the asic is initialized and if not, attempt to initialize 704 * it (all asics). 705 * Returns true if initialized or false if not. 706 */ 707 bool radeon_boot_test_post_card(struct radeon_device *rdev) 708 { 709 if (radeon_card_posted(rdev)) 710 return true; 711 712 if (rdev->bios) { 713 DRM_INFO("GPU not posted. posting now...\n"); 714 if (rdev->is_atom_bios) 715 atom_asic_init(rdev->mode_info.atom_context); 716 else 717 radeon_combios_asic_init(rdev->ddev); 718 return true; 719 } else { 720 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 721 return false; 722 } 723 } 724 725 /** 726 * radeon_dummy_page_init - init dummy page used by the driver 727 * 728 * @rdev: radeon_device pointer 729 * 730 * Allocate the dummy page used by the driver (all asics). 731 * This dummy page is used by the driver as a filler for gart entries 732 * when pages are taken out of the GART 733 * Returns 0 on sucess, -ENOMEM on failure. 734 */ 735 int radeon_dummy_page_init(struct radeon_device *rdev) 736 { 737 if (rdev->dummy_page.dmah) 738 return 0; 739 rdev->dummy_page.dmah = drm_pci_alloc(rdev->ddev, 740 PAGE_SIZE, PAGE_SIZE); 741 if (rdev->dummy_page.dmah == NULL) 742 return -ENOMEM; 743 rdev->dummy_page.addr = 744 (dma_addr_t)rdev->dummy_page.dmah->busaddr; 745 rdev->dummy_page.entry = radeon_gart_get_page_entry(rdev->dummy_page.addr, 746 RADEON_GART_PAGE_DUMMY); 747 return 0; 748 } 749 750 /** 751 * radeon_dummy_page_fini - free dummy page used by the driver 752 * 753 * @rdev: radeon_device pointer 754 * 755 * Frees the dummy page used by the driver (all asics). 756 */ 757 void radeon_dummy_page_fini(struct radeon_device *rdev) 758 { 759 if (rdev->dummy_page.dmah == NULL) 760 return; 761 drm_pci_free(rdev->ddev, rdev->dummy_page.dmah); 762 rdev->dummy_page.dmah = NULL; 763 rdev->dummy_page.addr = 0; 764 } 765 766 767 /* ATOM accessor methods */ 768 /* 769 * ATOM is an interpreted byte code stored in tables in the vbios. The 770 * driver registers callbacks to access registers and the interpreter 771 * in the driver parses the tables and executes then to program specific 772 * actions (set display modes, asic init, etc.). See radeon_atombios.c, 773 * atombios.h, and atom.c 774 */ 775 776 /** 777 * cail_pll_read - read PLL register 778 * 779 * @info: atom card_info pointer 780 * @reg: PLL register offset 781 * 782 * Provides a PLL register accessor for the atom interpreter (r4xx+). 783 * Returns the value of the PLL register. 784 */ 785 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) 786 { 787 struct radeon_device *rdev = info->dev->dev_private; 788 uint32_t r; 789 790 r = rdev->pll_rreg(rdev, reg); 791 return r; 792 } 793 794 /** 795 * cail_pll_write - write PLL register 796 * 797 * @info: atom card_info pointer 798 * @reg: PLL register offset 799 * @val: value to write to the pll register 800 * 801 * Provides a PLL register accessor for the atom interpreter (r4xx+). 802 */ 803 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) 804 { 805 struct radeon_device *rdev = info->dev->dev_private; 806 807 rdev->pll_wreg(rdev, reg, val); 808 } 809 810 /** 811 * cail_mc_read - read MC (Memory Controller) register 812 * 813 * @info: atom card_info pointer 814 * @reg: MC register offset 815 * 816 * Provides an MC register accessor for the atom interpreter (r4xx+). 817 * Returns the value of the MC register. 818 */ 819 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) 820 { 821 struct radeon_device *rdev = info->dev->dev_private; 822 uint32_t r; 823 824 r = rdev->mc_rreg(rdev, reg); 825 return r; 826 } 827 828 /** 829 * cail_mc_write - write MC (Memory Controller) register 830 * 831 * @info: atom card_info pointer 832 * @reg: MC register offset 833 * @val: value to write to the pll register 834 * 835 * Provides a MC register accessor for the atom interpreter (r4xx+). 836 */ 837 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) 838 { 839 struct radeon_device *rdev = info->dev->dev_private; 840 841 rdev->mc_wreg(rdev, reg, val); 842 } 843 844 /** 845 * cail_reg_write - write MMIO register 846 * 847 * @info: atom card_info pointer 848 * @reg: MMIO register offset 849 * @val: value to write to the pll register 850 * 851 * Provides a MMIO register accessor for the atom interpreter (r4xx+). 852 */ 853 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) 854 { 855 struct radeon_device *rdev = info->dev->dev_private; 856 857 WREG32(reg*4, val); 858 } 859 860 /** 861 * cail_reg_read - read MMIO register 862 * 863 * @info: atom card_info pointer 864 * @reg: MMIO register offset 865 * 866 * Provides an MMIO register accessor for the atom interpreter (r4xx+). 867 * Returns the value of the MMIO register. 868 */ 869 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) 870 { 871 struct radeon_device *rdev = info->dev->dev_private; 872 uint32_t r; 873 874 r = RREG32(reg*4); 875 return r; 876 } 877 878 /** 879 * cail_ioreg_write - write IO register 880 * 881 * @info: atom card_info pointer 882 * @reg: IO register offset 883 * @val: value to write to the pll register 884 * 885 * Provides a IO register accessor for the atom interpreter (r4xx+). 886 */ 887 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) 888 { 889 struct radeon_device *rdev = info->dev->dev_private; 890 891 WREG32_IO(reg*4, val); 892 } 893 894 /** 895 * cail_ioreg_read - read IO register 896 * 897 * @info: atom card_info pointer 898 * @reg: IO register offset 899 * 900 * Provides an IO register accessor for the atom interpreter (r4xx+). 901 * Returns the value of the IO register. 902 */ 903 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) 904 { 905 struct radeon_device *rdev = info->dev->dev_private; 906 uint32_t r; 907 908 r = RREG32_IO(reg*4); 909 return r; 910 } 911 912 /** 913 * radeon_atombios_init - init the driver info and callbacks for atombios 914 * 915 * @rdev: radeon_device pointer 916 * 917 * Initializes the driver info and register access callbacks for the 918 * ATOM interpreter (r4xx+). 919 * Returns 0 on sucess, -ENOMEM on failure. 920 * Called at driver startup. 921 */ 922 int radeon_atombios_init(struct radeon_device *rdev) 923 { 924 struct card_info *atom_card_info = 925 kzalloc(sizeof(struct card_info), GFP_KERNEL); 926 927 if (!atom_card_info) 928 return -ENOMEM; 929 930 rdev->mode_info.atom_card_info = atom_card_info; 931 atom_card_info->dev = rdev->ddev; 932 atom_card_info->reg_read = cail_reg_read; 933 atom_card_info->reg_write = cail_reg_write; 934 /* needed for iio ops */ 935 if (rdev->rio_mem) { 936 atom_card_info->ioreg_read = cail_ioreg_read; 937 atom_card_info->ioreg_write = cail_ioreg_write; 938 } else { 939 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); 940 atom_card_info->ioreg_read = cail_reg_read; 941 atom_card_info->ioreg_write = cail_reg_write; 942 } 943 atom_card_info->mc_read = cail_mc_read; 944 atom_card_info->mc_write = cail_mc_write; 945 atom_card_info->pll_read = cail_pll_read; 946 atom_card_info->pll_write = cail_pll_write; 947 948 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); 949 if (!rdev->mode_info.atom_context) { 950 radeon_atombios_fini(rdev); 951 return -ENOMEM; 952 } 953 954 lockinit(&rdev->mode_info.atom_context->mutex, "rmiacmtx", 0, LK_CANRECURSE); 955 lockinit(&rdev->mode_info.atom_context->scratch_mutex, "rmiacsmtx", 0, LK_CANRECURSE); 956 radeon_atom_initialize_bios_scratch_regs(rdev->ddev); 957 atom_allocate_fb_scratch(rdev->mode_info.atom_context); 958 return 0; 959 } 960 961 /** 962 * radeon_atombios_fini - free the driver info and callbacks for atombios 963 * 964 * @rdev: radeon_device pointer 965 * 966 * Frees the driver info and register access callbacks for the ATOM 967 * interpreter (r4xx+). 968 * Called at driver shutdown. 969 */ 970 void radeon_atombios_fini(struct radeon_device *rdev) 971 { 972 if (rdev->mode_info.atom_context) { 973 kfree(rdev->mode_info.atom_context->scratch); 974 } 975 kfree(rdev->mode_info.atom_context); 976 rdev->mode_info.atom_context = NULL; 977 kfree(rdev->mode_info.atom_card_info); 978 rdev->mode_info.atom_card_info = NULL; 979 } 980 981 /* COMBIOS */ 982 /* 983 * COMBIOS is the bios format prior to ATOM. It provides 984 * command tables similar to ATOM, but doesn't have a unified 985 * parser. See radeon_combios.c 986 */ 987 988 /** 989 * radeon_combios_init - init the driver info for combios 990 * 991 * @rdev: radeon_device pointer 992 * 993 * Initializes the driver info for combios (r1xx-r3xx). 994 * Returns 0 on sucess. 995 * Called at driver startup. 996 */ 997 int radeon_combios_init(struct radeon_device *rdev) 998 { 999 radeon_combios_initialize_bios_scratch_regs(rdev->ddev); 1000 return 0; 1001 } 1002 1003 /** 1004 * radeon_combios_fini - free the driver info for combios 1005 * 1006 * @rdev: radeon_device pointer 1007 * 1008 * Frees the driver info for combios (r1xx-r3xx). 1009 * Called at driver shutdown. 1010 */ 1011 void radeon_combios_fini(struct radeon_device *rdev) 1012 { 1013 } 1014 1015 #ifdef DUMBBELL_WIP 1016 /* if we get transitioned to only one device, take VGA back */ 1017 /** 1018 * radeon_vga_set_decode - enable/disable vga decode 1019 * 1020 * @cookie: radeon_device pointer 1021 * @state: enable/disable vga decode 1022 * 1023 * Enable/disable vga decode (all asics). 1024 * Returns VGA resource flags. 1025 */ 1026 static unsigned int radeon_vga_set_decode(void *cookie, bool state) 1027 { 1028 struct radeon_device *rdev = cookie; 1029 radeon_vga_set_state(rdev, state); 1030 if (state) 1031 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | 1032 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 1033 else 1034 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 1035 } 1036 #endif /* DUMBBELL_WIP */ 1037 1038 /** 1039 * radeon_check_pot_argument - check that argument is a power of two 1040 * 1041 * @arg: value to check 1042 * 1043 * Validates that a certain argument is a power of two (all asics). 1044 * Returns true if argument is valid. 1045 */ 1046 static bool radeon_check_pot_argument(int arg) 1047 { 1048 return (arg & (arg - 1)) == 0; 1049 } 1050 1051 /** 1052 * Determine a sensible default GART size according to ASIC family. 1053 * 1054 * @family ASIC family name 1055 */ 1056 static int radeon_gart_size_auto(enum radeon_family family) 1057 { 1058 /* default to a larger gart size on newer asics */ 1059 if (family >= CHIP_TAHITI) 1060 return 2048; 1061 else if (family >= CHIP_RV770) 1062 return 1024; 1063 else 1064 return 512; 1065 } 1066 1067 /** 1068 * radeon_check_arguments - validate module params 1069 * 1070 * @rdev: radeon_device pointer 1071 * 1072 * Validates certain module parameters and updates 1073 * the associated values used by the driver (all asics). 1074 */ 1075 static void radeon_check_arguments(struct radeon_device *rdev) 1076 { 1077 /* vramlimit must be a power of two */ 1078 if (!radeon_check_pot_argument(radeon_vram_limit)) { 1079 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", 1080 radeon_vram_limit); 1081 radeon_vram_limit = 0; 1082 } 1083 1084 if (radeon_gart_size == -1) { 1085 radeon_gart_size = radeon_gart_size_auto(rdev->family); 1086 } 1087 /* gtt size must be power of two and greater or equal to 32M */ 1088 if (radeon_gart_size < 32) { 1089 dev_warn(rdev->dev, "gart size (%d) too small\n", 1090 radeon_gart_size); 1091 radeon_gart_size = radeon_gart_size_auto(rdev->family); 1092 } else if (!radeon_check_pot_argument(radeon_gart_size)) { 1093 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", 1094 radeon_gart_size); 1095 radeon_gart_size = radeon_gart_size_auto(rdev->family); 1096 } 1097 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20; 1098 1099 /* AGP mode can only be -1, 1, 2, 4, 8 */ 1100 switch (radeon_agpmode) { 1101 case -1: 1102 case 0: 1103 case 1: 1104 case 2: 1105 case 4: 1106 case 8: 1107 break; 1108 default: 1109 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " 1110 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); 1111 radeon_agpmode = 0; 1112 break; 1113 } 1114 1115 if (!radeon_check_pot_argument(radeon_vm_size)) { 1116 dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n", 1117 radeon_vm_size); 1118 radeon_vm_size = 4; 1119 } 1120 1121 if (radeon_vm_size < 1) { 1122 dev_warn(rdev->dev, "VM size (%d) too small, min is 1GB\n", 1123 radeon_vm_size); 1124 radeon_vm_size = 4; 1125 } 1126 1127 /* 1128 * Max GPUVM size for Cayman, SI and CI are 40 bits. 1129 */ 1130 if (radeon_vm_size > 1024) { 1131 dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n", 1132 radeon_vm_size); 1133 radeon_vm_size = 4; 1134 } 1135 1136 /* defines number of bits in page table versus page directory, 1137 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the 1138 * page table and the remaining bits are in the page directory */ 1139 if (radeon_vm_block_size == -1) { 1140 1141 /* Total bits covered by PD + PTs */ 1142 unsigned bits = ilog2(radeon_vm_size) + 18; 1143 1144 /* Make sure the PD is 4K in size up to 8GB address space. 1145 Above that split equal between PD and PTs */ 1146 if (radeon_vm_size <= 8) 1147 radeon_vm_block_size = bits - 9; 1148 else 1149 radeon_vm_block_size = (bits + 3) / 2; 1150 1151 } else if (radeon_vm_block_size < 9) { 1152 dev_warn(rdev->dev, "VM page table size (%d) too small\n", 1153 radeon_vm_block_size); 1154 radeon_vm_block_size = 9; 1155 } 1156 1157 if (radeon_vm_block_size > 24 || 1158 (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) { 1159 dev_warn(rdev->dev, "VM page table size (%d) too large\n", 1160 radeon_vm_block_size); 1161 radeon_vm_block_size = 9; 1162 } 1163 } 1164 1165 /** 1166 * radeon_switcheroo_set_state - set switcheroo state 1167 * 1168 * @pdev: pci dev pointer 1169 * @state: vga_switcheroo state 1170 * 1171 * Callback for the switcheroo driver. Suspends or resumes the 1172 * the asics before or after it is powered up using ACPI methods. 1173 */ 1174 #ifdef DUMBBELL_WIP 1175 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) 1176 { 1177 struct drm_device *dev = pci_get_drvdata(pdev); 1178 struct radeon_device *rdev = dev->dev_private; 1179 1180 if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF) 1181 return; 1182 1183 if (state == VGA_SWITCHEROO_ON) { 1184 unsigned d3_delay = dev->pdev->d3_delay; 1185 1186 printk(KERN_INFO "radeon: switched on\n"); 1187 /* don't suspend or resume card normally */ 1188 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1189 1190 if (d3_delay < 20 && (rdev->px_quirk_flags & RADEON_PX_QUIRK_LONG_WAKEUP)) 1191 dev->pdev->d3_delay = 20; 1192 1193 radeon_resume_kms(dev, true, true); 1194 1195 dev->pdev->d3_delay = d3_delay; 1196 1197 dev->switch_power_state = DRM_SWITCH_POWER_ON; 1198 drm_kms_helper_poll_enable(dev); 1199 } else { 1200 printk(KERN_INFO "radeon: switched off\n"); 1201 drm_kms_helper_poll_disable(dev); 1202 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1203 radeon_suspend_kms(dev, true, true, false); 1204 dev->switch_power_state = DRM_SWITCH_POWER_OFF; 1205 } 1206 } 1207 #endif /* DUMBBELL_WIP */ 1208 1209 /** 1210 * radeon_switcheroo_can_switch - see if switcheroo state can change 1211 * 1212 * @pdev: pci dev pointer 1213 * 1214 * Callback for the switcheroo driver. Check of the switcheroo 1215 * state can be changed. 1216 * Returns true if the state can be changed, false if not. 1217 */ 1218 #ifdef DUMBBELL_WIP 1219 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev) 1220 { 1221 struct drm_device *dev = pci_get_drvdata(pdev); 1222 1223 /* 1224 * FIXME: open_count is protected by drm_global_mutex but that would lead to 1225 * locking inversion with the driver load path. And the access here is 1226 * completely racy anyway. So don't bother with locking for now. 1227 */ 1228 return dev->open_count == 0; 1229 } 1230 1231 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = { 1232 .set_gpu_state = radeon_switcheroo_set_state, 1233 .reprobe = NULL, 1234 .can_switch = radeon_switcheroo_can_switch, 1235 }; 1236 #endif /* DUMBBELL_WIP */ 1237 1238 /** 1239 * radeon_device_init - initialize the driver 1240 * 1241 * @rdev: radeon_device pointer 1242 * @pdev: drm dev pointer 1243 * @pdev: pci dev pointer 1244 * @flags: driver flags 1245 * 1246 * Initializes the driver info and hw (all asics). 1247 * Returns 0 for success or an error on failure. 1248 * Called at driver startup. 1249 */ 1250 int radeon_device_init(struct radeon_device *rdev, 1251 struct drm_device *ddev, 1252 struct pci_dev *pdev, 1253 uint32_t flags) 1254 { 1255 int r, i; 1256 int dma_bits; 1257 #ifdef PM_TODO 1258 bool runtime = false; 1259 #endif 1260 1261 rdev->shutdown = false; 1262 rdev->dev = &pdev->dev; 1263 rdev->ddev = ddev; 1264 rdev->pdev = pdev; 1265 rdev->flags = flags; 1266 rdev->family = flags & RADEON_FAMILY_MASK; 1267 rdev->is_atom_bios = false; 1268 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; 1269 rdev->mc.gtt_size = 512 * 1024 * 1024; 1270 rdev->accel_working = false; 1271 rdev->fictitious_range_registered = false; 1272 /* set up ring ids */ 1273 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1274 rdev->ring[i].idx = i; 1275 } 1276 1277 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", 1278 radeon_family_name[rdev->family], pdev->vendor, pdev->device, 1279 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); 1280 1281 /* mutex initialization are all done here so we 1282 * can recall function without having locking issues */ 1283 lockinit(&rdev->ring_lock, "drm__radeon_device__ring_lock", 0, 1284 LK_CANRECURSE); 1285 lockinit(&rdev->dc_hw_i2c_mutex, 1286 "drm__radeon_device__dc_hw_i2c_mutex", 0, LK_CANRECURSE); 1287 atomic_set(&rdev->ih.lock, 0); 1288 lockinit(&rdev->gem.mutex, "radeon_gemmtx", 0, LK_CANRECURSE); 1289 lockinit(&rdev->pm.mutex, "drm__radeon_device__pm__mutex", 0, 1290 LK_CANRECURSE); 1291 1292 lockinit(&rdev->gpu_clock_mutex, "radeon_clockmtx", 0, LK_CANRECURSE); 1293 lockinit(&rdev->srbm_mutex, "radeon_srbm_mutex", 0, LK_CANRECURSE); 1294 lockinit(&rdev->grbm_idx_mutex, "radeon_grbm_mutex", 0, LK_CANRECURSE); 1295 lockinit(&rdev->pm.mclk_lock, "drm__radeon_device__pm__mclk_lock", 0, 1296 LK_CANRECURSE); 1297 lockinit(&rdev->exclusive_lock, "drm__radeon_device__exclusive_lock", 1298 0, LK_CANRECURSE); 1299 init_waitqueue_head(&rdev->irq.vblank_queue); 1300 r = radeon_gem_init(rdev); 1301 if (r) 1302 return r; 1303 1304 radeon_check_arguments(rdev); 1305 /* Adjust VM size here. 1306 * Max GPUVM size for cayman+ is 40 bits. 1307 */ 1308 rdev->vm_manager.max_pfn = radeon_vm_size << 18; 1309 1310 /* Set asic functions */ 1311 r = radeon_asic_init(rdev); 1312 if (r) 1313 return r; 1314 1315 /* all of the newer IGP chips have an internal gart 1316 * However some rs4xx report as AGP, so remove that here. 1317 */ 1318 if ((rdev->family >= CHIP_RS400) && 1319 (rdev->flags & RADEON_IS_IGP)) { 1320 rdev->flags &= ~RADEON_IS_AGP; 1321 } 1322 1323 DRM_INFO("radeon_device_init: rdev->flags & RADEON_IS_AGP (%lu)\n", 1324 rdev->flags & RADEON_IS_AGP); 1325 1326 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { 1327 radeon_agp_disable(rdev); 1328 } 1329 1330 /* Set the internal MC address mask 1331 * This is the max address of the GPU's 1332 * internal address space. 1333 */ 1334 if (rdev->family >= CHIP_CAYMAN) 1335 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1336 else if (rdev->family >= CHIP_CEDAR) 1337 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */ 1338 else 1339 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */ 1340 1341 /* set DMA mask + need_dma32 flags. 1342 * PCIE - can handle 40-bits. 1343 * IGP - can handle 40-bits 1344 * AGP - generally dma32 is safest 1345 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 1346 */ 1347 rdev->need_dma32 = false; 1348 if (rdev->flags & RADEON_IS_AGP) 1349 rdev->need_dma32 = true; 1350 if ((rdev->flags & RADEON_IS_PCI) && 1351 (rdev->family <= CHIP_RS740)) 1352 rdev->need_dma32 = true; 1353 1354 dma_bits = rdev->need_dma32 ? 32 : 40; 1355 #ifdef DUMBBELL_WIP 1356 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 1357 if (r) { 1358 rdev->need_dma32 = true; 1359 dma_bits = 32; 1360 printk(KERN_WARNING "radeon: No suitable DMA available.\n"); 1361 } 1362 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 1363 if (r) { 1364 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32)); 1365 printk(KERN_WARNING "radeon: No coherent DMA available.\n"); 1366 } 1367 #endif /* DUMBBELL_WIP */ 1368 1369 /* Registers mapping */ 1370 /* TODO: block userspace mapping of io register */ 1371 lockinit(&rdev->mmio_idx_lock, "radeon_mpio", 0, LK_CANRECURSE); 1372 lockinit(&rdev->smc_idx_lock, "radeon_smc", 0, LK_CANRECURSE); 1373 lockinit(&rdev->pll_idx_lock, "radeon_pll", 0, LK_CANRECURSE); 1374 lockinit(&rdev->mc_idx_lock, "radeon_mc", 0, LK_CANRECURSE); 1375 lockinit(&rdev->pcie_idx_lock, "radeon_pcie", 0, LK_CANRECURSE); 1376 lockinit(&rdev->pciep_idx_lock, "radeon_pciep", 0, LK_CANRECURSE); 1377 lockinit(&rdev->pif_idx_lock, "radeon_pif", 0, LK_CANRECURSE); 1378 lockinit(&rdev->cg_idx_lock, "radeon_cg", 0, LK_CANRECURSE); 1379 lockinit(&rdev->uvd_idx_lock, "radeon_uvd", 0, LK_CANRECURSE); 1380 lockinit(&rdev->rcu_idx_lock, "radeon_rcu", 0, LK_CANRECURSE); 1381 lockinit(&rdev->didt_idx_lock, "radeon_didt", 0, LK_CANRECURSE); 1382 lockinit(&rdev->end_idx_lock, "radeon_end", 0, LK_CANRECURSE); 1383 if (rdev->family >= CHIP_BONAIRE) { 1384 rdev->rmmio_rid = PCIR_BAR(5); 1385 } else { 1386 rdev->rmmio_rid = PCIR_BAR(2); 1387 } 1388 rdev->rmmio = bus_alloc_resource_any(rdev->dev->bsddev, SYS_RES_MEMORY, 1389 &rdev->rmmio_rid, RF_ACTIVE | RF_SHAREABLE); 1390 if (rdev->rmmio == NULL) { 1391 return -ENOMEM; 1392 } 1393 rdev->rmmio_base = rman_get_start(rdev->rmmio); 1394 rdev->rmmio_size = rman_get_size(rdev->rmmio); 1395 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); 1396 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); 1397 1398 /* doorbell bar mapping */ 1399 if (rdev->family >= CHIP_BONAIRE) 1400 radeon_doorbell_init(rdev); 1401 1402 /* io port mapping */ 1403 for (i = 0; i < DRM_MAX_PCI_RESOURCE; i++) { 1404 uint32_t data; 1405 1406 data = pci_read_config(rdev->dev->bsddev, PCIR_BAR(i), 4); 1407 if (PCI_BAR_IO(data)) { 1408 rdev->rio_rid = PCIR_BAR(i); 1409 rdev->rio_mem = bus_alloc_resource_any(rdev->dev->bsddev, 1410 SYS_RES_IOPORT, &rdev->rio_rid, 1411 RF_ACTIVE | RF_SHAREABLE); 1412 break; 1413 } 1414 } 1415 if (rdev->rio_mem == NULL) 1416 DRM_ERROR("Unable to find PCI I/O BAR\n"); 1417 1418 rdev->tq = taskqueue_create("radeonkms", M_WAITOK, 1419 taskqueue_thread_enqueue, &rdev->tq); 1420 taskqueue_start_threads(&rdev->tq, 1, TDPRI_KERN_DAEMON, 1421 -1, "radeon taskq"); 1422 1423 if (rdev->flags & RADEON_IS_PX) 1424 radeon_device_handle_px_quirks(rdev); 1425 1426 #ifdef DUMBBELL_WIP 1427 /* if we have > 1 VGA cards, then disable the radeon VGA resources */ 1428 /* this will fail for cards that aren't VGA class devices, just 1429 * ignore it */ 1430 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); 1431 1432 #ifdef PM_TODO 1433 if (rdev->flags & RADEON_IS_PX) 1434 runtime = true; 1435 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime); 1436 if (runtime) 1437 vga_switcheroo_init_domain_pm_ops(rdev->dev->bsddev, &rdev->vga_pm_domain); 1438 #endif 1439 #endif /* DUMBBELL_WIP */ 1440 1441 r = radeon_init(rdev); 1442 if (r) 1443 goto failed; 1444 1445 r = radeon_gem_debugfs_init(rdev); 1446 if (r) { 1447 DRM_ERROR("registering gem debugfs failed (%d).\n", r); 1448 } 1449 1450 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { 1451 /* Acceleration not working on AGP card try again 1452 * with fallback to PCI or PCIE GART 1453 */ 1454 radeon_asic_reset(rdev); 1455 radeon_fini(rdev); 1456 radeon_agp_disable(rdev); 1457 r = radeon_init(rdev); 1458 if (r) 1459 goto failed; 1460 } 1461 1462 r = radeon_ib_ring_tests(rdev); 1463 if (r) 1464 DRM_ERROR("ib ring test failed (%d).\n", r); 1465 1466 DRM_INFO("%s: Taking over the fictitious range 0x%lx-0x%llx\n", 1467 __func__, (uintmax_t)rdev->mc.aper_base, 1468 (uintmax_t)rdev->mc.aper_base + rdev->mc.visible_vram_size); 1469 r = vm_phys_fictitious_reg_range( 1470 rdev->mc.aper_base, 1471 rdev->mc.aper_base + rdev->mc.visible_vram_size, 1472 VM_MEMATTR_WRITE_COMBINING); 1473 if (r != 0) { 1474 DRM_ERROR("Failed to register fictitious range " 1475 "0x%lx-0x%llx (%d).\n", (uintmax_t)rdev->mc.aper_base, 1476 (uintmax_t)rdev->mc.aper_base + rdev->mc.visible_vram_size, r); 1477 return (-r); 1478 } 1479 rdev->fictitious_range_registered = true; 1480 1481 /* 1482 * Turks/Thames GPU will freeze whole laptop if DPM is not restarted 1483 * after the CP ring have chew one packet at least. Hence here we stop 1484 * and restart DPM after the radeon_ib_ring_tests(). 1485 */ 1486 if (rdev->pm.dpm_enabled && 1487 (rdev->pm.pm_method == PM_METHOD_DPM) && 1488 (rdev->family == CHIP_TURKS) && 1489 (rdev->flags & RADEON_IS_MOBILITY)) { 1490 mutex_lock(&rdev->pm.mutex); 1491 radeon_dpm_disable(rdev); 1492 radeon_dpm_enable(rdev); 1493 mutex_unlock(&rdev->pm.mutex); 1494 } 1495 1496 if ((radeon_testing & 1)) { 1497 if (rdev->accel_working) 1498 radeon_test_moves(rdev); 1499 else 1500 DRM_INFO("radeon: acceleration disabled, skipping move tests\n"); 1501 } 1502 if ((radeon_testing & 2)) { 1503 if (rdev->accel_working) 1504 radeon_test_syncing(rdev); 1505 else 1506 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n"); 1507 } 1508 if (radeon_benchmarking) { 1509 if (rdev->accel_working) 1510 radeon_benchmark(rdev, radeon_benchmarking); 1511 else 1512 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n"); 1513 } 1514 return 0; 1515 1516 failed: 1517 #ifdef DRM_BDSM 1518 if (runtime) 1519 vga_switcheroo_fini_domain_pm_ops(rdev->dev); 1520 #endif 1521 return r; 1522 } 1523 1524 #ifdef DUMBBELL_WIP 1525 static void radeon_debugfs_remove_files(struct radeon_device *rdev); 1526 #endif /* DUMBBELL_WIP */ 1527 1528 /** 1529 * radeon_device_fini - tear down the driver 1530 * 1531 * @rdev: radeon_device pointer 1532 * 1533 * Tear down the driver info (all asics). 1534 * Called at driver shutdown. 1535 */ 1536 void radeon_device_fini(struct radeon_device *rdev) 1537 { 1538 DRM_INFO("radeon: finishing device.\n"); 1539 rdev->shutdown = true; 1540 /* evict vram memory */ 1541 radeon_bo_evict_vram(rdev); 1542 1543 if (rdev->fictitious_range_registered) { 1544 vm_phys_fictitious_unreg_range( 1545 rdev->mc.aper_base, 1546 rdev->mc.aper_base + rdev->mc.visible_vram_size); 1547 } 1548 1549 radeon_fini(rdev); 1550 #ifdef DUMBBELL_WIP 1551 vga_switcheroo_unregister_client(rdev->pdev); 1552 if (rdev->flags & RADEON_IS_PX) 1553 vga_switcheroo_fini_domain_pm_ops(rdev->dev); 1554 vga_client_register(rdev->pdev, NULL, NULL, NULL); 1555 #endif /* DUMBBELL_WIP */ 1556 1557 if (rdev->tq != NULL) { 1558 taskqueue_free(rdev->tq); 1559 rdev->tq = NULL; 1560 } 1561 1562 if (rdev->rio_mem) 1563 bus_release_resource(rdev->dev->bsddev, SYS_RES_IOPORT, rdev->rio_rid, 1564 rdev->rio_mem); 1565 rdev->rio_mem = NULL; 1566 bus_release_resource(rdev->dev->bsddev, SYS_RES_MEMORY, rdev->rmmio_rid, 1567 rdev->rmmio); 1568 rdev->rmmio = NULL; 1569 if (rdev->family >= CHIP_BONAIRE) 1570 radeon_doorbell_fini(rdev); 1571 #ifdef DUMBBELL_WIP 1572 radeon_debugfs_remove_files(rdev); 1573 #endif /* DUMBBELL_WIP */ 1574 } 1575 1576 1577 /* 1578 * Suspend & resume. 1579 */ 1580 /** 1581 * radeon_suspend_kms - initiate device suspend 1582 * 1583 * @pdev: drm dev pointer 1584 * @state: suspend state 1585 * 1586 * Puts the hw in the suspend state (all asics). 1587 * Returns 0 for success or an error on failure. 1588 * Called at driver suspend. 1589 */ 1590 int radeon_suspend_kms(struct drm_device *dev, bool suspend, 1591 bool fbcon, bool freeze) 1592 { 1593 struct radeon_device *rdev; 1594 struct drm_crtc *crtc; 1595 struct drm_connector *connector; 1596 int i, r; 1597 1598 if (dev == NULL || dev->dev_private == NULL) { 1599 return -ENODEV; 1600 } 1601 1602 rdev = dev->dev_private; 1603 1604 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1605 return 0; 1606 1607 drm_kms_helper_poll_disable(dev); 1608 1609 drm_modeset_lock_all(dev); 1610 /* turn off display hw */ 1611 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1612 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 1613 } 1614 drm_modeset_unlock_all(dev); 1615 1616 /* unpin the front buffers and cursors */ 1617 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1618 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1619 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->primary->fb); 1620 struct radeon_bo *robj; 1621 1622 if (radeon_crtc->cursor_bo) { 1623 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); 1624 r = radeon_bo_reserve(robj, false); 1625 if (r == 0) { 1626 radeon_bo_unpin(robj); 1627 radeon_bo_unreserve(robj); 1628 } 1629 } 1630 1631 if (rfb == NULL || rfb->obj == NULL) { 1632 continue; 1633 } 1634 robj = gem_to_radeon_bo(rfb->obj); 1635 /* don't unpin kernel fb objects */ 1636 if (!radeon_fbdev_robj_is_fb(rdev, robj)) { 1637 r = radeon_bo_reserve(robj, false); 1638 if (r == 0) { 1639 radeon_bo_unpin(robj); 1640 radeon_bo_unreserve(robj); 1641 } 1642 } 1643 } 1644 /* evict vram memory */ 1645 radeon_bo_evict_vram(rdev); 1646 1647 /* wait for gpu to finish processing current batch */ 1648 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1649 r = radeon_fence_wait_empty(rdev, i); 1650 if (r) { 1651 /* delay GPU reset to resume */ 1652 radeon_fence_driver_force_completion(rdev, i); 1653 } 1654 } 1655 1656 radeon_save_bios_scratch_regs(rdev); 1657 1658 radeon_suspend(rdev); 1659 radeon_hpd_fini(rdev); 1660 /* evict remaining vram memory */ 1661 radeon_bo_evict_vram(rdev); 1662 1663 radeon_agp_suspend(rdev); 1664 1665 pci_save_state(device_get_parent(rdev->dev->bsddev)); 1666 #ifdef DUMBBELL_WIP 1667 if (freeze && rdev->family >= CHIP_R600) { 1668 rdev->asic->asic_reset(rdev, true); 1669 pci_restore_state(device_get_parent(rdev->dev->bsddev)); 1670 } else if (suspend) { 1671 /* Shut down the device */ 1672 pci_disable_device(dev->pdev); 1673 #endif /* DUMBBELL_WIP */ 1674 pci_set_powerstate(dev->dev->bsddev, PCI_POWERSTATE_D3); 1675 #ifdef DUMBBELL_WIP 1676 } 1677 #endif 1678 if (fbcon) { 1679 #ifdef DUMBBELL_WIP 1680 console_lock(); 1681 #endif /* DUMBBELL_WIP */ 1682 radeon_fbdev_set_suspend(rdev, 1); 1683 #ifdef DUMBBELL_WIP 1684 console_unlock(); 1685 #endif /* DUMBBELL_WIP */ 1686 } 1687 return 0; 1688 } 1689 1690 /** 1691 * radeon_resume_kms - initiate device resume 1692 * 1693 * @pdev: drm dev pointer 1694 * 1695 * Bring the hw back to operating state (all asics). 1696 * Returns 0 for success or an error on failure. 1697 * Called at driver resume. 1698 */ 1699 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon) 1700 { 1701 struct drm_connector *connector; 1702 struct radeon_device *rdev = dev->dev_private; 1703 struct drm_crtc *crtc; 1704 int r; 1705 1706 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1707 return 0; 1708 1709 #ifdef DUMBBELL_WIP 1710 if (fbcon) { 1711 console_lock(); 1712 } 1713 #endif /* DUMBBELL_WIP */ 1714 if (resume) { 1715 pci_set_powerstate(dev->dev->bsddev, PCI_POWERSTATE_D0); 1716 pci_restore_state(device_get_parent(rdev->dev->bsddev)); 1717 #ifdef DUMBBELL_WIP 1718 if (pci_enable_device(dev->pdev)) { 1719 if (fbcon) 1720 console_unlock(); 1721 return -1; 1722 } 1723 #endif /* DUMBBELL_WIP */ 1724 } 1725 /* resume AGP if in use */ 1726 radeon_agp_resume(rdev); 1727 radeon_resume(rdev); 1728 1729 r = radeon_ib_ring_tests(rdev); 1730 if (r) 1731 DRM_ERROR("ib ring test failed (%d).\n", r); 1732 1733 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 1734 /* do dpm late init */ 1735 r = radeon_pm_late_init(rdev); 1736 if (r) { 1737 rdev->pm.dpm_enabled = false; 1738 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1739 } 1740 } else { 1741 /* resume old pm late */ 1742 radeon_pm_resume(rdev); 1743 } 1744 1745 radeon_restore_bios_scratch_regs(rdev); 1746 1747 /* pin cursors */ 1748 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1749 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1750 1751 if (radeon_crtc->cursor_bo) { 1752 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); 1753 r = radeon_bo_reserve(robj, false); 1754 if (r == 0) { 1755 /* Only 27 bit offset for legacy cursor */ 1756 r = radeon_bo_pin_restricted(robj, 1757 RADEON_GEM_DOMAIN_VRAM, 1758 ASIC_IS_AVIVO(rdev) ? 1759 0 : 1 << 27, 1760 (u64 *)&radeon_crtc->cursor_addr); 1761 if (r != 0) 1762 DRM_ERROR("Failed to pin cursor BO (%d)\n", r); 1763 radeon_bo_unreserve(robj); 1764 } 1765 } 1766 } 1767 1768 /* init dig PHYs, disp eng pll */ 1769 if (rdev->is_atom_bios) { 1770 radeon_atom_encoder_init(rdev); 1771 radeon_atom_disp_eng_pll_init(rdev); 1772 /* turn on the BL */ 1773 if (rdev->mode_info.bl_encoder) { 1774 u8 bl_level = radeon_get_backlight_level(rdev, 1775 rdev->mode_info.bl_encoder); 1776 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, 1777 bl_level); 1778 } 1779 } 1780 /* reset hpd state */ 1781 radeon_hpd_init(rdev); 1782 /* blat the mode back in */ 1783 if (fbcon) { 1784 drm_helper_resume_force_mode(dev); 1785 /* turn on display hw */ 1786 drm_modeset_lock_all(dev); 1787 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1788 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 1789 } 1790 drm_modeset_unlock_all(dev); 1791 } 1792 1793 drm_kms_helper_poll_enable(dev); 1794 1795 /* set the power state here in case we are a PX system or headless */ 1796 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 1797 radeon_pm_compute_clocks(rdev); 1798 1799 if (fbcon) { 1800 radeon_fbdev_set_suspend(rdev, 0); 1801 #ifdef DUMBBELL_WIP 1802 console_unlock(); 1803 #endif /* DUMBBELL_WIP */ 1804 } 1805 1806 return 0; 1807 } 1808 1809 /** 1810 * radeon_gpu_reset - reset the asic 1811 * 1812 * @rdev: radeon device pointer 1813 * 1814 * Attempt the reset the GPU if it has hung (all asics). 1815 * Returns 0 for success or an error on failure. 1816 */ 1817 int radeon_gpu_reset(struct radeon_device *rdev) 1818 { 1819 unsigned ring_sizes[RADEON_NUM_RINGS]; 1820 uint32_t *ring_data[RADEON_NUM_RINGS]; 1821 1822 bool saved = false; 1823 1824 int i, r; 1825 int resched; 1826 1827 lockmgr(&rdev->exclusive_lock, LK_EXCLUSIVE); 1828 1829 if (!rdev->needs_reset) { 1830 lockmgr(&rdev->exclusive_lock, LK_RELEASE); 1831 return 0; 1832 } 1833 1834 atomic_inc(&rdev->gpu_reset_counter); 1835 1836 radeon_save_bios_scratch_regs(rdev); 1837 /* block TTM */ 1838 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); 1839 radeon_suspend(rdev); 1840 radeon_hpd_fini(rdev); 1841 1842 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1843 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i], 1844 &ring_data[i]); 1845 if (ring_sizes[i]) { 1846 saved = true; 1847 dev_info(rdev->dev, "Saved %d dwords of commands " 1848 "on ring %d.\n", ring_sizes[i], i); 1849 } 1850 } 1851 1852 r = radeon_asic_reset(rdev); 1853 if (!r) { 1854 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n"); 1855 radeon_resume(rdev); 1856 } 1857 1858 radeon_restore_bios_scratch_regs(rdev); 1859 1860 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1861 if (!r && ring_data[i]) { 1862 radeon_ring_restore(rdev, &rdev->ring[i], 1863 ring_sizes[i], ring_data[i]); 1864 } else { 1865 radeon_fence_driver_force_completion(rdev, i); 1866 kfree(ring_data[i]); 1867 } 1868 } 1869 1870 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 1871 /* do dpm late init */ 1872 r = radeon_pm_late_init(rdev); 1873 if (r) { 1874 rdev->pm.dpm_enabled = false; 1875 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1876 } 1877 } else { 1878 /* resume old pm late */ 1879 radeon_pm_resume(rdev); 1880 } 1881 1882 /* init dig PHYs, disp eng pll */ 1883 if (rdev->is_atom_bios) { 1884 radeon_atom_encoder_init(rdev); 1885 radeon_atom_disp_eng_pll_init(rdev); 1886 /* turn on the BL */ 1887 if (rdev->mode_info.bl_encoder) { 1888 u8 bl_level = radeon_get_backlight_level(rdev, 1889 rdev->mode_info.bl_encoder); 1890 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, 1891 bl_level); 1892 } 1893 } 1894 /* reset hpd state */ 1895 radeon_hpd_init(rdev); 1896 1897 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); 1898 1899 rdev->in_reset = true; 1900 rdev->needs_reset = false; 1901 1902 #if 0 1903 downgrade_write(&rdev->exclusive_lock); 1904 #endif 1905 1906 drm_helper_resume_force_mode(rdev->ddev); 1907 1908 /* set the power state here in case we are a PX system or headless */ 1909 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 1910 radeon_pm_compute_clocks(rdev); 1911 1912 if (!r) { 1913 r = radeon_ib_ring_tests(rdev); 1914 if (r && saved) 1915 r = -EAGAIN; 1916 } else { 1917 /* bad news, how to tell it to userspace ? */ 1918 dev_info(rdev->dev, "GPU reset failed\n"); 1919 } 1920 1921 rdev->needs_reset = r == -EAGAIN; 1922 rdev->in_reset = false; 1923 1924 lockmgr(&rdev->exclusive_lock, LK_RELEASE); 1925 return r; 1926 } 1927 1928 1929 /* 1930 * Debugfs 1931 */ 1932 #ifdef DUMBBELL_WIP 1933 int radeon_debugfs_add_files(struct radeon_device *rdev, 1934 struct drm_info_list *files, 1935 unsigned nfiles) 1936 { 1937 unsigned i; 1938 1939 for (i = 0; i < rdev->debugfs_count; i++) { 1940 if (rdev->debugfs[i].files == files) { 1941 /* Already registered */ 1942 return 0; 1943 } 1944 } 1945 1946 i = rdev->debugfs_count + 1; 1947 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) { 1948 DRM_ERROR("Reached maximum number of debugfs components.\n"); 1949 DRM_ERROR("Report so we increase " 1950 "RADEON_DEBUGFS_MAX_COMPONENTS.\n"); 1951 return -EINVAL; 1952 } 1953 rdev->debugfs[rdev->debugfs_count].files = files; 1954 rdev->debugfs[rdev->debugfs_count].num_files = nfiles; 1955 rdev->debugfs_count = i; 1956 #if defined(CONFIG_DEBUG_FS) 1957 drm_debugfs_create_files(files, nfiles, 1958 rdev->ddev->control->debugfs_root, 1959 rdev->ddev->control); 1960 drm_debugfs_create_files(files, nfiles, 1961 rdev->ddev->primary->debugfs_root, 1962 rdev->ddev->primary); 1963 #endif 1964 return 0; 1965 } 1966 1967 static void radeon_debugfs_remove_files(struct radeon_device *rdev) 1968 { 1969 #if defined(CONFIG_DEBUG_FS) 1970 unsigned i; 1971 1972 for (i = 0; i < rdev->debugfs_count; i++) { 1973 drm_debugfs_remove_files(rdev->debugfs[i].files, 1974 rdev->debugfs[i].num_files, 1975 rdev->ddev->control); 1976 drm_debugfs_remove_files(rdev->debugfs[i].files, 1977 rdev->debugfs[i].num_files, 1978 rdev->ddev->primary); 1979 } 1980 #endif 1981 } 1982 1983 #if defined(CONFIG_DEBUG_FS) 1984 int radeon_debugfs_init(struct drm_minor *minor) 1985 { 1986 return 0; 1987 } 1988 1989 void radeon_debugfs_cleanup(struct drm_minor *minor) 1990 { 1991 } 1992 #endif 1993 #endif /* DUMBBELL_WIP */ 1994