1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/console.h> 29 #include <drm/drmP.h> 30 #include "drm/drm_legacy.h" /* for drm_dma_handle_t */ 31 #include <drm/drm_crtc_helper.h> 32 #include <drm/radeon_drm.h> 33 #include <linux/vgaarb.h> 34 #include <linux/vga_switcheroo.h> 35 #include "radeon_reg.h" 36 #include "radeon.h" 37 #include "atom.h" 38 39 #include <asm/cpufeature.h> 40 41 static const char radeon_family_name[][16] = { 42 "R100", 43 "RV100", 44 "RS100", 45 "RV200", 46 "RS200", 47 "R200", 48 "RV250", 49 "RS300", 50 "RV280", 51 "R300", 52 "R350", 53 "RV350", 54 "RV380", 55 "R420", 56 "R423", 57 "RV410", 58 "RS400", 59 "RS480", 60 "RS600", 61 "RS690", 62 "RS740", 63 "RV515", 64 "R520", 65 "RV530", 66 "RV560", 67 "RV570", 68 "R580", 69 "R600", 70 "RV610", 71 "RV630", 72 "RV670", 73 "RV620", 74 "RV635", 75 "RS780", 76 "RS880", 77 "RV770", 78 "RV730", 79 "RV710", 80 "RV740", 81 "CEDAR", 82 "REDWOOD", 83 "JUNIPER", 84 "CYPRESS", 85 "HEMLOCK", 86 "PALM", 87 "SUMO", 88 "SUMO2", 89 "BARTS", 90 "TURKS", 91 "CAICOS", 92 "CAYMAN", 93 "ARUBA", 94 "TAHITI", 95 "PITCAIRN", 96 "VERDE", 97 "OLAND", 98 "HAINAN", 99 "BONAIRE", 100 "KAVERI", 101 "KABINI", 102 "HAWAII", 103 "MULLINS", 104 "LAST", 105 }; 106 107 #if defined(CONFIG_VGA_SWITCHEROO) 108 bool radeon_has_atpx_dgpu_power_cntl(void); 109 bool radeon_is_atpx_hybrid(void); 110 #else 111 static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; } 112 static inline bool radeon_is_atpx_hybrid(void) { return false; } 113 #endif 114 115 #define RADEON_PX_QUIRK_DISABLE_PX (1 << 0) 116 #define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1) 117 118 struct radeon_px_quirk { 119 u32 chip_vendor; 120 u32 chip_device; 121 u32 subsys_vendor; 122 u32 subsys_device; 123 u32 px_quirk_flags; 124 }; 125 126 static struct radeon_px_quirk radeon_px_quirk_list[] = { 127 /* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m) 128 * https://bugzilla.kernel.org/show_bug.cgi?id=74551 129 */ 130 { PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX }, 131 /* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU 132 * https://bugzilla.kernel.org/show_bug.cgi?id=51381 133 */ 134 { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX }, 135 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU 136 * https://bugzilla.kernel.org/show_bug.cgi?id=51381 137 */ 138 { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX }, 139 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU 140 * https://bugs.freedesktop.org/show_bug.cgi?id=101491 141 */ 142 { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX }, 143 /* macbook pro 8.2 */ 144 { PCI_VENDOR_ID_ATI, 0x6741, PCI_VENDOR_ID_APPLE, 0x00e2, RADEON_PX_QUIRK_LONG_WAKEUP }, 145 { 0, 0, 0, 0, 0 }, 146 }; 147 148 bool radeon_is_px(struct drm_device *dev) 149 { 150 struct radeon_device *rdev = dev->dev_private; 151 152 if (rdev->flags & RADEON_IS_PX) 153 return true; 154 return false; 155 } 156 157 static void radeon_device_handle_px_quirks(struct radeon_device *rdev) 158 { 159 struct radeon_px_quirk *p = radeon_px_quirk_list; 160 161 /* Apply PX quirks */ 162 while (p && p->chip_device != 0) { 163 if (rdev->pdev->vendor == p->chip_vendor && 164 rdev->pdev->device == p->chip_device && 165 rdev->pdev->subsystem_vendor == p->subsys_vendor && 166 rdev->pdev->subsystem_device == p->subsys_device) { 167 rdev->px_quirk_flags = p->px_quirk_flags; 168 break; 169 } 170 ++p; 171 } 172 173 if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX) 174 rdev->flags &= ~RADEON_IS_PX; 175 176 /* disable PX is the system doesn't support dGPU power control or hybrid gfx */ 177 if (!radeon_is_atpx_hybrid() && 178 !radeon_has_atpx_dgpu_power_cntl()) 179 rdev->flags &= ~RADEON_IS_PX; 180 } 181 182 /** 183 * radeon_program_register_sequence - program an array of registers. 184 * 185 * @rdev: radeon_device pointer 186 * @registers: pointer to the register array 187 * @array_size: size of the register array 188 * 189 * Programs an array or registers with and and or masks. 190 * This is a helper for setting golden registers. 191 */ 192 void radeon_program_register_sequence(struct radeon_device *rdev, 193 const u32 *registers, 194 const u32 array_size) 195 { 196 u32 tmp, reg, and_mask, or_mask; 197 int i; 198 199 if (array_size % 3) 200 return; 201 202 for (i = 0; i < array_size; i +=3) { 203 reg = registers[i + 0]; 204 and_mask = registers[i + 1]; 205 or_mask = registers[i + 2]; 206 207 if (and_mask == 0xffffffff) { 208 tmp = or_mask; 209 } else { 210 tmp = RREG32(reg); 211 tmp &= ~and_mask; 212 tmp |= or_mask; 213 } 214 WREG32(reg, tmp); 215 } 216 } 217 218 void radeon_pci_config_reset(struct radeon_device *rdev) 219 { 220 pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA); 221 } 222 223 /** 224 * radeon_surface_init - Clear GPU surface registers. 225 * 226 * @rdev: radeon_device pointer 227 * 228 * Clear GPU surface registers (r1xx-r5xx). 229 */ 230 void radeon_surface_init(struct radeon_device *rdev) 231 { 232 /* FIXME: check this out */ 233 if (rdev->family < CHIP_R600) { 234 int i; 235 236 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 237 if (rdev->surface_regs[i].bo) 238 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); 239 else 240 radeon_clear_surface_reg(rdev, i); 241 } 242 /* enable surfaces */ 243 WREG32(RADEON_SURFACE_CNTL, 0); 244 } 245 } 246 247 /* 248 * GPU scratch registers helpers function. 249 */ 250 /** 251 * radeon_scratch_init - Init scratch register driver information. 252 * 253 * @rdev: radeon_device pointer 254 * 255 * Init CP scratch register driver information (r1xx-r5xx) 256 */ 257 void radeon_scratch_init(struct radeon_device *rdev) 258 { 259 int i; 260 261 /* FIXME: check this out */ 262 if (rdev->family < CHIP_R300) { 263 rdev->scratch.num_reg = 5; 264 } else { 265 rdev->scratch.num_reg = 7; 266 } 267 rdev->scratch.reg_base = RADEON_SCRATCH_REG0; 268 for (i = 0; i < rdev->scratch.num_reg; i++) { 269 rdev->scratch.free[i] = true; 270 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 271 } 272 } 273 274 /** 275 * radeon_scratch_get - Allocate a scratch register 276 * 277 * @rdev: radeon_device pointer 278 * @reg: scratch register mmio offset 279 * 280 * Allocate a CP scratch register for use by the driver (all asics). 281 * Returns 0 on success or -EINVAL on failure. 282 */ 283 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) 284 { 285 int i; 286 287 for (i = 0; i < rdev->scratch.num_reg; i++) { 288 if (rdev->scratch.free[i]) { 289 rdev->scratch.free[i] = false; 290 *reg = rdev->scratch.reg[i]; 291 return 0; 292 } 293 } 294 return -EINVAL; 295 } 296 297 /** 298 * radeon_scratch_free - Free a scratch register 299 * 300 * @rdev: radeon_device pointer 301 * @reg: scratch register mmio offset 302 * 303 * Free a CP scratch register allocated for use by the driver (all asics) 304 */ 305 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) 306 { 307 int i; 308 309 for (i = 0; i < rdev->scratch.num_reg; i++) { 310 if (rdev->scratch.reg[i] == reg) { 311 rdev->scratch.free[i] = true; 312 return; 313 } 314 } 315 } 316 317 /* 318 * GPU doorbell aperture helpers function. 319 */ 320 /** 321 * radeon_doorbell_init - Init doorbell driver information. 322 * 323 * @rdev: radeon_device pointer 324 * 325 * Init doorbell driver information (CIK) 326 * Returns 0 on success, error on failure. 327 */ 328 static int radeon_doorbell_init(struct radeon_device *rdev) 329 { 330 /* doorbell bar mapping */ 331 rdev->doorbell.base = pci_resource_start(rdev->pdev, 2); 332 rdev->doorbell.size = pci_resource_len(rdev->pdev, 2); 333 334 rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS); 335 if (rdev->doorbell.num_doorbells == 0) 336 return -EINVAL; 337 338 rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32)); 339 if (rdev->doorbell.ptr == NULL) { 340 return -ENOMEM; 341 } 342 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base); 343 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size); 344 345 memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used)); 346 347 return 0; 348 } 349 350 /** 351 * radeon_doorbell_fini - Tear down doorbell driver information. 352 * 353 * @rdev: radeon_device pointer 354 * 355 * Tear down doorbell driver information (CIK) 356 */ 357 static void radeon_doorbell_fini(struct radeon_device *rdev) 358 { 359 iounmap(rdev->doorbell.ptr); 360 rdev->doorbell.ptr = NULL; 361 } 362 363 /** 364 * radeon_doorbell_get - Allocate a doorbell entry 365 * 366 * @rdev: radeon_device pointer 367 * @doorbell: doorbell index 368 * 369 * Allocate a doorbell for use by the driver (all asics). 370 * Returns 0 on success or -EINVAL on failure. 371 */ 372 int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell) 373 { 374 unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells); 375 if (offset < rdev->doorbell.num_doorbells) { 376 __set_bit(offset, rdev->doorbell.used); 377 *doorbell = offset; 378 return 0; 379 } else { 380 return -EINVAL; 381 } 382 } 383 384 /** 385 * radeon_doorbell_free - Free a doorbell entry 386 * 387 * @rdev: radeon_device pointer 388 * @doorbell: doorbell index 389 * 390 * Free a doorbell allocated for use by the driver (all asics) 391 */ 392 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell) 393 { 394 if (doorbell < rdev->doorbell.num_doorbells) 395 __clear_bit(doorbell, rdev->doorbell.used); 396 } 397 398 /** 399 * radeon_doorbell_get_kfd_info - Report doorbell configuration required to 400 * setup KFD 401 * 402 * @rdev: radeon_device pointer 403 * @aperture_base: output returning doorbell aperture base physical address 404 * @aperture_size: output returning doorbell aperture size in bytes 405 * @start_offset: output returning # of doorbell bytes reserved for radeon. 406 * 407 * Radeon and the KFD share the doorbell aperture. Radeon sets it up, 408 * takes doorbells required for its own rings and reports the setup to KFD. 409 * Radeon reserved doorbells are at the start of the doorbell aperture. 410 */ 411 void radeon_doorbell_get_kfd_info(struct radeon_device *rdev, 412 phys_addr_t *aperture_base, 413 size_t *aperture_size, 414 size_t *start_offset) 415 { 416 /* The first num_doorbells are used by radeon. 417 * KFD takes whatever's left in the aperture. */ 418 if (rdev->doorbell.size > rdev->doorbell.num_doorbells * sizeof(u32)) { 419 *aperture_base = rdev->doorbell.base; 420 *aperture_size = rdev->doorbell.size; 421 *start_offset = rdev->doorbell.num_doorbells * sizeof(u32); 422 } else { 423 *aperture_base = 0; 424 *aperture_size = 0; 425 *start_offset = 0; 426 } 427 } 428 429 /* 430 * radeon_wb_*() 431 * Writeback is the the method by which the the GPU updates special pages 432 * in memory with the status of certain GPU events (fences, ring pointers, 433 * etc.). 434 */ 435 436 /** 437 * radeon_wb_disable - Disable Writeback 438 * 439 * @rdev: radeon_device pointer 440 * 441 * Disables Writeback (all asics). Used for suspend. 442 */ 443 void radeon_wb_disable(struct radeon_device *rdev) 444 { 445 rdev->wb.enabled = false; 446 } 447 448 /** 449 * radeon_wb_fini - Disable Writeback and free memory 450 * 451 * @rdev: radeon_device pointer 452 * 453 * Disables Writeback and frees the Writeback memory (all asics). 454 * Used at driver shutdown. 455 */ 456 void radeon_wb_fini(struct radeon_device *rdev) 457 { 458 radeon_wb_disable(rdev); 459 if (rdev->wb.wb_obj) { 460 if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) { 461 radeon_bo_kunmap(rdev->wb.wb_obj); 462 radeon_bo_unpin(rdev->wb.wb_obj); 463 radeon_bo_unreserve(rdev->wb.wb_obj); 464 } 465 radeon_bo_unref(&rdev->wb.wb_obj); 466 rdev->wb.wb = NULL; 467 rdev->wb.wb_obj = NULL; 468 } 469 } 470 471 /** 472 * radeon_wb_init- Init Writeback driver info and allocate memory 473 * 474 * @rdev: radeon_device pointer 475 * 476 * Disables Writeback and frees the Writeback memory (all asics). 477 * Used at driver startup. 478 * Returns 0 on success or an -error on failure. 479 */ 480 int radeon_wb_init(struct radeon_device *rdev) 481 { 482 int r; 483 void *wb_ptr = NULL; 484 485 if (rdev->wb.wb_obj == NULL) { 486 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, 487 RADEON_GEM_DOMAIN_GTT, 0, NULL, NULL, 488 &rdev->wb.wb_obj); 489 if (r) { 490 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); 491 return r; 492 } 493 r = radeon_bo_reserve(rdev->wb.wb_obj, false); 494 if (unlikely(r != 0)) { 495 radeon_wb_fini(rdev); 496 return r; 497 } 498 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, 499 (u64 *)&rdev->wb.gpu_addr); 500 if (r) { 501 radeon_bo_unreserve(rdev->wb.wb_obj); 502 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); 503 radeon_wb_fini(rdev); 504 return r; 505 } 506 wb_ptr = &rdev->wb.wb; 507 r = radeon_bo_kmap(rdev->wb.wb_obj, wb_ptr); 508 radeon_bo_unreserve(rdev->wb.wb_obj); 509 if (r) { 510 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); 511 radeon_wb_fini(rdev); 512 return r; 513 } 514 } 515 516 /* clear wb memory */ 517 memset(*(void **)wb_ptr, 0, RADEON_GPU_PAGE_SIZE); 518 /* disable event_write fences */ 519 rdev->wb.use_event = false; 520 /* disabled via module param */ 521 if (radeon_no_wb == 1) { 522 rdev->wb.enabled = false; 523 } else { 524 if (rdev->flags & RADEON_IS_AGP) { 525 /* often unreliable on AGP */ 526 rdev->wb.enabled = false; 527 } else if (rdev->family < CHIP_R300) { 528 /* often unreliable on pre-r300 */ 529 rdev->wb.enabled = false; 530 } else { 531 rdev->wb.enabled = true; 532 /* event_write fences are only available on r600+ */ 533 if (rdev->family >= CHIP_R600) { 534 rdev->wb.use_event = true; 535 } 536 } 537 } 538 /* always use writeback/events on NI, APUs */ 539 if (rdev->family >= CHIP_PALM) { 540 rdev->wb.enabled = true; 541 rdev->wb.use_event = true; 542 } 543 544 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis"); 545 546 return 0; 547 } 548 549 /** 550 * radeon_vram_location - try to find VRAM location 551 * @rdev: radeon device structure holding all necessary informations 552 * @mc: memory controller structure holding memory informations 553 * @base: base address at which to put VRAM 554 * 555 * Function will place try to place VRAM at base address provided 556 * as parameter (which is so far either PCI aperture address or 557 * for IGP TOM base address). 558 * 559 * If there is not enough space to fit the unvisible VRAM in the 32bits 560 * address space then we limit the VRAM size to the aperture. 561 * 562 * If we are using AGP and if the AGP aperture doesn't allow us to have 563 * room for all the VRAM than we restrict the VRAM to the PCI aperture 564 * size and print a warning. 565 * 566 * This function will never fails, worst case are limiting VRAM. 567 * 568 * Note: GTT start, end, size should be initialized before calling this 569 * function on AGP platform. 570 * 571 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, 572 * this shouldn't be a problem as we are using the PCI aperture as a reference. 573 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but 574 * not IGP. 575 * 576 * Note: we use mc_vram_size as on some board we need to program the mc to 577 * cover the whole aperture even if VRAM size is inferior to aperture size 578 * Novell bug 204882 + along with lots of ubuntu ones 579 * 580 * Note: when limiting vram it's safe to overwritte real_vram_size because 581 * we are not in case where real_vram_size is inferior to mc_vram_size (ie 582 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu 583 * ones) 584 * 585 * Note: IGP TOM addr should be the same as the aperture addr, we don't 586 * explicitly check for that thought. 587 * 588 * FIXME: when reducing VRAM size align new size on power of 2. 589 */ 590 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) 591 { 592 uint64_t limit = (uint64_t)radeon_vram_limit << 20; 593 594 mc->vram_start = base; 595 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) { 596 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 597 mc->real_vram_size = mc->aper_size; 598 mc->mc_vram_size = mc->aper_size; 599 } 600 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 601 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { 602 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 603 mc->real_vram_size = mc->aper_size; 604 mc->mc_vram_size = mc->aper_size; 605 } 606 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 607 if (limit && limit < mc->real_vram_size) 608 mc->real_vram_size = limit; 609 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 610 mc->mc_vram_size >> 20, mc->vram_start, 611 mc->vram_end, mc->real_vram_size >> 20); 612 } 613 614 /** 615 * radeon_gtt_location - try to find GTT location 616 * @rdev: radeon device structure holding all necessary informations 617 * @mc: memory controller structure holding memory informations 618 * 619 * Function will place try to place GTT before or after VRAM. 620 * 621 * If GTT size is bigger than space left then we ajust GTT size. 622 * Thus function will never fails. 623 * 624 * FIXME: when reducing GTT size align new size on power of 2. 625 */ 626 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 627 { 628 u64 size_af, size_bf; 629 630 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; 631 size_bf = mc->vram_start & ~mc->gtt_base_align; 632 if (size_bf > size_af) { 633 if (mc->gtt_size > size_bf) { 634 dev_warn(rdev->dev, "limiting GTT\n"); 635 mc->gtt_size = size_bf; 636 } 637 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; 638 } else { 639 if (mc->gtt_size > size_af) { 640 dev_warn(rdev->dev, "limiting GTT\n"); 641 mc->gtt_size = size_af; 642 } 643 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; 644 } 645 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; 646 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", 647 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); 648 } 649 650 /* 651 * GPU helpers function. 652 */ 653 654 /** 655 * radeon_device_is_virtual - check if we are running is a virtual environment 656 * 657 * Check if the asic has been passed through to a VM (all asics). 658 * Used at driver startup. 659 * Returns true if virtual or false if not. 660 */ 661 bool radeon_device_is_virtual(void); 662 bool radeon_device_is_virtual(void) 663 { 664 #ifdef CONFIG_X86 665 return boot_cpu_has(X86_FEATURE_HYPERVISOR); 666 #else 667 return false; 668 #endif 669 } 670 671 /** 672 * radeon_card_posted - check if the hw has already been initialized 673 * 674 * @rdev: radeon_device pointer 675 * 676 * Check if the asic has been initialized (all asics). 677 * Used at driver startup. 678 * Returns true if initialized or false if not. 679 */ 680 bool radeon_card_posted(struct radeon_device *rdev) 681 { 682 uint32_t reg; 683 684 /* for pass through, always force asic_init for CI */ 685 if (rdev->family >= CHIP_BONAIRE && 686 radeon_device_is_virtual()) 687 return false; 688 689 #ifdef DUMBBELL_WIP 690 /* required for EFI mode on macbook2,1 which uses an r5xx asic */ 691 if (efi_enabled(EFI_BOOT) && 692 (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && 693 (rdev->family < CHIP_R600)) 694 return false; 695 #endif /* DUMBBELL_WIP */ 696 697 if (ASIC_IS_NODCE(rdev)) 698 goto check_memsize; 699 700 /* first check CRTCs */ 701 if (ASIC_IS_DCE4(rdev)) { 702 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | 703 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 704 if (rdev->num_crtc >= 4) { 705 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | 706 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 707 } 708 if (rdev->num_crtc >= 6) { 709 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | 710 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 711 } 712 if (reg & EVERGREEN_CRTC_MASTER_EN) 713 return true; 714 } else if (ASIC_IS_AVIVO(rdev)) { 715 reg = RREG32(AVIVO_D1CRTC_CONTROL) | 716 RREG32(AVIVO_D2CRTC_CONTROL); 717 if (reg & AVIVO_CRTC_EN) { 718 return true; 719 } 720 } else { 721 reg = RREG32(RADEON_CRTC_GEN_CNTL) | 722 RREG32(RADEON_CRTC2_GEN_CNTL); 723 if (reg & RADEON_CRTC_EN) { 724 return true; 725 } 726 } 727 728 check_memsize: 729 /* then check MEM_SIZE, in case the crtcs are off */ 730 if (rdev->family >= CHIP_R600) 731 reg = RREG32(R600_CONFIG_MEMSIZE); 732 else 733 reg = RREG32(RADEON_CONFIG_MEMSIZE); 734 735 if (reg) 736 return true; 737 738 return false; 739 740 } 741 742 /** 743 * radeon_update_bandwidth_info - update display bandwidth params 744 * 745 * @rdev: radeon_device pointer 746 * 747 * Used when sclk/mclk are switched or display modes are set. 748 * params are used to calculate display watermarks (all asics) 749 */ 750 void radeon_update_bandwidth_info(struct radeon_device *rdev) 751 { 752 fixed20_12 a; 753 u32 sclk = rdev->pm.current_sclk; 754 u32 mclk = rdev->pm.current_mclk; 755 756 /* sclk/mclk in Mhz */ 757 a.full = dfixed_const(100); 758 rdev->pm.sclk.full = dfixed_const(sclk); 759 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); 760 rdev->pm.mclk.full = dfixed_const(mclk); 761 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); 762 763 if (rdev->flags & RADEON_IS_IGP) { 764 a.full = dfixed_const(16); 765 /* core_bandwidth = sclk(Mhz) * 16 */ 766 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); 767 } 768 } 769 770 /** 771 * radeon_boot_test_post_card - check and possibly initialize the hw 772 * 773 * @rdev: radeon_device pointer 774 * 775 * Check if the asic is initialized and if not, attempt to initialize 776 * it (all asics). 777 * Returns true if initialized or false if not. 778 */ 779 bool radeon_boot_test_post_card(struct radeon_device *rdev) 780 { 781 if (radeon_card_posted(rdev)) 782 return true; 783 784 if (rdev->bios) { 785 DRM_INFO("GPU not posted. posting now...\n"); 786 if (rdev->is_atom_bios) 787 atom_asic_init(rdev->mode_info.atom_context); 788 else 789 radeon_combios_asic_init(rdev->ddev); 790 return true; 791 } else { 792 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 793 return false; 794 } 795 } 796 797 /** 798 * radeon_dummy_page_init - init dummy page used by the driver 799 * 800 * @rdev: radeon_device pointer 801 * 802 * Allocate the dummy page used by the driver (all asics). 803 * This dummy page is used by the driver as a filler for gart entries 804 * when pages are taken out of the GART 805 * Returns 0 on sucess, -ENOMEM on failure. 806 */ 807 int radeon_dummy_page_init(struct radeon_device *rdev) 808 { 809 if (rdev->dummy_page.dmah) 810 return 0; 811 rdev->dummy_page.dmah = drm_pci_alloc(rdev->ddev, PAGE_SIZE, PAGE_SIZE); 812 if (rdev->dummy_page.dmah == NULL) 813 return -ENOMEM; 814 rdev->dummy_page.addr = (dma_addr_t)rdev->dummy_page.dmah->busaddr; 815 return 0; 816 } 817 818 /** 819 * radeon_dummy_page_fini - free dummy page used by the driver 820 * 821 * @rdev: radeon_device pointer 822 * 823 * Frees the dummy page used by the driver (all asics). 824 */ 825 void radeon_dummy_page_fini(struct radeon_device *rdev) 826 { 827 if (rdev->dummy_page.dmah == NULL) 828 return; 829 drm_pci_free(rdev->ddev, rdev->dummy_page.dmah); 830 rdev->dummy_page.addr = 0; 831 rdev->dummy_page.dmah = NULL; 832 } 833 834 835 /* ATOM accessor methods */ 836 /* 837 * ATOM is an interpreted byte code stored in tables in the vbios. The 838 * driver registers callbacks to access registers and the interpreter 839 * in the driver parses the tables and executes then to program specific 840 * actions (set display modes, asic init, etc.). See radeon_atombios.c, 841 * atombios.h, and atom.c 842 */ 843 844 /** 845 * cail_pll_read - read PLL register 846 * 847 * @info: atom card_info pointer 848 * @reg: PLL register offset 849 * 850 * Provides a PLL register accessor for the atom interpreter (r4xx+). 851 * Returns the value of the PLL register. 852 */ 853 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) 854 { 855 struct radeon_device *rdev = info->dev->dev_private; 856 uint32_t r; 857 858 r = rdev->pll_rreg(rdev, reg); 859 return r; 860 } 861 862 /** 863 * cail_pll_write - write PLL register 864 * 865 * @info: atom card_info pointer 866 * @reg: PLL register offset 867 * @val: value to write to the pll register 868 * 869 * Provides a PLL register accessor for the atom interpreter (r4xx+). 870 */ 871 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) 872 { 873 struct radeon_device *rdev = info->dev->dev_private; 874 875 rdev->pll_wreg(rdev, reg, val); 876 } 877 878 /** 879 * cail_mc_read - read MC (Memory Controller) register 880 * 881 * @info: atom card_info pointer 882 * @reg: MC register offset 883 * 884 * Provides an MC register accessor for the atom interpreter (r4xx+). 885 * Returns the value of the MC register. 886 */ 887 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) 888 { 889 struct radeon_device *rdev = info->dev->dev_private; 890 uint32_t r; 891 892 r = rdev->mc_rreg(rdev, reg); 893 return r; 894 } 895 896 /** 897 * cail_mc_write - write MC (Memory Controller) register 898 * 899 * @info: atom card_info pointer 900 * @reg: MC register offset 901 * @val: value to write to the pll register 902 * 903 * Provides a MC register accessor for the atom interpreter (r4xx+). 904 */ 905 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) 906 { 907 struct radeon_device *rdev = info->dev->dev_private; 908 909 rdev->mc_wreg(rdev, reg, val); 910 } 911 912 /** 913 * cail_reg_write - write MMIO register 914 * 915 * @info: atom card_info pointer 916 * @reg: MMIO register offset 917 * @val: value to write to the pll register 918 * 919 * Provides a MMIO register accessor for the atom interpreter (r4xx+). 920 */ 921 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) 922 { 923 struct radeon_device *rdev = info->dev->dev_private; 924 925 WREG32(reg*4, val); 926 } 927 928 /** 929 * cail_reg_read - read MMIO register 930 * 931 * @info: atom card_info pointer 932 * @reg: MMIO register offset 933 * 934 * Provides an MMIO register accessor for the atom interpreter (r4xx+). 935 * Returns the value of the MMIO register. 936 */ 937 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) 938 { 939 struct radeon_device *rdev = info->dev->dev_private; 940 uint32_t r; 941 942 r = RREG32(reg*4); 943 return r; 944 } 945 946 /** 947 * cail_ioreg_write - write IO register 948 * 949 * @info: atom card_info pointer 950 * @reg: IO register offset 951 * @val: value to write to the pll register 952 * 953 * Provides a IO register accessor for the atom interpreter (r4xx+). 954 */ 955 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) 956 { 957 struct radeon_device *rdev = info->dev->dev_private; 958 959 WREG32_IO(reg*4, val); 960 } 961 962 /** 963 * cail_ioreg_read - read IO register 964 * 965 * @info: atom card_info pointer 966 * @reg: IO register offset 967 * 968 * Provides an IO register accessor for the atom interpreter (r4xx+). 969 * Returns the value of the IO register. 970 */ 971 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) 972 { 973 struct radeon_device *rdev = info->dev->dev_private; 974 uint32_t r; 975 976 r = RREG32_IO(reg*4); 977 return r; 978 } 979 980 /** 981 * radeon_atombios_init - init the driver info and callbacks for atombios 982 * 983 * @rdev: radeon_device pointer 984 * 985 * Initializes the driver info and register access callbacks for the 986 * ATOM interpreter (r4xx+). 987 * Returns 0 on sucess, -ENOMEM on failure. 988 * Called at driver startup. 989 */ 990 int radeon_atombios_init(struct radeon_device *rdev) 991 { 992 struct card_info *atom_card_info = 993 kzalloc(sizeof(struct card_info), GFP_KERNEL); 994 995 if (!atom_card_info) 996 return -ENOMEM; 997 998 rdev->mode_info.atom_card_info = atom_card_info; 999 atom_card_info->dev = rdev->ddev; 1000 atom_card_info->reg_read = cail_reg_read; 1001 atom_card_info->reg_write = cail_reg_write; 1002 /* needed for iio ops */ 1003 if (rdev->rio_mem) { 1004 atom_card_info->ioreg_read = cail_ioreg_read; 1005 atom_card_info->ioreg_write = cail_ioreg_write; 1006 } else { 1007 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); 1008 atom_card_info->ioreg_read = cail_reg_read; 1009 atom_card_info->ioreg_write = cail_reg_write; 1010 } 1011 atom_card_info->mc_read = cail_mc_read; 1012 atom_card_info->mc_write = cail_mc_write; 1013 atom_card_info->pll_read = cail_pll_read; 1014 atom_card_info->pll_write = cail_pll_write; 1015 1016 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); 1017 if (!rdev->mode_info.atom_context) { 1018 radeon_atombios_fini(rdev); 1019 return -ENOMEM; 1020 } 1021 1022 lockinit(&rdev->mode_info.atom_context->mutex, "rmiacmtx", 0, LK_CANRECURSE); 1023 lockinit(&rdev->mode_info.atom_context->scratch_mutex, "rmiacsmtx", 0, LK_CANRECURSE); 1024 radeon_atom_initialize_bios_scratch_regs(rdev->ddev); 1025 atom_allocate_fb_scratch(rdev->mode_info.atom_context); 1026 return 0; 1027 } 1028 1029 /** 1030 * radeon_atombios_fini - free the driver info and callbacks for atombios 1031 * 1032 * @rdev: radeon_device pointer 1033 * 1034 * Frees the driver info and register access callbacks for the ATOM 1035 * interpreter (r4xx+). 1036 * Called at driver shutdown. 1037 */ 1038 void radeon_atombios_fini(struct radeon_device *rdev) 1039 { 1040 if (rdev->mode_info.atom_context) { 1041 kfree(rdev->mode_info.atom_context->scratch); 1042 } 1043 kfree(rdev->mode_info.atom_context); 1044 rdev->mode_info.atom_context = NULL; 1045 kfree(rdev->mode_info.atom_card_info); 1046 rdev->mode_info.atom_card_info = NULL; 1047 } 1048 1049 /* COMBIOS */ 1050 /* 1051 * COMBIOS is the bios format prior to ATOM. It provides 1052 * command tables similar to ATOM, but doesn't have a unified 1053 * parser. See radeon_combios.c 1054 */ 1055 1056 /** 1057 * radeon_combios_init - init the driver info for combios 1058 * 1059 * @rdev: radeon_device pointer 1060 * 1061 * Initializes the driver info for combios (r1xx-r3xx). 1062 * Returns 0 on sucess. 1063 * Called at driver startup. 1064 */ 1065 int radeon_combios_init(struct radeon_device *rdev) 1066 { 1067 radeon_combios_initialize_bios_scratch_regs(rdev->ddev); 1068 return 0; 1069 } 1070 1071 /** 1072 * radeon_combios_fini - free the driver info for combios 1073 * 1074 * @rdev: radeon_device pointer 1075 * 1076 * Frees the driver info for combios (r1xx-r3xx). 1077 * Called at driver shutdown. 1078 */ 1079 void radeon_combios_fini(struct radeon_device *rdev) 1080 { 1081 } 1082 1083 #ifdef DUMBBELL_WIP 1084 /* if we get transitioned to only one device, take VGA back */ 1085 /** 1086 * radeon_vga_set_decode - enable/disable vga decode 1087 * 1088 * @cookie: radeon_device pointer 1089 * @state: enable/disable vga decode 1090 * 1091 * Enable/disable vga decode (all asics). 1092 * Returns VGA resource flags. 1093 */ 1094 static unsigned int radeon_vga_set_decode(void *cookie, bool state) 1095 { 1096 struct radeon_device *rdev = cookie; 1097 radeon_vga_set_state(rdev, state); 1098 if (state) 1099 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | 1100 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 1101 else 1102 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 1103 } 1104 #endif /* DUMBBELL_WIP */ 1105 1106 /** 1107 * radeon_check_pot_argument - check that argument is a power of two 1108 * 1109 * @arg: value to check 1110 * 1111 * Validates that a certain argument is a power of two (all asics). 1112 * Returns true if argument is valid. 1113 */ 1114 static bool radeon_check_pot_argument(int arg) 1115 { 1116 return (arg & (arg - 1)) == 0; 1117 } 1118 1119 /** 1120 * Determine a sensible default GART size according to ASIC family. 1121 * 1122 * @family ASIC family name 1123 */ 1124 static int radeon_gart_size_auto(enum radeon_family family) 1125 { 1126 /* default to a larger gart size on newer asics */ 1127 if (family >= CHIP_TAHITI) 1128 return 2048; 1129 else if (family >= CHIP_RV770) 1130 return 1024; 1131 else 1132 return 512; 1133 } 1134 1135 /** 1136 * radeon_check_arguments - validate module params 1137 * 1138 * @rdev: radeon_device pointer 1139 * 1140 * Validates certain module parameters and updates 1141 * the associated values used by the driver (all asics). 1142 */ 1143 static void radeon_check_arguments(struct radeon_device *rdev) 1144 { 1145 /* vramlimit must be a power of two */ 1146 if (!radeon_check_pot_argument(radeon_vram_limit)) { 1147 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", 1148 radeon_vram_limit); 1149 radeon_vram_limit = 0; 1150 } 1151 1152 if (radeon_gart_size == -1) { 1153 radeon_gart_size = radeon_gart_size_auto(rdev->family); 1154 } 1155 /* gtt size must be power of two and greater or equal to 32M */ 1156 if (radeon_gart_size < 32) { 1157 dev_warn(rdev->dev, "gart size (%d) too small\n", 1158 radeon_gart_size); 1159 radeon_gart_size = radeon_gart_size_auto(rdev->family); 1160 } else if (!radeon_check_pot_argument(radeon_gart_size)) { 1161 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", 1162 radeon_gart_size); 1163 radeon_gart_size = radeon_gart_size_auto(rdev->family); 1164 } 1165 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20; 1166 1167 /* AGP mode can only be -1, 1, 2, 4, 8 */ 1168 switch (radeon_agpmode) { 1169 case -1: 1170 case 0: 1171 case 1: 1172 case 2: 1173 case 4: 1174 case 8: 1175 break; 1176 default: 1177 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " 1178 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); 1179 radeon_agpmode = 0; 1180 break; 1181 } 1182 1183 if (!radeon_check_pot_argument(radeon_vm_size)) { 1184 dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n", 1185 radeon_vm_size); 1186 radeon_vm_size = 4; 1187 } 1188 1189 if (radeon_vm_size < 1) { 1190 dev_warn(rdev->dev, "VM size (%d) too small, min is 1GB\n", 1191 radeon_vm_size); 1192 radeon_vm_size = 4; 1193 } 1194 1195 /* 1196 * Max GPUVM size for Cayman, SI and CI are 40 bits. 1197 */ 1198 if (radeon_vm_size > 1024) { 1199 dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n", 1200 radeon_vm_size); 1201 radeon_vm_size = 4; 1202 } 1203 1204 /* defines number of bits in page table versus page directory, 1205 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the 1206 * page table and the remaining bits are in the page directory */ 1207 if (radeon_vm_block_size == -1) { 1208 1209 /* Total bits covered by PD + PTs */ 1210 unsigned bits = ilog2(radeon_vm_size) + 18; 1211 1212 /* Make sure the PD is 4K in size up to 8GB address space. 1213 Above that split equal between PD and PTs */ 1214 if (radeon_vm_size <= 8) 1215 radeon_vm_block_size = bits - 9; 1216 else 1217 radeon_vm_block_size = (bits + 3) / 2; 1218 1219 } else if (radeon_vm_block_size < 9) { 1220 dev_warn(rdev->dev, "VM page table size (%d) too small\n", 1221 radeon_vm_block_size); 1222 radeon_vm_block_size = 9; 1223 } 1224 1225 if (radeon_vm_block_size > 24 || 1226 (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) { 1227 dev_warn(rdev->dev, "VM page table size (%d) too large\n", 1228 radeon_vm_block_size); 1229 radeon_vm_block_size = 9; 1230 } 1231 } 1232 1233 /** 1234 * radeon_switcheroo_set_state - set switcheroo state 1235 * 1236 * @pdev: pci dev pointer 1237 * @state: vga_switcheroo state 1238 * 1239 * Callback for the switcheroo driver. Suspends or resumes the 1240 * the asics before or after it is powered up using ACPI methods. 1241 */ 1242 #ifdef DUMBBELL_WIP 1243 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) 1244 { 1245 struct drm_device *dev = pci_get_drvdata(pdev); 1246 struct radeon_device *rdev = dev->dev_private; 1247 1248 if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF) 1249 return; 1250 1251 if (state == VGA_SWITCHEROO_ON) { 1252 unsigned d3_delay = dev->pdev->d3_delay; 1253 1254 printk(KERN_INFO "radeon: switched on\n"); 1255 /* don't suspend or resume card normally */ 1256 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1257 1258 if (d3_delay < 20 && (rdev->px_quirk_flags & RADEON_PX_QUIRK_LONG_WAKEUP)) 1259 dev->pdev->d3_delay = 20; 1260 1261 radeon_resume_kms(dev, true, true); 1262 1263 dev->pdev->d3_delay = d3_delay; 1264 1265 dev->switch_power_state = DRM_SWITCH_POWER_ON; 1266 drm_kms_helper_poll_enable(dev); 1267 } else { 1268 printk(KERN_INFO "radeon: switched off\n"); 1269 drm_kms_helper_poll_disable(dev); 1270 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1271 radeon_suspend_kms(dev, true, true, false); 1272 dev->switch_power_state = DRM_SWITCH_POWER_OFF; 1273 } 1274 } 1275 #endif /* DUMBBELL_WIP */ 1276 1277 /** 1278 * radeon_switcheroo_can_switch - see if switcheroo state can change 1279 * 1280 * @pdev: pci dev pointer 1281 * 1282 * Callback for the switcheroo driver. Check of the switcheroo 1283 * state can be changed. 1284 * Returns true if the state can be changed, false if not. 1285 */ 1286 #ifdef DUMBBELL_WIP 1287 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev) 1288 { 1289 struct drm_device *dev = pci_get_drvdata(pdev); 1290 1291 /* 1292 * FIXME: open_count is protected by drm_global_mutex but that would lead to 1293 * locking inversion with the driver load path. And the access here is 1294 * completely racy anyway. So don't bother with locking for now. 1295 */ 1296 return dev->open_count == 0; 1297 } 1298 1299 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = { 1300 .set_gpu_state = radeon_switcheroo_set_state, 1301 .reprobe = NULL, 1302 .can_switch = radeon_switcheroo_can_switch, 1303 }; 1304 #endif /* DUMBBELL_WIP */ 1305 1306 /** 1307 * radeon_device_init - initialize the driver 1308 * 1309 * @rdev: radeon_device pointer 1310 * @pdev: drm dev pointer 1311 * @pdev: pci dev pointer 1312 * @flags: driver flags 1313 * 1314 * Initializes the driver info and hw (all asics). 1315 * Returns 0 for success or an error on failure. 1316 * Called at driver startup. 1317 */ 1318 int radeon_device_init(struct radeon_device *rdev, 1319 struct drm_device *ddev, 1320 struct pci_dev *pdev, 1321 uint32_t flags) 1322 { 1323 int r, i; 1324 int dma_bits; 1325 #ifdef PM_TODO 1326 bool runtime = false; 1327 #endif 1328 1329 rdev->shutdown = false; 1330 rdev->dev = &pdev->dev; 1331 rdev->ddev = ddev; 1332 rdev->pdev = pdev; 1333 rdev->flags = flags; 1334 rdev->family = flags & RADEON_FAMILY_MASK; 1335 rdev->is_atom_bios = false; 1336 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; 1337 rdev->mc.gtt_size = 512 * 1024 * 1024; 1338 rdev->accel_working = false; 1339 rdev->fictitious_range_registered = false; 1340 /* set up ring ids */ 1341 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1342 rdev->ring[i].idx = i; 1343 } 1344 rdev->fence_context = fence_context_alloc(RADEON_NUM_RINGS); 1345 1346 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", 1347 radeon_family_name[rdev->family], pdev->vendor, pdev->device, 1348 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); 1349 1350 /* mutex initialization are all done here so we 1351 * can recall function without having locking issues */ 1352 lockinit(&rdev->ring_lock, "drdrl", 0, LK_CANRECURSE); 1353 lockinit(&rdev->dc_hw_i2c_mutex, "drddi2cm", 0, LK_CANRECURSE); 1354 atomic_set(&rdev->ih.lock, 0); 1355 lockinit(&rdev->gem.mutex, "radeon_gemmtx", 0, LK_CANRECURSE); 1356 lockinit(&rdev->pm.mutex, "drdpmm", 0, LK_CANRECURSE); 1357 lockinit(&rdev->gpu_clock_mutex, "radeon_clockmtx", 0, LK_CANRECURSE); 1358 lockinit(&rdev->srbm_mutex, "radeon_srbm_mutex", 0, LK_CANRECURSE); 1359 lockinit(&rdev->grbm_idx_mutex, "drgim", 0, LK_CANRECURSE); 1360 lockinit(&rdev->pm.mclk_lock, "drpmml", 0, LK_CANRECURSE); 1361 lockinit(&rdev->exclusive_lock, "drdel", 0, LK_CANRECURSE); 1362 init_waitqueue_head(&rdev->irq.vblank_queue); 1363 lockinit(&rdev->mn_lock, "drrml", 0, LK_CANRECURSE); 1364 r = radeon_gem_init(rdev); 1365 if (r) 1366 return r; 1367 1368 radeon_check_arguments(rdev); 1369 /* Adjust VM size here. 1370 * Max GPUVM size for cayman+ is 40 bits. 1371 */ 1372 rdev->vm_manager.max_pfn = radeon_vm_size << 18; 1373 1374 /* Set asic functions */ 1375 r = radeon_asic_init(rdev); 1376 if (r) 1377 return r; 1378 1379 /* all of the newer IGP chips have an internal gart 1380 * However some rs4xx report as AGP, so remove that here. 1381 */ 1382 if ((rdev->family >= CHIP_RS400) && 1383 (rdev->flags & RADEON_IS_IGP)) { 1384 rdev->flags &= ~RADEON_IS_AGP; 1385 } 1386 1387 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { 1388 radeon_agp_disable(rdev); 1389 } 1390 1391 /* Set the internal MC address mask 1392 * This is the max address of the GPU's 1393 * internal address space. 1394 */ 1395 if (rdev->family >= CHIP_CAYMAN) 1396 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1397 else if (rdev->family >= CHIP_CEDAR) 1398 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */ 1399 else 1400 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */ 1401 1402 /* set DMA mask + need_dma32 flags. 1403 * PCIE - can handle 40-bits. 1404 * IGP - can handle 40-bits 1405 * AGP - generally dma32 is safest 1406 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 1407 */ 1408 rdev->need_dma32 = false; 1409 if (rdev->flags & RADEON_IS_AGP) 1410 rdev->need_dma32 = true; 1411 if ((rdev->flags & RADEON_IS_PCI) && 1412 (rdev->family <= CHIP_RS740)) 1413 rdev->need_dma32 = true; 1414 1415 dma_bits = rdev->need_dma32 ? 32 : 40; 1416 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 1417 if (r) { 1418 rdev->need_dma32 = true; 1419 dma_bits = 32; 1420 printk(KERN_WARNING "radeon: No suitable DMA available.\n"); 1421 } 1422 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 1423 if (r) { 1424 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32)); 1425 printk(KERN_WARNING "radeon: No coherent DMA available.\n"); 1426 } 1427 1428 /* Registers mapping */ 1429 /* TODO: block userspace mapping of io register */ 1430 spin_init(&rdev->mmio_idx_lock, "radeon_mpio"); 1431 spin_init(&rdev->smc_idx_lock, "radeon_smc"); 1432 spin_init(&rdev->pll_idx_lock, "radeon_pll"); 1433 spin_init(&rdev->mc_idx_lock, "radeon_mc"); 1434 spin_init(&rdev->pcie_idx_lock, "radeon_pcie"); 1435 spin_init(&rdev->pciep_idx_lock, "radeon_pciep"); 1436 spin_init(&rdev->pif_idx_lock, "radeon_pif"); 1437 spin_init(&rdev->cg_idx_lock, "radeon_cg"); 1438 spin_init(&rdev->uvd_idx_lock, "radeon_uvd"); 1439 spin_init(&rdev->rcu_idx_lock, "radeon_rcu"); 1440 spin_init(&rdev->didt_idx_lock, "radeon_didt"); 1441 spin_init(&rdev->end_idx_lock, "radeon_end"); 1442 if (rdev->family >= CHIP_BONAIRE) { 1443 rdev->rmmio_base = pci_resource_start(rdev->pdev, 5); 1444 rdev->rmmio_size = pci_resource_len(rdev->pdev, 5); 1445 } else { 1446 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); 1447 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); 1448 } 1449 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); 1450 if (rdev->rmmio == NULL) { 1451 return -ENOMEM; 1452 } 1453 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); 1454 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); 1455 1456 /* doorbell bar mapping */ 1457 if (rdev->family >= CHIP_BONAIRE) 1458 radeon_doorbell_init(rdev); 1459 1460 /* io port mapping */ 1461 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 1462 uint32_t data; 1463 1464 data = pci_read_config(rdev->dev->bsddev, PCIR_BAR(i), 4); 1465 if (PCI_BAR_IO(data)) { 1466 rdev->rio_rid = PCIR_BAR(i); 1467 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i); 1468 rdev->rio_mem = bus_alloc_resource_any(rdev->dev->bsddev, 1469 SYS_RES_IOPORT, &rdev->rio_rid, 1470 RF_ACTIVE | RF_SHAREABLE); 1471 break; 1472 } 1473 } 1474 if (rdev->rio_mem == NULL) 1475 DRM_ERROR("Unable to find PCI I/O BAR\n"); 1476 1477 if (rdev->flags & RADEON_IS_PX) 1478 radeon_device_handle_px_quirks(rdev); 1479 1480 #ifdef DUMBBELL_WIP 1481 /* if we have > 1 VGA cards, then disable the radeon VGA resources */ 1482 /* this will fail for cards that aren't VGA class devices, just 1483 * ignore it */ 1484 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); 1485 1486 if (rdev->flags & RADEON_IS_PX) 1487 runtime = true; 1488 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime); 1489 if (runtime) 1490 vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain); 1491 #endif 1492 1493 r = radeon_init(rdev); 1494 if (r) 1495 goto failed; 1496 1497 r = radeon_gem_debugfs_init(rdev); 1498 if (r) { 1499 DRM_ERROR("registering gem debugfs failed (%d).\n", r); 1500 } 1501 1502 r = radeon_mst_debugfs_init(rdev); 1503 if (r) { 1504 DRM_ERROR("registering mst debugfs failed (%d).\n", r); 1505 } 1506 1507 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { 1508 /* Acceleration not working on AGP card try again 1509 * with fallback to PCI or PCIE GART 1510 */ 1511 radeon_asic_reset(rdev); 1512 radeon_fini(rdev); 1513 radeon_agp_disable(rdev); 1514 r = radeon_init(rdev); 1515 if (r) 1516 goto failed; 1517 } 1518 1519 r = radeon_ib_ring_tests(rdev); 1520 if (r) 1521 DRM_ERROR("ib ring test failed (%d).\n", r); 1522 1523 DRM_INFO("%s: Taking over the fictitious range 0x%lx-0x%llx\n", 1524 __func__, (uintmax_t)rdev->mc.aper_base, 1525 (uintmax_t)rdev->mc.aper_base + rdev->mc.visible_vram_size); 1526 r = vm_phys_fictitious_reg_range( 1527 rdev->mc.aper_base, 1528 rdev->mc.aper_base + rdev->mc.visible_vram_size, 1529 VM_MEMATTR_WRITE_COMBINING); 1530 if (r != 0) { 1531 DRM_ERROR("Failed to register fictitious range " 1532 "0x%lx-0x%llx (%d).\n", (uintmax_t)rdev->mc.aper_base, 1533 (uintmax_t)rdev->mc.aper_base + rdev->mc.visible_vram_size, r); 1534 return (-r); 1535 } 1536 rdev->fictitious_range_registered = true; 1537 1538 /* 1539 * Turks/Thames GPU will freeze whole laptop if DPM is not restarted 1540 * after the CP ring have chew one packet at least. Hence here we stop 1541 * and restart DPM after the radeon_ib_ring_tests(). 1542 */ 1543 if (rdev->pm.dpm_enabled && 1544 (rdev->pm.pm_method == PM_METHOD_DPM) && 1545 (rdev->family == CHIP_TURKS) && 1546 (rdev->flags & RADEON_IS_MOBILITY)) { 1547 mutex_lock(&rdev->pm.mutex); 1548 radeon_dpm_disable(rdev); 1549 radeon_dpm_enable(rdev); 1550 mutex_unlock(&rdev->pm.mutex); 1551 } 1552 1553 if ((radeon_testing & 1)) { 1554 if (rdev->accel_working) 1555 radeon_test_moves(rdev); 1556 else 1557 DRM_INFO("radeon: acceleration disabled, skipping move tests\n"); 1558 } 1559 if ((radeon_testing & 2)) { 1560 if (rdev->accel_working) 1561 radeon_test_syncing(rdev); 1562 else 1563 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n"); 1564 } 1565 if (radeon_benchmarking) { 1566 if (rdev->accel_working) 1567 radeon_benchmark(rdev, radeon_benchmarking); 1568 else 1569 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n"); 1570 } 1571 rdev->dummy_page.entry = radeon_gart_get_page_entry(rdev->dummy_page.addr, 1572 RADEON_GART_PAGE_DUMMY); 1573 return 0; 1574 1575 failed: 1576 #if 0 1577 if (runtime) 1578 vga_switcheroo_fini_domain_pm_ops(rdev->dev); 1579 #endif 1580 return r; 1581 } 1582 1583 static void radeon_debugfs_remove_files(struct radeon_device *rdev); 1584 1585 /** 1586 * radeon_device_fini - tear down the driver 1587 * 1588 * @rdev: radeon_device pointer 1589 * 1590 * Tear down the driver info (all asics). 1591 * Called at driver shutdown. 1592 */ 1593 void radeon_device_fini(struct radeon_device *rdev) 1594 { 1595 DRM_INFO("radeon: finishing device.\n"); 1596 rdev->shutdown = true; 1597 /* evict vram memory */ 1598 radeon_bo_evict_vram(rdev); 1599 1600 if (rdev->fictitious_range_registered) { 1601 vm_phys_fictitious_unreg_range( 1602 rdev->mc.aper_base, 1603 rdev->mc.aper_base + rdev->mc.visible_vram_size); 1604 } 1605 1606 radeon_fini(rdev); 1607 #ifdef DUMBBELL_WIP 1608 vga_switcheroo_unregister_client(rdev->pdev); 1609 if (rdev->flags & RADEON_IS_PX) 1610 vga_switcheroo_fini_domain_pm_ops(rdev->dev); 1611 vga_client_register(rdev->pdev, NULL, NULL, NULL); 1612 #endif /* DUMBBELL_WIP */ 1613 if (rdev->rio_mem) 1614 bus_release_resource(rdev->dev->bsddev, SYS_RES_IOPORT, rdev->rio_rid, 1615 rdev->rio_mem); 1616 rdev->rio_mem = NULL; 1617 iounmap(rdev->rmmio); 1618 rdev->rmmio = NULL; 1619 if (rdev->family >= CHIP_BONAIRE) 1620 radeon_doorbell_fini(rdev); 1621 radeon_debugfs_remove_files(rdev); 1622 } 1623 1624 1625 /* 1626 * Suspend & resume. 1627 */ 1628 /** 1629 * radeon_suspend_kms - initiate device suspend 1630 * 1631 * @pdev: drm dev pointer 1632 * @state: suspend state 1633 * 1634 * Puts the hw in the suspend state (all asics). 1635 * Returns 0 for success or an error on failure. 1636 * Called at driver suspend. 1637 */ 1638 int radeon_suspend_kms(struct drm_device *dev, bool suspend, 1639 bool fbcon, bool freeze) 1640 { 1641 struct radeon_device *rdev; 1642 struct drm_crtc *crtc; 1643 struct drm_connector *connector; 1644 int i, r; 1645 1646 if (dev == NULL || dev->dev_private == NULL) { 1647 return -ENODEV; 1648 } 1649 1650 rdev = dev->dev_private; 1651 1652 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1653 return 0; 1654 1655 drm_kms_helper_poll_disable(dev); 1656 1657 drm_modeset_lock_all(dev); 1658 /* turn off display hw */ 1659 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1660 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 1661 } 1662 drm_modeset_unlock_all(dev); 1663 1664 /* unpin the front buffers and cursors */ 1665 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1666 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1667 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->primary->fb); 1668 struct radeon_bo *robj; 1669 1670 if (radeon_crtc->cursor_bo) { 1671 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); 1672 r = radeon_bo_reserve(robj, false); 1673 if (r == 0) { 1674 radeon_bo_unpin(robj); 1675 radeon_bo_unreserve(robj); 1676 } 1677 } 1678 1679 if (rfb == NULL || rfb->obj == NULL) { 1680 continue; 1681 } 1682 robj = gem_to_radeon_bo(rfb->obj); 1683 /* don't unpin kernel fb objects */ 1684 if (!radeon_fbdev_robj_is_fb(rdev, robj)) { 1685 r = radeon_bo_reserve(robj, false); 1686 if (r == 0) { 1687 radeon_bo_unpin(robj); 1688 radeon_bo_unreserve(robj); 1689 } 1690 } 1691 } 1692 /* evict vram memory */ 1693 radeon_bo_evict_vram(rdev); 1694 1695 /* wait for gpu to finish processing current batch */ 1696 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1697 r = radeon_fence_wait_empty(rdev, i); 1698 if (r) { 1699 /* delay GPU reset to resume */ 1700 radeon_fence_driver_force_completion(rdev, i); 1701 } 1702 } 1703 1704 radeon_save_bios_scratch_regs(rdev); 1705 1706 radeon_suspend(rdev); 1707 radeon_hpd_fini(rdev); 1708 /* evict remaining vram memory */ 1709 radeon_bo_evict_vram(rdev); 1710 1711 radeon_agp_suspend(rdev); 1712 1713 pci_save_state(device_get_parent(rdev->dev->bsddev)); 1714 #ifdef DUMBBELL_WIP 1715 if (freeze && rdev->family >= CHIP_CEDAR) { 1716 rdev->asic->asic_reset(rdev, true); 1717 pci_restore_state(dev->pdev); 1718 } else if (suspend) { 1719 /* Shut down the device */ 1720 pci_disable_device(dev->pdev); 1721 pci_set_powerstate(dev->dev->bsddev, PCI_POWERSTATE_D3); 1722 } 1723 #endif 1724 1725 if (fbcon) { 1726 #ifdef DUMBBELL_WIP 1727 console_lock(); 1728 #endif /* DUMBBELL_WIP */ 1729 radeon_fbdev_set_suspend(rdev, 1); 1730 #ifdef DUMBBELL_WIP 1731 console_unlock(); 1732 #endif /* DUMBBELL_WIP */ 1733 } 1734 rdev->dummy_page.entry = radeon_gart_get_page_entry(rdev->dummy_page.addr, 1735 RADEON_GART_PAGE_DUMMY); 1736 return 0; 1737 } 1738 1739 /** 1740 * radeon_resume_kms - initiate device resume 1741 * 1742 * @pdev: drm dev pointer 1743 * 1744 * Bring the hw back to operating state (all asics). 1745 * Returns 0 for success or an error on failure. 1746 * Called at driver resume. 1747 */ 1748 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon) 1749 { 1750 struct drm_connector *connector; 1751 struct radeon_device *rdev = dev->dev_private; 1752 struct drm_crtc *crtc; 1753 int r; 1754 1755 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1756 return 0; 1757 1758 #ifdef DUMBBELL_WIP 1759 if (fbcon) { 1760 console_lock(); 1761 } 1762 #endif /* DUMBBELL_WIP */ 1763 if (resume) { 1764 #ifdef DUMBBELL_WIP 1765 pci_set_power_state(dev->pdev, PCI_D0); 1766 pci_restore_state(dev->pdev); 1767 if (pci_enable_device(dev->pdev)) { 1768 if (fbcon) 1769 console_unlock(); 1770 return -1; 1771 } 1772 #endif /* DUMBBELL_WIP */ 1773 } 1774 /* resume AGP if in use */ 1775 radeon_agp_resume(rdev); 1776 radeon_resume(rdev); 1777 1778 r = radeon_ib_ring_tests(rdev); 1779 if (r) 1780 DRM_ERROR("ib ring test failed (%d).\n", r); 1781 1782 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 1783 /* do dpm late init */ 1784 r = radeon_pm_late_init(rdev); 1785 if (r) { 1786 rdev->pm.dpm_enabled = false; 1787 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1788 } 1789 } else { 1790 /* resume old pm late */ 1791 radeon_pm_resume(rdev); 1792 } 1793 1794 radeon_restore_bios_scratch_regs(rdev); 1795 1796 /* pin cursors */ 1797 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1798 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1799 1800 if (radeon_crtc->cursor_bo) { 1801 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); 1802 r = radeon_bo_reserve(robj, false); 1803 if (r == 0) { 1804 /* Only 27 bit offset for legacy cursor */ 1805 r = radeon_bo_pin_restricted(robj, 1806 RADEON_GEM_DOMAIN_VRAM, 1807 ASIC_IS_AVIVO(rdev) ? 1808 0 : 1 << 27, 1809 (u64 *)&radeon_crtc->cursor_addr); 1810 if (r != 0) 1811 DRM_ERROR("Failed to pin cursor BO (%d)\n", r); 1812 radeon_bo_unreserve(robj); 1813 } 1814 } 1815 } 1816 1817 /* init dig PHYs, disp eng pll */ 1818 if (rdev->is_atom_bios) { 1819 radeon_atom_encoder_init(rdev); 1820 radeon_atom_disp_eng_pll_init(rdev); 1821 /* turn on the BL */ 1822 if (rdev->mode_info.bl_encoder) { 1823 u8 bl_level = radeon_get_backlight_level(rdev, 1824 rdev->mode_info.bl_encoder); 1825 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, 1826 bl_level); 1827 } 1828 } 1829 /* reset hpd state */ 1830 radeon_hpd_init(rdev); 1831 /* blat the mode back in */ 1832 if (fbcon) { 1833 drm_helper_resume_force_mode(dev); 1834 /* turn on display hw */ 1835 drm_modeset_lock_all(dev); 1836 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1837 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 1838 } 1839 drm_modeset_unlock_all(dev); 1840 } 1841 1842 drm_kms_helper_poll_enable(dev); 1843 1844 /* set the power state here in case we are a PX system or headless */ 1845 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 1846 radeon_pm_compute_clocks(rdev); 1847 1848 if (fbcon) { 1849 radeon_fbdev_set_suspend(rdev, 0); 1850 #ifdef DUMBBELL_WIP 1851 console_unlock(); 1852 #endif /* DUMBBELL_WIP */ 1853 } 1854 1855 return 0; 1856 } 1857 1858 /** 1859 * radeon_gpu_reset - reset the asic 1860 * 1861 * @rdev: radeon device pointer 1862 * 1863 * Attempt the reset the GPU if it has hung (all asics). 1864 * Returns 0 for success or an error on failure. 1865 */ 1866 int radeon_gpu_reset(struct radeon_device *rdev) 1867 { 1868 unsigned ring_sizes[RADEON_NUM_RINGS]; 1869 uint32_t *ring_data[RADEON_NUM_RINGS]; 1870 1871 bool saved = false; 1872 1873 int i, r; 1874 int resched; 1875 1876 down_write(&rdev->exclusive_lock); 1877 1878 if (!rdev->needs_reset) { 1879 up_write(&rdev->exclusive_lock); 1880 return 0; 1881 } 1882 1883 atomic_inc(&rdev->gpu_reset_counter); 1884 1885 radeon_save_bios_scratch_regs(rdev); 1886 /* block TTM */ 1887 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); 1888 radeon_suspend(rdev); 1889 radeon_hpd_fini(rdev); 1890 1891 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1892 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i], 1893 &ring_data[i]); 1894 if (ring_sizes[i]) { 1895 saved = true; 1896 dev_info(rdev->dev, "Saved %d dwords of commands " 1897 "on ring %d.\n", ring_sizes[i], i); 1898 } 1899 } 1900 1901 r = radeon_asic_reset(rdev); 1902 if (!r) { 1903 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n"); 1904 radeon_resume(rdev); 1905 } 1906 1907 radeon_restore_bios_scratch_regs(rdev); 1908 1909 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1910 if (!r && ring_data[i]) { 1911 radeon_ring_restore(rdev, &rdev->ring[i], 1912 ring_sizes[i], ring_data[i]); 1913 } else { 1914 radeon_fence_driver_force_completion(rdev, i); 1915 kfree(ring_data[i]); 1916 } 1917 } 1918 1919 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 1920 /* do dpm late init */ 1921 r = radeon_pm_late_init(rdev); 1922 if (r) { 1923 rdev->pm.dpm_enabled = false; 1924 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1925 } 1926 } else { 1927 /* resume old pm late */ 1928 radeon_pm_resume(rdev); 1929 } 1930 1931 /* init dig PHYs, disp eng pll */ 1932 if (rdev->is_atom_bios) { 1933 radeon_atom_encoder_init(rdev); 1934 radeon_atom_disp_eng_pll_init(rdev); 1935 /* turn on the BL */ 1936 if (rdev->mode_info.bl_encoder) { 1937 u8 bl_level = radeon_get_backlight_level(rdev, 1938 rdev->mode_info.bl_encoder); 1939 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, 1940 bl_level); 1941 } 1942 } 1943 /* reset hpd state */ 1944 radeon_hpd_init(rdev); 1945 1946 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); 1947 1948 rdev->in_reset = true; 1949 rdev->needs_reset = false; 1950 1951 #if 0 1952 downgrade_write(&rdev->exclusive_lock); 1953 #endif 1954 1955 drm_helper_resume_force_mode(rdev->ddev); 1956 1957 /* set the power state here in case we are a PX system or headless */ 1958 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 1959 radeon_pm_compute_clocks(rdev); 1960 1961 if (!r) { 1962 r = radeon_ib_ring_tests(rdev); 1963 if (r && saved) 1964 r = -EAGAIN; 1965 } else { 1966 /* bad news, how to tell it to userspace ? */ 1967 dev_info(rdev->dev, "GPU reset failed\n"); 1968 } 1969 1970 rdev->needs_reset = r == -EAGAIN; 1971 rdev->in_reset = false; 1972 1973 up_read(&rdev->exclusive_lock); 1974 return r; 1975 } 1976 1977 1978 /* 1979 * Debugfs 1980 */ 1981 int radeon_debugfs_add_files(struct radeon_device *rdev, 1982 struct drm_info_list *files, 1983 unsigned nfiles) 1984 { 1985 unsigned i; 1986 1987 for (i = 0; i < rdev->debugfs_count; i++) { 1988 if (rdev->debugfs[i].files == files) { 1989 /* Already registered */ 1990 return 0; 1991 } 1992 } 1993 1994 i = rdev->debugfs_count + 1; 1995 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) { 1996 DRM_ERROR("Reached maximum number of debugfs components.\n"); 1997 DRM_ERROR("Report so we increase " 1998 "RADEON_DEBUGFS_MAX_COMPONENTS.\n"); 1999 return -EINVAL; 2000 } 2001 rdev->debugfs[rdev->debugfs_count].files = files; 2002 rdev->debugfs[rdev->debugfs_count].num_files = nfiles; 2003 rdev->debugfs_count = i; 2004 #if defined(CONFIG_DEBUG_FS) 2005 drm_debugfs_create_files(files, nfiles, 2006 rdev->ddev->control->debugfs_root, 2007 rdev->ddev->control); 2008 drm_debugfs_create_files(files, nfiles, 2009 rdev->ddev->primary->debugfs_root, 2010 rdev->ddev->primary); 2011 #endif 2012 return 0; 2013 } 2014 2015 static void radeon_debugfs_remove_files(struct radeon_device *rdev) 2016 { 2017 #if defined(CONFIG_DEBUG_FS) 2018 unsigned i; 2019 2020 for (i = 0; i < rdev->debugfs_count; i++) { 2021 drm_debugfs_remove_files(rdev->debugfs[i].files, 2022 rdev->debugfs[i].num_files, 2023 rdev->ddev->control); 2024 drm_debugfs_remove_files(rdev->debugfs[i].files, 2025 rdev->debugfs[i].num_files, 2026 rdev->ddev->primary); 2027 } 2028 #endif 2029 } 2030