1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/console.h> 29 #include <drm/drmP.h> 30 #include "drm/drm_legacy.h" /* for drm_dma_handle_t */ 31 #include <drm/drm_crtc_helper.h> 32 #include <drm/radeon_drm.h> 33 #include <linux/vgaarb.h> 34 #include <linux/vga_switcheroo.h> 35 #include "radeon_reg.h" 36 #include "radeon.h" 37 #include "atom.h" 38 39 #include <asm/cpufeature.h> 40 41 static const char radeon_family_name[][16] = { 42 "R100", 43 "RV100", 44 "RS100", 45 "RV200", 46 "RS200", 47 "R200", 48 "RV250", 49 "RS300", 50 "RV280", 51 "R300", 52 "R350", 53 "RV350", 54 "RV380", 55 "R420", 56 "R423", 57 "RV410", 58 "RS400", 59 "RS480", 60 "RS600", 61 "RS690", 62 "RS740", 63 "RV515", 64 "R520", 65 "RV530", 66 "RV560", 67 "RV570", 68 "R580", 69 "R600", 70 "RV610", 71 "RV630", 72 "RV670", 73 "RV620", 74 "RV635", 75 "RS780", 76 "RS880", 77 "RV770", 78 "RV730", 79 "RV710", 80 "RV740", 81 "CEDAR", 82 "REDWOOD", 83 "JUNIPER", 84 "CYPRESS", 85 "HEMLOCK", 86 "PALM", 87 "SUMO", 88 "SUMO2", 89 "BARTS", 90 "TURKS", 91 "CAICOS", 92 "CAYMAN", 93 "ARUBA", 94 "TAHITI", 95 "PITCAIRN", 96 "VERDE", 97 "OLAND", 98 "HAINAN", 99 "BONAIRE", 100 "KAVERI", 101 "KABINI", 102 "HAWAII", 103 "MULLINS", 104 "LAST", 105 }; 106 107 #define RADEON_PX_QUIRK_DISABLE_PX (1 << 0) 108 #define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1) 109 110 struct radeon_px_quirk { 111 u32 chip_vendor; 112 u32 chip_device; 113 u32 subsys_vendor; 114 u32 subsys_device; 115 u32 px_quirk_flags; 116 }; 117 118 static struct radeon_px_quirk radeon_px_quirk_list[] = { 119 /* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m) 120 * https://bugzilla.kernel.org/show_bug.cgi?id=74551 121 */ 122 { PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX }, 123 /* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU 124 * https://bugzilla.kernel.org/show_bug.cgi?id=51381 125 */ 126 { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX }, 127 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU 128 * https://bugzilla.kernel.org/show_bug.cgi?id=51381 129 */ 130 { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX }, 131 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU 132 * https://bugs.freedesktop.org/show_bug.cgi?id=101491 133 */ 134 { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX }, 135 /* macbook pro 8.2 */ 136 { PCI_VENDOR_ID_ATI, 0x6741, PCI_VENDOR_ID_APPLE, 0x00e2, RADEON_PX_QUIRK_LONG_WAKEUP }, 137 { 0, 0, 0, 0, 0 }, 138 }; 139 140 bool radeon_is_px(struct drm_device *dev) 141 { 142 struct radeon_device *rdev = dev->dev_private; 143 144 if (rdev->flags & RADEON_IS_PX) 145 return true; 146 return false; 147 } 148 149 static void radeon_device_handle_px_quirks(struct radeon_device *rdev) 150 { 151 struct radeon_px_quirk *p = radeon_px_quirk_list; 152 153 /* Apply PX quirks */ 154 while (p && p->chip_device != 0) { 155 if (rdev->pdev->vendor == p->chip_vendor && 156 rdev->pdev->device == p->chip_device && 157 rdev->pdev->subsystem_vendor == p->subsys_vendor && 158 rdev->pdev->subsystem_device == p->subsys_device) { 159 rdev->px_quirk_flags = p->px_quirk_flags; 160 break; 161 } 162 ++p; 163 } 164 165 if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX) 166 rdev->flags &= ~RADEON_IS_PX; 167 } 168 169 /** 170 * radeon_program_register_sequence - program an array of registers. 171 * 172 * @rdev: radeon_device pointer 173 * @registers: pointer to the register array 174 * @array_size: size of the register array 175 * 176 * Programs an array or registers with and and or masks. 177 * This is a helper for setting golden registers. 178 */ 179 void radeon_program_register_sequence(struct radeon_device *rdev, 180 const u32 *registers, 181 const u32 array_size) 182 { 183 u32 tmp, reg, and_mask, or_mask; 184 int i; 185 186 if (array_size % 3) 187 return; 188 189 for (i = 0; i < array_size; i +=3) { 190 reg = registers[i + 0]; 191 and_mask = registers[i + 1]; 192 or_mask = registers[i + 2]; 193 194 if (and_mask == 0xffffffff) { 195 tmp = or_mask; 196 } else { 197 tmp = RREG32(reg); 198 tmp &= ~and_mask; 199 tmp |= or_mask; 200 } 201 WREG32(reg, tmp); 202 } 203 } 204 205 void radeon_pci_config_reset(struct radeon_device *rdev) 206 { 207 pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA); 208 } 209 210 /** 211 * radeon_surface_init - Clear GPU surface registers. 212 * 213 * @rdev: radeon_device pointer 214 * 215 * Clear GPU surface registers (r1xx-r5xx). 216 */ 217 void radeon_surface_init(struct radeon_device *rdev) 218 { 219 /* FIXME: check this out */ 220 if (rdev->family < CHIP_R600) { 221 int i; 222 223 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 224 if (rdev->surface_regs[i].bo) 225 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); 226 else 227 radeon_clear_surface_reg(rdev, i); 228 } 229 /* enable surfaces */ 230 WREG32(RADEON_SURFACE_CNTL, 0); 231 } 232 } 233 234 /* 235 * GPU scratch registers helpers function. 236 */ 237 /** 238 * radeon_scratch_init - Init scratch register driver information. 239 * 240 * @rdev: radeon_device pointer 241 * 242 * Init CP scratch register driver information (r1xx-r5xx) 243 */ 244 void radeon_scratch_init(struct radeon_device *rdev) 245 { 246 int i; 247 248 /* FIXME: check this out */ 249 if (rdev->family < CHIP_R300) { 250 rdev->scratch.num_reg = 5; 251 } else { 252 rdev->scratch.num_reg = 7; 253 } 254 rdev->scratch.reg_base = RADEON_SCRATCH_REG0; 255 for (i = 0; i < rdev->scratch.num_reg; i++) { 256 rdev->scratch.free[i] = true; 257 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 258 } 259 } 260 261 /** 262 * radeon_scratch_get - Allocate a scratch register 263 * 264 * @rdev: radeon_device pointer 265 * @reg: scratch register mmio offset 266 * 267 * Allocate a CP scratch register for use by the driver (all asics). 268 * Returns 0 on success or -EINVAL on failure. 269 */ 270 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) 271 { 272 int i; 273 274 for (i = 0; i < rdev->scratch.num_reg; i++) { 275 if (rdev->scratch.free[i]) { 276 rdev->scratch.free[i] = false; 277 *reg = rdev->scratch.reg[i]; 278 return 0; 279 } 280 } 281 return -EINVAL; 282 } 283 284 /** 285 * radeon_scratch_free - Free a scratch register 286 * 287 * @rdev: radeon_device pointer 288 * @reg: scratch register mmio offset 289 * 290 * Free a CP scratch register allocated for use by the driver (all asics) 291 */ 292 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) 293 { 294 int i; 295 296 for (i = 0; i < rdev->scratch.num_reg; i++) { 297 if (rdev->scratch.reg[i] == reg) { 298 rdev->scratch.free[i] = true; 299 return; 300 } 301 } 302 } 303 304 /* 305 * GPU doorbell aperture helpers function. 306 */ 307 /** 308 * radeon_doorbell_init - Init doorbell driver information. 309 * 310 * @rdev: radeon_device pointer 311 * 312 * Init doorbell driver information (CIK) 313 * Returns 0 on success, error on failure. 314 */ 315 static int radeon_doorbell_init(struct radeon_device *rdev) 316 { 317 /* doorbell bar mapping */ 318 rdev->doorbell.base = pci_resource_start(rdev->pdev, 2); 319 rdev->doorbell.size = pci_resource_len(rdev->pdev, 2); 320 321 rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS); 322 if (rdev->doorbell.num_doorbells == 0) 323 return -EINVAL; 324 325 rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32)); 326 if (rdev->doorbell.ptr == NULL) { 327 return -ENOMEM; 328 } 329 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base); 330 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size); 331 332 memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used)); 333 334 return 0; 335 } 336 337 /** 338 * radeon_doorbell_fini - Tear down doorbell driver information. 339 * 340 * @rdev: radeon_device pointer 341 * 342 * Tear down doorbell driver information (CIK) 343 */ 344 static void radeon_doorbell_fini(struct radeon_device *rdev) 345 { 346 iounmap(rdev->doorbell.ptr); 347 rdev->doorbell.ptr = NULL; 348 } 349 350 /** 351 * radeon_doorbell_get - Allocate a doorbell entry 352 * 353 * @rdev: radeon_device pointer 354 * @doorbell: doorbell index 355 * 356 * Allocate a doorbell for use by the driver (all asics). 357 * Returns 0 on success or -EINVAL on failure. 358 */ 359 int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell) 360 { 361 unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells); 362 if (offset < rdev->doorbell.num_doorbells) { 363 __set_bit(offset, rdev->doorbell.used); 364 *doorbell = offset; 365 return 0; 366 } else { 367 return -EINVAL; 368 } 369 } 370 371 /** 372 * radeon_doorbell_free - Free a doorbell entry 373 * 374 * @rdev: radeon_device pointer 375 * @doorbell: doorbell index 376 * 377 * Free a doorbell allocated for use by the driver (all asics) 378 */ 379 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell) 380 { 381 if (doorbell < rdev->doorbell.num_doorbells) 382 __clear_bit(doorbell, rdev->doorbell.used); 383 } 384 385 /** 386 * radeon_doorbell_get_kfd_info - Report doorbell configuration required to 387 * setup KFD 388 * 389 * @rdev: radeon_device pointer 390 * @aperture_base: output returning doorbell aperture base physical address 391 * @aperture_size: output returning doorbell aperture size in bytes 392 * @start_offset: output returning # of doorbell bytes reserved for radeon. 393 * 394 * Radeon and the KFD share the doorbell aperture. Radeon sets it up, 395 * takes doorbells required for its own rings and reports the setup to KFD. 396 * Radeon reserved doorbells are at the start of the doorbell aperture. 397 */ 398 void radeon_doorbell_get_kfd_info(struct radeon_device *rdev, 399 phys_addr_t *aperture_base, 400 size_t *aperture_size, 401 size_t *start_offset) 402 { 403 /* The first num_doorbells are used by radeon. 404 * KFD takes whatever's left in the aperture. */ 405 if (rdev->doorbell.size > rdev->doorbell.num_doorbells * sizeof(u32)) { 406 *aperture_base = rdev->doorbell.base; 407 *aperture_size = rdev->doorbell.size; 408 *start_offset = rdev->doorbell.num_doorbells * sizeof(u32); 409 } else { 410 *aperture_base = 0; 411 *aperture_size = 0; 412 *start_offset = 0; 413 } 414 } 415 416 /* 417 * radeon_wb_*() 418 * Writeback is the the method by which the the GPU updates special pages 419 * in memory with the status of certain GPU events (fences, ring pointers, 420 * etc.). 421 */ 422 423 /** 424 * radeon_wb_disable - Disable Writeback 425 * 426 * @rdev: radeon_device pointer 427 * 428 * Disables Writeback (all asics). Used for suspend. 429 */ 430 void radeon_wb_disable(struct radeon_device *rdev) 431 { 432 rdev->wb.enabled = false; 433 } 434 435 /** 436 * radeon_wb_fini - Disable Writeback and free memory 437 * 438 * @rdev: radeon_device pointer 439 * 440 * Disables Writeback and frees the Writeback memory (all asics). 441 * Used at driver shutdown. 442 */ 443 void radeon_wb_fini(struct radeon_device *rdev) 444 { 445 radeon_wb_disable(rdev); 446 if (rdev->wb.wb_obj) { 447 if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) { 448 radeon_bo_kunmap(rdev->wb.wb_obj); 449 radeon_bo_unpin(rdev->wb.wb_obj); 450 radeon_bo_unreserve(rdev->wb.wb_obj); 451 } 452 radeon_bo_unref(&rdev->wb.wb_obj); 453 rdev->wb.wb = NULL; 454 rdev->wb.wb_obj = NULL; 455 } 456 } 457 458 /** 459 * radeon_wb_init- Init Writeback driver info and allocate memory 460 * 461 * @rdev: radeon_device pointer 462 * 463 * Disables Writeback and frees the Writeback memory (all asics). 464 * Used at driver startup. 465 * Returns 0 on success or an -error on failure. 466 */ 467 int radeon_wb_init(struct radeon_device *rdev) 468 { 469 int r; 470 void *wb_ptr = NULL; 471 472 if (rdev->wb.wb_obj == NULL) { 473 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, 474 RADEON_GEM_DOMAIN_GTT, 0, NULL, NULL, 475 &rdev->wb.wb_obj); 476 if (r) { 477 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); 478 return r; 479 } 480 r = radeon_bo_reserve(rdev->wb.wb_obj, false); 481 if (unlikely(r != 0)) { 482 radeon_wb_fini(rdev); 483 return r; 484 } 485 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, 486 (u64 *)&rdev->wb.gpu_addr); 487 if (r) { 488 radeon_bo_unreserve(rdev->wb.wb_obj); 489 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); 490 radeon_wb_fini(rdev); 491 return r; 492 } 493 wb_ptr = &rdev->wb.wb; 494 r = radeon_bo_kmap(rdev->wb.wb_obj, wb_ptr); 495 radeon_bo_unreserve(rdev->wb.wb_obj); 496 if (r) { 497 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); 498 radeon_wb_fini(rdev); 499 return r; 500 } 501 } 502 503 /* clear wb memory */ 504 memset(*(void **)wb_ptr, 0, RADEON_GPU_PAGE_SIZE); 505 /* disable event_write fences */ 506 rdev->wb.use_event = false; 507 /* disabled via module param */ 508 if (radeon_no_wb == 1) { 509 rdev->wb.enabled = false; 510 } else { 511 if (rdev->flags & RADEON_IS_AGP) { 512 /* often unreliable on AGP */ 513 rdev->wb.enabled = false; 514 } else if (rdev->family < CHIP_R300) { 515 /* often unreliable on pre-r300 */ 516 rdev->wb.enabled = false; 517 } else { 518 rdev->wb.enabled = true; 519 /* event_write fences are only available on r600+ */ 520 if (rdev->family >= CHIP_R600) { 521 rdev->wb.use_event = true; 522 } 523 } 524 } 525 /* always use writeback/events on NI, APUs */ 526 if (rdev->family >= CHIP_PALM) { 527 rdev->wb.enabled = true; 528 rdev->wb.use_event = true; 529 } 530 531 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis"); 532 533 return 0; 534 } 535 536 /** 537 * radeon_vram_location - try to find VRAM location 538 * @rdev: radeon device structure holding all necessary informations 539 * @mc: memory controller structure holding memory informations 540 * @base: base address at which to put VRAM 541 * 542 * Function will place try to place VRAM at base address provided 543 * as parameter (which is so far either PCI aperture address or 544 * for IGP TOM base address). 545 * 546 * If there is not enough space to fit the unvisible VRAM in the 32bits 547 * address space then we limit the VRAM size to the aperture. 548 * 549 * If we are using AGP and if the AGP aperture doesn't allow us to have 550 * room for all the VRAM than we restrict the VRAM to the PCI aperture 551 * size and print a warning. 552 * 553 * This function will never fails, worst case are limiting VRAM. 554 * 555 * Note: GTT start, end, size should be initialized before calling this 556 * function on AGP platform. 557 * 558 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, 559 * this shouldn't be a problem as we are using the PCI aperture as a reference. 560 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but 561 * not IGP. 562 * 563 * Note: we use mc_vram_size as on some board we need to program the mc to 564 * cover the whole aperture even if VRAM size is inferior to aperture size 565 * Novell bug 204882 + along with lots of ubuntu ones 566 * 567 * Note: when limiting vram it's safe to overwritte real_vram_size because 568 * we are not in case where real_vram_size is inferior to mc_vram_size (ie 569 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu 570 * ones) 571 * 572 * Note: IGP TOM addr should be the same as the aperture addr, we don't 573 * explicitly check for that thought. 574 * 575 * FIXME: when reducing VRAM size align new size on power of 2. 576 */ 577 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) 578 { 579 uint64_t limit = (uint64_t)radeon_vram_limit << 20; 580 581 mc->vram_start = base; 582 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) { 583 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 584 mc->real_vram_size = mc->aper_size; 585 mc->mc_vram_size = mc->aper_size; 586 } 587 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 588 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { 589 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 590 mc->real_vram_size = mc->aper_size; 591 mc->mc_vram_size = mc->aper_size; 592 } 593 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 594 if (limit && limit < mc->real_vram_size) 595 mc->real_vram_size = limit; 596 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 597 mc->mc_vram_size >> 20, mc->vram_start, 598 mc->vram_end, mc->real_vram_size >> 20); 599 } 600 601 /** 602 * radeon_gtt_location - try to find GTT location 603 * @rdev: radeon device structure holding all necessary informations 604 * @mc: memory controller structure holding memory informations 605 * 606 * Function will place try to place GTT before or after VRAM. 607 * 608 * If GTT size is bigger than space left then we ajust GTT size. 609 * Thus function will never fails. 610 * 611 * FIXME: when reducing GTT size align new size on power of 2. 612 */ 613 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 614 { 615 u64 size_af, size_bf; 616 617 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; 618 size_bf = mc->vram_start & ~mc->gtt_base_align; 619 if (size_bf > size_af) { 620 if (mc->gtt_size > size_bf) { 621 dev_warn(rdev->dev, "limiting GTT\n"); 622 mc->gtt_size = size_bf; 623 } 624 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; 625 } else { 626 if (mc->gtt_size > size_af) { 627 dev_warn(rdev->dev, "limiting GTT\n"); 628 mc->gtt_size = size_af; 629 } 630 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; 631 } 632 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; 633 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", 634 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); 635 } 636 637 /* 638 * GPU helpers function. 639 */ 640 641 /** 642 * radeon_device_is_virtual - check if we are running is a virtual environment 643 * 644 * Check if the asic has been passed through to a VM (all asics). 645 * Used at driver startup. 646 * Returns true if virtual or false if not. 647 */ 648 static bool radeon_device_is_virtual(void) 649 { 650 #ifdef CONFIG_X86 651 return boot_cpu_has(X86_FEATURE_HYPERVISOR); 652 #else 653 return false; 654 #endif 655 } 656 657 /** 658 * radeon_card_posted - check if the hw has already been initialized 659 * 660 * @rdev: radeon_device pointer 661 * 662 * Check if the asic has been initialized (all asics). 663 * Used at driver startup. 664 * Returns true if initialized or false if not. 665 */ 666 bool radeon_card_posted(struct radeon_device *rdev) 667 { 668 uint32_t reg; 669 670 /* for pass through, always force asic_init for CI */ 671 if (rdev->family >= CHIP_BONAIRE && 672 radeon_device_is_virtual()) 673 return false; 674 675 #ifdef DUMBBELL_WIP 676 /* required for EFI mode on macbook2,1 which uses an r5xx asic */ 677 if (efi_enabled(EFI_BOOT) && 678 (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && 679 (rdev->family < CHIP_R600)) 680 return false; 681 #endif /* DUMBBELL_WIP */ 682 683 if (ASIC_IS_NODCE(rdev)) 684 goto check_memsize; 685 686 /* first check CRTCs */ 687 if (ASIC_IS_DCE4(rdev)) { 688 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | 689 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 690 if (rdev->num_crtc >= 4) { 691 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | 692 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 693 } 694 if (rdev->num_crtc >= 6) { 695 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | 696 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 697 } 698 if (reg & EVERGREEN_CRTC_MASTER_EN) 699 return true; 700 } else if (ASIC_IS_AVIVO(rdev)) { 701 reg = RREG32(AVIVO_D1CRTC_CONTROL) | 702 RREG32(AVIVO_D2CRTC_CONTROL); 703 if (reg & AVIVO_CRTC_EN) { 704 return true; 705 } 706 } else { 707 reg = RREG32(RADEON_CRTC_GEN_CNTL) | 708 RREG32(RADEON_CRTC2_GEN_CNTL); 709 if (reg & RADEON_CRTC_EN) { 710 return true; 711 } 712 } 713 714 check_memsize: 715 /* then check MEM_SIZE, in case the crtcs are off */ 716 if (rdev->family >= CHIP_R600) 717 reg = RREG32(R600_CONFIG_MEMSIZE); 718 else 719 reg = RREG32(RADEON_CONFIG_MEMSIZE); 720 721 if (reg) 722 return true; 723 724 return false; 725 726 } 727 728 /** 729 * radeon_update_bandwidth_info - update display bandwidth params 730 * 731 * @rdev: radeon_device pointer 732 * 733 * Used when sclk/mclk are switched or display modes are set. 734 * params are used to calculate display watermarks (all asics) 735 */ 736 void radeon_update_bandwidth_info(struct radeon_device *rdev) 737 { 738 fixed20_12 a; 739 u32 sclk = rdev->pm.current_sclk; 740 u32 mclk = rdev->pm.current_mclk; 741 742 /* sclk/mclk in Mhz */ 743 a.full = dfixed_const(100); 744 rdev->pm.sclk.full = dfixed_const(sclk); 745 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); 746 rdev->pm.mclk.full = dfixed_const(mclk); 747 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); 748 749 if (rdev->flags & RADEON_IS_IGP) { 750 a.full = dfixed_const(16); 751 /* core_bandwidth = sclk(Mhz) * 16 */ 752 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); 753 } 754 } 755 756 /** 757 * radeon_boot_test_post_card - check and possibly initialize the hw 758 * 759 * @rdev: radeon_device pointer 760 * 761 * Check if the asic is initialized and if not, attempt to initialize 762 * it (all asics). 763 * Returns true if initialized or false if not. 764 */ 765 bool radeon_boot_test_post_card(struct radeon_device *rdev) 766 { 767 if (radeon_card_posted(rdev)) 768 return true; 769 770 if (rdev->bios) { 771 DRM_INFO("GPU not posted. posting now...\n"); 772 if (rdev->is_atom_bios) 773 atom_asic_init(rdev->mode_info.atom_context); 774 else 775 radeon_combios_asic_init(rdev->ddev); 776 return true; 777 } else { 778 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 779 return false; 780 } 781 } 782 783 /** 784 * radeon_dummy_page_init - init dummy page used by the driver 785 * 786 * @rdev: radeon_device pointer 787 * 788 * Allocate the dummy page used by the driver (all asics). 789 * This dummy page is used by the driver as a filler for gart entries 790 * when pages are taken out of the GART 791 * Returns 0 on sucess, -ENOMEM on failure. 792 */ 793 int radeon_dummy_page_init(struct radeon_device *rdev) 794 { 795 if (rdev->dummy_page.dmah) 796 return 0; 797 rdev->dummy_page.dmah = drm_pci_alloc(rdev->ddev, PAGE_SIZE, PAGE_SIZE); 798 if (rdev->dummy_page.dmah == NULL) 799 return -ENOMEM; 800 rdev->dummy_page.addr = (dma_addr_t)rdev->dummy_page.dmah->busaddr; 801 return 0; 802 } 803 804 /** 805 * radeon_dummy_page_fini - free dummy page used by the driver 806 * 807 * @rdev: radeon_device pointer 808 * 809 * Frees the dummy page used by the driver (all asics). 810 */ 811 void radeon_dummy_page_fini(struct radeon_device *rdev) 812 { 813 if (rdev->dummy_page.dmah == NULL) 814 return; 815 drm_pci_free(rdev->ddev, rdev->dummy_page.dmah); 816 rdev->dummy_page.addr = 0; 817 rdev->dummy_page.dmah = NULL; 818 } 819 820 821 /* ATOM accessor methods */ 822 /* 823 * ATOM is an interpreted byte code stored in tables in the vbios. The 824 * driver registers callbacks to access registers and the interpreter 825 * in the driver parses the tables and executes then to program specific 826 * actions (set display modes, asic init, etc.). See radeon_atombios.c, 827 * atombios.h, and atom.c 828 */ 829 830 /** 831 * cail_pll_read - read PLL register 832 * 833 * @info: atom card_info pointer 834 * @reg: PLL register offset 835 * 836 * Provides a PLL register accessor for the atom interpreter (r4xx+). 837 * Returns the value of the PLL register. 838 */ 839 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) 840 { 841 struct radeon_device *rdev = info->dev->dev_private; 842 uint32_t r; 843 844 r = rdev->pll_rreg(rdev, reg); 845 return r; 846 } 847 848 /** 849 * cail_pll_write - write PLL register 850 * 851 * @info: atom card_info pointer 852 * @reg: PLL register offset 853 * @val: value to write to the pll register 854 * 855 * Provides a PLL register accessor for the atom interpreter (r4xx+). 856 */ 857 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) 858 { 859 struct radeon_device *rdev = info->dev->dev_private; 860 861 rdev->pll_wreg(rdev, reg, val); 862 } 863 864 /** 865 * cail_mc_read - read MC (Memory Controller) register 866 * 867 * @info: atom card_info pointer 868 * @reg: MC register offset 869 * 870 * Provides an MC register accessor for the atom interpreter (r4xx+). 871 * Returns the value of the MC register. 872 */ 873 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) 874 { 875 struct radeon_device *rdev = info->dev->dev_private; 876 uint32_t r; 877 878 r = rdev->mc_rreg(rdev, reg); 879 return r; 880 } 881 882 /** 883 * cail_mc_write - write MC (Memory Controller) register 884 * 885 * @info: atom card_info pointer 886 * @reg: MC register offset 887 * @val: value to write to the pll register 888 * 889 * Provides a MC register accessor for the atom interpreter (r4xx+). 890 */ 891 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) 892 { 893 struct radeon_device *rdev = info->dev->dev_private; 894 895 rdev->mc_wreg(rdev, reg, val); 896 } 897 898 /** 899 * cail_reg_write - write MMIO register 900 * 901 * @info: atom card_info pointer 902 * @reg: MMIO register offset 903 * @val: value to write to the pll register 904 * 905 * Provides a MMIO register accessor for the atom interpreter (r4xx+). 906 */ 907 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) 908 { 909 struct radeon_device *rdev = info->dev->dev_private; 910 911 WREG32(reg*4, val); 912 } 913 914 /** 915 * cail_reg_read - read MMIO register 916 * 917 * @info: atom card_info pointer 918 * @reg: MMIO register offset 919 * 920 * Provides an MMIO register accessor for the atom interpreter (r4xx+). 921 * Returns the value of the MMIO register. 922 */ 923 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) 924 { 925 struct radeon_device *rdev = info->dev->dev_private; 926 uint32_t r; 927 928 r = RREG32(reg*4); 929 return r; 930 } 931 932 /** 933 * cail_ioreg_write - write IO register 934 * 935 * @info: atom card_info pointer 936 * @reg: IO register offset 937 * @val: value to write to the pll register 938 * 939 * Provides a IO register accessor for the atom interpreter (r4xx+). 940 */ 941 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) 942 { 943 struct radeon_device *rdev = info->dev->dev_private; 944 945 WREG32_IO(reg*4, val); 946 } 947 948 /** 949 * cail_ioreg_read - read IO register 950 * 951 * @info: atom card_info pointer 952 * @reg: IO register offset 953 * 954 * Provides an IO register accessor for the atom interpreter (r4xx+). 955 * Returns the value of the IO register. 956 */ 957 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) 958 { 959 struct radeon_device *rdev = info->dev->dev_private; 960 uint32_t r; 961 962 r = RREG32_IO(reg*4); 963 return r; 964 } 965 966 /** 967 * radeon_atombios_init - init the driver info and callbacks for atombios 968 * 969 * @rdev: radeon_device pointer 970 * 971 * Initializes the driver info and register access callbacks for the 972 * ATOM interpreter (r4xx+). 973 * Returns 0 on sucess, -ENOMEM on failure. 974 * Called at driver startup. 975 */ 976 int radeon_atombios_init(struct radeon_device *rdev) 977 { 978 struct card_info *atom_card_info = 979 kzalloc(sizeof(struct card_info), GFP_KERNEL); 980 981 if (!atom_card_info) 982 return -ENOMEM; 983 984 rdev->mode_info.atom_card_info = atom_card_info; 985 atom_card_info->dev = rdev->ddev; 986 atom_card_info->reg_read = cail_reg_read; 987 atom_card_info->reg_write = cail_reg_write; 988 /* needed for iio ops */ 989 if (rdev->rio_mem) { 990 atom_card_info->ioreg_read = cail_ioreg_read; 991 atom_card_info->ioreg_write = cail_ioreg_write; 992 } else { 993 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); 994 atom_card_info->ioreg_read = cail_reg_read; 995 atom_card_info->ioreg_write = cail_reg_write; 996 } 997 atom_card_info->mc_read = cail_mc_read; 998 atom_card_info->mc_write = cail_mc_write; 999 atom_card_info->pll_read = cail_pll_read; 1000 atom_card_info->pll_write = cail_pll_write; 1001 1002 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); 1003 if (!rdev->mode_info.atom_context) { 1004 radeon_atombios_fini(rdev); 1005 return -ENOMEM; 1006 } 1007 1008 lockinit(&rdev->mode_info.atom_context->mutex, "rmiacmtx", 0, LK_CANRECURSE); 1009 lockinit(&rdev->mode_info.atom_context->scratch_mutex, "rmiacsmtx", 0, LK_CANRECURSE); 1010 radeon_atom_initialize_bios_scratch_regs(rdev->ddev); 1011 atom_allocate_fb_scratch(rdev->mode_info.atom_context); 1012 return 0; 1013 } 1014 1015 /** 1016 * radeon_atombios_fini - free the driver info and callbacks for atombios 1017 * 1018 * @rdev: radeon_device pointer 1019 * 1020 * Frees the driver info and register access callbacks for the ATOM 1021 * interpreter (r4xx+). 1022 * Called at driver shutdown. 1023 */ 1024 void radeon_atombios_fini(struct radeon_device *rdev) 1025 { 1026 if (rdev->mode_info.atom_context) { 1027 kfree(rdev->mode_info.atom_context->scratch); 1028 } 1029 kfree(rdev->mode_info.atom_context); 1030 rdev->mode_info.atom_context = NULL; 1031 kfree(rdev->mode_info.atom_card_info); 1032 rdev->mode_info.atom_card_info = NULL; 1033 } 1034 1035 /* COMBIOS */ 1036 /* 1037 * COMBIOS is the bios format prior to ATOM. It provides 1038 * command tables similar to ATOM, but doesn't have a unified 1039 * parser. See radeon_combios.c 1040 */ 1041 1042 /** 1043 * radeon_combios_init - init the driver info for combios 1044 * 1045 * @rdev: radeon_device pointer 1046 * 1047 * Initializes the driver info for combios (r1xx-r3xx). 1048 * Returns 0 on sucess. 1049 * Called at driver startup. 1050 */ 1051 int radeon_combios_init(struct radeon_device *rdev) 1052 { 1053 radeon_combios_initialize_bios_scratch_regs(rdev->ddev); 1054 return 0; 1055 } 1056 1057 /** 1058 * radeon_combios_fini - free the driver info for combios 1059 * 1060 * @rdev: radeon_device pointer 1061 * 1062 * Frees the driver info for combios (r1xx-r3xx). 1063 * Called at driver shutdown. 1064 */ 1065 void radeon_combios_fini(struct radeon_device *rdev) 1066 { 1067 } 1068 1069 #ifdef DUMBBELL_WIP 1070 /* if we get transitioned to only one device, take VGA back */ 1071 /** 1072 * radeon_vga_set_decode - enable/disable vga decode 1073 * 1074 * @cookie: radeon_device pointer 1075 * @state: enable/disable vga decode 1076 * 1077 * Enable/disable vga decode (all asics). 1078 * Returns VGA resource flags. 1079 */ 1080 static unsigned int radeon_vga_set_decode(void *cookie, bool state) 1081 { 1082 struct radeon_device *rdev = cookie; 1083 radeon_vga_set_state(rdev, state); 1084 if (state) 1085 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | 1086 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 1087 else 1088 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 1089 } 1090 #endif /* DUMBBELL_WIP */ 1091 1092 /** 1093 * radeon_check_pot_argument - check that argument is a power of two 1094 * 1095 * @arg: value to check 1096 * 1097 * Validates that a certain argument is a power of two (all asics). 1098 * Returns true if argument is valid. 1099 */ 1100 static bool radeon_check_pot_argument(int arg) 1101 { 1102 return (arg & (arg - 1)) == 0; 1103 } 1104 1105 /** 1106 * Determine a sensible default GART size according to ASIC family. 1107 * 1108 * @family ASIC family name 1109 */ 1110 static int radeon_gart_size_auto(enum radeon_family family) 1111 { 1112 /* default to a larger gart size on newer asics */ 1113 if (family >= CHIP_TAHITI) 1114 return 2048; 1115 else if (family >= CHIP_RV770) 1116 return 1024; 1117 else 1118 return 512; 1119 } 1120 1121 /** 1122 * radeon_check_arguments - validate module params 1123 * 1124 * @rdev: radeon_device pointer 1125 * 1126 * Validates certain module parameters and updates 1127 * the associated values used by the driver (all asics). 1128 */ 1129 static void radeon_check_arguments(struct radeon_device *rdev) 1130 { 1131 /* vramlimit must be a power of two */ 1132 if (!radeon_check_pot_argument(radeon_vram_limit)) { 1133 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", 1134 radeon_vram_limit); 1135 radeon_vram_limit = 0; 1136 } 1137 1138 if (radeon_gart_size == -1) { 1139 radeon_gart_size = radeon_gart_size_auto(rdev->family); 1140 } 1141 /* gtt size must be power of two and greater or equal to 32M */ 1142 if (radeon_gart_size < 32) { 1143 dev_warn(rdev->dev, "gart size (%d) too small\n", 1144 radeon_gart_size); 1145 radeon_gart_size = radeon_gart_size_auto(rdev->family); 1146 } else if (!radeon_check_pot_argument(radeon_gart_size)) { 1147 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", 1148 radeon_gart_size); 1149 radeon_gart_size = radeon_gart_size_auto(rdev->family); 1150 } 1151 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20; 1152 1153 /* AGP mode can only be -1, 1, 2, 4, 8 */ 1154 switch (radeon_agpmode) { 1155 case -1: 1156 case 0: 1157 case 1: 1158 case 2: 1159 case 4: 1160 case 8: 1161 break; 1162 default: 1163 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " 1164 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); 1165 radeon_agpmode = 0; 1166 break; 1167 } 1168 1169 if (!radeon_check_pot_argument(radeon_vm_size)) { 1170 dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n", 1171 radeon_vm_size); 1172 radeon_vm_size = 4; 1173 } 1174 1175 if (radeon_vm_size < 1) { 1176 dev_warn(rdev->dev, "VM size (%d) to small, min is 1GB\n", 1177 radeon_vm_size); 1178 radeon_vm_size = 4; 1179 } 1180 1181 /* 1182 * Max GPUVM size for Cayman, SI and CI are 40 bits. 1183 */ 1184 if (radeon_vm_size > 1024) { 1185 dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n", 1186 radeon_vm_size); 1187 radeon_vm_size = 4; 1188 } 1189 1190 /* defines number of bits in page table versus page directory, 1191 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the 1192 * page table and the remaining bits are in the page directory */ 1193 if (radeon_vm_block_size == -1) { 1194 1195 /* Total bits covered by PD + PTs */ 1196 unsigned bits = ilog2(radeon_vm_size) + 18; 1197 1198 /* Make sure the PD is 4K in size up to 8GB address space. 1199 Above that split equal between PD and PTs */ 1200 if (radeon_vm_size <= 8) 1201 radeon_vm_block_size = bits - 9; 1202 else 1203 radeon_vm_block_size = (bits + 3) / 2; 1204 1205 } else if (radeon_vm_block_size < 9) { 1206 dev_warn(rdev->dev, "VM page table size (%d) too small\n", 1207 radeon_vm_block_size); 1208 radeon_vm_block_size = 9; 1209 } 1210 1211 if (radeon_vm_block_size > 24 || 1212 (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) { 1213 dev_warn(rdev->dev, "VM page table size (%d) too large\n", 1214 radeon_vm_block_size); 1215 radeon_vm_block_size = 9; 1216 } 1217 } 1218 1219 /** 1220 * radeon_switcheroo_set_state - set switcheroo state 1221 * 1222 * @pdev: pci dev pointer 1223 * @state: vga_switcheroo state 1224 * 1225 * Callback for the switcheroo driver. Suspends or resumes the 1226 * the asics before or after it is powered up using ACPI methods. 1227 */ 1228 #ifdef DUMBBELL_WIP 1229 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) 1230 { 1231 struct drm_device *dev = pci_get_drvdata(pdev); 1232 struct radeon_device *rdev = dev->dev_private; 1233 1234 if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF) 1235 return; 1236 1237 if (state == VGA_SWITCHEROO_ON) { 1238 unsigned d3_delay = dev->pdev->d3_delay; 1239 1240 printk(KERN_INFO "radeon: switched on\n"); 1241 /* don't suspend or resume card normally */ 1242 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1243 1244 if (d3_delay < 20 && (rdev->px_quirk_flags & RADEON_PX_QUIRK_LONG_WAKEUP)) 1245 dev->pdev->d3_delay = 20; 1246 1247 radeon_resume_kms(dev, true, true); 1248 1249 dev->pdev->d3_delay = d3_delay; 1250 1251 dev->switch_power_state = DRM_SWITCH_POWER_ON; 1252 drm_kms_helper_poll_enable(dev); 1253 } else { 1254 printk(KERN_INFO "radeon: switched off\n"); 1255 drm_kms_helper_poll_disable(dev); 1256 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1257 radeon_suspend_kms(dev, true, true); 1258 dev->switch_power_state = DRM_SWITCH_POWER_OFF; 1259 } 1260 } 1261 #endif /* DUMBBELL_WIP */ 1262 1263 /** 1264 * radeon_switcheroo_can_switch - see if switcheroo state can change 1265 * 1266 * @pdev: pci dev pointer 1267 * 1268 * Callback for the switcheroo driver. Check of the switcheroo 1269 * state can be changed. 1270 * Returns true if the state can be changed, false if not. 1271 */ 1272 #ifdef DUMBBELL_WIP 1273 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev) 1274 { 1275 struct drm_device *dev = pci_get_drvdata(pdev); 1276 1277 /* 1278 * FIXME: open_count is protected by drm_global_mutex but that would lead to 1279 * locking inversion with the driver load path. And the access here is 1280 * completely racy anyway. So don't bother with locking for now. 1281 */ 1282 return dev->open_count == 0; 1283 } 1284 1285 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = { 1286 .set_gpu_state = radeon_switcheroo_set_state, 1287 .reprobe = NULL, 1288 .can_switch = radeon_switcheroo_can_switch, 1289 }; 1290 #endif /* DUMBBELL_WIP */ 1291 1292 /** 1293 * radeon_device_init - initialize the driver 1294 * 1295 * @rdev: radeon_device pointer 1296 * @pdev: drm dev pointer 1297 * @pdev: pci dev pointer 1298 * @flags: driver flags 1299 * 1300 * Initializes the driver info and hw (all asics). 1301 * Returns 0 for success or an error on failure. 1302 * Called at driver startup. 1303 */ 1304 int radeon_device_init(struct radeon_device *rdev, 1305 struct drm_device *ddev, 1306 struct pci_dev *pdev, 1307 uint32_t flags) 1308 { 1309 int r, i; 1310 int dma_bits; 1311 #ifdef PM_TODO 1312 bool runtime = false; 1313 #endif 1314 1315 rdev->shutdown = false; 1316 rdev->dev = &pdev->dev; 1317 rdev->ddev = ddev; 1318 rdev->pdev = pdev; 1319 rdev->flags = flags; 1320 rdev->family = flags & RADEON_FAMILY_MASK; 1321 rdev->is_atom_bios = false; 1322 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; 1323 rdev->mc.gtt_size = 512 * 1024 * 1024; 1324 rdev->accel_working = false; 1325 rdev->fictitious_range_registered = false; 1326 /* set up ring ids */ 1327 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1328 rdev->ring[i].idx = i; 1329 } 1330 rdev->fence_context = fence_context_alloc(RADEON_NUM_RINGS); 1331 1332 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n", 1333 radeon_family_name[rdev->family], pdev->vendor, pdev->device, 1334 pdev->subsystem_vendor, pdev->subsystem_device); 1335 1336 /* mutex initialization are all done here so we 1337 * can recall function without having locking issues */ 1338 lockinit(&rdev->ring_lock, "drdrl", 0, LK_CANRECURSE); 1339 lockinit(&rdev->dc_hw_i2c_mutex, "drddi2cm", 0, LK_CANRECURSE); 1340 atomic_set(&rdev->ih.lock, 0); 1341 lockinit(&rdev->gem.mutex, "radeon_gemmtx", 0, LK_CANRECURSE); 1342 lockinit(&rdev->pm.mutex, "drdpmm", 0, LK_CANRECURSE); 1343 lockinit(&rdev->gpu_clock_mutex, "radeon_clockmtx", 0, LK_CANRECURSE); 1344 lockinit(&rdev->srbm_mutex, "radeon_srbm_mutex", 0, LK_CANRECURSE); 1345 lockinit(&rdev->grbm_idx_mutex, "drgim", 0, LK_CANRECURSE); 1346 lockinit(&rdev->pm.mclk_lock, "drpmml", 0, LK_CANRECURSE); 1347 lockinit(&rdev->exclusive_lock, "drdel", 0, LK_CANRECURSE); 1348 init_waitqueue_head(&rdev->irq.vblank_queue); 1349 lockinit(&rdev->mn_lock, "drrml", 0, LK_CANRECURSE); 1350 r = radeon_gem_init(rdev); 1351 if (r) 1352 return r; 1353 1354 radeon_check_arguments(rdev); 1355 /* Adjust VM size here. 1356 * Max GPUVM size for cayman+ is 40 bits. 1357 */ 1358 rdev->vm_manager.max_pfn = radeon_vm_size << 18; 1359 1360 /* Set asic functions */ 1361 r = radeon_asic_init(rdev); 1362 if (r) 1363 return r; 1364 1365 /* all of the newer IGP chips have an internal gart 1366 * However some rs4xx report as AGP, so remove that here. 1367 */ 1368 if ((rdev->family >= CHIP_RS400) && 1369 (rdev->flags & RADEON_IS_IGP)) { 1370 rdev->flags &= ~RADEON_IS_AGP; 1371 } 1372 1373 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { 1374 radeon_agp_disable(rdev); 1375 } 1376 1377 /* Set the internal MC address mask 1378 * This is the max address of the GPU's 1379 * internal address space. 1380 */ 1381 if (rdev->family >= CHIP_CAYMAN) 1382 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1383 else if (rdev->family >= CHIP_CEDAR) 1384 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */ 1385 else 1386 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */ 1387 1388 /* set DMA mask + need_dma32 flags. 1389 * PCIE - can handle 40-bits. 1390 * IGP - can handle 40-bits 1391 * AGP - generally dma32 is safest 1392 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 1393 */ 1394 rdev->need_dma32 = false; 1395 if (rdev->flags & RADEON_IS_AGP) 1396 rdev->need_dma32 = true; 1397 if ((rdev->flags & RADEON_IS_PCI) && 1398 (rdev->family <= CHIP_RS740)) 1399 rdev->need_dma32 = true; 1400 1401 dma_bits = rdev->need_dma32 ? 32 : 40; 1402 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 1403 if (r) { 1404 rdev->need_dma32 = true; 1405 dma_bits = 32; 1406 printk(KERN_WARNING "radeon: No suitable DMA available.\n"); 1407 } 1408 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 1409 if (r) { 1410 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32)); 1411 printk(KERN_WARNING "radeon: No coherent DMA available.\n"); 1412 } 1413 1414 /* Registers mapping */ 1415 /* TODO: block userspace mapping of io register */ 1416 spin_init(&rdev->mmio_idx_lock, "radeon_mpio"); 1417 spin_init(&rdev->smc_idx_lock, "radeon_smc"); 1418 spin_init(&rdev->pll_idx_lock, "radeon_pll"); 1419 spin_init(&rdev->mc_idx_lock, "radeon_mc"); 1420 spin_init(&rdev->pcie_idx_lock, "radeon_pcie"); 1421 spin_init(&rdev->pciep_idx_lock, "radeon_pciep"); 1422 spin_init(&rdev->pif_idx_lock, "radeon_pif"); 1423 spin_init(&rdev->cg_idx_lock, "radeon_cg"); 1424 spin_init(&rdev->uvd_idx_lock, "radeon_uvd"); 1425 spin_init(&rdev->rcu_idx_lock, "radeon_rcu"); 1426 spin_init(&rdev->didt_idx_lock, "radeon_didt"); 1427 spin_init(&rdev->end_idx_lock, "radeon_end"); 1428 if (rdev->family >= CHIP_BONAIRE) { 1429 rdev->rmmio_rid = PCIR_BAR(5); 1430 } else { 1431 rdev->rmmio_rid = PCIR_BAR(2); 1432 } 1433 rdev->rmmio = bus_alloc_resource_any(rdev->dev->bsddev, SYS_RES_MEMORY, 1434 &rdev->rmmio_rid, RF_ACTIVE | RF_SHAREABLE); 1435 if (rdev->rmmio == NULL) { 1436 return -ENOMEM; 1437 } 1438 rdev->rmmio_base = rman_get_start(rdev->rmmio); 1439 rdev->rmmio_size = rman_get_size(rdev->rmmio); 1440 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); 1441 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); 1442 1443 /* doorbell bar mapping */ 1444 if (rdev->family >= CHIP_BONAIRE) 1445 radeon_doorbell_init(rdev); 1446 1447 /* io port mapping */ 1448 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 1449 uint32_t data; 1450 1451 data = pci_read_config(rdev->dev->bsddev, PCIR_BAR(i), 4); 1452 if (PCI_BAR_IO(data)) { 1453 rdev->rio_rid = PCIR_BAR(i); 1454 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i); 1455 rdev->rio_mem = bus_alloc_resource_any(rdev->dev->bsddev, 1456 SYS_RES_IOPORT, &rdev->rio_rid, 1457 RF_ACTIVE | RF_SHAREABLE); 1458 break; 1459 } 1460 } 1461 if (rdev->rio_mem == NULL) 1462 DRM_ERROR("Unable to find PCI I/O BAR\n"); 1463 1464 if (rdev->flags & RADEON_IS_PX) 1465 radeon_device_handle_px_quirks(rdev); 1466 1467 #ifdef DUMBBELL_WIP 1468 /* if we have > 1 VGA cards, then disable the radeon VGA resources */ 1469 /* this will fail for cards that aren't VGA class devices, just 1470 * ignore it */ 1471 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); 1472 1473 if (rdev->flags & RADEON_IS_PX) 1474 runtime = true; 1475 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime); 1476 if (runtime) 1477 vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain); 1478 #endif 1479 1480 r = radeon_init(rdev); 1481 if (r) 1482 goto failed; 1483 1484 r = radeon_gem_debugfs_init(rdev); 1485 if (r) { 1486 DRM_ERROR("registering gem debugfs failed (%d).\n", r); 1487 } 1488 1489 r = radeon_mst_debugfs_init(rdev); 1490 if (r) { 1491 DRM_ERROR("registering mst debugfs failed (%d).\n", r); 1492 } 1493 1494 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { 1495 /* Acceleration not working on AGP card try again 1496 * with fallback to PCI or PCIE GART 1497 */ 1498 radeon_asic_reset(rdev); 1499 radeon_fini(rdev); 1500 radeon_agp_disable(rdev); 1501 r = radeon_init(rdev); 1502 if (r) 1503 goto failed; 1504 } 1505 1506 r = radeon_ib_ring_tests(rdev); 1507 if (r) 1508 DRM_ERROR("ib ring test failed (%d).\n", r); 1509 1510 DRM_INFO("%s: Taking over the fictitious range 0x%lx-0x%llx\n", 1511 __func__, (uintmax_t)rdev->mc.aper_base, 1512 (uintmax_t)rdev->mc.aper_base + rdev->mc.visible_vram_size); 1513 r = vm_phys_fictitious_reg_range( 1514 rdev->mc.aper_base, 1515 rdev->mc.aper_base + rdev->mc.visible_vram_size, 1516 VM_MEMATTR_WRITE_COMBINING); 1517 if (r != 0) { 1518 DRM_ERROR("Failed to register fictitious range " 1519 "0x%lx-0x%llx (%d).\n", (uintmax_t)rdev->mc.aper_base, 1520 (uintmax_t)rdev->mc.aper_base + rdev->mc.visible_vram_size, r); 1521 return (-r); 1522 } 1523 rdev->fictitious_range_registered = true; 1524 1525 /* 1526 * Turks/Thames GPU will freeze whole laptop if DPM is not restarted 1527 * after the CP ring have chew one packet at least. Hence here we stop 1528 * and restart DPM after the radeon_ib_ring_tests(). 1529 */ 1530 if (rdev->pm.dpm_enabled && 1531 (rdev->pm.pm_method == PM_METHOD_DPM) && 1532 (rdev->family == CHIP_TURKS) && 1533 (rdev->flags & RADEON_IS_MOBILITY)) { 1534 mutex_lock(&rdev->pm.mutex); 1535 radeon_dpm_disable(rdev); 1536 radeon_dpm_enable(rdev); 1537 mutex_unlock(&rdev->pm.mutex); 1538 } 1539 1540 if ((radeon_testing & 1)) { 1541 if (rdev->accel_working) 1542 radeon_test_moves(rdev); 1543 else 1544 DRM_INFO("radeon: acceleration disabled, skipping move tests\n"); 1545 } 1546 if ((radeon_testing & 2)) { 1547 if (rdev->accel_working) 1548 radeon_test_syncing(rdev); 1549 else 1550 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n"); 1551 } 1552 if (radeon_benchmarking) { 1553 if (rdev->accel_working) 1554 radeon_benchmark(rdev, radeon_benchmarking); 1555 else 1556 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n"); 1557 } 1558 rdev->dummy_page.entry = radeon_gart_get_page_entry(rdev->dummy_page.addr, 1559 RADEON_GART_PAGE_DUMMY); 1560 return 0; 1561 1562 failed: 1563 #if 0 1564 if (runtime) 1565 vga_switcheroo_fini_domain_pm_ops(rdev->dev); 1566 #endif 1567 return r; 1568 } 1569 1570 static void radeon_debugfs_remove_files(struct radeon_device *rdev); 1571 1572 /** 1573 * radeon_device_fini - tear down the driver 1574 * 1575 * @rdev: radeon_device pointer 1576 * 1577 * Tear down the driver info (all asics). 1578 * Called at driver shutdown. 1579 */ 1580 void radeon_device_fini(struct radeon_device *rdev) 1581 { 1582 DRM_INFO("radeon: finishing device.\n"); 1583 rdev->shutdown = true; 1584 /* evict vram memory */ 1585 radeon_bo_evict_vram(rdev); 1586 1587 if (rdev->fictitious_range_registered) { 1588 vm_phys_fictitious_unreg_range( 1589 rdev->mc.aper_base, 1590 rdev->mc.aper_base + rdev->mc.visible_vram_size); 1591 } 1592 1593 radeon_fini(rdev); 1594 #ifdef DUMBBELL_WIP 1595 vga_switcheroo_unregister_client(rdev->pdev); 1596 if (rdev->flags & RADEON_IS_PX) 1597 vga_switcheroo_fini_domain_pm_ops(rdev->dev); 1598 vga_client_register(rdev->pdev, NULL, NULL, NULL); 1599 #endif /* DUMBBELL_WIP */ 1600 if (rdev->rio_mem) 1601 bus_release_resource(rdev->dev->bsddev, SYS_RES_IOPORT, rdev->rio_rid, 1602 rdev->rio_mem); 1603 rdev->rio_mem = NULL; 1604 bus_release_resource(rdev->dev->bsddev, SYS_RES_MEMORY, rdev->rmmio_rid, 1605 rdev->rmmio); 1606 rdev->rmmio = NULL; 1607 if (rdev->family >= CHIP_BONAIRE) 1608 radeon_doorbell_fini(rdev); 1609 radeon_debugfs_remove_files(rdev); 1610 } 1611 1612 1613 /* 1614 * Suspend & resume. 1615 */ 1616 /** 1617 * radeon_suspend_kms - initiate device suspend 1618 * 1619 * @pdev: drm dev pointer 1620 * @state: suspend state 1621 * 1622 * Puts the hw in the suspend state (all asics). 1623 * Returns 0 for success or an error on failure. 1624 * Called at driver suspend. 1625 */ 1626 int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon) 1627 { 1628 struct radeon_device *rdev; 1629 struct drm_crtc *crtc; 1630 struct drm_connector *connector; 1631 int i, r; 1632 1633 if (dev == NULL || dev->dev_private == NULL) { 1634 return -ENODEV; 1635 } 1636 1637 rdev = dev->dev_private; 1638 1639 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1640 return 0; 1641 1642 drm_kms_helper_poll_disable(dev); 1643 1644 drm_modeset_lock_all(dev); 1645 /* turn off display hw */ 1646 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1647 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 1648 } 1649 drm_modeset_unlock_all(dev); 1650 1651 /* unpin the front buffers and cursors */ 1652 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1653 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1654 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->primary->fb); 1655 struct radeon_bo *robj; 1656 1657 if (radeon_crtc->cursor_bo) { 1658 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); 1659 r = radeon_bo_reserve(robj, false); 1660 if (r == 0) { 1661 radeon_bo_unpin(robj); 1662 radeon_bo_unreserve(robj); 1663 } 1664 } 1665 1666 if (rfb == NULL || rfb->obj == NULL) { 1667 continue; 1668 } 1669 robj = gem_to_radeon_bo(rfb->obj); 1670 /* don't unpin kernel fb objects */ 1671 if (!radeon_fbdev_robj_is_fb(rdev, robj)) { 1672 r = radeon_bo_reserve(robj, false); 1673 if (r == 0) { 1674 radeon_bo_unpin(robj); 1675 radeon_bo_unreserve(robj); 1676 } 1677 } 1678 } 1679 /* evict vram memory */ 1680 radeon_bo_evict_vram(rdev); 1681 1682 /* wait for gpu to finish processing current batch */ 1683 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1684 r = radeon_fence_wait_empty(rdev, i); 1685 if (r) { 1686 /* delay GPU reset to resume */ 1687 radeon_fence_driver_force_completion(rdev, i); 1688 } 1689 } 1690 1691 radeon_save_bios_scratch_regs(rdev); 1692 1693 radeon_suspend(rdev); 1694 radeon_hpd_fini(rdev); 1695 /* evict remaining vram memory */ 1696 radeon_bo_evict_vram(rdev); 1697 1698 radeon_agp_suspend(rdev); 1699 1700 pci_save_state(device_get_parent(rdev->dev->bsddev)); 1701 #ifdef DUMBBELL_WIP 1702 if (suspend) { 1703 /* Shut down the device */ 1704 pci_disable_device(dev->pdev); 1705 #endif /* DUMBBELL_WIP */ 1706 pci_set_powerstate(dev->dev->bsddev, PCI_POWERSTATE_D3); 1707 #ifdef DUMBBELL_WIP 1708 } 1709 #endif 1710 1711 if (fbcon) { 1712 #ifdef DUMBBELL_WIP 1713 console_lock(); 1714 #endif /* DUMBBELL_WIP */ 1715 radeon_fbdev_set_suspend(rdev, 1); 1716 #ifdef DUMBBELL_WIP 1717 console_unlock(); 1718 #endif /* DUMBBELL_WIP */ 1719 } 1720 rdev->dummy_page.entry = radeon_gart_get_page_entry(rdev->dummy_page.addr, 1721 RADEON_GART_PAGE_DUMMY); 1722 return 0; 1723 } 1724 1725 /** 1726 * radeon_resume_kms - initiate device resume 1727 * 1728 * @pdev: drm dev pointer 1729 * 1730 * Bring the hw back to operating state (all asics). 1731 * Returns 0 for success or an error on failure. 1732 * Called at driver resume. 1733 */ 1734 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon) 1735 { 1736 struct drm_connector *connector; 1737 struct radeon_device *rdev = dev->dev_private; 1738 struct drm_crtc *crtc; 1739 int r; 1740 1741 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1742 return 0; 1743 1744 #ifdef DUMBBELL_WIP 1745 if (fbcon) { 1746 console_lock(); 1747 } 1748 #endif /* DUMBBELL_WIP */ 1749 if (resume) { 1750 #ifdef DUMBBELL_WIP 1751 pci_set_power_state(dev->pdev, PCI_D0); 1752 pci_restore_state(dev->pdev); 1753 if (pci_enable_device(dev->pdev)) { 1754 if (fbcon) 1755 console_unlock(); 1756 return -1; 1757 } 1758 #endif /* DUMBBELL_WIP */ 1759 } 1760 /* resume AGP if in use */ 1761 radeon_agp_resume(rdev); 1762 radeon_resume(rdev); 1763 1764 r = radeon_ib_ring_tests(rdev); 1765 if (r) 1766 DRM_ERROR("ib ring test failed (%d).\n", r); 1767 1768 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 1769 /* do dpm late init */ 1770 r = radeon_pm_late_init(rdev); 1771 if (r) { 1772 rdev->pm.dpm_enabled = false; 1773 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1774 } 1775 } else { 1776 /* resume old pm late */ 1777 radeon_pm_resume(rdev); 1778 } 1779 1780 radeon_restore_bios_scratch_regs(rdev); 1781 1782 /* pin cursors */ 1783 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1784 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1785 1786 if (radeon_crtc->cursor_bo) { 1787 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); 1788 r = radeon_bo_reserve(robj, false); 1789 if (r == 0) { 1790 /* Only 27 bit offset for legacy cursor */ 1791 r = radeon_bo_pin_restricted(robj, 1792 RADEON_GEM_DOMAIN_VRAM, 1793 ASIC_IS_AVIVO(rdev) ? 1794 0 : 1 << 27, 1795 (u64 *)&radeon_crtc->cursor_addr); 1796 if (r != 0) 1797 DRM_ERROR("Failed to pin cursor BO (%d)\n", r); 1798 radeon_bo_unreserve(robj); 1799 } 1800 } 1801 } 1802 1803 /* init dig PHYs, disp eng pll */ 1804 if (rdev->is_atom_bios) { 1805 radeon_atom_encoder_init(rdev); 1806 radeon_atom_disp_eng_pll_init(rdev); 1807 /* turn on the BL */ 1808 if (rdev->mode_info.bl_encoder) { 1809 u8 bl_level = radeon_get_backlight_level(rdev, 1810 rdev->mode_info.bl_encoder); 1811 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, 1812 bl_level); 1813 } 1814 } 1815 /* reset hpd state */ 1816 radeon_hpd_init(rdev); 1817 /* blat the mode back in */ 1818 if (fbcon) { 1819 drm_helper_resume_force_mode(dev); 1820 /* turn on display hw */ 1821 drm_modeset_lock_all(dev); 1822 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1823 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 1824 } 1825 drm_modeset_unlock_all(dev); 1826 } 1827 1828 drm_kms_helper_poll_enable(dev); 1829 1830 /* set the power state here in case we are a PX system or headless */ 1831 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 1832 radeon_pm_compute_clocks(rdev); 1833 1834 if (fbcon) { 1835 radeon_fbdev_set_suspend(rdev, 0); 1836 #ifdef DUMBBELL_WIP 1837 console_unlock(); 1838 #endif /* DUMBBELL_WIP */ 1839 } 1840 1841 return 0; 1842 } 1843 1844 /** 1845 * radeon_gpu_reset - reset the asic 1846 * 1847 * @rdev: radeon device pointer 1848 * 1849 * Attempt the reset the GPU if it has hung (all asics). 1850 * Returns 0 for success or an error on failure. 1851 */ 1852 int radeon_gpu_reset(struct radeon_device *rdev) 1853 { 1854 unsigned ring_sizes[RADEON_NUM_RINGS]; 1855 uint32_t *ring_data[RADEON_NUM_RINGS]; 1856 1857 bool saved = false; 1858 1859 int i, r; 1860 int resched; 1861 1862 down_write(&rdev->exclusive_lock); 1863 1864 if (!rdev->needs_reset) { 1865 up_write(&rdev->exclusive_lock); 1866 return 0; 1867 } 1868 1869 atomic_inc(&rdev->gpu_reset_counter); 1870 1871 radeon_save_bios_scratch_regs(rdev); 1872 /* block TTM */ 1873 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); 1874 radeon_suspend(rdev); 1875 radeon_hpd_fini(rdev); 1876 1877 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1878 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i], 1879 &ring_data[i]); 1880 if (ring_sizes[i]) { 1881 saved = true; 1882 dev_info(rdev->dev, "Saved %d dwords of commands " 1883 "on ring %d.\n", ring_sizes[i], i); 1884 } 1885 } 1886 1887 r = radeon_asic_reset(rdev); 1888 if (!r) { 1889 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n"); 1890 radeon_resume(rdev); 1891 } 1892 1893 radeon_restore_bios_scratch_regs(rdev); 1894 1895 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1896 if (!r && ring_data[i]) { 1897 radeon_ring_restore(rdev, &rdev->ring[i], 1898 ring_sizes[i], ring_data[i]); 1899 } else { 1900 radeon_fence_driver_force_completion(rdev, i); 1901 kfree(ring_data[i]); 1902 } 1903 } 1904 1905 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 1906 /* do dpm late init */ 1907 r = radeon_pm_late_init(rdev); 1908 if (r) { 1909 rdev->pm.dpm_enabled = false; 1910 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1911 } 1912 } else { 1913 /* resume old pm late */ 1914 radeon_pm_resume(rdev); 1915 } 1916 1917 /* init dig PHYs, disp eng pll */ 1918 if (rdev->is_atom_bios) { 1919 radeon_atom_encoder_init(rdev); 1920 radeon_atom_disp_eng_pll_init(rdev); 1921 /* turn on the BL */ 1922 if (rdev->mode_info.bl_encoder) { 1923 u8 bl_level = radeon_get_backlight_level(rdev, 1924 rdev->mode_info.bl_encoder); 1925 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, 1926 bl_level); 1927 } 1928 } 1929 /* reset hpd state */ 1930 radeon_hpd_init(rdev); 1931 1932 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); 1933 1934 rdev->in_reset = true; 1935 rdev->needs_reset = false; 1936 1937 #if 0 1938 downgrade_write(&rdev->exclusive_lock); 1939 #endif 1940 1941 drm_helper_resume_force_mode(rdev->ddev); 1942 1943 /* set the power state here in case we are a PX system or headless */ 1944 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 1945 radeon_pm_compute_clocks(rdev); 1946 1947 if (!r) { 1948 r = radeon_ib_ring_tests(rdev); 1949 if (r && saved) 1950 r = -EAGAIN; 1951 } else { 1952 /* bad news, how to tell it to userspace ? */ 1953 dev_info(rdev->dev, "GPU reset failed\n"); 1954 } 1955 1956 rdev->needs_reset = r == -EAGAIN; 1957 rdev->in_reset = false; 1958 1959 up_read(&rdev->exclusive_lock); 1960 return r; 1961 } 1962 1963 1964 /* 1965 * Debugfs 1966 */ 1967 int radeon_debugfs_add_files(struct radeon_device *rdev, 1968 struct drm_info_list *files, 1969 unsigned nfiles) 1970 { 1971 unsigned i; 1972 1973 for (i = 0; i < rdev->debugfs_count; i++) { 1974 if (rdev->debugfs[i].files == files) { 1975 /* Already registered */ 1976 return 0; 1977 } 1978 } 1979 1980 i = rdev->debugfs_count + 1; 1981 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) { 1982 DRM_ERROR("Reached maximum number of debugfs components.\n"); 1983 DRM_ERROR("Report so we increase " 1984 "RADEON_DEBUGFS_MAX_COMPONENTS.\n"); 1985 return -EINVAL; 1986 } 1987 rdev->debugfs[rdev->debugfs_count].files = files; 1988 rdev->debugfs[rdev->debugfs_count].num_files = nfiles; 1989 rdev->debugfs_count = i; 1990 #if defined(CONFIG_DEBUG_FS) 1991 drm_debugfs_create_files(files, nfiles, 1992 rdev->ddev->control->debugfs_root, 1993 rdev->ddev->control); 1994 drm_debugfs_create_files(files, nfiles, 1995 rdev->ddev->primary->debugfs_root, 1996 rdev->ddev->primary); 1997 #endif 1998 return 0; 1999 } 2000 2001 static void radeon_debugfs_remove_files(struct radeon_device *rdev) 2002 { 2003 #if defined(CONFIG_DEBUG_FS) 2004 unsigned i; 2005 2006 for (i = 0; i < rdev->debugfs_count; i++) { 2007 drm_debugfs_remove_files(rdev->debugfs[i].files, 2008 rdev->debugfs[i].num_files, 2009 rdev->ddev->control); 2010 drm_debugfs_remove_files(rdev->debugfs[i].files, 2011 rdev->debugfs[i].num_files, 2012 rdev->ddev->primary); 2013 } 2014 #endif 2015 } 2016 2017 #if defined(CONFIG_DEBUG_FS) 2018 int radeon_debugfs_init(struct drm_minor *minor) 2019 { 2020 return 0; 2021 } 2022 2023 void radeon_debugfs_cleanup(struct drm_minor *minor) 2024 { 2025 } 2026 #endif 2027