1926deccbSFrançois Tigeot /*
2926deccbSFrançois Tigeot * Copyright 2007-8 Advanced Micro Devices, Inc.
3926deccbSFrançois Tigeot * Copyright 2008 Red Hat Inc.
4926deccbSFrançois Tigeot *
5926deccbSFrançois Tigeot * Permission is hereby granted, free of charge, to any person obtaining a
6926deccbSFrançois Tigeot * copy of this software and associated documentation files (the "Software"),
7926deccbSFrançois Tigeot * to deal in the Software without restriction, including without limitation
8926deccbSFrançois Tigeot * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9926deccbSFrançois Tigeot * and/or sell copies of the Software, and to permit persons to whom the
10926deccbSFrançois Tigeot * Software is furnished to do so, subject to the following conditions:
11926deccbSFrançois Tigeot *
12926deccbSFrançois Tigeot * The above copyright notice and this permission notice shall be included in
13926deccbSFrançois Tigeot * all copies or substantial portions of the Software.
14926deccbSFrançois Tigeot *
15926deccbSFrançois Tigeot * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16926deccbSFrançois Tigeot * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17926deccbSFrançois Tigeot * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18926deccbSFrançois Tigeot * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19926deccbSFrançois Tigeot * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20926deccbSFrançois Tigeot * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21926deccbSFrançois Tigeot * OTHER DEALINGS IN THE SOFTWARE.
22926deccbSFrançois Tigeot *
23926deccbSFrançois Tigeot * Authors: Dave Airlie
24926deccbSFrançois Tigeot * Alex Deucher
25926deccbSFrançois Tigeot */
26926deccbSFrançois Tigeot #include <drm/drmP.h>
2783b4b9b9SFrançois Tigeot #include <drm/radeon_drm.h>
28926deccbSFrançois Tigeot #include "radeon.h"
29926deccbSFrançois Tigeot
30926deccbSFrançois Tigeot #include "atom.h"
31a85cb24fSFrançois Tigeot #include <asm/div64.h>
32926deccbSFrançois Tigeot
33c6f73aabSFrançois Tigeot #include <linux/pm_runtime.h>
34926deccbSFrançois Tigeot #include <drm/drm_crtc_helper.h>
352c9916cdSFrançois Tigeot #include <drm/drm_plane_helper.h>
36926deccbSFrançois Tigeot #include <drm/drm_edid.h>
37926deccbSFrançois Tigeot
38c6f73aabSFrançois Tigeot #include <linux/gcd.h>
39c6f73aabSFrançois Tigeot
avivo_crtc_load_lut(struct drm_crtc * crtc)40926deccbSFrançois Tigeot static void avivo_crtc_load_lut(struct drm_crtc *crtc)
41926deccbSFrançois Tigeot {
42926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
43926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev;
44926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private;
45*3f2dd94aSFrançois Tigeot u16 *r, *g, *b;
46926deccbSFrançois Tigeot int i;
47926deccbSFrançois Tigeot
48926deccbSFrançois Tigeot DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
49926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
50926deccbSFrançois Tigeot
51926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
52926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
53926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
54926deccbSFrançois Tigeot
55926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
56926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
57926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
58926deccbSFrançois Tigeot
59926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
60926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUT_RW_MODE, 0);
61926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
62926deccbSFrançois Tigeot
63926deccbSFrançois Tigeot WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
64*3f2dd94aSFrançois Tigeot r = crtc->gamma_store;
65*3f2dd94aSFrançois Tigeot g = r + crtc->gamma_size;
66*3f2dd94aSFrançois Tigeot b = g + crtc->gamma_size;
67926deccbSFrançois Tigeot for (i = 0; i < 256; i++) {
68926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUT_30_COLOR,
69*3f2dd94aSFrançois Tigeot ((*r++ & 0xffc0) << 14) |
70*3f2dd94aSFrançois Tigeot ((*g++ & 0xffc0) << 4) |
71*3f2dd94aSFrançois Tigeot (*b++ >> 6));
72926deccbSFrançois Tigeot }
73926deccbSFrançois Tigeot
74c6f73aabSFrançois Tigeot /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
75c6f73aabSFrançois Tigeot WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
76926deccbSFrançois Tigeot }
77926deccbSFrançois Tigeot
dce4_crtc_load_lut(struct drm_crtc * crtc)78926deccbSFrançois Tigeot static void dce4_crtc_load_lut(struct drm_crtc *crtc)
79926deccbSFrançois Tigeot {
80926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
81926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev;
82926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private;
83*3f2dd94aSFrançois Tigeot u16 *r, *g, *b;
84926deccbSFrançois Tigeot int i;
85926deccbSFrançois Tigeot
86926deccbSFrançois Tigeot DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
87926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
88926deccbSFrançois Tigeot
89926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
90926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
91926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
92926deccbSFrançois Tigeot
93926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
94926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
95926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
96926deccbSFrançois Tigeot
97926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
98926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
99926deccbSFrançois Tigeot
100926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
101*3f2dd94aSFrançois Tigeot r = crtc->gamma_store;
102*3f2dd94aSFrançois Tigeot g = r + crtc->gamma_size;
103*3f2dd94aSFrançois Tigeot b = g + crtc->gamma_size;
104926deccbSFrançois Tigeot for (i = 0; i < 256; i++) {
105926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
106*3f2dd94aSFrançois Tigeot ((*r++ & 0xffc0) << 14) |
107*3f2dd94aSFrançois Tigeot ((*g++ & 0xffc0) << 4) |
108*3f2dd94aSFrançois Tigeot (*b++ >> 6));
109926deccbSFrançois Tigeot }
110926deccbSFrançois Tigeot }
111926deccbSFrançois Tigeot
dce5_crtc_load_lut(struct drm_crtc * crtc)112926deccbSFrançois Tigeot static void dce5_crtc_load_lut(struct drm_crtc *crtc)
113926deccbSFrançois Tigeot {
114926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
115926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev;
116926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private;
117*3f2dd94aSFrançois Tigeot u16 *r, *g, *b;
118926deccbSFrançois Tigeot int i;
119926deccbSFrançois Tigeot
120926deccbSFrançois Tigeot DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
121926deccbSFrançois Tigeot
122926deccbSFrançois Tigeot WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
123926deccbSFrançois Tigeot (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
124926deccbSFrançois Tigeot NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
125926deccbSFrançois Tigeot WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
126926deccbSFrançois Tigeot NI_GRPH_PRESCALE_BYPASS);
127926deccbSFrançois Tigeot WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
128926deccbSFrançois Tigeot NI_OVL_PRESCALE_BYPASS);
129926deccbSFrançois Tigeot WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
130926deccbSFrançois Tigeot (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
131926deccbSFrançois Tigeot NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
132926deccbSFrançois Tigeot
133926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
134926deccbSFrançois Tigeot
135926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
136926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
137926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
138926deccbSFrançois Tigeot
139926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
140926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
141926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
142926deccbSFrançois Tigeot
143926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
144926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
145926deccbSFrançois Tigeot
146926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
147*3f2dd94aSFrançois Tigeot r = crtc->gamma_store;
148*3f2dd94aSFrançois Tigeot g = r + crtc->gamma_size;
149*3f2dd94aSFrançois Tigeot b = g + crtc->gamma_size;
150926deccbSFrançois Tigeot for (i = 0; i < 256; i++) {
151926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
152*3f2dd94aSFrançois Tigeot ((*r++ & 0xffc0) << 14) |
153*3f2dd94aSFrançois Tigeot ((*g++ & 0xffc0) << 4) |
154*3f2dd94aSFrançois Tigeot (*b++ >> 6));
155926deccbSFrançois Tigeot }
156926deccbSFrançois Tigeot
157926deccbSFrançois Tigeot WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
158926deccbSFrançois Tigeot (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
159926deccbSFrançois Tigeot NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
160926deccbSFrançois Tigeot NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
161926deccbSFrançois Tigeot NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
162926deccbSFrançois Tigeot WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
163926deccbSFrançois Tigeot (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
164926deccbSFrançois Tigeot NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
165926deccbSFrançois Tigeot WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
166926deccbSFrançois Tigeot (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
167926deccbSFrançois Tigeot NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
168926deccbSFrançois Tigeot WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
169c59a5c48SFrançois Tigeot (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) |
170926deccbSFrançois Tigeot NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
171926deccbSFrançois Tigeot /* XXX match this to the depth of the crtc fmt block, move to modeset? */
172926deccbSFrançois Tigeot WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
17357e252bfSMichael Neumann if (ASIC_IS_DCE8(rdev)) {
17457e252bfSMichael Neumann /* XXX this only needs to be programmed once per crtc at startup,
17557e252bfSMichael Neumann * not sure where the best place for it is
17657e252bfSMichael Neumann */
17757e252bfSMichael Neumann WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
17857e252bfSMichael Neumann CIK_CURSOR_ALPHA_BLND_ENA);
17957e252bfSMichael Neumann }
180926deccbSFrançois Tigeot }
181926deccbSFrançois Tigeot
legacy_crtc_load_lut(struct drm_crtc * crtc)182926deccbSFrançois Tigeot static void legacy_crtc_load_lut(struct drm_crtc *crtc)
183926deccbSFrançois Tigeot {
184926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
185926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev;
186926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private;
187*3f2dd94aSFrançois Tigeot u16 *r, *g, *b;
188926deccbSFrançois Tigeot int i;
189926deccbSFrançois Tigeot uint32_t dac2_cntl;
190926deccbSFrançois Tigeot
191926deccbSFrançois Tigeot dac2_cntl = RREG32(RADEON_DAC_CNTL2);
192926deccbSFrançois Tigeot if (radeon_crtc->crtc_id == 0)
193926deccbSFrançois Tigeot dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
194926deccbSFrançois Tigeot else
195926deccbSFrançois Tigeot dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
196926deccbSFrançois Tigeot WREG32(RADEON_DAC_CNTL2, dac2_cntl);
197926deccbSFrançois Tigeot
198926deccbSFrançois Tigeot WREG8(RADEON_PALETTE_INDEX, 0);
199*3f2dd94aSFrançois Tigeot r = crtc->gamma_store;
200*3f2dd94aSFrançois Tigeot g = r + crtc->gamma_size;
201*3f2dd94aSFrançois Tigeot b = g + crtc->gamma_size;
202926deccbSFrançois Tigeot for (i = 0; i < 256; i++) {
203926deccbSFrançois Tigeot WREG32(RADEON_PALETTE_30_DATA,
204*3f2dd94aSFrançois Tigeot ((*r++ & 0xffc0) << 14) |
205*3f2dd94aSFrançois Tigeot ((*g++ & 0xffc0) << 4) |
206*3f2dd94aSFrançois Tigeot (*b++ >> 6));
207926deccbSFrançois Tigeot }
208926deccbSFrançois Tigeot }
209926deccbSFrançois Tigeot
radeon_crtc_load_lut(struct drm_crtc * crtc)210926deccbSFrançois Tigeot void radeon_crtc_load_lut(struct drm_crtc *crtc)
211926deccbSFrançois Tigeot {
212926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev;
213926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private;
214926deccbSFrançois Tigeot
215926deccbSFrançois Tigeot if (!crtc->enabled)
216926deccbSFrançois Tigeot return;
217926deccbSFrançois Tigeot
218926deccbSFrançois Tigeot if (ASIC_IS_DCE5(rdev))
219926deccbSFrançois Tigeot dce5_crtc_load_lut(crtc);
220926deccbSFrançois Tigeot else if (ASIC_IS_DCE4(rdev))
221926deccbSFrançois Tigeot dce4_crtc_load_lut(crtc);
222926deccbSFrançois Tigeot else if (ASIC_IS_AVIVO(rdev))
223926deccbSFrançois Tigeot avivo_crtc_load_lut(crtc);
224926deccbSFrançois Tigeot else
225926deccbSFrançois Tigeot legacy_crtc_load_lut(crtc);
226926deccbSFrançois Tigeot }
227926deccbSFrançois Tigeot
radeon_crtc_gamma_set(struct drm_crtc * crtc,u16 * red,u16 * green,u16 * blue,uint32_t size,struct drm_modeset_acquire_ctx * ctx)2281dedbd3bSFrançois Tigeot static int radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
229a85cb24fSFrançois Tigeot u16 *blue, uint32_t size,
230a85cb24fSFrançois Tigeot struct drm_modeset_acquire_ctx *ctx)
231926deccbSFrançois Tigeot {
232926deccbSFrançois Tigeot radeon_crtc_load_lut(crtc);
2331dedbd3bSFrançois Tigeot
2341dedbd3bSFrançois Tigeot return 0;
235926deccbSFrançois Tigeot }
236926deccbSFrançois Tigeot
radeon_crtc_destroy(struct drm_crtc * crtc)237926deccbSFrançois Tigeot static void radeon_crtc_destroy(struct drm_crtc *crtc)
238926deccbSFrançois Tigeot {
239926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
240926deccbSFrançois Tigeot
241926deccbSFrançois Tigeot drm_crtc_cleanup(crtc);
242c6f73aabSFrançois Tigeot destroy_workqueue(radeon_crtc->flip_queue);
243c4ef309bSzrj kfree(radeon_crtc);
244926deccbSFrançois Tigeot }
245926deccbSFrançois Tigeot
246c6f73aabSFrançois Tigeot /**
247c6f73aabSFrançois Tigeot * radeon_unpin_work_func - unpin old buffer object
248c6f73aabSFrançois Tigeot *
249c6f73aabSFrançois Tigeot * @__work - kernel work item
250c6f73aabSFrançois Tigeot *
251c6f73aabSFrançois Tigeot * Unpin the old frame buffer object outside of the interrupt handler
252926deccbSFrançois Tigeot */
radeon_unpin_work_func(struct work_struct * __work)253c6f73aabSFrançois Tigeot static void radeon_unpin_work_func(struct work_struct *__work)
254926deccbSFrançois Tigeot {
255c6f73aabSFrançois Tigeot struct radeon_flip_work *work =
256c6f73aabSFrançois Tigeot container_of(__work, struct radeon_flip_work, unpin_work);
257926deccbSFrançois Tigeot int r;
258926deccbSFrançois Tigeot
259926deccbSFrançois Tigeot /* unpin of the old buffer */
260926deccbSFrançois Tigeot r = radeon_bo_reserve(work->old_rbo, false);
261926deccbSFrançois Tigeot if (likely(r == 0)) {
262926deccbSFrançois Tigeot r = radeon_bo_unpin(work->old_rbo);
263926deccbSFrançois Tigeot if (unlikely(r != 0)) {
264926deccbSFrançois Tigeot DRM_ERROR("failed to unpin buffer after flip\n");
265926deccbSFrançois Tigeot }
266926deccbSFrançois Tigeot radeon_bo_unreserve(work->old_rbo);
267926deccbSFrançois Tigeot } else
268926deccbSFrançois Tigeot DRM_ERROR("failed to reserve buffer after flip\n");
269926deccbSFrançois Tigeot
270*3f2dd94aSFrançois Tigeot drm_gem_object_put_unlocked(&work->old_rbo->gem_base);
271c4ef309bSzrj kfree(work);
272926deccbSFrançois Tigeot }
273926deccbSFrançois Tigeot
radeon_crtc_handle_vblank(struct radeon_device * rdev,int crtc_id)274c6f73aabSFrançois Tigeot void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
275926deccbSFrançois Tigeot {
276926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
2777dcf36dcSFrançois Tigeot unsigned long flags;
278926deccbSFrançois Tigeot u32 update_pending;
279926deccbSFrançois Tigeot int vpos, hpos;
280926deccbSFrançois Tigeot
281c6f73aabSFrançois Tigeot /* can happen during initialization */
282c6f73aabSFrançois Tigeot if (radeon_crtc == NULL)
283c6f73aabSFrançois Tigeot return;
284c6f73aabSFrançois Tigeot
285c6f73aabSFrançois Tigeot /* Skip the pageflip completion check below (based on polling) on
286c6f73aabSFrançois Tigeot * asics which reliably support hw pageflip completion irqs. pflip
287c6f73aabSFrançois Tigeot * irqs are a reliable and race-free method of handling pageflip
288c6f73aabSFrançois Tigeot * completion detection. A use_pflipirq module parameter < 2 allows
289c6f73aabSFrançois Tigeot * to override this in case of asics with faulty pflip irqs.
290c6f73aabSFrançois Tigeot * A module parameter of 0 would only use this polling based path,
291c6f73aabSFrançois Tigeot * a parameter of 1 would use pflip irq only as a backup to this
292c6f73aabSFrançois Tigeot * path, as in Linux 3.16.
293c6f73aabSFrançois Tigeot */
294c6f73aabSFrançois Tigeot if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev))
295c6f73aabSFrançois Tigeot return;
296c6f73aabSFrançois Tigeot
2977dcf36dcSFrançois Tigeot spin_lock_irqsave(&rdev->ddev->event_lock, flags);
298c6f73aabSFrançois Tigeot if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
299c6f73aabSFrançois Tigeot DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
300c6f73aabSFrançois Tigeot "RADEON_FLIP_SUBMITTED(%d)\n",
301c6f73aabSFrançois Tigeot radeon_crtc->flip_status,
302c6f73aabSFrançois Tigeot RADEON_FLIP_SUBMITTED);
3037dcf36dcSFrançois Tigeot spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
304926deccbSFrançois Tigeot return;
305926deccbSFrançois Tigeot }
306c6f73aabSFrançois Tigeot
307c6f73aabSFrançois Tigeot update_pending = radeon_page_flip_pending(rdev, crtc_id);
308926deccbSFrançois Tigeot
309926deccbSFrançois Tigeot /* Has the pageflip already completed in crtc, or is it certain
3101dedbd3bSFrançois Tigeot * to complete in this vblank? GET_DISTANCE_TO_VBLANKSTART provides
3111dedbd3bSFrançois Tigeot * distance to start of "fudged earlier" vblank in vpos, distance to
3121dedbd3bSFrançois Tigeot * start of real vblank in hpos. vpos >= 0 && hpos < 0 means we are in
3131dedbd3bSFrançois Tigeot * the last few scanlines before start of real vblank, where the vblank
3141dedbd3bSFrançois Tigeot * irq can fire, so we have sampled update_pending a bit too early and
3151dedbd3bSFrançois Tigeot * know the flip will complete at leading edge of the upcoming real
3161dedbd3bSFrançois Tigeot * vblank. On pre-AVIVO hardware, flips also complete inside the real
3171dedbd3bSFrançois Tigeot * vblank, not only at leading edge, so if update_pending for hpos >= 0
3181dedbd3bSFrançois Tigeot * == inside real vblank, the flip will complete almost immediately.
3191dedbd3bSFrançois Tigeot * Note that this method of completion handling is still not 100% race
3201dedbd3bSFrançois Tigeot * free, as we could execute before the radeon_flip_work_func managed
3211dedbd3bSFrançois Tigeot * to run and set the RADEON_FLIP_SUBMITTED status, thereby we no-op,
3221dedbd3bSFrançois Tigeot * but the flip still gets programmed into hw and completed during
3231dedbd3bSFrançois Tigeot * vblank, leading to a delayed emission of the flip completion event.
3241dedbd3bSFrançois Tigeot * This applies at least to pre-AVIVO hardware, where flips are always
3251dedbd3bSFrançois Tigeot * completing inside vblank, not only at leading edge of vblank.
326926deccbSFrançois Tigeot */
327926deccbSFrançois Tigeot if (update_pending &&
3281dedbd3bSFrançois Tigeot (DRM_SCANOUTPOS_VALID &
3291dedbd3bSFrançois Tigeot radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
3301dedbd3bSFrançois Tigeot GET_DISTANCE_TO_VBLANKSTART,
331352ff8bdSFrançois Tigeot &vpos, &hpos, NULL, NULL,
332352ff8bdSFrançois Tigeot &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) &&
3331dedbd3bSFrançois Tigeot ((vpos >= 0 && hpos < 0) || (hpos >= 0 && !ASIC_IS_AVIVO(rdev)))) {
334926deccbSFrançois Tigeot /* crtc didn't flip in this target vblank interval,
335926deccbSFrançois Tigeot * but flip is pending in crtc. Based on the current
336926deccbSFrançois Tigeot * scanout position we know that the current frame is
337926deccbSFrançois Tigeot * (nearly) complete and the flip will (likely)
338926deccbSFrançois Tigeot * complete before the start of the next frame.
339926deccbSFrançois Tigeot */
340926deccbSFrançois Tigeot update_pending = 0;
341926deccbSFrançois Tigeot }
3427dcf36dcSFrançois Tigeot spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
343c6f73aabSFrançois Tigeot if (!update_pending)
344c6f73aabSFrançois Tigeot radeon_crtc_handle_flip(rdev, crtc_id);
345c6f73aabSFrançois Tigeot }
346c6f73aabSFrançois Tigeot
347c6f73aabSFrançois Tigeot /**
348c6f73aabSFrançois Tigeot * radeon_crtc_handle_flip - page flip completed
349c6f73aabSFrançois Tigeot *
350c6f73aabSFrançois Tigeot * @rdev: radeon device pointer
351c6f73aabSFrançois Tigeot * @crtc_id: crtc number this event is for
352c6f73aabSFrançois Tigeot *
353c6f73aabSFrançois Tigeot * Called when we are sure that a page flip for this crtc is completed.
354926deccbSFrançois Tigeot */
radeon_crtc_handle_flip(struct radeon_device * rdev,int crtc_id)355c6f73aabSFrançois Tigeot void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
356c6f73aabSFrançois Tigeot {
357c6f73aabSFrançois Tigeot struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
358c6f73aabSFrançois Tigeot struct radeon_flip_work *work;
3597dcf36dcSFrançois Tigeot unsigned long flags;
360c6f73aabSFrançois Tigeot
361c6f73aabSFrançois Tigeot /* this can happen at init */
362c6f73aabSFrançois Tigeot if (radeon_crtc == NULL)
363c6f73aabSFrançois Tigeot return;
364c6f73aabSFrançois Tigeot
3657dcf36dcSFrançois Tigeot spin_lock_irqsave(&rdev->ddev->event_lock, flags);
366c6f73aabSFrançois Tigeot work = radeon_crtc->flip_work;
367c6f73aabSFrançois Tigeot if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
368c6f73aabSFrançois Tigeot DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
369c6f73aabSFrançois Tigeot "RADEON_FLIP_SUBMITTED(%d)\n",
370c6f73aabSFrançois Tigeot radeon_crtc->flip_status,
371c6f73aabSFrançois Tigeot RADEON_FLIP_SUBMITTED);
3727dcf36dcSFrançois Tigeot spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
373926deccbSFrançois Tigeot return;
374926deccbSFrançois Tigeot }
375926deccbSFrançois Tigeot
376c6f73aabSFrançois Tigeot /* Pageflip completed. Clean up. */
377c6f73aabSFrançois Tigeot radeon_crtc->flip_status = RADEON_FLIP_NONE;
378c6f73aabSFrançois Tigeot radeon_crtc->flip_work = NULL;
379926deccbSFrançois Tigeot
380926deccbSFrançois Tigeot /* wakeup userspace */
381f43cf1b1SMichael Neumann if (work->event)
382d78d3a22SFrançois Tigeot drm_crtc_send_vblank_event(&radeon_crtc->base, work->event);
383f43cf1b1SMichael Neumann
3847dcf36dcSFrançois Tigeot spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
385926deccbSFrançois Tigeot
3861dedbd3bSFrançois Tigeot drm_crtc_vblank_put(&radeon_crtc->base);
387c6f73aabSFrançois Tigeot radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
388c6f73aabSFrançois Tigeot queue_work(radeon_crtc->flip_queue, &work->unpin_work);
389c6f73aabSFrançois Tigeot }
390c6f73aabSFrançois Tigeot
391c6f73aabSFrançois Tigeot /**
392c6f73aabSFrançois Tigeot * radeon_flip_work_func - page flip framebuffer
393c6f73aabSFrançois Tigeot *
394c6f73aabSFrançois Tigeot * @work - kernel work item
395c6f73aabSFrançois Tigeot *
396c6f73aabSFrançois Tigeot * Wait for the buffer object to become idle and do the actual page flip
397c6f73aabSFrançois Tigeot */
radeon_flip_work_func(struct work_struct * __work)398c6f73aabSFrançois Tigeot static void radeon_flip_work_func(struct work_struct *__work)
399c6f73aabSFrançois Tigeot {
400c6f73aabSFrançois Tigeot struct radeon_flip_work *work =
401c6f73aabSFrançois Tigeot container_of(__work, struct radeon_flip_work, flip_work);
402c6f73aabSFrançois Tigeot struct radeon_device *rdev = work->rdev;
4031dedbd3bSFrançois Tigeot struct drm_device *dev = rdev->ddev;
404c6f73aabSFrançois Tigeot struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
405c6f73aabSFrançois Tigeot
406c6f73aabSFrançois Tigeot struct drm_crtc *crtc = &radeon_crtc->base;
4077dcf36dcSFrançois Tigeot unsigned long flags;
408c6f73aabSFrançois Tigeot int r;
4091dedbd3bSFrançois Tigeot int vpos, hpos;
410c6f73aabSFrançois Tigeot
4117dcf36dcSFrançois Tigeot down_read(&rdev->exclusive_lock);
412c6f73aabSFrançois Tigeot if (work->fence) {
4137dcf36dcSFrançois Tigeot struct radeon_fence *fence;
4147dcf36dcSFrançois Tigeot
4157dcf36dcSFrançois Tigeot fence = to_radeon_fence(work->fence);
4167dcf36dcSFrançois Tigeot if (fence && fence->rdev == rdev) {
4177dcf36dcSFrançois Tigeot r = radeon_fence_wait(fence, false);
418c6f73aabSFrançois Tigeot if (r == -EDEADLK) {
4197dcf36dcSFrançois Tigeot up_read(&rdev->exclusive_lock);
420591d5043SFrançois Tigeot do {
421c6f73aabSFrançois Tigeot r = radeon_gpu_reset(rdev);
422591d5043SFrançois Tigeot } while (r == -EAGAIN);
4237dcf36dcSFrançois Tigeot down_read(&rdev->exclusive_lock);
424c6f73aabSFrançois Tigeot }
4257dcf36dcSFrançois Tigeot } else
4266559babbSFrançois Tigeot r = dma_fence_wait(work->fence, false);
4277dcf36dcSFrançois Tigeot
428c6f73aabSFrançois Tigeot if (r)
429c6f73aabSFrançois Tigeot DRM_ERROR("failed to wait on page flip fence (%d)!\n", r);
430c6f73aabSFrançois Tigeot
431c6f73aabSFrançois Tigeot /* We continue with the page flip even if we failed to wait on
432c6f73aabSFrançois Tigeot * the fence, otherwise the DRM core and userspace will be
433c6f73aabSFrançois Tigeot * confused about which BO the CRTC is scanning out
434c6f73aabSFrançois Tigeot */
435c6f73aabSFrançois Tigeot
4366559babbSFrançois Tigeot dma_fence_put(work->fence);
4377dcf36dcSFrançois Tigeot work->fence = NULL;
438c6f73aabSFrançois Tigeot }
439c6f73aabSFrançois Tigeot
4401dedbd3bSFrançois Tigeot /* Wait until we're out of the vertical blank period before the one
4411dedbd3bSFrançois Tigeot * targeted by the flip. Always wait on pre DCE4 to avoid races with
4421dedbd3bSFrançois Tigeot * flip completion handling from vblank irq, as these old asics don't
4431dedbd3bSFrançois Tigeot * have reliable pageflip completion interrupts.
4441dedbd3bSFrançois Tigeot */
4451dedbd3bSFrançois Tigeot while (radeon_crtc->enabled &&
4461dedbd3bSFrançois Tigeot (radeon_get_crtc_scanoutpos(dev, work->crtc_id, 0,
4471dedbd3bSFrançois Tigeot &vpos, &hpos, NULL, NULL,
4481dedbd3bSFrançois Tigeot &crtc->hwmode)
4491dedbd3bSFrançois Tigeot & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
4501dedbd3bSFrançois Tigeot (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
4511dedbd3bSFrançois Tigeot (!ASIC_IS_AVIVO(rdev) ||
4521dedbd3bSFrançois Tigeot ((int) (work->target_vblank -
4531dedbd3bSFrançois Tigeot dev->driver->get_vblank_counter(dev, work->crtc_id)) > 0)))
4541dedbd3bSFrançois Tigeot usleep_range(1000, 2000);
4551dedbd3bSFrançois Tigeot
456c6f73aabSFrançois Tigeot /* We borrow the event spin lock for protecting flip_status */
4577dcf36dcSFrançois Tigeot spin_lock_irqsave(&crtc->dev->event_lock, flags);
458c6f73aabSFrançois Tigeot
459c6f73aabSFrançois Tigeot /* set the proper interrupt */
460c6f73aabSFrançois Tigeot radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
461c6f73aabSFrançois Tigeot
462c6f73aabSFrançois Tigeot /* do the flip (mmio) */
463d78d3a22SFrançois Tigeot radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async);
464c6f73aabSFrançois Tigeot
465c6f73aabSFrançois Tigeot radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
4667dcf36dcSFrançois Tigeot spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4677dcf36dcSFrançois Tigeot up_read(&rdev->exclusive_lock);
468926deccbSFrançois Tigeot }
469926deccbSFrançois Tigeot
radeon_crtc_page_flip_target(struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_pending_vblank_event * event,uint32_t page_flip_flags,uint32_t target,struct drm_modeset_acquire_ctx * ctx)4701dedbd3bSFrançois Tigeot static int radeon_crtc_page_flip_target(struct drm_crtc *crtc,
471926deccbSFrançois Tigeot struct drm_framebuffer *fb,
4729edbd4a0SFrançois Tigeot struct drm_pending_vblank_event *event,
4731dedbd3bSFrançois Tigeot uint32_t page_flip_flags,
474a85cb24fSFrançois Tigeot uint32_t target,
475a85cb24fSFrançois Tigeot struct drm_modeset_acquire_ctx *ctx)
476926deccbSFrançois Tigeot {
477926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev;
478926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private;
479926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
480926deccbSFrançois Tigeot struct radeon_framebuffer *old_radeon_fb;
481926deccbSFrançois Tigeot struct radeon_framebuffer *new_radeon_fb;
482926deccbSFrançois Tigeot struct drm_gem_object *obj;
483c6f73aabSFrançois Tigeot struct radeon_flip_work *work;
484c6f73aabSFrançois Tigeot struct radeon_bo *new_rbo;
485c6f73aabSFrançois Tigeot uint32_t tiling_flags, pitch_pixels;
486c6f73aabSFrançois Tigeot uint64_t base;
4877dcf36dcSFrançois Tigeot unsigned long flags;
488926deccbSFrançois Tigeot int r;
489926deccbSFrançois Tigeot
490c4ef309bSzrj work = kzalloc(sizeof *work, GFP_KERNEL);
491926deccbSFrançois Tigeot if (work == NULL)
492926deccbSFrançois Tigeot return -ENOMEM;
493926deccbSFrançois Tigeot
494c6f73aabSFrançois Tigeot INIT_WORK(&work->flip_work, radeon_flip_work_func);
495c6f73aabSFrançois Tigeot INIT_WORK(&work->unpin_work, radeon_unpin_work_func);
496c6f73aabSFrançois Tigeot
497926deccbSFrançois Tigeot work->rdev = rdev;
498926deccbSFrançois Tigeot work->crtc_id = radeon_crtc->crtc_id;
499c6f73aabSFrançois Tigeot work->event = event;
500d78d3a22SFrançois Tigeot work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
501c6f73aabSFrançois Tigeot
502926deccbSFrançois Tigeot /* schedule unpin of the old buffer */
503c6f73aabSFrançois Tigeot old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
504926deccbSFrançois Tigeot obj = old_radeon_fb->obj;
505c6f73aabSFrançois Tigeot
506926deccbSFrançois Tigeot /* take a reference to the old object */
507*3f2dd94aSFrançois Tigeot drm_gem_object_get(obj);
508c6f73aabSFrançois Tigeot work->old_rbo = gem_to_radeon_bo(obj);
509c6f73aabSFrançois Tigeot
510c6f73aabSFrançois Tigeot new_radeon_fb = to_radeon_framebuffer(fb);
511926deccbSFrançois Tigeot obj = new_radeon_fb->obj;
512c6f73aabSFrançois Tigeot new_rbo = gem_to_radeon_bo(obj);
513926deccbSFrançois Tigeot
514926deccbSFrançois Tigeot /* pin the new buffer */
515c6f73aabSFrançois Tigeot DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n",
516c6f73aabSFrançois Tigeot work->old_rbo, new_rbo);
517926deccbSFrançois Tigeot
518c6f73aabSFrançois Tigeot r = radeon_bo_reserve(new_rbo, false);
519926deccbSFrançois Tigeot if (unlikely(r != 0)) {
520926deccbSFrançois Tigeot DRM_ERROR("failed to reserve new rbo buffer before flip\n");
521c6f73aabSFrançois Tigeot goto cleanup;
522926deccbSFrançois Tigeot }
523926deccbSFrançois Tigeot /* Only 27 bit offset for legacy CRTC */
524c6f73aabSFrançois Tigeot r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM,
525f77dbd6cSFrançois Tigeot ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, (u64 *)&base);
526926deccbSFrançois Tigeot if (unlikely(r != 0)) {
527c6f73aabSFrançois Tigeot radeon_bo_unreserve(new_rbo);
528926deccbSFrançois Tigeot r = -EINVAL;
529926deccbSFrançois Tigeot DRM_ERROR("failed to pin new rbo buffer before flip\n");
530c6f73aabSFrançois Tigeot goto cleanup;
531926deccbSFrançois Tigeot }
5326559babbSFrançois Tigeot work->fence = dma_fence_get(reservation_object_get_excl(new_rbo->tbo.resv));
533c6f73aabSFrançois Tigeot radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
534c6f73aabSFrançois Tigeot radeon_bo_unreserve(new_rbo);
535926deccbSFrançois Tigeot
536926deccbSFrançois Tigeot if (!ASIC_IS_AVIVO(rdev)) {
537926deccbSFrançois Tigeot /* crtc offset is from display base addr not FB location */
538926deccbSFrançois Tigeot base -= radeon_crtc->legacy_display_base_addr;
539a85cb24fSFrançois Tigeot pitch_pixels = fb->pitches[0] / fb->format->cpp[0];
540926deccbSFrançois Tigeot
541926deccbSFrançois Tigeot if (tiling_flags & RADEON_TILING_MACRO) {
542926deccbSFrançois Tigeot if (ASIC_IS_R300(rdev)) {
543926deccbSFrançois Tigeot base &= ~0x7ff;
544926deccbSFrançois Tigeot } else {
545a85cb24fSFrançois Tigeot int byteshift = fb->format->cpp[0] * 8 >> 4;
546926deccbSFrançois Tigeot int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
547926deccbSFrançois Tigeot base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
548926deccbSFrançois Tigeot }
549926deccbSFrançois Tigeot } else {
550926deccbSFrançois Tigeot int offset = crtc->y * pitch_pixels + crtc->x;
551a85cb24fSFrançois Tigeot switch (fb->format->cpp[0] * 8) {
552926deccbSFrançois Tigeot case 8:
553926deccbSFrançois Tigeot default:
554926deccbSFrançois Tigeot offset *= 1;
555926deccbSFrançois Tigeot break;
556926deccbSFrançois Tigeot case 15:
557926deccbSFrançois Tigeot case 16:
558926deccbSFrançois Tigeot offset *= 2;
559926deccbSFrançois Tigeot break;
560926deccbSFrançois Tigeot case 24:
561926deccbSFrançois Tigeot offset *= 3;
562926deccbSFrançois Tigeot break;
563926deccbSFrançois Tigeot case 32:
564926deccbSFrançois Tigeot offset *= 4;
565926deccbSFrançois Tigeot break;
566926deccbSFrançois Tigeot }
567926deccbSFrançois Tigeot base += offset;
568926deccbSFrançois Tigeot }
569926deccbSFrançois Tigeot base &= ~7;
570926deccbSFrançois Tigeot }
571c6f73aabSFrançois Tigeot work->base = base;
5721dedbd3bSFrançois Tigeot work->target_vblank = target - drm_crtc_vblank_count(crtc) +
5731dedbd3bSFrançois Tigeot dev->driver->get_vblank_counter(dev, work->crtc_id);
574c6f73aabSFrançois Tigeot
575c6f73aabSFrançois Tigeot /* We borrow the event spin lock for protecting flip_work */
5767dcf36dcSFrançois Tigeot spin_lock_irqsave(&crtc->dev->event_lock, flags);
577c6f73aabSFrançois Tigeot
578c6f73aabSFrançois Tigeot if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
579c6f73aabSFrançois Tigeot DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5807dcf36dcSFrançois Tigeot spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
581c6f73aabSFrançois Tigeot r = -EBUSY;
5821dedbd3bSFrançois Tigeot goto pflip_cleanup;
583c6f73aabSFrançois Tigeot }
584c6f73aabSFrançois Tigeot radeon_crtc->flip_status = RADEON_FLIP_PENDING;
585c6f73aabSFrançois Tigeot radeon_crtc->flip_work = work;
586926deccbSFrançois Tigeot
587926deccbSFrançois Tigeot /* update crtc fb */
588ba55f2f5SFrançois Tigeot crtc->primary->fb = fb;
589926deccbSFrançois Tigeot
5907dcf36dcSFrançois Tigeot spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
591926deccbSFrançois Tigeot
592c6f73aabSFrançois Tigeot queue_work(radeon_crtc->flip_queue, &work->flip_work);
593926deccbSFrançois Tigeot return 0;
594926deccbSFrançois Tigeot
595926deccbSFrançois Tigeot pflip_cleanup:
596c6f73aabSFrançois Tigeot if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) {
597c6f73aabSFrançois Tigeot DRM_ERROR("failed to reserve new rbo in error path\n");
598c6f73aabSFrançois Tigeot goto cleanup;
599c6f73aabSFrançois Tigeot }
600c6f73aabSFrançois Tigeot if (unlikely(radeon_bo_unpin(new_rbo) != 0)) {
601c6f73aabSFrançois Tigeot DRM_ERROR("failed to unpin new rbo in error path\n");
602c6f73aabSFrançois Tigeot }
603c6f73aabSFrançois Tigeot radeon_bo_unreserve(new_rbo);
604c6f73aabSFrançois Tigeot
605c6f73aabSFrançois Tigeot cleanup:
606*3f2dd94aSFrançois Tigeot drm_gem_object_put_unlocked(&work->old_rbo->gem_base);
6076559babbSFrançois Tigeot dma_fence_put(work->fence);
608c4ef309bSzrj kfree(work);
609926deccbSFrançois Tigeot return r;
610926deccbSFrançois Tigeot }
611926deccbSFrançois Tigeot
612c6f73aabSFrançois Tigeot static int
radeon_crtc_set_config(struct drm_mode_set * set,struct drm_modeset_acquire_ctx * ctx)613a85cb24fSFrançois Tigeot radeon_crtc_set_config(struct drm_mode_set *set,
614a85cb24fSFrançois Tigeot struct drm_modeset_acquire_ctx *ctx)
615c6f73aabSFrançois Tigeot {
616c6f73aabSFrançois Tigeot struct drm_device *dev;
617c6f73aabSFrançois Tigeot struct radeon_device *rdev;
618c6f73aabSFrançois Tigeot struct drm_crtc *crtc;
619c6f73aabSFrançois Tigeot bool active = false;
620c6f73aabSFrançois Tigeot int ret;
621c6f73aabSFrançois Tigeot
622c6f73aabSFrançois Tigeot if (!set || !set->crtc)
623c6f73aabSFrançois Tigeot return -EINVAL;
624c6f73aabSFrançois Tigeot
625c6f73aabSFrançois Tigeot dev = set->crtc->dev;
626c6f73aabSFrançois Tigeot
627c6f73aabSFrançois Tigeot ret = pm_runtime_get_sync(dev->dev);
628c6f73aabSFrançois Tigeot if (ret < 0)
629c6f73aabSFrançois Tigeot return ret;
630c6f73aabSFrançois Tigeot
631a85cb24fSFrançois Tigeot ret = drm_crtc_helper_set_config(set, ctx);
632c6f73aabSFrançois Tigeot
633c6f73aabSFrançois Tigeot list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
634c6f73aabSFrançois Tigeot if (crtc->enabled)
635c6f73aabSFrançois Tigeot active = true;
636c6f73aabSFrançois Tigeot
637c6f73aabSFrançois Tigeot pm_runtime_mark_last_busy(dev->dev);
638c6f73aabSFrançois Tigeot
639c6f73aabSFrançois Tigeot rdev = dev->dev_private;
640c6f73aabSFrançois Tigeot /* if we have active crtcs and we don't have a power ref,
641c6f73aabSFrançois Tigeot take the current one */
642c6f73aabSFrançois Tigeot if (active && !rdev->have_disp_power_ref) {
643c6f73aabSFrançois Tigeot rdev->have_disp_power_ref = true;
644c6f73aabSFrançois Tigeot return ret;
645c6f73aabSFrançois Tigeot }
646c6f73aabSFrançois Tigeot /* if we have no active crtcs, then drop the power ref
647c6f73aabSFrançois Tigeot we got before */
648c6f73aabSFrançois Tigeot if (!active && rdev->have_disp_power_ref) {
649c6f73aabSFrançois Tigeot pm_runtime_put_autosuspend(dev->dev);
650c6f73aabSFrançois Tigeot rdev->have_disp_power_ref = false;
651c6f73aabSFrançois Tigeot }
652c6f73aabSFrançois Tigeot
653c6f73aabSFrançois Tigeot /* drop the power reference we got coming in here */
654c6f73aabSFrançois Tigeot pm_runtime_put_autosuspend(dev->dev);
655c6f73aabSFrançois Tigeot return ret;
656c6f73aabSFrançois Tigeot }
6571dedbd3bSFrançois Tigeot
658926deccbSFrançois Tigeot static const struct drm_crtc_funcs radeon_crtc_funcs = {
6597dcf36dcSFrançois Tigeot .cursor_set2 = radeon_crtc_cursor_set2,
660926deccbSFrançois Tigeot .cursor_move = radeon_crtc_cursor_move,
661926deccbSFrançois Tigeot .gamma_set = radeon_crtc_gamma_set,
662c6f73aabSFrançois Tigeot .set_config = radeon_crtc_set_config,
663926deccbSFrançois Tigeot .destroy = radeon_crtc_destroy,
6641dedbd3bSFrançois Tigeot .page_flip_target = radeon_crtc_page_flip_target,
665926deccbSFrançois Tigeot };
666926deccbSFrançois Tigeot
radeon_crtc_init(struct drm_device * dev,int index)667926deccbSFrançois Tigeot static void radeon_crtc_init(struct drm_device *dev, int index)
668926deccbSFrançois Tigeot {
669926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private;
670926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc;
671926deccbSFrançois Tigeot int i;
672926deccbSFrançois Tigeot
673c4ef309bSzrj radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
674926deccbSFrançois Tigeot if (radeon_crtc == NULL)
675926deccbSFrançois Tigeot return;
676926deccbSFrançois Tigeot
677926deccbSFrançois Tigeot drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
678926deccbSFrançois Tigeot
679926deccbSFrançois Tigeot drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
680926deccbSFrançois Tigeot radeon_crtc->crtc_id = index;
6811dedbd3bSFrançois Tigeot radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0);
682926deccbSFrançois Tigeot rdev->mode_info.crtcs[index] = radeon_crtc;
683926deccbSFrançois Tigeot
68457e252bfSMichael Neumann if (rdev->family >= CHIP_BONAIRE) {
68557e252bfSMichael Neumann radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
68657e252bfSMichael Neumann radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
68757e252bfSMichael Neumann } else {
68857e252bfSMichael Neumann radeon_crtc->max_cursor_width = CURSOR_WIDTH;
68957e252bfSMichael Neumann radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
69057e252bfSMichael Neumann }
691c6f73aabSFrançois Tigeot dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
692c6f73aabSFrançois Tigeot dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
69357e252bfSMichael Neumann
694926deccbSFrançois Tigeot #if 0
695926deccbSFrançois Tigeot radeon_crtc->mode_set.crtc = &radeon_crtc->base;
696926deccbSFrançois Tigeot radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
697926deccbSFrançois Tigeot radeon_crtc->mode_set.num_connectors = 0;
698926deccbSFrançois Tigeot #endif
699926deccbSFrançois Tigeot
700926deccbSFrançois Tigeot for (i = 0; i < 256; i++) {
701926deccbSFrançois Tigeot radeon_crtc->lut_r[i] = i << 2;
702926deccbSFrançois Tigeot radeon_crtc->lut_g[i] = i << 2;
703926deccbSFrançois Tigeot radeon_crtc->lut_b[i] = i << 2;
704926deccbSFrançois Tigeot }
705926deccbSFrançois Tigeot
706926deccbSFrançois Tigeot if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
707926deccbSFrançois Tigeot radeon_atombios_init_crtc(dev, radeon_crtc);
708926deccbSFrançois Tigeot else
709926deccbSFrançois Tigeot radeon_legacy_init_crtc(dev, radeon_crtc);
710926deccbSFrançois Tigeot }
711926deccbSFrançois Tigeot
71257e252bfSMichael Neumann static const char *encoder_names[38] = {
713926deccbSFrançois Tigeot "NONE",
714926deccbSFrançois Tigeot "INTERNAL_LVDS",
715926deccbSFrançois Tigeot "INTERNAL_TMDS1",
716926deccbSFrançois Tigeot "INTERNAL_TMDS2",
717926deccbSFrançois Tigeot "INTERNAL_DAC1",
718926deccbSFrançois Tigeot "INTERNAL_DAC2",
719926deccbSFrançois Tigeot "INTERNAL_SDVOA",
720926deccbSFrançois Tigeot "INTERNAL_SDVOB",
721926deccbSFrançois Tigeot "SI170B",
722926deccbSFrançois Tigeot "CH7303",
723926deccbSFrançois Tigeot "CH7301",
724926deccbSFrançois Tigeot "INTERNAL_DVO1",
725926deccbSFrançois Tigeot "EXTERNAL_SDVOA",
726926deccbSFrançois Tigeot "EXTERNAL_SDVOB",
727926deccbSFrançois Tigeot "TITFP513",
728926deccbSFrançois Tigeot "INTERNAL_LVTM1",
729926deccbSFrançois Tigeot "VT1623",
730926deccbSFrançois Tigeot "HDMI_SI1930",
731926deccbSFrançois Tigeot "HDMI_INTERNAL",
732926deccbSFrançois Tigeot "INTERNAL_KLDSCP_TMDS1",
733926deccbSFrançois Tigeot "INTERNAL_KLDSCP_DVO1",
734926deccbSFrançois Tigeot "INTERNAL_KLDSCP_DAC1",
735926deccbSFrançois Tigeot "INTERNAL_KLDSCP_DAC2",
736926deccbSFrançois Tigeot "SI178",
737926deccbSFrançois Tigeot "MVPU_FPGA",
738926deccbSFrançois Tigeot "INTERNAL_DDI",
739926deccbSFrançois Tigeot "VT1625",
740926deccbSFrançois Tigeot "HDMI_SI1932",
741926deccbSFrançois Tigeot "DP_AN9801",
742926deccbSFrançois Tigeot "DP_DP501",
743926deccbSFrançois Tigeot "INTERNAL_UNIPHY",
744926deccbSFrançois Tigeot "INTERNAL_KLDSCP_LVTMA",
745926deccbSFrançois Tigeot "INTERNAL_UNIPHY1",
746926deccbSFrançois Tigeot "INTERNAL_UNIPHY2",
747926deccbSFrançois Tigeot "NUTMEG",
748926deccbSFrançois Tigeot "TRAVIS",
74957e252bfSMichael Neumann "INTERNAL_VCE",
75057e252bfSMichael Neumann "INTERNAL_UNIPHY3",
751926deccbSFrançois Tigeot };
752926deccbSFrançois Tigeot
753926deccbSFrançois Tigeot static const char *hpd_names[6] = {
754926deccbSFrançois Tigeot "HPD1",
755926deccbSFrançois Tigeot "HPD2",
756926deccbSFrançois Tigeot "HPD3",
757926deccbSFrançois Tigeot "HPD4",
758926deccbSFrançois Tigeot "HPD5",
759926deccbSFrançois Tigeot "HPD6",
760926deccbSFrançois Tigeot };
761926deccbSFrançois Tigeot
radeon_print_display_setup(struct drm_device * dev)762926deccbSFrançois Tigeot static void radeon_print_display_setup(struct drm_device *dev)
763926deccbSFrançois Tigeot {
764926deccbSFrançois Tigeot struct drm_connector *connector;
765926deccbSFrançois Tigeot struct radeon_connector *radeon_connector;
766926deccbSFrançois Tigeot struct drm_encoder *encoder;
767926deccbSFrançois Tigeot struct radeon_encoder *radeon_encoder;
768926deccbSFrançois Tigeot uint32_t devices;
769926deccbSFrançois Tigeot int i = 0;
770926deccbSFrançois Tigeot
771926deccbSFrançois Tigeot DRM_INFO("Radeon Display Connectors\n");
772926deccbSFrançois Tigeot list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
773926deccbSFrançois Tigeot radeon_connector = to_radeon_connector(connector);
774926deccbSFrançois Tigeot DRM_INFO("Connector %d:\n", i);
775ba55f2f5SFrançois Tigeot DRM_INFO(" %s\n", connector->name);
776926deccbSFrançois Tigeot if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
777926deccbSFrançois Tigeot DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
778926deccbSFrançois Tigeot if (radeon_connector->ddc_bus) {
779926deccbSFrançois Tigeot DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
780926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.mask_clk_reg,
781926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.mask_data_reg,
782926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.a_clk_reg,
783926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.a_data_reg,
784926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.en_clk_reg,
785926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.en_data_reg,
786926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.y_clk_reg,
787926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.y_data_reg);
788926deccbSFrançois Tigeot if (radeon_connector->router.ddc_valid)
789926deccbSFrançois Tigeot DRM_INFO(" DDC Router 0x%x/0x%x\n",
790926deccbSFrançois Tigeot radeon_connector->router.ddc_mux_control_pin,
791926deccbSFrançois Tigeot radeon_connector->router.ddc_mux_state);
792926deccbSFrançois Tigeot if (radeon_connector->router.cd_valid)
793926deccbSFrançois Tigeot DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
794926deccbSFrançois Tigeot radeon_connector->router.cd_mux_control_pin,
795926deccbSFrançois Tigeot radeon_connector->router.cd_mux_state);
796926deccbSFrançois Tigeot } else {
797926deccbSFrançois Tigeot if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
798926deccbSFrançois Tigeot connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
799926deccbSFrançois Tigeot connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
800926deccbSFrançois Tigeot connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
801926deccbSFrançois Tigeot connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
802926deccbSFrançois Tigeot connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
803926deccbSFrançois Tigeot DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
804926deccbSFrançois Tigeot }
805926deccbSFrançois Tigeot DRM_INFO(" Encoders:\n");
806926deccbSFrançois Tigeot list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
807926deccbSFrançois Tigeot radeon_encoder = to_radeon_encoder(encoder);
808926deccbSFrançois Tigeot devices = radeon_encoder->devices & radeon_connector->devices;
809926deccbSFrançois Tigeot if (devices) {
810926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_CRT1_SUPPORT)
811926deccbSFrançois Tigeot DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
812926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_CRT2_SUPPORT)
813926deccbSFrançois Tigeot DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
814926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_LCD1_SUPPORT)
815926deccbSFrançois Tigeot DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
816926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP1_SUPPORT)
817926deccbSFrançois Tigeot DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
818926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP2_SUPPORT)
819926deccbSFrançois Tigeot DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
820926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP3_SUPPORT)
821926deccbSFrançois Tigeot DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
822926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP4_SUPPORT)
823926deccbSFrançois Tigeot DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
824926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP5_SUPPORT)
825926deccbSFrançois Tigeot DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
826926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP6_SUPPORT)
827926deccbSFrançois Tigeot DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
828926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_TV1_SUPPORT)
829926deccbSFrançois Tigeot DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
830926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_CV_SUPPORT)
831926deccbSFrançois Tigeot DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
832926deccbSFrançois Tigeot }
833926deccbSFrançois Tigeot }
834926deccbSFrançois Tigeot i++;
835926deccbSFrançois Tigeot }
836926deccbSFrançois Tigeot }
837926deccbSFrançois Tigeot
radeon_setup_enc_conn(struct drm_device * dev)838926deccbSFrançois Tigeot static bool radeon_setup_enc_conn(struct drm_device *dev)
839926deccbSFrançois Tigeot {
840926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private;
841926deccbSFrançois Tigeot bool ret = false;
842926deccbSFrançois Tigeot
843926deccbSFrançois Tigeot if (rdev->bios) {
844926deccbSFrançois Tigeot if (rdev->is_atom_bios) {
845926deccbSFrançois Tigeot ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
846926deccbSFrançois Tigeot if (ret == false)
847926deccbSFrançois Tigeot ret = radeon_get_atom_connector_info_from_object_table(dev);
848926deccbSFrançois Tigeot } else {
849926deccbSFrançois Tigeot ret = radeon_get_legacy_connector_info_from_bios(dev);
850926deccbSFrançois Tigeot if (ret == false)
851926deccbSFrançois Tigeot ret = radeon_get_legacy_connector_info_from_table(dev);
852926deccbSFrançois Tigeot }
853926deccbSFrançois Tigeot } else {
854926deccbSFrançois Tigeot if (!ASIC_IS_AVIVO(rdev))
855926deccbSFrançois Tigeot ret = radeon_get_legacy_connector_info_from_table(dev);
856926deccbSFrançois Tigeot }
857926deccbSFrançois Tigeot if (ret) {
858926deccbSFrançois Tigeot radeon_setup_encoder_clones(dev);
859926deccbSFrançois Tigeot radeon_print_display_setup(dev);
860926deccbSFrançois Tigeot }
861926deccbSFrançois Tigeot
862926deccbSFrançois Tigeot return ret;
863926deccbSFrançois Tigeot }
864926deccbSFrançois Tigeot
865926deccbSFrançois Tigeot /* avivo */
866c6f73aabSFrançois Tigeot
867c6f73aabSFrançois Tigeot /**
868c6f73aabSFrançois Tigeot * avivo_reduce_ratio - fractional number reduction
869c6f73aabSFrançois Tigeot *
870c6f73aabSFrançois Tigeot * @nom: nominator
871c6f73aabSFrançois Tigeot * @den: denominator
872c6f73aabSFrançois Tigeot * @nom_min: minimum value for nominator
873c6f73aabSFrançois Tigeot * @den_min: minimum value for denominator
874c6f73aabSFrançois Tigeot *
875c6f73aabSFrançois Tigeot * Find the greatest common divisor and apply it on both nominator and
876c6f73aabSFrançois Tigeot * denominator, but make nominator and denominator are at least as large
877c6f73aabSFrançois Tigeot * as their minimum values.
878c6f73aabSFrançois Tigeot */
avivo_reduce_ratio(unsigned * nom,unsigned * den,unsigned nom_min,unsigned den_min)879c6f73aabSFrançois Tigeot static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
880c6f73aabSFrançois Tigeot unsigned nom_min, unsigned den_min)
881926deccbSFrançois Tigeot {
882c6f73aabSFrançois Tigeot unsigned tmp;
883926deccbSFrançois Tigeot
884c6f73aabSFrançois Tigeot /* reduce the numbers to a simpler ratio */
885c59a5c48SFrançois Tigeot tmp = gcd(*nom, *den);
886c6f73aabSFrançois Tigeot *nom /= tmp;
887c6f73aabSFrançois Tigeot *den /= tmp;
888926deccbSFrançois Tigeot
889c6f73aabSFrançois Tigeot /* make sure nominator is large enough */
890c6f73aabSFrançois Tigeot if (*nom < nom_min) {
891c6f73aabSFrançois Tigeot tmp = DIV_ROUND_UP(nom_min, *nom);
892c6f73aabSFrançois Tigeot *nom *= tmp;
893c6f73aabSFrançois Tigeot *den *= tmp;
894926deccbSFrançois Tigeot }
895926deccbSFrançois Tigeot
896c6f73aabSFrançois Tigeot /* make sure the denominator is large enough */
897c6f73aabSFrançois Tigeot if (*den < den_min) {
898c6f73aabSFrançois Tigeot tmp = DIV_ROUND_UP(den_min, *den);
899c6f73aabSFrançois Tigeot *nom *= tmp;
900c6f73aabSFrançois Tigeot *den *= tmp;
901c6f73aabSFrançois Tigeot }
902c6f73aabSFrançois Tigeot }
903c6f73aabSFrançois Tigeot
904c6f73aabSFrançois Tigeot /**
905c6f73aabSFrançois Tigeot * avivo_get_fb_ref_div - feedback and ref divider calculation
906c6f73aabSFrançois Tigeot *
907c6f73aabSFrançois Tigeot * @nom: nominator
908c6f73aabSFrançois Tigeot * @den: denominator
909c6f73aabSFrançois Tigeot * @post_div: post divider
910c6f73aabSFrançois Tigeot * @fb_div_max: feedback divider maximum
911c6f73aabSFrançois Tigeot * @ref_div_max: reference divider maximum
912c6f73aabSFrançois Tigeot * @fb_div: resulting feedback divider
913c6f73aabSFrançois Tigeot * @ref_div: resulting reference divider
914c6f73aabSFrançois Tigeot *
915c6f73aabSFrançois Tigeot * Calculate feedback and reference divider for a given post divider. Makes
916c6f73aabSFrançois Tigeot * sure we stay within the limits.
917c6f73aabSFrançois Tigeot */
avivo_get_fb_ref_div(unsigned nom,unsigned den,unsigned post_div,unsigned fb_div_max,unsigned ref_div_max,unsigned * fb_div,unsigned * ref_div)918c6f73aabSFrançois Tigeot static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
919c6f73aabSFrançois Tigeot unsigned fb_div_max, unsigned ref_div_max,
920c6f73aabSFrançois Tigeot unsigned *fb_div, unsigned *ref_div)
921926deccbSFrançois Tigeot {
922c6f73aabSFrançois Tigeot /* limit reference * post divider to a maximum */
923c6f73aabSFrançois Tigeot ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
924926deccbSFrançois Tigeot
925c6f73aabSFrançois Tigeot /* get matching reference and feedback divider */
926c6f73aabSFrançois Tigeot *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
927c6f73aabSFrançois Tigeot *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
928926deccbSFrançois Tigeot
929c6f73aabSFrançois Tigeot /* limit fb divider to its maximum */
930c6f73aabSFrançois Tigeot if (*fb_div > fb_div_max) {
931c6f73aabSFrançois Tigeot *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
932c6f73aabSFrançois Tigeot *fb_div = fb_div_max;
933c6f73aabSFrançois Tigeot }
934926deccbSFrançois Tigeot }
935926deccbSFrançois Tigeot
936c6f73aabSFrançois Tigeot /**
937c6f73aabSFrançois Tigeot * radeon_compute_pll_avivo - compute PLL paramaters
938c6f73aabSFrançois Tigeot *
939c6f73aabSFrançois Tigeot * @pll: information about the PLL
940c6f73aabSFrançois Tigeot * @dot_clock_p: resulting pixel clock
941c6f73aabSFrançois Tigeot * fb_div_p: resulting feedback divider
942c6f73aabSFrançois Tigeot * frac_fb_div_p: fractional part of the feedback divider
943c6f73aabSFrançois Tigeot * ref_div_p: resulting reference divider
944c6f73aabSFrançois Tigeot * post_div_p: resulting reference divider
945c6f73aabSFrançois Tigeot *
946c6f73aabSFrançois Tigeot * Try to calculate the PLL parameters to generate the given frequency:
947c6f73aabSFrançois Tigeot * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
948c6f73aabSFrançois Tigeot */
radeon_compute_pll_avivo(struct radeon_pll * pll,u32 freq,u32 * dot_clock_p,u32 * fb_div_p,u32 * frac_fb_div_p,u32 * ref_div_p,u32 * post_div_p)949926deccbSFrançois Tigeot void radeon_compute_pll_avivo(struct radeon_pll *pll,
950926deccbSFrançois Tigeot u32 freq,
951926deccbSFrançois Tigeot u32 *dot_clock_p,
952926deccbSFrançois Tigeot u32 *fb_div_p,
953926deccbSFrançois Tigeot u32 *frac_fb_div_p,
954926deccbSFrançois Tigeot u32 *ref_div_p,
955926deccbSFrançois Tigeot u32 *post_div_p)
956926deccbSFrançois Tigeot {
957c6f73aabSFrançois Tigeot unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
958c6f73aabSFrançois Tigeot freq : freq / 10;
959926deccbSFrançois Tigeot
960c6f73aabSFrançois Tigeot unsigned fb_div_min, fb_div_max, fb_div;
961c6f73aabSFrançois Tigeot unsigned post_div_min, post_div_max, post_div;
962c6f73aabSFrançois Tigeot unsigned ref_div_min, ref_div_max, ref_div;
963c6f73aabSFrançois Tigeot unsigned post_div_best, diff_best;
964c6f73aabSFrançois Tigeot unsigned nom, den;
965c6f73aabSFrançois Tigeot
966c6f73aabSFrançois Tigeot /* determine allowed feedback divider range */
967c6f73aabSFrançois Tigeot fb_div_min = pll->min_feedback_div;
968c6f73aabSFrançois Tigeot fb_div_max = pll->max_feedback_div;
969926deccbSFrançois Tigeot
970926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
971c6f73aabSFrançois Tigeot fb_div_min *= 10;
972c6f73aabSFrançois Tigeot fb_div_max *= 10;
973926deccbSFrançois Tigeot }
974926deccbSFrançois Tigeot
975c6f73aabSFrançois Tigeot /* determine allowed ref divider range */
976c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_REF_DIV)
977c6f73aabSFrançois Tigeot ref_div_min = pll->reference_div;
978926deccbSFrançois Tigeot else
979c6f73aabSFrançois Tigeot ref_div_min = pll->min_ref_div;
980c6f73aabSFrançois Tigeot
981c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
982c6f73aabSFrançois Tigeot pll->flags & RADEON_PLL_USE_REF_DIV)
983c6f73aabSFrançois Tigeot ref_div_max = pll->reference_div;
9847dcf36dcSFrançois Tigeot else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
9857dcf36dcSFrançois Tigeot /* fix for problems on RS880 */
9867dcf36dcSFrançois Tigeot ref_div_max = min(pll->max_ref_div, 7u);
987c6f73aabSFrançois Tigeot else
988c6f73aabSFrançois Tigeot ref_div_max = pll->max_ref_div;
989c6f73aabSFrançois Tigeot
990c6f73aabSFrançois Tigeot /* determine allowed post divider range */
991c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_POST_DIV) {
992c6f73aabSFrançois Tigeot post_div_min = pll->post_div;
993c6f73aabSFrançois Tigeot post_div_max = pll->post_div;
994c6f73aabSFrançois Tigeot } else {
995c6f73aabSFrançois Tigeot unsigned vco_min, vco_max;
996c6f73aabSFrançois Tigeot
997c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_IS_LCD) {
998c6f73aabSFrançois Tigeot vco_min = pll->lcd_pll_out_min;
999c6f73aabSFrançois Tigeot vco_max = pll->lcd_pll_out_max;
1000c6f73aabSFrançois Tigeot } else {
1001c6f73aabSFrançois Tigeot vco_min = pll->pll_out_min;
1002c6f73aabSFrançois Tigeot vco_max = pll->pll_out_max;
1003c6f73aabSFrançois Tigeot }
1004c6f73aabSFrançois Tigeot
1005c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1006c6f73aabSFrançois Tigeot vco_min *= 10;
1007c6f73aabSFrançois Tigeot vco_max *= 10;
1008c6f73aabSFrançois Tigeot }
1009c6f73aabSFrançois Tigeot
1010c6f73aabSFrançois Tigeot post_div_min = vco_min / target_clock;
1011c6f73aabSFrançois Tigeot if ((target_clock * post_div_min) < vco_min)
1012c6f73aabSFrançois Tigeot ++post_div_min;
1013c6f73aabSFrançois Tigeot if (post_div_min < pll->min_post_div)
1014c6f73aabSFrançois Tigeot post_div_min = pll->min_post_div;
1015c6f73aabSFrançois Tigeot
1016c6f73aabSFrançois Tigeot post_div_max = vco_max / target_clock;
1017c6f73aabSFrançois Tigeot if ((target_clock * post_div_max) > vco_max)
1018c6f73aabSFrançois Tigeot --post_div_max;
1019c6f73aabSFrançois Tigeot if (post_div_max > pll->max_post_div)
1020c6f73aabSFrançois Tigeot post_div_max = pll->max_post_div;
1021c6f73aabSFrançois Tigeot }
1022c6f73aabSFrançois Tigeot
1023c6f73aabSFrançois Tigeot /* represent the searched ratio as fractional number */
1024c6f73aabSFrançois Tigeot nom = target_clock;
1025c6f73aabSFrançois Tigeot den = pll->reference_freq;
1026c6f73aabSFrançois Tigeot
1027c6f73aabSFrançois Tigeot /* reduce the numbers to a simpler ratio */
1028c6f73aabSFrançois Tigeot avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
1029c6f73aabSFrançois Tigeot
1030c6f73aabSFrançois Tigeot /* now search for a post divider */
1031c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1032c6f73aabSFrançois Tigeot post_div_best = post_div_min;
1033c6f73aabSFrançois Tigeot else
1034c6f73aabSFrançois Tigeot post_div_best = post_div_max;
1035c6f73aabSFrançois Tigeot diff_best = ~0;
1036c6f73aabSFrançois Tigeot
1037c6f73aabSFrançois Tigeot for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
1038c6f73aabSFrançois Tigeot unsigned diff;
1039c6f73aabSFrançois Tigeot avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
1040c6f73aabSFrançois Tigeot ref_div_max, &fb_div, &ref_div);
1041c6f73aabSFrançois Tigeot diff = abs(target_clock - (pll->reference_freq * fb_div) /
1042c6f73aabSFrançois Tigeot (ref_div * post_div));
1043c6f73aabSFrançois Tigeot
1044c6f73aabSFrançois Tigeot if (diff < diff_best || (diff == diff_best &&
1045c6f73aabSFrançois Tigeot !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1046c6f73aabSFrançois Tigeot
1047c6f73aabSFrançois Tigeot post_div_best = post_div;
1048c6f73aabSFrançois Tigeot diff_best = diff;
1049c6f73aabSFrançois Tigeot }
1050c6f73aabSFrançois Tigeot }
1051c6f73aabSFrançois Tigeot post_div = post_div_best;
1052c6f73aabSFrançois Tigeot
1053c6f73aabSFrançois Tigeot /* get the feedback and reference divider for the optimal value */
1054c6f73aabSFrançois Tigeot avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1055c6f73aabSFrançois Tigeot &fb_div, &ref_div);
1056c6f73aabSFrançois Tigeot
1057c6f73aabSFrançois Tigeot /* reduce the numbers to a simpler ratio once more */
1058c6f73aabSFrançois Tigeot /* this also makes sure that the reference divider is large enough */
1059c6f73aabSFrançois Tigeot avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1060c6f73aabSFrançois Tigeot
1061c6f73aabSFrançois Tigeot /* avoid high jitter with small fractional dividers */
1062c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1063c6f73aabSFrançois Tigeot fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
1064c6f73aabSFrançois Tigeot if (fb_div < fb_div_min) {
1065c6f73aabSFrançois Tigeot unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1066c6f73aabSFrançois Tigeot fb_div *= tmp;
1067c6f73aabSFrançois Tigeot ref_div *= tmp;
1068926deccbSFrançois Tigeot }
1069926deccbSFrançois Tigeot }
1070926deccbSFrançois Tigeot
1071c6f73aabSFrançois Tigeot /* and finally save the result */
1072c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1073c6f73aabSFrançois Tigeot *fb_div_p = fb_div / 10;
1074c6f73aabSFrançois Tigeot *frac_fb_div_p = fb_div % 10;
1075c6f73aabSFrançois Tigeot } else {
1076926deccbSFrançois Tigeot *fb_div_p = fb_div;
1077c6f73aabSFrançois Tigeot *frac_fb_div_p = 0;
1078c6f73aabSFrançois Tigeot }
1079c6f73aabSFrançois Tigeot
1080c6f73aabSFrançois Tigeot *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1081c6f73aabSFrançois Tigeot (pll->reference_freq * *frac_fb_div_p)) /
1082c6f73aabSFrançois Tigeot (ref_div * post_div * 10);
1083926deccbSFrançois Tigeot *ref_div_p = ref_div;
1084926deccbSFrançois Tigeot *post_div_p = post_div;
1085c6f73aabSFrançois Tigeot
1086c6f73aabSFrançois Tigeot DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1087c6f73aabSFrançois Tigeot freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1088c6f73aabSFrançois Tigeot ref_div, post_div);
1089926deccbSFrançois Tigeot }
1090926deccbSFrançois Tigeot
1091926deccbSFrançois Tigeot /* pre-avivo */
radeon_div(uint64_t n,uint32_t d)1092926deccbSFrançois Tigeot static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1093926deccbSFrançois Tigeot {
1094926deccbSFrançois Tigeot uint64_t mod;
1095926deccbSFrançois Tigeot
1096926deccbSFrançois Tigeot n += d / 2;
1097926deccbSFrançois Tigeot
1098926deccbSFrançois Tigeot mod = do_div(n, d);
1099926deccbSFrançois Tigeot return n;
1100926deccbSFrançois Tigeot }
1101926deccbSFrançois Tigeot
radeon_compute_pll_legacy(struct radeon_pll * pll,uint64_t freq,uint32_t * dot_clock_p,uint32_t * fb_div_p,uint32_t * frac_fb_div_p,uint32_t * ref_div_p,uint32_t * post_div_p)1102926deccbSFrançois Tigeot void radeon_compute_pll_legacy(struct radeon_pll *pll,
1103926deccbSFrançois Tigeot uint64_t freq,
1104926deccbSFrançois Tigeot uint32_t *dot_clock_p,
1105926deccbSFrançois Tigeot uint32_t *fb_div_p,
1106926deccbSFrançois Tigeot uint32_t *frac_fb_div_p,
1107926deccbSFrançois Tigeot uint32_t *ref_div_p,
1108926deccbSFrançois Tigeot uint32_t *post_div_p)
1109926deccbSFrançois Tigeot {
1110926deccbSFrançois Tigeot uint32_t min_ref_div = pll->min_ref_div;
1111926deccbSFrançois Tigeot uint32_t max_ref_div = pll->max_ref_div;
1112926deccbSFrançois Tigeot uint32_t min_post_div = pll->min_post_div;
1113926deccbSFrançois Tigeot uint32_t max_post_div = pll->max_post_div;
1114926deccbSFrançois Tigeot uint32_t min_fractional_feed_div = 0;
1115926deccbSFrançois Tigeot uint32_t max_fractional_feed_div = 0;
1116926deccbSFrançois Tigeot uint32_t best_vco = pll->best_vco;
1117926deccbSFrançois Tigeot uint32_t best_post_div = 1;
1118926deccbSFrançois Tigeot uint32_t best_ref_div = 1;
1119926deccbSFrançois Tigeot uint32_t best_feedback_div = 1;
1120926deccbSFrançois Tigeot uint32_t best_frac_feedback_div = 0;
1121926deccbSFrançois Tigeot uint32_t best_freq = -1;
1122926deccbSFrançois Tigeot uint32_t best_error = 0xffffffff;
1123926deccbSFrançois Tigeot uint32_t best_vco_diff = 1;
1124926deccbSFrançois Tigeot uint32_t post_div;
1125926deccbSFrançois Tigeot u32 pll_out_min, pll_out_max;
1126926deccbSFrançois Tigeot
1127a85cb24fSFrançois Tigeot DRM_DEBUG_KMS("PLL freq %lu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1128926deccbSFrançois Tigeot freq = freq * 1000;
1129926deccbSFrançois Tigeot
1130926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_IS_LCD) {
1131926deccbSFrançois Tigeot pll_out_min = pll->lcd_pll_out_min;
1132926deccbSFrançois Tigeot pll_out_max = pll->lcd_pll_out_max;
1133926deccbSFrançois Tigeot } else {
1134926deccbSFrançois Tigeot pll_out_min = pll->pll_out_min;
1135926deccbSFrançois Tigeot pll_out_max = pll->pll_out_max;
1136926deccbSFrançois Tigeot }
1137926deccbSFrançois Tigeot
1138926deccbSFrançois Tigeot if (pll_out_min > 64800)
1139926deccbSFrançois Tigeot pll_out_min = 64800;
1140926deccbSFrançois Tigeot
1141926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_REF_DIV)
1142926deccbSFrançois Tigeot min_ref_div = max_ref_div = pll->reference_div;
1143926deccbSFrançois Tigeot else {
1144926deccbSFrançois Tigeot while (min_ref_div < max_ref_div-1) {
1145926deccbSFrançois Tigeot uint32_t mid = (min_ref_div + max_ref_div) / 2;
1146926deccbSFrançois Tigeot uint32_t pll_in = pll->reference_freq / mid;
1147926deccbSFrançois Tigeot if (pll_in < pll->pll_in_min)
1148926deccbSFrançois Tigeot max_ref_div = mid;
1149926deccbSFrançois Tigeot else if (pll_in > pll->pll_in_max)
1150926deccbSFrançois Tigeot min_ref_div = mid;
1151926deccbSFrançois Tigeot else
1152926deccbSFrançois Tigeot break;
1153926deccbSFrançois Tigeot }
1154926deccbSFrançois Tigeot }
1155926deccbSFrançois Tigeot
1156926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_POST_DIV)
1157926deccbSFrançois Tigeot min_post_div = max_post_div = pll->post_div;
1158926deccbSFrançois Tigeot
1159926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1160926deccbSFrançois Tigeot min_fractional_feed_div = pll->min_frac_feedback_div;
1161926deccbSFrançois Tigeot max_fractional_feed_div = pll->max_frac_feedback_div;
1162926deccbSFrançois Tigeot }
1163926deccbSFrançois Tigeot
1164926deccbSFrançois Tigeot for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1165926deccbSFrançois Tigeot uint32_t ref_div;
1166926deccbSFrançois Tigeot
1167926deccbSFrançois Tigeot if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1168926deccbSFrançois Tigeot continue;
1169926deccbSFrançois Tigeot
1170926deccbSFrançois Tigeot /* legacy radeons only have a few post_divs */
1171926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_LEGACY) {
1172926deccbSFrançois Tigeot if ((post_div == 5) ||
1173926deccbSFrançois Tigeot (post_div == 7) ||
1174926deccbSFrançois Tigeot (post_div == 9) ||
1175926deccbSFrançois Tigeot (post_div == 10) ||
1176926deccbSFrançois Tigeot (post_div == 11) ||
1177926deccbSFrançois Tigeot (post_div == 13) ||
1178926deccbSFrançois Tigeot (post_div == 14) ||
1179926deccbSFrançois Tigeot (post_div == 15))
1180926deccbSFrançois Tigeot continue;
1181926deccbSFrançois Tigeot }
1182926deccbSFrançois Tigeot
1183926deccbSFrançois Tigeot for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1184926deccbSFrançois Tigeot uint32_t feedback_div, current_freq = 0, error, vco_diff;
1185926deccbSFrançois Tigeot uint32_t pll_in = pll->reference_freq / ref_div;
1186926deccbSFrançois Tigeot uint32_t min_feed_div = pll->min_feedback_div;
1187926deccbSFrançois Tigeot uint32_t max_feed_div = pll->max_feedback_div + 1;
1188926deccbSFrançois Tigeot
1189926deccbSFrançois Tigeot if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1190926deccbSFrançois Tigeot continue;
1191926deccbSFrançois Tigeot
1192926deccbSFrançois Tigeot while (min_feed_div < max_feed_div) {
1193926deccbSFrançois Tigeot uint32_t vco;
1194926deccbSFrançois Tigeot uint32_t min_frac_feed_div = min_fractional_feed_div;
1195926deccbSFrançois Tigeot uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1196926deccbSFrançois Tigeot uint32_t frac_feedback_div;
1197926deccbSFrançois Tigeot uint64_t tmp;
1198926deccbSFrançois Tigeot
1199926deccbSFrançois Tigeot feedback_div = (min_feed_div + max_feed_div) / 2;
1200926deccbSFrançois Tigeot
1201926deccbSFrançois Tigeot tmp = (uint64_t)pll->reference_freq * feedback_div;
1202926deccbSFrançois Tigeot vco = radeon_div(tmp, ref_div);
1203926deccbSFrançois Tigeot
1204926deccbSFrançois Tigeot if (vco < pll_out_min) {
1205926deccbSFrançois Tigeot min_feed_div = feedback_div + 1;
1206926deccbSFrançois Tigeot continue;
1207926deccbSFrançois Tigeot } else if (vco > pll_out_max) {
1208926deccbSFrançois Tigeot max_feed_div = feedback_div;
1209926deccbSFrançois Tigeot continue;
1210926deccbSFrançois Tigeot }
1211926deccbSFrançois Tigeot
1212926deccbSFrançois Tigeot while (min_frac_feed_div < max_frac_feed_div) {
1213926deccbSFrançois Tigeot frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1214926deccbSFrançois Tigeot tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1215926deccbSFrançois Tigeot tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1216926deccbSFrançois Tigeot current_freq = radeon_div(tmp, ref_div * post_div);
1217926deccbSFrançois Tigeot
1218926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1219926deccbSFrançois Tigeot if (freq < current_freq)
1220926deccbSFrançois Tigeot error = 0xffffffff;
1221926deccbSFrançois Tigeot else
1222926deccbSFrançois Tigeot error = freq - current_freq;
1223926deccbSFrançois Tigeot } else
1224926deccbSFrançois Tigeot error = abs(current_freq - freq);
1225926deccbSFrançois Tigeot vco_diff = abs(vco - best_vco);
1226926deccbSFrançois Tigeot
1227926deccbSFrançois Tigeot if ((best_vco == 0 && error < best_error) ||
1228926deccbSFrançois Tigeot (best_vco != 0 &&
1229926deccbSFrançois Tigeot ((best_error > 100 && error < best_error - 100) ||
1230926deccbSFrançois Tigeot (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1231926deccbSFrançois Tigeot best_post_div = post_div;
1232926deccbSFrançois Tigeot best_ref_div = ref_div;
1233926deccbSFrançois Tigeot best_feedback_div = feedback_div;
1234926deccbSFrançois Tigeot best_frac_feedback_div = frac_feedback_div;
1235926deccbSFrançois Tigeot best_freq = current_freq;
1236926deccbSFrançois Tigeot best_error = error;
1237926deccbSFrançois Tigeot best_vco_diff = vco_diff;
1238926deccbSFrançois Tigeot } else if (current_freq == freq) {
1239926deccbSFrançois Tigeot if (best_freq == -1) {
1240926deccbSFrançois Tigeot best_post_div = post_div;
1241926deccbSFrançois Tigeot best_ref_div = ref_div;
1242926deccbSFrançois Tigeot best_feedback_div = feedback_div;
1243926deccbSFrançois Tigeot best_frac_feedback_div = frac_feedback_div;
1244926deccbSFrançois Tigeot best_freq = current_freq;
1245926deccbSFrançois Tigeot best_error = error;
1246926deccbSFrançois Tigeot best_vco_diff = vco_diff;
1247926deccbSFrançois Tigeot } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1248926deccbSFrançois Tigeot ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1249926deccbSFrançois Tigeot ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1250926deccbSFrançois Tigeot ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1251926deccbSFrançois Tigeot ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1252926deccbSFrançois Tigeot ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1253926deccbSFrançois Tigeot best_post_div = post_div;
1254926deccbSFrançois Tigeot best_ref_div = ref_div;
1255926deccbSFrançois Tigeot best_feedback_div = feedback_div;
1256926deccbSFrançois Tigeot best_frac_feedback_div = frac_feedback_div;
1257926deccbSFrançois Tigeot best_freq = current_freq;
1258926deccbSFrançois Tigeot best_error = error;
1259926deccbSFrançois Tigeot best_vco_diff = vco_diff;
1260926deccbSFrançois Tigeot }
1261926deccbSFrançois Tigeot }
1262926deccbSFrançois Tigeot if (current_freq < freq)
1263926deccbSFrançois Tigeot min_frac_feed_div = frac_feedback_div + 1;
1264926deccbSFrançois Tigeot else
1265926deccbSFrançois Tigeot max_frac_feed_div = frac_feedback_div;
1266926deccbSFrançois Tigeot }
1267926deccbSFrançois Tigeot if (current_freq < freq)
1268926deccbSFrançois Tigeot min_feed_div = feedback_div + 1;
1269926deccbSFrançois Tigeot else
1270926deccbSFrançois Tigeot max_feed_div = feedback_div;
1271926deccbSFrançois Tigeot }
1272926deccbSFrançois Tigeot }
1273926deccbSFrançois Tigeot }
1274926deccbSFrançois Tigeot
1275926deccbSFrançois Tigeot *dot_clock_p = best_freq / 10000;
1276926deccbSFrançois Tigeot *fb_div_p = best_feedback_div;
1277926deccbSFrançois Tigeot *frac_fb_div_p = best_frac_feedback_div;
1278926deccbSFrançois Tigeot *ref_div_p = best_ref_div;
1279926deccbSFrançois Tigeot *post_div_p = best_post_div;
1280926deccbSFrançois Tigeot DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1281926deccbSFrançois Tigeot (long long)freq,
1282926deccbSFrançois Tigeot best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1283926deccbSFrançois Tigeot best_ref_div, best_post_div);
1284926deccbSFrançois Tigeot
1285926deccbSFrançois Tigeot }
1286926deccbSFrançois Tigeot
radeon_user_framebuffer_destroy(struct drm_framebuffer * fb)1287926deccbSFrançois Tigeot static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1288926deccbSFrançois Tigeot {
1289926deccbSFrançois Tigeot struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1290926deccbSFrançois Tigeot
1291*3f2dd94aSFrançois Tigeot drm_gem_object_put_unlocked(radeon_fb->obj);
1292926deccbSFrançois Tigeot drm_framebuffer_cleanup(fb);
1293c4ef309bSzrj kfree(radeon_fb);
1294926deccbSFrançois Tigeot }
1295926deccbSFrançois Tigeot
radeon_user_framebuffer_create_handle(struct drm_framebuffer * fb,struct drm_file * file_priv,unsigned int * handle)1296926deccbSFrançois Tigeot static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1297926deccbSFrançois Tigeot struct drm_file *file_priv,
1298926deccbSFrançois Tigeot unsigned int *handle)
1299926deccbSFrançois Tigeot {
1300926deccbSFrançois Tigeot struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1301926deccbSFrançois Tigeot
1302926deccbSFrançois Tigeot return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1303926deccbSFrançois Tigeot }
1304926deccbSFrançois Tigeot
1305926deccbSFrançois Tigeot static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1306926deccbSFrançois Tigeot .destroy = radeon_user_framebuffer_destroy,
1307926deccbSFrançois Tigeot .create_handle = radeon_user_framebuffer_create_handle,
1308926deccbSFrançois Tigeot };
1309926deccbSFrançois Tigeot
1310926deccbSFrançois Tigeot int
radeon_framebuffer_init(struct drm_device * dev,struct radeon_framebuffer * rfb,const struct drm_mode_fb_cmd2 * mode_cmd,struct drm_gem_object * obj)1311926deccbSFrançois Tigeot radeon_framebuffer_init(struct drm_device *dev,
1312926deccbSFrançois Tigeot struct radeon_framebuffer *rfb,
1313aee94f86SFrançois Tigeot const struct drm_mode_fb_cmd2 *mode_cmd,
1314926deccbSFrançois Tigeot struct drm_gem_object *obj)
1315926deccbSFrançois Tigeot {
1316926deccbSFrançois Tigeot int ret;
1317926deccbSFrançois Tigeot rfb->obj = obj;
1318a85cb24fSFrançois Tigeot drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
1319926deccbSFrançois Tigeot ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1320926deccbSFrançois Tigeot if (ret) {
1321926deccbSFrançois Tigeot rfb->obj = NULL;
1322926deccbSFrançois Tigeot return ret;
1323926deccbSFrançois Tigeot }
1324926deccbSFrançois Tigeot return 0;
1325926deccbSFrançois Tigeot }
1326926deccbSFrançois Tigeot
132760fc7eecSFrançois Tigeot static struct drm_framebuffer *
radeon_user_framebuffer_create(struct drm_device * dev,struct drm_file * file_priv,const struct drm_mode_fb_cmd2 * mode_cmd)1328926deccbSFrançois Tigeot radeon_user_framebuffer_create(struct drm_device *dev,
1329926deccbSFrançois Tigeot struct drm_file *file_priv,
1330aee94f86SFrançois Tigeot const struct drm_mode_fb_cmd2 *mode_cmd)
1331926deccbSFrançois Tigeot {
1332926deccbSFrançois Tigeot struct drm_gem_object *obj;
1333926deccbSFrançois Tigeot struct radeon_framebuffer *radeon_fb;
1334926deccbSFrançois Tigeot int ret;
1335926deccbSFrançois Tigeot
13368621f407SFrançois Tigeot obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1337926deccbSFrançois Tigeot if (obj == NULL) {
1338fb572d17SFrançois Tigeot dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1339926deccbSFrançois Tigeot "can't create framebuffer\n", mode_cmd->handles[0]);
134060fc7eecSFrançois Tigeot return ERR_PTR(-ENOENT);
1341926deccbSFrançois Tigeot }
1342926deccbSFrançois Tigeot
1343c59a5c48SFrançois Tigeot /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1344c59a5c48SFrançois Tigeot if (obj->import_attach) {
1345c59a5c48SFrançois Tigeot DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n");
1346c59a5c48SFrançois Tigeot return ERR_PTR(-EINVAL);
1347c59a5c48SFrançois Tigeot }
1348c59a5c48SFrançois Tigeot
1349c4ef309bSzrj radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1350926deccbSFrançois Tigeot if (radeon_fb == NULL) {
1351*3f2dd94aSFrançois Tigeot drm_gem_object_put_unlocked(obj);
135260fc7eecSFrançois Tigeot return ERR_PTR(-ENOMEM);
1353926deccbSFrançois Tigeot }
1354926deccbSFrançois Tigeot
1355926deccbSFrançois Tigeot ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1356926deccbSFrançois Tigeot if (ret) {
1357158486a6SFrançois Tigeot kfree(radeon_fb);
1358*3f2dd94aSFrançois Tigeot drm_gem_object_put_unlocked(obj);
135960fc7eecSFrançois Tigeot return ERR_PTR(ret);
1360926deccbSFrançois Tigeot }
1361926deccbSFrançois Tigeot
136260fc7eecSFrançois Tigeot return &radeon_fb->base;
1363926deccbSFrançois Tigeot }
1364926deccbSFrançois Tigeot
radeon_output_poll_changed(struct drm_device * dev)1365926deccbSFrançois Tigeot static void radeon_output_poll_changed(struct drm_device *dev)
1366926deccbSFrançois Tigeot {
1367926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private;
1368926deccbSFrançois Tigeot radeon_fb_output_poll_changed(rdev);
1369926deccbSFrançois Tigeot }
1370926deccbSFrançois Tigeot
1371926deccbSFrançois Tigeot static const struct drm_mode_config_funcs radeon_mode_funcs = {
1372926deccbSFrançois Tigeot .fb_create = radeon_user_framebuffer_create,
1373926deccbSFrançois Tigeot .output_poll_changed = radeon_output_poll_changed
1374926deccbSFrançois Tigeot };
1375926deccbSFrançois Tigeot
1376*3f2dd94aSFrançois Tigeot static const struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1377926deccbSFrançois Tigeot { { 0, "driver" },
1378926deccbSFrançois Tigeot { 1, "bios" },
1379926deccbSFrançois Tigeot };
1380926deccbSFrançois Tigeot
1381*3f2dd94aSFrançois Tigeot static const struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1382926deccbSFrançois Tigeot { { TV_STD_NTSC, "ntsc" },
1383926deccbSFrançois Tigeot { TV_STD_PAL, "pal" },
1384926deccbSFrançois Tigeot { TV_STD_PAL_M, "pal-m" },
1385926deccbSFrançois Tigeot { TV_STD_PAL_60, "pal-60" },
1386926deccbSFrançois Tigeot { TV_STD_NTSC_J, "ntsc-j" },
1387926deccbSFrançois Tigeot { TV_STD_SCART_PAL, "scart-pal" },
1388926deccbSFrançois Tigeot { TV_STD_PAL_CN, "pal-cn" },
1389926deccbSFrançois Tigeot { TV_STD_SECAM, "secam" },
1390926deccbSFrançois Tigeot };
1391926deccbSFrançois Tigeot
1392*3f2dd94aSFrançois Tigeot static const struct drm_prop_enum_list radeon_underscan_enum_list[] =
1393926deccbSFrançois Tigeot { { UNDERSCAN_OFF, "off" },
1394926deccbSFrançois Tigeot { UNDERSCAN_ON, "on" },
1395926deccbSFrançois Tigeot { UNDERSCAN_AUTO, "auto" },
1396926deccbSFrançois Tigeot };
1397926deccbSFrançois Tigeot
1398*3f2dd94aSFrançois Tigeot static const struct drm_prop_enum_list radeon_audio_enum_list[] =
13994cd92098Szrj { { RADEON_AUDIO_DISABLE, "off" },
14004cd92098Szrj { RADEON_AUDIO_ENABLE, "on" },
14014cd92098Szrj { RADEON_AUDIO_AUTO, "auto" },
14024cd92098Szrj };
14034cd92098Szrj
1404c6f73aabSFrançois Tigeot /* XXX support different dither options? spatial, temporal, both, etc. */
1405*3f2dd94aSFrançois Tigeot static const struct drm_prop_enum_list radeon_dither_enum_list[] =
1406c6f73aabSFrançois Tigeot { { RADEON_FMT_DITHER_DISABLE, "off" },
1407c6f73aabSFrançois Tigeot { RADEON_FMT_DITHER_ENABLE, "on" },
1408c6f73aabSFrançois Tigeot };
1409c6f73aabSFrançois Tigeot
1410*3f2dd94aSFrançois Tigeot static const struct drm_prop_enum_list radeon_output_csc_enum_list[] =
1411c59a5c48SFrançois Tigeot { { RADEON_OUTPUT_CSC_BYPASS, "bypass" },
1412c59a5c48SFrançois Tigeot { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" },
1413c59a5c48SFrançois Tigeot { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" },
1414c59a5c48SFrançois Tigeot { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" },
1415c59a5c48SFrançois Tigeot };
1416c59a5c48SFrançois Tigeot
radeon_modeset_create_props(struct radeon_device * rdev)1417926deccbSFrançois Tigeot static int radeon_modeset_create_props(struct radeon_device *rdev)
1418926deccbSFrançois Tigeot {
1419926deccbSFrançois Tigeot int sz;
1420926deccbSFrançois Tigeot
1421926deccbSFrançois Tigeot if (rdev->is_atom_bios) {
1422926deccbSFrançois Tigeot rdev->mode_info.coherent_mode_property =
1423926deccbSFrançois Tigeot drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1424926deccbSFrançois Tigeot if (!rdev->mode_info.coherent_mode_property)
1425926deccbSFrançois Tigeot return -ENOMEM;
1426926deccbSFrançois Tigeot }
1427926deccbSFrançois Tigeot
1428926deccbSFrançois Tigeot if (!ASIC_IS_AVIVO(rdev)) {
1429c4ef309bSzrj sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1430926deccbSFrançois Tigeot rdev->mode_info.tmds_pll_property =
1431926deccbSFrançois Tigeot drm_property_create_enum(rdev->ddev, 0,
1432926deccbSFrançois Tigeot "tmds_pll",
1433926deccbSFrançois Tigeot radeon_tmds_pll_enum_list, sz);
1434926deccbSFrançois Tigeot }
1435926deccbSFrançois Tigeot
1436926deccbSFrançois Tigeot rdev->mode_info.load_detect_property =
1437926deccbSFrançois Tigeot drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1438926deccbSFrançois Tigeot if (!rdev->mode_info.load_detect_property)
1439926deccbSFrançois Tigeot return -ENOMEM;
1440926deccbSFrançois Tigeot
1441926deccbSFrançois Tigeot drm_mode_create_scaling_mode_property(rdev->ddev);
1442926deccbSFrançois Tigeot
1443c4ef309bSzrj sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1444926deccbSFrançois Tigeot rdev->mode_info.tv_std_property =
1445926deccbSFrançois Tigeot drm_property_create_enum(rdev->ddev, 0,
1446926deccbSFrançois Tigeot "tv standard",
1447926deccbSFrançois Tigeot radeon_tv_std_enum_list, sz);
1448926deccbSFrançois Tigeot
1449c4ef309bSzrj sz = ARRAY_SIZE(radeon_underscan_enum_list);
1450926deccbSFrançois Tigeot rdev->mode_info.underscan_property =
1451926deccbSFrançois Tigeot drm_property_create_enum(rdev->ddev, 0,
1452926deccbSFrançois Tigeot "underscan",
1453926deccbSFrançois Tigeot radeon_underscan_enum_list, sz);
1454926deccbSFrançois Tigeot
1455926deccbSFrançois Tigeot rdev->mode_info.underscan_hborder_property =
1456926deccbSFrançois Tigeot drm_property_create_range(rdev->ddev, 0,
1457926deccbSFrançois Tigeot "underscan hborder", 0, 128);
1458926deccbSFrançois Tigeot if (!rdev->mode_info.underscan_hborder_property)
1459926deccbSFrançois Tigeot return -ENOMEM;
1460926deccbSFrançois Tigeot
1461926deccbSFrançois Tigeot rdev->mode_info.underscan_vborder_property =
1462926deccbSFrançois Tigeot drm_property_create_range(rdev->ddev, 0,
1463926deccbSFrançois Tigeot "underscan vborder", 0, 128);
1464926deccbSFrançois Tigeot if (!rdev->mode_info.underscan_vborder_property)
1465926deccbSFrançois Tigeot return -ENOMEM;
1466926deccbSFrançois Tigeot
14674cd92098Szrj sz = ARRAY_SIZE(radeon_audio_enum_list);
14684cd92098Szrj rdev->mode_info.audio_property =
14694cd92098Szrj drm_property_create_enum(rdev->ddev, 0,
14704cd92098Szrj "audio",
14714cd92098Szrj radeon_audio_enum_list, sz);
14724cd92098Szrj
1473c6f73aabSFrançois Tigeot sz = ARRAY_SIZE(radeon_dither_enum_list);
1474c6f73aabSFrançois Tigeot rdev->mode_info.dither_property =
1475c6f73aabSFrançois Tigeot drm_property_create_enum(rdev->ddev, 0,
1476c6f73aabSFrançois Tigeot "dither",
1477c6f73aabSFrançois Tigeot radeon_dither_enum_list, sz);
1478c6f73aabSFrançois Tigeot
1479c59a5c48SFrançois Tigeot sz = ARRAY_SIZE(radeon_output_csc_enum_list);
1480c59a5c48SFrançois Tigeot rdev->mode_info.output_csc_property =
1481c59a5c48SFrançois Tigeot drm_property_create_enum(rdev->ddev, 0,
1482c59a5c48SFrançois Tigeot "output_csc",
1483c59a5c48SFrançois Tigeot radeon_output_csc_enum_list, sz);
1484c59a5c48SFrançois Tigeot
1485926deccbSFrançois Tigeot return 0;
1486926deccbSFrançois Tigeot }
1487926deccbSFrançois Tigeot
radeon_update_display_priority(struct radeon_device * rdev)1488926deccbSFrançois Tigeot void radeon_update_display_priority(struct radeon_device *rdev)
1489926deccbSFrançois Tigeot {
1490926deccbSFrançois Tigeot /* adjustment options for the display watermarks */
1491926deccbSFrançois Tigeot if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1492926deccbSFrançois Tigeot /* set display priority to high for r3xx, rv515 chips
1493926deccbSFrançois Tigeot * this avoids flickering due to underflow to the
1494926deccbSFrançois Tigeot * display controllers during heavy acceleration.
1495926deccbSFrançois Tigeot * Don't force high on rs4xx igp chips as it seems to
1496926deccbSFrançois Tigeot * affect the sound card. See kernel bug 15982.
1497926deccbSFrançois Tigeot */
1498926deccbSFrançois Tigeot if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1499926deccbSFrançois Tigeot !(rdev->flags & RADEON_IS_IGP))
1500926deccbSFrançois Tigeot rdev->disp_priority = 2;
1501926deccbSFrançois Tigeot else
1502926deccbSFrançois Tigeot rdev->disp_priority = 0;
1503926deccbSFrançois Tigeot } else
1504926deccbSFrançois Tigeot rdev->disp_priority = radeon_disp_priority;
1505926deccbSFrançois Tigeot
1506926deccbSFrançois Tigeot }
1507926deccbSFrançois Tigeot
1508926deccbSFrançois Tigeot /*
1509926deccbSFrançois Tigeot * Allocate hdmi structs and determine register offsets
1510926deccbSFrançois Tigeot */
radeon_afmt_init(struct radeon_device * rdev)1511926deccbSFrançois Tigeot static void radeon_afmt_init(struct radeon_device *rdev)
1512926deccbSFrançois Tigeot {
1513926deccbSFrançois Tigeot int i;
1514926deccbSFrançois Tigeot
1515926deccbSFrançois Tigeot for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1516926deccbSFrançois Tigeot rdev->mode_info.afmt[i] = NULL;
1517926deccbSFrançois Tigeot
15184cd92098Szrj if (ASIC_IS_NODCE(rdev)) {
15194cd92098Szrj /* nothing to do */
1520926deccbSFrançois Tigeot } else if (ASIC_IS_DCE4(rdev)) {
15214cd92098Szrj static uint32_t eg_offsets[] = {
15224cd92098Szrj EVERGREEN_CRTC0_REGISTER_OFFSET,
15234cd92098Szrj EVERGREEN_CRTC1_REGISTER_OFFSET,
15244cd92098Szrj EVERGREEN_CRTC2_REGISTER_OFFSET,
15254cd92098Szrj EVERGREEN_CRTC3_REGISTER_OFFSET,
15264cd92098Szrj EVERGREEN_CRTC4_REGISTER_OFFSET,
15274cd92098Szrj EVERGREEN_CRTC5_REGISTER_OFFSET,
15284cd92098Szrj 0x13830 - 0x7030,
15294cd92098Szrj };
15304cd92098Szrj int num_afmt;
15314cd92098Szrj
15324cd92098Szrj /* DCE8 has 7 audio blocks tied to DIG encoders */
15334cd92098Szrj /* DCE6 has 6 audio blocks tied to DIG encoders */
1534926deccbSFrançois Tigeot /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1535926deccbSFrançois Tigeot /* DCE4.1 has 2 audio blocks tied to DIG encoders */
15364cd92098Szrj if (ASIC_IS_DCE8(rdev))
15374cd92098Szrj num_afmt = 7;
15384cd92098Szrj else if (ASIC_IS_DCE6(rdev))
15394cd92098Szrj num_afmt = 6;
15404cd92098Szrj else if (ASIC_IS_DCE5(rdev))
15414cd92098Szrj num_afmt = 6;
15424cd92098Szrj else if (ASIC_IS_DCE41(rdev))
15434cd92098Szrj num_afmt = 2;
15444cd92098Szrj else /* DCE4 */
15454cd92098Szrj num_afmt = 6;
15464cd92098Szrj
15474cd92098Szrj BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
15484cd92098Szrj for (i = 0; i < num_afmt; i++) {
15494cd92098Szrj rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
15504cd92098Szrj if (rdev->mode_info.afmt[i]) {
15514cd92098Szrj rdev->mode_info.afmt[i]->offset = eg_offsets[i];
15524cd92098Szrj rdev->mode_info.afmt[i]->id = i;
1553926deccbSFrançois Tigeot }
1554926deccbSFrançois Tigeot }
1555926deccbSFrançois Tigeot } else if (ASIC_IS_DCE3(rdev)) {
1556926deccbSFrançois Tigeot /* DCE3.x has 2 audio blocks tied to DIG encoders */
1557c4ef309bSzrj rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1558926deccbSFrançois Tigeot if (rdev->mode_info.afmt[0]) {
1559926deccbSFrançois Tigeot rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1560926deccbSFrançois Tigeot rdev->mode_info.afmt[0]->id = 0;
1561926deccbSFrançois Tigeot }
1562c4ef309bSzrj rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1563926deccbSFrançois Tigeot if (rdev->mode_info.afmt[1]) {
1564926deccbSFrançois Tigeot rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1565926deccbSFrançois Tigeot rdev->mode_info.afmt[1]->id = 1;
1566926deccbSFrançois Tigeot }
1567926deccbSFrançois Tigeot } else if (ASIC_IS_DCE2(rdev)) {
1568926deccbSFrançois Tigeot /* DCE2 has at least 1 routable audio block */
1569c4ef309bSzrj rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1570926deccbSFrançois Tigeot if (rdev->mode_info.afmt[0]) {
1571926deccbSFrançois Tigeot rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1572926deccbSFrançois Tigeot rdev->mode_info.afmt[0]->id = 0;
1573926deccbSFrançois Tigeot }
1574926deccbSFrançois Tigeot /* r6xx has 2 routable audio blocks */
1575926deccbSFrançois Tigeot if (rdev->family >= CHIP_R600) {
1576c4ef309bSzrj rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1577926deccbSFrançois Tigeot if (rdev->mode_info.afmt[1]) {
1578926deccbSFrançois Tigeot rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1579926deccbSFrançois Tigeot rdev->mode_info.afmt[1]->id = 1;
1580926deccbSFrançois Tigeot }
1581926deccbSFrançois Tigeot }
1582926deccbSFrançois Tigeot }
1583926deccbSFrançois Tigeot }
1584926deccbSFrançois Tigeot
radeon_afmt_fini(struct radeon_device * rdev)1585926deccbSFrançois Tigeot static void radeon_afmt_fini(struct radeon_device *rdev)
1586926deccbSFrançois Tigeot {
1587926deccbSFrançois Tigeot int i;
1588926deccbSFrançois Tigeot
1589926deccbSFrançois Tigeot for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1590c4ef309bSzrj kfree(rdev->mode_info.afmt[i]);
1591926deccbSFrançois Tigeot rdev->mode_info.afmt[i] = NULL;
1592926deccbSFrançois Tigeot }
1593926deccbSFrançois Tigeot }
1594926deccbSFrançois Tigeot
radeon_modeset_init(struct radeon_device * rdev)1595926deccbSFrançois Tigeot int radeon_modeset_init(struct radeon_device *rdev)
1596926deccbSFrançois Tigeot {
1597926deccbSFrançois Tigeot int i;
1598926deccbSFrançois Tigeot int ret;
1599926deccbSFrançois Tigeot
1600926deccbSFrançois Tigeot drm_mode_config_init(rdev->ddev);
1601926deccbSFrançois Tigeot rdev->mode_info.mode_config_initialized = true;
1602926deccbSFrançois Tigeot
1603926deccbSFrançois Tigeot rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1604926deccbSFrançois Tigeot
1605d78d3a22SFrançois Tigeot if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600)
1606d78d3a22SFrançois Tigeot rdev->ddev->mode_config.async_page_flip = true;
1607d78d3a22SFrançois Tigeot
1608926deccbSFrançois Tigeot if (ASIC_IS_DCE5(rdev)) {
1609926deccbSFrançois Tigeot rdev->ddev->mode_config.max_width = 16384;
1610926deccbSFrançois Tigeot rdev->ddev->mode_config.max_height = 16384;
1611926deccbSFrançois Tigeot } else if (ASIC_IS_AVIVO(rdev)) {
1612926deccbSFrançois Tigeot rdev->ddev->mode_config.max_width = 8192;
1613926deccbSFrançois Tigeot rdev->ddev->mode_config.max_height = 8192;
1614926deccbSFrançois Tigeot } else {
1615926deccbSFrançois Tigeot rdev->ddev->mode_config.max_width = 4096;
1616926deccbSFrançois Tigeot rdev->ddev->mode_config.max_height = 4096;
1617926deccbSFrançois Tigeot }
1618926deccbSFrançois Tigeot
1619926deccbSFrançois Tigeot rdev->ddev->mode_config.preferred_depth = 24;
1620926deccbSFrançois Tigeot rdev->ddev->mode_config.prefer_shadow = 1;
1621926deccbSFrançois Tigeot
1622926deccbSFrançois Tigeot rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1623926deccbSFrançois Tigeot
1624926deccbSFrançois Tigeot ret = radeon_modeset_create_props(rdev);
1625926deccbSFrançois Tigeot if (ret) {
1626926deccbSFrançois Tigeot return ret;
1627926deccbSFrançois Tigeot }
1628926deccbSFrançois Tigeot
1629926deccbSFrançois Tigeot /* init i2c buses */
1630926deccbSFrançois Tigeot radeon_i2c_init(rdev);
1631926deccbSFrançois Tigeot
1632926deccbSFrançois Tigeot /* check combios for a valid hardcoded EDID - Sun servers */
1633926deccbSFrançois Tigeot if (!rdev->is_atom_bios) {
1634926deccbSFrançois Tigeot /* check for hardcoded EDID in BIOS */
1635926deccbSFrançois Tigeot radeon_combios_check_hardcoded_edid(rdev);
1636926deccbSFrançois Tigeot }
1637926deccbSFrançois Tigeot
1638926deccbSFrançois Tigeot /* allocate crtcs */
1639926deccbSFrançois Tigeot for (i = 0; i < rdev->num_crtc; i++) {
1640926deccbSFrançois Tigeot radeon_crtc_init(rdev->ddev, i);
1641926deccbSFrançois Tigeot }
1642926deccbSFrançois Tigeot
1643926deccbSFrançois Tigeot /* okay we should have all the bios connectors */
1644926deccbSFrançois Tigeot ret = radeon_setup_enc_conn(rdev->ddev);
1645926deccbSFrançois Tigeot if (!ret) {
1646926deccbSFrançois Tigeot return ret;
1647926deccbSFrançois Tigeot }
1648926deccbSFrançois Tigeot
1649926deccbSFrançois Tigeot /* init dig PHYs, disp eng pll */
1650926deccbSFrançois Tigeot if (rdev->is_atom_bios) {
1651926deccbSFrançois Tigeot radeon_atom_encoder_init(rdev);
1652926deccbSFrançois Tigeot radeon_atom_disp_eng_pll_init(rdev);
1653926deccbSFrançois Tigeot }
1654926deccbSFrançois Tigeot
1655926deccbSFrançois Tigeot /* initialize hpd */
1656926deccbSFrançois Tigeot radeon_hpd_init(rdev);
1657926deccbSFrançois Tigeot
1658926deccbSFrançois Tigeot /* setup afmt */
1659926deccbSFrançois Tigeot radeon_afmt_init(rdev);
1660926deccbSFrançois Tigeot
1661926deccbSFrançois Tigeot radeon_fbdev_init(rdev);
1662926deccbSFrançois Tigeot drm_kms_helper_poll_init(rdev->ddev);
1663926deccbSFrançois Tigeot
1664c59a5c48SFrançois Tigeot /* do pm late init */
1665c6f73aabSFrançois Tigeot ret = radeon_pm_late_init(rdev);
1666c6f73aabSFrançois Tigeot
1667926deccbSFrançois Tigeot return 0;
1668926deccbSFrançois Tigeot }
1669926deccbSFrançois Tigeot
radeon_modeset_fini(struct radeon_device * rdev)1670926deccbSFrançois Tigeot void radeon_modeset_fini(struct radeon_device *rdev)
1671926deccbSFrançois Tigeot {
16721dedbd3bSFrançois Tigeot if (rdev->mode_info.mode_config_initialized) {
16731dedbd3bSFrançois Tigeot drm_kms_helper_poll_fini(rdev->ddev);
16741dedbd3bSFrançois Tigeot radeon_hpd_fini(rdev);
16751dedbd3bSFrançois Tigeot drm_crtc_force_disable_all(rdev->ddev);
1676926deccbSFrançois Tigeot radeon_fbdev_fini(rdev);
16771dedbd3bSFrançois Tigeot radeon_afmt_fini(rdev);
16781dedbd3bSFrançois Tigeot drm_mode_config_cleanup(rdev->ddev);
16791dedbd3bSFrançois Tigeot rdev->mode_info.mode_config_initialized = false;
16801dedbd3bSFrançois Tigeot }
16811dedbd3bSFrançois Tigeot
1682c4ef309bSzrj kfree(rdev->mode_info.bios_hardcoded_edid);
1683926deccbSFrançois Tigeot
1684d78d3a22SFrançois Tigeot /* free i2c buses */
1685d78d3a22SFrançois Tigeot radeon_i2c_fini(rdev);
1686926deccbSFrançois Tigeot }
1687926deccbSFrançois Tigeot
is_hdtv_mode(const struct drm_display_mode * mode)1688926deccbSFrançois Tigeot static bool is_hdtv_mode(const struct drm_display_mode *mode)
1689926deccbSFrançois Tigeot {
1690926deccbSFrançois Tigeot /* try and guess if this is a tv or a monitor */
1691926deccbSFrançois Tigeot if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1692926deccbSFrançois Tigeot (mode->vdisplay == 576) || /* 576p */
1693926deccbSFrançois Tigeot (mode->vdisplay == 720) || /* 720p */
1694926deccbSFrançois Tigeot (mode->vdisplay == 1080)) /* 1080p */
1695926deccbSFrançois Tigeot return true;
1696926deccbSFrançois Tigeot else
1697926deccbSFrançois Tigeot return false;
1698926deccbSFrançois Tigeot }
1699926deccbSFrançois Tigeot
radeon_crtc_scaling_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)1700926deccbSFrançois Tigeot bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1701926deccbSFrançois Tigeot const struct drm_display_mode *mode,
1702926deccbSFrançois Tigeot struct drm_display_mode *adjusted_mode)
1703926deccbSFrançois Tigeot {
1704926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev;
1705926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private;
1706926deccbSFrançois Tigeot struct drm_encoder *encoder;
1707926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1708926deccbSFrançois Tigeot struct radeon_encoder *radeon_encoder;
1709926deccbSFrançois Tigeot struct drm_connector *connector;
1710926deccbSFrançois Tigeot struct radeon_connector *radeon_connector;
1711926deccbSFrançois Tigeot bool first = true;
1712926deccbSFrançois Tigeot u32 src_v = 1, dst_v = 1;
1713926deccbSFrançois Tigeot u32 src_h = 1, dst_h = 1;
1714926deccbSFrançois Tigeot
1715926deccbSFrançois Tigeot radeon_crtc->h_border = 0;
1716926deccbSFrançois Tigeot radeon_crtc->v_border = 0;
1717926deccbSFrançois Tigeot
1718926deccbSFrançois Tigeot list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1719926deccbSFrançois Tigeot if (encoder->crtc != crtc)
1720926deccbSFrançois Tigeot continue;
1721926deccbSFrançois Tigeot radeon_encoder = to_radeon_encoder(encoder);
1722926deccbSFrançois Tigeot connector = radeon_get_connector_for_encoder(encoder);
1723926deccbSFrançois Tigeot radeon_connector = to_radeon_connector(connector);
1724926deccbSFrançois Tigeot
1725926deccbSFrançois Tigeot if (first) {
1726926deccbSFrançois Tigeot /* set scaling */
1727926deccbSFrançois Tigeot if (radeon_encoder->rmx_type == RMX_OFF)
1728926deccbSFrançois Tigeot radeon_crtc->rmx_type = RMX_OFF;
1729926deccbSFrançois Tigeot else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1730926deccbSFrançois Tigeot mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1731926deccbSFrançois Tigeot radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1732926deccbSFrançois Tigeot else
1733926deccbSFrançois Tigeot radeon_crtc->rmx_type = RMX_OFF;
1734926deccbSFrançois Tigeot /* copy native mode */
1735926deccbSFrançois Tigeot memcpy(&radeon_crtc->native_mode,
1736926deccbSFrançois Tigeot &radeon_encoder->native_mode,
1737926deccbSFrançois Tigeot sizeof(struct drm_display_mode));
1738926deccbSFrançois Tigeot src_v = crtc->mode.vdisplay;
1739926deccbSFrançois Tigeot dst_v = radeon_crtc->native_mode.vdisplay;
1740926deccbSFrançois Tigeot src_h = crtc->mode.hdisplay;
1741926deccbSFrançois Tigeot dst_h = radeon_crtc->native_mode.hdisplay;
1742926deccbSFrançois Tigeot
1743926deccbSFrançois Tigeot /* fix up for overscan on hdmi */
1744926deccbSFrançois Tigeot if (ASIC_IS_AVIVO(rdev) &&
1745926deccbSFrançois Tigeot (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1746926deccbSFrançois Tigeot ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1747926deccbSFrançois Tigeot ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1748c6f73aabSFrançois Tigeot drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
1749926deccbSFrançois Tigeot is_hdtv_mode(mode)))) {
1750926deccbSFrançois Tigeot if (radeon_encoder->underscan_hborder != 0)
1751926deccbSFrançois Tigeot radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1752926deccbSFrançois Tigeot else
1753926deccbSFrançois Tigeot radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1754926deccbSFrançois Tigeot if (radeon_encoder->underscan_vborder != 0)
1755926deccbSFrançois Tigeot radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1756926deccbSFrançois Tigeot else
1757926deccbSFrançois Tigeot radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1758926deccbSFrançois Tigeot radeon_crtc->rmx_type = RMX_FULL;
1759926deccbSFrançois Tigeot src_v = crtc->mode.vdisplay;
1760926deccbSFrançois Tigeot dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1761926deccbSFrançois Tigeot src_h = crtc->mode.hdisplay;
1762926deccbSFrançois Tigeot dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1763926deccbSFrançois Tigeot }
1764926deccbSFrançois Tigeot first = false;
1765926deccbSFrançois Tigeot } else {
1766926deccbSFrançois Tigeot if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1767926deccbSFrançois Tigeot /* WARNING: Right now this can't happen but
1768926deccbSFrançois Tigeot * in the future we need to check that scaling
1769926deccbSFrançois Tigeot * are consistent across different encoder
1770926deccbSFrançois Tigeot * (ie all encoder can work with the same
1771926deccbSFrançois Tigeot * scaling).
1772926deccbSFrançois Tigeot */
1773926deccbSFrançois Tigeot DRM_ERROR("Scaling not consistent across encoder.\n");
1774926deccbSFrançois Tigeot return false;
1775926deccbSFrançois Tigeot }
1776926deccbSFrançois Tigeot }
1777926deccbSFrançois Tigeot }
1778926deccbSFrançois Tigeot if (radeon_crtc->rmx_type != RMX_OFF) {
1779926deccbSFrançois Tigeot fixed20_12 a, b;
1780926deccbSFrançois Tigeot a.full = dfixed_const(src_v);
1781926deccbSFrançois Tigeot b.full = dfixed_const(dst_v);
1782926deccbSFrançois Tigeot radeon_crtc->vsc.full = dfixed_div(a, b);
1783926deccbSFrançois Tigeot a.full = dfixed_const(src_h);
1784926deccbSFrançois Tigeot b.full = dfixed_const(dst_h);
1785926deccbSFrançois Tigeot radeon_crtc->hsc.full = dfixed_div(a, b);
1786926deccbSFrançois Tigeot } else {
1787926deccbSFrançois Tigeot radeon_crtc->vsc.full = dfixed_const(1);
1788926deccbSFrançois Tigeot radeon_crtc->hsc.full = dfixed_const(1);
1789926deccbSFrançois Tigeot }
1790926deccbSFrançois Tigeot return true;
1791926deccbSFrançois Tigeot }
1792926deccbSFrançois Tigeot
1793926deccbSFrançois Tigeot /*
1794782e40d3SFrançois Tigeot * Retrieve current video scanout position of crtc on a given gpu, and
1795782e40d3SFrançois Tigeot * an optional accurate timestamp of when query happened.
1796926deccbSFrançois Tigeot *
1797926deccbSFrançois Tigeot * \param dev Device to query.
1798926deccbSFrançois Tigeot * \param crtc Crtc to query.
1799782e40d3SFrançois Tigeot * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1800c59a5c48SFrançois Tigeot * For driver internal use only also supports these flags:
1801c59a5c48SFrançois Tigeot *
1802c59a5c48SFrançois Tigeot * USE_REAL_VBLANKSTART to use the real start of vblank instead
1803c59a5c48SFrançois Tigeot * of a fudged earlier start of vblank.
1804c59a5c48SFrançois Tigeot *
1805c59a5c48SFrançois Tigeot * GET_DISTANCE_TO_VBLANKSTART to return distance to the
1806c59a5c48SFrançois Tigeot * fudged earlier start of vblank in *vpos and the distance
1807c59a5c48SFrançois Tigeot * to true start of vblank in *hpos.
1808c59a5c48SFrançois Tigeot *
1809926deccbSFrançois Tigeot * \param *vpos Location where vertical scanout position should be stored.
1810926deccbSFrançois Tigeot * \param *hpos Location where horizontal scanout position should go.
1811782e40d3SFrançois Tigeot * \param *stime Target location for timestamp taken immediately before
1812782e40d3SFrançois Tigeot * scanout position query. Can be NULL to skip timestamp.
1813782e40d3SFrançois Tigeot * \param *etime Target location for timestamp taken immediately after
1814782e40d3SFrançois Tigeot * scanout position query. Can be NULL to skip timestamp.
1815926deccbSFrançois Tigeot *
1816926deccbSFrançois Tigeot * Returns vpos as a positive number while in active scanout area.
1817926deccbSFrançois Tigeot * Returns vpos as a negative number inside vblank, counting the number
1818926deccbSFrançois Tigeot * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1819926deccbSFrançois Tigeot * until start of active scanout / end of vblank."
1820926deccbSFrançois Tigeot *
1821926deccbSFrançois Tigeot * \return Flags, or'ed together as follows:
1822926deccbSFrançois Tigeot *
1823926deccbSFrançois Tigeot * DRM_SCANOUTPOS_VALID = Query successful.
1824926deccbSFrançois Tigeot * DRM_SCANOUTPOS_INVBL = Inside vblank.
1825926deccbSFrançois Tigeot * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1826926deccbSFrançois Tigeot * this flag means that returned position may be offset by a constant but
1827926deccbSFrançois Tigeot * unknown small number of scanlines wrt. real scanout position.
1828926deccbSFrançois Tigeot *
1829926deccbSFrançois Tigeot */
radeon_get_crtc_scanoutpos(struct drm_device * dev,unsigned int pipe,unsigned int flags,int * vpos,int * hpos,ktime_t * stime,ktime_t * etime,const struct drm_display_mode * mode)1830c59a5c48SFrançois Tigeot int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
1831c59a5c48SFrançois Tigeot unsigned int flags, int *vpos, int *hpos,
1832c59a5c48SFrançois Tigeot ktime_t *stime, ktime_t *etime,
1833352ff8bdSFrançois Tigeot const struct drm_display_mode *mode)
1834926deccbSFrançois Tigeot {
1835926deccbSFrançois Tigeot u32 stat_crtc = 0, vbl = 0, position = 0;
1836926deccbSFrançois Tigeot int vbl_start, vbl_end, vtotal, ret = 0;
1837926deccbSFrançois Tigeot bool in_vbl = true;
1838926deccbSFrançois Tigeot
1839926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private;
1840926deccbSFrançois Tigeot
1841782e40d3SFrançois Tigeot /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1842782e40d3SFrançois Tigeot
1843782e40d3SFrançois Tigeot /* Get optional system timestamp before query. */
1844782e40d3SFrançois Tigeot if (stime)
1845782e40d3SFrançois Tigeot *stime = ktime_get();
1846782e40d3SFrançois Tigeot
1847926deccbSFrançois Tigeot if (ASIC_IS_DCE4(rdev)) {
1848c59a5c48SFrançois Tigeot if (pipe == 0) {
1849926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1850926deccbSFrançois Tigeot EVERGREEN_CRTC0_REGISTER_OFFSET);
1851926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1852926deccbSFrançois Tigeot EVERGREEN_CRTC0_REGISTER_OFFSET);
1853926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID;
1854926deccbSFrançois Tigeot }
1855c59a5c48SFrançois Tigeot if (pipe == 1) {
1856926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1857926deccbSFrançois Tigeot EVERGREEN_CRTC1_REGISTER_OFFSET);
1858926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1859926deccbSFrançois Tigeot EVERGREEN_CRTC1_REGISTER_OFFSET);
1860926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID;
1861926deccbSFrançois Tigeot }
1862c59a5c48SFrançois Tigeot if (pipe == 2) {
1863926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1864926deccbSFrançois Tigeot EVERGREEN_CRTC2_REGISTER_OFFSET);
1865926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1866926deccbSFrançois Tigeot EVERGREEN_CRTC2_REGISTER_OFFSET);
1867926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID;
1868926deccbSFrançois Tigeot }
1869c59a5c48SFrançois Tigeot if (pipe == 3) {
1870926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1871926deccbSFrançois Tigeot EVERGREEN_CRTC3_REGISTER_OFFSET);
1872926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1873926deccbSFrançois Tigeot EVERGREEN_CRTC3_REGISTER_OFFSET);
1874926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID;
1875926deccbSFrançois Tigeot }
1876c59a5c48SFrançois Tigeot if (pipe == 4) {
1877926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1878926deccbSFrançois Tigeot EVERGREEN_CRTC4_REGISTER_OFFSET);
1879926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1880926deccbSFrançois Tigeot EVERGREEN_CRTC4_REGISTER_OFFSET);
1881926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID;
1882926deccbSFrançois Tigeot }
1883c59a5c48SFrançois Tigeot if (pipe == 5) {
1884926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1885926deccbSFrançois Tigeot EVERGREEN_CRTC5_REGISTER_OFFSET);
1886926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1887926deccbSFrançois Tigeot EVERGREEN_CRTC5_REGISTER_OFFSET);
1888926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID;
1889926deccbSFrançois Tigeot }
1890926deccbSFrançois Tigeot } else if (ASIC_IS_AVIVO(rdev)) {
1891c59a5c48SFrançois Tigeot if (pipe == 0) {
1892926deccbSFrançois Tigeot vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1893926deccbSFrançois Tigeot position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1894926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID;
1895926deccbSFrançois Tigeot }
1896c59a5c48SFrançois Tigeot if (pipe == 1) {
1897926deccbSFrançois Tigeot vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1898926deccbSFrançois Tigeot position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1899926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID;
1900926deccbSFrançois Tigeot }
1901926deccbSFrançois Tigeot } else {
1902926deccbSFrançois Tigeot /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1903c59a5c48SFrançois Tigeot if (pipe == 0) {
1904926deccbSFrançois Tigeot /* Assume vbl_end == 0, get vbl_start from
1905926deccbSFrançois Tigeot * upper 16 bits.
1906926deccbSFrançois Tigeot */
1907926deccbSFrançois Tigeot vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1908926deccbSFrançois Tigeot RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1909926deccbSFrançois Tigeot /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1910926deccbSFrançois Tigeot position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1911926deccbSFrançois Tigeot stat_crtc = RREG32(RADEON_CRTC_STATUS);
1912926deccbSFrançois Tigeot if (!(stat_crtc & 1))
1913926deccbSFrançois Tigeot in_vbl = false;
1914926deccbSFrançois Tigeot
1915926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID;
1916926deccbSFrançois Tigeot }
1917c59a5c48SFrançois Tigeot if (pipe == 1) {
1918926deccbSFrançois Tigeot vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1919926deccbSFrançois Tigeot RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1920926deccbSFrançois Tigeot position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1921926deccbSFrançois Tigeot stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1922926deccbSFrançois Tigeot if (!(stat_crtc & 1))
1923926deccbSFrançois Tigeot in_vbl = false;
1924926deccbSFrançois Tigeot
1925926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID;
1926926deccbSFrançois Tigeot }
1927926deccbSFrançois Tigeot }
1928926deccbSFrançois Tigeot
1929782e40d3SFrançois Tigeot /* Get optional system timestamp after query. */
1930782e40d3SFrançois Tigeot if (etime)
1931782e40d3SFrançois Tigeot *etime = ktime_get();
1932782e40d3SFrançois Tigeot
1933782e40d3SFrançois Tigeot /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1934782e40d3SFrançois Tigeot
1935926deccbSFrançois Tigeot /* Decode into vertical and horizontal scanout position. */
1936926deccbSFrançois Tigeot *vpos = position & 0x1fff;
1937926deccbSFrançois Tigeot *hpos = (position >> 16) & 0x1fff;
1938926deccbSFrançois Tigeot
1939926deccbSFrançois Tigeot /* Valid vblank area boundaries from gpu retrieved? */
1940926deccbSFrançois Tigeot if (vbl > 0) {
1941926deccbSFrançois Tigeot /* Yes: Decode. */
1942926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_ACCURATE;
1943926deccbSFrançois Tigeot vbl_start = vbl & 0x1fff;
1944926deccbSFrançois Tigeot vbl_end = (vbl >> 16) & 0x1fff;
1945926deccbSFrançois Tigeot }
1946926deccbSFrançois Tigeot else {
1947926deccbSFrançois Tigeot /* No: Fake something reasonable which gives at least ok results. */
1948c59a5c48SFrançois Tigeot vbl_start = mode->crtc_vdisplay;
1949926deccbSFrançois Tigeot vbl_end = 0;
1950926deccbSFrançois Tigeot }
1951926deccbSFrançois Tigeot
1952c59a5c48SFrançois Tigeot /* Called from driver internal vblank counter query code? */
1953c59a5c48SFrançois Tigeot if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1954c59a5c48SFrançois Tigeot /* Caller wants distance from real vbl_start in *hpos */
1955c59a5c48SFrançois Tigeot *hpos = *vpos - vbl_start;
1956c59a5c48SFrançois Tigeot }
1957c59a5c48SFrançois Tigeot
1958c59a5c48SFrançois Tigeot /* Fudge vblank to start a few scanlines earlier to handle the
1959c59a5c48SFrançois Tigeot * problem that vblank irqs fire a few scanlines before start
1960c59a5c48SFrançois Tigeot * of vblank. Some driver internal callers need the true vblank
1961c59a5c48SFrançois Tigeot * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1962c59a5c48SFrançois Tigeot *
1963c59a5c48SFrançois Tigeot * The cause of the "early" vblank irq is that the irq is triggered
1964c59a5c48SFrançois Tigeot * by the line buffer logic when the line buffer read position enters
1965c59a5c48SFrançois Tigeot * the vblank, whereas our crtc scanout position naturally lags the
1966c59a5c48SFrançois Tigeot * line buffer read position.
1967c59a5c48SFrançois Tigeot */
1968c59a5c48SFrançois Tigeot if (!(flags & USE_REAL_VBLANKSTART))
1969c59a5c48SFrançois Tigeot vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1970c59a5c48SFrançois Tigeot
1971926deccbSFrançois Tigeot /* Test scanout position against vblank region. */
1972926deccbSFrançois Tigeot if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1973926deccbSFrançois Tigeot in_vbl = false;
1974926deccbSFrançois Tigeot
1975c59a5c48SFrançois Tigeot /* In vblank? */
1976c59a5c48SFrançois Tigeot if (in_vbl)
1977c59a5c48SFrançois Tigeot ret |= DRM_SCANOUTPOS_IN_VBLANK;
1978c59a5c48SFrançois Tigeot
1979c59a5c48SFrançois Tigeot /* Called from driver internal vblank counter query code? */
1980c59a5c48SFrançois Tigeot if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1981c59a5c48SFrançois Tigeot /* Caller wants distance from fudged earlier vbl_start */
1982c59a5c48SFrançois Tigeot *vpos -= vbl_start;
1983c59a5c48SFrançois Tigeot return ret;
1984c59a5c48SFrançois Tigeot }
1985c59a5c48SFrançois Tigeot
1986926deccbSFrançois Tigeot /* Check if inside vblank area and apply corrective offsets:
1987926deccbSFrançois Tigeot * vpos will then be >=0 in video scanout area, but negative
1988926deccbSFrançois Tigeot * within vblank area, counting down the number of lines until
1989926deccbSFrançois Tigeot * start of scanout.
1990926deccbSFrançois Tigeot */
1991926deccbSFrançois Tigeot
1992926deccbSFrançois Tigeot /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1993926deccbSFrançois Tigeot if (in_vbl && (*vpos >= vbl_start)) {
1994c59a5c48SFrançois Tigeot vtotal = mode->crtc_vtotal;
1995926deccbSFrançois Tigeot *vpos = *vpos - vtotal;
1996926deccbSFrançois Tigeot }
1997926deccbSFrançois Tigeot
1998926deccbSFrançois Tigeot /* Correct for shifted end of vbl at vbl_end. */
1999926deccbSFrançois Tigeot *vpos = *vpos - vbl_end;
2000926deccbSFrançois Tigeot
2001926deccbSFrançois Tigeot return ret;
2002926deccbSFrançois Tigeot }
2003