1926deccbSFrançois Tigeot /* 2926deccbSFrançois Tigeot * Copyright 2007-8 Advanced Micro Devices, Inc. 3926deccbSFrançois Tigeot * Copyright 2008 Red Hat Inc. 4926deccbSFrançois Tigeot * 5926deccbSFrançois Tigeot * Permission is hereby granted, free of charge, to any person obtaining a 6926deccbSFrançois Tigeot * copy of this software and associated documentation files (the "Software"), 7926deccbSFrançois Tigeot * to deal in the Software without restriction, including without limitation 8926deccbSFrançois Tigeot * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9926deccbSFrançois Tigeot * and/or sell copies of the Software, and to permit persons to whom the 10926deccbSFrançois Tigeot * Software is furnished to do so, subject to the following conditions: 11926deccbSFrançois Tigeot * 12926deccbSFrançois Tigeot * The above copyright notice and this permission notice shall be included in 13926deccbSFrançois Tigeot * all copies or substantial portions of the Software. 14926deccbSFrançois Tigeot * 15926deccbSFrançois Tigeot * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16926deccbSFrançois Tigeot * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17926deccbSFrançois Tigeot * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18926deccbSFrançois Tigeot * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19926deccbSFrançois Tigeot * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20926deccbSFrançois Tigeot * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21926deccbSFrançois Tigeot * OTHER DEALINGS IN THE SOFTWARE. 22926deccbSFrançois Tigeot * 23926deccbSFrançois Tigeot * Authors: Dave Airlie 24926deccbSFrançois Tigeot * Alex Deucher 25926deccbSFrançois Tigeot */ 26926deccbSFrançois Tigeot #include <drm/drmP.h> 2783b4b9b9SFrançois Tigeot #include <drm/radeon_drm.h> 28926deccbSFrançois Tigeot #include "radeon.h" 29926deccbSFrançois Tigeot 30926deccbSFrançois Tigeot #include "atom.h" 31926deccbSFrançois Tigeot 32c6f73aabSFrançois Tigeot #include <linux/pm_runtime.h> 33926deccbSFrançois Tigeot #include <drm/drm_crtc_helper.h> 342c9916cdSFrançois Tigeot #include <drm/drm_plane_helper.h> 35926deccbSFrançois Tigeot #include <drm/drm_edid.h> 36926deccbSFrançois Tigeot 37c6f73aabSFrançois Tigeot #include <linux/gcd.h> 38c6f73aabSFrançois Tigeot 39926deccbSFrançois Tigeot static void avivo_crtc_load_lut(struct drm_crtc *crtc) 40926deccbSFrançois Tigeot { 41926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 42926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev; 43926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 44926deccbSFrançois Tigeot int i; 45926deccbSFrançois Tigeot 46926deccbSFrançois Tigeot DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 47926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); 48926deccbSFrançois Tigeot 49926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 50926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 51926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 52926deccbSFrançois Tigeot 53926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 54926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 55926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 56926deccbSFrançois Tigeot 57926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); 58926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUT_RW_MODE, 0); 59926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); 60926deccbSFrançois Tigeot 61926deccbSFrançois Tigeot WREG8(AVIVO_DC_LUT_RW_INDEX, 0); 62926deccbSFrançois Tigeot for (i = 0; i < 256; i++) { 63926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUT_30_COLOR, 64926deccbSFrançois Tigeot (radeon_crtc->lut_r[i] << 20) | 65926deccbSFrançois Tigeot (radeon_crtc->lut_g[i] << 10) | 66926deccbSFrançois Tigeot (radeon_crtc->lut_b[i] << 0)); 67926deccbSFrançois Tigeot } 68926deccbSFrançois Tigeot 69c6f73aabSFrançois Tigeot /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */ 70c6f73aabSFrançois Tigeot WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1); 71926deccbSFrançois Tigeot } 72926deccbSFrançois Tigeot 73926deccbSFrançois Tigeot static void dce4_crtc_load_lut(struct drm_crtc *crtc) 74926deccbSFrançois Tigeot { 75926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 76926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev; 77926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 78926deccbSFrançois Tigeot int i; 79926deccbSFrançois Tigeot 80926deccbSFrançois Tigeot DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 81926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 82926deccbSFrançois Tigeot 83926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 84926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 85926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 86926deccbSFrançois Tigeot 87926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 88926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 89926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 90926deccbSFrançois Tigeot 91926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 92926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 93926deccbSFrançois Tigeot 94926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 95926deccbSFrançois Tigeot for (i = 0; i < 256; i++) { 96926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 97926deccbSFrançois Tigeot (radeon_crtc->lut_r[i] << 20) | 98926deccbSFrançois Tigeot (radeon_crtc->lut_g[i] << 10) | 99926deccbSFrançois Tigeot (radeon_crtc->lut_b[i] << 0)); 100926deccbSFrançois Tigeot } 101926deccbSFrançois Tigeot } 102926deccbSFrançois Tigeot 103926deccbSFrançois Tigeot static void dce5_crtc_load_lut(struct drm_crtc *crtc) 104926deccbSFrançois Tigeot { 105926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 106926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev; 107926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 108926deccbSFrançois Tigeot int i; 109926deccbSFrançois Tigeot 110926deccbSFrançois Tigeot DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 111926deccbSFrançois Tigeot 112926deccbSFrançois Tigeot WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 113926deccbSFrançois Tigeot (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | 114926deccbSFrançois Tigeot NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); 115926deccbSFrançois Tigeot WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, 116926deccbSFrançois Tigeot NI_GRPH_PRESCALE_BYPASS); 117926deccbSFrançois Tigeot WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, 118926deccbSFrançois Tigeot NI_OVL_PRESCALE_BYPASS); 119926deccbSFrançois Tigeot WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, 120926deccbSFrançois Tigeot (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | 121926deccbSFrançois Tigeot NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); 122926deccbSFrançois Tigeot 123926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 124926deccbSFrançois Tigeot 125926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 126926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 127926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 128926deccbSFrançois Tigeot 129926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 130926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 131926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 132926deccbSFrançois Tigeot 133926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 134926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 135926deccbSFrançois Tigeot 136926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 137926deccbSFrançois Tigeot for (i = 0; i < 256; i++) { 138926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 139926deccbSFrançois Tigeot (radeon_crtc->lut_r[i] << 20) | 140926deccbSFrançois Tigeot (radeon_crtc->lut_g[i] << 10) | 141926deccbSFrançois Tigeot (radeon_crtc->lut_b[i] << 0)); 142926deccbSFrançois Tigeot } 143926deccbSFrançois Tigeot 144926deccbSFrançois Tigeot WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, 145926deccbSFrançois Tigeot (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 146926deccbSFrançois Tigeot NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 147926deccbSFrançois Tigeot NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 148926deccbSFrançois Tigeot NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); 149926deccbSFrançois Tigeot WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, 150926deccbSFrançois Tigeot (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | 151926deccbSFrançois Tigeot NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); 152926deccbSFrançois Tigeot WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, 153926deccbSFrançois Tigeot (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | 154926deccbSFrançois Tigeot NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); 155926deccbSFrançois Tigeot WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 156c59a5c48SFrançois Tigeot (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) | 157926deccbSFrançois Tigeot NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); 158926deccbSFrançois Tigeot /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 159926deccbSFrançois Tigeot WREG32(0x6940 + radeon_crtc->crtc_offset, 0); 16057e252bfSMichael Neumann if (ASIC_IS_DCE8(rdev)) { 16157e252bfSMichael Neumann /* XXX this only needs to be programmed once per crtc at startup, 16257e252bfSMichael Neumann * not sure where the best place for it is 16357e252bfSMichael Neumann */ 16457e252bfSMichael Neumann WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset, 16557e252bfSMichael Neumann CIK_CURSOR_ALPHA_BLND_ENA); 16657e252bfSMichael Neumann } 167926deccbSFrançois Tigeot } 168926deccbSFrançois Tigeot 169926deccbSFrançois Tigeot static void legacy_crtc_load_lut(struct drm_crtc *crtc) 170926deccbSFrançois Tigeot { 171926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 172926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev; 173926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 174926deccbSFrançois Tigeot int i; 175926deccbSFrançois Tigeot uint32_t dac2_cntl; 176926deccbSFrançois Tigeot 177926deccbSFrançois Tigeot dac2_cntl = RREG32(RADEON_DAC_CNTL2); 178926deccbSFrançois Tigeot if (radeon_crtc->crtc_id == 0) 179926deccbSFrançois Tigeot dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; 180926deccbSFrançois Tigeot else 181926deccbSFrançois Tigeot dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; 182926deccbSFrançois Tigeot WREG32(RADEON_DAC_CNTL2, dac2_cntl); 183926deccbSFrançois Tigeot 184926deccbSFrançois Tigeot WREG8(RADEON_PALETTE_INDEX, 0); 185926deccbSFrançois Tigeot for (i = 0; i < 256; i++) { 186926deccbSFrançois Tigeot WREG32(RADEON_PALETTE_30_DATA, 187926deccbSFrançois Tigeot (radeon_crtc->lut_r[i] << 20) | 188926deccbSFrançois Tigeot (radeon_crtc->lut_g[i] << 10) | 189926deccbSFrançois Tigeot (radeon_crtc->lut_b[i] << 0)); 190926deccbSFrançois Tigeot } 191926deccbSFrançois Tigeot } 192926deccbSFrançois Tigeot 193926deccbSFrançois Tigeot void radeon_crtc_load_lut(struct drm_crtc *crtc) 194926deccbSFrançois Tigeot { 195926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev; 196926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 197926deccbSFrançois Tigeot 198926deccbSFrançois Tigeot if (!crtc->enabled) 199926deccbSFrançois Tigeot return; 200926deccbSFrançois Tigeot 201926deccbSFrançois Tigeot if (ASIC_IS_DCE5(rdev)) 202926deccbSFrançois Tigeot dce5_crtc_load_lut(crtc); 203926deccbSFrançois Tigeot else if (ASIC_IS_DCE4(rdev)) 204926deccbSFrançois Tigeot dce4_crtc_load_lut(crtc); 205926deccbSFrançois Tigeot else if (ASIC_IS_AVIVO(rdev)) 206926deccbSFrançois Tigeot avivo_crtc_load_lut(crtc); 207926deccbSFrançois Tigeot else 208926deccbSFrançois Tigeot legacy_crtc_load_lut(crtc); 209926deccbSFrançois Tigeot } 210926deccbSFrançois Tigeot 211926deccbSFrançois Tigeot /** Sets the color ramps on behalf of fbcon */ 212926deccbSFrançois Tigeot void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 213926deccbSFrançois Tigeot u16 blue, int regno) 214926deccbSFrançois Tigeot { 215926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 216926deccbSFrançois Tigeot 217926deccbSFrançois Tigeot radeon_crtc->lut_r[regno] = red >> 6; 218926deccbSFrançois Tigeot radeon_crtc->lut_g[regno] = green >> 6; 219926deccbSFrançois Tigeot radeon_crtc->lut_b[regno] = blue >> 6; 220926deccbSFrançois Tigeot } 221926deccbSFrançois Tigeot 222926deccbSFrançois Tigeot /** Gets the color ramps on behalf of fbcon */ 223926deccbSFrançois Tigeot void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 224926deccbSFrançois Tigeot u16 *blue, int regno) 225926deccbSFrançois Tigeot { 226926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 227926deccbSFrançois Tigeot 228926deccbSFrançois Tigeot *red = radeon_crtc->lut_r[regno] << 6; 229926deccbSFrançois Tigeot *green = radeon_crtc->lut_g[regno] << 6; 230926deccbSFrançois Tigeot *blue = radeon_crtc->lut_b[regno] << 6; 231926deccbSFrançois Tigeot } 232926deccbSFrançois Tigeot 2331dedbd3bSFrançois Tigeot static int radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2341dedbd3bSFrançois Tigeot u16 *blue, uint32_t size) 235926deccbSFrançois Tigeot { 236926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 2371dedbd3bSFrançois Tigeot int i; 238926deccbSFrançois Tigeot 239926deccbSFrançois Tigeot /* userspace palettes are always correct as is */ 2401dedbd3bSFrançois Tigeot for (i = 0; i < size; i++) { 241926deccbSFrançois Tigeot radeon_crtc->lut_r[i] = red[i] >> 6; 242926deccbSFrançois Tigeot radeon_crtc->lut_g[i] = green[i] >> 6; 243926deccbSFrançois Tigeot radeon_crtc->lut_b[i] = blue[i] >> 6; 244926deccbSFrançois Tigeot } 245926deccbSFrançois Tigeot radeon_crtc_load_lut(crtc); 2461dedbd3bSFrançois Tigeot 2471dedbd3bSFrançois Tigeot return 0; 248926deccbSFrançois Tigeot } 249926deccbSFrançois Tigeot 250926deccbSFrançois Tigeot static void radeon_crtc_destroy(struct drm_crtc *crtc) 251926deccbSFrançois Tigeot { 252926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 253926deccbSFrançois Tigeot 254926deccbSFrançois Tigeot drm_crtc_cleanup(crtc); 255c6f73aabSFrançois Tigeot destroy_workqueue(radeon_crtc->flip_queue); 256c4ef309bSzrj kfree(radeon_crtc); 257926deccbSFrançois Tigeot } 258926deccbSFrançois Tigeot 259c6f73aabSFrançois Tigeot /** 260c6f73aabSFrançois Tigeot * radeon_unpin_work_func - unpin old buffer object 261c6f73aabSFrançois Tigeot * 262c6f73aabSFrançois Tigeot * @__work - kernel work item 263c6f73aabSFrançois Tigeot * 264c6f73aabSFrançois Tigeot * Unpin the old frame buffer object outside of the interrupt handler 265926deccbSFrançois Tigeot */ 266c6f73aabSFrançois Tigeot static void radeon_unpin_work_func(struct work_struct *__work) 267926deccbSFrançois Tigeot { 268c6f73aabSFrançois Tigeot struct radeon_flip_work *work = 269c6f73aabSFrançois Tigeot container_of(__work, struct radeon_flip_work, unpin_work); 270926deccbSFrançois Tigeot int r; 271926deccbSFrançois Tigeot 272926deccbSFrançois Tigeot /* unpin of the old buffer */ 273926deccbSFrançois Tigeot r = radeon_bo_reserve(work->old_rbo, false); 274926deccbSFrançois Tigeot if (likely(r == 0)) { 275926deccbSFrançois Tigeot r = radeon_bo_unpin(work->old_rbo); 276926deccbSFrançois Tigeot if (unlikely(r != 0)) { 277926deccbSFrançois Tigeot DRM_ERROR("failed to unpin buffer after flip\n"); 278926deccbSFrançois Tigeot } 279926deccbSFrançois Tigeot radeon_bo_unreserve(work->old_rbo); 280926deccbSFrançois Tigeot } else 281926deccbSFrançois Tigeot DRM_ERROR("failed to reserve buffer after flip\n"); 282926deccbSFrançois Tigeot 283926deccbSFrançois Tigeot drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 284c4ef309bSzrj kfree(work); 285926deccbSFrançois Tigeot } 286926deccbSFrançois Tigeot 287c6f73aabSFrançois Tigeot void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id) 288926deccbSFrançois Tigeot { 289926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 2907dcf36dcSFrançois Tigeot unsigned long flags; 291926deccbSFrançois Tigeot u32 update_pending; 292926deccbSFrançois Tigeot int vpos, hpos; 293926deccbSFrançois Tigeot 294c6f73aabSFrançois Tigeot /* can happen during initialization */ 295c6f73aabSFrançois Tigeot if (radeon_crtc == NULL) 296c6f73aabSFrançois Tigeot return; 297c6f73aabSFrançois Tigeot 298c6f73aabSFrançois Tigeot /* Skip the pageflip completion check below (based on polling) on 299c6f73aabSFrançois Tigeot * asics which reliably support hw pageflip completion irqs. pflip 300c6f73aabSFrançois Tigeot * irqs are a reliable and race-free method of handling pageflip 301c6f73aabSFrançois Tigeot * completion detection. A use_pflipirq module parameter < 2 allows 302c6f73aabSFrançois Tigeot * to override this in case of asics with faulty pflip irqs. 303c6f73aabSFrançois Tigeot * A module parameter of 0 would only use this polling based path, 304c6f73aabSFrançois Tigeot * a parameter of 1 would use pflip irq only as a backup to this 305c6f73aabSFrançois Tigeot * path, as in Linux 3.16. 306c6f73aabSFrançois Tigeot */ 307c6f73aabSFrançois Tigeot if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev)) 308c6f73aabSFrançois Tigeot return; 309c6f73aabSFrançois Tigeot 3107dcf36dcSFrançois Tigeot spin_lock_irqsave(&rdev->ddev->event_lock, flags); 311c6f73aabSFrançois Tigeot if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 312c6f73aabSFrançois Tigeot DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 313c6f73aabSFrançois Tigeot "RADEON_FLIP_SUBMITTED(%d)\n", 314c6f73aabSFrançois Tigeot radeon_crtc->flip_status, 315c6f73aabSFrançois Tigeot RADEON_FLIP_SUBMITTED); 3167dcf36dcSFrançois Tigeot spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 317926deccbSFrançois Tigeot return; 318926deccbSFrançois Tigeot } 319c6f73aabSFrançois Tigeot 320c6f73aabSFrançois Tigeot update_pending = radeon_page_flip_pending(rdev, crtc_id); 321926deccbSFrançois Tigeot 322926deccbSFrançois Tigeot /* Has the pageflip already completed in crtc, or is it certain 3231dedbd3bSFrançois Tigeot * to complete in this vblank? GET_DISTANCE_TO_VBLANKSTART provides 3241dedbd3bSFrançois Tigeot * distance to start of "fudged earlier" vblank in vpos, distance to 3251dedbd3bSFrançois Tigeot * start of real vblank in hpos. vpos >= 0 && hpos < 0 means we are in 3261dedbd3bSFrançois Tigeot * the last few scanlines before start of real vblank, where the vblank 3271dedbd3bSFrançois Tigeot * irq can fire, so we have sampled update_pending a bit too early and 3281dedbd3bSFrançois Tigeot * know the flip will complete at leading edge of the upcoming real 3291dedbd3bSFrançois Tigeot * vblank. On pre-AVIVO hardware, flips also complete inside the real 3301dedbd3bSFrançois Tigeot * vblank, not only at leading edge, so if update_pending for hpos >= 0 3311dedbd3bSFrançois Tigeot * == inside real vblank, the flip will complete almost immediately. 3321dedbd3bSFrançois Tigeot * Note that this method of completion handling is still not 100% race 3331dedbd3bSFrançois Tigeot * free, as we could execute before the radeon_flip_work_func managed 3341dedbd3bSFrançois Tigeot * to run and set the RADEON_FLIP_SUBMITTED status, thereby we no-op, 3351dedbd3bSFrançois Tigeot * but the flip still gets programmed into hw and completed during 3361dedbd3bSFrançois Tigeot * vblank, leading to a delayed emission of the flip completion event. 3371dedbd3bSFrançois Tigeot * This applies at least to pre-AVIVO hardware, where flips are always 3381dedbd3bSFrançois Tigeot * completing inside vblank, not only at leading edge of vblank. 339926deccbSFrançois Tigeot */ 340926deccbSFrançois Tigeot if (update_pending && 3411dedbd3bSFrançois Tigeot (DRM_SCANOUTPOS_VALID & 3421dedbd3bSFrançois Tigeot radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 3431dedbd3bSFrançois Tigeot GET_DISTANCE_TO_VBLANKSTART, 344352ff8bdSFrançois Tigeot &vpos, &hpos, NULL, NULL, 345352ff8bdSFrançois Tigeot &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) && 3461dedbd3bSFrançois Tigeot ((vpos >= 0 && hpos < 0) || (hpos >= 0 && !ASIC_IS_AVIVO(rdev)))) { 347926deccbSFrançois Tigeot /* crtc didn't flip in this target vblank interval, 348926deccbSFrançois Tigeot * but flip is pending in crtc. Based on the current 349926deccbSFrançois Tigeot * scanout position we know that the current frame is 350926deccbSFrançois Tigeot * (nearly) complete and the flip will (likely) 351926deccbSFrançois Tigeot * complete before the start of the next frame. 352926deccbSFrançois Tigeot */ 353926deccbSFrançois Tigeot update_pending = 0; 354926deccbSFrançois Tigeot } 3557dcf36dcSFrançois Tigeot spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 356c6f73aabSFrançois Tigeot if (!update_pending) 357c6f73aabSFrançois Tigeot radeon_crtc_handle_flip(rdev, crtc_id); 358c6f73aabSFrançois Tigeot } 359c6f73aabSFrançois Tigeot 360c6f73aabSFrançois Tigeot /** 361c6f73aabSFrançois Tigeot * radeon_crtc_handle_flip - page flip completed 362c6f73aabSFrançois Tigeot * 363c6f73aabSFrançois Tigeot * @rdev: radeon device pointer 364c6f73aabSFrançois Tigeot * @crtc_id: crtc number this event is for 365c6f73aabSFrançois Tigeot * 366c6f73aabSFrançois Tigeot * Called when we are sure that a page flip for this crtc is completed. 367926deccbSFrançois Tigeot */ 368c6f73aabSFrançois Tigeot void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) 369c6f73aabSFrançois Tigeot { 370c6f73aabSFrançois Tigeot struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 371c6f73aabSFrançois Tigeot struct radeon_flip_work *work; 3727dcf36dcSFrançois Tigeot unsigned long flags; 373c6f73aabSFrançois Tigeot 374c6f73aabSFrançois Tigeot /* this can happen at init */ 375c6f73aabSFrançois Tigeot if (radeon_crtc == NULL) 376c6f73aabSFrançois Tigeot return; 377c6f73aabSFrançois Tigeot 3787dcf36dcSFrançois Tigeot spin_lock_irqsave(&rdev->ddev->event_lock, flags); 379c6f73aabSFrançois Tigeot work = radeon_crtc->flip_work; 380c6f73aabSFrançois Tigeot if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 381c6f73aabSFrançois Tigeot DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 382c6f73aabSFrançois Tigeot "RADEON_FLIP_SUBMITTED(%d)\n", 383c6f73aabSFrançois Tigeot radeon_crtc->flip_status, 384c6f73aabSFrançois Tigeot RADEON_FLIP_SUBMITTED); 3857dcf36dcSFrançois Tigeot spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 386926deccbSFrançois Tigeot return; 387926deccbSFrançois Tigeot } 388926deccbSFrançois Tigeot 389c6f73aabSFrançois Tigeot /* Pageflip completed. Clean up. */ 390c6f73aabSFrançois Tigeot radeon_crtc->flip_status = RADEON_FLIP_NONE; 391c6f73aabSFrançois Tigeot radeon_crtc->flip_work = NULL; 392926deccbSFrançois Tigeot 393926deccbSFrançois Tigeot /* wakeup userspace */ 394f43cf1b1SMichael Neumann if (work->event) 395d78d3a22SFrançois Tigeot drm_crtc_send_vblank_event(&radeon_crtc->base, work->event); 396f43cf1b1SMichael Neumann 3977dcf36dcSFrançois Tigeot spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 398926deccbSFrançois Tigeot 3991dedbd3bSFrançois Tigeot drm_crtc_vblank_put(&radeon_crtc->base); 400c6f73aabSFrançois Tigeot radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id); 401c6f73aabSFrançois Tigeot queue_work(radeon_crtc->flip_queue, &work->unpin_work); 402c6f73aabSFrançois Tigeot } 403c6f73aabSFrançois Tigeot 404c6f73aabSFrançois Tigeot /** 405c6f73aabSFrançois Tigeot * radeon_flip_work_func - page flip framebuffer 406c6f73aabSFrançois Tigeot * 407c6f73aabSFrançois Tigeot * @work - kernel work item 408c6f73aabSFrançois Tigeot * 409c6f73aabSFrançois Tigeot * Wait for the buffer object to become idle and do the actual page flip 410c6f73aabSFrançois Tigeot */ 411c6f73aabSFrançois Tigeot static void radeon_flip_work_func(struct work_struct *__work) 412c6f73aabSFrançois Tigeot { 413c6f73aabSFrançois Tigeot struct radeon_flip_work *work = 414c6f73aabSFrançois Tigeot container_of(__work, struct radeon_flip_work, flip_work); 415c6f73aabSFrançois Tigeot struct radeon_device *rdev = work->rdev; 4161dedbd3bSFrançois Tigeot struct drm_device *dev = rdev->ddev; 417c6f73aabSFrançois Tigeot struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id]; 418c6f73aabSFrançois Tigeot 419c6f73aabSFrançois Tigeot struct drm_crtc *crtc = &radeon_crtc->base; 4207dcf36dcSFrançois Tigeot unsigned long flags; 421c6f73aabSFrançois Tigeot int r; 4221dedbd3bSFrançois Tigeot int vpos, hpos; 423c6f73aabSFrançois Tigeot 4247dcf36dcSFrançois Tigeot down_read(&rdev->exclusive_lock); 425c6f73aabSFrançois Tigeot if (work->fence) { 4267dcf36dcSFrançois Tigeot struct radeon_fence *fence; 4277dcf36dcSFrançois Tigeot 4287dcf36dcSFrançois Tigeot fence = to_radeon_fence(work->fence); 4297dcf36dcSFrançois Tigeot if (fence && fence->rdev == rdev) { 4307dcf36dcSFrançois Tigeot r = radeon_fence_wait(fence, false); 431c6f73aabSFrançois Tigeot if (r == -EDEADLK) { 4327dcf36dcSFrançois Tigeot up_read(&rdev->exclusive_lock); 433591d5043SFrançois Tigeot do { 434c6f73aabSFrançois Tigeot r = radeon_gpu_reset(rdev); 435591d5043SFrançois Tigeot } while (r == -EAGAIN); 4367dcf36dcSFrançois Tigeot down_read(&rdev->exclusive_lock); 437c6f73aabSFrançois Tigeot } 4387dcf36dcSFrançois Tigeot } else 439*6559babbSFrançois Tigeot r = dma_fence_wait(work->fence, false); 4407dcf36dcSFrançois Tigeot 441c6f73aabSFrançois Tigeot if (r) 442c6f73aabSFrançois Tigeot DRM_ERROR("failed to wait on page flip fence (%d)!\n", r); 443c6f73aabSFrançois Tigeot 444c6f73aabSFrançois Tigeot /* We continue with the page flip even if we failed to wait on 445c6f73aabSFrançois Tigeot * the fence, otherwise the DRM core and userspace will be 446c6f73aabSFrançois Tigeot * confused about which BO the CRTC is scanning out 447c6f73aabSFrançois Tigeot */ 448c6f73aabSFrançois Tigeot 449*6559babbSFrançois Tigeot dma_fence_put(work->fence); 4507dcf36dcSFrançois Tigeot work->fence = NULL; 451c6f73aabSFrançois Tigeot } 452c6f73aabSFrançois Tigeot 4531dedbd3bSFrançois Tigeot /* Wait until we're out of the vertical blank period before the one 4541dedbd3bSFrançois Tigeot * targeted by the flip. Always wait on pre DCE4 to avoid races with 4551dedbd3bSFrançois Tigeot * flip completion handling from vblank irq, as these old asics don't 4561dedbd3bSFrançois Tigeot * have reliable pageflip completion interrupts. 4571dedbd3bSFrançois Tigeot */ 4581dedbd3bSFrançois Tigeot while (radeon_crtc->enabled && 4591dedbd3bSFrançois Tigeot (radeon_get_crtc_scanoutpos(dev, work->crtc_id, 0, 4601dedbd3bSFrançois Tigeot &vpos, &hpos, NULL, NULL, 4611dedbd3bSFrançois Tigeot &crtc->hwmode) 4621dedbd3bSFrançois Tigeot & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 4631dedbd3bSFrançois Tigeot (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 4641dedbd3bSFrançois Tigeot (!ASIC_IS_AVIVO(rdev) || 4651dedbd3bSFrançois Tigeot ((int) (work->target_vblank - 4661dedbd3bSFrançois Tigeot dev->driver->get_vblank_counter(dev, work->crtc_id)) > 0))) 4671dedbd3bSFrançois Tigeot usleep_range(1000, 2000); 4681dedbd3bSFrançois Tigeot 469c6f73aabSFrançois Tigeot /* We borrow the event spin lock for protecting flip_status */ 4707dcf36dcSFrançois Tigeot spin_lock_irqsave(&crtc->dev->event_lock, flags); 471c6f73aabSFrançois Tigeot 472c6f73aabSFrançois Tigeot /* set the proper interrupt */ 473c6f73aabSFrançois Tigeot radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id); 474c6f73aabSFrançois Tigeot 475c6f73aabSFrançois Tigeot /* do the flip (mmio) */ 476d78d3a22SFrançois Tigeot radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async); 477c6f73aabSFrançois Tigeot 478c6f73aabSFrançois Tigeot radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED; 4797dcf36dcSFrançois Tigeot spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 4807dcf36dcSFrançois Tigeot up_read(&rdev->exclusive_lock); 481926deccbSFrançois Tigeot } 482926deccbSFrançois Tigeot 4831dedbd3bSFrançois Tigeot static int radeon_crtc_page_flip_target(struct drm_crtc *crtc, 484926deccbSFrançois Tigeot struct drm_framebuffer *fb, 4859edbd4a0SFrançois Tigeot struct drm_pending_vblank_event *event, 4861dedbd3bSFrançois Tigeot uint32_t page_flip_flags, 4871dedbd3bSFrançois Tigeot uint32_t target) 488926deccbSFrançois Tigeot { 489926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev; 490926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 491926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 492926deccbSFrançois Tigeot struct radeon_framebuffer *old_radeon_fb; 493926deccbSFrançois Tigeot struct radeon_framebuffer *new_radeon_fb; 494926deccbSFrançois Tigeot struct drm_gem_object *obj; 495c6f73aabSFrançois Tigeot struct radeon_flip_work *work; 496c6f73aabSFrançois Tigeot struct radeon_bo *new_rbo; 497c6f73aabSFrançois Tigeot uint32_t tiling_flags, pitch_pixels; 498c6f73aabSFrançois Tigeot uint64_t base; 4997dcf36dcSFrançois Tigeot unsigned long flags; 500926deccbSFrançois Tigeot int r; 501926deccbSFrançois Tigeot 502c4ef309bSzrj work = kzalloc(sizeof *work, GFP_KERNEL); 503926deccbSFrançois Tigeot if (work == NULL) 504926deccbSFrançois Tigeot return -ENOMEM; 505926deccbSFrançois Tigeot 506c6f73aabSFrançois Tigeot INIT_WORK(&work->flip_work, radeon_flip_work_func); 507c6f73aabSFrançois Tigeot INIT_WORK(&work->unpin_work, radeon_unpin_work_func); 508c6f73aabSFrançois Tigeot 509926deccbSFrançois Tigeot work->rdev = rdev; 510926deccbSFrançois Tigeot work->crtc_id = radeon_crtc->crtc_id; 511c6f73aabSFrançois Tigeot work->event = event; 512d78d3a22SFrançois Tigeot work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 513c6f73aabSFrançois Tigeot 514926deccbSFrançois Tigeot /* schedule unpin of the old buffer */ 515c6f73aabSFrançois Tigeot old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb); 516926deccbSFrançois Tigeot obj = old_radeon_fb->obj; 517c6f73aabSFrançois Tigeot 518926deccbSFrançois Tigeot /* take a reference to the old object */ 519926deccbSFrançois Tigeot drm_gem_object_reference(obj); 520c6f73aabSFrançois Tigeot work->old_rbo = gem_to_radeon_bo(obj); 521c6f73aabSFrançois Tigeot 522c6f73aabSFrançois Tigeot new_radeon_fb = to_radeon_framebuffer(fb); 523926deccbSFrançois Tigeot obj = new_radeon_fb->obj; 524c6f73aabSFrançois Tigeot new_rbo = gem_to_radeon_bo(obj); 525926deccbSFrançois Tigeot 526926deccbSFrançois Tigeot /* pin the new buffer */ 527c6f73aabSFrançois Tigeot DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n", 528c6f73aabSFrançois Tigeot work->old_rbo, new_rbo); 529926deccbSFrançois Tigeot 530c6f73aabSFrançois Tigeot r = radeon_bo_reserve(new_rbo, false); 531926deccbSFrançois Tigeot if (unlikely(r != 0)) { 532926deccbSFrançois Tigeot DRM_ERROR("failed to reserve new rbo buffer before flip\n"); 533c6f73aabSFrançois Tigeot goto cleanup; 534926deccbSFrançois Tigeot } 535926deccbSFrançois Tigeot /* Only 27 bit offset for legacy CRTC */ 536c6f73aabSFrançois Tigeot r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM, 537f77dbd6cSFrançois Tigeot ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, (u64 *)&base); 538926deccbSFrançois Tigeot if (unlikely(r != 0)) { 539c6f73aabSFrançois Tigeot radeon_bo_unreserve(new_rbo); 540926deccbSFrançois Tigeot r = -EINVAL; 541926deccbSFrançois Tigeot DRM_ERROR("failed to pin new rbo buffer before flip\n"); 542c6f73aabSFrançois Tigeot goto cleanup; 543926deccbSFrançois Tigeot } 544*6559babbSFrançois Tigeot work->fence = dma_fence_get(reservation_object_get_excl(new_rbo->tbo.resv)); 545c6f73aabSFrançois Tigeot radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); 546c6f73aabSFrançois Tigeot radeon_bo_unreserve(new_rbo); 547926deccbSFrançois Tigeot 548926deccbSFrançois Tigeot if (!ASIC_IS_AVIVO(rdev)) { 549926deccbSFrançois Tigeot /* crtc offset is from display base addr not FB location */ 550926deccbSFrançois Tigeot base -= radeon_crtc->legacy_display_base_addr; 551926deccbSFrançois Tigeot pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8); 552926deccbSFrançois Tigeot 553926deccbSFrançois Tigeot if (tiling_flags & RADEON_TILING_MACRO) { 554926deccbSFrançois Tigeot if (ASIC_IS_R300(rdev)) { 555926deccbSFrançois Tigeot base &= ~0x7ff; 556926deccbSFrançois Tigeot } else { 557926deccbSFrançois Tigeot int byteshift = fb->bits_per_pixel >> 4; 558926deccbSFrançois Tigeot int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11; 559926deccbSFrançois Tigeot base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8); 560926deccbSFrançois Tigeot } 561926deccbSFrançois Tigeot } else { 562926deccbSFrançois Tigeot int offset = crtc->y * pitch_pixels + crtc->x; 563926deccbSFrançois Tigeot switch (fb->bits_per_pixel) { 564926deccbSFrançois Tigeot case 8: 565926deccbSFrançois Tigeot default: 566926deccbSFrançois Tigeot offset *= 1; 567926deccbSFrançois Tigeot break; 568926deccbSFrançois Tigeot case 15: 569926deccbSFrançois Tigeot case 16: 570926deccbSFrançois Tigeot offset *= 2; 571926deccbSFrançois Tigeot break; 572926deccbSFrançois Tigeot case 24: 573926deccbSFrançois Tigeot offset *= 3; 574926deccbSFrançois Tigeot break; 575926deccbSFrançois Tigeot case 32: 576926deccbSFrançois Tigeot offset *= 4; 577926deccbSFrançois Tigeot break; 578926deccbSFrançois Tigeot } 579926deccbSFrançois Tigeot base += offset; 580926deccbSFrançois Tigeot } 581926deccbSFrançois Tigeot base &= ~7; 582926deccbSFrançois Tigeot } 583c6f73aabSFrançois Tigeot work->base = base; 5841dedbd3bSFrançois Tigeot work->target_vblank = target - drm_crtc_vblank_count(crtc) + 5851dedbd3bSFrançois Tigeot dev->driver->get_vblank_counter(dev, work->crtc_id); 586c6f73aabSFrançois Tigeot 587c6f73aabSFrançois Tigeot /* We borrow the event spin lock for protecting flip_work */ 5887dcf36dcSFrançois Tigeot spin_lock_irqsave(&crtc->dev->event_lock, flags); 589c6f73aabSFrançois Tigeot 590c6f73aabSFrançois Tigeot if (radeon_crtc->flip_status != RADEON_FLIP_NONE) { 591c6f73aabSFrançois Tigeot DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 5927dcf36dcSFrançois Tigeot spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 593c6f73aabSFrançois Tigeot r = -EBUSY; 5941dedbd3bSFrançois Tigeot goto pflip_cleanup; 595c6f73aabSFrançois Tigeot } 596c6f73aabSFrançois Tigeot radeon_crtc->flip_status = RADEON_FLIP_PENDING; 597c6f73aabSFrançois Tigeot radeon_crtc->flip_work = work; 598926deccbSFrançois Tigeot 599926deccbSFrançois Tigeot /* update crtc fb */ 600ba55f2f5SFrançois Tigeot crtc->primary->fb = fb; 601926deccbSFrançois Tigeot 6027dcf36dcSFrançois Tigeot spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 603926deccbSFrançois Tigeot 604c6f73aabSFrançois Tigeot queue_work(radeon_crtc->flip_queue, &work->flip_work); 605926deccbSFrançois Tigeot return 0; 606926deccbSFrançois Tigeot 607926deccbSFrançois Tigeot pflip_cleanup: 608c6f73aabSFrançois Tigeot if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) { 609c6f73aabSFrançois Tigeot DRM_ERROR("failed to reserve new rbo in error path\n"); 610c6f73aabSFrançois Tigeot goto cleanup; 611c6f73aabSFrançois Tigeot } 612c6f73aabSFrançois Tigeot if (unlikely(radeon_bo_unpin(new_rbo) != 0)) { 613c6f73aabSFrançois Tigeot DRM_ERROR("failed to unpin new rbo in error path\n"); 614c6f73aabSFrançois Tigeot } 615c6f73aabSFrançois Tigeot radeon_bo_unreserve(new_rbo); 616c6f73aabSFrançois Tigeot 617c6f73aabSFrançois Tigeot cleanup: 618c6f73aabSFrançois Tigeot drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 619*6559babbSFrançois Tigeot dma_fence_put(work->fence); 620c4ef309bSzrj kfree(work); 621926deccbSFrançois Tigeot return r; 622926deccbSFrançois Tigeot } 623926deccbSFrançois Tigeot 624c6f73aabSFrançois Tigeot static int 625c6f73aabSFrançois Tigeot radeon_crtc_set_config(struct drm_mode_set *set) 626c6f73aabSFrançois Tigeot { 627c6f73aabSFrançois Tigeot struct drm_device *dev; 628c6f73aabSFrançois Tigeot struct radeon_device *rdev; 629c6f73aabSFrançois Tigeot struct drm_crtc *crtc; 630c6f73aabSFrançois Tigeot bool active = false; 631c6f73aabSFrançois Tigeot int ret; 632c6f73aabSFrançois Tigeot 633c6f73aabSFrançois Tigeot if (!set || !set->crtc) 634c6f73aabSFrançois Tigeot return -EINVAL; 635c6f73aabSFrançois Tigeot 636c6f73aabSFrançois Tigeot dev = set->crtc->dev; 637c6f73aabSFrançois Tigeot 638c6f73aabSFrançois Tigeot #ifdef PM_TODO 639c6f73aabSFrançois Tigeot ret = pm_runtime_get_sync(dev->dev); 640c6f73aabSFrançois Tigeot if (ret < 0) 641c6f73aabSFrançois Tigeot return ret; 642c6f73aabSFrançois Tigeot #endif 643c6f73aabSFrançois Tigeot 644c6f73aabSFrançois Tigeot ret = drm_crtc_helper_set_config(set); 645c6f73aabSFrançois Tigeot 646c6f73aabSFrançois Tigeot list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 647c6f73aabSFrançois Tigeot if (crtc->enabled) 648c6f73aabSFrançois Tigeot active = true; 649c6f73aabSFrançois Tigeot 650c6f73aabSFrançois Tigeot #ifdef PM_TODO 651c6f73aabSFrançois Tigeot pm_runtime_mark_last_busy(dev->dev); 652c6f73aabSFrançois Tigeot #endif 653c6f73aabSFrançois Tigeot 654c6f73aabSFrançois Tigeot rdev = dev->dev_private; 655c6f73aabSFrançois Tigeot /* if we have active crtcs and we don't have a power ref, 656c6f73aabSFrançois Tigeot take the current one */ 657c6f73aabSFrançois Tigeot if (active && !rdev->have_disp_power_ref) { 658c6f73aabSFrançois Tigeot rdev->have_disp_power_ref = true; 659c6f73aabSFrançois Tigeot return ret; 660c6f73aabSFrançois Tigeot } 661c6f73aabSFrançois Tigeot /* if we have no active crtcs, then drop the power ref 662c6f73aabSFrançois Tigeot we got before */ 663c6f73aabSFrançois Tigeot if (!active && rdev->have_disp_power_ref) { 664c6f73aabSFrançois Tigeot #ifdef PM_TODO 665c6f73aabSFrançois Tigeot pm_runtime_put_autosuspend(dev->dev); 666c6f73aabSFrançois Tigeot #endif 667c6f73aabSFrançois Tigeot rdev->have_disp_power_ref = false; 668c6f73aabSFrançois Tigeot } 669c6f73aabSFrançois Tigeot 670c6f73aabSFrançois Tigeot /* drop the power reference we got coming in here */ 671c6f73aabSFrançois Tigeot #ifdef PM_TODO 672c6f73aabSFrançois Tigeot pm_runtime_put_autosuspend(dev->dev); 673c6f73aabSFrançois Tigeot #endif 674c6f73aabSFrançois Tigeot return ret; 675c6f73aabSFrançois Tigeot } 6761dedbd3bSFrançois Tigeot 677926deccbSFrançois Tigeot static const struct drm_crtc_funcs radeon_crtc_funcs = { 6787dcf36dcSFrançois Tigeot .cursor_set2 = radeon_crtc_cursor_set2, 679926deccbSFrançois Tigeot .cursor_move = radeon_crtc_cursor_move, 680926deccbSFrançois Tigeot .gamma_set = radeon_crtc_gamma_set, 681c6f73aabSFrançois Tigeot .set_config = radeon_crtc_set_config, 682926deccbSFrançois Tigeot .destroy = radeon_crtc_destroy, 6831dedbd3bSFrançois Tigeot .page_flip_target = radeon_crtc_page_flip_target, 684926deccbSFrançois Tigeot }; 685926deccbSFrançois Tigeot 686926deccbSFrançois Tigeot static void radeon_crtc_init(struct drm_device *dev, int index) 687926deccbSFrançois Tigeot { 688926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 689926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc; 690926deccbSFrançois Tigeot int i; 691926deccbSFrançois Tigeot 692c4ef309bSzrj radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 693926deccbSFrançois Tigeot if (radeon_crtc == NULL) 694926deccbSFrançois Tigeot return; 695926deccbSFrançois Tigeot 696926deccbSFrançois Tigeot drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); 697926deccbSFrançois Tigeot 698926deccbSFrançois Tigeot drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); 699926deccbSFrançois Tigeot radeon_crtc->crtc_id = index; 7001dedbd3bSFrançois Tigeot radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0); 701926deccbSFrançois Tigeot rdev->mode_info.crtcs[index] = radeon_crtc; 702926deccbSFrançois Tigeot 70357e252bfSMichael Neumann if (rdev->family >= CHIP_BONAIRE) { 70457e252bfSMichael Neumann radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH; 70557e252bfSMichael Neumann radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT; 70657e252bfSMichael Neumann } else { 70757e252bfSMichael Neumann radeon_crtc->max_cursor_width = CURSOR_WIDTH; 70857e252bfSMichael Neumann radeon_crtc->max_cursor_height = CURSOR_HEIGHT; 70957e252bfSMichael Neumann } 710c6f73aabSFrançois Tigeot dev->mode_config.cursor_width = radeon_crtc->max_cursor_width; 711c6f73aabSFrançois Tigeot dev->mode_config.cursor_height = radeon_crtc->max_cursor_height; 71257e252bfSMichael Neumann 713926deccbSFrançois Tigeot #if 0 714926deccbSFrançois Tigeot radeon_crtc->mode_set.crtc = &radeon_crtc->base; 715926deccbSFrançois Tigeot radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); 716926deccbSFrançois Tigeot radeon_crtc->mode_set.num_connectors = 0; 717926deccbSFrançois Tigeot #endif 718926deccbSFrançois Tigeot 719926deccbSFrançois Tigeot for (i = 0; i < 256; i++) { 720926deccbSFrançois Tigeot radeon_crtc->lut_r[i] = i << 2; 721926deccbSFrançois Tigeot radeon_crtc->lut_g[i] = i << 2; 722926deccbSFrançois Tigeot radeon_crtc->lut_b[i] = i << 2; 723926deccbSFrançois Tigeot } 724926deccbSFrançois Tigeot 725926deccbSFrançois Tigeot if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) 726926deccbSFrançois Tigeot radeon_atombios_init_crtc(dev, radeon_crtc); 727926deccbSFrançois Tigeot else 728926deccbSFrançois Tigeot radeon_legacy_init_crtc(dev, radeon_crtc); 729926deccbSFrançois Tigeot } 730926deccbSFrançois Tigeot 73157e252bfSMichael Neumann static const char *encoder_names[38] = { 732926deccbSFrançois Tigeot "NONE", 733926deccbSFrançois Tigeot "INTERNAL_LVDS", 734926deccbSFrançois Tigeot "INTERNAL_TMDS1", 735926deccbSFrançois Tigeot "INTERNAL_TMDS2", 736926deccbSFrançois Tigeot "INTERNAL_DAC1", 737926deccbSFrançois Tigeot "INTERNAL_DAC2", 738926deccbSFrançois Tigeot "INTERNAL_SDVOA", 739926deccbSFrançois Tigeot "INTERNAL_SDVOB", 740926deccbSFrançois Tigeot "SI170B", 741926deccbSFrançois Tigeot "CH7303", 742926deccbSFrançois Tigeot "CH7301", 743926deccbSFrançois Tigeot "INTERNAL_DVO1", 744926deccbSFrançois Tigeot "EXTERNAL_SDVOA", 745926deccbSFrançois Tigeot "EXTERNAL_SDVOB", 746926deccbSFrançois Tigeot "TITFP513", 747926deccbSFrançois Tigeot "INTERNAL_LVTM1", 748926deccbSFrançois Tigeot "VT1623", 749926deccbSFrançois Tigeot "HDMI_SI1930", 750926deccbSFrançois Tigeot "HDMI_INTERNAL", 751926deccbSFrançois Tigeot "INTERNAL_KLDSCP_TMDS1", 752926deccbSFrançois Tigeot "INTERNAL_KLDSCP_DVO1", 753926deccbSFrançois Tigeot "INTERNAL_KLDSCP_DAC1", 754926deccbSFrançois Tigeot "INTERNAL_KLDSCP_DAC2", 755926deccbSFrançois Tigeot "SI178", 756926deccbSFrançois Tigeot "MVPU_FPGA", 757926deccbSFrançois Tigeot "INTERNAL_DDI", 758926deccbSFrançois Tigeot "VT1625", 759926deccbSFrançois Tigeot "HDMI_SI1932", 760926deccbSFrançois Tigeot "DP_AN9801", 761926deccbSFrançois Tigeot "DP_DP501", 762926deccbSFrançois Tigeot "INTERNAL_UNIPHY", 763926deccbSFrançois Tigeot "INTERNAL_KLDSCP_LVTMA", 764926deccbSFrançois Tigeot "INTERNAL_UNIPHY1", 765926deccbSFrançois Tigeot "INTERNAL_UNIPHY2", 766926deccbSFrançois Tigeot "NUTMEG", 767926deccbSFrançois Tigeot "TRAVIS", 76857e252bfSMichael Neumann "INTERNAL_VCE", 76957e252bfSMichael Neumann "INTERNAL_UNIPHY3", 770926deccbSFrançois Tigeot }; 771926deccbSFrançois Tigeot 772926deccbSFrançois Tigeot static const char *hpd_names[6] = { 773926deccbSFrançois Tigeot "HPD1", 774926deccbSFrançois Tigeot "HPD2", 775926deccbSFrançois Tigeot "HPD3", 776926deccbSFrançois Tigeot "HPD4", 777926deccbSFrançois Tigeot "HPD5", 778926deccbSFrançois Tigeot "HPD6", 779926deccbSFrançois Tigeot }; 780926deccbSFrançois Tigeot 781926deccbSFrançois Tigeot static void radeon_print_display_setup(struct drm_device *dev) 782926deccbSFrançois Tigeot { 783926deccbSFrançois Tigeot struct drm_connector *connector; 784926deccbSFrançois Tigeot struct radeon_connector *radeon_connector; 785926deccbSFrançois Tigeot struct drm_encoder *encoder; 786926deccbSFrançois Tigeot struct radeon_encoder *radeon_encoder; 787926deccbSFrançois Tigeot uint32_t devices; 788926deccbSFrançois Tigeot int i = 0; 789926deccbSFrançois Tigeot 790926deccbSFrançois Tigeot DRM_INFO("Radeon Display Connectors\n"); 791926deccbSFrançois Tigeot list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 792926deccbSFrançois Tigeot radeon_connector = to_radeon_connector(connector); 793926deccbSFrançois Tigeot DRM_INFO("Connector %d:\n", i); 794ba55f2f5SFrançois Tigeot DRM_INFO(" %s\n", connector->name); 795926deccbSFrançois Tigeot if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 796926deccbSFrançois Tigeot DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); 797926deccbSFrançois Tigeot if (radeon_connector->ddc_bus) { 798926deccbSFrançois Tigeot DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 799926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.mask_clk_reg, 800926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.mask_data_reg, 801926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.a_clk_reg, 802926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.a_data_reg, 803926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.en_clk_reg, 804926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.en_data_reg, 805926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.y_clk_reg, 806926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.y_data_reg); 807926deccbSFrançois Tigeot if (radeon_connector->router.ddc_valid) 808926deccbSFrançois Tigeot DRM_INFO(" DDC Router 0x%x/0x%x\n", 809926deccbSFrançois Tigeot radeon_connector->router.ddc_mux_control_pin, 810926deccbSFrançois Tigeot radeon_connector->router.ddc_mux_state); 811926deccbSFrançois Tigeot if (radeon_connector->router.cd_valid) 812926deccbSFrançois Tigeot DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 813926deccbSFrançois Tigeot radeon_connector->router.cd_mux_control_pin, 814926deccbSFrançois Tigeot radeon_connector->router.cd_mux_state); 815926deccbSFrançois Tigeot } else { 816926deccbSFrançois Tigeot if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 817926deccbSFrançois Tigeot connector->connector_type == DRM_MODE_CONNECTOR_DVII || 818926deccbSFrançois Tigeot connector->connector_type == DRM_MODE_CONNECTOR_DVID || 819926deccbSFrançois Tigeot connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 820926deccbSFrançois Tigeot connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 821926deccbSFrançois Tigeot connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 822926deccbSFrançois Tigeot DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 823926deccbSFrançois Tigeot } 824926deccbSFrançois Tigeot DRM_INFO(" Encoders:\n"); 825926deccbSFrançois Tigeot list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 826926deccbSFrançois Tigeot radeon_encoder = to_radeon_encoder(encoder); 827926deccbSFrançois Tigeot devices = radeon_encoder->devices & radeon_connector->devices; 828926deccbSFrançois Tigeot if (devices) { 829926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_CRT1_SUPPORT) 830926deccbSFrançois Tigeot DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); 831926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_CRT2_SUPPORT) 832926deccbSFrançois Tigeot DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); 833926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_LCD1_SUPPORT) 834926deccbSFrançois Tigeot DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); 835926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP1_SUPPORT) 836926deccbSFrançois Tigeot DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); 837926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP2_SUPPORT) 838926deccbSFrançois Tigeot DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); 839926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP3_SUPPORT) 840926deccbSFrançois Tigeot DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); 841926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP4_SUPPORT) 842926deccbSFrançois Tigeot DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); 843926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP5_SUPPORT) 844926deccbSFrançois Tigeot DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); 845926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP6_SUPPORT) 846926deccbSFrançois Tigeot DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); 847926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_TV1_SUPPORT) 848926deccbSFrançois Tigeot DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); 849926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_CV_SUPPORT) 850926deccbSFrançois Tigeot DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); 851926deccbSFrançois Tigeot } 852926deccbSFrançois Tigeot } 853926deccbSFrançois Tigeot i++; 854926deccbSFrançois Tigeot } 855926deccbSFrançois Tigeot } 856926deccbSFrançois Tigeot 857926deccbSFrançois Tigeot static bool radeon_setup_enc_conn(struct drm_device *dev) 858926deccbSFrançois Tigeot { 859926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 860926deccbSFrançois Tigeot bool ret = false; 861926deccbSFrançois Tigeot 862926deccbSFrançois Tigeot if (rdev->bios) { 863926deccbSFrançois Tigeot if (rdev->is_atom_bios) { 864926deccbSFrançois Tigeot ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); 865926deccbSFrançois Tigeot if (ret == false) 866926deccbSFrançois Tigeot ret = radeon_get_atom_connector_info_from_object_table(dev); 867926deccbSFrançois Tigeot } else { 868926deccbSFrançois Tigeot ret = radeon_get_legacy_connector_info_from_bios(dev); 869926deccbSFrançois Tigeot if (ret == false) 870926deccbSFrançois Tigeot ret = radeon_get_legacy_connector_info_from_table(dev); 871926deccbSFrançois Tigeot } 872926deccbSFrançois Tigeot } else { 873926deccbSFrançois Tigeot if (!ASIC_IS_AVIVO(rdev)) 874926deccbSFrançois Tigeot ret = radeon_get_legacy_connector_info_from_table(dev); 875926deccbSFrançois Tigeot } 876926deccbSFrançois Tigeot if (ret) { 877926deccbSFrançois Tigeot radeon_setup_encoder_clones(dev); 878926deccbSFrançois Tigeot radeon_print_display_setup(dev); 879926deccbSFrançois Tigeot } 880926deccbSFrançois Tigeot 881926deccbSFrançois Tigeot return ret; 882926deccbSFrançois Tigeot } 883926deccbSFrançois Tigeot 884926deccbSFrançois Tigeot /* avivo */ 885c6f73aabSFrançois Tigeot 886c6f73aabSFrançois Tigeot /** 887c6f73aabSFrançois Tigeot * avivo_reduce_ratio - fractional number reduction 888c6f73aabSFrançois Tigeot * 889c6f73aabSFrançois Tigeot * @nom: nominator 890c6f73aabSFrançois Tigeot * @den: denominator 891c6f73aabSFrançois Tigeot * @nom_min: minimum value for nominator 892c6f73aabSFrançois Tigeot * @den_min: minimum value for denominator 893c6f73aabSFrançois Tigeot * 894c6f73aabSFrançois Tigeot * Find the greatest common divisor and apply it on both nominator and 895c6f73aabSFrançois Tigeot * denominator, but make nominator and denominator are at least as large 896c6f73aabSFrançois Tigeot * as their minimum values. 897c6f73aabSFrançois Tigeot */ 898c6f73aabSFrançois Tigeot static void avivo_reduce_ratio(unsigned *nom, unsigned *den, 899c6f73aabSFrançois Tigeot unsigned nom_min, unsigned den_min) 900926deccbSFrançois Tigeot { 901c6f73aabSFrançois Tigeot unsigned tmp; 902926deccbSFrançois Tigeot 903c6f73aabSFrançois Tigeot /* reduce the numbers to a simpler ratio */ 904c59a5c48SFrançois Tigeot tmp = gcd(*nom, *den); 905c6f73aabSFrançois Tigeot *nom /= tmp; 906c6f73aabSFrançois Tigeot *den /= tmp; 907926deccbSFrançois Tigeot 908c6f73aabSFrançois Tigeot /* make sure nominator is large enough */ 909c6f73aabSFrançois Tigeot if (*nom < nom_min) { 910c6f73aabSFrançois Tigeot tmp = DIV_ROUND_UP(nom_min, *nom); 911c6f73aabSFrançois Tigeot *nom *= tmp; 912c6f73aabSFrançois Tigeot *den *= tmp; 913926deccbSFrançois Tigeot } 914926deccbSFrançois Tigeot 915c6f73aabSFrançois Tigeot /* make sure the denominator is large enough */ 916c6f73aabSFrançois Tigeot if (*den < den_min) { 917c6f73aabSFrançois Tigeot tmp = DIV_ROUND_UP(den_min, *den); 918c6f73aabSFrançois Tigeot *nom *= tmp; 919c6f73aabSFrançois Tigeot *den *= tmp; 920c6f73aabSFrançois Tigeot } 921c6f73aabSFrançois Tigeot } 922c6f73aabSFrançois Tigeot 923c6f73aabSFrançois Tigeot /** 924c6f73aabSFrançois Tigeot * avivo_get_fb_ref_div - feedback and ref divider calculation 925c6f73aabSFrançois Tigeot * 926c6f73aabSFrançois Tigeot * @nom: nominator 927c6f73aabSFrançois Tigeot * @den: denominator 928c6f73aabSFrançois Tigeot * @post_div: post divider 929c6f73aabSFrançois Tigeot * @fb_div_max: feedback divider maximum 930c6f73aabSFrançois Tigeot * @ref_div_max: reference divider maximum 931c6f73aabSFrançois Tigeot * @fb_div: resulting feedback divider 932c6f73aabSFrançois Tigeot * @ref_div: resulting reference divider 933c6f73aabSFrançois Tigeot * 934c6f73aabSFrançois Tigeot * Calculate feedback and reference divider for a given post divider. Makes 935c6f73aabSFrançois Tigeot * sure we stay within the limits. 936c6f73aabSFrançois Tigeot */ 937c6f73aabSFrançois Tigeot static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, 938c6f73aabSFrançois Tigeot unsigned fb_div_max, unsigned ref_div_max, 939c6f73aabSFrançois Tigeot unsigned *fb_div, unsigned *ref_div) 940926deccbSFrançois Tigeot { 941c6f73aabSFrançois Tigeot /* limit reference * post divider to a maximum */ 942c6f73aabSFrançois Tigeot ref_div_max = max(min(100 / post_div, ref_div_max), 1u); 943926deccbSFrançois Tigeot 944c6f73aabSFrançois Tigeot /* get matching reference and feedback divider */ 945c6f73aabSFrançois Tigeot *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); 946c6f73aabSFrançois Tigeot *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); 947926deccbSFrançois Tigeot 948c6f73aabSFrançois Tigeot /* limit fb divider to its maximum */ 949c6f73aabSFrançois Tigeot if (*fb_div > fb_div_max) { 950c6f73aabSFrançois Tigeot *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); 951c6f73aabSFrançois Tigeot *fb_div = fb_div_max; 952c6f73aabSFrançois Tigeot } 953926deccbSFrançois Tigeot } 954926deccbSFrançois Tigeot 955c6f73aabSFrançois Tigeot /** 956c6f73aabSFrançois Tigeot * radeon_compute_pll_avivo - compute PLL paramaters 957c6f73aabSFrançois Tigeot * 958c6f73aabSFrançois Tigeot * @pll: information about the PLL 959c6f73aabSFrançois Tigeot * @dot_clock_p: resulting pixel clock 960c6f73aabSFrançois Tigeot * fb_div_p: resulting feedback divider 961c6f73aabSFrançois Tigeot * frac_fb_div_p: fractional part of the feedback divider 962c6f73aabSFrançois Tigeot * ref_div_p: resulting reference divider 963c6f73aabSFrançois Tigeot * post_div_p: resulting reference divider 964c6f73aabSFrançois Tigeot * 965c6f73aabSFrançois Tigeot * Try to calculate the PLL parameters to generate the given frequency: 966c6f73aabSFrançois Tigeot * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div) 967c6f73aabSFrançois Tigeot */ 968926deccbSFrançois Tigeot void radeon_compute_pll_avivo(struct radeon_pll *pll, 969926deccbSFrançois Tigeot u32 freq, 970926deccbSFrançois Tigeot u32 *dot_clock_p, 971926deccbSFrançois Tigeot u32 *fb_div_p, 972926deccbSFrançois Tigeot u32 *frac_fb_div_p, 973926deccbSFrançois Tigeot u32 *ref_div_p, 974926deccbSFrançois Tigeot u32 *post_div_p) 975926deccbSFrançois Tigeot { 976c6f73aabSFrançois Tigeot unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? 977c6f73aabSFrançois Tigeot freq : freq / 10; 978926deccbSFrançois Tigeot 979c6f73aabSFrançois Tigeot unsigned fb_div_min, fb_div_max, fb_div; 980c6f73aabSFrançois Tigeot unsigned post_div_min, post_div_max, post_div; 981c6f73aabSFrançois Tigeot unsigned ref_div_min, ref_div_max, ref_div; 982c6f73aabSFrançois Tigeot unsigned post_div_best, diff_best; 983c6f73aabSFrançois Tigeot unsigned nom, den; 984c6f73aabSFrançois Tigeot 985c6f73aabSFrançois Tigeot /* determine allowed feedback divider range */ 986c6f73aabSFrançois Tigeot fb_div_min = pll->min_feedback_div; 987c6f73aabSFrançois Tigeot fb_div_max = pll->max_feedback_div; 988926deccbSFrançois Tigeot 989926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 990c6f73aabSFrançois Tigeot fb_div_min *= 10; 991c6f73aabSFrançois Tigeot fb_div_max *= 10; 992926deccbSFrançois Tigeot } 993926deccbSFrançois Tigeot 994c6f73aabSFrançois Tigeot /* determine allowed ref divider range */ 995c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_REF_DIV) 996c6f73aabSFrançois Tigeot ref_div_min = pll->reference_div; 997926deccbSFrançois Tigeot else 998c6f73aabSFrançois Tigeot ref_div_min = pll->min_ref_div; 999c6f73aabSFrançois Tigeot 1000c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && 1001c6f73aabSFrançois Tigeot pll->flags & RADEON_PLL_USE_REF_DIV) 1002c6f73aabSFrançois Tigeot ref_div_max = pll->reference_div; 10037dcf36dcSFrançois Tigeot else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 10047dcf36dcSFrançois Tigeot /* fix for problems on RS880 */ 10057dcf36dcSFrançois Tigeot ref_div_max = min(pll->max_ref_div, 7u); 1006c6f73aabSFrançois Tigeot else 1007c6f73aabSFrançois Tigeot ref_div_max = pll->max_ref_div; 1008c6f73aabSFrançois Tigeot 1009c6f73aabSFrançois Tigeot /* determine allowed post divider range */ 1010c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_POST_DIV) { 1011c6f73aabSFrançois Tigeot post_div_min = pll->post_div; 1012c6f73aabSFrançois Tigeot post_div_max = pll->post_div; 1013c6f73aabSFrançois Tigeot } else { 1014c6f73aabSFrançois Tigeot unsigned vco_min, vco_max; 1015c6f73aabSFrançois Tigeot 1016c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_IS_LCD) { 1017c6f73aabSFrançois Tigeot vco_min = pll->lcd_pll_out_min; 1018c6f73aabSFrançois Tigeot vco_max = pll->lcd_pll_out_max; 1019c6f73aabSFrançois Tigeot } else { 1020c6f73aabSFrançois Tigeot vco_min = pll->pll_out_min; 1021c6f73aabSFrançois Tigeot vco_max = pll->pll_out_max; 1022c6f73aabSFrançois Tigeot } 1023c6f73aabSFrançois Tigeot 1024c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1025c6f73aabSFrançois Tigeot vco_min *= 10; 1026c6f73aabSFrançois Tigeot vco_max *= 10; 1027c6f73aabSFrançois Tigeot } 1028c6f73aabSFrançois Tigeot 1029c6f73aabSFrançois Tigeot post_div_min = vco_min / target_clock; 1030c6f73aabSFrançois Tigeot if ((target_clock * post_div_min) < vco_min) 1031c6f73aabSFrançois Tigeot ++post_div_min; 1032c6f73aabSFrançois Tigeot if (post_div_min < pll->min_post_div) 1033c6f73aabSFrançois Tigeot post_div_min = pll->min_post_div; 1034c6f73aabSFrançois Tigeot 1035c6f73aabSFrançois Tigeot post_div_max = vco_max / target_clock; 1036c6f73aabSFrançois Tigeot if ((target_clock * post_div_max) > vco_max) 1037c6f73aabSFrançois Tigeot --post_div_max; 1038c6f73aabSFrançois Tigeot if (post_div_max > pll->max_post_div) 1039c6f73aabSFrançois Tigeot post_div_max = pll->max_post_div; 1040c6f73aabSFrançois Tigeot } 1041c6f73aabSFrançois Tigeot 1042c6f73aabSFrançois Tigeot /* represent the searched ratio as fractional number */ 1043c6f73aabSFrançois Tigeot nom = target_clock; 1044c6f73aabSFrançois Tigeot den = pll->reference_freq; 1045c6f73aabSFrançois Tigeot 1046c6f73aabSFrançois Tigeot /* reduce the numbers to a simpler ratio */ 1047c6f73aabSFrançois Tigeot avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min); 1048c6f73aabSFrançois Tigeot 1049c6f73aabSFrançois Tigeot /* now search for a post divider */ 1050c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 1051c6f73aabSFrançois Tigeot post_div_best = post_div_min; 1052c6f73aabSFrançois Tigeot else 1053c6f73aabSFrançois Tigeot post_div_best = post_div_max; 1054c6f73aabSFrançois Tigeot diff_best = ~0; 1055c6f73aabSFrançois Tigeot 1056c6f73aabSFrançois Tigeot for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { 1057c6f73aabSFrançois Tigeot unsigned diff; 1058c6f73aabSFrançois Tigeot avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, 1059c6f73aabSFrançois Tigeot ref_div_max, &fb_div, &ref_div); 1060c6f73aabSFrançois Tigeot diff = abs(target_clock - (pll->reference_freq * fb_div) / 1061c6f73aabSFrançois Tigeot (ref_div * post_div)); 1062c6f73aabSFrançois Tigeot 1063c6f73aabSFrançois Tigeot if (diff < diff_best || (diff == diff_best && 1064c6f73aabSFrançois Tigeot !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) { 1065c6f73aabSFrançois Tigeot 1066c6f73aabSFrançois Tigeot post_div_best = post_div; 1067c6f73aabSFrançois Tigeot diff_best = diff; 1068c6f73aabSFrançois Tigeot } 1069c6f73aabSFrançois Tigeot } 1070c6f73aabSFrançois Tigeot post_div = post_div_best; 1071c6f73aabSFrançois Tigeot 1072c6f73aabSFrançois Tigeot /* get the feedback and reference divider for the optimal value */ 1073c6f73aabSFrançois Tigeot avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max, 1074c6f73aabSFrançois Tigeot &fb_div, &ref_div); 1075c6f73aabSFrançois Tigeot 1076c6f73aabSFrançois Tigeot /* reduce the numbers to a simpler ratio once more */ 1077c6f73aabSFrançois Tigeot /* this also makes sure that the reference divider is large enough */ 1078c6f73aabSFrançois Tigeot avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); 1079c6f73aabSFrançois Tigeot 1080c6f73aabSFrançois Tigeot /* avoid high jitter with small fractional dividers */ 1081c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { 1082c6f73aabSFrançois Tigeot fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50); 1083c6f73aabSFrançois Tigeot if (fb_div < fb_div_min) { 1084c6f73aabSFrançois Tigeot unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div); 1085c6f73aabSFrançois Tigeot fb_div *= tmp; 1086c6f73aabSFrançois Tigeot ref_div *= tmp; 1087926deccbSFrançois Tigeot } 1088926deccbSFrançois Tigeot } 1089926deccbSFrançois Tigeot 1090c6f73aabSFrançois Tigeot /* and finally save the result */ 1091c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1092c6f73aabSFrançois Tigeot *fb_div_p = fb_div / 10; 1093c6f73aabSFrançois Tigeot *frac_fb_div_p = fb_div % 10; 1094c6f73aabSFrançois Tigeot } else { 1095926deccbSFrançois Tigeot *fb_div_p = fb_div; 1096c6f73aabSFrançois Tigeot *frac_fb_div_p = 0; 1097c6f73aabSFrançois Tigeot } 1098c6f73aabSFrançois Tigeot 1099c6f73aabSFrançois Tigeot *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + 1100c6f73aabSFrançois Tigeot (pll->reference_freq * *frac_fb_div_p)) / 1101c6f73aabSFrançois Tigeot (ref_div * post_div * 10); 1102926deccbSFrançois Tigeot *ref_div_p = ref_div; 1103926deccbSFrançois Tigeot *post_div_p = post_div; 1104c6f73aabSFrançois Tigeot 1105c6f73aabSFrançois Tigeot DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1106c6f73aabSFrançois Tigeot freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, 1107c6f73aabSFrançois Tigeot ref_div, post_div); 1108926deccbSFrançois Tigeot } 1109926deccbSFrançois Tigeot 1110926deccbSFrançois Tigeot /* pre-avivo */ 1111926deccbSFrançois Tigeot static inline uint32_t radeon_div(uint64_t n, uint32_t d) 1112926deccbSFrançois Tigeot { 1113926deccbSFrançois Tigeot uint64_t mod; 1114926deccbSFrançois Tigeot 1115926deccbSFrançois Tigeot n += d / 2; 1116926deccbSFrançois Tigeot 1117926deccbSFrançois Tigeot mod = do_div(n, d); 1118926deccbSFrançois Tigeot return n; 1119926deccbSFrançois Tigeot } 1120926deccbSFrançois Tigeot 1121926deccbSFrançois Tigeot void radeon_compute_pll_legacy(struct radeon_pll *pll, 1122926deccbSFrançois Tigeot uint64_t freq, 1123926deccbSFrançois Tigeot uint32_t *dot_clock_p, 1124926deccbSFrançois Tigeot uint32_t *fb_div_p, 1125926deccbSFrançois Tigeot uint32_t *frac_fb_div_p, 1126926deccbSFrançois Tigeot uint32_t *ref_div_p, 1127926deccbSFrançois Tigeot uint32_t *post_div_p) 1128926deccbSFrançois Tigeot { 1129926deccbSFrançois Tigeot uint32_t min_ref_div = pll->min_ref_div; 1130926deccbSFrançois Tigeot uint32_t max_ref_div = pll->max_ref_div; 1131926deccbSFrançois Tigeot uint32_t min_post_div = pll->min_post_div; 1132926deccbSFrançois Tigeot uint32_t max_post_div = pll->max_post_div; 1133926deccbSFrançois Tigeot uint32_t min_fractional_feed_div = 0; 1134926deccbSFrançois Tigeot uint32_t max_fractional_feed_div = 0; 1135926deccbSFrançois Tigeot uint32_t best_vco = pll->best_vco; 1136926deccbSFrançois Tigeot uint32_t best_post_div = 1; 1137926deccbSFrançois Tigeot uint32_t best_ref_div = 1; 1138926deccbSFrançois Tigeot uint32_t best_feedback_div = 1; 1139926deccbSFrançois Tigeot uint32_t best_frac_feedback_div = 0; 1140926deccbSFrançois Tigeot uint32_t best_freq = -1; 1141926deccbSFrançois Tigeot uint32_t best_error = 0xffffffff; 1142926deccbSFrançois Tigeot uint32_t best_vco_diff = 1; 1143926deccbSFrançois Tigeot uint32_t post_div; 1144926deccbSFrançois Tigeot u32 pll_out_min, pll_out_max; 1145926deccbSFrançois Tigeot 11464cd92098Szrj DRM_DEBUG_KMS("PLL freq %ju %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); 1147926deccbSFrançois Tigeot freq = freq * 1000; 1148926deccbSFrançois Tigeot 1149926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_IS_LCD) { 1150926deccbSFrançois Tigeot pll_out_min = pll->lcd_pll_out_min; 1151926deccbSFrançois Tigeot pll_out_max = pll->lcd_pll_out_max; 1152926deccbSFrançois Tigeot } else { 1153926deccbSFrançois Tigeot pll_out_min = pll->pll_out_min; 1154926deccbSFrançois Tigeot pll_out_max = pll->pll_out_max; 1155926deccbSFrançois Tigeot } 1156926deccbSFrançois Tigeot 1157926deccbSFrançois Tigeot if (pll_out_min > 64800) 1158926deccbSFrançois Tigeot pll_out_min = 64800; 1159926deccbSFrançois Tigeot 1160926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_REF_DIV) 1161926deccbSFrançois Tigeot min_ref_div = max_ref_div = pll->reference_div; 1162926deccbSFrançois Tigeot else { 1163926deccbSFrançois Tigeot while (min_ref_div < max_ref_div-1) { 1164926deccbSFrançois Tigeot uint32_t mid = (min_ref_div + max_ref_div) / 2; 1165926deccbSFrançois Tigeot uint32_t pll_in = pll->reference_freq / mid; 1166926deccbSFrançois Tigeot if (pll_in < pll->pll_in_min) 1167926deccbSFrançois Tigeot max_ref_div = mid; 1168926deccbSFrançois Tigeot else if (pll_in > pll->pll_in_max) 1169926deccbSFrançois Tigeot min_ref_div = mid; 1170926deccbSFrançois Tigeot else 1171926deccbSFrançois Tigeot break; 1172926deccbSFrançois Tigeot } 1173926deccbSFrançois Tigeot } 1174926deccbSFrançois Tigeot 1175926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_POST_DIV) 1176926deccbSFrançois Tigeot min_post_div = max_post_div = pll->post_div; 1177926deccbSFrançois Tigeot 1178926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1179926deccbSFrançois Tigeot min_fractional_feed_div = pll->min_frac_feedback_div; 1180926deccbSFrançois Tigeot max_fractional_feed_div = pll->max_frac_feedback_div; 1181926deccbSFrançois Tigeot } 1182926deccbSFrançois Tigeot 1183926deccbSFrançois Tigeot for (post_div = max_post_div; post_div >= min_post_div; --post_div) { 1184926deccbSFrançois Tigeot uint32_t ref_div; 1185926deccbSFrançois Tigeot 1186926deccbSFrançois Tigeot if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 1187926deccbSFrançois Tigeot continue; 1188926deccbSFrançois Tigeot 1189926deccbSFrançois Tigeot /* legacy radeons only have a few post_divs */ 1190926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_LEGACY) { 1191926deccbSFrançois Tigeot if ((post_div == 5) || 1192926deccbSFrançois Tigeot (post_div == 7) || 1193926deccbSFrançois Tigeot (post_div == 9) || 1194926deccbSFrançois Tigeot (post_div == 10) || 1195926deccbSFrançois Tigeot (post_div == 11) || 1196926deccbSFrançois Tigeot (post_div == 13) || 1197926deccbSFrançois Tigeot (post_div == 14) || 1198926deccbSFrançois Tigeot (post_div == 15)) 1199926deccbSFrançois Tigeot continue; 1200926deccbSFrançois Tigeot } 1201926deccbSFrançois Tigeot 1202926deccbSFrançois Tigeot for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { 1203926deccbSFrançois Tigeot uint32_t feedback_div, current_freq = 0, error, vco_diff; 1204926deccbSFrançois Tigeot uint32_t pll_in = pll->reference_freq / ref_div; 1205926deccbSFrançois Tigeot uint32_t min_feed_div = pll->min_feedback_div; 1206926deccbSFrançois Tigeot uint32_t max_feed_div = pll->max_feedback_div + 1; 1207926deccbSFrançois Tigeot 1208926deccbSFrançois Tigeot if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) 1209926deccbSFrançois Tigeot continue; 1210926deccbSFrançois Tigeot 1211926deccbSFrançois Tigeot while (min_feed_div < max_feed_div) { 1212926deccbSFrançois Tigeot uint32_t vco; 1213926deccbSFrançois Tigeot uint32_t min_frac_feed_div = min_fractional_feed_div; 1214926deccbSFrançois Tigeot uint32_t max_frac_feed_div = max_fractional_feed_div + 1; 1215926deccbSFrançois Tigeot uint32_t frac_feedback_div; 1216926deccbSFrançois Tigeot uint64_t tmp; 1217926deccbSFrançois Tigeot 1218926deccbSFrançois Tigeot feedback_div = (min_feed_div + max_feed_div) / 2; 1219926deccbSFrançois Tigeot 1220926deccbSFrançois Tigeot tmp = (uint64_t)pll->reference_freq * feedback_div; 1221926deccbSFrançois Tigeot vco = radeon_div(tmp, ref_div); 1222926deccbSFrançois Tigeot 1223926deccbSFrançois Tigeot if (vco < pll_out_min) { 1224926deccbSFrançois Tigeot min_feed_div = feedback_div + 1; 1225926deccbSFrançois Tigeot continue; 1226926deccbSFrançois Tigeot } else if (vco > pll_out_max) { 1227926deccbSFrançois Tigeot max_feed_div = feedback_div; 1228926deccbSFrançois Tigeot continue; 1229926deccbSFrançois Tigeot } 1230926deccbSFrançois Tigeot 1231926deccbSFrançois Tigeot while (min_frac_feed_div < max_frac_feed_div) { 1232926deccbSFrançois Tigeot frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; 1233926deccbSFrançois Tigeot tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; 1234926deccbSFrançois Tigeot tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; 1235926deccbSFrançois Tigeot current_freq = radeon_div(tmp, ref_div * post_div); 1236926deccbSFrançois Tigeot 1237926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 1238926deccbSFrançois Tigeot if (freq < current_freq) 1239926deccbSFrançois Tigeot error = 0xffffffff; 1240926deccbSFrançois Tigeot else 1241926deccbSFrançois Tigeot error = freq - current_freq; 1242926deccbSFrançois Tigeot } else 1243926deccbSFrançois Tigeot error = abs(current_freq - freq); 1244926deccbSFrançois Tigeot vco_diff = abs(vco - best_vco); 1245926deccbSFrançois Tigeot 1246926deccbSFrançois Tigeot if ((best_vco == 0 && error < best_error) || 1247926deccbSFrançois Tigeot (best_vco != 0 && 1248926deccbSFrançois Tigeot ((best_error > 100 && error < best_error - 100) || 1249926deccbSFrançois Tigeot (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { 1250926deccbSFrançois Tigeot best_post_div = post_div; 1251926deccbSFrançois Tigeot best_ref_div = ref_div; 1252926deccbSFrançois Tigeot best_feedback_div = feedback_div; 1253926deccbSFrançois Tigeot best_frac_feedback_div = frac_feedback_div; 1254926deccbSFrançois Tigeot best_freq = current_freq; 1255926deccbSFrançois Tigeot best_error = error; 1256926deccbSFrançois Tigeot best_vco_diff = vco_diff; 1257926deccbSFrançois Tigeot } else if (current_freq == freq) { 1258926deccbSFrançois Tigeot if (best_freq == -1) { 1259926deccbSFrançois Tigeot best_post_div = post_div; 1260926deccbSFrançois Tigeot best_ref_div = ref_div; 1261926deccbSFrançois Tigeot best_feedback_div = feedback_div; 1262926deccbSFrançois Tigeot best_frac_feedback_div = frac_feedback_div; 1263926deccbSFrançois Tigeot best_freq = current_freq; 1264926deccbSFrançois Tigeot best_error = error; 1265926deccbSFrançois Tigeot best_vco_diff = vco_diff; 1266926deccbSFrançois Tigeot } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 1267926deccbSFrançois Tigeot ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 1268926deccbSFrançois Tigeot ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 1269926deccbSFrançois Tigeot ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 1270926deccbSFrançois Tigeot ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 1271926deccbSFrançois Tigeot ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 1272926deccbSFrançois Tigeot best_post_div = post_div; 1273926deccbSFrançois Tigeot best_ref_div = ref_div; 1274926deccbSFrançois Tigeot best_feedback_div = feedback_div; 1275926deccbSFrançois Tigeot best_frac_feedback_div = frac_feedback_div; 1276926deccbSFrançois Tigeot best_freq = current_freq; 1277926deccbSFrançois Tigeot best_error = error; 1278926deccbSFrançois Tigeot best_vco_diff = vco_diff; 1279926deccbSFrançois Tigeot } 1280926deccbSFrançois Tigeot } 1281926deccbSFrançois Tigeot if (current_freq < freq) 1282926deccbSFrançois Tigeot min_frac_feed_div = frac_feedback_div + 1; 1283926deccbSFrançois Tigeot else 1284926deccbSFrançois Tigeot max_frac_feed_div = frac_feedback_div; 1285926deccbSFrançois Tigeot } 1286926deccbSFrançois Tigeot if (current_freq < freq) 1287926deccbSFrançois Tigeot min_feed_div = feedback_div + 1; 1288926deccbSFrançois Tigeot else 1289926deccbSFrançois Tigeot max_feed_div = feedback_div; 1290926deccbSFrançois Tigeot } 1291926deccbSFrançois Tigeot } 1292926deccbSFrançois Tigeot } 1293926deccbSFrançois Tigeot 1294926deccbSFrançois Tigeot *dot_clock_p = best_freq / 10000; 1295926deccbSFrançois Tigeot *fb_div_p = best_feedback_div; 1296926deccbSFrançois Tigeot *frac_fb_div_p = best_frac_feedback_div; 1297926deccbSFrançois Tigeot *ref_div_p = best_ref_div; 1298926deccbSFrançois Tigeot *post_div_p = best_post_div; 1299926deccbSFrançois Tigeot DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1300926deccbSFrançois Tigeot (long long)freq, 1301926deccbSFrançois Tigeot best_freq / 1000, best_feedback_div, best_frac_feedback_div, 1302926deccbSFrançois Tigeot best_ref_div, best_post_div); 1303926deccbSFrançois Tigeot 1304926deccbSFrançois Tigeot } 1305926deccbSFrançois Tigeot 1306926deccbSFrançois Tigeot static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) 1307926deccbSFrançois Tigeot { 1308926deccbSFrançois Tigeot struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1309926deccbSFrançois Tigeot 1310926deccbSFrançois Tigeot drm_gem_object_unreference_unlocked(radeon_fb->obj); 1311926deccbSFrançois Tigeot drm_framebuffer_cleanup(fb); 1312c4ef309bSzrj kfree(radeon_fb); 1313926deccbSFrançois Tigeot } 1314926deccbSFrançois Tigeot 1315926deccbSFrançois Tigeot static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, 1316926deccbSFrançois Tigeot struct drm_file *file_priv, 1317926deccbSFrançois Tigeot unsigned int *handle) 1318926deccbSFrançois Tigeot { 1319926deccbSFrançois Tigeot struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1320926deccbSFrançois Tigeot 1321926deccbSFrançois Tigeot return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); 1322926deccbSFrançois Tigeot } 1323926deccbSFrançois Tigeot 1324926deccbSFrançois Tigeot static const struct drm_framebuffer_funcs radeon_fb_funcs = { 1325926deccbSFrançois Tigeot .destroy = radeon_user_framebuffer_destroy, 1326926deccbSFrançois Tigeot .create_handle = radeon_user_framebuffer_create_handle, 1327926deccbSFrançois Tigeot }; 1328926deccbSFrançois Tigeot 1329926deccbSFrançois Tigeot int 1330926deccbSFrançois Tigeot radeon_framebuffer_init(struct drm_device *dev, 1331926deccbSFrançois Tigeot struct radeon_framebuffer *rfb, 1332aee94f86SFrançois Tigeot const struct drm_mode_fb_cmd2 *mode_cmd, 1333926deccbSFrançois Tigeot struct drm_gem_object *obj) 1334926deccbSFrançois Tigeot { 1335926deccbSFrançois Tigeot int ret; 1336926deccbSFrançois Tigeot rfb->obj = obj; 1337b403bed8SMichael Neumann drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); 1338926deccbSFrançois Tigeot ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); 1339926deccbSFrançois Tigeot if (ret) { 1340926deccbSFrançois Tigeot rfb->obj = NULL; 1341926deccbSFrançois Tigeot return ret; 1342926deccbSFrançois Tigeot } 1343926deccbSFrançois Tigeot return 0; 1344926deccbSFrançois Tigeot } 1345926deccbSFrançois Tigeot 134660fc7eecSFrançois Tigeot static struct drm_framebuffer * 1347926deccbSFrançois Tigeot radeon_user_framebuffer_create(struct drm_device *dev, 1348926deccbSFrançois Tigeot struct drm_file *file_priv, 1349aee94f86SFrançois Tigeot const struct drm_mode_fb_cmd2 *mode_cmd) 1350926deccbSFrançois Tigeot { 1351926deccbSFrançois Tigeot struct drm_gem_object *obj; 1352926deccbSFrançois Tigeot struct radeon_framebuffer *radeon_fb; 1353926deccbSFrançois Tigeot int ret; 1354926deccbSFrançois Tigeot 13558621f407SFrançois Tigeot obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); 1356926deccbSFrançois Tigeot if (obj == NULL) { 1357fb572d17SFrançois Tigeot dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 1358926deccbSFrançois Tigeot "can't create framebuffer\n", mode_cmd->handles[0]); 135960fc7eecSFrançois Tigeot return ERR_PTR(-ENOENT); 1360926deccbSFrançois Tigeot } 1361926deccbSFrançois Tigeot 1362c59a5c48SFrançois Tigeot /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ 1363c59a5c48SFrançois Tigeot if (obj->import_attach) { 1364c59a5c48SFrançois Tigeot DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n"); 1365c59a5c48SFrançois Tigeot return ERR_PTR(-EINVAL); 1366c59a5c48SFrançois Tigeot } 1367c59a5c48SFrançois Tigeot 1368c4ef309bSzrj radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); 1369926deccbSFrançois Tigeot if (radeon_fb == NULL) { 1370926deccbSFrançois Tigeot drm_gem_object_unreference_unlocked(obj); 137160fc7eecSFrançois Tigeot return ERR_PTR(-ENOMEM); 1372926deccbSFrançois Tigeot } 1373926deccbSFrançois Tigeot 1374926deccbSFrançois Tigeot ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj); 1375926deccbSFrançois Tigeot if (ret) { 1376158486a6SFrançois Tigeot kfree(radeon_fb); 1377926deccbSFrançois Tigeot drm_gem_object_unreference_unlocked(obj); 137860fc7eecSFrançois Tigeot return ERR_PTR(ret); 1379926deccbSFrançois Tigeot } 1380926deccbSFrançois Tigeot 138160fc7eecSFrançois Tigeot return &radeon_fb->base; 1382926deccbSFrançois Tigeot } 1383926deccbSFrançois Tigeot 1384926deccbSFrançois Tigeot static void radeon_output_poll_changed(struct drm_device *dev) 1385926deccbSFrançois Tigeot { 1386926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 1387926deccbSFrançois Tigeot radeon_fb_output_poll_changed(rdev); 1388926deccbSFrançois Tigeot } 1389926deccbSFrançois Tigeot 1390926deccbSFrançois Tigeot static const struct drm_mode_config_funcs radeon_mode_funcs = { 1391926deccbSFrançois Tigeot .fb_create = radeon_user_framebuffer_create, 1392926deccbSFrançois Tigeot .output_poll_changed = radeon_output_poll_changed 1393926deccbSFrançois Tigeot }; 1394926deccbSFrançois Tigeot 1395926deccbSFrançois Tigeot static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = 1396926deccbSFrançois Tigeot { { 0, "driver" }, 1397926deccbSFrançois Tigeot { 1, "bios" }, 1398926deccbSFrançois Tigeot }; 1399926deccbSFrançois Tigeot 1400926deccbSFrançois Tigeot static struct drm_prop_enum_list radeon_tv_std_enum_list[] = 1401926deccbSFrançois Tigeot { { TV_STD_NTSC, "ntsc" }, 1402926deccbSFrançois Tigeot { TV_STD_PAL, "pal" }, 1403926deccbSFrançois Tigeot { TV_STD_PAL_M, "pal-m" }, 1404926deccbSFrançois Tigeot { TV_STD_PAL_60, "pal-60" }, 1405926deccbSFrançois Tigeot { TV_STD_NTSC_J, "ntsc-j" }, 1406926deccbSFrançois Tigeot { TV_STD_SCART_PAL, "scart-pal" }, 1407926deccbSFrançois Tigeot { TV_STD_PAL_CN, "pal-cn" }, 1408926deccbSFrançois Tigeot { TV_STD_SECAM, "secam" }, 1409926deccbSFrançois Tigeot }; 1410926deccbSFrançois Tigeot 1411926deccbSFrançois Tigeot static struct drm_prop_enum_list radeon_underscan_enum_list[] = 1412926deccbSFrançois Tigeot { { UNDERSCAN_OFF, "off" }, 1413926deccbSFrançois Tigeot { UNDERSCAN_ON, "on" }, 1414926deccbSFrançois Tigeot { UNDERSCAN_AUTO, "auto" }, 1415926deccbSFrançois Tigeot }; 1416926deccbSFrançois Tigeot 14174cd92098Szrj static struct drm_prop_enum_list radeon_audio_enum_list[] = 14184cd92098Szrj { { RADEON_AUDIO_DISABLE, "off" }, 14194cd92098Szrj { RADEON_AUDIO_ENABLE, "on" }, 14204cd92098Szrj { RADEON_AUDIO_AUTO, "auto" }, 14214cd92098Szrj }; 14224cd92098Szrj 1423c6f73aabSFrançois Tigeot /* XXX support different dither options? spatial, temporal, both, etc. */ 1424c6f73aabSFrançois Tigeot static struct drm_prop_enum_list radeon_dither_enum_list[] = 1425c6f73aabSFrançois Tigeot { { RADEON_FMT_DITHER_DISABLE, "off" }, 1426c6f73aabSFrançois Tigeot { RADEON_FMT_DITHER_ENABLE, "on" }, 1427c6f73aabSFrançois Tigeot }; 1428c6f73aabSFrançois Tigeot 1429c59a5c48SFrançois Tigeot static struct drm_prop_enum_list radeon_output_csc_enum_list[] = 1430c59a5c48SFrançois Tigeot { { RADEON_OUTPUT_CSC_BYPASS, "bypass" }, 1431c59a5c48SFrançois Tigeot { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" }, 1432c59a5c48SFrançois Tigeot { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" }, 1433c59a5c48SFrançois Tigeot { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" }, 1434c59a5c48SFrançois Tigeot }; 1435c59a5c48SFrançois Tigeot 1436926deccbSFrançois Tigeot static int radeon_modeset_create_props(struct radeon_device *rdev) 1437926deccbSFrançois Tigeot { 1438926deccbSFrançois Tigeot int sz; 1439926deccbSFrançois Tigeot 1440926deccbSFrançois Tigeot if (rdev->is_atom_bios) { 1441926deccbSFrançois Tigeot rdev->mode_info.coherent_mode_property = 1442926deccbSFrançois Tigeot drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1); 1443926deccbSFrançois Tigeot if (!rdev->mode_info.coherent_mode_property) 1444926deccbSFrançois Tigeot return -ENOMEM; 1445926deccbSFrançois Tigeot } 1446926deccbSFrançois Tigeot 1447926deccbSFrançois Tigeot if (!ASIC_IS_AVIVO(rdev)) { 1448c4ef309bSzrj sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); 1449926deccbSFrançois Tigeot rdev->mode_info.tmds_pll_property = 1450926deccbSFrançois Tigeot drm_property_create_enum(rdev->ddev, 0, 1451926deccbSFrançois Tigeot "tmds_pll", 1452926deccbSFrançois Tigeot radeon_tmds_pll_enum_list, sz); 1453926deccbSFrançois Tigeot } 1454926deccbSFrançois Tigeot 1455926deccbSFrançois Tigeot rdev->mode_info.load_detect_property = 1456926deccbSFrançois Tigeot drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1); 1457926deccbSFrançois Tigeot if (!rdev->mode_info.load_detect_property) 1458926deccbSFrançois Tigeot return -ENOMEM; 1459926deccbSFrançois Tigeot 1460926deccbSFrançois Tigeot drm_mode_create_scaling_mode_property(rdev->ddev); 1461926deccbSFrançois Tigeot 1462c4ef309bSzrj sz = ARRAY_SIZE(radeon_tv_std_enum_list); 1463926deccbSFrançois Tigeot rdev->mode_info.tv_std_property = 1464926deccbSFrançois Tigeot drm_property_create_enum(rdev->ddev, 0, 1465926deccbSFrançois Tigeot "tv standard", 1466926deccbSFrançois Tigeot radeon_tv_std_enum_list, sz); 1467926deccbSFrançois Tigeot 1468c4ef309bSzrj sz = ARRAY_SIZE(radeon_underscan_enum_list); 1469926deccbSFrançois Tigeot rdev->mode_info.underscan_property = 1470926deccbSFrançois Tigeot drm_property_create_enum(rdev->ddev, 0, 1471926deccbSFrançois Tigeot "underscan", 1472926deccbSFrançois Tigeot radeon_underscan_enum_list, sz); 1473926deccbSFrançois Tigeot 1474926deccbSFrançois Tigeot rdev->mode_info.underscan_hborder_property = 1475926deccbSFrançois Tigeot drm_property_create_range(rdev->ddev, 0, 1476926deccbSFrançois Tigeot "underscan hborder", 0, 128); 1477926deccbSFrançois Tigeot if (!rdev->mode_info.underscan_hborder_property) 1478926deccbSFrançois Tigeot return -ENOMEM; 1479926deccbSFrançois Tigeot 1480926deccbSFrançois Tigeot rdev->mode_info.underscan_vborder_property = 1481926deccbSFrançois Tigeot drm_property_create_range(rdev->ddev, 0, 1482926deccbSFrançois Tigeot "underscan vborder", 0, 128); 1483926deccbSFrançois Tigeot if (!rdev->mode_info.underscan_vborder_property) 1484926deccbSFrançois Tigeot return -ENOMEM; 1485926deccbSFrançois Tigeot 14864cd92098Szrj sz = ARRAY_SIZE(radeon_audio_enum_list); 14874cd92098Szrj rdev->mode_info.audio_property = 14884cd92098Szrj drm_property_create_enum(rdev->ddev, 0, 14894cd92098Szrj "audio", 14904cd92098Szrj radeon_audio_enum_list, sz); 14914cd92098Szrj 1492c6f73aabSFrançois Tigeot sz = ARRAY_SIZE(radeon_dither_enum_list); 1493c6f73aabSFrançois Tigeot rdev->mode_info.dither_property = 1494c6f73aabSFrançois Tigeot drm_property_create_enum(rdev->ddev, 0, 1495c6f73aabSFrançois Tigeot "dither", 1496c6f73aabSFrançois Tigeot radeon_dither_enum_list, sz); 1497c6f73aabSFrançois Tigeot 1498c59a5c48SFrançois Tigeot sz = ARRAY_SIZE(radeon_output_csc_enum_list); 1499c59a5c48SFrançois Tigeot rdev->mode_info.output_csc_property = 1500c59a5c48SFrançois Tigeot drm_property_create_enum(rdev->ddev, 0, 1501c59a5c48SFrançois Tigeot "output_csc", 1502c59a5c48SFrançois Tigeot radeon_output_csc_enum_list, sz); 1503c59a5c48SFrançois Tigeot 1504926deccbSFrançois Tigeot return 0; 1505926deccbSFrançois Tigeot } 1506926deccbSFrançois Tigeot 1507926deccbSFrançois Tigeot void radeon_update_display_priority(struct radeon_device *rdev) 1508926deccbSFrançois Tigeot { 1509926deccbSFrançois Tigeot /* adjustment options for the display watermarks */ 1510926deccbSFrançois Tigeot if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { 1511926deccbSFrançois Tigeot /* set display priority to high for r3xx, rv515 chips 1512926deccbSFrançois Tigeot * this avoids flickering due to underflow to the 1513926deccbSFrançois Tigeot * display controllers during heavy acceleration. 1514926deccbSFrançois Tigeot * Don't force high on rs4xx igp chips as it seems to 1515926deccbSFrançois Tigeot * affect the sound card. See kernel bug 15982. 1516926deccbSFrançois Tigeot */ 1517926deccbSFrançois Tigeot if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && 1518926deccbSFrançois Tigeot !(rdev->flags & RADEON_IS_IGP)) 1519926deccbSFrançois Tigeot rdev->disp_priority = 2; 1520926deccbSFrançois Tigeot else 1521926deccbSFrançois Tigeot rdev->disp_priority = 0; 1522926deccbSFrançois Tigeot } else 1523926deccbSFrançois Tigeot rdev->disp_priority = radeon_disp_priority; 1524926deccbSFrançois Tigeot 1525926deccbSFrançois Tigeot } 1526926deccbSFrançois Tigeot 1527926deccbSFrançois Tigeot /* 1528926deccbSFrançois Tigeot * Allocate hdmi structs and determine register offsets 1529926deccbSFrançois Tigeot */ 1530926deccbSFrançois Tigeot static void radeon_afmt_init(struct radeon_device *rdev) 1531926deccbSFrançois Tigeot { 1532926deccbSFrançois Tigeot int i; 1533926deccbSFrançois Tigeot 1534926deccbSFrançois Tigeot for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) 1535926deccbSFrançois Tigeot rdev->mode_info.afmt[i] = NULL; 1536926deccbSFrançois Tigeot 15374cd92098Szrj if (ASIC_IS_NODCE(rdev)) { 15384cd92098Szrj /* nothing to do */ 1539926deccbSFrançois Tigeot } else if (ASIC_IS_DCE4(rdev)) { 15404cd92098Szrj static uint32_t eg_offsets[] = { 15414cd92098Szrj EVERGREEN_CRTC0_REGISTER_OFFSET, 15424cd92098Szrj EVERGREEN_CRTC1_REGISTER_OFFSET, 15434cd92098Szrj EVERGREEN_CRTC2_REGISTER_OFFSET, 15444cd92098Szrj EVERGREEN_CRTC3_REGISTER_OFFSET, 15454cd92098Szrj EVERGREEN_CRTC4_REGISTER_OFFSET, 15464cd92098Szrj EVERGREEN_CRTC5_REGISTER_OFFSET, 15474cd92098Szrj 0x13830 - 0x7030, 15484cd92098Szrj }; 15494cd92098Szrj int num_afmt; 15504cd92098Szrj 15514cd92098Szrj /* DCE8 has 7 audio blocks tied to DIG encoders */ 15524cd92098Szrj /* DCE6 has 6 audio blocks tied to DIG encoders */ 1553926deccbSFrançois Tigeot /* DCE4/5 has 6 audio blocks tied to DIG encoders */ 1554926deccbSFrançois Tigeot /* DCE4.1 has 2 audio blocks tied to DIG encoders */ 15554cd92098Szrj if (ASIC_IS_DCE8(rdev)) 15564cd92098Szrj num_afmt = 7; 15574cd92098Szrj else if (ASIC_IS_DCE6(rdev)) 15584cd92098Szrj num_afmt = 6; 15594cd92098Szrj else if (ASIC_IS_DCE5(rdev)) 15604cd92098Szrj num_afmt = 6; 15614cd92098Szrj else if (ASIC_IS_DCE41(rdev)) 15624cd92098Szrj num_afmt = 2; 15634cd92098Szrj else /* DCE4 */ 15644cd92098Szrj num_afmt = 6; 15654cd92098Szrj 15664cd92098Szrj BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets)); 15674cd92098Szrj for (i = 0; i < num_afmt; i++) { 15684cd92098Szrj rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 15694cd92098Szrj if (rdev->mode_info.afmt[i]) { 15704cd92098Szrj rdev->mode_info.afmt[i]->offset = eg_offsets[i]; 15714cd92098Szrj rdev->mode_info.afmt[i]->id = i; 1572926deccbSFrançois Tigeot } 1573926deccbSFrançois Tigeot } 1574926deccbSFrançois Tigeot } else if (ASIC_IS_DCE3(rdev)) { 1575926deccbSFrançois Tigeot /* DCE3.x has 2 audio blocks tied to DIG encoders */ 1576c4ef309bSzrj rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1577926deccbSFrançois Tigeot if (rdev->mode_info.afmt[0]) { 1578926deccbSFrançois Tigeot rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0; 1579926deccbSFrançois Tigeot rdev->mode_info.afmt[0]->id = 0; 1580926deccbSFrançois Tigeot } 1581c4ef309bSzrj rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1582926deccbSFrançois Tigeot if (rdev->mode_info.afmt[1]) { 1583926deccbSFrançois Tigeot rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1; 1584926deccbSFrançois Tigeot rdev->mode_info.afmt[1]->id = 1; 1585926deccbSFrançois Tigeot } 1586926deccbSFrançois Tigeot } else if (ASIC_IS_DCE2(rdev)) { 1587926deccbSFrançois Tigeot /* DCE2 has at least 1 routable audio block */ 1588c4ef309bSzrj rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1589926deccbSFrançois Tigeot if (rdev->mode_info.afmt[0]) { 1590926deccbSFrançois Tigeot rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0; 1591926deccbSFrançois Tigeot rdev->mode_info.afmt[0]->id = 0; 1592926deccbSFrançois Tigeot } 1593926deccbSFrançois Tigeot /* r6xx has 2 routable audio blocks */ 1594926deccbSFrançois Tigeot if (rdev->family >= CHIP_R600) { 1595c4ef309bSzrj rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1596926deccbSFrançois Tigeot if (rdev->mode_info.afmt[1]) { 1597926deccbSFrançois Tigeot rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1; 1598926deccbSFrançois Tigeot rdev->mode_info.afmt[1]->id = 1; 1599926deccbSFrançois Tigeot } 1600926deccbSFrançois Tigeot } 1601926deccbSFrançois Tigeot } 1602926deccbSFrançois Tigeot } 1603926deccbSFrançois Tigeot 1604926deccbSFrançois Tigeot static void radeon_afmt_fini(struct radeon_device *rdev) 1605926deccbSFrançois Tigeot { 1606926deccbSFrançois Tigeot int i; 1607926deccbSFrançois Tigeot 1608926deccbSFrançois Tigeot for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) { 1609c4ef309bSzrj kfree(rdev->mode_info.afmt[i]); 1610926deccbSFrançois Tigeot rdev->mode_info.afmt[i] = NULL; 1611926deccbSFrançois Tigeot } 1612926deccbSFrançois Tigeot } 1613926deccbSFrançois Tigeot 1614926deccbSFrançois Tigeot int radeon_modeset_init(struct radeon_device *rdev) 1615926deccbSFrançois Tigeot { 1616926deccbSFrançois Tigeot int i; 1617926deccbSFrançois Tigeot int ret; 1618926deccbSFrançois Tigeot 1619926deccbSFrançois Tigeot drm_mode_config_init(rdev->ddev); 1620926deccbSFrançois Tigeot rdev->mode_info.mode_config_initialized = true; 1621926deccbSFrançois Tigeot 1622926deccbSFrançois Tigeot rdev->ddev->mode_config.funcs = &radeon_mode_funcs; 1623926deccbSFrançois Tigeot 1624d78d3a22SFrançois Tigeot if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600) 1625d78d3a22SFrançois Tigeot rdev->ddev->mode_config.async_page_flip = true; 1626d78d3a22SFrançois Tigeot 1627926deccbSFrançois Tigeot if (ASIC_IS_DCE5(rdev)) { 1628926deccbSFrançois Tigeot rdev->ddev->mode_config.max_width = 16384; 1629926deccbSFrançois Tigeot rdev->ddev->mode_config.max_height = 16384; 1630926deccbSFrançois Tigeot } else if (ASIC_IS_AVIVO(rdev)) { 1631926deccbSFrançois Tigeot rdev->ddev->mode_config.max_width = 8192; 1632926deccbSFrançois Tigeot rdev->ddev->mode_config.max_height = 8192; 1633926deccbSFrançois Tigeot } else { 1634926deccbSFrançois Tigeot rdev->ddev->mode_config.max_width = 4096; 1635926deccbSFrançois Tigeot rdev->ddev->mode_config.max_height = 4096; 1636926deccbSFrançois Tigeot } 1637926deccbSFrançois Tigeot 1638926deccbSFrançois Tigeot rdev->ddev->mode_config.preferred_depth = 24; 1639926deccbSFrançois Tigeot rdev->ddev->mode_config.prefer_shadow = 1; 1640926deccbSFrançois Tigeot 1641926deccbSFrançois Tigeot rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; 1642926deccbSFrançois Tigeot 1643926deccbSFrançois Tigeot ret = radeon_modeset_create_props(rdev); 1644926deccbSFrançois Tigeot if (ret) { 1645926deccbSFrançois Tigeot return ret; 1646926deccbSFrançois Tigeot } 1647926deccbSFrançois Tigeot 1648926deccbSFrançois Tigeot /* init i2c buses */ 1649926deccbSFrançois Tigeot radeon_i2c_init(rdev); 1650926deccbSFrançois Tigeot 1651926deccbSFrançois Tigeot /* check combios for a valid hardcoded EDID - Sun servers */ 1652926deccbSFrançois Tigeot if (!rdev->is_atom_bios) { 1653926deccbSFrançois Tigeot /* check for hardcoded EDID in BIOS */ 1654926deccbSFrançois Tigeot radeon_combios_check_hardcoded_edid(rdev); 1655926deccbSFrançois Tigeot } 1656926deccbSFrançois Tigeot 1657926deccbSFrançois Tigeot /* allocate crtcs */ 1658926deccbSFrançois Tigeot for (i = 0; i < rdev->num_crtc; i++) { 1659926deccbSFrançois Tigeot radeon_crtc_init(rdev->ddev, i); 1660926deccbSFrançois Tigeot } 1661926deccbSFrançois Tigeot 1662926deccbSFrançois Tigeot /* okay we should have all the bios connectors */ 1663926deccbSFrançois Tigeot ret = radeon_setup_enc_conn(rdev->ddev); 1664926deccbSFrançois Tigeot if (!ret) { 1665926deccbSFrançois Tigeot return ret; 1666926deccbSFrançois Tigeot } 1667926deccbSFrançois Tigeot 1668926deccbSFrançois Tigeot /* init dig PHYs, disp eng pll */ 1669926deccbSFrançois Tigeot if (rdev->is_atom_bios) { 1670926deccbSFrançois Tigeot radeon_atom_encoder_init(rdev); 1671926deccbSFrançois Tigeot radeon_atom_disp_eng_pll_init(rdev); 1672926deccbSFrançois Tigeot } 1673926deccbSFrançois Tigeot 1674926deccbSFrançois Tigeot /* initialize hpd */ 1675926deccbSFrançois Tigeot radeon_hpd_init(rdev); 1676926deccbSFrançois Tigeot 1677926deccbSFrançois Tigeot /* setup afmt */ 1678926deccbSFrançois Tigeot radeon_afmt_init(rdev); 1679926deccbSFrançois Tigeot 1680926deccbSFrançois Tigeot radeon_fbdev_init(rdev); 1681926deccbSFrançois Tigeot drm_kms_helper_poll_init(rdev->ddev); 1682926deccbSFrançois Tigeot 1683c59a5c48SFrançois Tigeot /* do pm late init */ 1684c6f73aabSFrançois Tigeot ret = radeon_pm_late_init(rdev); 1685c6f73aabSFrançois Tigeot 1686926deccbSFrançois Tigeot return 0; 1687926deccbSFrançois Tigeot } 1688926deccbSFrançois Tigeot 1689926deccbSFrançois Tigeot void radeon_modeset_fini(struct radeon_device *rdev) 1690926deccbSFrançois Tigeot { 16911dedbd3bSFrançois Tigeot if (rdev->mode_info.mode_config_initialized) { 16921dedbd3bSFrançois Tigeot drm_kms_helper_poll_fini(rdev->ddev); 16931dedbd3bSFrançois Tigeot radeon_hpd_fini(rdev); 16941dedbd3bSFrançois Tigeot drm_crtc_force_disable_all(rdev->ddev); 1695926deccbSFrançois Tigeot radeon_fbdev_fini(rdev); 16961dedbd3bSFrançois Tigeot radeon_afmt_fini(rdev); 16971dedbd3bSFrançois Tigeot drm_mode_config_cleanup(rdev->ddev); 16981dedbd3bSFrançois Tigeot rdev->mode_info.mode_config_initialized = false; 16991dedbd3bSFrançois Tigeot } 17001dedbd3bSFrançois Tigeot 1701c4ef309bSzrj kfree(rdev->mode_info.bios_hardcoded_edid); 1702926deccbSFrançois Tigeot 1703d78d3a22SFrançois Tigeot /* free i2c buses */ 1704d78d3a22SFrançois Tigeot radeon_i2c_fini(rdev); 1705926deccbSFrançois Tigeot } 1706926deccbSFrançois Tigeot 1707926deccbSFrançois Tigeot static bool is_hdtv_mode(const struct drm_display_mode *mode) 1708926deccbSFrançois Tigeot { 1709926deccbSFrançois Tigeot /* try and guess if this is a tv or a monitor */ 1710926deccbSFrançois Tigeot if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 1711926deccbSFrançois Tigeot (mode->vdisplay == 576) || /* 576p */ 1712926deccbSFrançois Tigeot (mode->vdisplay == 720) || /* 720p */ 1713926deccbSFrançois Tigeot (mode->vdisplay == 1080)) /* 1080p */ 1714926deccbSFrançois Tigeot return true; 1715926deccbSFrançois Tigeot else 1716926deccbSFrançois Tigeot return false; 1717926deccbSFrançois Tigeot } 1718926deccbSFrançois Tigeot 1719926deccbSFrançois Tigeot bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 1720926deccbSFrançois Tigeot const struct drm_display_mode *mode, 1721926deccbSFrançois Tigeot struct drm_display_mode *adjusted_mode) 1722926deccbSFrançois Tigeot { 1723926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev; 1724926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 1725926deccbSFrançois Tigeot struct drm_encoder *encoder; 1726926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1727926deccbSFrançois Tigeot struct radeon_encoder *radeon_encoder; 1728926deccbSFrançois Tigeot struct drm_connector *connector; 1729926deccbSFrançois Tigeot struct radeon_connector *radeon_connector; 1730926deccbSFrançois Tigeot bool first = true; 1731926deccbSFrançois Tigeot u32 src_v = 1, dst_v = 1; 1732926deccbSFrançois Tigeot u32 src_h = 1, dst_h = 1; 1733926deccbSFrançois Tigeot 1734926deccbSFrançois Tigeot radeon_crtc->h_border = 0; 1735926deccbSFrançois Tigeot radeon_crtc->v_border = 0; 1736926deccbSFrançois Tigeot 1737926deccbSFrançois Tigeot list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1738926deccbSFrançois Tigeot if (encoder->crtc != crtc) 1739926deccbSFrançois Tigeot continue; 1740926deccbSFrançois Tigeot radeon_encoder = to_radeon_encoder(encoder); 1741926deccbSFrançois Tigeot connector = radeon_get_connector_for_encoder(encoder); 1742926deccbSFrançois Tigeot radeon_connector = to_radeon_connector(connector); 1743926deccbSFrançois Tigeot 1744926deccbSFrançois Tigeot if (first) { 1745926deccbSFrançois Tigeot /* set scaling */ 1746926deccbSFrançois Tigeot if (radeon_encoder->rmx_type == RMX_OFF) 1747926deccbSFrançois Tigeot radeon_crtc->rmx_type = RMX_OFF; 1748926deccbSFrançois Tigeot else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || 1749926deccbSFrançois Tigeot mode->vdisplay < radeon_encoder->native_mode.vdisplay) 1750926deccbSFrançois Tigeot radeon_crtc->rmx_type = radeon_encoder->rmx_type; 1751926deccbSFrançois Tigeot else 1752926deccbSFrançois Tigeot radeon_crtc->rmx_type = RMX_OFF; 1753926deccbSFrançois Tigeot /* copy native mode */ 1754926deccbSFrançois Tigeot memcpy(&radeon_crtc->native_mode, 1755926deccbSFrançois Tigeot &radeon_encoder->native_mode, 1756926deccbSFrançois Tigeot sizeof(struct drm_display_mode)); 1757926deccbSFrançois Tigeot src_v = crtc->mode.vdisplay; 1758926deccbSFrançois Tigeot dst_v = radeon_crtc->native_mode.vdisplay; 1759926deccbSFrançois Tigeot src_h = crtc->mode.hdisplay; 1760926deccbSFrançois Tigeot dst_h = radeon_crtc->native_mode.hdisplay; 1761926deccbSFrançois Tigeot 1762926deccbSFrançois Tigeot /* fix up for overscan on hdmi */ 1763926deccbSFrançois Tigeot if (ASIC_IS_AVIVO(rdev) && 1764926deccbSFrançois Tigeot (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 1765926deccbSFrançois Tigeot ((radeon_encoder->underscan_type == UNDERSCAN_ON) || 1766926deccbSFrançois Tigeot ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && 1767c6f73aabSFrançois Tigeot drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 1768926deccbSFrançois Tigeot is_hdtv_mode(mode)))) { 1769926deccbSFrançois Tigeot if (radeon_encoder->underscan_hborder != 0) 1770926deccbSFrançois Tigeot radeon_crtc->h_border = radeon_encoder->underscan_hborder; 1771926deccbSFrançois Tigeot else 1772926deccbSFrançois Tigeot radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; 1773926deccbSFrançois Tigeot if (radeon_encoder->underscan_vborder != 0) 1774926deccbSFrançois Tigeot radeon_crtc->v_border = radeon_encoder->underscan_vborder; 1775926deccbSFrançois Tigeot else 1776926deccbSFrançois Tigeot radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; 1777926deccbSFrançois Tigeot radeon_crtc->rmx_type = RMX_FULL; 1778926deccbSFrançois Tigeot src_v = crtc->mode.vdisplay; 1779926deccbSFrançois Tigeot dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); 1780926deccbSFrançois Tigeot src_h = crtc->mode.hdisplay; 1781926deccbSFrançois Tigeot dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); 1782926deccbSFrançois Tigeot } 1783926deccbSFrançois Tigeot first = false; 1784926deccbSFrançois Tigeot } else { 1785926deccbSFrançois Tigeot if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { 1786926deccbSFrançois Tigeot /* WARNING: Right now this can't happen but 1787926deccbSFrançois Tigeot * in the future we need to check that scaling 1788926deccbSFrançois Tigeot * are consistent across different encoder 1789926deccbSFrançois Tigeot * (ie all encoder can work with the same 1790926deccbSFrançois Tigeot * scaling). 1791926deccbSFrançois Tigeot */ 1792926deccbSFrançois Tigeot DRM_ERROR("Scaling not consistent across encoder.\n"); 1793926deccbSFrançois Tigeot return false; 1794926deccbSFrançois Tigeot } 1795926deccbSFrançois Tigeot } 1796926deccbSFrançois Tigeot } 1797926deccbSFrançois Tigeot if (radeon_crtc->rmx_type != RMX_OFF) { 1798926deccbSFrançois Tigeot fixed20_12 a, b; 1799926deccbSFrançois Tigeot a.full = dfixed_const(src_v); 1800926deccbSFrançois Tigeot b.full = dfixed_const(dst_v); 1801926deccbSFrançois Tigeot radeon_crtc->vsc.full = dfixed_div(a, b); 1802926deccbSFrançois Tigeot a.full = dfixed_const(src_h); 1803926deccbSFrançois Tigeot b.full = dfixed_const(dst_h); 1804926deccbSFrançois Tigeot radeon_crtc->hsc.full = dfixed_div(a, b); 1805926deccbSFrançois Tigeot } else { 1806926deccbSFrançois Tigeot radeon_crtc->vsc.full = dfixed_const(1); 1807926deccbSFrançois Tigeot radeon_crtc->hsc.full = dfixed_const(1); 1808926deccbSFrançois Tigeot } 1809926deccbSFrançois Tigeot return true; 1810926deccbSFrançois Tigeot } 1811926deccbSFrançois Tigeot 1812926deccbSFrançois Tigeot /* 1813782e40d3SFrançois Tigeot * Retrieve current video scanout position of crtc on a given gpu, and 1814782e40d3SFrançois Tigeot * an optional accurate timestamp of when query happened. 1815926deccbSFrançois Tigeot * 1816926deccbSFrançois Tigeot * \param dev Device to query. 1817926deccbSFrançois Tigeot * \param crtc Crtc to query. 1818782e40d3SFrançois Tigeot * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 1819c59a5c48SFrançois Tigeot * For driver internal use only also supports these flags: 1820c59a5c48SFrançois Tigeot * 1821c59a5c48SFrançois Tigeot * USE_REAL_VBLANKSTART to use the real start of vblank instead 1822c59a5c48SFrançois Tigeot * of a fudged earlier start of vblank. 1823c59a5c48SFrançois Tigeot * 1824c59a5c48SFrançois Tigeot * GET_DISTANCE_TO_VBLANKSTART to return distance to the 1825c59a5c48SFrançois Tigeot * fudged earlier start of vblank in *vpos and the distance 1826c59a5c48SFrançois Tigeot * to true start of vblank in *hpos. 1827c59a5c48SFrançois Tigeot * 1828926deccbSFrançois Tigeot * \param *vpos Location where vertical scanout position should be stored. 1829926deccbSFrançois Tigeot * \param *hpos Location where horizontal scanout position should go. 1830782e40d3SFrançois Tigeot * \param *stime Target location for timestamp taken immediately before 1831782e40d3SFrançois Tigeot * scanout position query. Can be NULL to skip timestamp. 1832782e40d3SFrançois Tigeot * \param *etime Target location for timestamp taken immediately after 1833782e40d3SFrançois Tigeot * scanout position query. Can be NULL to skip timestamp. 1834926deccbSFrançois Tigeot * 1835926deccbSFrançois Tigeot * Returns vpos as a positive number while in active scanout area. 1836926deccbSFrançois Tigeot * Returns vpos as a negative number inside vblank, counting the number 1837926deccbSFrançois Tigeot * of scanlines to go until end of vblank, e.g., -1 means "one scanline 1838926deccbSFrançois Tigeot * until start of active scanout / end of vblank." 1839926deccbSFrançois Tigeot * 1840926deccbSFrançois Tigeot * \return Flags, or'ed together as follows: 1841926deccbSFrançois Tigeot * 1842926deccbSFrançois Tigeot * DRM_SCANOUTPOS_VALID = Query successful. 1843926deccbSFrançois Tigeot * DRM_SCANOUTPOS_INVBL = Inside vblank. 1844926deccbSFrançois Tigeot * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 1845926deccbSFrançois Tigeot * this flag means that returned position may be offset by a constant but 1846926deccbSFrançois Tigeot * unknown small number of scanlines wrt. real scanout position. 1847926deccbSFrançois Tigeot * 1848926deccbSFrançois Tigeot */ 1849c59a5c48SFrançois Tigeot int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 1850c59a5c48SFrançois Tigeot unsigned int flags, int *vpos, int *hpos, 1851c59a5c48SFrançois Tigeot ktime_t *stime, ktime_t *etime, 1852352ff8bdSFrançois Tigeot const struct drm_display_mode *mode) 1853926deccbSFrançois Tigeot { 1854926deccbSFrançois Tigeot u32 stat_crtc = 0, vbl = 0, position = 0; 1855926deccbSFrançois Tigeot int vbl_start, vbl_end, vtotal, ret = 0; 1856926deccbSFrançois Tigeot bool in_vbl = true; 1857926deccbSFrançois Tigeot 1858926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 1859926deccbSFrançois Tigeot 1860782e40d3SFrançois Tigeot /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 1861782e40d3SFrançois Tigeot 1862782e40d3SFrançois Tigeot /* Get optional system timestamp before query. */ 1863782e40d3SFrançois Tigeot if (stime) 1864782e40d3SFrançois Tigeot *stime = ktime_get(); 1865782e40d3SFrançois Tigeot 1866926deccbSFrançois Tigeot if (ASIC_IS_DCE4(rdev)) { 1867c59a5c48SFrançois Tigeot if (pipe == 0) { 1868926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1869926deccbSFrançois Tigeot EVERGREEN_CRTC0_REGISTER_OFFSET); 1870926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1871926deccbSFrançois Tigeot EVERGREEN_CRTC0_REGISTER_OFFSET); 1872926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1873926deccbSFrançois Tigeot } 1874c59a5c48SFrançois Tigeot if (pipe == 1) { 1875926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1876926deccbSFrançois Tigeot EVERGREEN_CRTC1_REGISTER_OFFSET); 1877926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1878926deccbSFrançois Tigeot EVERGREEN_CRTC1_REGISTER_OFFSET); 1879926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1880926deccbSFrançois Tigeot } 1881c59a5c48SFrançois Tigeot if (pipe == 2) { 1882926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1883926deccbSFrançois Tigeot EVERGREEN_CRTC2_REGISTER_OFFSET); 1884926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1885926deccbSFrançois Tigeot EVERGREEN_CRTC2_REGISTER_OFFSET); 1886926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1887926deccbSFrançois Tigeot } 1888c59a5c48SFrançois Tigeot if (pipe == 3) { 1889926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1890926deccbSFrançois Tigeot EVERGREEN_CRTC3_REGISTER_OFFSET); 1891926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1892926deccbSFrançois Tigeot EVERGREEN_CRTC3_REGISTER_OFFSET); 1893926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1894926deccbSFrançois Tigeot } 1895c59a5c48SFrançois Tigeot if (pipe == 4) { 1896926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1897926deccbSFrançois Tigeot EVERGREEN_CRTC4_REGISTER_OFFSET); 1898926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1899926deccbSFrançois Tigeot EVERGREEN_CRTC4_REGISTER_OFFSET); 1900926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1901926deccbSFrançois Tigeot } 1902c59a5c48SFrançois Tigeot if (pipe == 5) { 1903926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1904926deccbSFrançois Tigeot EVERGREEN_CRTC5_REGISTER_OFFSET); 1905926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1906926deccbSFrançois Tigeot EVERGREEN_CRTC5_REGISTER_OFFSET); 1907926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1908926deccbSFrançois Tigeot } 1909926deccbSFrançois Tigeot } else if (ASIC_IS_AVIVO(rdev)) { 1910c59a5c48SFrançois Tigeot if (pipe == 0) { 1911926deccbSFrançois Tigeot vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); 1912926deccbSFrançois Tigeot position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); 1913926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1914926deccbSFrançois Tigeot } 1915c59a5c48SFrançois Tigeot if (pipe == 1) { 1916926deccbSFrançois Tigeot vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); 1917926deccbSFrançois Tigeot position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); 1918926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1919926deccbSFrançois Tigeot } 1920926deccbSFrançois Tigeot } else { 1921926deccbSFrançois Tigeot /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ 1922c59a5c48SFrançois Tigeot if (pipe == 0) { 1923926deccbSFrançois Tigeot /* Assume vbl_end == 0, get vbl_start from 1924926deccbSFrançois Tigeot * upper 16 bits. 1925926deccbSFrançois Tigeot */ 1926926deccbSFrançois Tigeot vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & 1927926deccbSFrançois Tigeot RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1928926deccbSFrançois Tigeot /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ 1929926deccbSFrançois Tigeot position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1930926deccbSFrançois Tigeot stat_crtc = RREG32(RADEON_CRTC_STATUS); 1931926deccbSFrançois Tigeot if (!(stat_crtc & 1)) 1932926deccbSFrançois Tigeot in_vbl = false; 1933926deccbSFrançois Tigeot 1934926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1935926deccbSFrançois Tigeot } 1936c59a5c48SFrançois Tigeot if (pipe == 1) { 1937926deccbSFrançois Tigeot vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & 1938926deccbSFrançois Tigeot RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1939926deccbSFrançois Tigeot position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1940926deccbSFrançois Tigeot stat_crtc = RREG32(RADEON_CRTC2_STATUS); 1941926deccbSFrançois Tigeot if (!(stat_crtc & 1)) 1942926deccbSFrançois Tigeot in_vbl = false; 1943926deccbSFrançois Tigeot 1944926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1945926deccbSFrançois Tigeot } 1946926deccbSFrançois Tigeot } 1947926deccbSFrançois Tigeot 1948782e40d3SFrançois Tigeot /* Get optional system timestamp after query. */ 1949782e40d3SFrançois Tigeot if (etime) 1950782e40d3SFrançois Tigeot *etime = ktime_get(); 1951782e40d3SFrançois Tigeot 1952782e40d3SFrançois Tigeot /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 1953782e40d3SFrançois Tigeot 1954926deccbSFrançois Tigeot /* Decode into vertical and horizontal scanout position. */ 1955926deccbSFrançois Tigeot *vpos = position & 0x1fff; 1956926deccbSFrançois Tigeot *hpos = (position >> 16) & 0x1fff; 1957926deccbSFrançois Tigeot 1958926deccbSFrançois Tigeot /* Valid vblank area boundaries from gpu retrieved? */ 1959926deccbSFrançois Tigeot if (vbl > 0) { 1960926deccbSFrançois Tigeot /* Yes: Decode. */ 1961926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_ACCURATE; 1962926deccbSFrançois Tigeot vbl_start = vbl & 0x1fff; 1963926deccbSFrançois Tigeot vbl_end = (vbl >> 16) & 0x1fff; 1964926deccbSFrançois Tigeot } 1965926deccbSFrançois Tigeot else { 1966926deccbSFrançois Tigeot /* No: Fake something reasonable which gives at least ok results. */ 1967c59a5c48SFrançois Tigeot vbl_start = mode->crtc_vdisplay; 1968926deccbSFrançois Tigeot vbl_end = 0; 1969926deccbSFrançois Tigeot } 1970926deccbSFrançois Tigeot 1971c59a5c48SFrançois Tigeot /* Called from driver internal vblank counter query code? */ 1972c59a5c48SFrançois Tigeot if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1973c59a5c48SFrançois Tigeot /* Caller wants distance from real vbl_start in *hpos */ 1974c59a5c48SFrançois Tigeot *hpos = *vpos - vbl_start; 1975c59a5c48SFrançois Tigeot } 1976c59a5c48SFrançois Tigeot 1977c59a5c48SFrançois Tigeot /* Fudge vblank to start a few scanlines earlier to handle the 1978c59a5c48SFrançois Tigeot * problem that vblank irqs fire a few scanlines before start 1979c59a5c48SFrançois Tigeot * of vblank. Some driver internal callers need the true vblank 1980c59a5c48SFrançois Tigeot * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 1981c59a5c48SFrançois Tigeot * 1982c59a5c48SFrançois Tigeot * The cause of the "early" vblank irq is that the irq is triggered 1983c59a5c48SFrançois Tigeot * by the line buffer logic when the line buffer read position enters 1984c59a5c48SFrançois Tigeot * the vblank, whereas our crtc scanout position naturally lags the 1985c59a5c48SFrançois Tigeot * line buffer read position. 1986c59a5c48SFrançois Tigeot */ 1987c59a5c48SFrançois Tigeot if (!(flags & USE_REAL_VBLANKSTART)) 1988c59a5c48SFrançois Tigeot vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 1989c59a5c48SFrançois Tigeot 1990926deccbSFrançois Tigeot /* Test scanout position against vblank region. */ 1991926deccbSFrançois Tigeot if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 1992926deccbSFrançois Tigeot in_vbl = false; 1993926deccbSFrançois Tigeot 1994c59a5c48SFrançois Tigeot /* In vblank? */ 1995c59a5c48SFrançois Tigeot if (in_vbl) 1996c59a5c48SFrançois Tigeot ret |= DRM_SCANOUTPOS_IN_VBLANK; 1997c59a5c48SFrançois Tigeot 1998c59a5c48SFrançois Tigeot /* Called from driver internal vblank counter query code? */ 1999c59a5c48SFrançois Tigeot if (flags & GET_DISTANCE_TO_VBLANKSTART) { 2000c59a5c48SFrançois Tigeot /* Caller wants distance from fudged earlier vbl_start */ 2001c59a5c48SFrançois Tigeot *vpos -= vbl_start; 2002c59a5c48SFrançois Tigeot return ret; 2003c59a5c48SFrançois Tigeot } 2004c59a5c48SFrançois Tigeot 2005926deccbSFrançois Tigeot /* Check if inside vblank area and apply corrective offsets: 2006926deccbSFrançois Tigeot * vpos will then be >=0 in video scanout area, but negative 2007926deccbSFrançois Tigeot * within vblank area, counting down the number of lines until 2008926deccbSFrançois Tigeot * start of scanout. 2009926deccbSFrançois Tigeot */ 2010926deccbSFrançois Tigeot 2011926deccbSFrançois Tigeot /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 2012926deccbSFrançois Tigeot if (in_vbl && (*vpos >= vbl_start)) { 2013c59a5c48SFrançois Tigeot vtotal = mode->crtc_vtotal; 2014926deccbSFrançois Tigeot *vpos = *vpos - vtotal; 2015926deccbSFrançois Tigeot } 2016926deccbSFrançois Tigeot 2017926deccbSFrançois Tigeot /* Correct for shifted end of vbl at vbl_end. */ 2018926deccbSFrançois Tigeot *vpos = *vpos - vbl_end; 2019926deccbSFrançois Tigeot 2020926deccbSFrançois Tigeot return ret; 2021926deccbSFrançois Tigeot } 2022