1926deccbSFrançois Tigeot /* 2926deccbSFrançois Tigeot * Copyright 2007-8 Advanced Micro Devices, Inc. 3926deccbSFrançois Tigeot * Copyright 2008 Red Hat Inc. 4926deccbSFrançois Tigeot * 5926deccbSFrançois Tigeot * Permission is hereby granted, free of charge, to any person obtaining a 6926deccbSFrançois Tigeot * copy of this software and associated documentation files (the "Software"), 7926deccbSFrançois Tigeot * to deal in the Software without restriction, including without limitation 8926deccbSFrançois Tigeot * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9926deccbSFrançois Tigeot * and/or sell copies of the Software, and to permit persons to whom the 10926deccbSFrançois Tigeot * Software is furnished to do so, subject to the following conditions: 11926deccbSFrançois Tigeot * 12926deccbSFrançois Tigeot * The above copyright notice and this permission notice shall be included in 13926deccbSFrançois Tigeot * all copies or substantial portions of the Software. 14926deccbSFrançois Tigeot * 15926deccbSFrançois Tigeot * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16926deccbSFrançois Tigeot * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17926deccbSFrançois Tigeot * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18926deccbSFrançois Tigeot * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19926deccbSFrançois Tigeot * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20926deccbSFrançois Tigeot * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21926deccbSFrançois Tigeot * OTHER DEALINGS IN THE SOFTWARE. 22926deccbSFrançois Tigeot * 23926deccbSFrançois Tigeot * Authors: Dave Airlie 24926deccbSFrançois Tigeot * Alex Deucher 25926deccbSFrançois Tigeot * 26926deccbSFrançois Tigeot * $FreeBSD: head/sys/dev/drm2/radeon/radeon_display.c 254885 2013-08-25 19:37:15Z dumbbell $ 27926deccbSFrançois Tigeot */ 28926deccbSFrançois Tigeot 29926deccbSFrançois Tigeot #include <drm/drmP.h> 30926deccbSFrançois Tigeot #include <uapi_drm/radeon_drm.h> 31926deccbSFrançois Tigeot #include "radeon.h" 32926deccbSFrançois Tigeot 33926deccbSFrançois Tigeot #include "atom.h" 34926deccbSFrançois Tigeot 35926deccbSFrançois Tigeot #include <drm/drm_crtc_helper.h> 36926deccbSFrançois Tigeot #include <drm/drm_edid.h> 3760fc7eecSFrançois Tigeot #include <linux/err.h> 38926deccbSFrançois Tigeot 39926deccbSFrançois Tigeot static void avivo_crtc_load_lut(struct drm_crtc *crtc) 40926deccbSFrançois Tigeot { 41926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 42926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev; 43926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 44926deccbSFrançois Tigeot int i; 45926deccbSFrançois Tigeot 46926deccbSFrançois Tigeot DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 47926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); 48926deccbSFrançois Tigeot 49926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 50926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 51926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 52926deccbSFrançois Tigeot 53926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 54926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 55926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 56926deccbSFrançois Tigeot 57926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); 58926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUT_RW_MODE, 0); 59926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); 60926deccbSFrançois Tigeot 61926deccbSFrançois Tigeot WREG8(AVIVO_DC_LUT_RW_INDEX, 0); 62926deccbSFrançois Tigeot for (i = 0; i < 256; i++) { 63926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUT_30_COLOR, 64926deccbSFrançois Tigeot (radeon_crtc->lut_r[i] << 20) | 65926deccbSFrançois Tigeot (radeon_crtc->lut_g[i] << 10) | 66926deccbSFrançois Tigeot (radeon_crtc->lut_b[i] << 0)); 67926deccbSFrançois Tigeot } 68926deccbSFrançois Tigeot 69926deccbSFrançois Tigeot WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); 70926deccbSFrançois Tigeot } 71926deccbSFrançois Tigeot 72926deccbSFrançois Tigeot static void dce4_crtc_load_lut(struct drm_crtc *crtc) 73926deccbSFrançois Tigeot { 74926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 75926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev; 76926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 77926deccbSFrançois Tigeot int i; 78926deccbSFrançois Tigeot 79926deccbSFrançois Tigeot DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 80926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 81926deccbSFrançois Tigeot 82926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 83926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 84926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 85926deccbSFrançois Tigeot 86926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 87926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 88926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 89926deccbSFrançois Tigeot 90926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 91926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 92926deccbSFrançois Tigeot 93926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 94926deccbSFrançois Tigeot for (i = 0; i < 256; i++) { 95926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 96926deccbSFrançois Tigeot (radeon_crtc->lut_r[i] << 20) | 97926deccbSFrançois Tigeot (radeon_crtc->lut_g[i] << 10) | 98926deccbSFrançois Tigeot (radeon_crtc->lut_b[i] << 0)); 99926deccbSFrançois Tigeot } 100926deccbSFrançois Tigeot } 101926deccbSFrançois Tigeot 102926deccbSFrançois Tigeot static void dce5_crtc_load_lut(struct drm_crtc *crtc) 103926deccbSFrançois Tigeot { 104926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 105926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev; 106926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 107926deccbSFrançois Tigeot int i; 108926deccbSFrançois Tigeot 109926deccbSFrançois Tigeot DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 110926deccbSFrançois Tigeot 111926deccbSFrançois Tigeot WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 112926deccbSFrançois Tigeot (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | 113926deccbSFrançois Tigeot NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); 114926deccbSFrançois Tigeot WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, 115926deccbSFrançois Tigeot NI_GRPH_PRESCALE_BYPASS); 116926deccbSFrançois Tigeot WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, 117926deccbSFrançois Tigeot NI_OVL_PRESCALE_BYPASS); 118926deccbSFrançois Tigeot WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, 119926deccbSFrançois Tigeot (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | 120926deccbSFrançois Tigeot NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); 121926deccbSFrançois Tigeot 122926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 123926deccbSFrançois Tigeot 124926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 125926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 126926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 127926deccbSFrançois Tigeot 128926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 129926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 130926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 131926deccbSFrançois Tigeot 132926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 133926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 134926deccbSFrançois Tigeot 135926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 136926deccbSFrançois Tigeot for (i = 0; i < 256; i++) { 137926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 138926deccbSFrançois Tigeot (radeon_crtc->lut_r[i] << 20) | 139926deccbSFrançois Tigeot (radeon_crtc->lut_g[i] << 10) | 140926deccbSFrançois Tigeot (radeon_crtc->lut_b[i] << 0)); 141926deccbSFrançois Tigeot } 142926deccbSFrançois Tigeot 143926deccbSFrançois Tigeot WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, 144926deccbSFrançois Tigeot (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 145926deccbSFrançois Tigeot NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 146926deccbSFrançois Tigeot NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 147926deccbSFrançois Tigeot NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); 148926deccbSFrançois Tigeot WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, 149926deccbSFrançois Tigeot (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | 150926deccbSFrançois Tigeot NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); 151926deccbSFrançois Tigeot WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, 152926deccbSFrançois Tigeot (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | 153926deccbSFrançois Tigeot NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); 154926deccbSFrançois Tigeot WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 155926deccbSFrançois Tigeot (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) | 156926deccbSFrançois Tigeot NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); 157926deccbSFrançois Tigeot /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 158926deccbSFrançois Tigeot WREG32(0x6940 + radeon_crtc->crtc_offset, 0); 159926deccbSFrançois Tigeot 160926deccbSFrançois Tigeot } 161926deccbSFrançois Tigeot 162926deccbSFrançois Tigeot static void legacy_crtc_load_lut(struct drm_crtc *crtc) 163926deccbSFrançois Tigeot { 164926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 165926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev; 166926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 167926deccbSFrançois Tigeot int i; 168926deccbSFrançois Tigeot uint32_t dac2_cntl; 169926deccbSFrançois Tigeot 170926deccbSFrançois Tigeot dac2_cntl = RREG32(RADEON_DAC_CNTL2); 171926deccbSFrançois Tigeot if (radeon_crtc->crtc_id == 0) 172926deccbSFrançois Tigeot dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; 173926deccbSFrançois Tigeot else 174926deccbSFrançois Tigeot dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; 175926deccbSFrançois Tigeot WREG32(RADEON_DAC_CNTL2, dac2_cntl); 176926deccbSFrançois Tigeot 177926deccbSFrançois Tigeot WREG8(RADEON_PALETTE_INDEX, 0); 178926deccbSFrançois Tigeot for (i = 0; i < 256; i++) { 179926deccbSFrançois Tigeot WREG32(RADEON_PALETTE_30_DATA, 180926deccbSFrançois Tigeot (radeon_crtc->lut_r[i] << 20) | 181926deccbSFrançois Tigeot (radeon_crtc->lut_g[i] << 10) | 182926deccbSFrançois Tigeot (radeon_crtc->lut_b[i] << 0)); 183926deccbSFrançois Tigeot } 184926deccbSFrançois Tigeot } 185926deccbSFrançois Tigeot 186926deccbSFrançois Tigeot void radeon_crtc_load_lut(struct drm_crtc *crtc) 187926deccbSFrançois Tigeot { 188926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev; 189926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 190926deccbSFrançois Tigeot 191926deccbSFrançois Tigeot if (!crtc->enabled) 192926deccbSFrançois Tigeot return; 193926deccbSFrançois Tigeot 194926deccbSFrançois Tigeot if (ASIC_IS_DCE5(rdev)) 195926deccbSFrançois Tigeot dce5_crtc_load_lut(crtc); 196926deccbSFrançois Tigeot else if (ASIC_IS_DCE4(rdev)) 197926deccbSFrançois Tigeot dce4_crtc_load_lut(crtc); 198926deccbSFrançois Tigeot else if (ASIC_IS_AVIVO(rdev)) 199926deccbSFrançois Tigeot avivo_crtc_load_lut(crtc); 200926deccbSFrançois Tigeot else 201926deccbSFrançois Tigeot legacy_crtc_load_lut(crtc); 202926deccbSFrançois Tigeot } 203926deccbSFrançois Tigeot 204926deccbSFrançois Tigeot /** Sets the color ramps on behalf of fbcon */ 205926deccbSFrançois Tigeot void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 206926deccbSFrançois Tigeot u16 blue, int regno) 207926deccbSFrançois Tigeot { 208926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 209926deccbSFrançois Tigeot 210926deccbSFrançois Tigeot radeon_crtc->lut_r[regno] = red >> 6; 211926deccbSFrançois Tigeot radeon_crtc->lut_g[regno] = green >> 6; 212926deccbSFrançois Tigeot radeon_crtc->lut_b[regno] = blue >> 6; 213926deccbSFrançois Tigeot } 214926deccbSFrançois Tigeot 215926deccbSFrançois Tigeot /** Gets the color ramps on behalf of fbcon */ 216926deccbSFrançois Tigeot void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 217926deccbSFrançois Tigeot u16 *blue, int regno) 218926deccbSFrançois Tigeot { 219926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 220926deccbSFrançois Tigeot 221926deccbSFrançois Tigeot *red = radeon_crtc->lut_r[regno] << 6; 222926deccbSFrançois Tigeot *green = radeon_crtc->lut_g[regno] << 6; 223926deccbSFrançois Tigeot *blue = radeon_crtc->lut_b[regno] << 6; 224926deccbSFrançois Tigeot } 225926deccbSFrançois Tigeot 226926deccbSFrançois Tigeot static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 227926deccbSFrançois Tigeot u16 *blue, uint32_t start, uint32_t size) 228926deccbSFrançois Tigeot { 229926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 230926deccbSFrançois Tigeot int end = (start + size > 256) ? 256 : start + size, i; 231926deccbSFrançois Tigeot 232926deccbSFrançois Tigeot /* userspace palettes are always correct as is */ 233926deccbSFrançois Tigeot for (i = start; i < end; i++) { 234926deccbSFrançois Tigeot radeon_crtc->lut_r[i] = red[i] >> 6; 235926deccbSFrançois Tigeot radeon_crtc->lut_g[i] = green[i] >> 6; 236926deccbSFrançois Tigeot radeon_crtc->lut_b[i] = blue[i] >> 6; 237926deccbSFrançois Tigeot } 238926deccbSFrançois Tigeot radeon_crtc_load_lut(crtc); 239926deccbSFrançois Tigeot } 240926deccbSFrançois Tigeot 241926deccbSFrançois Tigeot static void radeon_crtc_destroy(struct drm_crtc *crtc) 242926deccbSFrançois Tigeot { 243926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 244926deccbSFrançois Tigeot 245926deccbSFrançois Tigeot drm_crtc_cleanup(crtc); 2465a3b77d5SFrançois Tigeot drm_free(radeon_crtc, M_DRM); 247926deccbSFrançois Tigeot } 248926deccbSFrançois Tigeot 249926deccbSFrançois Tigeot /* 250926deccbSFrançois Tigeot * Handle unpin events outside the interrupt handler proper. 251926deccbSFrançois Tigeot */ 252926deccbSFrançois Tigeot static void radeon_unpin_work_func(void *arg, int pending) 253926deccbSFrançois Tigeot { 254926deccbSFrançois Tigeot struct radeon_unpin_work *work = arg; 255926deccbSFrançois Tigeot int r; 256926deccbSFrançois Tigeot 257926deccbSFrançois Tigeot /* unpin of the old buffer */ 258926deccbSFrançois Tigeot r = radeon_bo_reserve(work->old_rbo, false); 259926deccbSFrançois Tigeot if (likely(r == 0)) { 260926deccbSFrançois Tigeot r = radeon_bo_unpin(work->old_rbo); 261926deccbSFrançois Tigeot if (unlikely(r != 0)) { 262926deccbSFrançois Tigeot DRM_ERROR("failed to unpin buffer after flip\n"); 263926deccbSFrançois Tigeot } 264926deccbSFrançois Tigeot radeon_bo_unreserve(work->old_rbo); 265926deccbSFrançois Tigeot } else 266926deccbSFrançois Tigeot DRM_ERROR("failed to reserve buffer after flip\n"); 267926deccbSFrançois Tigeot 268926deccbSFrançois Tigeot drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 2695a3b77d5SFrançois Tigeot drm_free(work, M_DRM); 270926deccbSFrançois Tigeot } 271926deccbSFrançois Tigeot 272926deccbSFrançois Tigeot void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) 273926deccbSFrançois Tigeot { 274926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 275926deccbSFrançois Tigeot struct radeon_unpin_work *work; 276926deccbSFrançois Tigeot struct drm_pending_vblank_event *e; 277926deccbSFrançois Tigeot struct timeval now; 278926deccbSFrançois Tigeot u32 update_pending; 279926deccbSFrançois Tigeot int vpos, hpos; 280926deccbSFrançois Tigeot 281926deccbSFrançois Tigeot lockmgr(&rdev->ddev->event_lock, LK_EXCLUSIVE); 282926deccbSFrançois Tigeot work = radeon_crtc->unpin_work; 283926deccbSFrançois Tigeot if (work == NULL || 284926deccbSFrançois Tigeot (work->fence && !radeon_fence_signaled(work->fence))) { 285926deccbSFrançois Tigeot lockmgr(&rdev->ddev->event_lock, LK_RELEASE); 286926deccbSFrançois Tigeot return; 287926deccbSFrançois Tigeot } 288926deccbSFrançois Tigeot /* New pageflip, or just completion of a previous one? */ 289926deccbSFrançois Tigeot if (!radeon_crtc->deferred_flip_completion) { 290926deccbSFrançois Tigeot /* do the flip (mmio) */ 291926deccbSFrançois Tigeot update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base); 292926deccbSFrançois Tigeot } else { 293926deccbSFrançois Tigeot /* This is just a completion of a flip queued in crtc 294926deccbSFrançois Tigeot * at last invocation. Make sure we go directly to 295926deccbSFrançois Tigeot * completion routine. 296926deccbSFrançois Tigeot */ 297926deccbSFrançois Tigeot update_pending = 0; 298926deccbSFrançois Tigeot radeon_crtc->deferred_flip_completion = 0; 299926deccbSFrançois Tigeot } 300926deccbSFrançois Tigeot 301926deccbSFrançois Tigeot /* Has the pageflip already completed in crtc, or is it certain 302926deccbSFrançois Tigeot * to complete in this vblank? 303926deccbSFrançois Tigeot */ 304926deccbSFrançois Tigeot if (update_pending && 305926deccbSFrançois Tigeot (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 306926deccbSFrançois Tigeot &vpos, &hpos)) && 307926deccbSFrançois Tigeot ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) || 308926deccbSFrançois Tigeot (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) { 309926deccbSFrançois Tigeot /* crtc didn't flip in this target vblank interval, 310926deccbSFrançois Tigeot * but flip is pending in crtc. Based on the current 311926deccbSFrançois Tigeot * scanout position we know that the current frame is 312926deccbSFrançois Tigeot * (nearly) complete and the flip will (likely) 313926deccbSFrançois Tigeot * complete before the start of the next frame. 314926deccbSFrançois Tigeot */ 315926deccbSFrançois Tigeot update_pending = 0; 316926deccbSFrançois Tigeot } 317926deccbSFrançois Tigeot if (update_pending) { 318926deccbSFrançois Tigeot /* crtc didn't flip in this target vblank interval, 319926deccbSFrançois Tigeot * but flip is pending in crtc. It will complete it 320926deccbSFrançois Tigeot * in next vblank interval, so complete the flip at 321926deccbSFrançois Tigeot * next vblank irq. 322926deccbSFrançois Tigeot */ 323926deccbSFrançois Tigeot radeon_crtc->deferred_flip_completion = 1; 324926deccbSFrançois Tigeot lockmgr(&rdev->ddev->event_lock, LK_RELEASE); 325926deccbSFrançois Tigeot return; 326926deccbSFrançois Tigeot } 327926deccbSFrançois Tigeot 328926deccbSFrançois Tigeot /* Pageflip (will be) certainly completed in this vblank. Clean up. */ 329926deccbSFrançois Tigeot radeon_crtc->unpin_work = NULL; 330926deccbSFrançois Tigeot 331926deccbSFrançois Tigeot /* wakeup userspace */ 332926deccbSFrançois Tigeot if (work->event) { 333926deccbSFrançois Tigeot e = work->event; 334926deccbSFrançois Tigeot e->event.sequence = drm_vblank_count_and_time(rdev->ddev, crtc_id, &now); 335926deccbSFrançois Tigeot e->event.tv_sec = now.tv_sec; 336926deccbSFrançois Tigeot e->event.tv_usec = now.tv_usec; 337926deccbSFrançois Tigeot list_add_tail(&e->base.link, &e->base.file_priv->event_list); 338ac145779SImre Vadasz drm_event_wakeup(&e->base); 339926deccbSFrançois Tigeot } 340926deccbSFrançois Tigeot lockmgr(&rdev->ddev->event_lock, LK_RELEASE); 341926deccbSFrançois Tigeot 342926deccbSFrançois Tigeot drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id); 343926deccbSFrançois Tigeot radeon_fence_unref(&work->fence); 344926deccbSFrançois Tigeot radeon_post_page_flip(work->rdev, work->crtc_id); 345926deccbSFrançois Tigeot taskqueue_enqueue(rdev->tq, &work->work); 346926deccbSFrançois Tigeot } 347926deccbSFrançois Tigeot 348926deccbSFrançois Tigeot static int radeon_crtc_page_flip(struct drm_crtc *crtc, 349926deccbSFrançois Tigeot struct drm_framebuffer *fb, 350*9edbd4a0SFrançois Tigeot struct drm_pending_vblank_event *event, 351*9edbd4a0SFrançois Tigeot uint32_t page_flip_flags) 352926deccbSFrançois Tigeot { 353926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev; 354926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 355926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 356926deccbSFrançois Tigeot struct radeon_framebuffer *old_radeon_fb; 357926deccbSFrançois Tigeot struct radeon_framebuffer *new_radeon_fb; 358926deccbSFrançois Tigeot struct drm_gem_object *obj; 359926deccbSFrançois Tigeot struct radeon_bo *rbo; 360926deccbSFrançois Tigeot struct radeon_unpin_work *work; 361926deccbSFrançois Tigeot u32 tiling_flags, pitch_pixels; 362926deccbSFrançois Tigeot u64 base; 363926deccbSFrançois Tigeot int r; 364926deccbSFrançois Tigeot 3655a3b77d5SFrançois Tigeot work = kmalloc(sizeof *work, M_DRM, M_WAITOK | M_ZERO); 366926deccbSFrançois Tigeot if (work == NULL) 367926deccbSFrançois Tigeot return -ENOMEM; 368926deccbSFrançois Tigeot 369926deccbSFrançois Tigeot work->event = event; 370926deccbSFrançois Tigeot work->rdev = rdev; 371926deccbSFrançois Tigeot work->crtc_id = radeon_crtc->crtc_id; 372926deccbSFrançois Tigeot old_radeon_fb = to_radeon_framebuffer(crtc->fb); 373926deccbSFrançois Tigeot new_radeon_fb = to_radeon_framebuffer(fb); 374926deccbSFrançois Tigeot /* schedule unpin of the old buffer */ 375926deccbSFrançois Tigeot obj = old_radeon_fb->obj; 376926deccbSFrançois Tigeot /* take a reference to the old object */ 377926deccbSFrançois Tigeot drm_gem_object_reference(obj); 378926deccbSFrançois Tigeot rbo = gem_to_radeon_bo(obj); 379926deccbSFrançois Tigeot work->old_rbo = rbo; 380926deccbSFrançois Tigeot obj = new_radeon_fb->obj; 381926deccbSFrançois Tigeot rbo = gem_to_radeon_bo(obj); 382926deccbSFrançois Tigeot 383926deccbSFrançois Tigeot lockmgr(&rbo->tbo.bdev->fence_lock, LK_EXCLUSIVE); 384926deccbSFrançois Tigeot if (rbo->tbo.sync_obj) 385926deccbSFrançois Tigeot work->fence = radeon_fence_ref(rbo->tbo.sync_obj); 386926deccbSFrançois Tigeot lockmgr(&rbo->tbo.bdev->fence_lock, LK_RELEASE); 387926deccbSFrançois Tigeot 388926deccbSFrançois Tigeot TASK_INIT(&work->work, 0, radeon_unpin_work_func, work); 389926deccbSFrançois Tigeot 390926deccbSFrançois Tigeot /* We borrow the event spin lock for protecting unpin_work */ 391926deccbSFrançois Tigeot lockmgr(&dev->event_lock, LK_EXCLUSIVE); 392926deccbSFrançois Tigeot if (radeon_crtc->unpin_work) { 393926deccbSFrançois Tigeot DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 394926deccbSFrançois Tigeot r = -EBUSY; 395926deccbSFrançois Tigeot goto unlock_free; 396926deccbSFrançois Tigeot } 397926deccbSFrançois Tigeot radeon_crtc->unpin_work = work; 398926deccbSFrançois Tigeot radeon_crtc->deferred_flip_completion = 0; 399926deccbSFrançois Tigeot lockmgr(&dev->event_lock, LK_RELEASE); 400926deccbSFrançois Tigeot 401926deccbSFrançois Tigeot /* pin the new buffer */ 402926deccbSFrançois Tigeot DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n", 403926deccbSFrançois Tigeot work->old_rbo, rbo); 404926deccbSFrançois Tigeot 405926deccbSFrançois Tigeot r = radeon_bo_reserve(rbo, false); 406926deccbSFrançois Tigeot if (unlikely(r != 0)) { 407926deccbSFrançois Tigeot DRM_ERROR("failed to reserve new rbo buffer before flip\n"); 408926deccbSFrançois Tigeot goto pflip_cleanup; 409926deccbSFrançois Tigeot } 410926deccbSFrançois Tigeot /* Only 27 bit offset for legacy CRTC */ 411926deccbSFrançois Tigeot r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 412926deccbSFrançois Tigeot ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base); 413926deccbSFrançois Tigeot if (unlikely(r != 0)) { 414926deccbSFrançois Tigeot radeon_bo_unreserve(rbo); 415926deccbSFrançois Tigeot r = -EINVAL; 416926deccbSFrançois Tigeot DRM_ERROR("failed to pin new rbo buffer before flip\n"); 417926deccbSFrançois Tigeot goto pflip_cleanup; 418926deccbSFrançois Tigeot } 419926deccbSFrançois Tigeot radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 420926deccbSFrançois Tigeot radeon_bo_unreserve(rbo); 421926deccbSFrançois Tigeot 422926deccbSFrançois Tigeot if (!ASIC_IS_AVIVO(rdev)) { 423926deccbSFrançois Tigeot /* crtc offset is from display base addr not FB location */ 424926deccbSFrançois Tigeot base -= radeon_crtc->legacy_display_base_addr; 425926deccbSFrançois Tigeot pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8); 426926deccbSFrançois Tigeot 427926deccbSFrançois Tigeot if (tiling_flags & RADEON_TILING_MACRO) { 428926deccbSFrançois Tigeot if (ASIC_IS_R300(rdev)) { 429926deccbSFrançois Tigeot base &= ~0x7ff; 430926deccbSFrançois Tigeot } else { 431926deccbSFrançois Tigeot int byteshift = fb->bits_per_pixel >> 4; 432926deccbSFrançois Tigeot int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11; 433926deccbSFrançois Tigeot base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8); 434926deccbSFrançois Tigeot } 435926deccbSFrançois Tigeot } else { 436926deccbSFrançois Tigeot int offset = crtc->y * pitch_pixels + crtc->x; 437926deccbSFrançois Tigeot switch (fb->bits_per_pixel) { 438926deccbSFrançois Tigeot case 8: 439926deccbSFrançois Tigeot default: 440926deccbSFrançois Tigeot offset *= 1; 441926deccbSFrançois Tigeot break; 442926deccbSFrançois Tigeot case 15: 443926deccbSFrançois Tigeot case 16: 444926deccbSFrançois Tigeot offset *= 2; 445926deccbSFrançois Tigeot break; 446926deccbSFrançois Tigeot case 24: 447926deccbSFrançois Tigeot offset *= 3; 448926deccbSFrançois Tigeot break; 449926deccbSFrançois Tigeot case 32: 450926deccbSFrançois Tigeot offset *= 4; 451926deccbSFrançois Tigeot break; 452926deccbSFrançois Tigeot } 453926deccbSFrançois Tigeot base += offset; 454926deccbSFrançois Tigeot } 455926deccbSFrançois Tigeot base &= ~7; 456926deccbSFrançois Tigeot } 457926deccbSFrançois Tigeot 458926deccbSFrançois Tigeot lockmgr(&dev->event_lock, LK_EXCLUSIVE); 459926deccbSFrançois Tigeot work->new_crtc_base = base; 460926deccbSFrançois Tigeot lockmgr(&dev->event_lock, LK_RELEASE); 461926deccbSFrançois Tigeot 462926deccbSFrançois Tigeot /* update crtc fb */ 463926deccbSFrançois Tigeot crtc->fb = fb; 464926deccbSFrançois Tigeot 465926deccbSFrançois Tigeot r = drm_vblank_get(dev, radeon_crtc->crtc_id); 466926deccbSFrançois Tigeot if (r) { 467926deccbSFrançois Tigeot DRM_ERROR("failed to get vblank before flip\n"); 468926deccbSFrançois Tigeot goto pflip_cleanup1; 469926deccbSFrançois Tigeot } 470926deccbSFrançois Tigeot 471926deccbSFrançois Tigeot /* set the proper interrupt */ 472926deccbSFrançois Tigeot radeon_pre_page_flip(rdev, radeon_crtc->crtc_id); 473926deccbSFrançois Tigeot 474926deccbSFrançois Tigeot return 0; 475926deccbSFrançois Tigeot 476926deccbSFrançois Tigeot pflip_cleanup1: 477926deccbSFrançois Tigeot if (unlikely(radeon_bo_reserve(rbo, false) != 0)) { 478926deccbSFrançois Tigeot DRM_ERROR("failed to reserve new rbo in error path\n"); 479926deccbSFrançois Tigeot goto pflip_cleanup; 480926deccbSFrançois Tigeot } 481926deccbSFrançois Tigeot if (unlikely(radeon_bo_unpin(rbo) != 0)) { 482926deccbSFrançois Tigeot DRM_ERROR("failed to unpin new rbo in error path\n"); 483926deccbSFrançois Tigeot } 484926deccbSFrançois Tigeot radeon_bo_unreserve(rbo); 485926deccbSFrançois Tigeot 486926deccbSFrançois Tigeot pflip_cleanup: 487926deccbSFrançois Tigeot lockmgr(&dev->event_lock, LK_EXCLUSIVE); 488926deccbSFrançois Tigeot radeon_crtc->unpin_work = NULL; 489926deccbSFrançois Tigeot unlock_free: 490926deccbSFrançois Tigeot lockmgr(&dev->event_lock, LK_RELEASE); 491926deccbSFrançois Tigeot drm_gem_object_unreference_unlocked(old_radeon_fb->obj); 492926deccbSFrançois Tigeot radeon_fence_unref(&work->fence); 4935a3b77d5SFrançois Tigeot drm_free(work, M_DRM); 494926deccbSFrançois Tigeot 495926deccbSFrançois Tigeot return r; 496926deccbSFrançois Tigeot } 497926deccbSFrançois Tigeot 498926deccbSFrançois Tigeot static const struct drm_crtc_funcs radeon_crtc_funcs = { 499926deccbSFrançois Tigeot .cursor_set = radeon_crtc_cursor_set, 500926deccbSFrançois Tigeot .cursor_move = radeon_crtc_cursor_move, 501926deccbSFrançois Tigeot .gamma_set = radeon_crtc_gamma_set, 502926deccbSFrançois Tigeot .set_config = drm_crtc_helper_set_config, 503926deccbSFrançois Tigeot .destroy = radeon_crtc_destroy, 504926deccbSFrançois Tigeot .page_flip = radeon_crtc_page_flip, 505926deccbSFrançois Tigeot }; 506926deccbSFrançois Tigeot 507926deccbSFrançois Tigeot static void radeon_crtc_init(struct drm_device *dev, int index) 508926deccbSFrançois Tigeot { 509926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 510926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc; 511926deccbSFrançois Tigeot int i; 512926deccbSFrançois Tigeot 513926deccbSFrançois Tigeot radeon_crtc = kmalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), 5145a3b77d5SFrançois Tigeot M_DRM, M_WAITOK | M_ZERO); 515926deccbSFrançois Tigeot if (radeon_crtc == NULL) 516926deccbSFrançois Tigeot return; 517926deccbSFrançois Tigeot 518926deccbSFrançois Tigeot drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); 519926deccbSFrançois Tigeot 520926deccbSFrançois Tigeot drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); 521926deccbSFrançois Tigeot radeon_crtc->crtc_id = index; 522926deccbSFrançois Tigeot rdev->mode_info.crtcs[index] = radeon_crtc; 523926deccbSFrançois Tigeot 524926deccbSFrançois Tigeot #if 0 525926deccbSFrançois Tigeot radeon_crtc->mode_set.crtc = &radeon_crtc->base; 526926deccbSFrançois Tigeot radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); 527926deccbSFrançois Tigeot radeon_crtc->mode_set.num_connectors = 0; 528926deccbSFrançois Tigeot #endif 529926deccbSFrançois Tigeot 530926deccbSFrançois Tigeot for (i = 0; i < 256; i++) { 531926deccbSFrançois Tigeot radeon_crtc->lut_r[i] = i << 2; 532926deccbSFrançois Tigeot radeon_crtc->lut_g[i] = i << 2; 533926deccbSFrançois Tigeot radeon_crtc->lut_b[i] = i << 2; 534926deccbSFrançois Tigeot } 535926deccbSFrançois Tigeot 536926deccbSFrançois Tigeot if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) 537926deccbSFrançois Tigeot radeon_atombios_init_crtc(dev, radeon_crtc); 538926deccbSFrançois Tigeot else 539926deccbSFrançois Tigeot radeon_legacy_init_crtc(dev, radeon_crtc); 540926deccbSFrançois Tigeot } 541926deccbSFrançois Tigeot 542926deccbSFrançois Tigeot static const char *encoder_names[37] = { 543926deccbSFrançois Tigeot "NONE", 544926deccbSFrançois Tigeot "INTERNAL_LVDS", 545926deccbSFrançois Tigeot "INTERNAL_TMDS1", 546926deccbSFrançois Tigeot "INTERNAL_TMDS2", 547926deccbSFrançois Tigeot "INTERNAL_DAC1", 548926deccbSFrançois Tigeot "INTERNAL_DAC2", 549926deccbSFrançois Tigeot "INTERNAL_SDVOA", 550926deccbSFrançois Tigeot "INTERNAL_SDVOB", 551926deccbSFrançois Tigeot "SI170B", 552926deccbSFrançois Tigeot "CH7303", 553926deccbSFrançois Tigeot "CH7301", 554926deccbSFrançois Tigeot "INTERNAL_DVO1", 555926deccbSFrançois Tigeot "EXTERNAL_SDVOA", 556926deccbSFrançois Tigeot "EXTERNAL_SDVOB", 557926deccbSFrançois Tigeot "TITFP513", 558926deccbSFrançois Tigeot "INTERNAL_LVTM1", 559926deccbSFrançois Tigeot "VT1623", 560926deccbSFrançois Tigeot "HDMI_SI1930", 561926deccbSFrançois Tigeot "HDMI_INTERNAL", 562926deccbSFrançois Tigeot "INTERNAL_KLDSCP_TMDS1", 563926deccbSFrançois Tigeot "INTERNAL_KLDSCP_DVO1", 564926deccbSFrançois Tigeot "INTERNAL_KLDSCP_DAC1", 565926deccbSFrançois Tigeot "INTERNAL_KLDSCP_DAC2", 566926deccbSFrançois Tigeot "SI178", 567926deccbSFrançois Tigeot "MVPU_FPGA", 568926deccbSFrançois Tigeot "INTERNAL_DDI", 569926deccbSFrançois Tigeot "VT1625", 570926deccbSFrançois Tigeot "HDMI_SI1932", 571926deccbSFrançois Tigeot "DP_AN9801", 572926deccbSFrançois Tigeot "DP_DP501", 573926deccbSFrançois Tigeot "INTERNAL_UNIPHY", 574926deccbSFrançois Tigeot "INTERNAL_KLDSCP_LVTMA", 575926deccbSFrançois Tigeot "INTERNAL_UNIPHY1", 576926deccbSFrançois Tigeot "INTERNAL_UNIPHY2", 577926deccbSFrançois Tigeot "NUTMEG", 578926deccbSFrançois Tigeot "TRAVIS", 579926deccbSFrançois Tigeot "INTERNAL_VCE" 580926deccbSFrançois Tigeot }; 581926deccbSFrançois Tigeot 582926deccbSFrançois Tigeot static const char *hpd_names[6] = { 583926deccbSFrançois Tigeot "HPD1", 584926deccbSFrançois Tigeot "HPD2", 585926deccbSFrançois Tigeot "HPD3", 586926deccbSFrançois Tigeot "HPD4", 587926deccbSFrançois Tigeot "HPD5", 588926deccbSFrançois Tigeot "HPD6", 589926deccbSFrançois Tigeot }; 590926deccbSFrançois Tigeot 591926deccbSFrançois Tigeot static void radeon_print_display_setup(struct drm_device *dev) 592926deccbSFrançois Tigeot { 593926deccbSFrançois Tigeot struct drm_connector *connector; 594926deccbSFrançois Tigeot struct radeon_connector *radeon_connector; 595926deccbSFrançois Tigeot struct drm_encoder *encoder; 596926deccbSFrançois Tigeot struct radeon_encoder *radeon_encoder; 597926deccbSFrançois Tigeot uint32_t devices; 598926deccbSFrançois Tigeot int i = 0; 599926deccbSFrançois Tigeot 600926deccbSFrançois Tigeot DRM_INFO("Radeon Display Connectors\n"); 601926deccbSFrançois Tigeot list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 602926deccbSFrançois Tigeot radeon_connector = to_radeon_connector(connector); 603926deccbSFrançois Tigeot DRM_INFO("Connector %d:\n", i); 604926deccbSFrançois Tigeot DRM_INFO(" %s\n", drm_get_connector_name(connector)); 605926deccbSFrançois Tigeot if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 606926deccbSFrançois Tigeot DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); 607926deccbSFrançois Tigeot if (radeon_connector->ddc_bus) { 608926deccbSFrançois Tigeot DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 609926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.mask_clk_reg, 610926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.mask_data_reg, 611926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.a_clk_reg, 612926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.a_data_reg, 613926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.en_clk_reg, 614926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.en_data_reg, 615926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.y_clk_reg, 616926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.y_data_reg); 617926deccbSFrançois Tigeot if (radeon_connector->router.ddc_valid) 618926deccbSFrançois Tigeot DRM_INFO(" DDC Router 0x%x/0x%x\n", 619926deccbSFrançois Tigeot radeon_connector->router.ddc_mux_control_pin, 620926deccbSFrançois Tigeot radeon_connector->router.ddc_mux_state); 621926deccbSFrançois Tigeot if (radeon_connector->router.cd_valid) 622926deccbSFrançois Tigeot DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 623926deccbSFrançois Tigeot radeon_connector->router.cd_mux_control_pin, 624926deccbSFrançois Tigeot radeon_connector->router.cd_mux_state); 625926deccbSFrançois Tigeot } else { 626926deccbSFrançois Tigeot if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 627926deccbSFrançois Tigeot connector->connector_type == DRM_MODE_CONNECTOR_DVII || 628926deccbSFrançois Tigeot connector->connector_type == DRM_MODE_CONNECTOR_DVID || 629926deccbSFrançois Tigeot connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 630926deccbSFrançois Tigeot connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 631926deccbSFrançois Tigeot connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 632926deccbSFrançois Tigeot DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 633926deccbSFrançois Tigeot } 634926deccbSFrançois Tigeot DRM_INFO(" Encoders:\n"); 635926deccbSFrançois Tigeot list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 636926deccbSFrançois Tigeot radeon_encoder = to_radeon_encoder(encoder); 637926deccbSFrançois Tigeot devices = radeon_encoder->devices & radeon_connector->devices; 638926deccbSFrançois Tigeot if (devices) { 639926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_CRT1_SUPPORT) 640926deccbSFrançois Tigeot DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); 641926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_CRT2_SUPPORT) 642926deccbSFrançois Tigeot DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); 643926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_LCD1_SUPPORT) 644926deccbSFrançois Tigeot DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); 645926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP1_SUPPORT) 646926deccbSFrançois Tigeot DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); 647926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP2_SUPPORT) 648926deccbSFrançois Tigeot DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); 649926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP3_SUPPORT) 650926deccbSFrançois Tigeot DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); 651926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP4_SUPPORT) 652926deccbSFrançois Tigeot DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); 653926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP5_SUPPORT) 654926deccbSFrançois Tigeot DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); 655926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP6_SUPPORT) 656926deccbSFrançois Tigeot DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); 657926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_TV1_SUPPORT) 658926deccbSFrançois Tigeot DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); 659926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_CV_SUPPORT) 660926deccbSFrançois Tigeot DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); 661926deccbSFrançois Tigeot } 662926deccbSFrançois Tigeot } 663926deccbSFrançois Tigeot i++; 664926deccbSFrançois Tigeot } 665926deccbSFrançois Tigeot } 666926deccbSFrançois Tigeot 667926deccbSFrançois Tigeot static bool radeon_setup_enc_conn(struct drm_device *dev) 668926deccbSFrançois Tigeot { 669926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 670926deccbSFrançois Tigeot bool ret = false; 671926deccbSFrançois Tigeot 672926deccbSFrançois Tigeot if (rdev->bios) { 673926deccbSFrançois Tigeot if (rdev->is_atom_bios) { 674926deccbSFrançois Tigeot ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); 675926deccbSFrançois Tigeot if (ret == false) 676926deccbSFrançois Tigeot ret = radeon_get_atom_connector_info_from_object_table(dev); 677926deccbSFrançois Tigeot } else { 678926deccbSFrançois Tigeot ret = radeon_get_legacy_connector_info_from_bios(dev); 679926deccbSFrançois Tigeot if (ret == false) 680926deccbSFrançois Tigeot ret = radeon_get_legacy_connector_info_from_table(dev); 681926deccbSFrançois Tigeot } 682926deccbSFrançois Tigeot } else { 683926deccbSFrançois Tigeot if (!ASIC_IS_AVIVO(rdev)) 684926deccbSFrançois Tigeot ret = radeon_get_legacy_connector_info_from_table(dev); 685926deccbSFrançois Tigeot } 686926deccbSFrançois Tigeot if (ret) { 687926deccbSFrançois Tigeot radeon_setup_encoder_clones(dev); 688926deccbSFrançois Tigeot radeon_print_display_setup(dev); 689926deccbSFrançois Tigeot } 690926deccbSFrançois Tigeot 691926deccbSFrançois Tigeot return ret; 692926deccbSFrançois Tigeot } 693926deccbSFrançois Tigeot 694926deccbSFrançois Tigeot int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) 695926deccbSFrançois Tigeot { 696926deccbSFrançois Tigeot struct drm_device *dev = radeon_connector->base.dev; 697926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 698926deccbSFrançois Tigeot int ret = 0; 699926deccbSFrançois Tigeot 700926deccbSFrançois Tigeot /* on hw with routers, select right port */ 701926deccbSFrançois Tigeot if (radeon_connector->router.ddc_valid) 702926deccbSFrançois Tigeot radeon_router_select_ddc_port(radeon_connector); 703926deccbSFrançois Tigeot 704926deccbSFrançois Tigeot if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) != 705926deccbSFrançois Tigeot ENCODER_OBJECT_ID_NONE) { 706926deccbSFrançois Tigeot struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 707926deccbSFrançois Tigeot 708926deccbSFrançois Tigeot if (dig->dp_i2c_bus) 709926deccbSFrançois Tigeot radeon_connector->edid = drm_get_edid(&radeon_connector->base, 710926deccbSFrançois Tigeot dig->dp_i2c_bus->adapter); 711926deccbSFrançois Tigeot } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 712926deccbSFrançois Tigeot (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) { 713926deccbSFrançois Tigeot struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 714926deccbSFrançois Tigeot 715926deccbSFrançois Tigeot if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 716926deccbSFrançois Tigeot dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus) 717926deccbSFrançois Tigeot radeon_connector->edid = drm_get_edid(&radeon_connector->base, 718926deccbSFrançois Tigeot dig->dp_i2c_bus->adapter); 719926deccbSFrançois Tigeot else if (radeon_connector->ddc_bus && !radeon_connector->edid) 720926deccbSFrançois Tigeot radeon_connector->edid = drm_get_edid(&radeon_connector->base, 721926deccbSFrançois Tigeot radeon_connector->ddc_bus->adapter); 722926deccbSFrançois Tigeot } else { 723926deccbSFrançois Tigeot if (radeon_connector->ddc_bus && !radeon_connector->edid) 724926deccbSFrançois Tigeot radeon_connector->edid = drm_get_edid(&radeon_connector->base, 725926deccbSFrançois Tigeot radeon_connector->ddc_bus->adapter); 726926deccbSFrançois Tigeot } 727926deccbSFrançois Tigeot 728926deccbSFrançois Tigeot if (!radeon_connector->edid) { 729926deccbSFrançois Tigeot if (rdev->is_atom_bios) { 730926deccbSFrançois Tigeot /* some laptops provide a hardcoded edid in rom for LCDs */ 731926deccbSFrançois Tigeot if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) || 732926deccbSFrançois Tigeot (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP))) 733926deccbSFrançois Tigeot radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); 734926deccbSFrançois Tigeot } else 735926deccbSFrançois Tigeot /* some servers provide a hardcoded edid in rom for KVMs */ 736926deccbSFrançois Tigeot radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); 737926deccbSFrançois Tigeot } 738926deccbSFrançois Tigeot if (radeon_connector->edid) { 739926deccbSFrançois Tigeot drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); 740926deccbSFrançois Tigeot ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); 741926deccbSFrançois Tigeot return ret; 742926deccbSFrançois Tigeot } 743926deccbSFrançois Tigeot drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); 744926deccbSFrançois Tigeot return 0; 745926deccbSFrançois Tigeot } 746926deccbSFrançois Tigeot 747926deccbSFrançois Tigeot /* avivo */ 748926deccbSFrançois Tigeot static void avivo_get_fb_div(struct radeon_pll *pll, 749926deccbSFrançois Tigeot u32 target_clock, 750926deccbSFrançois Tigeot u32 post_div, 751926deccbSFrançois Tigeot u32 ref_div, 752926deccbSFrançois Tigeot u32 *fb_div, 753926deccbSFrançois Tigeot u32 *frac_fb_div) 754926deccbSFrançois Tigeot { 755926deccbSFrançois Tigeot u32 tmp = post_div * ref_div; 756926deccbSFrançois Tigeot 757926deccbSFrançois Tigeot tmp *= target_clock; 758926deccbSFrançois Tigeot *fb_div = tmp / pll->reference_freq; 759926deccbSFrançois Tigeot *frac_fb_div = tmp % pll->reference_freq; 760926deccbSFrançois Tigeot 761926deccbSFrançois Tigeot if (*fb_div > pll->max_feedback_div) 762926deccbSFrançois Tigeot *fb_div = pll->max_feedback_div; 763926deccbSFrançois Tigeot else if (*fb_div < pll->min_feedback_div) 764926deccbSFrançois Tigeot *fb_div = pll->min_feedback_div; 765926deccbSFrançois Tigeot } 766926deccbSFrançois Tigeot 767926deccbSFrançois Tigeot static u32 avivo_get_post_div(struct radeon_pll *pll, 768926deccbSFrançois Tigeot u32 target_clock) 769926deccbSFrançois Tigeot { 770926deccbSFrançois Tigeot u32 vco, post_div, tmp; 771926deccbSFrançois Tigeot 772926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_POST_DIV) 773926deccbSFrançois Tigeot return pll->post_div; 774926deccbSFrançois Tigeot 775926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) { 776926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_IS_LCD) 777926deccbSFrançois Tigeot vco = pll->lcd_pll_out_min; 778926deccbSFrançois Tigeot else 779926deccbSFrançois Tigeot vco = pll->pll_out_min; 780926deccbSFrançois Tigeot } else { 781926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_IS_LCD) 782926deccbSFrançois Tigeot vco = pll->lcd_pll_out_max; 783926deccbSFrançois Tigeot else 784926deccbSFrançois Tigeot vco = pll->pll_out_max; 785926deccbSFrançois Tigeot } 786926deccbSFrançois Tigeot 787926deccbSFrançois Tigeot post_div = vco / target_clock; 788926deccbSFrançois Tigeot tmp = vco % target_clock; 789926deccbSFrançois Tigeot 790926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) { 791926deccbSFrançois Tigeot if (tmp) 792926deccbSFrançois Tigeot post_div++; 793926deccbSFrançois Tigeot } else { 794926deccbSFrançois Tigeot if (!tmp) 795926deccbSFrançois Tigeot post_div--; 796926deccbSFrançois Tigeot } 797926deccbSFrançois Tigeot 798926deccbSFrançois Tigeot if (post_div > pll->max_post_div) 799926deccbSFrançois Tigeot post_div = pll->max_post_div; 800926deccbSFrançois Tigeot else if (post_div < pll->min_post_div) 801926deccbSFrançois Tigeot post_div = pll->min_post_div; 802926deccbSFrançois Tigeot 803926deccbSFrançois Tigeot return post_div; 804926deccbSFrançois Tigeot } 805926deccbSFrançois Tigeot 806926deccbSFrançois Tigeot #define MAX_TOLERANCE 10 807926deccbSFrançois Tigeot 808926deccbSFrançois Tigeot void radeon_compute_pll_avivo(struct radeon_pll *pll, 809926deccbSFrançois Tigeot u32 freq, 810926deccbSFrançois Tigeot u32 *dot_clock_p, 811926deccbSFrançois Tigeot u32 *fb_div_p, 812926deccbSFrançois Tigeot u32 *frac_fb_div_p, 813926deccbSFrançois Tigeot u32 *ref_div_p, 814926deccbSFrançois Tigeot u32 *post_div_p) 815926deccbSFrançois Tigeot { 816926deccbSFrançois Tigeot u32 target_clock = freq / 10; 817926deccbSFrançois Tigeot u32 post_div = avivo_get_post_div(pll, target_clock); 818926deccbSFrançois Tigeot u32 ref_div = pll->min_ref_div; 819926deccbSFrançois Tigeot u32 fb_div = 0, frac_fb_div = 0, tmp; 820926deccbSFrançois Tigeot 821926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_REF_DIV) 822926deccbSFrançois Tigeot ref_div = pll->reference_div; 823926deccbSFrançois Tigeot 824926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 825926deccbSFrançois Tigeot avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div); 826926deccbSFrançois Tigeot frac_fb_div = (100 * frac_fb_div) / pll->reference_freq; 827926deccbSFrançois Tigeot if (frac_fb_div >= 5) { 828926deccbSFrançois Tigeot frac_fb_div -= 5; 829926deccbSFrançois Tigeot frac_fb_div = frac_fb_div / 10; 830926deccbSFrançois Tigeot frac_fb_div++; 831926deccbSFrançois Tigeot } 832926deccbSFrançois Tigeot if (frac_fb_div >= 10) { 833926deccbSFrançois Tigeot fb_div++; 834926deccbSFrançois Tigeot frac_fb_div = 0; 835926deccbSFrançois Tigeot } 836926deccbSFrançois Tigeot } else { 837926deccbSFrançois Tigeot while (ref_div <= pll->max_ref_div) { 838926deccbSFrançois Tigeot avivo_get_fb_div(pll, target_clock, post_div, ref_div, 839926deccbSFrançois Tigeot &fb_div, &frac_fb_div); 840926deccbSFrançois Tigeot if (frac_fb_div >= (pll->reference_freq / 2)) 841926deccbSFrançois Tigeot fb_div++; 842926deccbSFrançois Tigeot frac_fb_div = 0; 843926deccbSFrançois Tigeot tmp = (pll->reference_freq * fb_div) / (post_div * ref_div); 844926deccbSFrançois Tigeot tmp = (tmp * 10000) / target_clock; 845926deccbSFrançois Tigeot 846926deccbSFrançois Tigeot if (tmp > (10000 + MAX_TOLERANCE)) 847926deccbSFrançois Tigeot ref_div++; 848926deccbSFrançois Tigeot else if (tmp >= (10000 - MAX_TOLERANCE)) 849926deccbSFrançois Tigeot break; 850926deccbSFrançois Tigeot else 851926deccbSFrançois Tigeot ref_div++; 852926deccbSFrançois Tigeot } 853926deccbSFrançois Tigeot } 854926deccbSFrançois Tigeot 855926deccbSFrançois Tigeot *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) / 856926deccbSFrançois Tigeot (ref_div * post_div * 10); 857926deccbSFrançois Tigeot *fb_div_p = fb_div; 858926deccbSFrançois Tigeot *frac_fb_div_p = frac_fb_div; 859926deccbSFrançois Tigeot *ref_div_p = ref_div; 860926deccbSFrançois Tigeot *post_div_p = post_div; 861926deccbSFrançois Tigeot DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n", 862926deccbSFrançois Tigeot *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div); 863926deccbSFrançois Tigeot } 864926deccbSFrançois Tigeot 865926deccbSFrançois Tigeot /* pre-avivo */ 866926deccbSFrançois Tigeot static inline uint32_t radeon_div(uint64_t n, uint32_t d) 867926deccbSFrançois Tigeot { 868926deccbSFrançois Tigeot uint64_t mod; 869926deccbSFrançois Tigeot 870926deccbSFrançois Tigeot n += d / 2; 871926deccbSFrançois Tigeot 872926deccbSFrançois Tigeot mod = do_div(n, d); 873926deccbSFrançois Tigeot return n; 874926deccbSFrançois Tigeot } 875926deccbSFrançois Tigeot 876926deccbSFrançois Tigeot void radeon_compute_pll_legacy(struct radeon_pll *pll, 877926deccbSFrançois Tigeot uint64_t freq, 878926deccbSFrançois Tigeot uint32_t *dot_clock_p, 879926deccbSFrançois Tigeot uint32_t *fb_div_p, 880926deccbSFrançois Tigeot uint32_t *frac_fb_div_p, 881926deccbSFrançois Tigeot uint32_t *ref_div_p, 882926deccbSFrançois Tigeot uint32_t *post_div_p) 883926deccbSFrançois Tigeot { 884926deccbSFrançois Tigeot uint32_t min_ref_div = pll->min_ref_div; 885926deccbSFrançois Tigeot uint32_t max_ref_div = pll->max_ref_div; 886926deccbSFrançois Tigeot uint32_t min_post_div = pll->min_post_div; 887926deccbSFrançois Tigeot uint32_t max_post_div = pll->max_post_div; 888926deccbSFrançois Tigeot uint32_t min_fractional_feed_div = 0; 889926deccbSFrançois Tigeot uint32_t max_fractional_feed_div = 0; 890926deccbSFrançois Tigeot uint32_t best_vco = pll->best_vco; 891926deccbSFrançois Tigeot uint32_t best_post_div = 1; 892926deccbSFrançois Tigeot uint32_t best_ref_div = 1; 893926deccbSFrançois Tigeot uint32_t best_feedback_div = 1; 894926deccbSFrançois Tigeot uint32_t best_frac_feedback_div = 0; 895926deccbSFrançois Tigeot uint32_t best_freq = -1; 896926deccbSFrançois Tigeot uint32_t best_error = 0xffffffff; 897926deccbSFrançois Tigeot uint32_t best_vco_diff = 1; 898926deccbSFrançois Tigeot uint32_t post_div; 899926deccbSFrançois Tigeot u32 pll_out_min, pll_out_max; 900926deccbSFrançois Tigeot 901926deccbSFrançois Tigeot DRM_DEBUG_KMS("PLL freq %ju %u %u\n", (uintmax_t)freq, pll->min_ref_div, pll->max_ref_div); 902926deccbSFrançois Tigeot freq = freq * 1000; 903926deccbSFrançois Tigeot 904926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_IS_LCD) { 905926deccbSFrançois Tigeot pll_out_min = pll->lcd_pll_out_min; 906926deccbSFrançois Tigeot pll_out_max = pll->lcd_pll_out_max; 907926deccbSFrançois Tigeot } else { 908926deccbSFrançois Tigeot pll_out_min = pll->pll_out_min; 909926deccbSFrançois Tigeot pll_out_max = pll->pll_out_max; 910926deccbSFrançois Tigeot } 911926deccbSFrançois Tigeot 912926deccbSFrançois Tigeot if (pll_out_min > 64800) 913926deccbSFrançois Tigeot pll_out_min = 64800; 914926deccbSFrançois Tigeot 915926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_REF_DIV) 916926deccbSFrançois Tigeot min_ref_div = max_ref_div = pll->reference_div; 917926deccbSFrançois Tigeot else { 918926deccbSFrançois Tigeot while (min_ref_div < max_ref_div-1) { 919926deccbSFrançois Tigeot uint32_t mid = (min_ref_div + max_ref_div) / 2; 920926deccbSFrançois Tigeot uint32_t pll_in = pll->reference_freq / mid; 921926deccbSFrançois Tigeot if (pll_in < pll->pll_in_min) 922926deccbSFrançois Tigeot max_ref_div = mid; 923926deccbSFrançois Tigeot else if (pll_in > pll->pll_in_max) 924926deccbSFrançois Tigeot min_ref_div = mid; 925926deccbSFrançois Tigeot else 926926deccbSFrançois Tigeot break; 927926deccbSFrançois Tigeot } 928926deccbSFrançois Tigeot } 929926deccbSFrançois Tigeot 930926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_POST_DIV) 931926deccbSFrançois Tigeot min_post_div = max_post_div = pll->post_div; 932926deccbSFrançois Tigeot 933926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 934926deccbSFrançois Tigeot min_fractional_feed_div = pll->min_frac_feedback_div; 935926deccbSFrançois Tigeot max_fractional_feed_div = pll->max_frac_feedback_div; 936926deccbSFrançois Tigeot } 937926deccbSFrançois Tigeot 938926deccbSFrançois Tigeot for (post_div = max_post_div; post_div >= min_post_div; --post_div) { 939926deccbSFrançois Tigeot uint32_t ref_div; 940926deccbSFrançois Tigeot 941926deccbSFrançois Tigeot if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 942926deccbSFrançois Tigeot continue; 943926deccbSFrançois Tigeot 944926deccbSFrançois Tigeot /* legacy radeons only have a few post_divs */ 945926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_LEGACY) { 946926deccbSFrançois Tigeot if ((post_div == 5) || 947926deccbSFrançois Tigeot (post_div == 7) || 948926deccbSFrançois Tigeot (post_div == 9) || 949926deccbSFrançois Tigeot (post_div == 10) || 950926deccbSFrançois Tigeot (post_div == 11) || 951926deccbSFrançois Tigeot (post_div == 13) || 952926deccbSFrançois Tigeot (post_div == 14) || 953926deccbSFrançois Tigeot (post_div == 15)) 954926deccbSFrançois Tigeot continue; 955926deccbSFrançois Tigeot } 956926deccbSFrançois Tigeot 957926deccbSFrançois Tigeot for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { 958926deccbSFrançois Tigeot uint32_t feedback_div, current_freq = 0, error, vco_diff; 959926deccbSFrançois Tigeot uint32_t pll_in = pll->reference_freq / ref_div; 960926deccbSFrançois Tigeot uint32_t min_feed_div = pll->min_feedback_div; 961926deccbSFrançois Tigeot uint32_t max_feed_div = pll->max_feedback_div + 1; 962926deccbSFrançois Tigeot 963926deccbSFrançois Tigeot if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) 964926deccbSFrançois Tigeot continue; 965926deccbSFrançois Tigeot 966926deccbSFrançois Tigeot while (min_feed_div < max_feed_div) { 967926deccbSFrançois Tigeot uint32_t vco; 968926deccbSFrançois Tigeot uint32_t min_frac_feed_div = min_fractional_feed_div; 969926deccbSFrançois Tigeot uint32_t max_frac_feed_div = max_fractional_feed_div + 1; 970926deccbSFrançois Tigeot uint32_t frac_feedback_div; 971926deccbSFrançois Tigeot uint64_t tmp; 972926deccbSFrançois Tigeot 973926deccbSFrançois Tigeot feedback_div = (min_feed_div + max_feed_div) / 2; 974926deccbSFrançois Tigeot 975926deccbSFrançois Tigeot tmp = (uint64_t)pll->reference_freq * feedback_div; 976926deccbSFrançois Tigeot vco = radeon_div(tmp, ref_div); 977926deccbSFrançois Tigeot 978926deccbSFrançois Tigeot if (vco < pll_out_min) { 979926deccbSFrançois Tigeot min_feed_div = feedback_div + 1; 980926deccbSFrançois Tigeot continue; 981926deccbSFrançois Tigeot } else if (vco > pll_out_max) { 982926deccbSFrançois Tigeot max_feed_div = feedback_div; 983926deccbSFrançois Tigeot continue; 984926deccbSFrançois Tigeot } 985926deccbSFrançois Tigeot 986926deccbSFrançois Tigeot while (min_frac_feed_div < max_frac_feed_div) { 987926deccbSFrançois Tigeot frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; 988926deccbSFrançois Tigeot tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; 989926deccbSFrançois Tigeot tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; 990926deccbSFrançois Tigeot current_freq = radeon_div(tmp, ref_div * post_div); 991926deccbSFrançois Tigeot 992926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 993926deccbSFrançois Tigeot if (freq < current_freq) 994926deccbSFrançois Tigeot error = 0xffffffff; 995926deccbSFrançois Tigeot else 996926deccbSFrançois Tigeot error = freq - current_freq; 997926deccbSFrançois Tigeot } else 998926deccbSFrançois Tigeot error = abs(current_freq - freq); 999926deccbSFrançois Tigeot vco_diff = abs(vco - best_vco); 1000926deccbSFrançois Tigeot 1001926deccbSFrançois Tigeot if ((best_vco == 0 && error < best_error) || 1002926deccbSFrançois Tigeot (best_vco != 0 && 1003926deccbSFrançois Tigeot ((best_error > 100 && error < best_error - 100) || 1004926deccbSFrançois Tigeot (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { 1005926deccbSFrançois Tigeot best_post_div = post_div; 1006926deccbSFrançois Tigeot best_ref_div = ref_div; 1007926deccbSFrançois Tigeot best_feedback_div = feedback_div; 1008926deccbSFrançois Tigeot best_frac_feedback_div = frac_feedback_div; 1009926deccbSFrançois Tigeot best_freq = current_freq; 1010926deccbSFrançois Tigeot best_error = error; 1011926deccbSFrançois Tigeot best_vco_diff = vco_diff; 1012926deccbSFrançois Tigeot } else if (current_freq == freq) { 1013926deccbSFrançois Tigeot if (best_freq == -1) { 1014926deccbSFrançois Tigeot best_post_div = post_div; 1015926deccbSFrançois Tigeot best_ref_div = ref_div; 1016926deccbSFrançois Tigeot best_feedback_div = feedback_div; 1017926deccbSFrançois Tigeot best_frac_feedback_div = frac_feedback_div; 1018926deccbSFrançois Tigeot best_freq = current_freq; 1019926deccbSFrançois Tigeot best_error = error; 1020926deccbSFrançois Tigeot best_vco_diff = vco_diff; 1021926deccbSFrançois Tigeot } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 1022926deccbSFrançois Tigeot ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 1023926deccbSFrançois Tigeot ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 1024926deccbSFrançois Tigeot ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 1025926deccbSFrançois Tigeot ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 1026926deccbSFrançois Tigeot ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 1027926deccbSFrançois Tigeot best_post_div = post_div; 1028926deccbSFrançois Tigeot best_ref_div = ref_div; 1029926deccbSFrançois Tigeot best_feedback_div = feedback_div; 1030926deccbSFrançois Tigeot best_frac_feedback_div = frac_feedback_div; 1031926deccbSFrançois Tigeot best_freq = current_freq; 1032926deccbSFrançois Tigeot best_error = error; 1033926deccbSFrançois Tigeot best_vco_diff = vco_diff; 1034926deccbSFrançois Tigeot } 1035926deccbSFrançois Tigeot } 1036926deccbSFrançois Tigeot if (current_freq < freq) 1037926deccbSFrançois Tigeot min_frac_feed_div = frac_feedback_div + 1; 1038926deccbSFrançois Tigeot else 1039926deccbSFrançois Tigeot max_frac_feed_div = frac_feedback_div; 1040926deccbSFrançois Tigeot } 1041926deccbSFrançois Tigeot if (current_freq < freq) 1042926deccbSFrançois Tigeot min_feed_div = feedback_div + 1; 1043926deccbSFrançois Tigeot else 1044926deccbSFrançois Tigeot max_feed_div = feedback_div; 1045926deccbSFrançois Tigeot } 1046926deccbSFrançois Tigeot } 1047926deccbSFrançois Tigeot } 1048926deccbSFrançois Tigeot 1049926deccbSFrançois Tigeot *dot_clock_p = best_freq / 10000; 1050926deccbSFrançois Tigeot *fb_div_p = best_feedback_div; 1051926deccbSFrançois Tigeot *frac_fb_div_p = best_frac_feedback_div; 1052926deccbSFrançois Tigeot *ref_div_p = best_ref_div; 1053926deccbSFrançois Tigeot *post_div_p = best_post_div; 1054926deccbSFrançois Tigeot DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1055926deccbSFrançois Tigeot (long long)freq, 1056926deccbSFrançois Tigeot best_freq / 1000, best_feedback_div, best_frac_feedback_div, 1057926deccbSFrançois Tigeot best_ref_div, best_post_div); 1058926deccbSFrançois Tigeot 1059926deccbSFrançois Tigeot } 1060926deccbSFrançois Tigeot 1061926deccbSFrançois Tigeot static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) 1062926deccbSFrançois Tigeot { 1063926deccbSFrançois Tigeot struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1064926deccbSFrançois Tigeot 1065926deccbSFrançois Tigeot if (radeon_fb->obj) { 1066926deccbSFrançois Tigeot drm_gem_object_unreference_unlocked(radeon_fb->obj); 1067926deccbSFrançois Tigeot } 1068926deccbSFrançois Tigeot drm_framebuffer_cleanup(fb); 10695a3b77d5SFrançois Tigeot drm_free(radeon_fb, M_DRM); 1070926deccbSFrançois Tigeot } 1071926deccbSFrançois Tigeot 1072926deccbSFrançois Tigeot static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, 1073926deccbSFrançois Tigeot struct drm_file *file_priv, 1074926deccbSFrançois Tigeot unsigned int *handle) 1075926deccbSFrançois Tigeot { 1076926deccbSFrançois Tigeot struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1077926deccbSFrançois Tigeot 1078926deccbSFrançois Tigeot return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); 1079926deccbSFrançois Tigeot } 1080926deccbSFrançois Tigeot 1081926deccbSFrançois Tigeot static const struct drm_framebuffer_funcs radeon_fb_funcs = { 1082926deccbSFrançois Tigeot .destroy = radeon_user_framebuffer_destroy, 1083926deccbSFrançois Tigeot .create_handle = radeon_user_framebuffer_create_handle, 1084926deccbSFrançois Tigeot }; 1085926deccbSFrançois Tigeot 1086926deccbSFrançois Tigeot int 1087926deccbSFrançois Tigeot radeon_framebuffer_init(struct drm_device *dev, 1088926deccbSFrançois Tigeot struct radeon_framebuffer *rfb, 1089926deccbSFrançois Tigeot struct drm_mode_fb_cmd2 *mode_cmd, 1090926deccbSFrançois Tigeot struct drm_gem_object *obj) 1091926deccbSFrançois Tigeot { 1092926deccbSFrançois Tigeot int ret; 1093926deccbSFrançois Tigeot rfb->obj = obj; 1094b403bed8SMichael Neumann drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); 1095926deccbSFrançois Tigeot ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); 1096926deccbSFrançois Tigeot if (ret) { 1097926deccbSFrançois Tigeot rfb->obj = NULL; 1098926deccbSFrançois Tigeot return ret; 1099926deccbSFrançois Tigeot } 1100926deccbSFrançois Tigeot return 0; 1101926deccbSFrançois Tigeot } 1102926deccbSFrançois Tigeot 110360fc7eecSFrançois Tigeot static struct drm_framebuffer * 1104926deccbSFrançois Tigeot radeon_user_framebuffer_create(struct drm_device *dev, 1105926deccbSFrançois Tigeot struct drm_file *file_priv, 110660fc7eecSFrançois Tigeot struct drm_mode_fb_cmd2 *mode_cmd) 1107926deccbSFrançois Tigeot { 1108926deccbSFrançois Tigeot struct drm_gem_object *obj; 1109926deccbSFrançois Tigeot struct radeon_framebuffer *radeon_fb; 1110926deccbSFrançois Tigeot int ret; 1111926deccbSFrançois Tigeot 1112926deccbSFrançois Tigeot obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]); 1113926deccbSFrançois Tigeot if (obj == NULL) { 11146df74fa7SFrançois Tigeot dev_err(dev->dev, "No GEM object associated to handle 0x%08X, " 1115926deccbSFrançois Tigeot "can't create framebuffer\n", mode_cmd->handles[0]); 111660fc7eecSFrançois Tigeot return ERR_PTR(-ENOENT); 1117926deccbSFrançois Tigeot } 1118926deccbSFrançois Tigeot 11195a3b77d5SFrançois Tigeot radeon_fb = kmalloc(sizeof(*radeon_fb), M_DRM, 1120926deccbSFrançois Tigeot M_WAITOK | M_ZERO); 1121926deccbSFrançois Tigeot if (radeon_fb == NULL) { 1122926deccbSFrançois Tigeot drm_gem_object_unreference_unlocked(obj); 112360fc7eecSFrançois Tigeot return ERR_PTR(-ENOMEM); 1124926deccbSFrançois Tigeot } 1125926deccbSFrançois Tigeot 1126926deccbSFrançois Tigeot ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj); 1127926deccbSFrançois Tigeot if (ret) { 1128158486a6SFrançois Tigeot kfree(radeon_fb); 1129926deccbSFrançois Tigeot drm_gem_object_unreference_unlocked(obj); 113060fc7eecSFrançois Tigeot return ERR_PTR(ret); 1131926deccbSFrançois Tigeot } 1132926deccbSFrançois Tigeot 113360fc7eecSFrançois Tigeot return &radeon_fb->base; 1134926deccbSFrançois Tigeot } 1135926deccbSFrançois Tigeot 1136926deccbSFrançois Tigeot static void radeon_output_poll_changed(struct drm_device *dev) 1137926deccbSFrançois Tigeot { 1138926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 1139926deccbSFrançois Tigeot radeon_fb_output_poll_changed(rdev); 1140926deccbSFrançois Tigeot } 1141926deccbSFrançois Tigeot 1142926deccbSFrançois Tigeot static const struct drm_mode_config_funcs radeon_mode_funcs = { 1143926deccbSFrançois Tigeot .fb_create = radeon_user_framebuffer_create, 1144926deccbSFrançois Tigeot .output_poll_changed = radeon_output_poll_changed 1145926deccbSFrançois Tigeot }; 1146926deccbSFrançois Tigeot 1147926deccbSFrançois Tigeot static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = 1148926deccbSFrançois Tigeot { { 0, "driver" }, 1149926deccbSFrançois Tigeot { 1, "bios" }, 1150926deccbSFrançois Tigeot }; 1151926deccbSFrançois Tigeot 1152926deccbSFrançois Tigeot static struct drm_prop_enum_list radeon_tv_std_enum_list[] = 1153926deccbSFrançois Tigeot { { TV_STD_NTSC, "ntsc" }, 1154926deccbSFrançois Tigeot { TV_STD_PAL, "pal" }, 1155926deccbSFrançois Tigeot { TV_STD_PAL_M, "pal-m" }, 1156926deccbSFrançois Tigeot { TV_STD_PAL_60, "pal-60" }, 1157926deccbSFrançois Tigeot { TV_STD_NTSC_J, "ntsc-j" }, 1158926deccbSFrançois Tigeot { TV_STD_SCART_PAL, "scart-pal" }, 1159926deccbSFrançois Tigeot { TV_STD_PAL_CN, "pal-cn" }, 1160926deccbSFrançois Tigeot { TV_STD_SECAM, "secam" }, 1161926deccbSFrançois Tigeot }; 1162926deccbSFrançois Tigeot 1163926deccbSFrançois Tigeot static struct drm_prop_enum_list radeon_underscan_enum_list[] = 1164926deccbSFrançois Tigeot { { UNDERSCAN_OFF, "off" }, 1165926deccbSFrançois Tigeot { UNDERSCAN_ON, "on" }, 1166926deccbSFrançois Tigeot { UNDERSCAN_AUTO, "auto" }, 1167926deccbSFrançois Tigeot }; 1168926deccbSFrançois Tigeot 1169926deccbSFrançois Tigeot static int radeon_modeset_create_props(struct radeon_device *rdev) 1170926deccbSFrançois Tigeot { 1171926deccbSFrançois Tigeot int sz; 1172926deccbSFrançois Tigeot 1173926deccbSFrançois Tigeot if (rdev->is_atom_bios) { 1174926deccbSFrançois Tigeot rdev->mode_info.coherent_mode_property = 1175926deccbSFrançois Tigeot drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1); 1176926deccbSFrançois Tigeot if (!rdev->mode_info.coherent_mode_property) 1177926deccbSFrançois Tigeot return -ENOMEM; 1178926deccbSFrançois Tigeot } 1179926deccbSFrançois Tigeot 1180926deccbSFrançois Tigeot if (!ASIC_IS_AVIVO(rdev)) { 1181926deccbSFrançois Tigeot sz = DRM_ARRAY_SIZE(radeon_tmds_pll_enum_list); 1182926deccbSFrançois Tigeot rdev->mode_info.tmds_pll_property = 1183926deccbSFrançois Tigeot drm_property_create_enum(rdev->ddev, 0, 1184926deccbSFrançois Tigeot "tmds_pll", 1185926deccbSFrançois Tigeot radeon_tmds_pll_enum_list, sz); 1186926deccbSFrançois Tigeot } 1187926deccbSFrançois Tigeot 1188926deccbSFrançois Tigeot rdev->mode_info.load_detect_property = 1189926deccbSFrançois Tigeot drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1); 1190926deccbSFrançois Tigeot if (!rdev->mode_info.load_detect_property) 1191926deccbSFrançois Tigeot return -ENOMEM; 1192926deccbSFrançois Tigeot 1193926deccbSFrançois Tigeot drm_mode_create_scaling_mode_property(rdev->ddev); 1194926deccbSFrançois Tigeot 1195926deccbSFrançois Tigeot sz = DRM_ARRAY_SIZE(radeon_tv_std_enum_list); 1196926deccbSFrançois Tigeot rdev->mode_info.tv_std_property = 1197926deccbSFrançois Tigeot drm_property_create_enum(rdev->ddev, 0, 1198926deccbSFrançois Tigeot "tv standard", 1199926deccbSFrançois Tigeot radeon_tv_std_enum_list, sz); 1200926deccbSFrançois Tigeot 1201926deccbSFrançois Tigeot sz = DRM_ARRAY_SIZE(radeon_underscan_enum_list); 1202926deccbSFrançois Tigeot rdev->mode_info.underscan_property = 1203926deccbSFrançois Tigeot drm_property_create_enum(rdev->ddev, 0, 1204926deccbSFrançois Tigeot "underscan", 1205926deccbSFrançois Tigeot radeon_underscan_enum_list, sz); 1206926deccbSFrançois Tigeot 1207926deccbSFrançois Tigeot rdev->mode_info.underscan_hborder_property = 1208926deccbSFrançois Tigeot drm_property_create_range(rdev->ddev, 0, 1209926deccbSFrançois Tigeot "underscan hborder", 0, 128); 1210926deccbSFrançois Tigeot if (!rdev->mode_info.underscan_hborder_property) 1211926deccbSFrançois Tigeot return -ENOMEM; 1212926deccbSFrançois Tigeot 1213926deccbSFrançois Tigeot rdev->mode_info.underscan_vborder_property = 1214926deccbSFrançois Tigeot drm_property_create_range(rdev->ddev, 0, 1215926deccbSFrançois Tigeot "underscan vborder", 0, 128); 1216926deccbSFrançois Tigeot if (!rdev->mode_info.underscan_vborder_property) 1217926deccbSFrançois Tigeot return -ENOMEM; 1218926deccbSFrançois Tigeot 1219926deccbSFrançois Tigeot return 0; 1220926deccbSFrançois Tigeot } 1221926deccbSFrançois Tigeot 1222926deccbSFrançois Tigeot void radeon_update_display_priority(struct radeon_device *rdev) 1223926deccbSFrançois Tigeot { 1224926deccbSFrançois Tigeot /* adjustment options for the display watermarks */ 1225926deccbSFrançois Tigeot if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { 1226926deccbSFrançois Tigeot /* set display priority to high for r3xx, rv515 chips 1227926deccbSFrançois Tigeot * this avoids flickering due to underflow to the 1228926deccbSFrançois Tigeot * display controllers during heavy acceleration. 1229926deccbSFrançois Tigeot * Don't force high on rs4xx igp chips as it seems to 1230926deccbSFrançois Tigeot * affect the sound card. See kernel bug 15982. 1231926deccbSFrançois Tigeot */ 1232926deccbSFrançois Tigeot if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && 1233926deccbSFrançois Tigeot !(rdev->flags & RADEON_IS_IGP)) 1234926deccbSFrançois Tigeot rdev->disp_priority = 2; 1235926deccbSFrançois Tigeot else 1236926deccbSFrançois Tigeot rdev->disp_priority = 0; 1237926deccbSFrançois Tigeot } else 1238926deccbSFrançois Tigeot rdev->disp_priority = radeon_disp_priority; 1239926deccbSFrançois Tigeot 1240926deccbSFrançois Tigeot } 1241926deccbSFrançois Tigeot 1242926deccbSFrançois Tigeot /* 1243926deccbSFrançois Tigeot * Allocate hdmi structs and determine register offsets 1244926deccbSFrançois Tigeot */ 1245926deccbSFrançois Tigeot static void radeon_afmt_init(struct radeon_device *rdev) 1246926deccbSFrançois Tigeot { 1247926deccbSFrançois Tigeot int i; 1248926deccbSFrançois Tigeot 1249926deccbSFrançois Tigeot for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) 1250926deccbSFrançois Tigeot rdev->mode_info.afmt[i] = NULL; 1251926deccbSFrançois Tigeot 1252926deccbSFrançois Tigeot if (ASIC_IS_DCE6(rdev)) { 1253926deccbSFrançois Tigeot /* todo */ 1254926deccbSFrançois Tigeot } else if (ASIC_IS_DCE4(rdev)) { 1255926deccbSFrançois Tigeot /* DCE4/5 has 6 audio blocks tied to DIG encoders */ 1256926deccbSFrançois Tigeot /* DCE4.1 has 2 audio blocks tied to DIG encoders */ 1257926deccbSFrançois Tigeot rdev->mode_info.afmt[0] = kmalloc(sizeof(struct radeon_afmt), 12585a3b77d5SFrançois Tigeot M_DRM, 1259926deccbSFrançois Tigeot M_WAITOK | M_ZERO); 1260926deccbSFrançois Tigeot if (rdev->mode_info.afmt[0]) { 1261926deccbSFrançois Tigeot rdev->mode_info.afmt[0]->offset = EVERGREEN_CRTC0_REGISTER_OFFSET; 1262926deccbSFrançois Tigeot rdev->mode_info.afmt[0]->id = 0; 1263926deccbSFrançois Tigeot } 1264926deccbSFrançois Tigeot rdev->mode_info.afmt[1] = kmalloc(sizeof(struct radeon_afmt), 12655a3b77d5SFrançois Tigeot M_DRM, 1266926deccbSFrançois Tigeot M_WAITOK | M_ZERO); 1267926deccbSFrançois Tigeot if (rdev->mode_info.afmt[1]) { 1268926deccbSFrançois Tigeot rdev->mode_info.afmt[1]->offset = EVERGREEN_CRTC1_REGISTER_OFFSET; 1269926deccbSFrançois Tigeot rdev->mode_info.afmt[1]->id = 1; 1270926deccbSFrançois Tigeot } 1271926deccbSFrançois Tigeot if (!ASIC_IS_DCE41(rdev)) { 1272926deccbSFrançois Tigeot rdev->mode_info.afmt[2] = kmalloc(sizeof(struct radeon_afmt), 12735a3b77d5SFrançois Tigeot M_DRM, 1274926deccbSFrançois Tigeot M_WAITOK | M_ZERO); 1275926deccbSFrançois Tigeot if (rdev->mode_info.afmt[2]) { 1276926deccbSFrançois Tigeot rdev->mode_info.afmt[2]->offset = EVERGREEN_CRTC2_REGISTER_OFFSET; 1277926deccbSFrançois Tigeot rdev->mode_info.afmt[2]->id = 2; 1278926deccbSFrançois Tigeot } 1279926deccbSFrançois Tigeot rdev->mode_info.afmt[3] = kmalloc(sizeof(struct radeon_afmt), 12805a3b77d5SFrançois Tigeot M_DRM, 1281926deccbSFrançois Tigeot M_WAITOK | M_ZERO); 1282926deccbSFrançois Tigeot if (rdev->mode_info.afmt[3]) { 1283926deccbSFrançois Tigeot rdev->mode_info.afmt[3]->offset = EVERGREEN_CRTC3_REGISTER_OFFSET; 1284926deccbSFrançois Tigeot rdev->mode_info.afmt[3]->id = 3; 1285926deccbSFrançois Tigeot } 1286926deccbSFrançois Tigeot rdev->mode_info.afmt[4] = kmalloc(sizeof(struct radeon_afmt), 12875a3b77d5SFrançois Tigeot M_DRM, 1288926deccbSFrançois Tigeot M_WAITOK | M_ZERO); 1289926deccbSFrançois Tigeot if (rdev->mode_info.afmt[4]) { 1290926deccbSFrançois Tigeot rdev->mode_info.afmt[4]->offset = EVERGREEN_CRTC4_REGISTER_OFFSET; 1291926deccbSFrançois Tigeot rdev->mode_info.afmt[4]->id = 4; 1292926deccbSFrançois Tigeot } 1293926deccbSFrançois Tigeot rdev->mode_info.afmt[5] = kmalloc(sizeof(struct radeon_afmt), 12945a3b77d5SFrançois Tigeot M_DRM, 1295926deccbSFrançois Tigeot M_WAITOK | M_ZERO); 1296926deccbSFrançois Tigeot if (rdev->mode_info.afmt[5]) { 1297926deccbSFrançois Tigeot rdev->mode_info.afmt[5]->offset = EVERGREEN_CRTC5_REGISTER_OFFSET; 1298926deccbSFrançois Tigeot rdev->mode_info.afmt[5]->id = 5; 1299926deccbSFrançois Tigeot } 1300926deccbSFrançois Tigeot } 1301926deccbSFrançois Tigeot } else if (ASIC_IS_DCE3(rdev)) { 1302926deccbSFrançois Tigeot /* DCE3.x has 2 audio blocks tied to DIG encoders */ 1303926deccbSFrançois Tigeot rdev->mode_info.afmt[0] = kmalloc(sizeof(struct radeon_afmt), 13045a3b77d5SFrançois Tigeot M_DRM, 1305926deccbSFrançois Tigeot M_WAITOK | M_ZERO); 1306926deccbSFrançois Tigeot if (rdev->mode_info.afmt[0]) { 1307926deccbSFrançois Tigeot rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0; 1308926deccbSFrançois Tigeot rdev->mode_info.afmt[0]->id = 0; 1309926deccbSFrançois Tigeot } 1310926deccbSFrançois Tigeot rdev->mode_info.afmt[1] = kmalloc(sizeof(struct radeon_afmt), 13115a3b77d5SFrançois Tigeot M_DRM, 1312926deccbSFrançois Tigeot M_WAITOK | M_ZERO); 1313926deccbSFrançois Tigeot if (rdev->mode_info.afmt[1]) { 1314926deccbSFrançois Tigeot rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1; 1315926deccbSFrançois Tigeot rdev->mode_info.afmt[1]->id = 1; 1316926deccbSFrançois Tigeot } 1317926deccbSFrançois Tigeot } else if (ASIC_IS_DCE2(rdev)) { 1318926deccbSFrançois Tigeot /* DCE2 has at least 1 routable audio block */ 1319926deccbSFrançois Tigeot rdev->mode_info.afmt[0] = kmalloc(sizeof(struct radeon_afmt), 13205a3b77d5SFrançois Tigeot M_DRM, 1321926deccbSFrançois Tigeot M_WAITOK | M_ZERO); 1322926deccbSFrançois Tigeot if (rdev->mode_info.afmt[0]) { 1323926deccbSFrançois Tigeot rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0; 1324926deccbSFrançois Tigeot rdev->mode_info.afmt[0]->id = 0; 1325926deccbSFrançois Tigeot } 1326926deccbSFrançois Tigeot /* r6xx has 2 routable audio blocks */ 1327926deccbSFrançois Tigeot if (rdev->family >= CHIP_R600) { 1328926deccbSFrançois Tigeot rdev->mode_info.afmt[1] = kmalloc(sizeof(struct radeon_afmt), 13295a3b77d5SFrançois Tigeot M_DRM, 1330926deccbSFrançois Tigeot M_WAITOK | M_ZERO); 1331926deccbSFrançois Tigeot if (rdev->mode_info.afmt[1]) { 1332926deccbSFrançois Tigeot rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1; 1333926deccbSFrançois Tigeot rdev->mode_info.afmt[1]->id = 1; 1334926deccbSFrançois Tigeot } 1335926deccbSFrançois Tigeot } 1336926deccbSFrançois Tigeot } 1337926deccbSFrançois Tigeot } 1338926deccbSFrançois Tigeot 1339926deccbSFrançois Tigeot static void radeon_afmt_fini(struct radeon_device *rdev) 1340926deccbSFrançois Tigeot { 1341926deccbSFrançois Tigeot int i; 1342926deccbSFrançois Tigeot 1343926deccbSFrançois Tigeot for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) { 13445a3b77d5SFrançois Tigeot drm_free(rdev->mode_info.afmt[i], M_DRM); 1345926deccbSFrançois Tigeot rdev->mode_info.afmt[i] = NULL; 1346926deccbSFrançois Tigeot } 1347926deccbSFrançois Tigeot } 1348926deccbSFrançois Tigeot 1349926deccbSFrançois Tigeot int radeon_modeset_init(struct radeon_device *rdev) 1350926deccbSFrançois Tigeot { 1351926deccbSFrançois Tigeot int i; 1352926deccbSFrançois Tigeot int ret; 1353926deccbSFrançois Tigeot 1354926deccbSFrançois Tigeot drm_mode_config_init(rdev->ddev); 1355926deccbSFrançois Tigeot rdev->mode_info.mode_config_initialized = true; 1356926deccbSFrançois Tigeot 1357926deccbSFrançois Tigeot rdev->ddev->mode_config.funcs = &radeon_mode_funcs; 1358926deccbSFrançois Tigeot 1359926deccbSFrançois Tigeot if (ASIC_IS_DCE5(rdev)) { 1360926deccbSFrançois Tigeot rdev->ddev->mode_config.max_width = 16384; 1361926deccbSFrançois Tigeot rdev->ddev->mode_config.max_height = 16384; 1362926deccbSFrançois Tigeot } else if (ASIC_IS_AVIVO(rdev)) { 1363926deccbSFrançois Tigeot rdev->ddev->mode_config.max_width = 8192; 1364926deccbSFrançois Tigeot rdev->ddev->mode_config.max_height = 8192; 1365926deccbSFrançois Tigeot } else { 1366926deccbSFrançois Tigeot rdev->ddev->mode_config.max_width = 4096; 1367926deccbSFrançois Tigeot rdev->ddev->mode_config.max_height = 4096; 1368926deccbSFrançois Tigeot } 1369926deccbSFrançois Tigeot 1370926deccbSFrançois Tigeot rdev->ddev->mode_config.preferred_depth = 24; 1371926deccbSFrançois Tigeot rdev->ddev->mode_config.prefer_shadow = 1; 1372926deccbSFrançois Tigeot 1373926deccbSFrançois Tigeot rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; 1374926deccbSFrançois Tigeot 1375926deccbSFrançois Tigeot ret = radeon_modeset_create_props(rdev); 1376926deccbSFrançois Tigeot if (ret) { 1377926deccbSFrançois Tigeot return ret; 1378926deccbSFrançois Tigeot } 1379926deccbSFrançois Tigeot 1380926deccbSFrançois Tigeot /* init i2c buses */ 1381926deccbSFrançois Tigeot radeon_i2c_init(rdev); 1382926deccbSFrançois Tigeot 1383926deccbSFrançois Tigeot /* check combios for a valid hardcoded EDID - Sun servers */ 1384926deccbSFrançois Tigeot if (!rdev->is_atom_bios) { 1385926deccbSFrançois Tigeot /* check for hardcoded EDID in BIOS */ 1386926deccbSFrançois Tigeot radeon_combios_check_hardcoded_edid(rdev); 1387926deccbSFrançois Tigeot } 1388926deccbSFrançois Tigeot 1389926deccbSFrançois Tigeot /* allocate crtcs */ 1390926deccbSFrançois Tigeot for (i = 0; i < rdev->num_crtc; i++) { 1391926deccbSFrançois Tigeot radeon_crtc_init(rdev->ddev, i); 1392926deccbSFrançois Tigeot } 1393926deccbSFrançois Tigeot 1394926deccbSFrançois Tigeot /* okay we should have all the bios connectors */ 1395926deccbSFrançois Tigeot ret = radeon_setup_enc_conn(rdev->ddev); 1396926deccbSFrançois Tigeot if (!ret) { 1397926deccbSFrançois Tigeot return ret; 1398926deccbSFrançois Tigeot } 1399926deccbSFrançois Tigeot 1400926deccbSFrançois Tigeot /* init dig PHYs, disp eng pll */ 1401926deccbSFrançois Tigeot if (rdev->is_atom_bios) { 1402926deccbSFrançois Tigeot radeon_atom_encoder_init(rdev); 1403926deccbSFrançois Tigeot radeon_atom_disp_eng_pll_init(rdev); 1404926deccbSFrançois Tigeot } 1405926deccbSFrançois Tigeot 1406926deccbSFrançois Tigeot /* initialize hpd */ 1407926deccbSFrançois Tigeot radeon_hpd_init(rdev); 1408926deccbSFrançois Tigeot 1409926deccbSFrançois Tigeot /* setup afmt */ 1410926deccbSFrançois Tigeot radeon_afmt_init(rdev); 1411926deccbSFrançois Tigeot 1412926deccbSFrançois Tigeot /* Initialize power management */ 1413926deccbSFrançois Tigeot radeon_pm_init(rdev); 1414926deccbSFrançois Tigeot 1415926deccbSFrançois Tigeot radeon_fbdev_init(rdev); 1416926deccbSFrançois Tigeot drm_kms_helper_poll_init(rdev->ddev); 1417926deccbSFrançois Tigeot 1418926deccbSFrançois Tigeot return 0; 1419926deccbSFrançois Tigeot } 1420926deccbSFrançois Tigeot 1421926deccbSFrançois Tigeot void radeon_modeset_fini(struct radeon_device *rdev) 1422926deccbSFrançois Tigeot { 1423926deccbSFrançois Tigeot radeon_fbdev_fini(rdev); 14245a3b77d5SFrançois Tigeot drm_free(rdev->mode_info.bios_hardcoded_edid, M_DRM); 1425926deccbSFrançois Tigeot radeon_pm_fini(rdev); 1426926deccbSFrançois Tigeot 1427926deccbSFrançois Tigeot if (rdev->mode_info.mode_config_initialized) { 1428926deccbSFrançois Tigeot radeon_afmt_fini(rdev); 1429926deccbSFrançois Tigeot drm_kms_helper_poll_fini(rdev->ddev); 1430926deccbSFrançois Tigeot radeon_hpd_fini(rdev); 1431926deccbSFrançois Tigeot DRM_UNLOCK(rdev->ddev); /* Work around lock recursion. dumbbell@ */ 1432926deccbSFrançois Tigeot drm_mode_config_cleanup(rdev->ddev); 1433926deccbSFrançois Tigeot DRM_LOCK(rdev->ddev); 1434926deccbSFrançois Tigeot rdev->mode_info.mode_config_initialized = false; 1435926deccbSFrançois Tigeot } 1436926deccbSFrançois Tigeot /* free i2c buses */ 1437926deccbSFrançois Tigeot radeon_i2c_fini(rdev); 1438926deccbSFrançois Tigeot } 1439926deccbSFrançois Tigeot 1440926deccbSFrançois Tigeot static bool is_hdtv_mode(const struct drm_display_mode *mode) 1441926deccbSFrançois Tigeot { 1442926deccbSFrançois Tigeot /* try and guess if this is a tv or a monitor */ 1443926deccbSFrançois Tigeot if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 1444926deccbSFrançois Tigeot (mode->vdisplay == 576) || /* 576p */ 1445926deccbSFrançois Tigeot (mode->vdisplay == 720) || /* 720p */ 1446926deccbSFrançois Tigeot (mode->vdisplay == 1080)) /* 1080p */ 1447926deccbSFrançois Tigeot return true; 1448926deccbSFrançois Tigeot else 1449926deccbSFrançois Tigeot return false; 1450926deccbSFrançois Tigeot } 1451926deccbSFrançois Tigeot 1452926deccbSFrançois Tigeot bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 1453926deccbSFrançois Tigeot const struct drm_display_mode *mode, 1454926deccbSFrançois Tigeot struct drm_display_mode *adjusted_mode) 1455926deccbSFrançois Tigeot { 1456926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev; 1457926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 1458926deccbSFrançois Tigeot struct drm_encoder *encoder; 1459926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1460926deccbSFrançois Tigeot struct radeon_encoder *radeon_encoder; 1461926deccbSFrançois Tigeot struct drm_connector *connector; 1462926deccbSFrançois Tigeot struct radeon_connector *radeon_connector; 1463926deccbSFrançois Tigeot bool first = true; 1464926deccbSFrançois Tigeot u32 src_v = 1, dst_v = 1; 1465926deccbSFrançois Tigeot u32 src_h = 1, dst_h = 1; 1466926deccbSFrançois Tigeot 1467926deccbSFrançois Tigeot radeon_crtc->h_border = 0; 1468926deccbSFrançois Tigeot radeon_crtc->v_border = 0; 1469926deccbSFrançois Tigeot 1470926deccbSFrançois Tigeot list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1471926deccbSFrançois Tigeot if (encoder->crtc != crtc) 1472926deccbSFrançois Tigeot continue; 1473926deccbSFrançois Tigeot radeon_encoder = to_radeon_encoder(encoder); 1474926deccbSFrançois Tigeot connector = radeon_get_connector_for_encoder(encoder); 1475926deccbSFrançois Tigeot radeon_connector = to_radeon_connector(connector); 1476926deccbSFrançois Tigeot 1477926deccbSFrançois Tigeot if (first) { 1478926deccbSFrançois Tigeot /* set scaling */ 1479926deccbSFrançois Tigeot if (radeon_encoder->rmx_type == RMX_OFF) 1480926deccbSFrançois Tigeot radeon_crtc->rmx_type = RMX_OFF; 1481926deccbSFrançois Tigeot else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || 1482926deccbSFrançois Tigeot mode->vdisplay < radeon_encoder->native_mode.vdisplay) 1483926deccbSFrançois Tigeot radeon_crtc->rmx_type = radeon_encoder->rmx_type; 1484926deccbSFrançois Tigeot else 1485926deccbSFrançois Tigeot radeon_crtc->rmx_type = RMX_OFF; 1486926deccbSFrançois Tigeot /* copy native mode */ 1487926deccbSFrançois Tigeot memcpy(&radeon_crtc->native_mode, 1488926deccbSFrançois Tigeot &radeon_encoder->native_mode, 1489926deccbSFrançois Tigeot sizeof(struct drm_display_mode)); 1490926deccbSFrançois Tigeot src_v = crtc->mode.vdisplay; 1491926deccbSFrançois Tigeot dst_v = radeon_crtc->native_mode.vdisplay; 1492926deccbSFrançois Tigeot src_h = crtc->mode.hdisplay; 1493926deccbSFrançois Tigeot dst_h = radeon_crtc->native_mode.hdisplay; 1494926deccbSFrançois Tigeot 1495926deccbSFrançois Tigeot /* fix up for overscan on hdmi */ 1496926deccbSFrançois Tigeot if (ASIC_IS_AVIVO(rdev) && 1497926deccbSFrançois Tigeot (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 1498926deccbSFrançois Tigeot ((radeon_encoder->underscan_type == UNDERSCAN_ON) || 1499926deccbSFrançois Tigeot ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && 1500926deccbSFrançois Tigeot drm_detect_hdmi_monitor(radeon_connector->edid) && 1501926deccbSFrançois Tigeot is_hdtv_mode(mode)))) { 1502926deccbSFrançois Tigeot if (radeon_encoder->underscan_hborder != 0) 1503926deccbSFrançois Tigeot radeon_crtc->h_border = radeon_encoder->underscan_hborder; 1504926deccbSFrançois Tigeot else 1505926deccbSFrançois Tigeot radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; 1506926deccbSFrançois Tigeot if (radeon_encoder->underscan_vborder != 0) 1507926deccbSFrançois Tigeot radeon_crtc->v_border = radeon_encoder->underscan_vborder; 1508926deccbSFrançois Tigeot else 1509926deccbSFrançois Tigeot radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; 1510926deccbSFrançois Tigeot radeon_crtc->rmx_type = RMX_FULL; 1511926deccbSFrançois Tigeot src_v = crtc->mode.vdisplay; 1512926deccbSFrançois Tigeot dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); 1513926deccbSFrançois Tigeot src_h = crtc->mode.hdisplay; 1514926deccbSFrançois Tigeot dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); 1515926deccbSFrançois Tigeot } 1516926deccbSFrançois Tigeot first = false; 1517926deccbSFrançois Tigeot } else { 1518926deccbSFrançois Tigeot if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { 1519926deccbSFrançois Tigeot /* WARNING: Right now this can't happen but 1520926deccbSFrançois Tigeot * in the future we need to check that scaling 1521926deccbSFrançois Tigeot * are consistent across different encoder 1522926deccbSFrançois Tigeot * (ie all encoder can work with the same 1523926deccbSFrançois Tigeot * scaling). 1524926deccbSFrançois Tigeot */ 1525926deccbSFrançois Tigeot DRM_ERROR("Scaling not consistent across encoder.\n"); 1526926deccbSFrançois Tigeot return false; 1527926deccbSFrançois Tigeot } 1528926deccbSFrançois Tigeot } 1529926deccbSFrançois Tigeot } 1530926deccbSFrançois Tigeot if (radeon_crtc->rmx_type != RMX_OFF) { 1531926deccbSFrançois Tigeot fixed20_12 a, b; 1532926deccbSFrançois Tigeot a.full = dfixed_const(src_v); 1533926deccbSFrançois Tigeot b.full = dfixed_const(dst_v); 1534926deccbSFrançois Tigeot radeon_crtc->vsc.full = dfixed_div(a, b); 1535926deccbSFrançois Tigeot a.full = dfixed_const(src_h); 1536926deccbSFrançois Tigeot b.full = dfixed_const(dst_h); 1537926deccbSFrançois Tigeot radeon_crtc->hsc.full = dfixed_div(a, b); 1538926deccbSFrançois Tigeot } else { 1539926deccbSFrançois Tigeot radeon_crtc->vsc.full = dfixed_const(1); 1540926deccbSFrançois Tigeot radeon_crtc->hsc.full = dfixed_const(1); 1541926deccbSFrançois Tigeot } 1542926deccbSFrançois Tigeot return true; 1543926deccbSFrançois Tigeot } 1544926deccbSFrançois Tigeot 1545926deccbSFrançois Tigeot /* 1546926deccbSFrançois Tigeot * Retrieve current video scanout position of crtc on a given gpu. 1547926deccbSFrançois Tigeot * 1548926deccbSFrançois Tigeot * \param dev Device to query. 1549926deccbSFrançois Tigeot * \param crtc Crtc to query. 1550926deccbSFrançois Tigeot * \param *vpos Location where vertical scanout position should be stored. 1551926deccbSFrançois Tigeot * \param *hpos Location where horizontal scanout position should go. 1552926deccbSFrançois Tigeot * 1553926deccbSFrançois Tigeot * Returns vpos as a positive number while in active scanout area. 1554926deccbSFrançois Tigeot * Returns vpos as a negative number inside vblank, counting the number 1555926deccbSFrançois Tigeot * of scanlines to go until end of vblank, e.g., -1 means "one scanline 1556926deccbSFrançois Tigeot * until start of active scanout / end of vblank." 1557926deccbSFrançois Tigeot * 1558926deccbSFrançois Tigeot * \return Flags, or'ed together as follows: 1559926deccbSFrançois Tigeot * 1560926deccbSFrançois Tigeot * DRM_SCANOUTPOS_VALID = Query successful. 1561926deccbSFrançois Tigeot * DRM_SCANOUTPOS_INVBL = Inside vblank. 1562926deccbSFrançois Tigeot * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 1563926deccbSFrançois Tigeot * this flag means that returned position may be offset by a constant but 1564926deccbSFrançois Tigeot * unknown small number of scanlines wrt. real scanout position. 1565926deccbSFrançois Tigeot * 1566926deccbSFrançois Tigeot */ 1567926deccbSFrançois Tigeot int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos) 1568926deccbSFrançois Tigeot { 1569926deccbSFrançois Tigeot u32 stat_crtc = 0, vbl = 0, position = 0; 1570926deccbSFrançois Tigeot int vbl_start, vbl_end, vtotal, ret = 0; 1571926deccbSFrançois Tigeot bool in_vbl = true; 1572926deccbSFrançois Tigeot 1573926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 1574926deccbSFrançois Tigeot 1575926deccbSFrançois Tigeot if (ASIC_IS_DCE4(rdev)) { 1576926deccbSFrançois Tigeot if (crtc == 0) { 1577926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1578926deccbSFrançois Tigeot EVERGREEN_CRTC0_REGISTER_OFFSET); 1579926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1580926deccbSFrançois Tigeot EVERGREEN_CRTC0_REGISTER_OFFSET); 1581926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1582926deccbSFrançois Tigeot } 1583926deccbSFrançois Tigeot if (crtc == 1) { 1584926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1585926deccbSFrançois Tigeot EVERGREEN_CRTC1_REGISTER_OFFSET); 1586926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1587926deccbSFrançois Tigeot EVERGREEN_CRTC1_REGISTER_OFFSET); 1588926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1589926deccbSFrançois Tigeot } 1590926deccbSFrançois Tigeot if (crtc == 2) { 1591926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1592926deccbSFrançois Tigeot EVERGREEN_CRTC2_REGISTER_OFFSET); 1593926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1594926deccbSFrançois Tigeot EVERGREEN_CRTC2_REGISTER_OFFSET); 1595926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1596926deccbSFrançois Tigeot } 1597926deccbSFrançois Tigeot if (crtc == 3) { 1598926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1599926deccbSFrançois Tigeot EVERGREEN_CRTC3_REGISTER_OFFSET); 1600926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1601926deccbSFrançois Tigeot EVERGREEN_CRTC3_REGISTER_OFFSET); 1602926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1603926deccbSFrançois Tigeot } 1604926deccbSFrançois Tigeot if (crtc == 4) { 1605926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1606926deccbSFrançois Tigeot EVERGREEN_CRTC4_REGISTER_OFFSET); 1607926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1608926deccbSFrançois Tigeot EVERGREEN_CRTC4_REGISTER_OFFSET); 1609926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1610926deccbSFrançois Tigeot } 1611926deccbSFrançois Tigeot if (crtc == 5) { 1612926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1613926deccbSFrançois Tigeot EVERGREEN_CRTC5_REGISTER_OFFSET); 1614926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1615926deccbSFrançois Tigeot EVERGREEN_CRTC5_REGISTER_OFFSET); 1616926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1617926deccbSFrançois Tigeot } 1618926deccbSFrançois Tigeot } else if (ASIC_IS_AVIVO(rdev)) { 1619926deccbSFrançois Tigeot if (crtc == 0) { 1620926deccbSFrançois Tigeot vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); 1621926deccbSFrançois Tigeot position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); 1622926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1623926deccbSFrançois Tigeot } 1624926deccbSFrançois Tigeot if (crtc == 1) { 1625926deccbSFrançois Tigeot vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); 1626926deccbSFrançois Tigeot position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); 1627926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1628926deccbSFrançois Tigeot } 1629926deccbSFrançois Tigeot } else { 1630926deccbSFrançois Tigeot /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ 1631926deccbSFrançois Tigeot if (crtc == 0) { 1632926deccbSFrançois Tigeot /* Assume vbl_end == 0, get vbl_start from 1633926deccbSFrançois Tigeot * upper 16 bits. 1634926deccbSFrançois Tigeot */ 1635926deccbSFrançois Tigeot vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & 1636926deccbSFrançois Tigeot RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1637926deccbSFrançois Tigeot /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ 1638926deccbSFrançois Tigeot position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1639926deccbSFrançois Tigeot stat_crtc = RREG32(RADEON_CRTC_STATUS); 1640926deccbSFrançois Tigeot if (!(stat_crtc & 1)) 1641926deccbSFrançois Tigeot in_vbl = false; 1642926deccbSFrançois Tigeot 1643926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1644926deccbSFrançois Tigeot } 1645926deccbSFrançois Tigeot if (crtc == 1) { 1646926deccbSFrançois Tigeot vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & 1647926deccbSFrançois Tigeot RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1648926deccbSFrançois Tigeot position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1649926deccbSFrançois Tigeot stat_crtc = RREG32(RADEON_CRTC2_STATUS); 1650926deccbSFrançois Tigeot if (!(stat_crtc & 1)) 1651926deccbSFrançois Tigeot in_vbl = false; 1652926deccbSFrançois Tigeot 1653926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1654926deccbSFrançois Tigeot } 1655926deccbSFrançois Tigeot } 1656926deccbSFrançois Tigeot 1657926deccbSFrançois Tigeot /* Decode into vertical and horizontal scanout position. */ 1658926deccbSFrançois Tigeot *vpos = position & 0x1fff; 1659926deccbSFrançois Tigeot *hpos = (position >> 16) & 0x1fff; 1660926deccbSFrançois Tigeot 1661926deccbSFrançois Tigeot /* Valid vblank area boundaries from gpu retrieved? */ 1662926deccbSFrançois Tigeot if (vbl > 0) { 1663926deccbSFrançois Tigeot /* Yes: Decode. */ 1664926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_ACCURATE; 1665926deccbSFrançois Tigeot vbl_start = vbl & 0x1fff; 1666926deccbSFrançois Tigeot vbl_end = (vbl >> 16) & 0x1fff; 1667926deccbSFrançois Tigeot } 1668926deccbSFrançois Tigeot else { 1669926deccbSFrançois Tigeot /* No: Fake something reasonable which gives at least ok results. */ 1670926deccbSFrançois Tigeot vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay; 1671926deccbSFrançois Tigeot vbl_end = 0; 1672926deccbSFrançois Tigeot } 1673926deccbSFrançois Tigeot 1674926deccbSFrançois Tigeot /* Test scanout position against vblank region. */ 1675926deccbSFrançois Tigeot if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 1676926deccbSFrançois Tigeot in_vbl = false; 1677926deccbSFrançois Tigeot 1678926deccbSFrançois Tigeot /* Check if inside vblank area and apply corrective offsets: 1679926deccbSFrançois Tigeot * vpos will then be >=0 in video scanout area, but negative 1680926deccbSFrançois Tigeot * within vblank area, counting down the number of lines until 1681926deccbSFrançois Tigeot * start of scanout. 1682926deccbSFrançois Tigeot */ 1683926deccbSFrançois Tigeot 1684926deccbSFrançois Tigeot /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 1685926deccbSFrançois Tigeot if (in_vbl && (*vpos >= vbl_start)) { 1686926deccbSFrançois Tigeot vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal; 1687926deccbSFrançois Tigeot *vpos = *vpos - vtotal; 1688926deccbSFrançois Tigeot } 1689926deccbSFrançois Tigeot 1690926deccbSFrançois Tigeot /* Correct for shifted end of vbl at vbl_end. */ 1691926deccbSFrançois Tigeot *vpos = *vpos - vbl_end; 1692926deccbSFrançois Tigeot 1693926deccbSFrançois Tigeot /* In vblank? */ 1694926deccbSFrançois Tigeot if (in_vbl) 1695926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_INVBL; 1696926deccbSFrançois Tigeot 1697926deccbSFrançois Tigeot return ret; 1698926deccbSFrançois Tigeot } 1699