1926deccbSFrançois Tigeot /* 2926deccbSFrançois Tigeot * Copyright 2007-8 Advanced Micro Devices, Inc. 3926deccbSFrançois Tigeot * Copyright 2008 Red Hat Inc. 4926deccbSFrançois Tigeot * 5926deccbSFrançois Tigeot * Permission is hereby granted, free of charge, to any person obtaining a 6926deccbSFrançois Tigeot * copy of this software and associated documentation files (the "Software"), 7926deccbSFrançois Tigeot * to deal in the Software without restriction, including without limitation 8926deccbSFrançois Tigeot * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9926deccbSFrançois Tigeot * and/or sell copies of the Software, and to permit persons to whom the 10926deccbSFrançois Tigeot * Software is furnished to do so, subject to the following conditions: 11926deccbSFrançois Tigeot * 12926deccbSFrançois Tigeot * The above copyright notice and this permission notice shall be included in 13926deccbSFrançois Tigeot * all copies or substantial portions of the Software. 14926deccbSFrançois Tigeot * 15926deccbSFrançois Tigeot * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16926deccbSFrançois Tigeot * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17926deccbSFrançois Tigeot * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18926deccbSFrançois Tigeot * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19926deccbSFrançois Tigeot * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20926deccbSFrançois Tigeot * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21926deccbSFrançois Tigeot * OTHER DEALINGS IN THE SOFTWARE. 22926deccbSFrançois Tigeot * 23926deccbSFrançois Tigeot * Authors: Dave Airlie 24926deccbSFrançois Tigeot * Alex Deucher 25926deccbSFrançois Tigeot * 26926deccbSFrançois Tigeot * $FreeBSD: head/sys/dev/drm2/radeon/radeon_display.c 254885 2013-08-25 19:37:15Z dumbbell $ 27926deccbSFrançois Tigeot */ 28926deccbSFrançois Tigeot 29926deccbSFrançois Tigeot #include <drm/drmP.h> 30926deccbSFrançois Tigeot #include <uapi_drm/radeon_drm.h> 31926deccbSFrançois Tigeot #include "radeon.h" 32926deccbSFrançois Tigeot 33926deccbSFrançois Tigeot #include "atom.h" 34926deccbSFrançois Tigeot 35c6f73aabSFrançois Tigeot #ifdef PM_TODO 36c6f73aabSFrançois Tigeot #include <linux/pm_runtime.h> 37c6f73aabSFrançois Tigeot #endif 38926deccbSFrançois Tigeot #include <drm/drm_crtc_helper.h> 392c9916cdSFrançois Tigeot #include <drm/drm_plane_helper.h> 40926deccbSFrançois Tigeot #include <drm/drm_edid.h> 4160fc7eecSFrançois Tigeot #include <linux/err.h> 42926deccbSFrançois Tigeot 43c6f73aabSFrançois Tigeot #include <linux/gcd.h> 44c6f73aabSFrançois Tigeot 45926deccbSFrançois Tigeot static void avivo_crtc_load_lut(struct drm_crtc *crtc) 46926deccbSFrançois Tigeot { 47926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 48926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev; 49926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 50926deccbSFrançois Tigeot int i; 51926deccbSFrançois Tigeot 52926deccbSFrançois Tigeot DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 53926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); 54926deccbSFrançois Tigeot 55926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 56926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 57926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 58926deccbSFrançois Tigeot 59926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 60926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 61926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 62926deccbSFrançois Tigeot 63926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); 64926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUT_RW_MODE, 0); 65926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); 66926deccbSFrançois Tigeot 67926deccbSFrançois Tigeot WREG8(AVIVO_DC_LUT_RW_INDEX, 0); 68926deccbSFrançois Tigeot for (i = 0; i < 256; i++) { 69926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUT_30_COLOR, 70926deccbSFrançois Tigeot (radeon_crtc->lut_r[i] << 20) | 71926deccbSFrançois Tigeot (radeon_crtc->lut_g[i] << 10) | 72926deccbSFrançois Tigeot (radeon_crtc->lut_b[i] << 0)); 73926deccbSFrançois Tigeot } 74926deccbSFrançois Tigeot 75c6f73aabSFrançois Tigeot /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */ 76c6f73aabSFrançois Tigeot WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1); 77926deccbSFrançois Tigeot } 78926deccbSFrançois Tigeot 79926deccbSFrançois Tigeot static void dce4_crtc_load_lut(struct drm_crtc *crtc) 80926deccbSFrançois Tigeot { 81926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 82926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev; 83926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 84926deccbSFrançois Tigeot int i; 85926deccbSFrançois Tigeot 86926deccbSFrançois Tigeot DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 87926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 88926deccbSFrançois Tigeot 89926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 90926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 91926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 92926deccbSFrançois Tigeot 93926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 94926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 95926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 96926deccbSFrançois Tigeot 97926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 98926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 99926deccbSFrançois Tigeot 100926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 101926deccbSFrançois Tigeot for (i = 0; i < 256; i++) { 102926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 103926deccbSFrançois Tigeot (radeon_crtc->lut_r[i] << 20) | 104926deccbSFrançois Tigeot (radeon_crtc->lut_g[i] << 10) | 105926deccbSFrançois Tigeot (radeon_crtc->lut_b[i] << 0)); 106926deccbSFrançois Tigeot } 107926deccbSFrançois Tigeot } 108926deccbSFrançois Tigeot 109926deccbSFrançois Tigeot static void dce5_crtc_load_lut(struct drm_crtc *crtc) 110926deccbSFrançois Tigeot { 111926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 112926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev; 113926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 114926deccbSFrançois Tigeot int i; 115926deccbSFrançois Tigeot 116926deccbSFrançois Tigeot DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 117926deccbSFrançois Tigeot 118926deccbSFrançois Tigeot WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 119926deccbSFrançois Tigeot (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | 120926deccbSFrançois Tigeot NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); 121926deccbSFrançois Tigeot WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, 122926deccbSFrançois Tigeot NI_GRPH_PRESCALE_BYPASS); 123926deccbSFrançois Tigeot WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, 124926deccbSFrançois Tigeot NI_OVL_PRESCALE_BYPASS); 125926deccbSFrançois Tigeot WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, 126926deccbSFrançois Tigeot (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | 127926deccbSFrançois Tigeot NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); 128926deccbSFrançois Tigeot 129926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 130926deccbSFrançois Tigeot 131926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 132926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 133926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 134926deccbSFrançois Tigeot 135926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 136926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 137926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 138926deccbSFrançois Tigeot 139926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 140926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 141926deccbSFrançois Tigeot 142926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 143926deccbSFrançois Tigeot for (i = 0; i < 256; i++) { 144926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 145926deccbSFrançois Tigeot (radeon_crtc->lut_r[i] << 20) | 146926deccbSFrançois Tigeot (radeon_crtc->lut_g[i] << 10) | 147926deccbSFrançois Tigeot (radeon_crtc->lut_b[i] << 0)); 148926deccbSFrançois Tigeot } 149926deccbSFrançois Tigeot 150926deccbSFrançois Tigeot WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, 151926deccbSFrançois Tigeot (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 152926deccbSFrançois Tigeot NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 153926deccbSFrançois Tigeot NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 154926deccbSFrançois Tigeot NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); 155926deccbSFrançois Tigeot WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, 156926deccbSFrançois Tigeot (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | 157926deccbSFrançois Tigeot NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); 158926deccbSFrançois Tigeot WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, 159926deccbSFrançois Tigeot (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | 160926deccbSFrançois Tigeot NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); 161926deccbSFrançois Tigeot WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 162926deccbSFrançois Tigeot (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) | 163926deccbSFrançois Tigeot NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); 164926deccbSFrançois Tigeot /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 165926deccbSFrançois Tigeot WREG32(0x6940 + radeon_crtc->crtc_offset, 0); 16657e252bfSMichael Neumann if (ASIC_IS_DCE8(rdev)) { 16757e252bfSMichael Neumann /* XXX this only needs to be programmed once per crtc at startup, 16857e252bfSMichael Neumann * not sure where the best place for it is 16957e252bfSMichael Neumann */ 17057e252bfSMichael Neumann WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset, 17157e252bfSMichael Neumann CIK_CURSOR_ALPHA_BLND_ENA); 17257e252bfSMichael Neumann } 173926deccbSFrançois Tigeot } 174926deccbSFrançois Tigeot 175926deccbSFrançois Tigeot static void legacy_crtc_load_lut(struct drm_crtc *crtc) 176926deccbSFrançois Tigeot { 177926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 178926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev; 179926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 180926deccbSFrançois Tigeot int i; 181926deccbSFrançois Tigeot uint32_t dac2_cntl; 182926deccbSFrançois Tigeot 183926deccbSFrançois Tigeot dac2_cntl = RREG32(RADEON_DAC_CNTL2); 184926deccbSFrançois Tigeot if (radeon_crtc->crtc_id == 0) 185926deccbSFrançois Tigeot dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; 186926deccbSFrançois Tigeot else 187926deccbSFrançois Tigeot dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; 188926deccbSFrançois Tigeot WREG32(RADEON_DAC_CNTL2, dac2_cntl); 189926deccbSFrançois Tigeot 190926deccbSFrançois Tigeot WREG8(RADEON_PALETTE_INDEX, 0); 191926deccbSFrançois Tigeot for (i = 0; i < 256; i++) { 192926deccbSFrançois Tigeot WREG32(RADEON_PALETTE_30_DATA, 193926deccbSFrançois Tigeot (radeon_crtc->lut_r[i] << 20) | 194926deccbSFrançois Tigeot (radeon_crtc->lut_g[i] << 10) | 195926deccbSFrançois Tigeot (radeon_crtc->lut_b[i] << 0)); 196926deccbSFrançois Tigeot } 197926deccbSFrançois Tigeot } 198926deccbSFrançois Tigeot 199926deccbSFrançois Tigeot void radeon_crtc_load_lut(struct drm_crtc *crtc) 200926deccbSFrançois Tigeot { 201926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev; 202926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 203926deccbSFrançois Tigeot 204926deccbSFrançois Tigeot if (!crtc->enabled) 205926deccbSFrançois Tigeot return; 206926deccbSFrançois Tigeot 207926deccbSFrançois Tigeot if (ASIC_IS_DCE5(rdev)) 208926deccbSFrançois Tigeot dce5_crtc_load_lut(crtc); 209926deccbSFrançois Tigeot else if (ASIC_IS_DCE4(rdev)) 210926deccbSFrançois Tigeot dce4_crtc_load_lut(crtc); 211926deccbSFrançois Tigeot else if (ASIC_IS_AVIVO(rdev)) 212926deccbSFrançois Tigeot avivo_crtc_load_lut(crtc); 213926deccbSFrançois Tigeot else 214926deccbSFrançois Tigeot legacy_crtc_load_lut(crtc); 215926deccbSFrançois Tigeot } 216926deccbSFrançois Tigeot 217926deccbSFrançois Tigeot /** Sets the color ramps on behalf of fbcon */ 218926deccbSFrançois Tigeot void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 219926deccbSFrançois Tigeot u16 blue, int regno) 220926deccbSFrançois Tigeot { 221926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 222926deccbSFrançois Tigeot 223926deccbSFrançois Tigeot radeon_crtc->lut_r[regno] = red >> 6; 224926deccbSFrançois Tigeot radeon_crtc->lut_g[regno] = green >> 6; 225926deccbSFrançois Tigeot radeon_crtc->lut_b[regno] = blue >> 6; 226926deccbSFrançois Tigeot } 227926deccbSFrançois Tigeot 228926deccbSFrançois Tigeot /** Gets the color ramps on behalf of fbcon */ 229926deccbSFrançois Tigeot void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 230926deccbSFrançois Tigeot u16 *blue, int regno) 231926deccbSFrançois Tigeot { 232926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 233926deccbSFrançois Tigeot 234926deccbSFrançois Tigeot *red = radeon_crtc->lut_r[regno] << 6; 235926deccbSFrançois Tigeot *green = radeon_crtc->lut_g[regno] << 6; 236926deccbSFrançois Tigeot *blue = radeon_crtc->lut_b[regno] << 6; 237926deccbSFrançois Tigeot } 238926deccbSFrançois Tigeot 239926deccbSFrançois Tigeot static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 240926deccbSFrançois Tigeot u16 *blue, uint32_t start, uint32_t size) 241926deccbSFrançois Tigeot { 242926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 243926deccbSFrançois Tigeot int end = (start + size > 256) ? 256 : start + size, i; 244926deccbSFrançois Tigeot 245926deccbSFrançois Tigeot /* userspace palettes are always correct as is */ 246926deccbSFrançois Tigeot for (i = start; i < end; i++) { 247926deccbSFrançois Tigeot radeon_crtc->lut_r[i] = red[i] >> 6; 248926deccbSFrançois Tigeot radeon_crtc->lut_g[i] = green[i] >> 6; 249926deccbSFrançois Tigeot radeon_crtc->lut_b[i] = blue[i] >> 6; 250926deccbSFrançois Tigeot } 251926deccbSFrançois Tigeot radeon_crtc_load_lut(crtc); 252926deccbSFrançois Tigeot } 253926deccbSFrançois Tigeot 254926deccbSFrançois Tigeot static void radeon_crtc_destroy(struct drm_crtc *crtc) 255926deccbSFrançois Tigeot { 256926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 257926deccbSFrançois Tigeot 258926deccbSFrançois Tigeot drm_crtc_cleanup(crtc); 259c6f73aabSFrançois Tigeot destroy_workqueue(radeon_crtc->flip_queue); 260c4ef309bSzrj kfree(radeon_crtc); 261926deccbSFrançois Tigeot } 262926deccbSFrançois Tigeot 263c6f73aabSFrançois Tigeot /** 264c6f73aabSFrançois Tigeot * radeon_unpin_work_func - unpin old buffer object 265c6f73aabSFrançois Tigeot * 266c6f73aabSFrançois Tigeot * @__work - kernel work item 267c6f73aabSFrançois Tigeot * 268c6f73aabSFrançois Tigeot * Unpin the old frame buffer object outside of the interrupt handler 269926deccbSFrançois Tigeot */ 270c6f73aabSFrançois Tigeot static void radeon_unpin_work_func(struct work_struct *__work) 271926deccbSFrançois Tigeot { 272c6f73aabSFrançois Tigeot struct radeon_flip_work *work = 273c6f73aabSFrançois Tigeot container_of(__work, struct radeon_flip_work, unpin_work); 274926deccbSFrançois Tigeot int r; 275926deccbSFrançois Tigeot 276926deccbSFrançois Tigeot /* unpin of the old buffer */ 277926deccbSFrançois Tigeot r = radeon_bo_reserve(work->old_rbo, false); 278926deccbSFrançois Tigeot if (likely(r == 0)) { 279926deccbSFrançois Tigeot r = radeon_bo_unpin(work->old_rbo); 280926deccbSFrançois Tigeot if (unlikely(r != 0)) { 281926deccbSFrançois Tigeot DRM_ERROR("failed to unpin buffer after flip\n"); 282926deccbSFrançois Tigeot } 283926deccbSFrançois Tigeot radeon_bo_unreserve(work->old_rbo); 284926deccbSFrançois Tigeot } else 285926deccbSFrançois Tigeot DRM_ERROR("failed to reserve buffer after flip\n"); 286926deccbSFrançois Tigeot 287926deccbSFrançois Tigeot drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 288c4ef309bSzrj kfree(work); 289926deccbSFrançois Tigeot } 290926deccbSFrançois Tigeot 291c6f73aabSFrançois Tigeot void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id) 292926deccbSFrançois Tigeot { 293926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 294926deccbSFrançois Tigeot u32 update_pending; 295926deccbSFrançois Tigeot int vpos, hpos; 296926deccbSFrançois Tigeot 297c6f73aabSFrançois Tigeot /* can happen during initialization */ 298c6f73aabSFrançois Tigeot if (radeon_crtc == NULL) 299c6f73aabSFrançois Tigeot return; 300c6f73aabSFrançois Tigeot 301c6f73aabSFrançois Tigeot /* Skip the pageflip completion check below (based on polling) on 302c6f73aabSFrançois Tigeot * asics which reliably support hw pageflip completion irqs. pflip 303c6f73aabSFrançois Tigeot * irqs are a reliable and race-free method of handling pageflip 304c6f73aabSFrançois Tigeot * completion detection. A use_pflipirq module parameter < 2 allows 305c6f73aabSFrançois Tigeot * to override this in case of asics with faulty pflip irqs. 306c6f73aabSFrançois Tigeot * A module parameter of 0 would only use this polling based path, 307c6f73aabSFrançois Tigeot * a parameter of 1 would use pflip irq only as a backup to this 308c6f73aabSFrançois Tigeot * path, as in Linux 3.16. 309c6f73aabSFrançois Tigeot */ 310c6f73aabSFrançois Tigeot if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev)) 311c6f73aabSFrançois Tigeot return; 312c6f73aabSFrançois Tigeot 313926deccbSFrançois Tigeot lockmgr(&rdev->ddev->event_lock, LK_EXCLUSIVE); 314c6f73aabSFrançois Tigeot if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 315c6f73aabSFrançois Tigeot DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 316c6f73aabSFrançois Tigeot "RADEON_FLIP_SUBMITTED(%d)\n", 317c6f73aabSFrançois Tigeot radeon_crtc->flip_status, 318c6f73aabSFrançois Tigeot RADEON_FLIP_SUBMITTED); 319926deccbSFrançois Tigeot lockmgr(&rdev->ddev->event_lock, LK_RELEASE); 320926deccbSFrançois Tigeot return; 321926deccbSFrançois Tigeot } 322c6f73aabSFrançois Tigeot 323c6f73aabSFrançois Tigeot update_pending = radeon_page_flip_pending(rdev, crtc_id); 324926deccbSFrançois Tigeot 325926deccbSFrançois Tigeot /* Has the pageflip already completed in crtc, or is it certain 326926deccbSFrançois Tigeot * to complete in this vblank? 327926deccbSFrançois Tigeot */ 328926deccbSFrançois Tigeot if (update_pending && 329782e40d3SFrançois Tigeot (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0, 330352ff8bdSFrançois Tigeot &vpos, &hpos, NULL, NULL, 331352ff8bdSFrançois Tigeot &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) && 332926deccbSFrançois Tigeot ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) || 333926deccbSFrançois Tigeot (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) { 334926deccbSFrançois Tigeot /* crtc didn't flip in this target vblank interval, 335926deccbSFrançois Tigeot * but flip is pending in crtc. Based on the current 336926deccbSFrançois Tigeot * scanout position we know that the current frame is 337926deccbSFrançois Tigeot * (nearly) complete and the flip will (likely) 338926deccbSFrançois Tigeot * complete before the start of the next frame. 339926deccbSFrançois Tigeot */ 340926deccbSFrançois Tigeot update_pending = 0; 341926deccbSFrançois Tigeot } 342c6f73aabSFrançois Tigeot lockmgr(&rdev->ddev->event_lock, LK_RELEASE); 343c6f73aabSFrançois Tigeot if (!update_pending) 344c6f73aabSFrançois Tigeot radeon_crtc_handle_flip(rdev, crtc_id); 345c6f73aabSFrançois Tigeot } 346c6f73aabSFrançois Tigeot 347c6f73aabSFrançois Tigeot /** 348c6f73aabSFrançois Tigeot * radeon_crtc_handle_flip - page flip completed 349c6f73aabSFrançois Tigeot * 350c6f73aabSFrançois Tigeot * @rdev: radeon device pointer 351c6f73aabSFrançois Tigeot * @crtc_id: crtc number this event is for 352c6f73aabSFrançois Tigeot * 353c6f73aabSFrançois Tigeot * Called when we are sure that a page flip for this crtc is completed. 354926deccbSFrançois Tigeot */ 355c6f73aabSFrançois Tigeot void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) 356c6f73aabSFrançois Tigeot { 357c6f73aabSFrançois Tigeot struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 358c6f73aabSFrançois Tigeot struct radeon_flip_work *work; 359c6f73aabSFrançois Tigeot 360c6f73aabSFrançois Tigeot /* this can happen at init */ 361c6f73aabSFrançois Tigeot if (radeon_crtc == NULL) 362c6f73aabSFrançois Tigeot return; 363c6f73aabSFrançois Tigeot 364c6f73aabSFrançois Tigeot lockmgr(&rdev->ddev->event_lock, LK_EXCLUSIVE); 365c6f73aabSFrançois Tigeot work = radeon_crtc->flip_work; 366c6f73aabSFrançois Tigeot if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 367c6f73aabSFrançois Tigeot DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 368c6f73aabSFrançois Tigeot "RADEON_FLIP_SUBMITTED(%d)\n", 369c6f73aabSFrançois Tigeot radeon_crtc->flip_status, 370c6f73aabSFrançois Tigeot RADEON_FLIP_SUBMITTED); 371926deccbSFrançois Tigeot lockmgr(&rdev->ddev->event_lock, LK_RELEASE); 372926deccbSFrançois Tigeot return; 373926deccbSFrançois Tigeot } 374926deccbSFrançois Tigeot 375c6f73aabSFrançois Tigeot /* Pageflip completed. Clean up. */ 376c6f73aabSFrançois Tigeot radeon_crtc->flip_status = RADEON_FLIP_NONE; 377c6f73aabSFrançois Tigeot radeon_crtc->flip_work = NULL; 378926deccbSFrançois Tigeot 379926deccbSFrançois Tigeot /* wakeup userspace */ 380f43cf1b1SMichael Neumann if (work->event) 381f43cf1b1SMichael Neumann drm_send_vblank_event(rdev->ddev, crtc_id, work->event); 382f43cf1b1SMichael Neumann 383926deccbSFrançois Tigeot lockmgr(&rdev->ddev->event_lock, LK_RELEASE); 384926deccbSFrançois Tigeot 385926deccbSFrançois Tigeot drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id); 386c6f73aabSFrançois Tigeot radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id); 387c6f73aabSFrançois Tigeot queue_work(radeon_crtc->flip_queue, &work->unpin_work); 388c6f73aabSFrançois Tigeot } 389c6f73aabSFrançois Tigeot 390c6f73aabSFrançois Tigeot /** 391c6f73aabSFrançois Tigeot * radeon_flip_work_func - page flip framebuffer 392c6f73aabSFrançois Tigeot * 393c6f73aabSFrançois Tigeot * @work - kernel work item 394c6f73aabSFrançois Tigeot * 395c6f73aabSFrançois Tigeot * Wait for the buffer object to become idle and do the actual page flip 396c6f73aabSFrançois Tigeot */ 397c6f73aabSFrançois Tigeot static void radeon_flip_work_func(struct work_struct *__work) 398c6f73aabSFrançois Tigeot { 399c6f73aabSFrançois Tigeot struct radeon_flip_work *work = 400c6f73aabSFrançois Tigeot container_of(__work, struct radeon_flip_work, flip_work); 401c6f73aabSFrançois Tigeot struct radeon_device *rdev = work->rdev; 402c6f73aabSFrançois Tigeot struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id]; 403c6f73aabSFrançois Tigeot 404c6f73aabSFrançois Tigeot struct drm_crtc *crtc = &radeon_crtc->base; 405c6f73aabSFrançois Tigeot int r; 406c6f73aabSFrançois Tigeot 407c6f73aabSFrançois Tigeot lockmgr(&rdev->exclusive_lock, LK_EXCLUSIVE); 408c6f73aabSFrançois Tigeot if (work->fence) { 409c6f73aabSFrançois Tigeot r = radeon_fence_wait(work->fence, false); 410c6f73aabSFrançois Tigeot if (r == -EDEADLK) { 411c6f73aabSFrançois Tigeot lockmgr(&rdev->exclusive_lock, LK_RELEASE); 412591d5043SFrançois Tigeot do { 413c6f73aabSFrançois Tigeot r = radeon_gpu_reset(rdev); 414591d5043SFrançois Tigeot } while (r == -EAGAIN); 415c6f73aabSFrançois Tigeot lockmgr(&rdev->exclusive_lock, LK_EXCLUSIVE); 416c6f73aabSFrançois Tigeot } 417c6f73aabSFrançois Tigeot if (r) 418c6f73aabSFrançois Tigeot DRM_ERROR("failed to wait on page flip fence (%d)!\n", r); 419c6f73aabSFrançois Tigeot 420c6f73aabSFrançois Tigeot /* We continue with the page flip even if we failed to wait on 421c6f73aabSFrançois Tigeot * the fence, otherwise the DRM core and userspace will be 422c6f73aabSFrançois Tigeot * confused about which BO the CRTC is scanning out 423c6f73aabSFrançois Tigeot */ 424c6f73aabSFrançois Tigeot 425926deccbSFrançois Tigeot radeon_fence_unref(&work->fence); 426c6f73aabSFrançois Tigeot } 427c6f73aabSFrançois Tigeot 428c6f73aabSFrançois Tigeot /* We borrow the event spin lock for protecting flip_status */ 429c6f73aabSFrançois Tigeot lockmgr(&crtc->dev->event_lock, LK_EXCLUSIVE); 430c6f73aabSFrançois Tigeot 431c6f73aabSFrançois Tigeot /* set the proper interrupt */ 432c6f73aabSFrançois Tigeot radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id); 433c6f73aabSFrançois Tigeot 434c6f73aabSFrançois Tigeot /* do the flip (mmio) */ 435c6f73aabSFrançois Tigeot radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base); 436c6f73aabSFrançois Tigeot 437c6f73aabSFrançois Tigeot radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED; 438c6f73aabSFrançois Tigeot lockmgr(&crtc->dev->event_lock, LK_RELEASE); 439c6f73aabSFrançois Tigeot lockmgr(&rdev->exclusive_lock, LK_RELEASE); 440926deccbSFrançois Tigeot } 441926deccbSFrançois Tigeot 442926deccbSFrançois Tigeot static int radeon_crtc_page_flip(struct drm_crtc *crtc, 443926deccbSFrançois Tigeot struct drm_framebuffer *fb, 4449edbd4a0SFrançois Tigeot struct drm_pending_vblank_event *event, 4459edbd4a0SFrançois Tigeot uint32_t page_flip_flags) 446926deccbSFrançois Tigeot { 447926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev; 448926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 449926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 450926deccbSFrançois Tigeot struct radeon_framebuffer *old_radeon_fb; 451926deccbSFrançois Tigeot struct radeon_framebuffer *new_radeon_fb; 452926deccbSFrançois Tigeot struct drm_gem_object *obj; 453c6f73aabSFrançois Tigeot struct radeon_flip_work *work; 454c6f73aabSFrançois Tigeot struct radeon_bo *new_rbo; 455c6f73aabSFrançois Tigeot uint32_t tiling_flags, pitch_pixels; 456c6f73aabSFrançois Tigeot uint64_t base; 457926deccbSFrançois Tigeot int r; 458926deccbSFrançois Tigeot 459c4ef309bSzrj work = kzalloc(sizeof *work, GFP_KERNEL); 460926deccbSFrançois Tigeot if (work == NULL) 461926deccbSFrançois Tigeot return -ENOMEM; 462926deccbSFrançois Tigeot 463c6f73aabSFrançois Tigeot INIT_WORK(&work->flip_work, radeon_flip_work_func); 464c6f73aabSFrançois Tigeot INIT_WORK(&work->unpin_work, radeon_unpin_work_func); 465c6f73aabSFrançois Tigeot 466926deccbSFrançois Tigeot work->rdev = rdev; 467926deccbSFrançois Tigeot work->crtc_id = radeon_crtc->crtc_id; 468c6f73aabSFrançois Tigeot work->event = event; 469c6f73aabSFrançois Tigeot 470926deccbSFrançois Tigeot /* schedule unpin of the old buffer */ 471c6f73aabSFrançois Tigeot old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb); 472926deccbSFrançois Tigeot obj = old_radeon_fb->obj; 473c6f73aabSFrançois Tigeot 474926deccbSFrançois Tigeot /* take a reference to the old object */ 475926deccbSFrançois Tigeot drm_gem_object_reference(obj); 476c6f73aabSFrançois Tigeot work->old_rbo = gem_to_radeon_bo(obj); 477c6f73aabSFrançois Tigeot 478c6f73aabSFrançois Tigeot new_radeon_fb = to_radeon_framebuffer(fb); 479926deccbSFrançois Tigeot obj = new_radeon_fb->obj; 480c6f73aabSFrançois Tigeot new_rbo = gem_to_radeon_bo(obj); 481926deccbSFrançois Tigeot 482c6f73aabSFrançois Tigeot lockmgr(&new_rbo->tbo.bdev->fence_lock, LK_EXCLUSIVE); 483c6f73aabSFrançois Tigeot if (new_rbo->tbo.sync_obj) 484c6f73aabSFrançois Tigeot work->fence = radeon_fence_ref(new_rbo->tbo.sync_obj); 485c6f73aabSFrançois Tigeot lockmgr(&new_rbo->tbo.bdev->fence_lock, LK_RELEASE); 486926deccbSFrançois Tigeot 487926deccbSFrançois Tigeot /* pin the new buffer */ 488c6f73aabSFrançois Tigeot DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n", 489c6f73aabSFrançois Tigeot work->old_rbo, new_rbo); 490926deccbSFrançois Tigeot 491c6f73aabSFrançois Tigeot r = radeon_bo_reserve(new_rbo, false); 492926deccbSFrançois Tigeot if (unlikely(r != 0)) { 493926deccbSFrançois Tigeot DRM_ERROR("failed to reserve new rbo buffer before flip\n"); 494c6f73aabSFrançois Tigeot goto cleanup; 495926deccbSFrançois Tigeot } 496926deccbSFrançois Tigeot /* Only 27 bit offset for legacy CRTC */ 497c6f73aabSFrançois Tigeot r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM, 498926deccbSFrançois Tigeot ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base); 499926deccbSFrançois Tigeot if (unlikely(r != 0)) { 500c6f73aabSFrançois Tigeot radeon_bo_unreserve(new_rbo); 501926deccbSFrançois Tigeot r = -EINVAL; 502926deccbSFrançois Tigeot DRM_ERROR("failed to pin new rbo buffer before flip\n"); 503c6f73aabSFrançois Tigeot goto cleanup; 504926deccbSFrançois Tigeot } 505c6f73aabSFrançois Tigeot radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); 506c6f73aabSFrançois Tigeot radeon_bo_unreserve(new_rbo); 507926deccbSFrançois Tigeot 508926deccbSFrançois Tigeot if (!ASIC_IS_AVIVO(rdev)) { 509926deccbSFrançois Tigeot /* crtc offset is from display base addr not FB location */ 510926deccbSFrançois Tigeot base -= radeon_crtc->legacy_display_base_addr; 511926deccbSFrançois Tigeot pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8); 512926deccbSFrançois Tigeot 513926deccbSFrançois Tigeot if (tiling_flags & RADEON_TILING_MACRO) { 514926deccbSFrançois Tigeot if (ASIC_IS_R300(rdev)) { 515926deccbSFrançois Tigeot base &= ~0x7ff; 516926deccbSFrançois Tigeot } else { 517926deccbSFrançois Tigeot int byteshift = fb->bits_per_pixel >> 4; 518926deccbSFrançois Tigeot int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11; 519926deccbSFrançois Tigeot base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8); 520926deccbSFrançois Tigeot } 521926deccbSFrançois Tigeot } else { 522926deccbSFrançois Tigeot int offset = crtc->y * pitch_pixels + crtc->x; 523926deccbSFrançois Tigeot switch (fb->bits_per_pixel) { 524926deccbSFrançois Tigeot case 8: 525926deccbSFrançois Tigeot default: 526926deccbSFrançois Tigeot offset *= 1; 527926deccbSFrançois Tigeot break; 528926deccbSFrançois Tigeot case 15: 529926deccbSFrançois Tigeot case 16: 530926deccbSFrançois Tigeot offset *= 2; 531926deccbSFrançois Tigeot break; 532926deccbSFrançois Tigeot case 24: 533926deccbSFrançois Tigeot offset *= 3; 534926deccbSFrançois Tigeot break; 535926deccbSFrançois Tigeot case 32: 536926deccbSFrançois Tigeot offset *= 4; 537926deccbSFrançois Tigeot break; 538926deccbSFrançois Tigeot } 539926deccbSFrançois Tigeot base += offset; 540926deccbSFrançois Tigeot } 541926deccbSFrançois Tigeot base &= ~7; 542926deccbSFrançois Tigeot } 543c6f73aabSFrançois Tigeot work->base = base; 544926deccbSFrançois Tigeot 545c6f73aabSFrançois Tigeot r = drm_vblank_get(crtc->dev, radeon_crtc->crtc_id); 546c6f73aabSFrançois Tigeot if (r) { 547c6f73aabSFrançois Tigeot DRM_ERROR("failed to get vblank before flip\n"); 548c6f73aabSFrançois Tigeot goto pflip_cleanup; 549c6f73aabSFrançois Tigeot } 550c6f73aabSFrançois Tigeot 551c6f73aabSFrançois Tigeot /* We borrow the event spin lock for protecting flip_work */ 552c6f73aabSFrançois Tigeot lockmgr(&crtc->dev->event_lock, LK_EXCLUSIVE); 553c6f73aabSFrançois Tigeot 554c6f73aabSFrançois Tigeot if (radeon_crtc->flip_status != RADEON_FLIP_NONE) { 555c6f73aabSFrançois Tigeot DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 556c6f73aabSFrançois Tigeot lockmgr(&crtc->dev->event_lock, LK_RELEASE); 557c6f73aabSFrançois Tigeot r = -EBUSY; 558c6f73aabSFrançois Tigeot goto vblank_cleanup; 559c6f73aabSFrançois Tigeot } 560c6f73aabSFrançois Tigeot radeon_crtc->flip_status = RADEON_FLIP_PENDING; 561c6f73aabSFrançois Tigeot radeon_crtc->flip_work = work; 562926deccbSFrançois Tigeot 563926deccbSFrançois Tigeot /* update crtc fb */ 564ba55f2f5SFrançois Tigeot crtc->primary->fb = fb; 565926deccbSFrançois Tigeot 566c6f73aabSFrançois Tigeot lockmgr(&crtc->dev->event_lock, LK_RELEASE); 567926deccbSFrançois Tigeot 568c6f73aabSFrançois Tigeot queue_work(radeon_crtc->flip_queue, &work->flip_work); 569926deccbSFrançois Tigeot return 0; 570926deccbSFrançois Tigeot 571c6f73aabSFrançois Tigeot vblank_cleanup: 572c6f73aabSFrançois Tigeot drm_vblank_put(crtc->dev, radeon_crtc->crtc_id); 573926deccbSFrançois Tigeot 574926deccbSFrançois Tigeot pflip_cleanup: 575c6f73aabSFrançois Tigeot if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) { 576c6f73aabSFrançois Tigeot DRM_ERROR("failed to reserve new rbo in error path\n"); 577c6f73aabSFrançois Tigeot goto cleanup; 578c6f73aabSFrançois Tigeot } 579c6f73aabSFrançois Tigeot if (unlikely(radeon_bo_unpin(new_rbo) != 0)) { 580c6f73aabSFrançois Tigeot DRM_ERROR("failed to unpin new rbo in error path\n"); 581c6f73aabSFrançois Tigeot } 582c6f73aabSFrançois Tigeot radeon_bo_unreserve(new_rbo); 583c6f73aabSFrançois Tigeot 584c6f73aabSFrançois Tigeot cleanup: 585c6f73aabSFrançois Tigeot drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 586926deccbSFrançois Tigeot radeon_fence_unref(&work->fence); 587c4ef309bSzrj kfree(work); 588926deccbSFrançois Tigeot 589926deccbSFrançois Tigeot return r; 590926deccbSFrançois Tigeot } 591926deccbSFrançois Tigeot 592c6f73aabSFrançois Tigeot static int 593c6f73aabSFrançois Tigeot radeon_crtc_set_config(struct drm_mode_set *set) 594c6f73aabSFrançois Tigeot { 595c6f73aabSFrançois Tigeot struct drm_device *dev; 596c6f73aabSFrançois Tigeot struct radeon_device *rdev; 597c6f73aabSFrançois Tigeot struct drm_crtc *crtc; 598c6f73aabSFrançois Tigeot bool active = false; 599c6f73aabSFrançois Tigeot int ret; 600c6f73aabSFrançois Tigeot 601c6f73aabSFrançois Tigeot if (!set || !set->crtc) 602c6f73aabSFrançois Tigeot return -EINVAL; 603c6f73aabSFrançois Tigeot 604c6f73aabSFrançois Tigeot dev = set->crtc->dev; 605c6f73aabSFrançois Tigeot 606c6f73aabSFrançois Tigeot #ifdef PM_TODO 607c6f73aabSFrançois Tigeot ret = pm_runtime_get_sync(dev->dev); 608c6f73aabSFrançois Tigeot if (ret < 0) 609c6f73aabSFrançois Tigeot return ret; 610c6f73aabSFrançois Tigeot #endif 611c6f73aabSFrançois Tigeot 612c6f73aabSFrançois Tigeot ret = drm_crtc_helper_set_config(set); 613c6f73aabSFrançois Tigeot 614c6f73aabSFrançois Tigeot list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 615c6f73aabSFrançois Tigeot if (crtc->enabled) 616c6f73aabSFrançois Tigeot active = true; 617c6f73aabSFrançois Tigeot 618c6f73aabSFrançois Tigeot #ifdef PM_TODO 619c6f73aabSFrançois Tigeot pm_runtime_mark_last_busy(dev->dev); 620c6f73aabSFrançois Tigeot #endif 621c6f73aabSFrançois Tigeot 622c6f73aabSFrançois Tigeot rdev = dev->dev_private; 623c6f73aabSFrançois Tigeot /* if we have active crtcs and we don't have a power ref, 624c6f73aabSFrançois Tigeot take the current one */ 625c6f73aabSFrançois Tigeot if (active && !rdev->have_disp_power_ref) { 626c6f73aabSFrançois Tigeot rdev->have_disp_power_ref = true; 627c6f73aabSFrançois Tigeot return ret; 628c6f73aabSFrançois Tigeot } 629c6f73aabSFrançois Tigeot /* if we have no active crtcs, then drop the power ref 630c6f73aabSFrançois Tigeot we got before */ 631c6f73aabSFrançois Tigeot if (!active && rdev->have_disp_power_ref) { 632c6f73aabSFrançois Tigeot #ifdef PM_TODO 633c6f73aabSFrançois Tigeot pm_runtime_put_autosuspend(dev->dev); 634c6f73aabSFrançois Tigeot #endif 635c6f73aabSFrançois Tigeot rdev->have_disp_power_ref = false; 636c6f73aabSFrançois Tigeot } 637c6f73aabSFrançois Tigeot 638c6f73aabSFrançois Tigeot /* drop the power reference we got coming in here */ 639c6f73aabSFrançois Tigeot #ifdef PM_TODO 640c6f73aabSFrançois Tigeot pm_runtime_put_autosuspend(dev->dev); 641c6f73aabSFrançois Tigeot #endif 642c6f73aabSFrançois Tigeot return ret; 643c6f73aabSFrançois Tigeot } 644926deccbSFrançois Tigeot static const struct drm_crtc_funcs radeon_crtc_funcs = { 645926deccbSFrançois Tigeot .cursor_set = radeon_crtc_cursor_set, 646926deccbSFrançois Tigeot .cursor_move = radeon_crtc_cursor_move, 647926deccbSFrançois Tigeot .gamma_set = radeon_crtc_gamma_set, 648c6f73aabSFrançois Tigeot .set_config = radeon_crtc_set_config, 649926deccbSFrançois Tigeot .destroy = radeon_crtc_destroy, 650926deccbSFrançois Tigeot .page_flip = radeon_crtc_page_flip, 651926deccbSFrançois Tigeot }; 652926deccbSFrançois Tigeot 653926deccbSFrançois Tigeot static void radeon_crtc_init(struct drm_device *dev, int index) 654926deccbSFrançois Tigeot { 655926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 656926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc; 657926deccbSFrançois Tigeot int i; 658926deccbSFrançois Tigeot 659c4ef309bSzrj radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 660926deccbSFrançois Tigeot if (radeon_crtc == NULL) 661926deccbSFrançois Tigeot return; 662926deccbSFrançois Tigeot 663926deccbSFrançois Tigeot drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); 664926deccbSFrançois Tigeot 665926deccbSFrançois Tigeot drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); 666926deccbSFrançois Tigeot radeon_crtc->crtc_id = index; 667c6f73aabSFrançois Tigeot radeon_crtc->flip_queue = create_singlethread_workqueue("radeon-crtc"); 668926deccbSFrançois Tigeot rdev->mode_info.crtcs[index] = radeon_crtc; 669926deccbSFrançois Tigeot 67057e252bfSMichael Neumann if (rdev->family >= CHIP_BONAIRE) { 67157e252bfSMichael Neumann radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH; 67257e252bfSMichael Neumann radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT; 67357e252bfSMichael Neumann } else { 67457e252bfSMichael Neumann radeon_crtc->max_cursor_width = CURSOR_WIDTH; 67557e252bfSMichael Neumann radeon_crtc->max_cursor_height = CURSOR_HEIGHT; 67657e252bfSMichael Neumann } 677c6f73aabSFrançois Tigeot dev->mode_config.cursor_width = radeon_crtc->max_cursor_width; 678c6f73aabSFrançois Tigeot dev->mode_config.cursor_height = radeon_crtc->max_cursor_height; 67957e252bfSMichael Neumann 680926deccbSFrançois Tigeot #if 0 681926deccbSFrançois Tigeot radeon_crtc->mode_set.crtc = &radeon_crtc->base; 682926deccbSFrançois Tigeot radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); 683926deccbSFrançois Tigeot radeon_crtc->mode_set.num_connectors = 0; 684926deccbSFrançois Tigeot #endif 685926deccbSFrançois Tigeot 686926deccbSFrançois Tigeot for (i = 0; i < 256; i++) { 687926deccbSFrançois Tigeot radeon_crtc->lut_r[i] = i << 2; 688926deccbSFrançois Tigeot radeon_crtc->lut_g[i] = i << 2; 689926deccbSFrançois Tigeot radeon_crtc->lut_b[i] = i << 2; 690926deccbSFrançois Tigeot } 691926deccbSFrançois Tigeot 692926deccbSFrançois Tigeot if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) 693926deccbSFrançois Tigeot radeon_atombios_init_crtc(dev, radeon_crtc); 694926deccbSFrançois Tigeot else 695926deccbSFrançois Tigeot radeon_legacy_init_crtc(dev, radeon_crtc); 696926deccbSFrançois Tigeot } 697926deccbSFrançois Tigeot 69857e252bfSMichael Neumann static const char *encoder_names[38] = { 699926deccbSFrançois Tigeot "NONE", 700926deccbSFrançois Tigeot "INTERNAL_LVDS", 701926deccbSFrançois Tigeot "INTERNAL_TMDS1", 702926deccbSFrançois Tigeot "INTERNAL_TMDS2", 703926deccbSFrançois Tigeot "INTERNAL_DAC1", 704926deccbSFrançois Tigeot "INTERNAL_DAC2", 705926deccbSFrançois Tigeot "INTERNAL_SDVOA", 706926deccbSFrançois Tigeot "INTERNAL_SDVOB", 707926deccbSFrançois Tigeot "SI170B", 708926deccbSFrançois Tigeot "CH7303", 709926deccbSFrançois Tigeot "CH7301", 710926deccbSFrançois Tigeot "INTERNAL_DVO1", 711926deccbSFrançois Tigeot "EXTERNAL_SDVOA", 712926deccbSFrançois Tigeot "EXTERNAL_SDVOB", 713926deccbSFrançois Tigeot "TITFP513", 714926deccbSFrançois Tigeot "INTERNAL_LVTM1", 715926deccbSFrançois Tigeot "VT1623", 716926deccbSFrançois Tigeot "HDMI_SI1930", 717926deccbSFrançois Tigeot "HDMI_INTERNAL", 718926deccbSFrançois Tigeot "INTERNAL_KLDSCP_TMDS1", 719926deccbSFrançois Tigeot "INTERNAL_KLDSCP_DVO1", 720926deccbSFrançois Tigeot "INTERNAL_KLDSCP_DAC1", 721926deccbSFrançois Tigeot "INTERNAL_KLDSCP_DAC2", 722926deccbSFrançois Tigeot "SI178", 723926deccbSFrançois Tigeot "MVPU_FPGA", 724926deccbSFrançois Tigeot "INTERNAL_DDI", 725926deccbSFrançois Tigeot "VT1625", 726926deccbSFrançois Tigeot "HDMI_SI1932", 727926deccbSFrançois Tigeot "DP_AN9801", 728926deccbSFrançois Tigeot "DP_DP501", 729926deccbSFrançois Tigeot "INTERNAL_UNIPHY", 730926deccbSFrançois Tigeot "INTERNAL_KLDSCP_LVTMA", 731926deccbSFrançois Tigeot "INTERNAL_UNIPHY1", 732926deccbSFrançois Tigeot "INTERNAL_UNIPHY2", 733926deccbSFrançois Tigeot "NUTMEG", 734926deccbSFrançois Tigeot "TRAVIS", 73557e252bfSMichael Neumann "INTERNAL_VCE", 73657e252bfSMichael Neumann "INTERNAL_UNIPHY3", 737926deccbSFrançois Tigeot }; 738926deccbSFrançois Tigeot 739926deccbSFrançois Tigeot static const char *hpd_names[6] = { 740926deccbSFrançois Tigeot "HPD1", 741926deccbSFrançois Tigeot "HPD2", 742926deccbSFrançois Tigeot "HPD3", 743926deccbSFrançois Tigeot "HPD4", 744926deccbSFrançois Tigeot "HPD5", 745926deccbSFrançois Tigeot "HPD6", 746926deccbSFrançois Tigeot }; 747926deccbSFrançois Tigeot 748926deccbSFrançois Tigeot static void radeon_print_display_setup(struct drm_device *dev) 749926deccbSFrançois Tigeot { 750926deccbSFrançois Tigeot struct drm_connector *connector; 751926deccbSFrançois Tigeot struct radeon_connector *radeon_connector; 752926deccbSFrançois Tigeot struct drm_encoder *encoder; 753926deccbSFrançois Tigeot struct radeon_encoder *radeon_encoder; 754926deccbSFrançois Tigeot uint32_t devices; 755926deccbSFrançois Tigeot int i = 0; 756926deccbSFrançois Tigeot 757926deccbSFrançois Tigeot DRM_INFO("Radeon Display Connectors\n"); 758926deccbSFrançois Tigeot list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 759926deccbSFrançois Tigeot radeon_connector = to_radeon_connector(connector); 760926deccbSFrançois Tigeot DRM_INFO("Connector %d:\n", i); 761ba55f2f5SFrançois Tigeot DRM_INFO(" %s\n", connector->name); 762926deccbSFrançois Tigeot if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 763926deccbSFrançois Tigeot DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); 764926deccbSFrançois Tigeot if (radeon_connector->ddc_bus) { 765926deccbSFrançois Tigeot DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 766926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.mask_clk_reg, 767926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.mask_data_reg, 768926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.a_clk_reg, 769926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.a_data_reg, 770926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.en_clk_reg, 771926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.en_data_reg, 772926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.y_clk_reg, 773926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.y_data_reg); 774926deccbSFrançois Tigeot if (radeon_connector->router.ddc_valid) 775926deccbSFrançois Tigeot DRM_INFO(" DDC Router 0x%x/0x%x\n", 776926deccbSFrançois Tigeot radeon_connector->router.ddc_mux_control_pin, 777926deccbSFrançois Tigeot radeon_connector->router.ddc_mux_state); 778926deccbSFrançois Tigeot if (radeon_connector->router.cd_valid) 779926deccbSFrançois Tigeot DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 780926deccbSFrançois Tigeot radeon_connector->router.cd_mux_control_pin, 781926deccbSFrançois Tigeot radeon_connector->router.cd_mux_state); 782926deccbSFrançois Tigeot } else { 783926deccbSFrançois Tigeot if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 784926deccbSFrançois Tigeot connector->connector_type == DRM_MODE_CONNECTOR_DVII || 785926deccbSFrançois Tigeot connector->connector_type == DRM_MODE_CONNECTOR_DVID || 786926deccbSFrançois Tigeot connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 787926deccbSFrançois Tigeot connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 788926deccbSFrançois Tigeot connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 789926deccbSFrançois Tigeot DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 790926deccbSFrançois Tigeot } 791926deccbSFrançois Tigeot DRM_INFO(" Encoders:\n"); 792926deccbSFrançois Tigeot list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 793926deccbSFrançois Tigeot radeon_encoder = to_radeon_encoder(encoder); 794926deccbSFrançois Tigeot devices = radeon_encoder->devices & radeon_connector->devices; 795926deccbSFrançois Tigeot if (devices) { 796926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_CRT1_SUPPORT) 797926deccbSFrançois Tigeot DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); 798926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_CRT2_SUPPORT) 799926deccbSFrançois Tigeot DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); 800926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_LCD1_SUPPORT) 801926deccbSFrançois Tigeot DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); 802926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP1_SUPPORT) 803926deccbSFrançois Tigeot DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); 804926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP2_SUPPORT) 805926deccbSFrançois Tigeot DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); 806926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP3_SUPPORT) 807926deccbSFrançois Tigeot DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); 808926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP4_SUPPORT) 809926deccbSFrançois Tigeot DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); 810926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP5_SUPPORT) 811926deccbSFrançois Tigeot DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); 812926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP6_SUPPORT) 813926deccbSFrançois Tigeot DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); 814926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_TV1_SUPPORT) 815926deccbSFrançois Tigeot DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); 816926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_CV_SUPPORT) 817926deccbSFrançois Tigeot DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); 818926deccbSFrançois Tigeot } 819926deccbSFrançois Tigeot } 820926deccbSFrançois Tigeot i++; 821926deccbSFrançois Tigeot } 822926deccbSFrançois Tigeot } 823926deccbSFrançois Tigeot 824926deccbSFrançois Tigeot static bool radeon_setup_enc_conn(struct drm_device *dev) 825926deccbSFrançois Tigeot { 826926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 827926deccbSFrançois Tigeot bool ret = false; 828926deccbSFrançois Tigeot 829926deccbSFrançois Tigeot if (rdev->bios) { 830926deccbSFrançois Tigeot if (rdev->is_atom_bios) { 831926deccbSFrançois Tigeot ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); 832926deccbSFrançois Tigeot if (ret == false) 833926deccbSFrançois Tigeot ret = radeon_get_atom_connector_info_from_object_table(dev); 834926deccbSFrançois Tigeot } else { 835926deccbSFrançois Tigeot ret = radeon_get_legacy_connector_info_from_bios(dev); 836926deccbSFrançois Tigeot if (ret == false) 837926deccbSFrançois Tigeot ret = radeon_get_legacy_connector_info_from_table(dev); 838926deccbSFrançois Tigeot } 839926deccbSFrançois Tigeot } else { 840926deccbSFrançois Tigeot if (!ASIC_IS_AVIVO(rdev)) 841926deccbSFrançois Tigeot ret = radeon_get_legacy_connector_info_from_table(dev); 842926deccbSFrançois Tigeot } 843926deccbSFrançois Tigeot if (ret) { 844926deccbSFrançois Tigeot radeon_setup_encoder_clones(dev); 845926deccbSFrançois Tigeot radeon_print_display_setup(dev); 846926deccbSFrançois Tigeot } 847926deccbSFrançois Tigeot 848926deccbSFrançois Tigeot return ret; 849926deccbSFrançois Tigeot } 850926deccbSFrançois Tigeot 851926deccbSFrançois Tigeot /* avivo */ 852c6f73aabSFrançois Tigeot 853c6f73aabSFrançois Tigeot /** 854c6f73aabSFrançois Tigeot * avivo_reduce_ratio - fractional number reduction 855c6f73aabSFrançois Tigeot * 856c6f73aabSFrançois Tigeot * @nom: nominator 857c6f73aabSFrançois Tigeot * @den: denominator 858c6f73aabSFrançois Tigeot * @nom_min: minimum value for nominator 859c6f73aabSFrançois Tigeot * @den_min: minimum value for denominator 860c6f73aabSFrançois Tigeot * 861c6f73aabSFrançois Tigeot * Find the greatest common divisor and apply it on both nominator and 862c6f73aabSFrançois Tigeot * denominator, but make nominator and denominator are at least as large 863c6f73aabSFrançois Tigeot * as their minimum values. 864c6f73aabSFrançois Tigeot */ 865c6f73aabSFrançois Tigeot static void avivo_reduce_ratio(unsigned *nom, unsigned *den, 866c6f73aabSFrançois Tigeot unsigned nom_min, unsigned den_min) 867926deccbSFrançois Tigeot { 868c6f73aabSFrançois Tigeot unsigned tmp; 869926deccbSFrançois Tigeot 870c6f73aabSFrançois Tigeot /* reduce the numbers to a simpler ratio */ 871c6f73aabSFrançois Tigeot tmp = gcd64(*nom, *den); 872c6f73aabSFrançois Tigeot *nom /= tmp; 873c6f73aabSFrançois Tigeot *den /= tmp; 874926deccbSFrançois Tigeot 875c6f73aabSFrançois Tigeot /* make sure nominator is large enough */ 876c6f73aabSFrançois Tigeot if (*nom < nom_min) { 877c6f73aabSFrançois Tigeot tmp = DIV_ROUND_UP(nom_min, *nom); 878c6f73aabSFrançois Tigeot *nom *= tmp; 879c6f73aabSFrançois Tigeot *den *= tmp; 880926deccbSFrançois Tigeot } 881926deccbSFrançois Tigeot 882c6f73aabSFrançois Tigeot /* make sure the denominator is large enough */ 883c6f73aabSFrançois Tigeot if (*den < den_min) { 884c6f73aabSFrançois Tigeot tmp = DIV_ROUND_UP(den_min, *den); 885c6f73aabSFrançois Tigeot *nom *= tmp; 886c6f73aabSFrançois Tigeot *den *= tmp; 887c6f73aabSFrançois Tigeot } 888c6f73aabSFrançois Tigeot } 889c6f73aabSFrançois Tigeot 890c6f73aabSFrançois Tigeot /** 891c6f73aabSFrançois Tigeot * avivo_get_fb_ref_div - feedback and ref divider calculation 892c6f73aabSFrançois Tigeot * 893c6f73aabSFrançois Tigeot * @nom: nominator 894c6f73aabSFrançois Tigeot * @den: denominator 895c6f73aabSFrançois Tigeot * @post_div: post divider 896c6f73aabSFrançois Tigeot * @fb_div_max: feedback divider maximum 897c6f73aabSFrançois Tigeot * @ref_div_max: reference divider maximum 898c6f73aabSFrançois Tigeot * @fb_div: resulting feedback divider 899c6f73aabSFrançois Tigeot * @ref_div: resulting reference divider 900c6f73aabSFrançois Tigeot * 901c6f73aabSFrançois Tigeot * Calculate feedback and reference divider for a given post divider. Makes 902c6f73aabSFrançois Tigeot * sure we stay within the limits. 903c6f73aabSFrançois Tigeot */ 904c6f73aabSFrançois Tigeot static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, 905c6f73aabSFrançois Tigeot unsigned fb_div_max, unsigned ref_div_max, 906c6f73aabSFrançois Tigeot unsigned *fb_div, unsigned *ref_div) 907926deccbSFrançois Tigeot { 908c6f73aabSFrançois Tigeot /* limit reference * post divider to a maximum */ 909c6f73aabSFrançois Tigeot ref_div_max = max(min(100 / post_div, ref_div_max), 1u); 910926deccbSFrançois Tigeot 911c6f73aabSFrançois Tigeot /* get matching reference and feedback divider */ 912c6f73aabSFrançois Tigeot *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); 913c6f73aabSFrançois Tigeot *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); 914926deccbSFrançois Tigeot 915c6f73aabSFrançois Tigeot /* limit fb divider to its maximum */ 916c6f73aabSFrançois Tigeot if (*fb_div > fb_div_max) { 917c6f73aabSFrançois Tigeot *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); 918c6f73aabSFrançois Tigeot *fb_div = fb_div_max; 919c6f73aabSFrançois Tigeot } 920926deccbSFrançois Tigeot } 921926deccbSFrançois Tigeot 922c6f73aabSFrançois Tigeot /** 923c6f73aabSFrançois Tigeot * radeon_compute_pll_avivo - compute PLL paramaters 924c6f73aabSFrançois Tigeot * 925c6f73aabSFrançois Tigeot * @pll: information about the PLL 926c6f73aabSFrançois Tigeot * @dot_clock_p: resulting pixel clock 927c6f73aabSFrançois Tigeot * fb_div_p: resulting feedback divider 928c6f73aabSFrançois Tigeot * frac_fb_div_p: fractional part of the feedback divider 929c6f73aabSFrançois Tigeot * ref_div_p: resulting reference divider 930c6f73aabSFrançois Tigeot * post_div_p: resulting reference divider 931c6f73aabSFrançois Tigeot * 932c6f73aabSFrançois Tigeot * Try to calculate the PLL parameters to generate the given frequency: 933c6f73aabSFrançois Tigeot * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div) 934c6f73aabSFrançois Tigeot */ 935926deccbSFrançois Tigeot void radeon_compute_pll_avivo(struct radeon_pll *pll, 936926deccbSFrançois Tigeot u32 freq, 937926deccbSFrançois Tigeot u32 *dot_clock_p, 938926deccbSFrançois Tigeot u32 *fb_div_p, 939926deccbSFrançois Tigeot u32 *frac_fb_div_p, 940926deccbSFrançois Tigeot u32 *ref_div_p, 941926deccbSFrançois Tigeot u32 *post_div_p) 942926deccbSFrançois Tigeot { 943c6f73aabSFrançois Tigeot unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? 944c6f73aabSFrançois Tigeot freq : freq / 10; 945926deccbSFrançois Tigeot 946c6f73aabSFrançois Tigeot unsigned fb_div_min, fb_div_max, fb_div; 947c6f73aabSFrançois Tigeot unsigned post_div_min, post_div_max, post_div; 948c6f73aabSFrançois Tigeot unsigned ref_div_min, ref_div_max, ref_div; 949c6f73aabSFrançois Tigeot unsigned post_div_best, diff_best; 950c6f73aabSFrançois Tigeot unsigned nom, den; 951c6f73aabSFrançois Tigeot 952c6f73aabSFrançois Tigeot /* determine allowed feedback divider range */ 953c6f73aabSFrançois Tigeot fb_div_min = pll->min_feedback_div; 954c6f73aabSFrançois Tigeot fb_div_max = pll->max_feedback_div; 955926deccbSFrançois Tigeot 956926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 957c6f73aabSFrançois Tigeot fb_div_min *= 10; 958c6f73aabSFrançois Tigeot fb_div_max *= 10; 959926deccbSFrançois Tigeot } 960926deccbSFrançois Tigeot 961c6f73aabSFrançois Tigeot /* determine allowed ref divider range */ 962c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_REF_DIV) 963c6f73aabSFrançois Tigeot ref_div_min = pll->reference_div; 964926deccbSFrançois Tigeot else 965c6f73aabSFrançois Tigeot ref_div_min = pll->min_ref_div; 966c6f73aabSFrançois Tigeot 967c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && 968c6f73aabSFrançois Tigeot pll->flags & RADEON_PLL_USE_REF_DIV) 969c6f73aabSFrançois Tigeot ref_div_max = pll->reference_div; 970c6f73aabSFrançois Tigeot else 971c6f73aabSFrançois Tigeot ref_div_max = pll->max_ref_div; 972c6f73aabSFrançois Tigeot 973c6f73aabSFrançois Tigeot /* determine allowed post divider range */ 974c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_POST_DIV) { 975c6f73aabSFrançois Tigeot post_div_min = pll->post_div; 976c6f73aabSFrançois Tigeot post_div_max = pll->post_div; 977c6f73aabSFrançois Tigeot } else { 978c6f73aabSFrançois Tigeot unsigned vco_min, vco_max; 979c6f73aabSFrançois Tigeot 980c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_IS_LCD) { 981c6f73aabSFrançois Tigeot vco_min = pll->lcd_pll_out_min; 982c6f73aabSFrançois Tigeot vco_max = pll->lcd_pll_out_max; 983c6f73aabSFrançois Tigeot } else { 984c6f73aabSFrançois Tigeot vco_min = pll->pll_out_min; 985c6f73aabSFrançois Tigeot vco_max = pll->pll_out_max; 986c6f73aabSFrançois Tigeot } 987c6f73aabSFrançois Tigeot 988c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 989c6f73aabSFrançois Tigeot vco_min *= 10; 990c6f73aabSFrançois Tigeot vco_max *= 10; 991c6f73aabSFrançois Tigeot } 992c6f73aabSFrançois Tigeot 993c6f73aabSFrançois Tigeot post_div_min = vco_min / target_clock; 994c6f73aabSFrançois Tigeot if ((target_clock * post_div_min) < vco_min) 995c6f73aabSFrançois Tigeot ++post_div_min; 996c6f73aabSFrançois Tigeot if (post_div_min < pll->min_post_div) 997c6f73aabSFrançois Tigeot post_div_min = pll->min_post_div; 998c6f73aabSFrançois Tigeot 999c6f73aabSFrançois Tigeot post_div_max = vco_max / target_clock; 1000c6f73aabSFrançois Tigeot if ((target_clock * post_div_max) > vco_max) 1001c6f73aabSFrançois Tigeot --post_div_max; 1002c6f73aabSFrançois Tigeot if (post_div_max > pll->max_post_div) 1003c6f73aabSFrançois Tigeot post_div_max = pll->max_post_div; 1004c6f73aabSFrançois Tigeot } 1005c6f73aabSFrançois Tigeot 1006c6f73aabSFrançois Tigeot /* represent the searched ratio as fractional number */ 1007c6f73aabSFrançois Tigeot nom = target_clock; 1008c6f73aabSFrançois Tigeot den = pll->reference_freq; 1009c6f73aabSFrançois Tigeot 1010c6f73aabSFrançois Tigeot /* reduce the numbers to a simpler ratio */ 1011c6f73aabSFrançois Tigeot avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min); 1012c6f73aabSFrançois Tigeot 1013c6f73aabSFrançois Tigeot /* now search for a post divider */ 1014c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 1015c6f73aabSFrançois Tigeot post_div_best = post_div_min; 1016c6f73aabSFrançois Tigeot else 1017c6f73aabSFrançois Tigeot post_div_best = post_div_max; 1018c6f73aabSFrançois Tigeot diff_best = ~0; 1019c6f73aabSFrançois Tigeot 1020c6f73aabSFrançois Tigeot for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { 1021c6f73aabSFrançois Tigeot unsigned diff; 1022c6f73aabSFrançois Tigeot avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, 1023c6f73aabSFrançois Tigeot ref_div_max, &fb_div, &ref_div); 1024c6f73aabSFrançois Tigeot diff = abs(target_clock - (pll->reference_freq * fb_div) / 1025c6f73aabSFrançois Tigeot (ref_div * post_div)); 1026c6f73aabSFrançois Tigeot 1027c6f73aabSFrançois Tigeot if (diff < diff_best || (diff == diff_best && 1028c6f73aabSFrançois Tigeot !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) { 1029c6f73aabSFrançois Tigeot 1030c6f73aabSFrançois Tigeot post_div_best = post_div; 1031c6f73aabSFrançois Tigeot diff_best = diff; 1032c6f73aabSFrançois Tigeot } 1033c6f73aabSFrançois Tigeot } 1034c6f73aabSFrançois Tigeot post_div = post_div_best; 1035c6f73aabSFrançois Tigeot 1036c6f73aabSFrançois Tigeot /* get the feedback and reference divider for the optimal value */ 1037c6f73aabSFrançois Tigeot avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max, 1038c6f73aabSFrançois Tigeot &fb_div, &ref_div); 1039c6f73aabSFrançois Tigeot 1040c6f73aabSFrançois Tigeot /* reduce the numbers to a simpler ratio once more */ 1041c6f73aabSFrançois Tigeot /* this also makes sure that the reference divider is large enough */ 1042c6f73aabSFrançois Tigeot avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); 1043c6f73aabSFrançois Tigeot 1044c6f73aabSFrançois Tigeot /* avoid high jitter with small fractional dividers */ 1045c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { 1046c6f73aabSFrançois Tigeot fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50); 1047c6f73aabSFrançois Tigeot if (fb_div < fb_div_min) { 1048c6f73aabSFrançois Tigeot unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div); 1049c6f73aabSFrançois Tigeot fb_div *= tmp; 1050c6f73aabSFrançois Tigeot ref_div *= tmp; 1051926deccbSFrançois Tigeot } 1052926deccbSFrançois Tigeot } 1053926deccbSFrançois Tigeot 1054c6f73aabSFrançois Tigeot /* and finally save the result */ 1055c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1056c6f73aabSFrançois Tigeot *fb_div_p = fb_div / 10; 1057c6f73aabSFrançois Tigeot *frac_fb_div_p = fb_div % 10; 1058c6f73aabSFrançois Tigeot } else { 1059926deccbSFrançois Tigeot *fb_div_p = fb_div; 1060c6f73aabSFrançois Tigeot *frac_fb_div_p = 0; 1061c6f73aabSFrançois Tigeot } 1062c6f73aabSFrançois Tigeot 1063c6f73aabSFrançois Tigeot *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + 1064c6f73aabSFrançois Tigeot (pll->reference_freq * *frac_fb_div_p)) / 1065c6f73aabSFrançois Tigeot (ref_div * post_div * 10); 1066926deccbSFrançois Tigeot *ref_div_p = ref_div; 1067926deccbSFrançois Tigeot *post_div_p = post_div; 1068c6f73aabSFrançois Tigeot 1069c6f73aabSFrançois Tigeot DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1070c6f73aabSFrançois Tigeot freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, 1071c6f73aabSFrançois Tigeot ref_div, post_div); 1072926deccbSFrançois Tigeot } 1073926deccbSFrançois Tigeot 1074926deccbSFrançois Tigeot /* pre-avivo */ 1075926deccbSFrançois Tigeot static inline uint32_t radeon_div(uint64_t n, uint32_t d) 1076926deccbSFrançois Tigeot { 1077926deccbSFrançois Tigeot uint64_t mod; 1078926deccbSFrançois Tigeot 1079926deccbSFrançois Tigeot n += d / 2; 1080926deccbSFrançois Tigeot 1081926deccbSFrançois Tigeot mod = do_div(n, d); 1082926deccbSFrançois Tigeot return n; 1083926deccbSFrançois Tigeot } 1084926deccbSFrançois Tigeot 1085926deccbSFrançois Tigeot void radeon_compute_pll_legacy(struct radeon_pll *pll, 1086926deccbSFrançois Tigeot uint64_t freq, 1087926deccbSFrançois Tigeot uint32_t *dot_clock_p, 1088926deccbSFrançois Tigeot uint32_t *fb_div_p, 1089926deccbSFrançois Tigeot uint32_t *frac_fb_div_p, 1090926deccbSFrançois Tigeot uint32_t *ref_div_p, 1091926deccbSFrançois Tigeot uint32_t *post_div_p) 1092926deccbSFrançois Tigeot { 1093926deccbSFrançois Tigeot uint32_t min_ref_div = pll->min_ref_div; 1094926deccbSFrançois Tigeot uint32_t max_ref_div = pll->max_ref_div; 1095926deccbSFrançois Tigeot uint32_t min_post_div = pll->min_post_div; 1096926deccbSFrançois Tigeot uint32_t max_post_div = pll->max_post_div; 1097926deccbSFrançois Tigeot uint32_t min_fractional_feed_div = 0; 1098926deccbSFrançois Tigeot uint32_t max_fractional_feed_div = 0; 1099926deccbSFrançois Tigeot uint32_t best_vco = pll->best_vco; 1100926deccbSFrançois Tigeot uint32_t best_post_div = 1; 1101926deccbSFrançois Tigeot uint32_t best_ref_div = 1; 1102926deccbSFrançois Tigeot uint32_t best_feedback_div = 1; 1103926deccbSFrançois Tigeot uint32_t best_frac_feedback_div = 0; 1104926deccbSFrançois Tigeot uint32_t best_freq = -1; 1105926deccbSFrançois Tigeot uint32_t best_error = 0xffffffff; 1106926deccbSFrançois Tigeot uint32_t best_vco_diff = 1; 1107926deccbSFrançois Tigeot uint32_t post_div; 1108926deccbSFrançois Tigeot u32 pll_out_min, pll_out_max; 1109926deccbSFrançois Tigeot 11104cd92098Szrj DRM_DEBUG_KMS("PLL freq %ju %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); 1111926deccbSFrançois Tigeot freq = freq * 1000; 1112926deccbSFrançois Tigeot 1113926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_IS_LCD) { 1114926deccbSFrançois Tigeot pll_out_min = pll->lcd_pll_out_min; 1115926deccbSFrançois Tigeot pll_out_max = pll->lcd_pll_out_max; 1116926deccbSFrançois Tigeot } else { 1117926deccbSFrançois Tigeot pll_out_min = pll->pll_out_min; 1118926deccbSFrançois Tigeot pll_out_max = pll->pll_out_max; 1119926deccbSFrançois Tigeot } 1120926deccbSFrançois Tigeot 1121926deccbSFrançois Tigeot if (pll_out_min > 64800) 1122926deccbSFrançois Tigeot pll_out_min = 64800; 1123926deccbSFrançois Tigeot 1124926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_REF_DIV) 1125926deccbSFrançois Tigeot min_ref_div = max_ref_div = pll->reference_div; 1126926deccbSFrançois Tigeot else { 1127926deccbSFrançois Tigeot while (min_ref_div < max_ref_div-1) { 1128926deccbSFrançois Tigeot uint32_t mid = (min_ref_div + max_ref_div) / 2; 1129926deccbSFrançois Tigeot uint32_t pll_in = pll->reference_freq / mid; 1130926deccbSFrançois Tigeot if (pll_in < pll->pll_in_min) 1131926deccbSFrançois Tigeot max_ref_div = mid; 1132926deccbSFrançois Tigeot else if (pll_in > pll->pll_in_max) 1133926deccbSFrançois Tigeot min_ref_div = mid; 1134926deccbSFrançois Tigeot else 1135926deccbSFrançois Tigeot break; 1136926deccbSFrançois Tigeot } 1137926deccbSFrançois Tigeot } 1138926deccbSFrançois Tigeot 1139926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_POST_DIV) 1140926deccbSFrançois Tigeot min_post_div = max_post_div = pll->post_div; 1141926deccbSFrançois Tigeot 1142926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1143926deccbSFrançois Tigeot min_fractional_feed_div = pll->min_frac_feedback_div; 1144926deccbSFrançois Tigeot max_fractional_feed_div = pll->max_frac_feedback_div; 1145926deccbSFrançois Tigeot } 1146926deccbSFrançois Tigeot 1147926deccbSFrançois Tigeot for (post_div = max_post_div; post_div >= min_post_div; --post_div) { 1148926deccbSFrançois Tigeot uint32_t ref_div; 1149926deccbSFrançois Tigeot 1150926deccbSFrançois Tigeot if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 1151926deccbSFrançois Tigeot continue; 1152926deccbSFrançois Tigeot 1153926deccbSFrançois Tigeot /* legacy radeons only have a few post_divs */ 1154926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_LEGACY) { 1155926deccbSFrançois Tigeot if ((post_div == 5) || 1156926deccbSFrançois Tigeot (post_div == 7) || 1157926deccbSFrançois Tigeot (post_div == 9) || 1158926deccbSFrançois Tigeot (post_div == 10) || 1159926deccbSFrançois Tigeot (post_div == 11) || 1160926deccbSFrançois Tigeot (post_div == 13) || 1161926deccbSFrançois Tigeot (post_div == 14) || 1162926deccbSFrançois Tigeot (post_div == 15)) 1163926deccbSFrançois Tigeot continue; 1164926deccbSFrançois Tigeot } 1165926deccbSFrançois Tigeot 1166926deccbSFrançois Tigeot for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { 1167926deccbSFrançois Tigeot uint32_t feedback_div, current_freq = 0, error, vco_diff; 1168926deccbSFrançois Tigeot uint32_t pll_in = pll->reference_freq / ref_div; 1169926deccbSFrançois Tigeot uint32_t min_feed_div = pll->min_feedback_div; 1170926deccbSFrançois Tigeot uint32_t max_feed_div = pll->max_feedback_div + 1; 1171926deccbSFrançois Tigeot 1172926deccbSFrançois Tigeot if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) 1173926deccbSFrançois Tigeot continue; 1174926deccbSFrançois Tigeot 1175926deccbSFrançois Tigeot while (min_feed_div < max_feed_div) { 1176926deccbSFrançois Tigeot uint32_t vco; 1177926deccbSFrançois Tigeot uint32_t min_frac_feed_div = min_fractional_feed_div; 1178926deccbSFrançois Tigeot uint32_t max_frac_feed_div = max_fractional_feed_div + 1; 1179926deccbSFrançois Tigeot uint32_t frac_feedback_div; 1180926deccbSFrançois Tigeot uint64_t tmp; 1181926deccbSFrançois Tigeot 1182926deccbSFrançois Tigeot feedback_div = (min_feed_div + max_feed_div) / 2; 1183926deccbSFrançois Tigeot 1184926deccbSFrançois Tigeot tmp = (uint64_t)pll->reference_freq * feedback_div; 1185926deccbSFrançois Tigeot vco = radeon_div(tmp, ref_div); 1186926deccbSFrançois Tigeot 1187926deccbSFrançois Tigeot if (vco < pll_out_min) { 1188926deccbSFrançois Tigeot min_feed_div = feedback_div + 1; 1189926deccbSFrançois Tigeot continue; 1190926deccbSFrançois Tigeot } else if (vco > pll_out_max) { 1191926deccbSFrançois Tigeot max_feed_div = feedback_div; 1192926deccbSFrançois Tigeot continue; 1193926deccbSFrançois Tigeot } 1194926deccbSFrançois Tigeot 1195926deccbSFrançois Tigeot while (min_frac_feed_div < max_frac_feed_div) { 1196926deccbSFrançois Tigeot frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; 1197926deccbSFrançois Tigeot tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; 1198926deccbSFrançois Tigeot tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; 1199926deccbSFrançois Tigeot current_freq = radeon_div(tmp, ref_div * post_div); 1200926deccbSFrançois Tigeot 1201926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 1202926deccbSFrançois Tigeot if (freq < current_freq) 1203926deccbSFrançois Tigeot error = 0xffffffff; 1204926deccbSFrançois Tigeot else 1205926deccbSFrançois Tigeot error = freq - current_freq; 1206926deccbSFrançois Tigeot } else 1207926deccbSFrançois Tigeot error = abs(current_freq - freq); 1208926deccbSFrançois Tigeot vco_diff = abs(vco - best_vco); 1209926deccbSFrançois Tigeot 1210926deccbSFrançois Tigeot if ((best_vco == 0 && error < best_error) || 1211926deccbSFrançois Tigeot (best_vco != 0 && 1212926deccbSFrançois Tigeot ((best_error > 100 && error < best_error - 100) || 1213926deccbSFrançois Tigeot (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { 1214926deccbSFrançois Tigeot best_post_div = post_div; 1215926deccbSFrançois Tigeot best_ref_div = ref_div; 1216926deccbSFrançois Tigeot best_feedback_div = feedback_div; 1217926deccbSFrançois Tigeot best_frac_feedback_div = frac_feedback_div; 1218926deccbSFrançois Tigeot best_freq = current_freq; 1219926deccbSFrançois Tigeot best_error = error; 1220926deccbSFrançois Tigeot best_vco_diff = vco_diff; 1221926deccbSFrançois Tigeot } else if (current_freq == freq) { 1222926deccbSFrançois Tigeot if (best_freq == -1) { 1223926deccbSFrançois Tigeot best_post_div = post_div; 1224926deccbSFrançois Tigeot best_ref_div = ref_div; 1225926deccbSFrançois Tigeot best_feedback_div = feedback_div; 1226926deccbSFrançois Tigeot best_frac_feedback_div = frac_feedback_div; 1227926deccbSFrançois Tigeot best_freq = current_freq; 1228926deccbSFrançois Tigeot best_error = error; 1229926deccbSFrançois Tigeot best_vco_diff = vco_diff; 1230926deccbSFrançois Tigeot } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 1231926deccbSFrançois Tigeot ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 1232926deccbSFrançois Tigeot ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 1233926deccbSFrançois Tigeot ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 1234926deccbSFrançois Tigeot ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 1235926deccbSFrançois Tigeot ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 1236926deccbSFrançois Tigeot best_post_div = post_div; 1237926deccbSFrançois Tigeot best_ref_div = ref_div; 1238926deccbSFrançois Tigeot best_feedback_div = feedback_div; 1239926deccbSFrançois Tigeot best_frac_feedback_div = frac_feedback_div; 1240926deccbSFrançois Tigeot best_freq = current_freq; 1241926deccbSFrançois Tigeot best_error = error; 1242926deccbSFrançois Tigeot best_vco_diff = vco_diff; 1243926deccbSFrançois Tigeot } 1244926deccbSFrançois Tigeot } 1245926deccbSFrançois Tigeot if (current_freq < freq) 1246926deccbSFrançois Tigeot min_frac_feed_div = frac_feedback_div + 1; 1247926deccbSFrançois Tigeot else 1248926deccbSFrançois Tigeot max_frac_feed_div = frac_feedback_div; 1249926deccbSFrançois Tigeot } 1250926deccbSFrançois Tigeot if (current_freq < freq) 1251926deccbSFrançois Tigeot min_feed_div = feedback_div + 1; 1252926deccbSFrançois Tigeot else 1253926deccbSFrançois Tigeot max_feed_div = feedback_div; 1254926deccbSFrançois Tigeot } 1255926deccbSFrançois Tigeot } 1256926deccbSFrançois Tigeot } 1257926deccbSFrançois Tigeot 1258926deccbSFrançois Tigeot *dot_clock_p = best_freq / 10000; 1259926deccbSFrançois Tigeot *fb_div_p = best_feedback_div; 1260926deccbSFrançois Tigeot *frac_fb_div_p = best_frac_feedback_div; 1261926deccbSFrançois Tigeot *ref_div_p = best_ref_div; 1262926deccbSFrançois Tigeot *post_div_p = best_post_div; 1263926deccbSFrançois Tigeot DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1264926deccbSFrançois Tigeot (long long)freq, 1265926deccbSFrançois Tigeot best_freq / 1000, best_feedback_div, best_frac_feedback_div, 1266926deccbSFrançois Tigeot best_ref_div, best_post_div); 1267926deccbSFrançois Tigeot 1268926deccbSFrançois Tigeot } 1269926deccbSFrançois Tigeot 1270926deccbSFrançois Tigeot static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) 1271926deccbSFrançois Tigeot { 1272926deccbSFrançois Tigeot struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1273926deccbSFrançois Tigeot 1274926deccbSFrançois Tigeot if (radeon_fb->obj) { 1275926deccbSFrançois Tigeot drm_gem_object_unreference_unlocked(radeon_fb->obj); 1276926deccbSFrançois Tigeot } 1277926deccbSFrançois Tigeot drm_framebuffer_cleanup(fb); 1278c4ef309bSzrj kfree(radeon_fb); 1279926deccbSFrançois Tigeot } 1280926deccbSFrançois Tigeot 1281926deccbSFrançois Tigeot static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, 1282926deccbSFrançois Tigeot struct drm_file *file_priv, 1283926deccbSFrançois Tigeot unsigned int *handle) 1284926deccbSFrançois Tigeot { 1285926deccbSFrançois Tigeot struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1286926deccbSFrançois Tigeot 1287926deccbSFrançois Tigeot return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); 1288926deccbSFrançois Tigeot } 1289926deccbSFrançois Tigeot 1290926deccbSFrançois Tigeot static const struct drm_framebuffer_funcs radeon_fb_funcs = { 1291926deccbSFrançois Tigeot .destroy = radeon_user_framebuffer_destroy, 1292926deccbSFrançois Tigeot .create_handle = radeon_user_framebuffer_create_handle, 1293926deccbSFrançois Tigeot }; 1294926deccbSFrançois Tigeot 1295926deccbSFrançois Tigeot int 1296926deccbSFrançois Tigeot radeon_framebuffer_init(struct drm_device *dev, 1297926deccbSFrançois Tigeot struct radeon_framebuffer *rfb, 1298*aee94f86SFrançois Tigeot const struct drm_mode_fb_cmd2 *mode_cmd, 1299926deccbSFrançois Tigeot struct drm_gem_object *obj) 1300926deccbSFrançois Tigeot { 1301926deccbSFrançois Tigeot int ret; 1302926deccbSFrançois Tigeot rfb->obj = obj; 1303b403bed8SMichael Neumann drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); 1304926deccbSFrançois Tigeot ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); 1305926deccbSFrançois Tigeot if (ret) { 1306926deccbSFrançois Tigeot rfb->obj = NULL; 1307926deccbSFrançois Tigeot return ret; 1308926deccbSFrançois Tigeot } 1309926deccbSFrançois Tigeot return 0; 1310926deccbSFrançois Tigeot } 1311926deccbSFrançois Tigeot 131260fc7eecSFrançois Tigeot static struct drm_framebuffer * 1313926deccbSFrançois Tigeot radeon_user_framebuffer_create(struct drm_device *dev, 1314926deccbSFrançois Tigeot struct drm_file *file_priv, 1315*aee94f86SFrançois Tigeot const struct drm_mode_fb_cmd2 *mode_cmd) 1316926deccbSFrançois Tigeot { 1317926deccbSFrançois Tigeot struct drm_gem_object *obj; 1318926deccbSFrançois Tigeot struct radeon_framebuffer *radeon_fb; 1319926deccbSFrançois Tigeot int ret; 1320926deccbSFrançois Tigeot 1321926deccbSFrançois Tigeot obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]); 1322926deccbSFrançois Tigeot if (obj == NULL) { 1323fb572d17SFrançois Tigeot dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 1324926deccbSFrançois Tigeot "can't create framebuffer\n", mode_cmd->handles[0]); 132560fc7eecSFrançois Tigeot return ERR_PTR(-ENOENT); 1326926deccbSFrançois Tigeot } 1327926deccbSFrançois Tigeot 1328c4ef309bSzrj radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); 1329926deccbSFrançois Tigeot if (radeon_fb == NULL) { 1330926deccbSFrançois Tigeot drm_gem_object_unreference_unlocked(obj); 133160fc7eecSFrançois Tigeot return ERR_PTR(-ENOMEM); 1332926deccbSFrançois Tigeot } 1333926deccbSFrançois Tigeot 1334926deccbSFrançois Tigeot ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj); 1335926deccbSFrançois Tigeot if (ret) { 1336158486a6SFrançois Tigeot kfree(radeon_fb); 1337926deccbSFrançois Tigeot drm_gem_object_unreference_unlocked(obj); 133860fc7eecSFrançois Tigeot return ERR_PTR(ret); 1339926deccbSFrançois Tigeot } 1340926deccbSFrançois Tigeot 134160fc7eecSFrançois Tigeot return &radeon_fb->base; 1342926deccbSFrançois Tigeot } 1343926deccbSFrançois Tigeot 1344926deccbSFrançois Tigeot static void radeon_output_poll_changed(struct drm_device *dev) 1345926deccbSFrançois Tigeot { 1346926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 1347926deccbSFrançois Tigeot radeon_fb_output_poll_changed(rdev); 1348926deccbSFrançois Tigeot } 1349926deccbSFrançois Tigeot 1350926deccbSFrançois Tigeot static const struct drm_mode_config_funcs radeon_mode_funcs = { 1351926deccbSFrançois Tigeot .fb_create = radeon_user_framebuffer_create, 1352926deccbSFrançois Tigeot .output_poll_changed = radeon_output_poll_changed 1353926deccbSFrançois Tigeot }; 1354926deccbSFrançois Tigeot 1355926deccbSFrançois Tigeot static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = 1356926deccbSFrançois Tigeot { { 0, "driver" }, 1357926deccbSFrançois Tigeot { 1, "bios" }, 1358926deccbSFrançois Tigeot }; 1359926deccbSFrançois Tigeot 1360926deccbSFrançois Tigeot static struct drm_prop_enum_list radeon_tv_std_enum_list[] = 1361926deccbSFrançois Tigeot { { TV_STD_NTSC, "ntsc" }, 1362926deccbSFrançois Tigeot { TV_STD_PAL, "pal" }, 1363926deccbSFrançois Tigeot { TV_STD_PAL_M, "pal-m" }, 1364926deccbSFrançois Tigeot { TV_STD_PAL_60, "pal-60" }, 1365926deccbSFrançois Tigeot { TV_STD_NTSC_J, "ntsc-j" }, 1366926deccbSFrançois Tigeot { TV_STD_SCART_PAL, "scart-pal" }, 1367926deccbSFrançois Tigeot { TV_STD_PAL_CN, "pal-cn" }, 1368926deccbSFrançois Tigeot { TV_STD_SECAM, "secam" }, 1369926deccbSFrançois Tigeot }; 1370926deccbSFrançois Tigeot 1371926deccbSFrançois Tigeot static struct drm_prop_enum_list radeon_underscan_enum_list[] = 1372926deccbSFrançois Tigeot { { UNDERSCAN_OFF, "off" }, 1373926deccbSFrançois Tigeot { UNDERSCAN_ON, "on" }, 1374926deccbSFrançois Tigeot { UNDERSCAN_AUTO, "auto" }, 1375926deccbSFrançois Tigeot }; 1376926deccbSFrançois Tigeot 13774cd92098Szrj static struct drm_prop_enum_list radeon_audio_enum_list[] = 13784cd92098Szrj { { RADEON_AUDIO_DISABLE, "off" }, 13794cd92098Szrj { RADEON_AUDIO_ENABLE, "on" }, 13804cd92098Szrj { RADEON_AUDIO_AUTO, "auto" }, 13814cd92098Szrj }; 13824cd92098Szrj 1383c6f73aabSFrançois Tigeot /* XXX support different dither options? spatial, temporal, both, etc. */ 1384c6f73aabSFrançois Tigeot static struct drm_prop_enum_list radeon_dither_enum_list[] = 1385c6f73aabSFrançois Tigeot { { RADEON_FMT_DITHER_DISABLE, "off" }, 1386c6f73aabSFrançois Tigeot { RADEON_FMT_DITHER_ENABLE, "on" }, 1387c6f73aabSFrançois Tigeot }; 1388c6f73aabSFrançois Tigeot 1389926deccbSFrançois Tigeot static int radeon_modeset_create_props(struct radeon_device *rdev) 1390926deccbSFrançois Tigeot { 1391926deccbSFrançois Tigeot int sz; 1392926deccbSFrançois Tigeot 1393926deccbSFrançois Tigeot if (rdev->is_atom_bios) { 1394926deccbSFrançois Tigeot rdev->mode_info.coherent_mode_property = 1395926deccbSFrançois Tigeot drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1); 1396926deccbSFrançois Tigeot if (!rdev->mode_info.coherent_mode_property) 1397926deccbSFrançois Tigeot return -ENOMEM; 1398926deccbSFrançois Tigeot } 1399926deccbSFrançois Tigeot 1400926deccbSFrançois Tigeot if (!ASIC_IS_AVIVO(rdev)) { 1401c4ef309bSzrj sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); 1402926deccbSFrançois Tigeot rdev->mode_info.tmds_pll_property = 1403926deccbSFrançois Tigeot drm_property_create_enum(rdev->ddev, 0, 1404926deccbSFrançois Tigeot "tmds_pll", 1405926deccbSFrançois Tigeot radeon_tmds_pll_enum_list, sz); 1406926deccbSFrançois Tigeot } 1407926deccbSFrançois Tigeot 1408926deccbSFrançois Tigeot rdev->mode_info.load_detect_property = 1409926deccbSFrançois Tigeot drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1); 1410926deccbSFrançois Tigeot if (!rdev->mode_info.load_detect_property) 1411926deccbSFrançois Tigeot return -ENOMEM; 1412926deccbSFrançois Tigeot 1413926deccbSFrançois Tigeot drm_mode_create_scaling_mode_property(rdev->ddev); 1414926deccbSFrançois Tigeot 1415c4ef309bSzrj sz = ARRAY_SIZE(radeon_tv_std_enum_list); 1416926deccbSFrançois Tigeot rdev->mode_info.tv_std_property = 1417926deccbSFrançois Tigeot drm_property_create_enum(rdev->ddev, 0, 1418926deccbSFrançois Tigeot "tv standard", 1419926deccbSFrançois Tigeot radeon_tv_std_enum_list, sz); 1420926deccbSFrançois Tigeot 1421c4ef309bSzrj sz = ARRAY_SIZE(radeon_underscan_enum_list); 1422926deccbSFrançois Tigeot rdev->mode_info.underscan_property = 1423926deccbSFrançois Tigeot drm_property_create_enum(rdev->ddev, 0, 1424926deccbSFrançois Tigeot "underscan", 1425926deccbSFrançois Tigeot radeon_underscan_enum_list, sz); 1426926deccbSFrançois Tigeot 1427926deccbSFrançois Tigeot rdev->mode_info.underscan_hborder_property = 1428926deccbSFrançois Tigeot drm_property_create_range(rdev->ddev, 0, 1429926deccbSFrançois Tigeot "underscan hborder", 0, 128); 1430926deccbSFrançois Tigeot if (!rdev->mode_info.underscan_hborder_property) 1431926deccbSFrançois Tigeot return -ENOMEM; 1432926deccbSFrançois Tigeot 1433926deccbSFrançois Tigeot rdev->mode_info.underscan_vborder_property = 1434926deccbSFrançois Tigeot drm_property_create_range(rdev->ddev, 0, 1435926deccbSFrançois Tigeot "underscan vborder", 0, 128); 1436926deccbSFrançois Tigeot if (!rdev->mode_info.underscan_vborder_property) 1437926deccbSFrançois Tigeot return -ENOMEM; 1438926deccbSFrançois Tigeot 14394cd92098Szrj sz = ARRAY_SIZE(radeon_audio_enum_list); 14404cd92098Szrj rdev->mode_info.audio_property = 14414cd92098Szrj drm_property_create_enum(rdev->ddev, 0, 14424cd92098Szrj "audio", 14434cd92098Szrj radeon_audio_enum_list, sz); 14444cd92098Szrj 1445c6f73aabSFrançois Tigeot sz = ARRAY_SIZE(radeon_dither_enum_list); 1446c6f73aabSFrançois Tigeot rdev->mode_info.dither_property = 1447c6f73aabSFrançois Tigeot drm_property_create_enum(rdev->ddev, 0, 1448c6f73aabSFrançois Tigeot "dither", 1449c6f73aabSFrançois Tigeot radeon_dither_enum_list, sz); 1450c6f73aabSFrançois Tigeot 1451926deccbSFrançois Tigeot return 0; 1452926deccbSFrançois Tigeot } 1453926deccbSFrançois Tigeot 1454926deccbSFrançois Tigeot void radeon_update_display_priority(struct radeon_device *rdev) 1455926deccbSFrançois Tigeot { 1456926deccbSFrançois Tigeot /* adjustment options for the display watermarks */ 1457926deccbSFrançois Tigeot if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { 1458926deccbSFrançois Tigeot /* set display priority to high for r3xx, rv515 chips 1459926deccbSFrançois Tigeot * this avoids flickering due to underflow to the 1460926deccbSFrançois Tigeot * display controllers during heavy acceleration. 1461926deccbSFrançois Tigeot * Don't force high on rs4xx igp chips as it seems to 1462926deccbSFrançois Tigeot * affect the sound card. See kernel bug 15982. 1463926deccbSFrançois Tigeot */ 1464926deccbSFrançois Tigeot if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && 1465926deccbSFrançois Tigeot !(rdev->flags & RADEON_IS_IGP)) 1466926deccbSFrançois Tigeot rdev->disp_priority = 2; 1467926deccbSFrançois Tigeot else 1468926deccbSFrançois Tigeot rdev->disp_priority = 0; 1469926deccbSFrançois Tigeot } else 1470926deccbSFrançois Tigeot rdev->disp_priority = radeon_disp_priority; 1471926deccbSFrançois Tigeot 1472926deccbSFrançois Tigeot } 1473926deccbSFrançois Tigeot 1474926deccbSFrançois Tigeot /* 1475926deccbSFrançois Tigeot * Allocate hdmi structs and determine register offsets 1476926deccbSFrançois Tigeot */ 1477926deccbSFrançois Tigeot static void radeon_afmt_init(struct radeon_device *rdev) 1478926deccbSFrançois Tigeot { 1479926deccbSFrançois Tigeot int i; 1480926deccbSFrançois Tigeot 1481926deccbSFrançois Tigeot for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) 1482926deccbSFrançois Tigeot rdev->mode_info.afmt[i] = NULL; 1483926deccbSFrançois Tigeot 14844cd92098Szrj if (ASIC_IS_NODCE(rdev)) { 14854cd92098Szrj /* nothing to do */ 1486926deccbSFrançois Tigeot } else if (ASIC_IS_DCE4(rdev)) { 14874cd92098Szrj static uint32_t eg_offsets[] = { 14884cd92098Szrj EVERGREEN_CRTC0_REGISTER_OFFSET, 14894cd92098Szrj EVERGREEN_CRTC1_REGISTER_OFFSET, 14904cd92098Szrj EVERGREEN_CRTC2_REGISTER_OFFSET, 14914cd92098Szrj EVERGREEN_CRTC3_REGISTER_OFFSET, 14924cd92098Szrj EVERGREEN_CRTC4_REGISTER_OFFSET, 14934cd92098Szrj EVERGREEN_CRTC5_REGISTER_OFFSET, 14944cd92098Szrj 0x13830 - 0x7030, 14954cd92098Szrj }; 14964cd92098Szrj int num_afmt; 14974cd92098Szrj 14984cd92098Szrj /* DCE8 has 7 audio blocks tied to DIG encoders */ 14994cd92098Szrj /* DCE6 has 6 audio blocks tied to DIG encoders */ 1500926deccbSFrançois Tigeot /* DCE4/5 has 6 audio blocks tied to DIG encoders */ 1501926deccbSFrançois Tigeot /* DCE4.1 has 2 audio blocks tied to DIG encoders */ 15024cd92098Szrj if (ASIC_IS_DCE8(rdev)) 15034cd92098Szrj num_afmt = 7; 15044cd92098Szrj else if (ASIC_IS_DCE6(rdev)) 15054cd92098Szrj num_afmt = 6; 15064cd92098Szrj else if (ASIC_IS_DCE5(rdev)) 15074cd92098Szrj num_afmt = 6; 15084cd92098Szrj else if (ASIC_IS_DCE41(rdev)) 15094cd92098Szrj num_afmt = 2; 15104cd92098Szrj else /* DCE4 */ 15114cd92098Szrj num_afmt = 6; 15124cd92098Szrj 15134cd92098Szrj BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets)); 15144cd92098Szrj for (i = 0; i < num_afmt; i++) { 15154cd92098Szrj rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 15164cd92098Szrj if (rdev->mode_info.afmt[i]) { 15174cd92098Szrj rdev->mode_info.afmt[i]->offset = eg_offsets[i]; 15184cd92098Szrj rdev->mode_info.afmt[i]->id = i; 1519926deccbSFrançois Tigeot } 1520926deccbSFrançois Tigeot } 1521926deccbSFrançois Tigeot } else if (ASIC_IS_DCE3(rdev)) { 1522926deccbSFrançois Tigeot /* DCE3.x has 2 audio blocks tied to DIG encoders */ 1523c4ef309bSzrj rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1524926deccbSFrançois Tigeot if (rdev->mode_info.afmt[0]) { 1525926deccbSFrançois Tigeot rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0; 1526926deccbSFrançois Tigeot rdev->mode_info.afmt[0]->id = 0; 1527926deccbSFrançois Tigeot } 1528c4ef309bSzrj rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1529926deccbSFrançois Tigeot if (rdev->mode_info.afmt[1]) { 1530926deccbSFrançois Tigeot rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1; 1531926deccbSFrançois Tigeot rdev->mode_info.afmt[1]->id = 1; 1532926deccbSFrançois Tigeot } 1533926deccbSFrançois Tigeot } else if (ASIC_IS_DCE2(rdev)) { 1534926deccbSFrançois Tigeot /* DCE2 has at least 1 routable audio block */ 1535c4ef309bSzrj rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1536926deccbSFrançois Tigeot if (rdev->mode_info.afmt[0]) { 1537926deccbSFrançois Tigeot rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0; 1538926deccbSFrançois Tigeot rdev->mode_info.afmt[0]->id = 0; 1539926deccbSFrançois Tigeot } 1540926deccbSFrançois Tigeot /* r6xx has 2 routable audio blocks */ 1541926deccbSFrançois Tigeot if (rdev->family >= CHIP_R600) { 1542c4ef309bSzrj rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1543926deccbSFrançois Tigeot if (rdev->mode_info.afmt[1]) { 1544926deccbSFrançois Tigeot rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1; 1545926deccbSFrançois Tigeot rdev->mode_info.afmt[1]->id = 1; 1546926deccbSFrançois Tigeot } 1547926deccbSFrançois Tigeot } 1548926deccbSFrançois Tigeot } 1549926deccbSFrançois Tigeot } 1550926deccbSFrançois Tigeot 1551926deccbSFrançois Tigeot static void radeon_afmt_fini(struct radeon_device *rdev) 1552926deccbSFrançois Tigeot { 1553926deccbSFrançois Tigeot int i; 1554926deccbSFrançois Tigeot 1555926deccbSFrançois Tigeot for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) { 1556c4ef309bSzrj kfree(rdev->mode_info.afmt[i]); 1557926deccbSFrançois Tigeot rdev->mode_info.afmt[i] = NULL; 1558926deccbSFrançois Tigeot } 1559926deccbSFrançois Tigeot } 1560926deccbSFrançois Tigeot 1561926deccbSFrançois Tigeot int radeon_modeset_init(struct radeon_device *rdev) 1562926deccbSFrançois Tigeot { 1563926deccbSFrançois Tigeot int i; 1564926deccbSFrançois Tigeot int ret; 1565926deccbSFrançois Tigeot 1566926deccbSFrançois Tigeot drm_mode_config_init(rdev->ddev); 1567926deccbSFrançois Tigeot rdev->mode_info.mode_config_initialized = true; 1568926deccbSFrançois Tigeot 1569926deccbSFrançois Tigeot rdev->ddev->mode_config.funcs = &radeon_mode_funcs; 1570926deccbSFrançois Tigeot 1571926deccbSFrançois Tigeot if (ASIC_IS_DCE5(rdev)) { 1572926deccbSFrançois Tigeot rdev->ddev->mode_config.max_width = 16384; 1573926deccbSFrançois Tigeot rdev->ddev->mode_config.max_height = 16384; 1574926deccbSFrançois Tigeot } else if (ASIC_IS_AVIVO(rdev)) { 1575926deccbSFrançois Tigeot rdev->ddev->mode_config.max_width = 8192; 1576926deccbSFrançois Tigeot rdev->ddev->mode_config.max_height = 8192; 1577926deccbSFrançois Tigeot } else { 1578926deccbSFrançois Tigeot rdev->ddev->mode_config.max_width = 4096; 1579926deccbSFrançois Tigeot rdev->ddev->mode_config.max_height = 4096; 1580926deccbSFrançois Tigeot } 1581926deccbSFrançois Tigeot 1582926deccbSFrançois Tigeot rdev->ddev->mode_config.preferred_depth = 24; 1583926deccbSFrançois Tigeot rdev->ddev->mode_config.prefer_shadow = 1; 1584926deccbSFrançois Tigeot 1585926deccbSFrançois Tigeot rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; 1586926deccbSFrançois Tigeot 1587926deccbSFrançois Tigeot ret = radeon_modeset_create_props(rdev); 1588926deccbSFrançois Tigeot if (ret) { 1589926deccbSFrançois Tigeot return ret; 1590926deccbSFrançois Tigeot } 1591926deccbSFrançois Tigeot 1592926deccbSFrançois Tigeot /* init i2c buses */ 1593926deccbSFrançois Tigeot radeon_i2c_init(rdev); 1594926deccbSFrançois Tigeot 1595926deccbSFrançois Tigeot /* check combios for a valid hardcoded EDID - Sun servers */ 1596926deccbSFrançois Tigeot if (!rdev->is_atom_bios) { 1597926deccbSFrançois Tigeot /* check for hardcoded EDID in BIOS */ 1598926deccbSFrançois Tigeot radeon_combios_check_hardcoded_edid(rdev); 1599926deccbSFrançois Tigeot } 1600926deccbSFrançois Tigeot 1601926deccbSFrançois Tigeot /* allocate crtcs */ 1602926deccbSFrançois Tigeot for (i = 0; i < rdev->num_crtc; i++) { 1603926deccbSFrançois Tigeot radeon_crtc_init(rdev->ddev, i); 1604926deccbSFrançois Tigeot } 1605926deccbSFrançois Tigeot 1606926deccbSFrançois Tigeot /* okay we should have all the bios connectors */ 1607926deccbSFrançois Tigeot ret = radeon_setup_enc_conn(rdev->ddev); 1608926deccbSFrançois Tigeot if (!ret) { 1609926deccbSFrançois Tigeot return ret; 1610926deccbSFrançois Tigeot } 1611926deccbSFrançois Tigeot 1612926deccbSFrançois Tigeot /* init dig PHYs, disp eng pll */ 1613926deccbSFrançois Tigeot if (rdev->is_atom_bios) { 1614926deccbSFrançois Tigeot radeon_atom_encoder_init(rdev); 1615926deccbSFrançois Tigeot radeon_atom_disp_eng_pll_init(rdev); 1616926deccbSFrançois Tigeot } 1617926deccbSFrançois Tigeot 1618926deccbSFrançois Tigeot /* initialize hpd */ 1619926deccbSFrançois Tigeot radeon_hpd_init(rdev); 1620926deccbSFrançois Tigeot 1621926deccbSFrançois Tigeot /* setup afmt */ 1622926deccbSFrançois Tigeot radeon_afmt_init(rdev); 1623926deccbSFrançois Tigeot 1624926deccbSFrançois Tigeot radeon_fbdev_init(rdev); 1625926deccbSFrançois Tigeot drm_kms_helper_poll_init(rdev->ddev); 1626926deccbSFrançois Tigeot 1627c6f73aabSFrançois Tigeot if (rdev->pm.dpm_enabled) { 1628c6f73aabSFrançois Tigeot /* do dpm late init */ 1629c6f73aabSFrançois Tigeot ret = radeon_pm_late_init(rdev); 1630c6f73aabSFrançois Tigeot if (ret) { 1631c6f73aabSFrançois Tigeot rdev->pm.dpm_enabled = false; 1632c6f73aabSFrançois Tigeot DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1633c6f73aabSFrançois Tigeot } 1634c6f73aabSFrançois Tigeot /* set the dpm state for PX since there won't be 1635c6f73aabSFrançois Tigeot * a modeset to call this. 1636c6f73aabSFrançois Tigeot */ 1637c6f73aabSFrançois Tigeot radeon_pm_compute_clocks(rdev); 1638c6f73aabSFrançois Tigeot } 1639c6f73aabSFrançois Tigeot 1640926deccbSFrançois Tigeot return 0; 1641926deccbSFrançois Tigeot } 1642926deccbSFrançois Tigeot 1643926deccbSFrançois Tigeot void radeon_modeset_fini(struct radeon_device *rdev) 1644926deccbSFrançois Tigeot { 1645926deccbSFrançois Tigeot radeon_fbdev_fini(rdev); 1646c4ef309bSzrj kfree(rdev->mode_info.bios_hardcoded_edid); 1647926deccbSFrançois Tigeot 1648926deccbSFrançois Tigeot if (rdev->mode_info.mode_config_initialized) { 1649926deccbSFrançois Tigeot radeon_afmt_fini(rdev); 1650926deccbSFrançois Tigeot drm_kms_helper_poll_fini(rdev->ddev); 1651926deccbSFrançois Tigeot radeon_hpd_fini(rdev); 1652926deccbSFrançois Tigeot DRM_UNLOCK(rdev->ddev); /* Work around lock recursion. dumbbell@ */ 1653926deccbSFrançois Tigeot drm_mode_config_cleanup(rdev->ddev); 1654926deccbSFrançois Tigeot DRM_LOCK(rdev->ddev); 1655926deccbSFrançois Tigeot rdev->mode_info.mode_config_initialized = false; 1656926deccbSFrançois Tigeot } 1657926deccbSFrançois Tigeot /* free i2c buses */ 1658926deccbSFrançois Tigeot radeon_i2c_fini(rdev); 1659926deccbSFrançois Tigeot } 1660926deccbSFrançois Tigeot 1661926deccbSFrançois Tigeot static bool is_hdtv_mode(const struct drm_display_mode *mode) 1662926deccbSFrançois Tigeot { 1663926deccbSFrançois Tigeot /* try and guess if this is a tv or a monitor */ 1664926deccbSFrançois Tigeot if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 1665926deccbSFrançois Tigeot (mode->vdisplay == 576) || /* 576p */ 1666926deccbSFrançois Tigeot (mode->vdisplay == 720) || /* 720p */ 1667926deccbSFrançois Tigeot (mode->vdisplay == 1080)) /* 1080p */ 1668926deccbSFrançois Tigeot return true; 1669926deccbSFrançois Tigeot else 1670926deccbSFrançois Tigeot return false; 1671926deccbSFrançois Tigeot } 1672926deccbSFrançois Tigeot 1673926deccbSFrançois Tigeot bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 1674926deccbSFrançois Tigeot const struct drm_display_mode *mode, 1675926deccbSFrançois Tigeot struct drm_display_mode *adjusted_mode) 1676926deccbSFrançois Tigeot { 1677926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev; 1678926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 1679926deccbSFrançois Tigeot struct drm_encoder *encoder; 1680926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1681926deccbSFrançois Tigeot struct radeon_encoder *radeon_encoder; 1682926deccbSFrançois Tigeot struct drm_connector *connector; 1683926deccbSFrançois Tigeot struct radeon_connector *radeon_connector; 1684926deccbSFrançois Tigeot bool first = true; 1685926deccbSFrançois Tigeot u32 src_v = 1, dst_v = 1; 1686926deccbSFrançois Tigeot u32 src_h = 1, dst_h = 1; 1687926deccbSFrançois Tigeot 1688926deccbSFrançois Tigeot radeon_crtc->h_border = 0; 1689926deccbSFrançois Tigeot radeon_crtc->v_border = 0; 1690926deccbSFrançois Tigeot 1691926deccbSFrançois Tigeot list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1692926deccbSFrançois Tigeot if (encoder->crtc != crtc) 1693926deccbSFrançois Tigeot continue; 1694926deccbSFrançois Tigeot radeon_encoder = to_radeon_encoder(encoder); 1695926deccbSFrançois Tigeot connector = radeon_get_connector_for_encoder(encoder); 1696926deccbSFrançois Tigeot radeon_connector = to_radeon_connector(connector); 1697926deccbSFrançois Tigeot 1698926deccbSFrançois Tigeot if (first) { 1699926deccbSFrançois Tigeot /* set scaling */ 1700926deccbSFrançois Tigeot if (radeon_encoder->rmx_type == RMX_OFF) 1701926deccbSFrançois Tigeot radeon_crtc->rmx_type = RMX_OFF; 1702926deccbSFrançois Tigeot else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || 1703926deccbSFrançois Tigeot mode->vdisplay < radeon_encoder->native_mode.vdisplay) 1704926deccbSFrançois Tigeot radeon_crtc->rmx_type = radeon_encoder->rmx_type; 1705926deccbSFrançois Tigeot else 1706926deccbSFrançois Tigeot radeon_crtc->rmx_type = RMX_OFF; 1707926deccbSFrançois Tigeot /* copy native mode */ 1708926deccbSFrançois Tigeot memcpy(&radeon_crtc->native_mode, 1709926deccbSFrançois Tigeot &radeon_encoder->native_mode, 1710926deccbSFrançois Tigeot sizeof(struct drm_display_mode)); 1711926deccbSFrançois Tigeot src_v = crtc->mode.vdisplay; 1712926deccbSFrançois Tigeot dst_v = radeon_crtc->native_mode.vdisplay; 1713926deccbSFrançois Tigeot src_h = crtc->mode.hdisplay; 1714926deccbSFrançois Tigeot dst_h = radeon_crtc->native_mode.hdisplay; 1715926deccbSFrançois Tigeot 1716926deccbSFrançois Tigeot /* fix up for overscan on hdmi */ 1717926deccbSFrançois Tigeot if (ASIC_IS_AVIVO(rdev) && 1718926deccbSFrançois Tigeot (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 1719926deccbSFrançois Tigeot ((radeon_encoder->underscan_type == UNDERSCAN_ON) || 1720926deccbSFrançois Tigeot ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && 1721c6f73aabSFrançois Tigeot drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 1722926deccbSFrançois Tigeot is_hdtv_mode(mode)))) { 1723926deccbSFrançois Tigeot if (radeon_encoder->underscan_hborder != 0) 1724926deccbSFrançois Tigeot radeon_crtc->h_border = radeon_encoder->underscan_hborder; 1725926deccbSFrançois Tigeot else 1726926deccbSFrançois Tigeot radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; 1727926deccbSFrançois Tigeot if (radeon_encoder->underscan_vborder != 0) 1728926deccbSFrançois Tigeot radeon_crtc->v_border = radeon_encoder->underscan_vborder; 1729926deccbSFrançois Tigeot else 1730926deccbSFrançois Tigeot radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; 1731926deccbSFrançois Tigeot radeon_crtc->rmx_type = RMX_FULL; 1732926deccbSFrançois Tigeot src_v = crtc->mode.vdisplay; 1733926deccbSFrançois Tigeot dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); 1734926deccbSFrançois Tigeot src_h = crtc->mode.hdisplay; 1735926deccbSFrançois Tigeot dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); 1736926deccbSFrançois Tigeot } 1737926deccbSFrançois Tigeot first = false; 1738926deccbSFrançois Tigeot } else { 1739926deccbSFrançois Tigeot if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { 1740926deccbSFrançois Tigeot /* WARNING: Right now this can't happen but 1741926deccbSFrançois Tigeot * in the future we need to check that scaling 1742926deccbSFrançois Tigeot * are consistent across different encoder 1743926deccbSFrançois Tigeot * (ie all encoder can work with the same 1744926deccbSFrançois Tigeot * scaling). 1745926deccbSFrançois Tigeot */ 1746926deccbSFrançois Tigeot DRM_ERROR("Scaling not consistent across encoder.\n"); 1747926deccbSFrançois Tigeot return false; 1748926deccbSFrançois Tigeot } 1749926deccbSFrançois Tigeot } 1750926deccbSFrançois Tigeot } 1751926deccbSFrançois Tigeot if (radeon_crtc->rmx_type != RMX_OFF) { 1752926deccbSFrançois Tigeot fixed20_12 a, b; 1753926deccbSFrançois Tigeot a.full = dfixed_const(src_v); 1754926deccbSFrançois Tigeot b.full = dfixed_const(dst_v); 1755926deccbSFrançois Tigeot radeon_crtc->vsc.full = dfixed_div(a, b); 1756926deccbSFrançois Tigeot a.full = dfixed_const(src_h); 1757926deccbSFrançois Tigeot b.full = dfixed_const(dst_h); 1758926deccbSFrançois Tigeot radeon_crtc->hsc.full = dfixed_div(a, b); 1759926deccbSFrançois Tigeot } else { 1760926deccbSFrançois Tigeot radeon_crtc->vsc.full = dfixed_const(1); 1761926deccbSFrançois Tigeot radeon_crtc->hsc.full = dfixed_const(1); 1762926deccbSFrançois Tigeot } 1763926deccbSFrançois Tigeot return true; 1764926deccbSFrançois Tigeot } 1765926deccbSFrançois Tigeot 1766926deccbSFrançois Tigeot /* 1767782e40d3SFrançois Tigeot * Retrieve current video scanout position of crtc on a given gpu, and 1768782e40d3SFrançois Tigeot * an optional accurate timestamp of when query happened. 1769926deccbSFrançois Tigeot * 1770926deccbSFrançois Tigeot * \param dev Device to query. 1771926deccbSFrançois Tigeot * \param crtc Crtc to query. 1772782e40d3SFrançois Tigeot * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 1773926deccbSFrançois Tigeot * \param *vpos Location where vertical scanout position should be stored. 1774926deccbSFrançois Tigeot * \param *hpos Location where horizontal scanout position should go. 1775782e40d3SFrançois Tigeot * \param *stime Target location for timestamp taken immediately before 1776782e40d3SFrançois Tigeot * scanout position query. Can be NULL to skip timestamp. 1777782e40d3SFrançois Tigeot * \param *etime Target location for timestamp taken immediately after 1778782e40d3SFrançois Tigeot * scanout position query. Can be NULL to skip timestamp. 1779926deccbSFrançois Tigeot * 1780926deccbSFrançois Tigeot * Returns vpos as a positive number while in active scanout area. 1781926deccbSFrançois Tigeot * Returns vpos as a negative number inside vblank, counting the number 1782926deccbSFrançois Tigeot * of scanlines to go until end of vblank, e.g., -1 means "one scanline 1783926deccbSFrançois Tigeot * until start of active scanout / end of vblank." 1784926deccbSFrançois Tigeot * 1785926deccbSFrançois Tigeot * \return Flags, or'ed together as follows: 1786926deccbSFrançois Tigeot * 1787926deccbSFrançois Tigeot * DRM_SCANOUTPOS_VALID = Query successful. 1788926deccbSFrançois Tigeot * DRM_SCANOUTPOS_INVBL = Inside vblank. 1789926deccbSFrançois Tigeot * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 1790926deccbSFrançois Tigeot * this flag means that returned position may be offset by a constant but 1791926deccbSFrançois Tigeot * unknown small number of scanlines wrt. real scanout position. 1792926deccbSFrançois Tigeot * 1793926deccbSFrançois Tigeot */ 1794782e40d3SFrançois Tigeot int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags, 1795352ff8bdSFrançois Tigeot int *vpos, int *hpos, ktime_t *stime, ktime_t *etime, 1796352ff8bdSFrançois Tigeot const struct drm_display_mode *mode) 1797926deccbSFrançois Tigeot { 1798926deccbSFrançois Tigeot u32 stat_crtc = 0, vbl = 0, position = 0; 1799926deccbSFrançois Tigeot int vbl_start, vbl_end, vtotal, ret = 0; 1800926deccbSFrançois Tigeot bool in_vbl = true; 1801926deccbSFrançois Tigeot 1802926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 1803926deccbSFrançois Tigeot 1804782e40d3SFrançois Tigeot /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 1805782e40d3SFrançois Tigeot 1806782e40d3SFrançois Tigeot /* Get optional system timestamp before query. */ 1807782e40d3SFrançois Tigeot if (stime) 1808782e40d3SFrançois Tigeot *stime = ktime_get(); 1809782e40d3SFrançois Tigeot 1810926deccbSFrançois Tigeot if (ASIC_IS_DCE4(rdev)) { 1811926deccbSFrançois Tigeot if (crtc == 0) { 1812926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1813926deccbSFrançois Tigeot EVERGREEN_CRTC0_REGISTER_OFFSET); 1814926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1815926deccbSFrançois Tigeot EVERGREEN_CRTC0_REGISTER_OFFSET); 1816926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1817926deccbSFrançois Tigeot } 1818926deccbSFrançois Tigeot if (crtc == 1) { 1819926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1820926deccbSFrançois Tigeot EVERGREEN_CRTC1_REGISTER_OFFSET); 1821926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1822926deccbSFrançois Tigeot EVERGREEN_CRTC1_REGISTER_OFFSET); 1823926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1824926deccbSFrançois Tigeot } 1825926deccbSFrançois Tigeot if (crtc == 2) { 1826926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1827926deccbSFrançois Tigeot EVERGREEN_CRTC2_REGISTER_OFFSET); 1828926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1829926deccbSFrançois Tigeot EVERGREEN_CRTC2_REGISTER_OFFSET); 1830926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1831926deccbSFrançois Tigeot } 1832926deccbSFrançois Tigeot if (crtc == 3) { 1833926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1834926deccbSFrançois Tigeot EVERGREEN_CRTC3_REGISTER_OFFSET); 1835926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1836926deccbSFrançois Tigeot EVERGREEN_CRTC3_REGISTER_OFFSET); 1837926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1838926deccbSFrançois Tigeot } 1839926deccbSFrançois Tigeot if (crtc == 4) { 1840926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1841926deccbSFrançois Tigeot EVERGREEN_CRTC4_REGISTER_OFFSET); 1842926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1843926deccbSFrançois Tigeot EVERGREEN_CRTC4_REGISTER_OFFSET); 1844926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1845926deccbSFrançois Tigeot } 1846926deccbSFrançois Tigeot if (crtc == 5) { 1847926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1848926deccbSFrançois Tigeot EVERGREEN_CRTC5_REGISTER_OFFSET); 1849926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1850926deccbSFrançois Tigeot EVERGREEN_CRTC5_REGISTER_OFFSET); 1851926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1852926deccbSFrançois Tigeot } 1853926deccbSFrançois Tigeot } else if (ASIC_IS_AVIVO(rdev)) { 1854926deccbSFrançois Tigeot if (crtc == 0) { 1855926deccbSFrançois Tigeot vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); 1856926deccbSFrançois Tigeot position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); 1857926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1858926deccbSFrançois Tigeot } 1859926deccbSFrançois Tigeot if (crtc == 1) { 1860926deccbSFrançois Tigeot vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); 1861926deccbSFrançois Tigeot position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); 1862926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1863926deccbSFrançois Tigeot } 1864926deccbSFrançois Tigeot } else { 1865926deccbSFrançois Tigeot /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ 1866926deccbSFrançois Tigeot if (crtc == 0) { 1867926deccbSFrançois Tigeot /* Assume vbl_end == 0, get vbl_start from 1868926deccbSFrançois Tigeot * upper 16 bits. 1869926deccbSFrançois Tigeot */ 1870926deccbSFrançois Tigeot vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & 1871926deccbSFrançois Tigeot RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1872926deccbSFrançois Tigeot /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ 1873926deccbSFrançois Tigeot position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1874926deccbSFrançois Tigeot stat_crtc = RREG32(RADEON_CRTC_STATUS); 1875926deccbSFrançois Tigeot if (!(stat_crtc & 1)) 1876926deccbSFrançois Tigeot in_vbl = false; 1877926deccbSFrançois Tigeot 1878926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1879926deccbSFrançois Tigeot } 1880926deccbSFrançois Tigeot if (crtc == 1) { 1881926deccbSFrançois Tigeot vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & 1882926deccbSFrançois Tigeot RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1883926deccbSFrançois Tigeot position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1884926deccbSFrançois Tigeot stat_crtc = RREG32(RADEON_CRTC2_STATUS); 1885926deccbSFrançois Tigeot if (!(stat_crtc & 1)) 1886926deccbSFrançois Tigeot in_vbl = false; 1887926deccbSFrançois Tigeot 1888926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1889926deccbSFrançois Tigeot } 1890926deccbSFrançois Tigeot } 1891926deccbSFrançois Tigeot 1892782e40d3SFrançois Tigeot /* Get optional system timestamp after query. */ 1893782e40d3SFrançois Tigeot if (etime) 1894782e40d3SFrançois Tigeot *etime = ktime_get(); 1895782e40d3SFrançois Tigeot 1896782e40d3SFrançois Tigeot /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 1897782e40d3SFrançois Tigeot 1898926deccbSFrançois Tigeot /* Decode into vertical and horizontal scanout position. */ 1899926deccbSFrançois Tigeot *vpos = position & 0x1fff; 1900926deccbSFrançois Tigeot *hpos = (position >> 16) & 0x1fff; 1901926deccbSFrançois Tigeot 1902926deccbSFrançois Tigeot /* Valid vblank area boundaries from gpu retrieved? */ 1903926deccbSFrançois Tigeot if (vbl > 0) { 1904926deccbSFrançois Tigeot /* Yes: Decode. */ 1905926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_ACCURATE; 1906926deccbSFrançois Tigeot vbl_start = vbl & 0x1fff; 1907926deccbSFrançois Tigeot vbl_end = (vbl >> 16) & 0x1fff; 1908926deccbSFrançois Tigeot } 1909926deccbSFrançois Tigeot else { 1910926deccbSFrançois Tigeot /* No: Fake something reasonable which gives at least ok results. */ 1911352ff8bdSFrançois Tigeot vbl_start = mode->crtc_vdisplay; 1912926deccbSFrançois Tigeot vbl_end = 0; 1913926deccbSFrançois Tigeot } 1914926deccbSFrançois Tigeot 1915926deccbSFrançois Tigeot /* Test scanout position against vblank region. */ 1916926deccbSFrançois Tigeot if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 1917926deccbSFrançois Tigeot in_vbl = false; 1918926deccbSFrançois Tigeot 1919926deccbSFrançois Tigeot /* Check if inside vblank area and apply corrective offsets: 1920926deccbSFrançois Tigeot * vpos will then be >=0 in video scanout area, but negative 1921926deccbSFrançois Tigeot * within vblank area, counting down the number of lines until 1922926deccbSFrançois Tigeot * start of scanout. 1923926deccbSFrançois Tigeot */ 1924926deccbSFrançois Tigeot 1925926deccbSFrançois Tigeot /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 1926926deccbSFrançois Tigeot if (in_vbl && (*vpos >= vbl_start)) { 1927352ff8bdSFrançois Tigeot vtotal = mode->crtc_vtotal; 1928926deccbSFrançois Tigeot *vpos = *vpos - vtotal; 1929926deccbSFrançois Tigeot } 1930926deccbSFrançois Tigeot 1931926deccbSFrançois Tigeot /* Correct for shifted end of vbl at vbl_end. */ 1932926deccbSFrançois Tigeot *vpos = *vpos - vbl_end; 1933926deccbSFrançois Tigeot 1934926deccbSFrançois Tigeot /* In vblank? */ 1935926deccbSFrançois Tigeot if (in_vbl) 19361b13d190SFrançois Tigeot ret |= DRM_SCANOUTPOS_IN_VBLANK; 1937926deccbSFrançois Tigeot 1938782e40d3SFrançois Tigeot /* Is vpos outside nominal vblank area, but less than 1939782e40d3SFrançois Tigeot * 1/100 of a frame height away from start of vblank? 1940782e40d3SFrançois Tigeot * If so, assume this isn't a massively delayed vblank 1941782e40d3SFrançois Tigeot * interrupt, but a vblank interrupt that fired a few 1942782e40d3SFrançois Tigeot * microseconds before true start of vblank. Compensate 1943782e40d3SFrançois Tigeot * by adding a full frame duration to the final timestamp. 1944782e40d3SFrançois Tigeot * Happens, e.g., on ATI R500, R600. 1945782e40d3SFrançois Tigeot * 1946782e40d3SFrançois Tigeot * We only do this if DRM_CALLED_FROM_VBLIRQ. 1947782e40d3SFrançois Tigeot */ 1948782e40d3SFrançois Tigeot if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) { 1949782e40d3SFrançois Tigeot vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay; 1950782e40d3SFrançois Tigeot vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal; 1951782e40d3SFrançois Tigeot 1952782e40d3SFrançois Tigeot if (vbl_start - *vpos < vtotal / 100) { 1953782e40d3SFrançois Tigeot *vpos -= vtotal; 1954782e40d3SFrançois Tigeot 1955782e40d3SFrançois Tigeot /* Signal this correction as "applied". */ 1956782e40d3SFrançois Tigeot ret |= 0x8; 1957782e40d3SFrançois Tigeot } 1958782e40d3SFrançois Tigeot } 1959782e40d3SFrançois Tigeot 1960926deccbSFrançois Tigeot return ret; 1961926deccbSFrançois Tigeot } 1962