1926deccbSFrançois Tigeot /* 2926deccbSFrançois Tigeot * Copyright 2007-8 Advanced Micro Devices, Inc. 3926deccbSFrançois Tigeot * Copyright 2008 Red Hat Inc. 4926deccbSFrançois Tigeot * 5926deccbSFrançois Tigeot * Permission is hereby granted, free of charge, to any person obtaining a 6926deccbSFrançois Tigeot * copy of this software and associated documentation files (the "Software"), 7926deccbSFrançois Tigeot * to deal in the Software without restriction, including without limitation 8926deccbSFrançois Tigeot * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9926deccbSFrançois Tigeot * and/or sell copies of the Software, and to permit persons to whom the 10926deccbSFrançois Tigeot * Software is furnished to do so, subject to the following conditions: 11926deccbSFrançois Tigeot * 12926deccbSFrançois Tigeot * The above copyright notice and this permission notice shall be included in 13926deccbSFrançois Tigeot * all copies or substantial portions of the Software. 14926deccbSFrançois Tigeot * 15926deccbSFrançois Tigeot * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16926deccbSFrançois Tigeot * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17926deccbSFrançois Tigeot * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18926deccbSFrançois Tigeot * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19926deccbSFrançois Tigeot * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20926deccbSFrançois Tigeot * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21926deccbSFrançois Tigeot * OTHER DEALINGS IN THE SOFTWARE. 22926deccbSFrançois Tigeot * 23926deccbSFrançois Tigeot * Authors: Dave Airlie 24926deccbSFrançois Tigeot * Alex Deucher 25926deccbSFrançois Tigeot */ 26926deccbSFrançois Tigeot #include <drm/drmP.h> 2783b4b9b9SFrançois Tigeot #include <drm/radeon_drm.h> 28926deccbSFrançois Tigeot #include "radeon.h" 29926deccbSFrançois Tigeot 30926deccbSFrançois Tigeot #include "atom.h" 31926deccbSFrançois Tigeot 32c6f73aabSFrançois Tigeot #include <linux/pm_runtime.h> 33926deccbSFrançois Tigeot #include <drm/drm_crtc_helper.h> 342c9916cdSFrançois Tigeot #include <drm/drm_plane_helper.h> 35926deccbSFrançois Tigeot #include <drm/drm_edid.h> 36926deccbSFrançois Tigeot 37c6f73aabSFrançois Tigeot #include <linux/gcd.h> 38c6f73aabSFrançois Tigeot 39926deccbSFrançois Tigeot static void avivo_crtc_load_lut(struct drm_crtc *crtc) 40926deccbSFrançois Tigeot { 41926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 42926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev; 43926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 44926deccbSFrançois Tigeot int i; 45926deccbSFrançois Tigeot 46926deccbSFrançois Tigeot DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 47926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); 48926deccbSFrançois Tigeot 49926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 50926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 51926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 52926deccbSFrançois Tigeot 53926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 54926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 55926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 56926deccbSFrançois Tigeot 57926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); 58926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUT_RW_MODE, 0); 59926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); 60926deccbSFrançois Tigeot 61926deccbSFrançois Tigeot WREG8(AVIVO_DC_LUT_RW_INDEX, 0); 62926deccbSFrançois Tigeot for (i = 0; i < 256; i++) { 63926deccbSFrançois Tigeot WREG32(AVIVO_DC_LUT_30_COLOR, 64926deccbSFrançois Tigeot (radeon_crtc->lut_r[i] << 20) | 65926deccbSFrançois Tigeot (radeon_crtc->lut_g[i] << 10) | 66926deccbSFrançois Tigeot (radeon_crtc->lut_b[i] << 0)); 67926deccbSFrançois Tigeot } 68926deccbSFrançois Tigeot 69c6f73aabSFrançois Tigeot /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */ 70c6f73aabSFrançois Tigeot WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1); 71926deccbSFrançois Tigeot } 72926deccbSFrançois Tigeot 73926deccbSFrançois Tigeot static void dce4_crtc_load_lut(struct drm_crtc *crtc) 74926deccbSFrançois Tigeot { 75926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 76926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev; 77926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 78926deccbSFrançois Tigeot int i; 79926deccbSFrançois Tigeot 80926deccbSFrançois Tigeot DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 81926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 82926deccbSFrançois Tigeot 83926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 84926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 85926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 86926deccbSFrançois Tigeot 87926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 88926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 89926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 90926deccbSFrançois Tigeot 91926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 92926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 93926deccbSFrançois Tigeot 94926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 95926deccbSFrançois Tigeot for (i = 0; i < 256; i++) { 96926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 97926deccbSFrançois Tigeot (radeon_crtc->lut_r[i] << 20) | 98926deccbSFrançois Tigeot (radeon_crtc->lut_g[i] << 10) | 99926deccbSFrançois Tigeot (radeon_crtc->lut_b[i] << 0)); 100926deccbSFrançois Tigeot } 101926deccbSFrançois Tigeot } 102926deccbSFrançois Tigeot 103926deccbSFrançois Tigeot static void dce5_crtc_load_lut(struct drm_crtc *crtc) 104926deccbSFrançois Tigeot { 105926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 106926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev; 107926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 108926deccbSFrançois Tigeot int i; 109926deccbSFrançois Tigeot 110926deccbSFrançois Tigeot DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 111926deccbSFrançois Tigeot 112926deccbSFrançois Tigeot WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 113926deccbSFrançois Tigeot (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | 114926deccbSFrançois Tigeot NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); 115926deccbSFrançois Tigeot WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, 116926deccbSFrançois Tigeot NI_GRPH_PRESCALE_BYPASS); 117926deccbSFrançois Tigeot WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, 118926deccbSFrançois Tigeot NI_OVL_PRESCALE_BYPASS); 119926deccbSFrançois Tigeot WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, 120926deccbSFrançois Tigeot (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | 121926deccbSFrançois Tigeot NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); 122926deccbSFrançois Tigeot 123926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 124926deccbSFrançois Tigeot 125926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 126926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 127926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 128926deccbSFrançois Tigeot 129926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 130926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 131926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 132926deccbSFrançois Tigeot 133926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 134926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 135926deccbSFrançois Tigeot 136926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 137926deccbSFrançois Tigeot for (i = 0; i < 256; i++) { 138926deccbSFrançois Tigeot WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 139926deccbSFrançois Tigeot (radeon_crtc->lut_r[i] << 20) | 140926deccbSFrançois Tigeot (radeon_crtc->lut_g[i] << 10) | 141926deccbSFrançois Tigeot (radeon_crtc->lut_b[i] << 0)); 142926deccbSFrançois Tigeot } 143926deccbSFrançois Tigeot 144926deccbSFrançois Tigeot WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, 145926deccbSFrançois Tigeot (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 146926deccbSFrançois Tigeot NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 147926deccbSFrançois Tigeot NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 148926deccbSFrançois Tigeot NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); 149926deccbSFrançois Tigeot WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, 150926deccbSFrançois Tigeot (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | 151926deccbSFrançois Tigeot NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); 152926deccbSFrançois Tigeot WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, 153926deccbSFrançois Tigeot (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | 154926deccbSFrançois Tigeot NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); 155926deccbSFrançois Tigeot WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 156c59a5c48SFrançois Tigeot (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) | 157926deccbSFrançois Tigeot NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); 158926deccbSFrançois Tigeot /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 159926deccbSFrançois Tigeot WREG32(0x6940 + radeon_crtc->crtc_offset, 0); 16057e252bfSMichael Neumann if (ASIC_IS_DCE8(rdev)) { 16157e252bfSMichael Neumann /* XXX this only needs to be programmed once per crtc at startup, 16257e252bfSMichael Neumann * not sure where the best place for it is 16357e252bfSMichael Neumann */ 16457e252bfSMichael Neumann WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset, 16557e252bfSMichael Neumann CIK_CURSOR_ALPHA_BLND_ENA); 16657e252bfSMichael Neumann } 167926deccbSFrançois Tigeot } 168926deccbSFrançois Tigeot 169926deccbSFrançois Tigeot static void legacy_crtc_load_lut(struct drm_crtc *crtc) 170926deccbSFrançois Tigeot { 171926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 172926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev; 173926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 174926deccbSFrançois Tigeot int i; 175926deccbSFrançois Tigeot uint32_t dac2_cntl; 176926deccbSFrançois Tigeot 177926deccbSFrançois Tigeot dac2_cntl = RREG32(RADEON_DAC_CNTL2); 178926deccbSFrançois Tigeot if (radeon_crtc->crtc_id == 0) 179926deccbSFrançois Tigeot dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; 180926deccbSFrançois Tigeot else 181926deccbSFrançois Tigeot dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; 182926deccbSFrançois Tigeot WREG32(RADEON_DAC_CNTL2, dac2_cntl); 183926deccbSFrançois Tigeot 184926deccbSFrançois Tigeot WREG8(RADEON_PALETTE_INDEX, 0); 185926deccbSFrançois Tigeot for (i = 0; i < 256; i++) { 186926deccbSFrançois Tigeot WREG32(RADEON_PALETTE_30_DATA, 187926deccbSFrançois Tigeot (radeon_crtc->lut_r[i] << 20) | 188926deccbSFrançois Tigeot (radeon_crtc->lut_g[i] << 10) | 189926deccbSFrançois Tigeot (radeon_crtc->lut_b[i] << 0)); 190926deccbSFrançois Tigeot } 191926deccbSFrançois Tigeot } 192926deccbSFrançois Tigeot 193926deccbSFrançois Tigeot void radeon_crtc_load_lut(struct drm_crtc *crtc) 194926deccbSFrançois Tigeot { 195926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev; 196926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 197926deccbSFrançois Tigeot 198926deccbSFrançois Tigeot if (!crtc->enabled) 199926deccbSFrançois Tigeot return; 200926deccbSFrançois Tigeot 201926deccbSFrançois Tigeot if (ASIC_IS_DCE5(rdev)) 202926deccbSFrançois Tigeot dce5_crtc_load_lut(crtc); 203926deccbSFrançois Tigeot else if (ASIC_IS_DCE4(rdev)) 204926deccbSFrançois Tigeot dce4_crtc_load_lut(crtc); 205926deccbSFrançois Tigeot else if (ASIC_IS_AVIVO(rdev)) 206926deccbSFrançois Tigeot avivo_crtc_load_lut(crtc); 207926deccbSFrançois Tigeot else 208926deccbSFrançois Tigeot legacy_crtc_load_lut(crtc); 209926deccbSFrançois Tigeot } 210926deccbSFrançois Tigeot 211926deccbSFrançois Tigeot /** Sets the color ramps on behalf of fbcon */ 212926deccbSFrançois Tigeot void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 213926deccbSFrançois Tigeot u16 blue, int regno) 214926deccbSFrançois Tigeot { 215926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 216926deccbSFrançois Tigeot 217926deccbSFrançois Tigeot radeon_crtc->lut_r[regno] = red >> 6; 218926deccbSFrançois Tigeot radeon_crtc->lut_g[regno] = green >> 6; 219926deccbSFrançois Tigeot radeon_crtc->lut_b[regno] = blue >> 6; 220926deccbSFrançois Tigeot } 221926deccbSFrançois Tigeot 222926deccbSFrançois Tigeot /** Gets the color ramps on behalf of fbcon */ 223926deccbSFrançois Tigeot void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 224926deccbSFrançois Tigeot u16 *blue, int regno) 225926deccbSFrançois Tigeot { 226926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 227926deccbSFrançois Tigeot 228926deccbSFrançois Tigeot *red = radeon_crtc->lut_r[regno] << 6; 229926deccbSFrançois Tigeot *green = radeon_crtc->lut_g[regno] << 6; 230926deccbSFrançois Tigeot *blue = radeon_crtc->lut_b[regno] << 6; 231926deccbSFrançois Tigeot } 232926deccbSFrançois Tigeot 233926deccbSFrançois Tigeot static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 234926deccbSFrançois Tigeot u16 *blue, uint32_t start, uint32_t size) 235926deccbSFrançois Tigeot { 236926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 237926deccbSFrançois Tigeot int end = (start + size > 256) ? 256 : start + size, i; 238926deccbSFrançois Tigeot 239926deccbSFrançois Tigeot /* userspace palettes are always correct as is */ 240926deccbSFrançois Tigeot for (i = start; i < end; i++) { 241926deccbSFrançois Tigeot radeon_crtc->lut_r[i] = red[i] >> 6; 242926deccbSFrançois Tigeot radeon_crtc->lut_g[i] = green[i] >> 6; 243926deccbSFrançois Tigeot radeon_crtc->lut_b[i] = blue[i] >> 6; 244926deccbSFrançois Tigeot } 245926deccbSFrançois Tigeot radeon_crtc_load_lut(crtc); 246926deccbSFrançois Tigeot } 247926deccbSFrançois Tigeot 248926deccbSFrançois Tigeot static void radeon_crtc_destroy(struct drm_crtc *crtc) 249926deccbSFrançois Tigeot { 250926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 251926deccbSFrançois Tigeot 252926deccbSFrançois Tigeot drm_crtc_cleanup(crtc); 253c6f73aabSFrançois Tigeot destroy_workqueue(radeon_crtc->flip_queue); 254c4ef309bSzrj kfree(radeon_crtc); 255926deccbSFrançois Tigeot } 256926deccbSFrançois Tigeot 257c6f73aabSFrançois Tigeot /** 258c6f73aabSFrançois Tigeot * radeon_unpin_work_func - unpin old buffer object 259c6f73aabSFrançois Tigeot * 260c6f73aabSFrançois Tigeot * @__work - kernel work item 261c6f73aabSFrançois Tigeot * 262c6f73aabSFrançois Tigeot * Unpin the old frame buffer object outside of the interrupt handler 263926deccbSFrançois Tigeot */ 264c6f73aabSFrançois Tigeot static void radeon_unpin_work_func(struct work_struct *__work) 265926deccbSFrançois Tigeot { 266c6f73aabSFrançois Tigeot struct radeon_flip_work *work = 267c6f73aabSFrançois Tigeot container_of(__work, struct radeon_flip_work, unpin_work); 268926deccbSFrançois Tigeot int r; 269926deccbSFrançois Tigeot 270926deccbSFrançois Tigeot /* unpin of the old buffer */ 271926deccbSFrançois Tigeot r = radeon_bo_reserve(work->old_rbo, false); 272926deccbSFrançois Tigeot if (likely(r == 0)) { 273926deccbSFrançois Tigeot r = radeon_bo_unpin(work->old_rbo); 274926deccbSFrançois Tigeot if (unlikely(r != 0)) { 275926deccbSFrançois Tigeot DRM_ERROR("failed to unpin buffer after flip\n"); 276926deccbSFrançois Tigeot } 277926deccbSFrançois Tigeot radeon_bo_unreserve(work->old_rbo); 278926deccbSFrançois Tigeot } else 279926deccbSFrançois Tigeot DRM_ERROR("failed to reserve buffer after flip\n"); 280926deccbSFrançois Tigeot 281926deccbSFrançois Tigeot drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 282c4ef309bSzrj kfree(work); 283926deccbSFrançois Tigeot } 284926deccbSFrançois Tigeot 285c6f73aabSFrançois Tigeot void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id) 286926deccbSFrançois Tigeot { 287926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 2887dcf36dcSFrançois Tigeot unsigned long flags; 289926deccbSFrançois Tigeot u32 update_pending; 290926deccbSFrançois Tigeot int vpos, hpos; 291926deccbSFrançois Tigeot 292c6f73aabSFrançois Tigeot /* can happen during initialization */ 293c6f73aabSFrançois Tigeot if (radeon_crtc == NULL) 294c6f73aabSFrançois Tigeot return; 295c6f73aabSFrançois Tigeot 296c6f73aabSFrançois Tigeot /* Skip the pageflip completion check below (based on polling) on 297c6f73aabSFrançois Tigeot * asics which reliably support hw pageflip completion irqs. pflip 298c6f73aabSFrançois Tigeot * irqs are a reliable and race-free method of handling pageflip 299c6f73aabSFrançois Tigeot * completion detection. A use_pflipirq module parameter < 2 allows 300c6f73aabSFrançois Tigeot * to override this in case of asics with faulty pflip irqs. 301c6f73aabSFrançois Tigeot * A module parameter of 0 would only use this polling based path, 302c6f73aabSFrançois Tigeot * a parameter of 1 would use pflip irq only as a backup to this 303c6f73aabSFrançois Tigeot * path, as in Linux 3.16. 304c6f73aabSFrançois Tigeot */ 305c6f73aabSFrançois Tigeot if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev)) 306c6f73aabSFrançois Tigeot return; 307c6f73aabSFrançois Tigeot 3087dcf36dcSFrançois Tigeot spin_lock_irqsave(&rdev->ddev->event_lock, flags); 309c6f73aabSFrançois Tigeot if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 310c6f73aabSFrançois Tigeot DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 311c6f73aabSFrançois Tigeot "RADEON_FLIP_SUBMITTED(%d)\n", 312c6f73aabSFrançois Tigeot radeon_crtc->flip_status, 313c6f73aabSFrançois Tigeot RADEON_FLIP_SUBMITTED); 3147dcf36dcSFrançois Tigeot spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 315926deccbSFrançois Tigeot return; 316926deccbSFrançois Tigeot } 317c6f73aabSFrançois Tigeot 318c6f73aabSFrançois Tigeot update_pending = radeon_page_flip_pending(rdev, crtc_id); 319926deccbSFrançois Tigeot 320926deccbSFrançois Tigeot /* Has the pageflip already completed in crtc, or is it certain 321926deccbSFrançois Tigeot * to complete in this vblank? 322926deccbSFrançois Tigeot */ 323926deccbSFrançois Tigeot if (update_pending && 324c59a5c48SFrançois Tigeot (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, 325c59a5c48SFrançois Tigeot crtc_id, 326c59a5c48SFrançois Tigeot USE_REAL_VBLANKSTART, 327352ff8bdSFrançois Tigeot &vpos, &hpos, NULL, NULL, 328352ff8bdSFrançois Tigeot &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) && 329926deccbSFrançois Tigeot ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) || 330926deccbSFrançois Tigeot (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) { 331926deccbSFrançois Tigeot /* crtc didn't flip in this target vblank interval, 332926deccbSFrançois Tigeot * but flip is pending in crtc. Based on the current 333926deccbSFrançois Tigeot * scanout position we know that the current frame is 334926deccbSFrançois Tigeot * (nearly) complete and the flip will (likely) 335926deccbSFrançois Tigeot * complete before the start of the next frame. 336926deccbSFrançois Tigeot */ 337926deccbSFrançois Tigeot update_pending = 0; 338926deccbSFrançois Tigeot } 3397dcf36dcSFrançois Tigeot spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 340c6f73aabSFrançois Tigeot if (!update_pending) 341c6f73aabSFrançois Tigeot radeon_crtc_handle_flip(rdev, crtc_id); 342c6f73aabSFrançois Tigeot } 343c6f73aabSFrançois Tigeot 344c6f73aabSFrançois Tigeot /** 345c6f73aabSFrançois Tigeot * radeon_crtc_handle_flip - page flip completed 346c6f73aabSFrançois Tigeot * 347c6f73aabSFrançois Tigeot * @rdev: radeon device pointer 348c6f73aabSFrançois Tigeot * @crtc_id: crtc number this event is for 349c6f73aabSFrançois Tigeot * 350c6f73aabSFrançois Tigeot * Called when we are sure that a page flip for this crtc is completed. 351926deccbSFrançois Tigeot */ 352c6f73aabSFrançois Tigeot void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) 353c6f73aabSFrançois Tigeot { 354c6f73aabSFrançois Tigeot struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 355c6f73aabSFrançois Tigeot struct radeon_flip_work *work; 3567dcf36dcSFrançois Tigeot unsigned long flags; 357c6f73aabSFrançois Tigeot 358c6f73aabSFrançois Tigeot /* this can happen at init */ 359c6f73aabSFrançois Tigeot if (radeon_crtc == NULL) 360c6f73aabSFrançois Tigeot return; 361c6f73aabSFrançois Tigeot 3627dcf36dcSFrançois Tigeot spin_lock_irqsave(&rdev->ddev->event_lock, flags); 363c6f73aabSFrançois Tigeot work = radeon_crtc->flip_work; 364c6f73aabSFrançois Tigeot if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 365c6f73aabSFrançois Tigeot DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 366c6f73aabSFrançois Tigeot "RADEON_FLIP_SUBMITTED(%d)\n", 367c6f73aabSFrançois Tigeot radeon_crtc->flip_status, 368c6f73aabSFrançois Tigeot RADEON_FLIP_SUBMITTED); 3697dcf36dcSFrançois Tigeot spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 370926deccbSFrançois Tigeot return; 371926deccbSFrançois Tigeot } 372926deccbSFrançois Tigeot 373c6f73aabSFrançois Tigeot /* Pageflip completed. Clean up. */ 374c6f73aabSFrançois Tigeot radeon_crtc->flip_status = RADEON_FLIP_NONE; 375c6f73aabSFrançois Tigeot radeon_crtc->flip_work = NULL; 376926deccbSFrançois Tigeot 377926deccbSFrançois Tigeot /* wakeup userspace */ 378f43cf1b1SMichael Neumann if (work->event) 379*d78d3a22SFrançois Tigeot drm_crtc_send_vblank_event(&radeon_crtc->base, work->event); 380f43cf1b1SMichael Neumann 3817dcf36dcSFrançois Tigeot spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 382926deccbSFrançois Tigeot 383926deccbSFrançois Tigeot drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id); 384c6f73aabSFrançois Tigeot radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id); 385c6f73aabSFrançois Tigeot queue_work(radeon_crtc->flip_queue, &work->unpin_work); 386c6f73aabSFrançois Tigeot } 387c6f73aabSFrançois Tigeot 388c6f73aabSFrançois Tigeot /** 389c6f73aabSFrançois Tigeot * radeon_flip_work_func - page flip framebuffer 390c6f73aabSFrançois Tigeot * 391c6f73aabSFrançois Tigeot * @work - kernel work item 392c6f73aabSFrançois Tigeot * 393c6f73aabSFrançois Tigeot * Wait for the buffer object to become idle and do the actual page flip 394c6f73aabSFrançois Tigeot */ 395c6f73aabSFrançois Tigeot static void radeon_flip_work_func(struct work_struct *__work) 396c6f73aabSFrançois Tigeot { 397c6f73aabSFrançois Tigeot struct radeon_flip_work *work = 398c6f73aabSFrançois Tigeot container_of(__work, struct radeon_flip_work, flip_work); 399c6f73aabSFrançois Tigeot struct radeon_device *rdev = work->rdev; 400c6f73aabSFrançois Tigeot struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id]; 401c6f73aabSFrançois Tigeot 402c6f73aabSFrançois Tigeot struct drm_crtc *crtc = &radeon_crtc->base; 4037dcf36dcSFrançois Tigeot unsigned long flags; 404c6f73aabSFrançois Tigeot int r; 405c59a5c48SFrançois Tigeot int vpos, hpos, stat, min_udelay = 0; 406c59a5c48SFrançois Tigeot unsigned repcnt = 4; 407c59a5c48SFrançois Tigeot struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id]; 408c6f73aabSFrançois Tigeot 4097dcf36dcSFrançois Tigeot down_read(&rdev->exclusive_lock); 410c6f73aabSFrançois Tigeot if (work->fence) { 4117dcf36dcSFrançois Tigeot struct radeon_fence *fence; 4127dcf36dcSFrançois Tigeot 4137dcf36dcSFrançois Tigeot fence = to_radeon_fence(work->fence); 4147dcf36dcSFrançois Tigeot if (fence && fence->rdev == rdev) { 4157dcf36dcSFrançois Tigeot r = radeon_fence_wait(fence, false); 416c6f73aabSFrançois Tigeot if (r == -EDEADLK) { 4177dcf36dcSFrançois Tigeot up_read(&rdev->exclusive_lock); 418591d5043SFrançois Tigeot do { 419c6f73aabSFrançois Tigeot r = radeon_gpu_reset(rdev); 420591d5043SFrançois Tigeot } while (r == -EAGAIN); 4217dcf36dcSFrançois Tigeot down_read(&rdev->exclusive_lock); 422c6f73aabSFrançois Tigeot } 4237dcf36dcSFrançois Tigeot } else 4247dcf36dcSFrançois Tigeot r = fence_wait(work->fence, false); 4257dcf36dcSFrançois Tigeot 426c6f73aabSFrançois Tigeot if (r) 427c6f73aabSFrançois Tigeot DRM_ERROR("failed to wait on page flip fence (%d)!\n", r); 428c6f73aabSFrançois Tigeot 429c6f73aabSFrançois Tigeot /* We continue with the page flip even if we failed to wait on 430c6f73aabSFrançois Tigeot * the fence, otherwise the DRM core and userspace will be 431c6f73aabSFrançois Tigeot * confused about which BO the CRTC is scanning out 432c6f73aabSFrançois Tigeot */ 433c6f73aabSFrançois Tigeot 4347dcf36dcSFrançois Tigeot fence_put(work->fence); 4357dcf36dcSFrançois Tigeot work->fence = NULL; 436c6f73aabSFrançois Tigeot } 437c6f73aabSFrançois Tigeot 438c6f73aabSFrançois Tigeot /* We borrow the event spin lock for protecting flip_status */ 4397dcf36dcSFrançois Tigeot spin_lock_irqsave(&crtc->dev->event_lock, flags); 440c6f73aabSFrançois Tigeot 441c6f73aabSFrançois Tigeot /* set the proper interrupt */ 442c6f73aabSFrançois Tigeot radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id); 443c6f73aabSFrançois Tigeot 444c59a5c48SFrançois Tigeot /* If this happens to execute within the "virtually extended" vblank 445c59a5c48SFrançois Tigeot * interval before the start of the real vblank interval then it needs 446c59a5c48SFrançois Tigeot * to delay programming the mmio flip until the real vblank is entered. 447c59a5c48SFrançois Tigeot * This prevents completing a flip too early due to the way we fudge 448c59a5c48SFrançois Tigeot * our vblank counter and vblank timestamps in order to work around the 449c59a5c48SFrançois Tigeot * problem that the hw fires vblank interrupts before actual start of 450c59a5c48SFrançois Tigeot * vblank (when line buffer refilling is done for a frame). It 451c59a5c48SFrançois Tigeot * complements the fudging logic in radeon_get_crtc_scanoutpos() for 452c59a5c48SFrançois Tigeot * timestamping and radeon_get_vblank_counter_kms() for vblank counts. 453c59a5c48SFrançois Tigeot * 454c59a5c48SFrançois Tigeot * In practice this won't execute very often unless on very fast 455c59a5c48SFrançois Tigeot * machines because the time window for this to happen is very small. 456c59a5c48SFrançois Tigeot */ 457c59a5c48SFrançois Tigeot while (radeon_crtc->enabled && --repcnt) { 458c59a5c48SFrançois Tigeot /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank 459c59a5c48SFrançois Tigeot * start in hpos, and to the "fudged earlier" vblank start in 460c59a5c48SFrançois Tigeot * vpos. 461c59a5c48SFrançois Tigeot */ 462c59a5c48SFrançois Tigeot stat = radeon_get_crtc_scanoutpos(rdev->ddev, work->crtc_id, 463c59a5c48SFrançois Tigeot GET_DISTANCE_TO_VBLANKSTART, 464c59a5c48SFrançois Tigeot &vpos, &hpos, NULL, NULL, 465c59a5c48SFrançois Tigeot &crtc->hwmode); 466c59a5c48SFrançois Tigeot 467c59a5c48SFrançois Tigeot if ((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 468c59a5c48SFrançois Tigeot (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE) || 469c59a5c48SFrançois Tigeot !(vpos >= 0 && hpos <= 0)) 470c59a5c48SFrançois Tigeot break; 471c59a5c48SFrançois Tigeot 472c59a5c48SFrançois Tigeot /* Sleep at least until estimated real start of hw vblank */ 473c59a5c48SFrançois Tigeot min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5); 474c59a5c48SFrançois Tigeot if (min_udelay > vblank->framedur_ns / 2000) { 475c59a5c48SFrançois Tigeot /* Don't wait ridiculously long - something is wrong */ 476c59a5c48SFrançois Tigeot repcnt = 0; 477c59a5c48SFrançois Tigeot break; 478c59a5c48SFrançois Tigeot } 479c59a5c48SFrançois Tigeot spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 480c59a5c48SFrançois Tigeot usleep_range(min_udelay, 2 * min_udelay); 481c59a5c48SFrançois Tigeot spin_lock_irqsave(&crtc->dev->event_lock, flags); 482c59a5c48SFrançois Tigeot }; 483c59a5c48SFrançois Tigeot 484c59a5c48SFrançois Tigeot if (!repcnt) 485c59a5c48SFrançois Tigeot DRM_DEBUG_DRIVER("Delay problem on crtc %d: min_udelay %d, " 486c59a5c48SFrançois Tigeot "framedur %d, linedur %d, stat %d, vpos %d, " 487c59a5c48SFrançois Tigeot "hpos %d\n", work->crtc_id, min_udelay, 488c59a5c48SFrançois Tigeot vblank->framedur_ns / 1000, 489c59a5c48SFrançois Tigeot vblank->linedur_ns / 1000, stat, vpos, hpos); 490c59a5c48SFrançois Tigeot 491c6f73aabSFrançois Tigeot /* do the flip (mmio) */ 492*d78d3a22SFrançois Tigeot radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async); 493c6f73aabSFrançois Tigeot 494c6f73aabSFrançois Tigeot radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED; 4957dcf36dcSFrançois Tigeot spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 4967dcf36dcSFrançois Tigeot up_read(&rdev->exclusive_lock); 497926deccbSFrançois Tigeot } 498926deccbSFrançois Tigeot 499926deccbSFrançois Tigeot static int radeon_crtc_page_flip(struct drm_crtc *crtc, 500926deccbSFrançois Tigeot struct drm_framebuffer *fb, 5019edbd4a0SFrançois Tigeot struct drm_pending_vblank_event *event, 5029edbd4a0SFrançois Tigeot uint32_t page_flip_flags) 503926deccbSFrançois Tigeot { 504926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev; 505926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 506926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 507926deccbSFrançois Tigeot struct radeon_framebuffer *old_radeon_fb; 508926deccbSFrançois Tigeot struct radeon_framebuffer *new_radeon_fb; 509926deccbSFrançois Tigeot struct drm_gem_object *obj; 510c6f73aabSFrançois Tigeot struct radeon_flip_work *work; 511c6f73aabSFrançois Tigeot struct radeon_bo *new_rbo; 512c6f73aabSFrançois Tigeot uint32_t tiling_flags, pitch_pixels; 513c6f73aabSFrançois Tigeot uint64_t base; 5147dcf36dcSFrançois Tigeot unsigned long flags; 515926deccbSFrançois Tigeot int r; 516926deccbSFrançois Tigeot 517c4ef309bSzrj work = kzalloc(sizeof *work, GFP_KERNEL); 518926deccbSFrançois Tigeot if (work == NULL) 519926deccbSFrançois Tigeot return -ENOMEM; 520926deccbSFrançois Tigeot 521c6f73aabSFrançois Tigeot INIT_WORK(&work->flip_work, radeon_flip_work_func); 522c6f73aabSFrançois Tigeot INIT_WORK(&work->unpin_work, radeon_unpin_work_func); 523c6f73aabSFrançois Tigeot 524926deccbSFrançois Tigeot work->rdev = rdev; 525926deccbSFrançois Tigeot work->crtc_id = radeon_crtc->crtc_id; 526c6f73aabSFrançois Tigeot work->event = event; 527*d78d3a22SFrançois Tigeot work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 528c6f73aabSFrançois Tigeot 529926deccbSFrançois Tigeot /* schedule unpin of the old buffer */ 530c6f73aabSFrançois Tigeot old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb); 531926deccbSFrançois Tigeot obj = old_radeon_fb->obj; 532c6f73aabSFrançois Tigeot 533926deccbSFrançois Tigeot /* take a reference to the old object */ 534926deccbSFrançois Tigeot drm_gem_object_reference(obj); 535c6f73aabSFrançois Tigeot work->old_rbo = gem_to_radeon_bo(obj); 536c6f73aabSFrançois Tigeot 537c6f73aabSFrançois Tigeot new_radeon_fb = to_radeon_framebuffer(fb); 538926deccbSFrançois Tigeot obj = new_radeon_fb->obj; 539c6f73aabSFrançois Tigeot new_rbo = gem_to_radeon_bo(obj); 540926deccbSFrançois Tigeot 541926deccbSFrançois Tigeot /* pin the new buffer */ 542c6f73aabSFrançois Tigeot DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n", 543c6f73aabSFrançois Tigeot work->old_rbo, new_rbo); 544926deccbSFrançois Tigeot 545c6f73aabSFrançois Tigeot r = radeon_bo_reserve(new_rbo, false); 546926deccbSFrançois Tigeot if (unlikely(r != 0)) { 547926deccbSFrançois Tigeot DRM_ERROR("failed to reserve new rbo buffer before flip\n"); 548c6f73aabSFrançois Tigeot goto cleanup; 549926deccbSFrançois Tigeot } 550926deccbSFrançois Tigeot /* Only 27 bit offset for legacy CRTC */ 551c6f73aabSFrançois Tigeot r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM, 552f77dbd6cSFrançois Tigeot ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, (u64 *)&base); 553926deccbSFrançois Tigeot if (unlikely(r != 0)) { 554c6f73aabSFrançois Tigeot radeon_bo_unreserve(new_rbo); 555926deccbSFrançois Tigeot r = -EINVAL; 556926deccbSFrançois Tigeot DRM_ERROR("failed to pin new rbo buffer before flip\n"); 557c6f73aabSFrançois Tigeot goto cleanup; 558926deccbSFrançois Tigeot } 5597dcf36dcSFrançois Tigeot work->fence = fence_get(reservation_object_get_excl(new_rbo->tbo.resv)); 560c6f73aabSFrançois Tigeot radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); 561c6f73aabSFrançois Tigeot radeon_bo_unreserve(new_rbo); 562926deccbSFrançois Tigeot 563926deccbSFrançois Tigeot if (!ASIC_IS_AVIVO(rdev)) { 564926deccbSFrançois Tigeot /* crtc offset is from display base addr not FB location */ 565926deccbSFrançois Tigeot base -= radeon_crtc->legacy_display_base_addr; 566926deccbSFrançois Tigeot pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8); 567926deccbSFrançois Tigeot 568926deccbSFrançois Tigeot if (tiling_flags & RADEON_TILING_MACRO) { 569926deccbSFrançois Tigeot if (ASIC_IS_R300(rdev)) { 570926deccbSFrançois Tigeot base &= ~0x7ff; 571926deccbSFrançois Tigeot } else { 572926deccbSFrançois Tigeot int byteshift = fb->bits_per_pixel >> 4; 573926deccbSFrançois Tigeot int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11; 574926deccbSFrançois Tigeot base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8); 575926deccbSFrançois Tigeot } 576926deccbSFrançois Tigeot } else { 577926deccbSFrançois Tigeot int offset = crtc->y * pitch_pixels + crtc->x; 578926deccbSFrançois Tigeot switch (fb->bits_per_pixel) { 579926deccbSFrançois Tigeot case 8: 580926deccbSFrançois Tigeot default: 581926deccbSFrançois Tigeot offset *= 1; 582926deccbSFrançois Tigeot break; 583926deccbSFrançois Tigeot case 15: 584926deccbSFrançois Tigeot case 16: 585926deccbSFrançois Tigeot offset *= 2; 586926deccbSFrançois Tigeot break; 587926deccbSFrançois Tigeot case 24: 588926deccbSFrançois Tigeot offset *= 3; 589926deccbSFrançois Tigeot break; 590926deccbSFrançois Tigeot case 32: 591926deccbSFrançois Tigeot offset *= 4; 592926deccbSFrançois Tigeot break; 593926deccbSFrançois Tigeot } 594926deccbSFrançois Tigeot base += offset; 595926deccbSFrançois Tigeot } 596926deccbSFrançois Tigeot base &= ~7; 597926deccbSFrançois Tigeot } 598c6f73aabSFrançois Tigeot work->base = base; 599926deccbSFrançois Tigeot 600c6f73aabSFrançois Tigeot r = drm_vblank_get(crtc->dev, radeon_crtc->crtc_id); 601c6f73aabSFrançois Tigeot if (r) { 602c6f73aabSFrançois Tigeot DRM_ERROR("failed to get vblank before flip\n"); 603c6f73aabSFrançois Tigeot goto pflip_cleanup; 604c6f73aabSFrançois Tigeot } 605c6f73aabSFrançois Tigeot 606c6f73aabSFrançois Tigeot /* We borrow the event spin lock for protecting flip_work */ 6077dcf36dcSFrançois Tigeot spin_lock_irqsave(&crtc->dev->event_lock, flags); 608c6f73aabSFrançois Tigeot 609c6f73aabSFrançois Tigeot if (radeon_crtc->flip_status != RADEON_FLIP_NONE) { 610c6f73aabSFrançois Tigeot DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 6117dcf36dcSFrançois Tigeot spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 612c6f73aabSFrançois Tigeot r = -EBUSY; 613c6f73aabSFrançois Tigeot goto vblank_cleanup; 614c6f73aabSFrançois Tigeot } 615c6f73aabSFrançois Tigeot radeon_crtc->flip_status = RADEON_FLIP_PENDING; 616c6f73aabSFrançois Tigeot radeon_crtc->flip_work = work; 617926deccbSFrançois Tigeot 618926deccbSFrançois Tigeot /* update crtc fb */ 619ba55f2f5SFrançois Tigeot crtc->primary->fb = fb; 620926deccbSFrançois Tigeot 6217dcf36dcSFrançois Tigeot spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 622926deccbSFrançois Tigeot 623c6f73aabSFrançois Tigeot queue_work(radeon_crtc->flip_queue, &work->flip_work); 624926deccbSFrançois Tigeot return 0; 625926deccbSFrançois Tigeot 626c6f73aabSFrançois Tigeot vblank_cleanup: 627c6f73aabSFrançois Tigeot drm_vblank_put(crtc->dev, radeon_crtc->crtc_id); 628926deccbSFrançois Tigeot 629926deccbSFrançois Tigeot pflip_cleanup: 630c6f73aabSFrançois Tigeot if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) { 631c6f73aabSFrançois Tigeot DRM_ERROR("failed to reserve new rbo in error path\n"); 632c6f73aabSFrançois Tigeot goto cleanup; 633c6f73aabSFrançois Tigeot } 634c6f73aabSFrançois Tigeot if (unlikely(radeon_bo_unpin(new_rbo) != 0)) { 635c6f73aabSFrançois Tigeot DRM_ERROR("failed to unpin new rbo in error path\n"); 636c6f73aabSFrançois Tigeot } 637c6f73aabSFrançois Tigeot radeon_bo_unreserve(new_rbo); 638c6f73aabSFrançois Tigeot 639c6f73aabSFrançois Tigeot cleanup: 640c6f73aabSFrançois Tigeot drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 6417dcf36dcSFrançois Tigeot fence_put(work->fence); 642c4ef309bSzrj kfree(work); 643926deccbSFrançois Tigeot return r; 644926deccbSFrançois Tigeot } 645926deccbSFrançois Tigeot 646c6f73aabSFrançois Tigeot static int 647c6f73aabSFrançois Tigeot radeon_crtc_set_config(struct drm_mode_set *set) 648c6f73aabSFrançois Tigeot { 649c6f73aabSFrançois Tigeot struct drm_device *dev; 650c6f73aabSFrançois Tigeot struct radeon_device *rdev; 651c6f73aabSFrançois Tigeot struct drm_crtc *crtc; 652c6f73aabSFrançois Tigeot bool active = false; 653c6f73aabSFrançois Tigeot int ret; 654c6f73aabSFrançois Tigeot 655c6f73aabSFrançois Tigeot if (!set || !set->crtc) 656c6f73aabSFrançois Tigeot return -EINVAL; 657c6f73aabSFrançois Tigeot 658c6f73aabSFrançois Tigeot dev = set->crtc->dev; 659c6f73aabSFrançois Tigeot 660c6f73aabSFrançois Tigeot #ifdef PM_TODO 661c6f73aabSFrançois Tigeot ret = pm_runtime_get_sync(dev->dev); 662c6f73aabSFrançois Tigeot if (ret < 0) 663c6f73aabSFrançois Tigeot return ret; 664c6f73aabSFrançois Tigeot #endif 665c6f73aabSFrançois Tigeot 666c6f73aabSFrançois Tigeot ret = drm_crtc_helper_set_config(set); 667c6f73aabSFrançois Tigeot 668c6f73aabSFrançois Tigeot list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 669c6f73aabSFrançois Tigeot if (crtc->enabled) 670c6f73aabSFrançois Tigeot active = true; 671c6f73aabSFrançois Tigeot 672c6f73aabSFrançois Tigeot #ifdef PM_TODO 673c6f73aabSFrançois Tigeot pm_runtime_mark_last_busy(dev->dev); 674c6f73aabSFrançois Tigeot #endif 675c6f73aabSFrançois Tigeot 676c6f73aabSFrançois Tigeot rdev = dev->dev_private; 677c6f73aabSFrançois Tigeot /* if we have active crtcs and we don't have a power ref, 678c6f73aabSFrançois Tigeot take the current one */ 679c6f73aabSFrançois Tigeot if (active && !rdev->have_disp_power_ref) { 680c6f73aabSFrançois Tigeot rdev->have_disp_power_ref = true; 681c6f73aabSFrançois Tigeot return ret; 682c6f73aabSFrançois Tigeot } 683c6f73aabSFrançois Tigeot /* if we have no active crtcs, then drop the power ref 684c6f73aabSFrançois Tigeot we got before */ 685c6f73aabSFrançois Tigeot if (!active && rdev->have_disp_power_ref) { 686c6f73aabSFrançois Tigeot #ifdef PM_TODO 687c6f73aabSFrançois Tigeot pm_runtime_put_autosuspend(dev->dev); 688c6f73aabSFrançois Tigeot #endif 689c6f73aabSFrançois Tigeot rdev->have_disp_power_ref = false; 690c6f73aabSFrançois Tigeot } 691c6f73aabSFrançois Tigeot 692c6f73aabSFrançois Tigeot /* drop the power reference we got coming in here */ 693c6f73aabSFrançois Tigeot #ifdef PM_TODO 694c6f73aabSFrançois Tigeot pm_runtime_put_autosuspend(dev->dev); 695c6f73aabSFrançois Tigeot #endif 696c6f73aabSFrançois Tigeot return ret; 697c6f73aabSFrançois Tigeot } 698926deccbSFrançois Tigeot static const struct drm_crtc_funcs radeon_crtc_funcs = { 6997dcf36dcSFrançois Tigeot .cursor_set2 = radeon_crtc_cursor_set2, 700926deccbSFrançois Tigeot .cursor_move = radeon_crtc_cursor_move, 701926deccbSFrançois Tigeot .gamma_set = radeon_crtc_gamma_set, 702c6f73aabSFrançois Tigeot .set_config = radeon_crtc_set_config, 703926deccbSFrançois Tigeot .destroy = radeon_crtc_destroy, 704926deccbSFrançois Tigeot .page_flip = radeon_crtc_page_flip, 705926deccbSFrançois Tigeot }; 706926deccbSFrançois Tigeot 707926deccbSFrançois Tigeot static void radeon_crtc_init(struct drm_device *dev, int index) 708926deccbSFrançois Tigeot { 709926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 710926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc; 711926deccbSFrançois Tigeot int i; 712926deccbSFrançois Tigeot 713c4ef309bSzrj radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 714926deccbSFrançois Tigeot if (radeon_crtc == NULL) 715926deccbSFrançois Tigeot return; 716926deccbSFrançois Tigeot 717926deccbSFrançois Tigeot drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); 718926deccbSFrançois Tigeot 719926deccbSFrançois Tigeot drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); 720926deccbSFrançois Tigeot radeon_crtc->crtc_id = index; 721c6f73aabSFrançois Tigeot radeon_crtc->flip_queue = create_singlethread_workqueue("radeon-crtc"); 722926deccbSFrançois Tigeot rdev->mode_info.crtcs[index] = radeon_crtc; 723926deccbSFrançois Tigeot 72457e252bfSMichael Neumann if (rdev->family >= CHIP_BONAIRE) { 72557e252bfSMichael Neumann radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH; 72657e252bfSMichael Neumann radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT; 72757e252bfSMichael Neumann } else { 72857e252bfSMichael Neumann radeon_crtc->max_cursor_width = CURSOR_WIDTH; 72957e252bfSMichael Neumann radeon_crtc->max_cursor_height = CURSOR_HEIGHT; 73057e252bfSMichael Neumann } 731c6f73aabSFrançois Tigeot dev->mode_config.cursor_width = radeon_crtc->max_cursor_width; 732c6f73aabSFrançois Tigeot dev->mode_config.cursor_height = radeon_crtc->max_cursor_height; 73357e252bfSMichael Neumann 734926deccbSFrançois Tigeot #if 0 735926deccbSFrançois Tigeot radeon_crtc->mode_set.crtc = &radeon_crtc->base; 736926deccbSFrançois Tigeot radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); 737926deccbSFrançois Tigeot radeon_crtc->mode_set.num_connectors = 0; 738926deccbSFrançois Tigeot #endif 739926deccbSFrançois Tigeot 740926deccbSFrançois Tigeot for (i = 0; i < 256; i++) { 741926deccbSFrançois Tigeot radeon_crtc->lut_r[i] = i << 2; 742926deccbSFrançois Tigeot radeon_crtc->lut_g[i] = i << 2; 743926deccbSFrançois Tigeot radeon_crtc->lut_b[i] = i << 2; 744926deccbSFrançois Tigeot } 745926deccbSFrançois Tigeot 746926deccbSFrançois Tigeot if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) 747926deccbSFrançois Tigeot radeon_atombios_init_crtc(dev, radeon_crtc); 748926deccbSFrançois Tigeot else 749926deccbSFrançois Tigeot radeon_legacy_init_crtc(dev, radeon_crtc); 750926deccbSFrançois Tigeot } 751926deccbSFrançois Tigeot 75257e252bfSMichael Neumann static const char *encoder_names[38] = { 753926deccbSFrançois Tigeot "NONE", 754926deccbSFrançois Tigeot "INTERNAL_LVDS", 755926deccbSFrançois Tigeot "INTERNAL_TMDS1", 756926deccbSFrançois Tigeot "INTERNAL_TMDS2", 757926deccbSFrançois Tigeot "INTERNAL_DAC1", 758926deccbSFrançois Tigeot "INTERNAL_DAC2", 759926deccbSFrançois Tigeot "INTERNAL_SDVOA", 760926deccbSFrançois Tigeot "INTERNAL_SDVOB", 761926deccbSFrançois Tigeot "SI170B", 762926deccbSFrançois Tigeot "CH7303", 763926deccbSFrançois Tigeot "CH7301", 764926deccbSFrançois Tigeot "INTERNAL_DVO1", 765926deccbSFrançois Tigeot "EXTERNAL_SDVOA", 766926deccbSFrançois Tigeot "EXTERNAL_SDVOB", 767926deccbSFrançois Tigeot "TITFP513", 768926deccbSFrançois Tigeot "INTERNAL_LVTM1", 769926deccbSFrançois Tigeot "VT1623", 770926deccbSFrançois Tigeot "HDMI_SI1930", 771926deccbSFrançois Tigeot "HDMI_INTERNAL", 772926deccbSFrançois Tigeot "INTERNAL_KLDSCP_TMDS1", 773926deccbSFrançois Tigeot "INTERNAL_KLDSCP_DVO1", 774926deccbSFrançois Tigeot "INTERNAL_KLDSCP_DAC1", 775926deccbSFrançois Tigeot "INTERNAL_KLDSCP_DAC2", 776926deccbSFrançois Tigeot "SI178", 777926deccbSFrançois Tigeot "MVPU_FPGA", 778926deccbSFrançois Tigeot "INTERNAL_DDI", 779926deccbSFrançois Tigeot "VT1625", 780926deccbSFrançois Tigeot "HDMI_SI1932", 781926deccbSFrançois Tigeot "DP_AN9801", 782926deccbSFrançois Tigeot "DP_DP501", 783926deccbSFrançois Tigeot "INTERNAL_UNIPHY", 784926deccbSFrançois Tigeot "INTERNAL_KLDSCP_LVTMA", 785926deccbSFrançois Tigeot "INTERNAL_UNIPHY1", 786926deccbSFrançois Tigeot "INTERNAL_UNIPHY2", 787926deccbSFrançois Tigeot "NUTMEG", 788926deccbSFrançois Tigeot "TRAVIS", 78957e252bfSMichael Neumann "INTERNAL_VCE", 79057e252bfSMichael Neumann "INTERNAL_UNIPHY3", 791926deccbSFrançois Tigeot }; 792926deccbSFrançois Tigeot 793926deccbSFrançois Tigeot static const char *hpd_names[6] = { 794926deccbSFrançois Tigeot "HPD1", 795926deccbSFrançois Tigeot "HPD2", 796926deccbSFrançois Tigeot "HPD3", 797926deccbSFrançois Tigeot "HPD4", 798926deccbSFrançois Tigeot "HPD5", 799926deccbSFrançois Tigeot "HPD6", 800926deccbSFrançois Tigeot }; 801926deccbSFrançois Tigeot 802926deccbSFrançois Tigeot static void radeon_print_display_setup(struct drm_device *dev) 803926deccbSFrançois Tigeot { 804926deccbSFrançois Tigeot struct drm_connector *connector; 805926deccbSFrançois Tigeot struct radeon_connector *radeon_connector; 806926deccbSFrançois Tigeot struct drm_encoder *encoder; 807926deccbSFrançois Tigeot struct radeon_encoder *radeon_encoder; 808926deccbSFrançois Tigeot uint32_t devices; 809926deccbSFrançois Tigeot int i = 0; 810926deccbSFrançois Tigeot 811926deccbSFrançois Tigeot DRM_INFO("Radeon Display Connectors\n"); 812926deccbSFrançois Tigeot list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 813926deccbSFrançois Tigeot radeon_connector = to_radeon_connector(connector); 814926deccbSFrançois Tigeot DRM_INFO("Connector %d:\n", i); 815ba55f2f5SFrançois Tigeot DRM_INFO(" %s\n", connector->name); 816926deccbSFrançois Tigeot if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 817926deccbSFrançois Tigeot DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); 818926deccbSFrançois Tigeot if (radeon_connector->ddc_bus) { 819926deccbSFrançois Tigeot DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 820926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.mask_clk_reg, 821926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.mask_data_reg, 822926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.a_clk_reg, 823926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.a_data_reg, 824926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.en_clk_reg, 825926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.en_data_reg, 826926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.y_clk_reg, 827926deccbSFrançois Tigeot radeon_connector->ddc_bus->rec.y_data_reg); 828926deccbSFrançois Tigeot if (radeon_connector->router.ddc_valid) 829926deccbSFrançois Tigeot DRM_INFO(" DDC Router 0x%x/0x%x\n", 830926deccbSFrançois Tigeot radeon_connector->router.ddc_mux_control_pin, 831926deccbSFrançois Tigeot radeon_connector->router.ddc_mux_state); 832926deccbSFrançois Tigeot if (radeon_connector->router.cd_valid) 833926deccbSFrançois Tigeot DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 834926deccbSFrançois Tigeot radeon_connector->router.cd_mux_control_pin, 835926deccbSFrançois Tigeot radeon_connector->router.cd_mux_state); 836926deccbSFrançois Tigeot } else { 837926deccbSFrançois Tigeot if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 838926deccbSFrançois Tigeot connector->connector_type == DRM_MODE_CONNECTOR_DVII || 839926deccbSFrançois Tigeot connector->connector_type == DRM_MODE_CONNECTOR_DVID || 840926deccbSFrançois Tigeot connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 841926deccbSFrançois Tigeot connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 842926deccbSFrançois Tigeot connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 843926deccbSFrançois Tigeot DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 844926deccbSFrançois Tigeot } 845926deccbSFrançois Tigeot DRM_INFO(" Encoders:\n"); 846926deccbSFrançois Tigeot list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 847926deccbSFrançois Tigeot radeon_encoder = to_radeon_encoder(encoder); 848926deccbSFrançois Tigeot devices = radeon_encoder->devices & radeon_connector->devices; 849926deccbSFrançois Tigeot if (devices) { 850926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_CRT1_SUPPORT) 851926deccbSFrançois Tigeot DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); 852926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_CRT2_SUPPORT) 853926deccbSFrançois Tigeot DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); 854926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_LCD1_SUPPORT) 855926deccbSFrançois Tigeot DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); 856926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP1_SUPPORT) 857926deccbSFrançois Tigeot DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); 858926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP2_SUPPORT) 859926deccbSFrançois Tigeot DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); 860926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP3_SUPPORT) 861926deccbSFrançois Tigeot DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); 862926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP4_SUPPORT) 863926deccbSFrançois Tigeot DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); 864926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP5_SUPPORT) 865926deccbSFrançois Tigeot DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); 866926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_DFP6_SUPPORT) 867926deccbSFrançois Tigeot DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); 868926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_TV1_SUPPORT) 869926deccbSFrançois Tigeot DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); 870926deccbSFrançois Tigeot if (devices & ATOM_DEVICE_CV_SUPPORT) 871926deccbSFrançois Tigeot DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); 872926deccbSFrançois Tigeot } 873926deccbSFrançois Tigeot } 874926deccbSFrançois Tigeot i++; 875926deccbSFrançois Tigeot } 876926deccbSFrançois Tigeot } 877926deccbSFrançois Tigeot 878926deccbSFrançois Tigeot static bool radeon_setup_enc_conn(struct drm_device *dev) 879926deccbSFrançois Tigeot { 880926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 881926deccbSFrançois Tigeot bool ret = false; 882926deccbSFrançois Tigeot 883926deccbSFrançois Tigeot if (rdev->bios) { 884926deccbSFrançois Tigeot if (rdev->is_atom_bios) { 885926deccbSFrançois Tigeot ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); 886926deccbSFrançois Tigeot if (ret == false) 887926deccbSFrançois Tigeot ret = radeon_get_atom_connector_info_from_object_table(dev); 888926deccbSFrançois Tigeot } else { 889926deccbSFrançois Tigeot ret = radeon_get_legacy_connector_info_from_bios(dev); 890926deccbSFrançois Tigeot if (ret == false) 891926deccbSFrançois Tigeot ret = radeon_get_legacy_connector_info_from_table(dev); 892926deccbSFrançois Tigeot } 893926deccbSFrançois Tigeot } else { 894926deccbSFrançois Tigeot if (!ASIC_IS_AVIVO(rdev)) 895926deccbSFrançois Tigeot ret = radeon_get_legacy_connector_info_from_table(dev); 896926deccbSFrançois Tigeot } 897926deccbSFrançois Tigeot if (ret) { 898926deccbSFrançois Tigeot radeon_setup_encoder_clones(dev); 899926deccbSFrançois Tigeot radeon_print_display_setup(dev); 900926deccbSFrançois Tigeot } 901926deccbSFrançois Tigeot 902926deccbSFrançois Tigeot return ret; 903926deccbSFrançois Tigeot } 904926deccbSFrançois Tigeot 905926deccbSFrançois Tigeot /* avivo */ 906c6f73aabSFrançois Tigeot 907c6f73aabSFrançois Tigeot /** 908c6f73aabSFrançois Tigeot * avivo_reduce_ratio - fractional number reduction 909c6f73aabSFrançois Tigeot * 910c6f73aabSFrançois Tigeot * @nom: nominator 911c6f73aabSFrançois Tigeot * @den: denominator 912c6f73aabSFrançois Tigeot * @nom_min: minimum value for nominator 913c6f73aabSFrançois Tigeot * @den_min: minimum value for denominator 914c6f73aabSFrançois Tigeot * 915c6f73aabSFrançois Tigeot * Find the greatest common divisor and apply it on both nominator and 916c6f73aabSFrançois Tigeot * denominator, but make nominator and denominator are at least as large 917c6f73aabSFrançois Tigeot * as their minimum values. 918c6f73aabSFrançois Tigeot */ 919c6f73aabSFrançois Tigeot static void avivo_reduce_ratio(unsigned *nom, unsigned *den, 920c6f73aabSFrançois Tigeot unsigned nom_min, unsigned den_min) 921926deccbSFrançois Tigeot { 922c6f73aabSFrançois Tigeot unsigned tmp; 923926deccbSFrançois Tigeot 924c6f73aabSFrançois Tigeot /* reduce the numbers to a simpler ratio */ 925c59a5c48SFrançois Tigeot tmp = gcd(*nom, *den); 926c6f73aabSFrançois Tigeot *nom /= tmp; 927c6f73aabSFrançois Tigeot *den /= tmp; 928926deccbSFrançois Tigeot 929c6f73aabSFrançois Tigeot /* make sure nominator is large enough */ 930c6f73aabSFrançois Tigeot if (*nom < nom_min) { 931c6f73aabSFrançois Tigeot tmp = DIV_ROUND_UP(nom_min, *nom); 932c6f73aabSFrançois Tigeot *nom *= tmp; 933c6f73aabSFrançois Tigeot *den *= tmp; 934926deccbSFrançois Tigeot } 935926deccbSFrançois Tigeot 936c6f73aabSFrançois Tigeot /* make sure the denominator is large enough */ 937c6f73aabSFrançois Tigeot if (*den < den_min) { 938c6f73aabSFrançois Tigeot tmp = DIV_ROUND_UP(den_min, *den); 939c6f73aabSFrançois Tigeot *nom *= tmp; 940c6f73aabSFrançois Tigeot *den *= tmp; 941c6f73aabSFrançois Tigeot } 942c6f73aabSFrançois Tigeot } 943c6f73aabSFrançois Tigeot 944c6f73aabSFrançois Tigeot /** 945c6f73aabSFrançois Tigeot * avivo_get_fb_ref_div - feedback and ref divider calculation 946c6f73aabSFrançois Tigeot * 947c6f73aabSFrançois Tigeot * @nom: nominator 948c6f73aabSFrançois Tigeot * @den: denominator 949c6f73aabSFrançois Tigeot * @post_div: post divider 950c6f73aabSFrançois Tigeot * @fb_div_max: feedback divider maximum 951c6f73aabSFrançois Tigeot * @ref_div_max: reference divider maximum 952c6f73aabSFrançois Tigeot * @fb_div: resulting feedback divider 953c6f73aabSFrançois Tigeot * @ref_div: resulting reference divider 954c6f73aabSFrançois Tigeot * 955c6f73aabSFrançois Tigeot * Calculate feedback and reference divider for a given post divider. Makes 956c6f73aabSFrançois Tigeot * sure we stay within the limits. 957c6f73aabSFrançois Tigeot */ 958c6f73aabSFrançois Tigeot static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, 959c6f73aabSFrançois Tigeot unsigned fb_div_max, unsigned ref_div_max, 960c6f73aabSFrançois Tigeot unsigned *fb_div, unsigned *ref_div) 961926deccbSFrançois Tigeot { 962c6f73aabSFrançois Tigeot /* limit reference * post divider to a maximum */ 963c6f73aabSFrançois Tigeot ref_div_max = max(min(100 / post_div, ref_div_max), 1u); 964926deccbSFrançois Tigeot 965c6f73aabSFrançois Tigeot /* get matching reference and feedback divider */ 966c6f73aabSFrançois Tigeot *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); 967c6f73aabSFrançois Tigeot *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); 968926deccbSFrançois Tigeot 969c6f73aabSFrançois Tigeot /* limit fb divider to its maximum */ 970c6f73aabSFrançois Tigeot if (*fb_div > fb_div_max) { 971c6f73aabSFrançois Tigeot *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); 972c6f73aabSFrançois Tigeot *fb_div = fb_div_max; 973c6f73aabSFrançois Tigeot } 974926deccbSFrançois Tigeot } 975926deccbSFrançois Tigeot 976c6f73aabSFrançois Tigeot /** 977c6f73aabSFrançois Tigeot * radeon_compute_pll_avivo - compute PLL paramaters 978c6f73aabSFrançois Tigeot * 979c6f73aabSFrançois Tigeot * @pll: information about the PLL 980c6f73aabSFrançois Tigeot * @dot_clock_p: resulting pixel clock 981c6f73aabSFrançois Tigeot * fb_div_p: resulting feedback divider 982c6f73aabSFrançois Tigeot * frac_fb_div_p: fractional part of the feedback divider 983c6f73aabSFrançois Tigeot * ref_div_p: resulting reference divider 984c6f73aabSFrançois Tigeot * post_div_p: resulting reference divider 985c6f73aabSFrançois Tigeot * 986c6f73aabSFrançois Tigeot * Try to calculate the PLL parameters to generate the given frequency: 987c6f73aabSFrançois Tigeot * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div) 988c6f73aabSFrançois Tigeot */ 989926deccbSFrançois Tigeot void radeon_compute_pll_avivo(struct radeon_pll *pll, 990926deccbSFrançois Tigeot u32 freq, 991926deccbSFrançois Tigeot u32 *dot_clock_p, 992926deccbSFrançois Tigeot u32 *fb_div_p, 993926deccbSFrançois Tigeot u32 *frac_fb_div_p, 994926deccbSFrançois Tigeot u32 *ref_div_p, 995926deccbSFrançois Tigeot u32 *post_div_p) 996926deccbSFrançois Tigeot { 997c6f73aabSFrançois Tigeot unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? 998c6f73aabSFrançois Tigeot freq : freq / 10; 999926deccbSFrançois Tigeot 1000c6f73aabSFrançois Tigeot unsigned fb_div_min, fb_div_max, fb_div; 1001c6f73aabSFrançois Tigeot unsigned post_div_min, post_div_max, post_div; 1002c6f73aabSFrançois Tigeot unsigned ref_div_min, ref_div_max, ref_div; 1003c6f73aabSFrançois Tigeot unsigned post_div_best, diff_best; 1004c6f73aabSFrançois Tigeot unsigned nom, den; 1005c6f73aabSFrançois Tigeot 1006c6f73aabSFrançois Tigeot /* determine allowed feedback divider range */ 1007c6f73aabSFrançois Tigeot fb_div_min = pll->min_feedback_div; 1008c6f73aabSFrançois Tigeot fb_div_max = pll->max_feedback_div; 1009926deccbSFrançois Tigeot 1010926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1011c6f73aabSFrançois Tigeot fb_div_min *= 10; 1012c6f73aabSFrançois Tigeot fb_div_max *= 10; 1013926deccbSFrançois Tigeot } 1014926deccbSFrançois Tigeot 1015c6f73aabSFrançois Tigeot /* determine allowed ref divider range */ 1016c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_REF_DIV) 1017c6f73aabSFrançois Tigeot ref_div_min = pll->reference_div; 1018926deccbSFrançois Tigeot else 1019c6f73aabSFrançois Tigeot ref_div_min = pll->min_ref_div; 1020c6f73aabSFrançois Tigeot 1021c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && 1022c6f73aabSFrançois Tigeot pll->flags & RADEON_PLL_USE_REF_DIV) 1023c6f73aabSFrançois Tigeot ref_div_max = pll->reference_div; 10247dcf36dcSFrançois Tigeot else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 10257dcf36dcSFrançois Tigeot /* fix for problems on RS880 */ 10267dcf36dcSFrançois Tigeot ref_div_max = min(pll->max_ref_div, 7u); 1027c6f73aabSFrançois Tigeot else 1028c6f73aabSFrançois Tigeot ref_div_max = pll->max_ref_div; 1029c6f73aabSFrançois Tigeot 1030c6f73aabSFrançois Tigeot /* determine allowed post divider range */ 1031c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_POST_DIV) { 1032c6f73aabSFrançois Tigeot post_div_min = pll->post_div; 1033c6f73aabSFrançois Tigeot post_div_max = pll->post_div; 1034c6f73aabSFrançois Tigeot } else { 1035c6f73aabSFrançois Tigeot unsigned vco_min, vco_max; 1036c6f73aabSFrançois Tigeot 1037c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_IS_LCD) { 1038c6f73aabSFrançois Tigeot vco_min = pll->lcd_pll_out_min; 1039c6f73aabSFrançois Tigeot vco_max = pll->lcd_pll_out_max; 1040c6f73aabSFrançois Tigeot } else { 1041c6f73aabSFrançois Tigeot vco_min = pll->pll_out_min; 1042c6f73aabSFrançois Tigeot vco_max = pll->pll_out_max; 1043c6f73aabSFrançois Tigeot } 1044c6f73aabSFrançois Tigeot 1045c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1046c6f73aabSFrançois Tigeot vco_min *= 10; 1047c6f73aabSFrançois Tigeot vco_max *= 10; 1048c6f73aabSFrançois Tigeot } 1049c6f73aabSFrançois Tigeot 1050c6f73aabSFrançois Tigeot post_div_min = vco_min / target_clock; 1051c6f73aabSFrançois Tigeot if ((target_clock * post_div_min) < vco_min) 1052c6f73aabSFrançois Tigeot ++post_div_min; 1053c6f73aabSFrançois Tigeot if (post_div_min < pll->min_post_div) 1054c6f73aabSFrançois Tigeot post_div_min = pll->min_post_div; 1055c6f73aabSFrançois Tigeot 1056c6f73aabSFrançois Tigeot post_div_max = vco_max / target_clock; 1057c6f73aabSFrançois Tigeot if ((target_clock * post_div_max) > vco_max) 1058c6f73aabSFrançois Tigeot --post_div_max; 1059c6f73aabSFrançois Tigeot if (post_div_max > pll->max_post_div) 1060c6f73aabSFrançois Tigeot post_div_max = pll->max_post_div; 1061c6f73aabSFrançois Tigeot } 1062c6f73aabSFrançois Tigeot 1063c6f73aabSFrançois Tigeot /* represent the searched ratio as fractional number */ 1064c6f73aabSFrançois Tigeot nom = target_clock; 1065c6f73aabSFrançois Tigeot den = pll->reference_freq; 1066c6f73aabSFrançois Tigeot 1067c6f73aabSFrançois Tigeot /* reduce the numbers to a simpler ratio */ 1068c6f73aabSFrançois Tigeot avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min); 1069c6f73aabSFrançois Tigeot 1070c6f73aabSFrançois Tigeot /* now search for a post divider */ 1071c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 1072c6f73aabSFrançois Tigeot post_div_best = post_div_min; 1073c6f73aabSFrançois Tigeot else 1074c6f73aabSFrançois Tigeot post_div_best = post_div_max; 1075c6f73aabSFrançois Tigeot diff_best = ~0; 1076c6f73aabSFrançois Tigeot 1077c6f73aabSFrançois Tigeot for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { 1078c6f73aabSFrançois Tigeot unsigned diff; 1079c6f73aabSFrançois Tigeot avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, 1080c6f73aabSFrançois Tigeot ref_div_max, &fb_div, &ref_div); 1081c6f73aabSFrançois Tigeot diff = abs(target_clock - (pll->reference_freq * fb_div) / 1082c6f73aabSFrançois Tigeot (ref_div * post_div)); 1083c6f73aabSFrançois Tigeot 1084c6f73aabSFrançois Tigeot if (diff < diff_best || (diff == diff_best && 1085c6f73aabSFrançois Tigeot !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) { 1086c6f73aabSFrançois Tigeot 1087c6f73aabSFrançois Tigeot post_div_best = post_div; 1088c6f73aabSFrançois Tigeot diff_best = diff; 1089c6f73aabSFrançois Tigeot } 1090c6f73aabSFrançois Tigeot } 1091c6f73aabSFrançois Tigeot post_div = post_div_best; 1092c6f73aabSFrançois Tigeot 1093c6f73aabSFrançois Tigeot /* get the feedback and reference divider for the optimal value */ 1094c6f73aabSFrançois Tigeot avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max, 1095c6f73aabSFrançois Tigeot &fb_div, &ref_div); 1096c6f73aabSFrançois Tigeot 1097c6f73aabSFrançois Tigeot /* reduce the numbers to a simpler ratio once more */ 1098c6f73aabSFrançois Tigeot /* this also makes sure that the reference divider is large enough */ 1099c6f73aabSFrançois Tigeot avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); 1100c6f73aabSFrançois Tigeot 1101c6f73aabSFrançois Tigeot /* avoid high jitter with small fractional dividers */ 1102c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { 1103c6f73aabSFrançois Tigeot fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50); 1104c6f73aabSFrançois Tigeot if (fb_div < fb_div_min) { 1105c6f73aabSFrançois Tigeot unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div); 1106c6f73aabSFrançois Tigeot fb_div *= tmp; 1107c6f73aabSFrançois Tigeot ref_div *= tmp; 1108926deccbSFrançois Tigeot } 1109926deccbSFrançois Tigeot } 1110926deccbSFrançois Tigeot 1111c6f73aabSFrançois Tigeot /* and finally save the result */ 1112c6f73aabSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1113c6f73aabSFrançois Tigeot *fb_div_p = fb_div / 10; 1114c6f73aabSFrançois Tigeot *frac_fb_div_p = fb_div % 10; 1115c6f73aabSFrançois Tigeot } else { 1116926deccbSFrançois Tigeot *fb_div_p = fb_div; 1117c6f73aabSFrançois Tigeot *frac_fb_div_p = 0; 1118c6f73aabSFrançois Tigeot } 1119c6f73aabSFrançois Tigeot 1120c6f73aabSFrançois Tigeot *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + 1121c6f73aabSFrançois Tigeot (pll->reference_freq * *frac_fb_div_p)) / 1122c6f73aabSFrançois Tigeot (ref_div * post_div * 10); 1123926deccbSFrançois Tigeot *ref_div_p = ref_div; 1124926deccbSFrançois Tigeot *post_div_p = post_div; 1125c6f73aabSFrançois Tigeot 1126c6f73aabSFrançois Tigeot DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1127c6f73aabSFrançois Tigeot freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, 1128c6f73aabSFrançois Tigeot ref_div, post_div); 1129926deccbSFrançois Tigeot } 1130926deccbSFrançois Tigeot 1131926deccbSFrançois Tigeot /* pre-avivo */ 1132926deccbSFrançois Tigeot static inline uint32_t radeon_div(uint64_t n, uint32_t d) 1133926deccbSFrançois Tigeot { 1134926deccbSFrançois Tigeot uint64_t mod; 1135926deccbSFrançois Tigeot 1136926deccbSFrançois Tigeot n += d / 2; 1137926deccbSFrançois Tigeot 1138926deccbSFrançois Tigeot mod = do_div(n, d); 1139926deccbSFrançois Tigeot return n; 1140926deccbSFrançois Tigeot } 1141926deccbSFrançois Tigeot 1142926deccbSFrançois Tigeot void radeon_compute_pll_legacy(struct radeon_pll *pll, 1143926deccbSFrançois Tigeot uint64_t freq, 1144926deccbSFrançois Tigeot uint32_t *dot_clock_p, 1145926deccbSFrançois Tigeot uint32_t *fb_div_p, 1146926deccbSFrançois Tigeot uint32_t *frac_fb_div_p, 1147926deccbSFrançois Tigeot uint32_t *ref_div_p, 1148926deccbSFrançois Tigeot uint32_t *post_div_p) 1149926deccbSFrançois Tigeot { 1150926deccbSFrançois Tigeot uint32_t min_ref_div = pll->min_ref_div; 1151926deccbSFrançois Tigeot uint32_t max_ref_div = pll->max_ref_div; 1152926deccbSFrançois Tigeot uint32_t min_post_div = pll->min_post_div; 1153926deccbSFrançois Tigeot uint32_t max_post_div = pll->max_post_div; 1154926deccbSFrançois Tigeot uint32_t min_fractional_feed_div = 0; 1155926deccbSFrançois Tigeot uint32_t max_fractional_feed_div = 0; 1156926deccbSFrançois Tigeot uint32_t best_vco = pll->best_vco; 1157926deccbSFrançois Tigeot uint32_t best_post_div = 1; 1158926deccbSFrançois Tigeot uint32_t best_ref_div = 1; 1159926deccbSFrançois Tigeot uint32_t best_feedback_div = 1; 1160926deccbSFrançois Tigeot uint32_t best_frac_feedback_div = 0; 1161926deccbSFrançois Tigeot uint32_t best_freq = -1; 1162926deccbSFrançois Tigeot uint32_t best_error = 0xffffffff; 1163926deccbSFrançois Tigeot uint32_t best_vco_diff = 1; 1164926deccbSFrançois Tigeot uint32_t post_div; 1165926deccbSFrançois Tigeot u32 pll_out_min, pll_out_max; 1166926deccbSFrançois Tigeot 11674cd92098Szrj DRM_DEBUG_KMS("PLL freq %ju %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); 1168926deccbSFrançois Tigeot freq = freq * 1000; 1169926deccbSFrançois Tigeot 1170926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_IS_LCD) { 1171926deccbSFrançois Tigeot pll_out_min = pll->lcd_pll_out_min; 1172926deccbSFrançois Tigeot pll_out_max = pll->lcd_pll_out_max; 1173926deccbSFrançois Tigeot } else { 1174926deccbSFrançois Tigeot pll_out_min = pll->pll_out_min; 1175926deccbSFrançois Tigeot pll_out_max = pll->pll_out_max; 1176926deccbSFrançois Tigeot } 1177926deccbSFrançois Tigeot 1178926deccbSFrançois Tigeot if (pll_out_min > 64800) 1179926deccbSFrançois Tigeot pll_out_min = 64800; 1180926deccbSFrançois Tigeot 1181926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_REF_DIV) 1182926deccbSFrançois Tigeot min_ref_div = max_ref_div = pll->reference_div; 1183926deccbSFrançois Tigeot else { 1184926deccbSFrançois Tigeot while (min_ref_div < max_ref_div-1) { 1185926deccbSFrançois Tigeot uint32_t mid = (min_ref_div + max_ref_div) / 2; 1186926deccbSFrançois Tigeot uint32_t pll_in = pll->reference_freq / mid; 1187926deccbSFrançois Tigeot if (pll_in < pll->pll_in_min) 1188926deccbSFrançois Tigeot max_ref_div = mid; 1189926deccbSFrançois Tigeot else if (pll_in > pll->pll_in_max) 1190926deccbSFrançois Tigeot min_ref_div = mid; 1191926deccbSFrançois Tigeot else 1192926deccbSFrançois Tigeot break; 1193926deccbSFrançois Tigeot } 1194926deccbSFrançois Tigeot } 1195926deccbSFrançois Tigeot 1196926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_POST_DIV) 1197926deccbSFrançois Tigeot min_post_div = max_post_div = pll->post_div; 1198926deccbSFrançois Tigeot 1199926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1200926deccbSFrançois Tigeot min_fractional_feed_div = pll->min_frac_feedback_div; 1201926deccbSFrançois Tigeot max_fractional_feed_div = pll->max_frac_feedback_div; 1202926deccbSFrançois Tigeot } 1203926deccbSFrançois Tigeot 1204926deccbSFrançois Tigeot for (post_div = max_post_div; post_div >= min_post_div; --post_div) { 1205926deccbSFrançois Tigeot uint32_t ref_div; 1206926deccbSFrançois Tigeot 1207926deccbSFrançois Tigeot if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 1208926deccbSFrançois Tigeot continue; 1209926deccbSFrançois Tigeot 1210926deccbSFrançois Tigeot /* legacy radeons only have a few post_divs */ 1211926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_LEGACY) { 1212926deccbSFrançois Tigeot if ((post_div == 5) || 1213926deccbSFrançois Tigeot (post_div == 7) || 1214926deccbSFrançois Tigeot (post_div == 9) || 1215926deccbSFrançois Tigeot (post_div == 10) || 1216926deccbSFrançois Tigeot (post_div == 11) || 1217926deccbSFrançois Tigeot (post_div == 13) || 1218926deccbSFrançois Tigeot (post_div == 14) || 1219926deccbSFrançois Tigeot (post_div == 15)) 1220926deccbSFrançois Tigeot continue; 1221926deccbSFrançois Tigeot } 1222926deccbSFrançois Tigeot 1223926deccbSFrançois Tigeot for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { 1224926deccbSFrançois Tigeot uint32_t feedback_div, current_freq = 0, error, vco_diff; 1225926deccbSFrançois Tigeot uint32_t pll_in = pll->reference_freq / ref_div; 1226926deccbSFrançois Tigeot uint32_t min_feed_div = pll->min_feedback_div; 1227926deccbSFrançois Tigeot uint32_t max_feed_div = pll->max_feedback_div + 1; 1228926deccbSFrançois Tigeot 1229926deccbSFrançois Tigeot if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) 1230926deccbSFrançois Tigeot continue; 1231926deccbSFrançois Tigeot 1232926deccbSFrançois Tigeot while (min_feed_div < max_feed_div) { 1233926deccbSFrançois Tigeot uint32_t vco; 1234926deccbSFrançois Tigeot uint32_t min_frac_feed_div = min_fractional_feed_div; 1235926deccbSFrançois Tigeot uint32_t max_frac_feed_div = max_fractional_feed_div + 1; 1236926deccbSFrançois Tigeot uint32_t frac_feedback_div; 1237926deccbSFrançois Tigeot uint64_t tmp; 1238926deccbSFrançois Tigeot 1239926deccbSFrançois Tigeot feedback_div = (min_feed_div + max_feed_div) / 2; 1240926deccbSFrançois Tigeot 1241926deccbSFrançois Tigeot tmp = (uint64_t)pll->reference_freq * feedback_div; 1242926deccbSFrançois Tigeot vco = radeon_div(tmp, ref_div); 1243926deccbSFrançois Tigeot 1244926deccbSFrançois Tigeot if (vco < pll_out_min) { 1245926deccbSFrançois Tigeot min_feed_div = feedback_div + 1; 1246926deccbSFrançois Tigeot continue; 1247926deccbSFrançois Tigeot } else if (vco > pll_out_max) { 1248926deccbSFrançois Tigeot max_feed_div = feedback_div; 1249926deccbSFrançois Tigeot continue; 1250926deccbSFrançois Tigeot } 1251926deccbSFrançois Tigeot 1252926deccbSFrançois Tigeot while (min_frac_feed_div < max_frac_feed_div) { 1253926deccbSFrançois Tigeot frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; 1254926deccbSFrançois Tigeot tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; 1255926deccbSFrançois Tigeot tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; 1256926deccbSFrançois Tigeot current_freq = radeon_div(tmp, ref_div * post_div); 1257926deccbSFrançois Tigeot 1258926deccbSFrançois Tigeot if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 1259926deccbSFrançois Tigeot if (freq < current_freq) 1260926deccbSFrançois Tigeot error = 0xffffffff; 1261926deccbSFrançois Tigeot else 1262926deccbSFrançois Tigeot error = freq - current_freq; 1263926deccbSFrançois Tigeot } else 1264926deccbSFrançois Tigeot error = abs(current_freq - freq); 1265926deccbSFrançois Tigeot vco_diff = abs(vco - best_vco); 1266926deccbSFrançois Tigeot 1267926deccbSFrançois Tigeot if ((best_vco == 0 && error < best_error) || 1268926deccbSFrançois Tigeot (best_vco != 0 && 1269926deccbSFrançois Tigeot ((best_error > 100 && error < best_error - 100) || 1270926deccbSFrançois Tigeot (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { 1271926deccbSFrançois Tigeot best_post_div = post_div; 1272926deccbSFrançois Tigeot best_ref_div = ref_div; 1273926deccbSFrançois Tigeot best_feedback_div = feedback_div; 1274926deccbSFrançois Tigeot best_frac_feedback_div = frac_feedback_div; 1275926deccbSFrançois Tigeot best_freq = current_freq; 1276926deccbSFrançois Tigeot best_error = error; 1277926deccbSFrançois Tigeot best_vco_diff = vco_diff; 1278926deccbSFrançois Tigeot } else if (current_freq == freq) { 1279926deccbSFrançois Tigeot if (best_freq == -1) { 1280926deccbSFrançois Tigeot best_post_div = post_div; 1281926deccbSFrançois Tigeot best_ref_div = ref_div; 1282926deccbSFrançois Tigeot best_feedback_div = feedback_div; 1283926deccbSFrançois Tigeot best_frac_feedback_div = frac_feedback_div; 1284926deccbSFrançois Tigeot best_freq = current_freq; 1285926deccbSFrançois Tigeot best_error = error; 1286926deccbSFrançois Tigeot best_vco_diff = vco_diff; 1287926deccbSFrançois Tigeot } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 1288926deccbSFrançois Tigeot ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 1289926deccbSFrançois Tigeot ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 1290926deccbSFrançois Tigeot ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 1291926deccbSFrançois Tigeot ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 1292926deccbSFrançois Tigeot ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 1293926deccbSFrançois Tigeot best_post_div = post_div; 1294926deccbSFrançois Tigeot best_ref_div = ref_div; 1295926deccbSFrançois Tigeot best_feedback_div = feedback_div; 1296926deccbSFrançois Tigeot best_frac_feedback_div = frac_feedback_div; 1297926deccbSFrançois Tigeot best_freq = current_freq; 1298926deccbSFrançois Tigeot best_error = error; 1299926deccbSFrançois Tigeot best_vco_diff = vco_diff; 1300926deccbSFrançois Tigeot } 1301926deccbSFrançois Tigeot } 1302926deccbSFrançois Tigeot if (current_freq < freq) 1303926deccbSFrançois Tigeot min_frac_feed_div = frac_feedback_div + 1; 1304926deccbSFrançois Tigeot else 1305926deccbSFrançois Tigeot max_frac_feed_div = frac_feedback_div; 1306926deccbSFrançois Tigeot } 1307926deccbSFrançois Tigeot if (current_freq < freq) 1308926deccbSFrançois Tigeot min_feed_div = feedback_div + 1; 1309926deccbSFrançois Tigeot else 1310926deccbSFrançois Tigeot max_feed_div = feedback_div; 1311926deccbSFrançois Tigeot } 1312926deccbSFrançois Tigeot } 1313926deccbSFrançois Tigeot } 1314926deccbSFrançois Tigeot 1315926deccbSFrançois Tigeot *dot_clock_p = best_freq / 10000; 1316926deccbSFrançois Tigeot *fb_div_p = best_feedback_div; 1317926deccbSFrançois Tigeot *frac_fb_div_p = best_frac_feedback_div; 1318926deccbSFrançois Tigeot *ref_div_p = best_ref_div; 1319926deccbSFrançois Tigeot *post_div_p = best_post_div; 1320926deccbSFrançois Tigeot DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1321926deccbSFrançois Tigeot (long long)freq, 1322926deccbSFrançois Tigeot best_freq / 1000, best_feedback_div, best_frac_feedback_div, 1323926deccbSFrançois Tigeot best_ref_div, best_post_div); 1324926deccbSFrançois Tigeot 1325926deccbSFrançois Tigeot } 1326926deccbSFrançois Tigeot 1327926deccbSFrançois Tigeot static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) 1328926deccbSFrançois Tigeot { 1329926deccbSFrançois Tigeot struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1330926deccbSFrançois Tigeot 1331926deccbSFrançois Tigeot if (radeon_fb->obj) { 1332926deccbSFrançois Tigeot drm_gem_object_unreference_unlocked(radeon_fb->obj); 1333926deccbSFrançois Tigeot } 1334926deccbSFrançois Tigeot drm_framebuffer_cleanup(fb); 1335c4ef309bSzrj kfree(radeon_fb); 1336926deccbSFrançois Tigeot } 1337926deccbSFrançois Tigeot 1338926deccbSFrançois Tigeot static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, 1339926deccbSFrançois Tigeot struct drm_file *file_priv, 1340926deccbSFrançois Tigeot unsigned int *handle) 1341926deccbSFrançois Tigeot { 1342926deccbSFrançois Tigeot struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1343926deccbSFrançois Tigeot 1344926deccbSFrançois Tigeot return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); 1345926deccbSFrançois Tigeot } 1346926deccbSFrançois Tigeot 1347926deccbSFrançois Tigeot static const struct drm_framebuffer_funcs radeon_fb_funcs = { 1348926deccbSFrançois Tigeot .destroy = radeon_user_framebuffer_destroy, 1349926deccbSFrançois Tigeot .create_handle = radeon_user_framebuffer_create_handle, 1350926deccbSFrançois Tigeot }; 1351926deccbSFrançois Tigeot 1352926deccbSFrançois Tigeot int 1353926deccbSFrançois Tigeot radeon_framebuffer_init(struct drm_device *dev, 1354926deccbSFrançois Tigeot struct radeon_framebuffer *rfb, 1355aee94f86SFrançois Tigeot const struct drm_mode_fb_cmd2 *mode_cmd, 1356926deccbSFrançois Tigeot struct drm_gem_object *obj) 1357926deccbSFrançois Tigeot { 1358926deccbSFrançois Tigeot int ret; 1359926deccbSFrançois Tigeot rfb->obj = obj; 1360b403bed8SMichael Neumann drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); 1361926deccbSFrançois Tigeot ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); 1362926deccbSFrançois Tigeot if (ret) { 1363926deccbSFrançois Tigeot rfb->obj = NULL; 1364926deccbSFrançois Tigeot return ret; 1365926deccbSFrançois Tigeot } 1366926deccbSFrançois Tigeot return 0; 1367926deccbSFrançois Tigeot } 1368926deccbSFrançois Tigeot 136960fc7eecSFrançois Tigeot static struct drm_framebuffer * 1370926deccbSFrançois Tigeot radeon_user_framebuffer_create(struct drm_device *dev, 1371926deccbSFrançois Tigeot struct drm_file *file_priv, 1372aee94f86SFrançois Tigeot const struct drm_mode_fb_cmd2 *mode_cmd) 1373926deccbSFrançois Tigeot { 1374926deccbSFrançois Tigeot struct drm_gem_object *obj; 1375926deccbSFrançois Tigeot struct radeon_framebuffer *radeon_fb; 1376926deccbSFrançois Tigeot int ret; 1377926deccbSFrançois Tigeot 13788621f407SFrançois Tigeot obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); 1379926deccbSFrançois Tigeot if (obj == NULL) { 1380fb572d17SFrançois Tigeot dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 1381926deccbSFrançois Tigeot "can't create framebuffer\n", mode_cmd->handles[0]); 138260fc7eecSFrançois Tigeot return ERR_PTR(-ENOENT); 1383926deccbSFrançois Tigeot } 1384926deccbSFrançois Tigeot 1385c59a5c48SFrançois Tigeot /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ 1386c59a5c48SFrançois Tigeot if (obj->import_attach) { 1387c59a5c48SFrançois Tigeot DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n"); 1388c59a5c48SFrançois Tigeot return ERR_PTR(-EINVAL); 1389c59a5c48SFrançois Tigeot } 1390c59a5c48SFrançois Tigeot 1391c4ef309bSzrj radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); 1392926deccbSFrançois Tigeot if (radeon_fb == NULL) { 1393926deccbSFrançois Tigeot drm_gem_object_unreference_unlocked(obj); 139460fc7eecSFrançois Tigeot return ERR_PTR(-ENOMEM); 1395926deccbSFrançois Tigeot } 1396926deccbSFrançois Tigeot 1397926deccbSFrançois Tigeot ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj); 1398926deccbSFrançois Tigeot if (ret) { 1399158486a6SFrançois Tigeot kfree(radeon_fb); 1400926deccbSFrançois Tigeot drm_gem_object_unreference_unlocked(obj); 140160fc7eecSFrançois Tigeot return ERR_PTR(ret); 1402926deccbSFrançois Tigeot } 1403926deccbSFrançois Tigeot 140460fc7eecSFrançois Tigeot return &radeon_fb->base; 1405926deccbSFrançois Tigeot } 1406926deccbSFrançois Tigeot 1407926deccbSFrançois Tigeot static void radeon_output_poll_changed(struct drm_device *dev) 1408926deccbSFrançois Tigeot { 1409926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 1410926deccbSFrançois Tigeot radeon_fb_output_poll_changed(rdev); 1411926deccbSFrançois Tigeot } 1412926deccbSFrançois Tigeot 1413926deccbSFrançois Tigeot static const struct drm_mode_config_funcs radeon_mode_funcs = { 1414926deccbSFrançois Tigeot .fb_create = radeon_user_framebuffer_create, 1415926deccbSFrançois Tigeot .output_poll_changed = radeon_output_poll_changed 1416926deccbSFrançois Tigeot }; 1417926deccbSFrançois Tigeot 1418926deccbSFrançois Tigeot static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = 1419926deccbSFrançois Tigeot { { 0, "driver" }, 1420926deccbSFrançois Tigeot { 1, "bios" }, 1421926deccbSFrançois Tigeot }; 1422926deccbSFrançois Tigeot 1423926deccbSFrançois Tigeot static struct drm_prop_enum_list radeon_tv_std_enum_list[] = 1424926deccbSFrançois Tigeot { { TV_STD_NTSC, "ntsc" }, 1425926deccbSFrançois Tigeot { TV_STD_PAL, "pal" }, 1426926deccbSFrançois Tigeot { TV_STD_PAL_M, "pal-m" }, 1427926deccbSFrançois Tigeot { TV_STD_PAL_60, "pal-60" }, 1428926deccbSFrançois Tigeot { TV_STD_NTSC_J, "ntsc-j" }, 1429926deccbSFrançois Tigeot { TV_STD_SCART_PAL, "scart-pal" }, 1430926deccbSFrançois Tigeot { TV_STD_PAL_CN, "pal-cn" }, 1431926deccbSFrançois Tigeot { TV_STD_SECAM, "secam" }, 1432926deccbSFrançois Tigeot }; 1433926deccbSFrançois Tigeot 1434926deccbSFrançois Tigeot static struct drm_prop_enum_list radeon_underscan_enum_list[] = 1435926deccbSFrançois Tigeot { { UNDERSCAN_OFF, "off" }, 1436926deccbSFrançois Tigeot { UNDERSCAN_ON, "on" }, 1437926deccbSFrançois Tigeot { UNDERSCAN_AUTO, "auto" }, 1438926deccbSFrançois Tigeot }; 1439926deccbSFrançois Tigeot 14404cd92098Szrj static struct drm_prop_enum_list radeon_audio_enum_list[] = 14414cd92098Szrj { { RADEON_AUDIO_DISABLE, "off" }, 14424cd92098Szrj { RADEON_AUDIO_ENABLE, "on" }, 14434cd92098Szrj { RADEON_AUDIO_AUTO, "auto" }, 14444cd92098Szrj }; 14454cd92098Szrj 1446c6f73aabSFrançois Tigeot /* XXX support different dither options? spatial, temporal, both, etc. */ 1447c6f73aabSFrançois Tigeot static struct drm_prop_enum_list radeon_dither_enum_list[] = 1448c6f73aabSFrançois Tigeot { { RADEON_FMT_DITHER_DISABLE, "off" }, 1449c6f73aabSFrançois Tigeot { RADEON_FMT_DITHER_ENABLE, "on" }, 1450c6f73aabSFrançois Tigeot }; 1451c6f73aabSFrançois Tigeot 1452c59a5c48SFrançois Tigeot static struct drm_prop_enum_list radeon_output_csc_enum_list[] = 1453c59a5c48SFrançois Tigeot { { RADEON_OUTPUT_CSC_BYPASS, "bypass" }, 1454c59a5c48SFrançois Tigeot { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" }, 1455c59a5c48SFrançois Tigeot { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" }, 1456c59a5c48SFrançois Tigeot { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" }, 1457c59a5c48SFrançois Tigeot }; 1458c59a5c48SFrançois Tigeot 1459926deccbSFrançois Tigeot static int radeon_modeset_create_props(struct radeon_device *rdev) 1460926deccbSFrançois Tigeot { 1461926deccbSFrançois Tigeot int sz; 1462926deccbSFrançois Tigeot 1463926deccbSFrançois Tigeot if (rdev->is_atom_bios) { 1464926deccbSFrançois Tigeot rdev->mode_info.coherent_mode_property = 1465926deccbSFrançois Tigeot drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1); 1466926deccbSFrançois Tigeot if (!rdev->mode_info.coherent_mode_property) 1467926deccbSFrançois Tigeot return -ENOMEM; 1468926deccbSFrançois Tigeot } 1469926deccbSFrançois Tigeot 1470926deccbSFrançois Tigeot if (!ASIC_IS_AVIVO(rdev)) { 1471c4ef309bSzrj sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); 1472926deccbSFrançois Tigeot rdev->mode_info.tmds_pll_property = 1473926deccbSFrançois Tigeot drm_property_create_enum(rdev->ddev, 0, 1474926deccbSFrançois Tigeot "tmds_pll", 1475926deccbSFrançois Tigeot radeon_tmds_pll_enum_list, sz); 1476926deccbSFrançois Tigeot } 1477926deccbSFrançois Tigeot 1478926deccbSFrançois Tigeot rdev->mode_info.load_detect_property = 1479926deccbSFrançois Tigeot drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1); 1480926deccbSFrançois Tigeot if (!rdev->mode_info.load_detect_property) 1481926deccbSFrançois Tigeot return -ENOMEM; 1482926deccbSFrançois Tigeot 1483926deccbSFrançois Tigeot drm_mode_create_scaling_mode_property(rdev->ddev); 1484926deccbSFrançois Tigeot 1485c4ef309bSzrj sz = ARRAY_SIZE(radeon_tv_std_enum_list); 1486926deccbSFrançois Tigeot rdev->mode_info.tv_std_property = 1487926deccbSFrançois Tigeot drm_property_create_enum(rdev->ddev, 0, 1488926deccbSFrançois Tigeot "tv standard", 1489926deccbSFrançois Tigeot radeon_tv_std_enum_list, sz); 1490926deccbSFrançois Tigeot 1491c4ef309bSzrj sz = ARRAY_SIZE(radeon_underscan_enum_list); 1492926deccbSFrançois Tigeot rdev->mode_info.underscan_property = 1493926deccbSFrançois Tigeot drm_property_create_enum(rdev->ddev, 0, 1494926deccbSFrançois Tigeot "underscan", 1495926deccbSFrançois Tigeot radeon_underscan_enum_list, sz); 1496926deccbSFrançois Tigeot 1497926deccbSFrançois Tigeot rdev->mode_info.underscan_hborder_property = 1498926deccbSFrançois Tigeot drm_property_create_range(rdev->ddev, 0, 1499926deccbSFrançois Tigeot "underscan hborder", 0, 128); 1500926deccbSFrançois Tigeot if (!rdev->mode_info.underscan_hborder_property) 1501926deccbSFrançois Tigeot return -ENOMEM; 1502926deccbSFrançois Tigeot 1503926deccbSFrançois Tigeot rdev->mode_info.underscan_vborder_property = 1504926deccbSFrançois Tigeot drm_property_create_range(rdev->ddev, 0, 1505926deccbSFrançois Tigeot "underscan vborder", 0, 128); 1506926deccbSFrançois Tigeot if (!rdev->mode_info.underscan_vborder_property) 1507926deccbSFrançois Tigeot return -ENOMEM; 1508926deccbSFrançois Tigeot 15094cd92098Szrj sz = ARRAY_SIZE(radeon_audio_enum_list); 15104cd92098Szrj rdev->mode_info.audio_property = 15114cd92098Szrj drm_property_create_enum(rdev->ddev, 0, 15124cd92098Szrj "audio", 15134cd92098Szrj radeon_audio_enum_list, sz); 15144cd92098Szrj 1515c6f73aabSFrançois Tigeot sz = ARRAY_SIZE(radeon_dither_enum_list); 1516c6f73aabSFrançois Tigeot rdev->mode_info.dither_property = 1517c6f73aabSFrançois Tigeot drm_property_create_enum(rdev->ddev, 0, 1518c6f73aabSFrançois Tigeot "dither", 1519c6f73aabSFrançois Tigeot radeon_dither_enum_list, sz); 1520c6f73aabSFrançois Tigeot 1521c59a5c48SFrançois Tigeot sz = ARRAY_SIZE(radeon_output_csc_enum_list); 1522c59a5c48SFrançois Tigeot rdev->mode_info.output_csc_property = 1523c59a5c48SFrançois Tigeot drm_property_create_enum(rdev->ddev, 0, 1524c59a5c48SFrançois Tigeot "output_csc", 1525c59a5c48SFrançois Tigeot radeon_output_csc_enum_list, sz); 1526c59a5c48SFrançois Tigeot 1527926deccbSFrançois Tigeot return 0; 1528926deccbSFrançois Tigeot } 1529926deccbSFrançois Tigeot 1530926deccbSFrançois Tigeot void radeon_update_display_priority(struct radeon_device *rdev) 1531926deccbSFrançois Tigeot { 1532926deccbSFrançois Tigeot /* adjustment options for the display watermarks */ 1533926deccbSFrançois Tigeot if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { 1534926deccbSFrançois Tigeot /* set display priority to high for r3xx, rv515 chips 1535926deccbSFrançois Tigeot * this avoids flickering due to underflow to the 1536926deccbSFrançois Tigeot * display controllers during heavy acceleration. 1537926deccbSFrançois Tigeot * Don't force high on rs4xx igp chips as it seems to 1538926deccbSFrançois Tigeot * affect the sound card. See kernel bug 15982. 1539926deccbSFrançois Tigeot */ 1540926deccbSFrançois Tigeot if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && 1541926deccbSFrançois Tigeot !(rdev->flags & RADEON_IS_IGP)) 1542926deccbSFrançois Tigeot rdev->disp_priority = 2; 1543926deccbSFrançois Tigeot else 1544926deccbSFrançois Tigeot rdev->disp_priority = 0; 1545926deccbSFrançois Tigeot } else 1546926deccbSFrançois Tigeot rdev->disp_priority = radeon_disp_priority; 1547926deccbSFrançois Tigeot 1548926deccbSFrançois Tigeot } 1549926deccbSFrançois Tigeot 1550926deccbSFrançois Tigeot /* 1551926deccbSFrançois Tigeot * Allocate hdmi structs and determine register offsets 1552926deccbSFrançois Tigeot */ 1553926deccbSFrançois Tigeot static void radeon_afmt_init(struct radeon_device *rdev) 1554926deccbSFrançois Tigeot { 1555926deccbSFrançois Tigeot int i; 1556926deccbSFrançois Tigeot 1557926deccbSFrançois Tigeot for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) 1558926deccbSFrançois Tigeot rdev->mode_info.afmt[i] = NULL; 1559926deccbSFrançois Tigeot 15604cd92098Szrj if (ASIC_IS_NODCE(rdev)) { 15614cd92098Szrj /* nothing to do */ 1562926deccbSFrançois Tigeot } else if (ASIC_IS_DCE4(rdev)) { 15634cd92098Szrj static uint32_t eg_offsets[] = { 15644cd92098Szrj EVERGREEN_CRTC0_REGISTER_OFFSET, 15654cd92098Szrj EVERGREEN_CRTC1_REGISTER_OFFSET, 15664cd92098Szrj EVERGREEN_CRTC2_REGISTER_OFFSET, 15674cd92098Szrj EVERGREEN_CRTC3_REGISTER_OFFSET, 15684cd92098Szrj EVERGREEN_CRTC4_REGISTER_OFFSET, 15694cd92098Szrj EVERGREEN_CRTC5_REGISTER_OFFSET, 15704cd92098Szrj 0x13830 - 0x7030, 15714cd92098Szrj }; 15724cd92098Szrj int num_afmt; 15734cd92098Szrj 15744cd92098Szrj /* DCE8 has 7 audio blocks tied to DIG encoders */ 15754cd92098Szrj /* DCE6 has 6 audio blocks tied to DIG encoders */ 1576926deccbSFrançois Tigeot /* DCE4/5 has 6 audio blocks tied to DIG encoders */ 1577926deccbSFrançois Tigeot /* DCE4.1 has 2 audio blocks tied to DIG encoders */ 15784cd92098Szrj if (ASIC_IS_DCE8(rdev)) 15794cd92098Szrj num_afmt = 7; 15804cd92098Szrj else if (ASIC_IS_DCE6(rdev)) 15814cd92098Szrj num_afmt = 6; 15824cd92098Szrj else if (ASIC_IS_DCE5(rdev)) 15834cd92098Szrj num_afmt = 6; 15844cd92098Szrj else if (ASIC_IS_DCE41(rdev)) 15854cd92098Szrj num_afmt = 2; 15864cd92098Szrj else /* DCE4 */ 15874cd92098Szrj num_afmt = 6; 15884cd92098Szrj 15894cd92098Szrj BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets)); 15904cd92098Szrj for (i = 0; i < num_afmt; i++) { 15914cd92098Szrj rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 15924cd92098Szrj if (rdev->mode_info.afmt[i]) { 15934cd92098Szrj rdev->mode_info.afmt[i]->offset = eg_offsets[i]; 15944cd92098Szrj rdev->mode_info.afmt[i]->id = i; 1595926deccbSFrançois Tigeot } 1596926deccbSFrançois Tigeot } 1597926deccbSFrançois Tigeot } else if (ASIC_IS_DCE3(rdev)) { 1598926deccbSFrançois Tigeot /* DCE3.x has 2 audio blocks tied to DIG encoders */ 1599c4ef309bSzrj rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1600926deccbSFrançois Tigeot if (rdev->mode_info.afmt[0]) { 1601926deccbSFrançois Tigeot rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0; 1602926deccbSFrançois Tigeot rdev->mode_info.afmt[0]->id = 0; 1603926deccbSFrançois Tigeot } 1604c4ef309bSzrj rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1605926deccbSFrançois Tigeot if (rdev->mode_info.afmt[1]) { 1606926deccbSFrançois Tigeot rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1; 1607926deccbSFrançois Tigeot rdev->mode_info.afmt[1]->id = 1; 1608926deccbSFrançois Tigeot } 1609926deccbSFrançois Tigeot } else if (ASIC_IS_DCE2(rdev)) { 1610926deccbSFrançois Tigeot /* DCE2 has at least 1 routable audio block */ 1611c4ef309bSzrj rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1612926deccbSFrançois Tigeot if (rdev->mode_info.afmt[0]) { 1613926deccbSFrançois Tigeot rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0; 1614926deccbSFrançois Tigeot rdev->mode_info.afmt[0]->id = 0; 1615926deccbSFrançois Tigeot } 1616926deccbSFrançois Tigeot /* r6xx has 2 routable audio blocks */ 1617926deccbSFrançois Tigeot if (rdev->family >= CHIP_R600) { 1618c4ef309bSzrj rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1619926deccbSFrançois Tigeot if (rdev->mode_info.afmt[1]) { 1620926deccbSFrançois Tigeot rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1; 1621926deccbSFrançois Tigeot rdev->mode_info.afmt[1]->id = 1; 1622926deccbSFrançois Tigeot } 1623926deccbSFrançois Tigeot } 1624926deccbSFrançois Tigeot } 1625926deccbSFrançois Tigeot } 1626926deccbSFrançois Tigeot 1627926deccbSFrançois Tigeot static void radeon_afmt_fini(struct radeon_device *rdev) 1628926deccbSFrançois Tigeot { 1629926deccbSFrançois Tigeot int i; 1630926deccbSFrançois Tigeot 1631926deccbSFrançois Tigeot for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) { 1632c4ef309bSzrj kfree(rdev->mode_info.afmt[i]); 1633926deccbSFrançois Tigeot rdev->mode_info.afmt[i] = NULL; 1634926deccbSFrançois Tigeot } 1635926deccbSFrançois Tigeot } 1636926deccbSFrançois Tigeot 1637926deccbSFrançois Tigeot int radeon_modeset_init(struct radeon_device *rdev) 1638926deccbSFrançois Tigeot { 1639926deccbSFrançois Tigeot int i; 1640926deccbSFrançois Tigeot int ret; 1641926deccbSFrançois Tigeot 1642926deccbSFrançois Tigeot drm_mode_config_init(rdev->ddev); 1643926deccbSFrançois Tigeot rdev->mode_info.mode_config_initialized = true; 1644926deccbSFrançois Tigeot 1645926deccbSFrançois Tigeot rdev->ddev->mode_config.funcs = &radeon_mode_funcs; 1646926deccbSFrançois Tigeot 1647*d78d3a22SFrançois Tigeot if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600) 1648*d78d3a22SFrançois Tigeot rdev->ddev->mode_config.async_page_flip = true; 1649*d78d3a22SFrançois Tigeot 1650926deccbSFrançois Tigeot if (ASIC_IS_DCE5(rdev)) { 1651926deccbSFrançois Tigeot rdev->ddev->mode_config.max_width = 16384; 1652926deccbSFrançois Tigeot rdev->ddev->mode_config.max_height = 16384; 1653926deccbSFrançois Tigeot } else if (ASIC_IS_AVIVO(rdev)) { 1654926deccbSFrançois Tigeot rdev->ddev->mode_config.max_width = 8192; 1655926deccbSFrançois Tigeot rdev->ddev->mode_config.max_height = 8192; 1656926deccbSFrançois Tigeot } else { 1657926deccbSFrançois Tigeot rdev->ddev->mode_config.max_width = 4096; 1658926deccbSFrançois Tigeot rdev->ddev->mode_config.max_height = 4096; 1659926deccbSFrançois Tigeot } 1660926deccbSFrançois Tigeot 1661926deccbSFrançois Tigeot rdev->ddev->mode_config.preferred_depth = 24; 1662926deccbSFrançois Tigeot rdev->ddev->mode_config.prefer_shadow = 1; 1663926deccbSFrançois Tigeot 1664926deccbSFrançois Tigeot rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; 1665926deccbSFrançois Tigeot 1666926deccbSFrançois Tigeot ret = radeon_modeset_create_props(rdev); 1667926deccbSFrançois Tigeot if (ret) { 1668926deccbSFrançois Tigeot return ret; 1669926deccbSFrançois Tigeot } 1670926deccbSFrançois Tigeot 1671926deccbSFrançois Tigeot /* init i2c buses */ 1672926deccbSFrançois Tigeot radeon_i2c_init(rdev); 1673926deccbSFrançois Tigeot 1674926deccbSFrançois Tigeot /* check combios for a valid hardcoded EDID - Sun servers */ 1675926deccbSFrançois Tigeot if (!rdev->is_atom_bios) { 1676926deccbSFrançois Tigeot /* check for hardcoded EDID in BIOS */ 1677926deccbSFrançois Tigeot radeon_combios_check_hardcoded_edid(rdev); 1678926deccbSFrançois Tigeot } 1679926deccbSFrançois Tigeot 1680926deccbSFrançois Tigeot /* allocate crtcs */ 1681926deccbSFrançois Tigeot for (i = 0; i < rdev->num_crtc; i++) { 1682926deccbSFrançois Tigeot radeon_crtc_init(rdev->ddev, i); 1683926deccbSFrançois Tigeot } 1684926deccbSFrançois Tigeot 1685926deccbSFrançois Tigeot /* okay we should have all the bios connectors */ 1686926deccbSFrançois Tigeot ret = radeon_setup_enc_conn(rdev->ddev); 1687926deccbSFrançois Tigeot if (!ret) { 1688926deccbSFrançois Tigeot return ret; 1689926deccbSFrançois Tigeot } 1690926deccbSFrançois Tigeot 1691926deccbSFrançois Tigeot /* init dig PHYs, disp eng pll */ 1692926deccbSFrançois Tigeot if (rdev->is_atom_bios) { 1693926deccbSFrançois Tigeot radeon_atom_encoder_init(rdev); 1694926deccbSFrançois Tigeot radeon_atom_disp_eng_pll_init(rdev); 1695926deccbSFrançois Tigeot } 1696926deccbSFrançois Tigeot 1697926deccbSFrançois Tigeot /* initialize hpd */ 1698926deccbSFrançois Tigeot radeon_hpd_init(rdev); 1699926deccbSFrançois Tigeot 1700926deccbSFrançois Tigeot /* setup afmt */ 1701926deccbSFrançois Tigeot radeon_afmt_init(rdev); 1702926deccbSFrançois Tigeot 1703926deccbSFrançois Tigeot radeon_fbdev_init(rdev); 1704926deccbSFrançois Tigeot drm_kms_helper_poll_init(rdev->ddev); 1705926deccbSFrançois Tigeot 1706c59a5c48SFrançois Tigeot /* do pm late init */ 1707c6f73aabSFrançois Tigeot ret = radeon_pm_late_init(rdev); 1708c6f73aabSFrançois Tigeot 1709926deccbSFrançois Tigeot return 0; 1710926deccbSFrançois Tigeot } 1711926deccbSFrançois Tigeot 1712926deccbSFrançois Tigeot void radeon_modeset_fini(struct radeon_device *rdev) 1713926deccbSFrançois Tigeot { 1714926deccbSFrançois Tigeot radeon_fbdev_fini(rdev); 1715c4ef309bSzrj kfree(rdev->mode_info.bios_hardcoded_edid); 1716926deccbSFrançois Tigeot 1717*d78d3a22SFrançois Tigeot /* free i2c buses */ 1718*d78d3a22SFrançois Tigeot radeon_i2c_fini(rdev); 1719*d78d3a22SFrançois Tigeot 1720926deccbSFrançois Tigeot if (rdev->mode_info.mode_config_initialized) { 1721926deccbSFrançois Tigeot radeon_afmt_fini(rdev); 1722926deccbSFrançois Tigeot drm_kms_helper_poll_fini(rdev->ddev); 1723926deccbSFrançois Tigeot radeon_hpd_fini(rdev); 1724926deccbSFrançois Tigeot drm_mode_config_cleanup(rdev->ddev); 1725926deccbSFrançois Tigeot rdev->mode_info.mode_config_initialized = false; 1726926deccbSFrançois Tigeot } 1727926deccbSFrançois Tigeot } 1728926deccbSFrançois Tigeot 1729926deccbSFrançois Tigeot static bool is_hdtv_mode(const struct drm_display_mode *mode) 1730926deccbSFrançois Tigeot { 1731926deccbSFrançois Tigeot /* try and guess if this is a tv or a monitor */ 1732926deccbSFrançois Tigeot if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 1733926deccbSFrançois Tigeot (mode->vdisplay == 576) || /* 576p */ 1734926deccbSFrançois Tigeot (mode->vdisplay == 720) || /* 720p */ 1735926deccbSFrançois Tigeot (mode->vdisplay == 1080)) /* 1080p */ 1736926deccbSFrançois Tigeot return true; 1737926deccbSFrançois Tigeot else 1738926deccbSFrançois Tigeot return false; 1739926deccbSFrançois Tigeot } 1740926deccbSFrançois Tigeot 1741926deccbSFrançois Tigeot bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 1742926deccbSFrançois Tigeot const struct drm_display_mode *mode, 1743926deccbSFrançois Tigeot struct drm_display_mode *adjusted_mode) 1744926deccbSFrançois Tigeot { 1745926deccbSFrançois Tigeot struct drm_device *dev = crtc->dev; 1746926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 1747926deccbSFrançois Tigeot struct drm_encoder *encoder; 1748926deccbSFrançois Tigeot struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1749926deccbSFrançois Tigeot struct radeon_encoder *radeon_encoder; 1750926deccbSFrançois Tigeot struct drm_connector *connector; 1751926deccbSFrançois Tigeot struct radeon_connector *radeon_connector; 1752926deccbSFrançois Tigeot bool first = true; 1753926deccbSFrançois Tigeot u32 src_v = 1, dst_v = 1; 1754926deccbSFrançois Tigeot u32 src_h = 1, dst_h = 1; 1755926deccbSFrançois Tigeot 1756926deccbSFrançois Tigeot radeon_crtc->h_border = 0; 1757926deccbSFrançois Tigeot radeon_crtc->v_border = 0; 1758926deccbSFrançois Tigeot 1759926deccbSFrançois Tigeot list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1760926deccbSFrançois Tigeot if (encoder->crtc != crtc) 1761926deccbSFrançois Tigeot continue; 1762926deccbSFrançois Tigeot radeon_encoder = to_radeon_encoder(encoder); 1763926deccbSFrançois Tigeot connector = radeon_get_connector_for_encoder(encoder); 1764926deccbSFrançois Tigeot radeon_connector = to_radeon_connector(connector); 1765926deccbSFrançois Tigeot 1766926deccbSFrançois Tigeot if (first) { 1767926deccbSFrançois Tigeot /* set scaling */ 1768926deccbSFrançois Tigeot if (radeon_encoder->rmx_type == RMX_OFF) 1769926deccbSFrançois Tigeot radeon_crtc->rmx_type = RMX_OFF; 1770926deccbSFrançois Tigeot else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || 1771926deccbSFrançois Tigeot mode->vdisplay < radeon_encoder->native_mode.vdisplay) 1772926deccbSFrançois Tigeot radeon_crtc->rmx_type = radeon_encoder->rmx_type; 1773926deccbSFrançois Tigeot else 1774926deccbSFrançois Tigeot radeon_crtc->rmx_type = RMX_OFF; 1775926deccbSFrançois Tigeot /* copy native mode */ 1776926deccbSFrançois Tigeot memcpy(&radeon_crtc->native_mode, 1777926deccbSFrançois Tigeot &radeon_encoder->native_mode, 1778926deccbSFrançois Tigeot sizeof(struct drm_display_mode)); 1779926deccbSFrançois Tigeot src_v = crtc->mode.vdisplay; 1780926deccbSFrançois Tigeot dst_v = radeon_crtc->native_mode.vdisplay; 1781926deccbSFrançois Tigeot src_h = crtc->mode.hdisplay; 1782926deccbSFrançois Tigeot dst_h = radeon_crtc->native_mode.hdisplay; 1783926deccbSFrançois Tigeot 1784926deccbSFrançois Tigeot /* fix up for overscan on hdmi */ 1785926deccbSFrançois Tigeot if (ASIC_IS_AVIVO(rdev) && 1786926deccbSFrançois Tigeot (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 1787926deccbSFrançois Tigeot ((radeon_encoder->underscan_type == UNDERSCAN_ON) || 1788926deccbSFrançois Tigeot ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && 1789c6f73aabSFrançois Tigeot drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 1790926deccbSFrançois Tigeot is_hdtv_mode(mode)))) { 1791926deccbSFrançois Tigeot if (radeon_encoder->underscan_hborder != 0) 1792926deccbSFrançois Tigeot radeon_crtc->h_border = radeon_encoder->underscan_hborder; 1793926deccbSFrançois Tigeot else 1794926deccbSFrançois Tigeot radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; 1795926deccbSFrançois Tigeot if (radeon_encoder->underscan_vborder != 0) 1796926deccbSFrançois Tigeot radeon_crtc->v_border = radeon_encoder->underscan_vborder; 1797926deccbSFrançois Tigeot else 1798926deccbSFrançois Tigeot radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; 1799926deccbSFrançois Tigeot radeon_crtc->rmx_type = RMX_FULL; 1800926deccbSFrançois Tigeot src_v = crtc->mode.vdisplay; 1801926deccbSFrançois Tigeot dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); 1802926deccbSFrançois Tigeot src_h = crtc->mode.hdisplay; 1803926deccbSFrançois Tigeot dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); 1804926deccbSFrançois Tigeot } 1805926deccbSFrançois Tigeot first = false; 1806926deccbSFrançois Tigeot } else { 1807926deccbSFrançois Tigeot if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { 1808926deccbSFrançois Tigeot /* WARNING: Right now this can't happen but 1809926deccbSFrançois Tigeot * in the future we need to check that scaling 1810926deccbSFrançois Tigeot * are consistent across different encoder 1811926deccbSFrançois Tigeot * (ie all encoder can work with the same 1812926deccbSFrançois Tigeot * scaling). 1813926deccbSFrançois Tigeot */ 1814926deccbSFrançois Tigeot DRM_ERROR("Scaling not consistent across encoder.\n"); 1815926deccbSFrançois Tigeot return false; 1816926deccbSFrançois Tigeot } 1817926deccbSFrançois Tigeot } 1818926deccbSFrançois Tigeot } 1819926deccbSFrançois Tigeot if (radeon_crtc->rmx_type != RMX_OFF) { 1820926deccbSFrançois Tigeot fixed20_12 a, b; 1821926deccbSFrançois Tigeot a.full = dfixed_const(src_v); 1822926deccbSFrançois Tigeot b.full = dfixed_const(dst_v); 1823926deccbSFrançois Tigeot radeon_crtc->vsc.full = dfixed_div(a, b); 1824926deccbSFrançois Tigeot a.full = dfixed_const(src_h); 1825926deccbSFrançois Tigeot b.full = dfixed_const(dst_h); 1826926deccbSFrançois Tigeot radeon_crtc->hsc.full = dfixed_div(a, b); 1827926deccbSFrançois Tigeot } else { 1828926deccbSFrançois Tigeot radeon_crtc->vsc.full = dfixed_const(1); 1829926deccbSFrançois Tigeot radeon_crtc->hsc.full = dfixed_const(1); 1830926deccbSFrançois Tigeot } 1831926deccbSFrançois Tigeot return true; 1832926deccbSFrançois Tigeot } 1833926deccbSFrançois Tigeot 1834926deccbSFrançois Tigeot /* 1835782e40d3SFrançois Tigeot * Retrieve current video scanout position of crtc on a given gpu, and 1836782e40d3SFrançois Tigeot * an optional accurate timestamp of when query happened. 1837926deccbSFrançois Tigeot * 1838926deccbSFrançois Tigeot * \param dev Device to query. 1839926deccbSFrançois Tigeot * \param crtc Crtc to query. 1840782e40d3SFrançois Tigeot * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 1841c59a5c48SFrançois Tigeot * For driver internal use only also supports these flags: 1842c59a5c48SFrançois Tigeot * 1843c59a5c48SFrançois Tigeot * USE_REAL_VBLANKSTART to use the real start of vblank instead 1844c59a5c48SFrançois Tigeot * of a fudged earlier start of vblank. 1845c59a5c48SFrançois Tigeot * 1846c59a5c48SFrançois Tigeot * GET_DISTANCE_TO_VBLANKSTART to return distance to the 1847c59a5c48SFrançois Tigeot * fudged earlier start of vblank in *vpos and the distance 1848c59a5c48SFrançois Tigeot * to true start of vblank in *hpos. 1849c59a5c48SFrançois Tigeot * 1850926deccbSFrançois Tigeot * \param *vpos Location where vertical scanout position should be stored. 1851926deccbSFrançois Tigeot * \param *hpos Location where horizontal scanout position should go. 1852782e40d3SFrançois Tigeot * \param *stime Target location for timestamp taken immediately before 1853782e40d3SFrançois Tigeot * scanout position query. Can be NULL to skip timestamp. 1854782e40d3SFrançois Tigeot * \param *etime Target location for timestamp taken immediately after 1855782e40d3SFrançois Tigeot * scanout position query. Can be NULL to skip timestamp. 1856926deccbSFrançois Tigeot * 1857926deccbSFrançois Tigeot * Returns vpos as a positive number while in active scanout area. 1858926deccbSFrançois Tigeot * Returns vpos as a negative number inside vblank, counting the number 1859926deccbSFrançois Tigeot * of scanlines to go until end of vblank, e.g., -1 means "one scanline 1860926deccbSFrançois Tigeot * until start of active scanout / end of vblank." 1861926deccbSFrançois Tigeot * 1862926deccbSFrançois Tigeot * \return Flags, or'ed together as follows: 1863926deccbSFrançois Tigeot * 1864926deccbSFrançois Tigeot * DRM_SCANOUTPOS_VALID = Query successful. 1865926deccbSFrançois Tigeot * DRM_SCANOUTPOS_INVBL = Inside vblank. 1866926deccbSFrançois Tigeot * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 1867926deccbSFrançois Tigeot * this flag means that returned position may be offset by a constant but 1868926deccbSFrançois Tigeot * unknown small number of scanlines wrt. real scanout position. 1869926deccbSFrançois Tigeot * 1870926deccbSFrançois Tigeot */ 1871c59a5c48SFrançois Tigeot int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 1872c59a5c48SFrançois Tigeot unsigned int flags, int *vpos, int *hpos, 1873c59a5c48SFrançois Tigeot ktime_t *stime, ktime_t *etime, 1874352ff8bdSFrançois Tigeot const struct drm_display_mode *mode) 1875926deccbSFrançois Tigeot { 1876926deccbSFrançois Tigeot u32 stat_crtc = 0, vbl = 0, position = 0; 1877926deccbSFrançois Tigeot int vbl_start, vbl_end, vtotal, ret = 0; 1878926deccbSFrançois Tigeot bool in_vbl = true; 1879926deccbSFrançois Tigeot 1880926deccbSFrançois Tigeot struct radeon_device *rdev = dev->dev_private; 1881926deccbSFrançois Tigeot 1882782e40d3SFrançois Tigeot /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 1883782e40d3SFrançois Tigeot 1884782e40d3SFrançois Tigeot /* Get optional system timestamp before query. */ 1885782e40d3SFrançois Tigeot if (stime) 1886782e40d3SFrançois Tigeot *stime = ktime_get(); 1887782e40d3SFrançois Tigeot 1888926deccbSFrançois Tigeot if (ASIC_IS_DCE4(rdev)) { 1889c59a5c48SFrançois Tigeot if (pipe == 0) { 1890926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1891926deccbSFrançois Tigeot EVERGREEN_CRTC0_REGISTER_OFFSET); 1892926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1893926deccbSFrançois Tigeot EVERGREEN_CRTC0_REGISTER_OFFSET); 1894926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1895926deccbSFrançois Tigeot } 1896c59a5c48SFrançois Tigeot if (pipe == 1) { 1897926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1898926deccbSFrançois Tigeot EVERGREEN_CRTC1_REGISTER_OFFSET); 1899926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1900926deccbSFrançois Tigeot EVERGREEN_CRTC1_REGISTER_OFFSET); 1901926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1902926deccbSFrançois Tigeot } 1903c59a5c48SFrançois Tigeot if (pipe == 2) { 1904926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1905926deccbSFrançois Tigeot EVERGREEN_CRTC2_REGISTER_OFFSET); 1906926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1907926deccbSFrançois Tigeot EVERGREEN_CRTC2_REGISTER_OFFSET); 1908926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1909926deccbSFrançois Tigeot } 1910c59a5c48SFrançois Tigeot if (pipe == 3) { 1911926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1912926deccbSFrançois Tigeot EVERGREEN_CRTC3_REGISTER_OFFSET); 1913926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1914926deccbSFrançois Tigeot EVERGREEN_CRTC3_REGISTER_OFFSET); 1915926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1916926deccbSFrançois Tigeot } 1917c59a5c48SFrançois Tigeot if (pipe == 4) { 1918926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1919926deccbSFrançois Tigeot EVERGREEN_CRTC4_REGISTER_OFFSET); 1920926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1921926deccbSFrançois Tigeot EVERGREEN_CRTC4_REGISTER_OFFSET); 1922926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1923926deccbSFrançois Tigeot } 1924c59a5c48SFrançois Tigeot if (pipe == 5) { 1925926deccbSFrançois Tigeot vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1926926deccbSFrançois Tigeot EVERGREEN_CRTC5_REGISTER_OFFSET); 1927926deccbSFrançois Tigeot position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1928926deccbSFrançois Tigeot EVERGREEN_CRTC5_REGISTER_OFFSET); 1929926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1930926deccbSFrançois Tigeot } 1931926deccbSFrançois Tigeot } else if (ASIC_IS_AVIVO(rdev)) { 1932c59a5c48SFrançois Tigeot if (pipe == 0) { 1933926deccbSFrançois Tigeot vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); 1934926deccbSFrançois Tigeot position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); 1935926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1936926deccbSFrançois Tigeot } 1937c59a5c48SFrançois Tigeot if (pipe == 1) { 1938926deccbSFrançois Tigeot vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); 1939926deccbSFrançois Tigeot position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); 1940926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1941926deccbSFrançois Tigeot } 1942926deccbSFrançois Tigeot } else { 1943926deccbSFrançois Tigeot /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ 1944c59a5c48SFrançois Tigeot if (pipe == 0) { 1945926deccbSFrançois Tigeot /* Assume vbl_end == 0, get vbl_start from 1946926deccbSFrançois Tigeot * upper 16 bits. 1947926deccbSFrançois Tigeot */ 1948926deccbSFrançois Tigeot vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & 1949926deccbSFrançois Tigeot RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1950926deccbSFrançois Tigeot /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ 1951926deccbSFrançois Tigeot position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1952926deccbSFrançois Tigeot stat_crtc = RREG32(RADEON_CRTC_STATUS); 1953926deccbSFrançois Tigeot if (!(stat_crtc & 1)) 1954926deccbSFrançois Tigeot in_vbl = false; 1955926deccbSFrançois Tigeot 1956926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1957926deccbSFrançois Tigeot } 1958c59a5c48SFrançois Tigeot if (pipe == 1) { 1959926deccbSFrançois Tigeot vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & 1960926deccbSFrançois Tigeot RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1961926deccbSFrançois Tigeot position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1962926deccbSFrançois Tigeot stat_crtc = RREG32(RADEON_CRTC2_STATUS); 1963926deccbSFrançois Tigeot if (!(stat_crtc & 1)) 1964926deccbSFrançois Tigeot in_vbl = false; 1965926deccbSFrançois Tigeot 1966926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_VALID; 1967926deccbSFrançois Tigeot } 1968926deccbSFrançois Tigeot } 1969926deccbSFrançois Tigeot 1970782e40d3SFrançois Tigeot /* Get optional system timestamp after query. */ 1971782e40d3SFrançois Tigeot if (etime) 1972782e40d3SFrançois Tigeot *etime = ktime_get(); 1973782e40d3SFrançois Tigeot 1974782e40d3SFrançois Tigeot /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 1975782e40d3SFrançois Tigeot 1976926deccbSFrançois Tigeot /* Decode into vertical and horizontal scanout position. */ 1977926deccbSFrançois Tigeot *vpos = position & 0x1fff; 1978926deccbSFrançois Tigeot *hpos = (position >> 16) & 0x1fff; 1979926deccbSFrançois Tigeot 1980926deccbSFrançois Tigeot /* Valid vblank area boundaries from gpu retrieved? */ 1981926deccbSFrançois Tigeot if (vbl > 0) { 1982926deccbSFrançois Tigeot /* Yes: Decode. */ 1983926deccbSFrançois Tigeot ret |= DRM_SCANOUTPOS_ACCURATE; 1984926deccbSFrançois Tigeot vbl_start = vbl & 0x1fff; 1985926deccbSFrançois Tigeot vbl_end = (vbl >> 16) & 0x1fff; 1986926deccbSFrançois Tigeot } 1987926deccbSFrançois Tigeot else { 1988926deccbSFrançois Tigeot /* No: Fake something reasonable which gives at least ok results. */ 1989c59a5c48SFrançois Tigeot vbl_start = mode->crtc_vdisplay; 1990926deccbSFrançois Tigeot vbl_end = 0; 1991926deccbSFrançois Tigeot } 1992926deccbSFrançois Tigeot 1993c59a5c48SFrançois Tigeot /* Called from driver internal vblank counter query code? */ 1994c59a5c48SFrançois Tigeot if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1995c59a5c48SFrançois Tigeot /* Caller wants distance from real vbl_start in *hpos */ 1996c59a5c48SFrançois Tigeot *hpos = *vpos - vbl_start; 1997c59a5c48SFrançois Tigeot } 1998c59a5c48SFrançois Tigeot 1999c59a5c48SFrançois Tigeot /* Fudge vblank to start a few scanlines earlier to handle the 2000c59a5c48SFrançois Tigeot * problem that vblank irqs fire a few scanlines before start 2001c59a5c48SFrançois Tigeot * of vblank. Some driver internal callers need the true vblank 2002c59a5c48SFrançois Tigeot * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 2003c59a5c48SFrançois Tigeot * 2004c59a5c48SFrançois Tigeot * The cause of the "early" vblank irq is that the irq is triggered 2005c59a5c48SFrançois Tigeot * by the line buffer logic when the line buffer read position enters 2006c59a5c48SFrançois Tigeot * the vblank, whereas our crtc scanout position naturally lags the 2007c59a5c48SFrançois Tigeot * line buffer read position. 2008c59a5c48SFrançois Tigeot */ 2009c59a5c48SFrançois Tigeot if (!(flags & USE_REAL_VBLANKSTART)) 2010c59a5c48SFrançois Tigeot vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 2011c59a5c48SFrançois Tigeot 2012926deccbSFrançois Tigeot /* Test scanout position against vblank region. */ 2013926deccbSFrançois Tigeot if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 2014926deccbSFrançois Tigeot in_vbl = false; 2015926deccbSFrançois Tigeot 2016c59a5c48SFrançois Tigeot /* In vblank? */ 2017c59a5c48SFrançois Tigeot if (in_vbl) 2018c59a5c48SFrançois Tigeot ret |= DRM_SCANOUTPOS_IN_VBLANK; 2019c59a5c48SFrançois Tigeot 2020c59a5c48SFrançois Tigeot /* Called from driver internal vblank counter query code? */ 2021c59a5c48SFrançois Tigeot if (flags & GET_DISTANCE_TO_VBLANKSTART) { 2022c59a5c48SFrançois Tigeot /* Caller wants distance from fudged earlier vbl_start */ 2023c59a5c48SFrançois Tigeot *vpos -= vbl_start; 2024c59a5c48SFrançois Tigeot return ret; 2025c59a5c48SFrançois Tigeot } 2026c59a5c48SFrançois Tigeot 2027926deccbSFrançois Tigeot /* Check if inside vblank area and apply corrective offsets: 2028926deccbSFrançois Tigeot * vpos will then be >=0 in video scanout area, but negative 2029926deccbSFrançois Tigeot * within vblank area, counting down the number of lines until 2030926deccbSFrançois Tigeot * start of scanout. 2031926deccbSFrançois Tigeot */ 2032926deccbSFrançois Tigeot 2033926deccbSFrançois Tigeot /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 2034926deccbSFrançois Tigeot if (in_vbl && (*vpos >= vbl_start)) { 2035c59a5c48SFrançois Tigeot vtotal = mode->crtc_vtotal; 2036926deccbSFrançois Tigeot *vpos = *vpos - vtotal; 2037926deccbSFrançois Tigeot } 2038926deccbSFrançois Tigeot 2039926deccbSFrançois Tigeot /* Correct for shifted end of vbl at vbl_end. */ 2040926deccbSFrançois Tigeot *vpos = *vpos - vbl_end; 2041926deccbSFrançois Tigeot 2042926deccbSFrançois Tigeot return ret; 2043926deccbSFrançois Tigeot } 2044