1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * 26 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_display.c 254885 2013-08-25 19:37:15Z dumbbell $ 27 */ 28 29 #include <drm/drmP.h> 30 #include <drm/radeon_drm.h> 31 #include "radeon.h" 32 33 #include "atom.h" 34 35 #ifdef PM_TODO 36 #include <linux/pm_runtime.h> 37 #endif 38 #include <drm/drm_crtc_helper.h> 39 #include <drm/drm_plane_helper.h> 40 #include <drm/drm_edid.h> 41 #include <linux/err.h> 42 43 #include <linux/gcd.h> 44 45 static void avivo_crtc_load_lut(struct drm_crtc *crtc) 46 { 47 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 48 struct drm_device *dev = crtc->dev; 49 struct radeon_device *rdev = dev->dev_private; 50 int i; 51 52 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 53 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); 54 55 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 56 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 57 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 58 59 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 60 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 61 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 62 63 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); 64 WREG32(AVIVO_DC_LUT_RW_MODE, 0); 65 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); 66 67 WREG8(AVIVO_DC_LUT_RW_INDEX, 0); 68 for (i = 0; i < 256; i++) { 69 WREG32(AVIVO_DC_LUT_30_COLOR, 70 (radeon_crtc->lut_r[i] << 20) | 71 (radeon_crtc->lut_g[i] << 10) | 72 (radeon_crtc->lut_b[i] << 0)); 73 } 74 75 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */ 76 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1); 77 } 78 79 static void dce4_crtc_load_lut(struct drm_crtc *crtc) 80 { 81 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 82 struct drm_device *dev = crtc->dev; 83 struct radeon_device *rdev = dev->dev_private; 84 int i; 85 86 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 87 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 88 89 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 90 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 91 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 92 93 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 94 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 95 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 96 97 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 98 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 99 100 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 101 for (i = 0; i < 256; i++) { 102 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 103 (radeon_crtc->lut_r[i] << 20) | 104 (radeon_crtc->lut_g[i] << 10) | 105 (radeon_crtc->lut_b[i] << 0)); 106 } 107 } 108 109 static void dce5_crtc_load_lut(struct drm_crtc *crtc) 110 { 111 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 112 struct drm_device *dev = crtc->dev; 113 struct radeon_device *rdev = dev->dev_private; 114 int i; 115 116 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 117 118 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 119 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | 120 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); 121 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, 122 NI_GRPH_PRESCALE_BYPASS); 123 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, 124 NI_OVL_PRESCALE_BYPASS); 125 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, 126 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | 127 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); 128 129 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 130 131 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 132 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 133 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 134 135 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 136 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 137 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 138 139 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 140 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 141 142 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 143 for (i = 0; i < 256; i++) { 144 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 145 (radeon_crtc->lut_r[i] << 20) | 146 (radeon_crtc->lut_g[i] << 10) | 147 (radeon_crtc->lut_b[i] << 0)); 148 } 149 150 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, 151 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 152 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 153 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 154 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); 155 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, 156 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | 157 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); 158 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, 159 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | 160 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); 161 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 162 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) | 163 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); 164 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 165 WREG32(0x6940 + radeon_crtc->crtc_offset, 0); 166 if (ASIC_IS_DCE8(rdev)) { 167 /* XXX this only needs to be programmed once per crtc at startup, 168 * not sure where the best place for it is 169 */ 170 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset, 171 CIK_CURSOR_ALPHA_BLND_ENA); 172 } 173 } 174 175 static void legacy_crtc_load_lut(struct drm_crtc *crtc) 176 { 177 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 178 struct drm_device *dev = crtc->dev; 179 struct radeon_device *rdev = dev->dev_private; 180 int i; 181 uint32_t dac2_cntl; 182 183 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 184 if (radeon_crtc->crtc_id == 0) 185 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; 186 else 187 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; 188 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 189 190 WREG8(RADEON_PALETTE_INDEX, 0); 191 for (i = 0; i < 256; i++) { 192 WREG32(RADEON_PALETTE_30_DATA, 193 (radeon_crtc->lut_r[i] << 20) | 194 (radeon_crtc->lut_g[i] << 10) | 195 (radeon_crtc->lut_b[i] << 0)); 196 } 197 } 198 199 void radeon_crtc_load_lut(struct drm_crtc *crtc) 200 { 201 struct drm_device *dev = crtc->dev; 202 struct radeon_device *rdev = dev->dev_private; 203 204 if (!crtc->enabled) 205 return; 206 207 if (ASIC_IS_DCE5(rdev)) 208 dce5_crtc_load_lut(crtc); 209 else if (ASIC_IS_DCE4(rdev)) 210 dce4_crtc_load_lut(crtc); 211 else if (ASIC_IS_AVIVO(rdev)) 212 avivo_crtc_load_lut(crtc); 213 else 214 legacy_crtc_load_lut(crtc); 215 } 216 217 /** Sets the color ramps on behalf of fbcon */ 218 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 219 u16 blue, int regno) 220 { 221 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 222 223 radeon_crtc->lut_r[regno] = red >> 6; 224 radeon_crtc->lut_g[regno] = green >> 6; 225 radeon_crtc->lut_b[regno] = blue >> 6; 226 } 227 228 /** Gets the color ramps on behalf of fbcon */ 229 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 230 u16 *blue, int regno) 231 { 232 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 233 234 *red = radeon_crtc->lut_r[regno] << 6; 235 *green = radeon_crtc->lut_g[regno] << 6; 236 *blue = radeon_crtc->lut_b[regno] << 6; 237 } 238 239 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 240 u16 *blue, uint32_t start, uint32_t size) 241 { 242 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 243 int end = (start + size > 256) ? 256 : start + size, i; 244 245 /* userspace palettes are always correct as is */ 246 for (i = start; i < end; i++) { 247 radeon_crtc->lut_r[i] = red[i] >> 6; 248 radeon_crtc->lut_g[i] = green[i] >> 6; 249 radeon_crtc->lut_b[i] = blue[i] >> 6; 250 } 251 radeon_crtc_load_lut(crtc); 252 } 253 254 static void radeon_crtc_destroy(struct drm_crtc *crtc) 255 { 256 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 257 258 drm_crtc_cleanup(crtc); 259 destroy_workqueue(radeon_crtc->flip_queue); 260 kfree(radeon_crtc); 261 } 262 263 /** 264 * radeon_unpin_work_func - unpin old buffer object 265 * 266 * @__work - kernel work item 267 * 268 * Unpin the old frame buffer object outside of the interrupt handler 269 */ 270 static void radeon_unpin_work_func(struct work_struct *__work) 271 { 272 struct radeon_flip_work *work = 273 container_of(__work, struct radeon_flip_work, unpin_work); 274 int r; 275 276 /* unpin of the old buffer */ 277 r = radeon_bo_reserve(work->old_rbo, false); 278 if (likely(r == 0)) { 279 r = radeon_bo_unpin(work->old_rbo); 280 if (unlikely(r != 0)) { 281 DRM_ERROR("failed to unpin buffer after flip\n"); 282 } 283 radeon_bo_unreserve(work->old_rbo); 284 } else 285 DRM_ERROR("failed to reserve buffer after flip\n"); 286 287 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 288 kfree(work); 289 } 290 291 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id) 292 { 293 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 294 u32 update_pending; 295 int vpos, hpos; 296 297 /* can happen during initialization */ 298 if (radeon_crtc == NULL) 299 return; 300 301 /* Skip the pageflip completion check below (based on polling) on 302 * asics which reliably support hw pageflip completion irqs. pflip 303 * irqs are a reliable and race-free method of handling pageflip 304 * completion detection. A use_pflipirq module parameter < 2 allows 305 * to override this in case of asics with faulty pflip irqs. 306 * A module parameter of 0 would only use this polling based path, 307 * a parameter of 1 would use pflip irq only as a backup to this 308 * path, as in Linux 3.16. 309 */ 310 if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev)) 311 return; 312 313 lockmgr(&rdev->ddev->event_lock, LK_EXCLUSIVE); 314 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 315 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 316 "RADEON_FLIP_SUBMITTED(%d)\n", 317 radeon_crtc->flip_status, 318 RADEON_FLIP_SUBMITTED); 319 lockmgr(&rdev->ddev->event_lock, LK_RELEASE); 320 return; 321 } 322 323 update_pending = radeon_page_flip_pending(rdev, crtc_id); 324 325 /* Has the pageflip already completed in crtc, or is it certain 326 * to complete in this vblank? 327 */ 328 if (update_pending && 329 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0, 330 &vpos, &hpos, NULL, NULL, 331 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) && 332 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) || 333 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) { 334 /* crtc didn't flip in this target vblank interval, 335 * but flip is pending in crtc. Based on the current 336 * scanout position we know that the current frame is 337 * (nearly) complete and the flip will (likely) 338 * complete before the start of the next frame. 339 */ 340 update_pending = 0; 341 } 342 lockmgr(&rdev->ddev->event_lock, LK_RELEASE); 343 if (!update_pending) 344 radeon_crtc_handle_flip(rdev, crtc_id); 345 } 346 347 /** 348 * radeon_crtc_handle_flip - page flip completed 349 * 350 * @rdev: radeon device pointer 351 * @crtc_id: crtc number this event is for 352 * 353 * Called when we are sure that a page flip for this crtc is completed. 354 */ 355 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) 356 { 357 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 358 struct radeon_flip_work *work; 359 360 /* this can happen at init */ 361 if (radeon_crtc == NULL) 362 return; 363 364 lockmgr(&rdev->ddev->event_lock, LK_EXCLUSIVE); 365 work = radeon_crtc->flip_work; 366 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 367 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 368 "RADEON_FLIP_SUBMITTED(%d)\n", 369 radeon_crtc->flip_status, 370 RADEON_FLIP_SUBMITTED); 371 lockmgr(&rdev->ddev->event_lock, LK_RELEASE); 372 return; 373 } 374 375 /* Pageflip completed. Clean up. */ 376 radeon_crtc->flip_status = RADEON_FLIP_NONE; 377 radeon_crtc->flip_work = NULL; 378 379 /* wakeup userspace */ 380 if (work->event) 381 drm_send_vblank_event(rdev->ddev, crtc_id, work->event); 382 383 lockmgr(&rdev->ddev->event_lock, LK_RELEASE); 384 385 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id); 386 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id); 387 queue_work(radeon_crtc->flip_queue, &work->unpin_work); 388 } 389 390 /** 391 * radeon_flip_work_func - page flip framebuffer 392 * 393 * @work - kernel work item 394 * 395 * Wait for the buffer object to become idle and do the actual page flip 396 */ 397 static void radeon_flip_work_func(struct work_struct *__work) 398 { 399 struct radeon_flip_work *work = 400 container_of(__work, struct radeon_flip_work, flip_work); 401 struct radeon_device *rdev = work->rdev; 402 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id]; 403 404 struct drm_crtc *crtc = &radeon_crtc->base; 405 int r; 406 407 lockmgr(&rdev->exclusive_lock, LK_EXCLUSIVE); 408 if (work->fence) { 409 r = radeon_fence_wait(work->fence, false); 410 if (r == -EDEADLK) { 411 lockmgr(&rdev->exclusive_lock, LK_RELEASE); 412 do { 413 r = radeon_gpu_reset(rdev); 414 } while (r == -EAGAIN); 415 lockmgr(&rdev->exclusive_lock, LK_EXCLUSIVE); 416 } 417 if (r) 418 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r); 419 420 /* We continue with the page flip even if we failed to wait on 421 * the fence, otherwise the DRM core and userspace will be 422 * confused about which BO the CRTC is scanning out 423 */ 424 425 radeon_fence_unref(&work->fence); 426 } 427 428 /* We borrow the event spin lock for protecting flip_status */ 429 lockmgr(&crtc->dev->event_lock, LK_EXCLUSIVE); 430 431 /* set the proper interrupt */ 432 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id); 433 434 /* do the flip (mmio) */ 435 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base); 436 437 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED; 438 lockmgr(&crtc->dev->event_lock, LK_RELEASE); 439 lockmgr(&rdev->exclusive_lock, LK_RELEASE); 440 } 441 442 static int radeon_crtc_page_flip(struct drm_crtc *crtc, 443 struct drm_framebuffer *fb, 444 struct drm_pending_vblank_event *event, 445 uint32_t page_flip_flags) 446 { 447 struct drm_device *dev = crtc->dev; 448 struct radeon_device *rdev = dev->dev_private; 449 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 450 struct radeon_framebuffer *old_radeon_fb; 451 struct radeon_framebuffer *new_radeon_fb; 452 struct drm_gem_object *obj; 453 struct radeon_flip_work *work; 454 struct radeon_bo *new_rbo; 455 uint32_t tiling_flags, pitch_pixels; 456 uint64_t base; 457 int r; 458 459 work = kzalloc(sizeof *work, GFP_KERNEL); 460 if (work == NULL) 461 return -ENOMEM; 462 463 INIT_WORK(&work->flip_work, radeon_flip_work_func); 464 INIT_WORK(&work->unpin_work, radeon_unpin_work_func); 465 466 work->rdev = rdev; 467 work->crtc_id = radeon_crtc->crtc_id; 468 work->event = event; 469 470 /* schedule unpin of the old buffer */ 471 old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb); 472 obj = old_radeon_fb->obj; 473 474 /* take a reference to the old object */ 475 drm_gem_object_reference(obj); 476 work->old_rbo = gem_to_radeon_bo(obj); 477 478 new_radeon_fb = to_radeon_framebuffer(fb); 479 obj = new_radeon_fb->obj; 480 new_rbo = gem_to_radeon_bo(obj); 481 482 /* pin the new buffer */ 483 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n", 484 work->old_rbo, new_rbo); 485 486 r = radeon_bo_reserve(new_rbo, false); 487 if (unlikely(r != 0)) { 488 DRM_ERROR("failed to reserve new rbo buffer before flip\n"); 489 goto cleanup; 490 } 491 /* Only 27 bit offset for legacy CRTC */ 492 r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM, 493 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, (u64 *)&base); 494 if (unlikely(r != 0)) { 495 radeon_bo_unreserve(new_rbo); 496 r = -EINVAL; 497 DRM_ERROR("failed to pin new rbo buffer before flip\n"); 498 goto cleanup; 499 } 500 work->fence = (struct radeon_fence *)fence_get(reservation_object_get_excl(new_rbo->tbo.resv)); 501 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); 502 radeon_bo_unreserve(new_rbo); 503 504 if (!ASIC_IS_AVIVO(rdev)) { 505 /* crtc offset is from display base addr not FB location */ 506 base -= radeon_crtc->legacy_display_base_addr; 507 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8); 508 509 if (tiling_flags & RADEON_TILING_MACRO) { 510 if (ASIC_IS_R300(rdev)) { 511 base &= ~0x7ff; 512 } else { 513 int byteshift = fb->bits_per_pixel >> 4; 514 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11; 515 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8); 516 } 517 } else { 518 int offset = crtc->y * pitch_pixels + crtc->x; 519 switch (fb->bits_per_pixel) { 520 case 8: 521 default: 522 offset *= 1; 523 break; 524 case 15: 525 case 16: 526 offset *= 2; 527 break; 528 case 24: 529 offset *= 3; 530 break; 531 case 32: 532 offset *= 4; 533 break; 534 } 535 base += offset; 536 } 537 base &= ~7; 538 } 539 work->base = base; 540 541 r = drm_vblank_get(crtc->dev, radeon_crtc->crtc_id); 542 if (r) { 543 DRM_ERROR("failed to get vblank before flip\n"); 544 goto pflip_cleanup; 545 } 546 547 /* We borrow the event spin lock for protecting flip_work */ 548 lockmgr(&crtc->dev->event_lock, LK_EXCLUSIVE); 549 550 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) { 551 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 552 lockmgr(&crtc->dev->event_lock, LK_RELEASE); 553 r = -EBUSY; 554 goto vblank_cleanup; 555 } 556 radeon_crtc->flip_status = RADEON_FLIP_PENDING; 557 radeon_crtc->flip_work = work; 558 559 /* update crtc fb */ 560 crtc->primary->fb = fb; 561 562 lockmgr(&crtc->dev->event_lock, LK_RELEASE); 563 564 queue_work(radeon_crtc->flip_queue, &work->flip_work); 565 return 0; 566 567 vblank_cleanup: 568 drm_vblank_put(crtc->dev, radeon_crtc->crtc_id); 569 570 pflip_cleanup: 571 if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) { 572 DRM_ERROR("failed to reserve new rbo in error path\n"); 573 goto cleanup; 574 } 575 if (unlikely(radeon_bo_unpin(new_rbo) != 0)) { 576 DRM_ERROR("failed to unpin new rbo in error path\n"); 577 } 578 radeon_bo_unreserve(new_rbo); 579 580 cleanup: 581 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 582 radeon_fence_unref(&work->fence); 583 kfree(work); 584 return r; 585 } 586 587 static int 588 radeon_crtc_set_config(struct drm_mode_set *set) 589 { 590 struct drm_device *dev; 591 struct radeon_device *rdev; 592 struct drm_crtc *crtc; 593 bool active = false; 594 int ret; 595 596 if (!set || !set->crtc) 597 return -EINVAL; 598 599 dev = set->crtc->dev; 600 601 #ifdef PM_TODO 602 ret = pm_runtime_get_sync(dev->dev); 603 if (ret < 0) 604 return ret; 605 #endif 606 607 ret = drm_crtc_helper_set_config(set); 608 609 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 610 if (crtc->enabled) 611 active = true; 612 613 #ifdef PM_TODO 614 pm_runtime_mark_last_busy(dev->dev); 615 #endif 616 617 rdev = dev->dev_private; 618 /* if we have active crtcs and we don't have a power ref, 619 take the current one */ 620 if (active && !rdev->have_disp_power_ref) { 621 rdev->have_disp_power_ref = true; 622 return ret; 623 } 624 /* if we have no active crtcs, then drop the power ref 625 we got before */ 626 if (!active && rdev->have_disp_power_ref) { 627 #ifdef PM_TODO 628 pm_runtime_put_autosuspend(dev->dev); 629 #endif 630 rdev->have_disp_power_ref = false; 631 } 632 633 /* drop the power reference we got coming in here */ 634 #ifdef PM_TODO 635 pm_runtime_put_autosuspend(dev->dev); 636 #endif 637 return ret; 638 } 639 static const struct drm_crtc_funcs radeon_crtc_funcs = { 640 .cursor_set = radeon_crtc_cursor_set, 641 .cursor_move = radeon_crtc_cursor_move, 642 .gamma_set = radeon_crtc_gamma_set, 643 .set_config = radeon_crtc_set_config, 644 .destroy = radeon_crtc_destroy, 645 .page_flip = radeon_crtc_page_flip, 646 }; 647 648 static void radeon_crtc_init(struct drm_device *dev, int index) 649 { 650 struct radeon_device *rdev = dev->dev_private; 651 struct radeon_crtc *radeon_crtc; 652 int i; 653 654 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 655 if (radeon_crtc == NULL) 656 return; 657 658 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); 659 660 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); 661 radeon_crtc->crtc_id = index; 662 radeon_crtc->flip_queue = create_singlethread_workqueue("radeon-crtc"); 663 rdev->mode_info.crtcs[index] = radeon_crtc; 664 665 if (rdev->family >= CHIP_BONAIRE) { 666 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH; 667 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT; 668 } else { 669 radeon_crtc->max_cursor_width = CURSOR_WIDTH; 670 radeon_crtc->max_cursor_height = CURSOR_HEIGHT; 671 } 672 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width; 673 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height; 674 675 #if 0 676 radeon_crtc->mode_set.crtc = &radeon_crtc->base; 677 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); 678 radeon_crtc->mode_set.num_connectors = 0; 679 #endif 680 681 for (i = 0; i < 256; i++) { 682 radeon_crtc->lut_r[i] = i << 2; 683 radeon_crtc->lut_g[i] = i << 2; 684 radeon_crtc->lut_b[i] = i << 2; 685 } 686 687 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) 688 radeon_atombios_init_crtc(dev, radeon_crtc); 689 else 690 radeon_legacy_init_crtc(dev, radeon_crtc); 691 } 692 693 static const char *encoder_names[38] = { 694 "NONE", 695 "INTERNAL_LVDS", 696 "INTERNAL_TMDS1", 697 "INTERNAL_TMDS2", 698 "INTERNAL_DAC1", 699 "INTERNAL_DAC2", 700 "INTERNAL_SDVOA", 701 "INTERNAL_SDVOB", 702 "SI170B", 703 "CH7303", 704 "CH7301", 705 "INTERNAL_DVO1", 706 "EXTERNAL_SDVOA", 707 "EXTERNAL_SDVOB", 708 "TITFP513", 709 "INTERNAL_LVTM1", 710 "VT1623", 711 "HDMI_SI1930", 712 "HDMI_INTERNAL", 713 "INTERNAL_KLDSCP_TMDS1", 714 "INTERNAL_KLDSCP_DVO1", 715 "INTERNAL_KLDSCP_DAC1", 716 "INTERNAL_KLDSCP_DAC2", 717 "SI178", 718 "MVPU_FPGA", 719 "INTERNAL_DDI", 720 "VT1625", 721 "HDMI_SI1932", 722 "DP_AN9801", 723 "DP_DP501", 724 "INTERNAL_UNIPHY", 725 "INTERNAL_KLDSCP_LVTMA", 726 "INTERNAL_UNIPHY1", 727 "INTERNAL_UNIPHY2", 728 "NUTMEG", 729 "TRAVIS", 730 "INTERNAL_VCE", 731 "INTERNAL_UNIPHY3", 732 }; 733 734 static const char *hpd_names[6] = { 735 "HPD1", 736 "HPD2", 737 "HPD3", 738 "HPD4", 739 "HPD5", 740 "HPD6", 741 }; 742 743 static void radeon_print_display_setup(struct drm_device *dev) 744 { 745 struct drm_connector *connector; 746 struct radeon_connector *radeon_connector; 747 struct drm_encoder *encoder; 748 struct radeon_encoder *radeon_encoder; 749 uint32_t devices; 750 int i = 0; 751 752 DRM_INFO("Radeon Display Connectors\n"); 753 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 754 radeon_connector = to_radeon_connector(connector); 755 DRM_INFO("Connector %d:\n", i); 756 DRM_INFO(" %s\n", connector->name); 757 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 758 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); 759 if (radeon_connector->ddc_bus) { 760 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 761 radeon_connector->ddc_bus->rec.mask_clk_reg, 762 radeon_connector->ddc_bus->rec.mask_data_reg, 763 radeon_connector->ddc_bus->rec.a_clk_reg, 764 radeon_connector->ddc_bus->rec.a_data_reg, 765 radeon_connector->ddc_bus->rec.en_clk_reg, 766 radeon_connector->ddc_bus->rec.en_data_reg, 767 radeon_connector->ddc_bus->rec.y_clk_reg, 768 radeon_connector->ddc_bus->rec.y_data_reg); 769 if (radeon_connector->router.ddc_valid) 770 DRM_INFO(" DDC Router 0x%x/0x%x\n", 771 radeon_connector->router.ddc_mux_control_pin, 772 radeon_connector->router.ddc_mux_state); 773 if (radeon_connector->router.cd_valid) 774 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 775 radeon_connector->router.cd_mux_control_pin, 776 radeon_connector->router.cd_mux_state); 777 } else { 778 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 779 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 780 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 781 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 782 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 783 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 784 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 785 } 786 DRM_INFO(" Encoders:\n"); 787 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 788 radeon_encoder = to_radeon_encoder(encoder); 789 devices = radeon_encoder->devices & radeon_connector->devices; 790 if (devices) { 791 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 792 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); 793 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 794 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); 795 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 796 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); 797 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 798 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); 799 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 800 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); 801 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 802 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); 803 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 804 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); 805 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 806 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); 807 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 808 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); 809 if (devices & ATOM_DEVICE_TV1_SUPPORT) 810 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); 811 if (devices & ATOM_DEVICE_CV_SUPPORT) 812 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); 813 } 814 } 815 i++; 816 } 817 } 818 819 static bool radeon_setup_enc_conn(struct drm_device *dev) 820 { 821 struct radeon_device *rdev = dev->dev_private; 822 bool ret = false; 823 824 if (rdev->bios) { 825 if (rdev->is_atom_bios) { 826 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); 827 if (ret == false) 828 ret = radeon_get_atom_connector_info_from_object_table(dev); 829 } else { 830 ret = radeon_get_legacy_connector_info_from_bios(dev); 831 if (ret == false) 832 ret = radeon_get_legacy_connector_info_from_table(dev); 833 } 834 } else { 835 if (!ASIC_IS_AVIVO(rdev)) 836 ret = radeon_get_legacy_connector_info_from_table(dev); 837 } 838 if (ret) { 839 radeon_setup_encoder_clones(dev); 840 radeon_print_display_setup(dev); 841 } 842 843 return ret; 844 } 845 846 /* avivo */ 847 848 /** 849 * avivo_reduce_ratio - fractional number reduction 850 * 851 * @nom: nominator 852 * @den: denominator 853 * @nom_min: minimum value for nominator 854 * @den_min: minimum value for denominator 855 * 856 * Find the greatest common divisor and apply it on both nominator and 857 * denominator, but make nominator and denominator are at least as large 858 * as their minimum values. 859 */ 860 static void avivo_reduce_ratio(unsigned *nom, unsigned *den, 861 unsigned nom_min, unsigned den_min) 862 { 863 unsigned tmp; 864 865 /* reduce the numbers to a simpler ratio */ 866 tmp = gcd64(*nom, *den); 867 *nom /= tmp; 868 *den /= tmp; 869 870 /* make sure nominator is large enough */ 871 if (*nom < nom_min) { 872 tmp = DIV_ROUND_UP(nom_min, *nom); 873 *nom *= tmp; 874 *den *= tmp; 875 } 876 877 /* make sure the denominator is large enough */ 878 if (*den < den_min) { 879 tmp = DIV_ROUND_UP(den_min, *den); 880 *nom *= tmp; 881 *den *= tmp; 882 } 883 } 884 885 /** 886 * avivo_get_fb_ref_div - feedback and ref divider calculation 887 * 888 * @nom: nominator 889 * @den: denominator 890 * @post_div: post divider 891 * @fb_div_max: feedback divider maximum 892 * @ref_div_max: reference divider maximum 893 * @fb_div: resulting feedback divider 894 * @ref_div: resulting reference divider 895 * 896 * Calculate feedback and reference divider for a given post divider. Makes 897 * sure we stay within the limits. 898 */ 899 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, 900 unsigned fb_div_max, unsigned ref_div_max, 901 unsigned *fb_div, unsigned *ref_div) 902 { 903 /* limit reference * post divider to a maximum */ 904 ref_div_max = max(min(100 / post_div, ref_div_max), 1u); 905 906 /* get matching reference and feedback divider */ 907 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); 908 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); 909 910 /* limit fb divider to its maximum */ 911 if (*fb_div > fb_div_max) { 912 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); 913 *fb_div = fb_div_max; 914 } 915 } 916 917 /** 918 * radeon_compute_pll_avivo - compute PLL paramaters 919 * 920 * @pll: information about the PLL 921 * @dot_clock_p: resulting pixel clock 922 * fb_div_p: resulting feedback divider 923 * frac_fb_div_p: fractional part of the feedback divider 924 * ref_div_p: resulting reference divider 925 * post_div_p: resulting reference divider 926 * 927 * Try to calculate the PLL parameters to generate the given frequency: 928 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div) 929 */ 930 void radeon_compute_pll_avivo(struct radeon_pll *pll, 931 u32 freq, 932 u32 *dot_clock_p, 933 u32 *fb_div_p, 934 u32 *frac_fb_div_p, 935 u32 *ref_div_p, 936 u32 *post_div_p) 937 { 938 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? 939 freq : freq / 10; 940 941 unsigned fb_div_min, fb_div_max, fb_div; 942 unsigned post_div_min, post_div_max, post_div; 943 unsigned ref_div_min, ref_div_max, ref_div; 944 unsigned post_div_best, diff_best; 945 unsigned nom, den; 946 947 /* determine allowed feedback divider range */ 948 fb_div_min = pll->min_feedback_div; 949 fb_div_max = pll->max_feedback_div; 950 951 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 952 fb_div_min *= 10; 953 fb_div_max *= 10; 954 } 955 956 /* determine allowed ref divider range */ 957 if (pll->flags & RADEON_PLL_USE_REF_DIV) 958 ref_div_min = pll->reference_div; 959 else 960 ref_div_min = pll->min_ref_div; 961 962 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && 963 pll->flags & RADEON_PLL_USE_REF_DIV) 964 ref_div_max = pll->reference_div; 965 else 966 ref_div_max = pll->max_ref_div; 967 968 /* determine allowed post divider range */ 969 if (pll->flags & RADEON_PLL_USE_POST_DIV) { 970 post_div_min = pll->post_div; 971 post_div_max = pll->post_div; 972 } else { 973 unsigned vco_min, vco_max; 974 975 if (pll->flags & RADEON_PLL_IS_LCD) { 976 vco_min = pll->lcd_pll_out_min; 977 vco_max = pll->lcd_pll_out_max; 978 } else { 979 vco_min = pll->pll_out_min; 980 vco_max = pll->pll_out_max; 981 } 982 983 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 984 vco_min *= 10; 985 vco_max *= 10; 986 } 987 988 post_div_min = vco_min / target_clock; 989 if ((target_clock * post_div_min) < vco_min) 990 ++post_div_min; 991 if (post_div_min < pll->min_post_div) 992 post_div_min = pll->min_post_div; 993 994 post_div_max = vco_max / target_clock; 995 if ((target_clock * post_div_max) > vco_max) 996 --post_div_max; 997 if (post_div_max > pll->max_post_div) 998 post_div_max = pll->max_post_div; 999 } 1000 1001 /* represent the searched ratio as fractional number */ 1002 nom = target_clock; 1003 den = pll->reference_freq; 1004 1005 /* reduce the numbers to a simpler ratio */ 1006 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min); 1007 1008 /* now search for a post divider */ 1009 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 1010 post_div_best = post_div_min; 1011 else 1012 post_div_best = post_div_max; 1013 diff_best = ~0; 1014 1015 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { 1016 unsigned diff; 1017 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, 1018 ref_div_max, &fb_div, &ref_div); 1019 diff = abs(target_clock - (pll->reference_freq * fb_div) / 1020 (ref_div * post_div)); 1021 1022 if (diff < diff_best || (diff == diff_best && 1023 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) { 1024 1025 post_div_best = post_div; 1026 diff_best = diff; 1027 } 1028 } 1029 post_div = post_div_best; 1030 1031 /* get the feedback and reference divider for the optimal value */ 1032 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max, 1033 &fb_div, &ref_div); 1034 1035 /* reduce the numbers to a simpler ratio once more */ 1036 /* this also makes sure that the reference divider is large enough */ 1037 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); 1038 1039 /* avoid high jitter with small fractional dividers */ 1040 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { 1041 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50); 1042 if (fb_div < fb_div_min) { 1043 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div); 1044 fb_div *= tmp; 1045 ref_div *= tmp; 1046 } 1047 } 1048 1049 /* and finally save the result */ 1050 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1051 *fb_div_p = fb_div / 10; 1052 *frac_fb_div_p = fb_div % 10; 1053 } else { 1054 *fb_div_p = fb_div; 1055 *frac_fb_div_p = 0; 1056 } 1057 1058 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + 1059 (pll->reference_freq * *frac_fb_div_p)) / 1060 (ref_div * post_div * 10); 1061 *ref_div_p = ref_div; 1062 *post_div_p = post_div; 1063 1064 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1065 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, 1066 ref_div, post_div); 1067 } 1068 1069 /* pre-avivo */ 1070 static inline uint32_t radeon_div(uint64_t n, uint32_t d) 1071 { 1072 uint64_t mod; 1073 1074 n += d / 2; 1075 1076 mod = do_div(n, d); 1077 return n; 1078 } 1079 1080 void radeon_compute_pll_legacy(struct radeon_pll *pll, 1081 uint64_t freq, 1082 uint32_t *dot_clock_p, 1083 uint32_t *fb_div_p, 1084 uint32_t *frac_fb_div_p, 1085 uint32_t *ref_div_p, 1086 uint32_t *post_div_p) 1087 { 1088 uint32_t min_ref_div = pll->min_ref_div; 1089 uint32_t max_ref_div = pll->max_ref_div; 1090 uint32_t min_post_div = pll->min_post_div; 1091 uint32_t max_post_div = pll->max_post_div; 1092 uint32_t min_fractional_feed_div = 0; 1093 uint32_t max_fractional_feed_div = 0; 1094 uint32_t best_vco = pll->best_vco; 1095 uint32_t best_post_div = 1; 1096 uint32_t best_ref_div = 1; 1097 uint32_t best_feedback_div = 1; 1098 uint32_t best_frac_feedback_div = 0; 1099 uint32_t best_freq = -1; 1100 uint32_t best_error = 0xffffffff; 1101 uint32_t best_vco_diff = 1; 1102 uint32_t post_div; 1103 u32 pll_out_min, pll_out_max; 1104 1105 DRM_DEBUG_KMS("PLL freq %ju %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); 1106 freq = freq * 1000; 1107 1108 if (pll->flags & RADEON_PLL_IS_LCD) { 1109 pll_out_min = pll->lcd_pll_out_min; 1110 pll_out_max = pll->lcd_pll_out_max; 1111 } else { 1112 pll_out_min = pll->pll_out_min; 1113 pll_out_max = pll->pll_out_max; 1114 } 1115 1116 if (pll_out_min > 64800) 1117 pll_out_min = 64800; 1118 1119 if (pll->flags & RADEON_PLL_USE_REF_DIV) 1120 min_ref_div = max_ref_div = pll->reference_div; 1121 else { 1122 while (min_ref_div < max_ref_div-1) { 1123 uint32_t mid = (min_ref_div + max_ref_div) / 2; 1124 uint32_t pll_in = pll->reference_freq / mid; 1125 if (pll_in < pll->pll_in_min) 1126 max_ref_div = mid; 1127 else if (pll_in > pll->pll_in_max) 1128 min_ref_div = mid; 1129 else 1130 break; 1131 } 1132 } 1133 1134 if (pll->flags & RADEON_PLL_USE_POST_DIV) 1135 min_post_div = max_post_div = pll->post_div; 1136 1137 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1138 min_fractional_feed_div = pll->min_frac_feedback_div; 1139 max_fractional_feed_div = pll->max_frac_feedback_div; 1140 } 1141 1142 for (post_div = max_post_div; post_div >= min_post_div; --post_div) { 1143 uint32_t ref_div; 1144 1145 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 1146 continue; 1147 1148 /* legacy radeons only have a few post_divs */ 1149 if (pll->flags & RADEON_PLL_LEGACY) { 1150 if ((post_div == 5) || 1151 (post_div == 7) || 1152 (post_div == 9) || 1153 (post_div == 10) || 1154 (post_div == 11) || 1155 (post_div == 13) || 1156 (post_div == 14) || 1157 (post_div == 15)) 1158 continue; 1159 } 1160 1161 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { 1162 uint32_t feedback_div, current_freq = 0, error, vco_diff; 1163 uint32_t pll_in = pll->reference_freq / ref_div; 1164 uint32_t min_feed_div = pll->min_feedback_div; 1165 uint32_t max_feed_div = pll->max_feedback_div + 1; 1166 1167 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) 1168 continue; 1169 1170 while (min_feed_div < max_feed_div) { 1171 uint32_t vco; 1172 uint32_t min_frac_feed_div = min_fractional_feed_div; 1173 uint32_t max_frac_feed_div = max_fractional_feed_div + 1; 1174 uint32_t frac_feedback_div; 1175 uint64_t tmp; 1176 1177 feedback_div = (min_feed_div + max_feed_div) / 2; 1178 1179 tmp = (uint64_t)pll->reference_freq * feedback_div; 1180 vco = radeon_div(tmp, ref_div); 1181 1182 if (vco < pll_out_min) { 1183 min_feed_div = feedback_div + 1; 1184 continue; 1185 } else if (vco > pll_out_max) { 1186 max_feed_div = feedback_div; 1187 continue; 1188 } 1189 1190 while (min_frac_feed_div < max_frac_feed_div) { 1191 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; 1192 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; 1193 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; 1194 current_freq = radeon_div(tmp, ref_div * post_div); 1195 1196 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 1197 if (freq < current_freq) 1198 error = 0xffffffff; 1199 else 1200 error = freq - current_freq; 1201 } else 1202 error = abs(current_freq - freq); 1203 vco_diff = abs(vco - best_vco); 1204 1205 if ((best_vco == 0 && error < best_error) || 1206 (best_vco != 0 && 1207 ((best_error > 100 && error < best_error - 100) || 1208 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { 1209 best_post_div = post_div; 1210 best_ref_div = ref_div; 1211 best_feedback_div = feedback_div; 1212 best_frac_feedback_div = frac_feedback_div; 1213 best_freq = current_freq; 1214 best_error = error; 1215 best_vco_diff = vco_diff; 1216 } else if (current_freq == freq) { 1217 if (best_freq == -1) { 1218 best_post_div = post_div; 1219 best_ref_div = ref_div; 1220 best_feedback_div = feedback_div; 1221 best_frac_feedback_div = frac_feedback_div; 1222 best_freq = current_freq; 1223 best_error = error; 1224 best_vco_diff = vco_diff; 1225 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 1226 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 1227 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 1228 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 1229 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 1230 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 1231 best_post_div = post_div; 1232 best_ref_div = ref_div; 1233 best_feedback_div = feedback_div; 1234 best_frac_feedback_div = frac_feedback_div; 1235 best_freq = current_freq; 1236 best_error = error; 1237 best_vco_diff = vco_diff; 1238 } 1239 } 1240 if (current_freq < freq) 1241 min_frac_feed_div = frac_feedback_div + 1; 1242 else 1243 max_frac_feed_div = frac_feedback_div; 1244 } 1245 if (current_freq < freq) 1246 min_feed_div = feedback_div + 1; 1247 else 1248 max_feed_div = feedback_div; 1249 } 1250 } 1251 } 1252 1253 *dot_clock_p = best_freq / 10000; 1254 *fb_div_p = best_feedback_div; 1255 *frac_fb_div_p = best_frac_feedback_div; 1256 *ref_div_p = best_ref_div; 1257 *post_div_p = best_post_div; 1258 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1259 (long long)freq, 1260 best_freq / 1000, best_feedback_div, best_frac_feedback_div, 1261 best_ref_div, best_post_div); 1262 1263 } 1264 1265 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) 1266 { 1267 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1268 1269 if (radeon_fb->obj) { 1270 drm_gem_object_unreference_unlocked(radeon_fb->obj); 1271 } 1272 drm_framebuffer_cleanup(fb); 1273 kfree(radeon_fb); 1274 } 1275 1276 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, 1277 struct drm_file *file_priv, 1278 unsigned int *handle) 1279 { 1280 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1281 1282 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); 1283 } 1284 1285 static const struct drm_framebuffer_funcs radeon_fb_funcs = { 1286 .destroy = radeon_user_framebuffer_destroy, 1287 .create_handle = radeon_user_framebuffer_create_handle, 1288 }; 1289 1290 int 1291 radeon_framebuffer_init(struct drm_device *dev, 1292 struct radeon_framebuffer *rfb, 1293 const struct drm_mode_fb_cmd2 *mode_cmd, 1294 struct drm_gem_object *obj) 1295 { 1296 int ret; 1297 rfb->obj = obj; 1298 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); 1299 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); 1300 if (ret) { 1301 rfb->obj = NULL; 1302 return ret; 1303 } 1304 return 0; 1305 } 1306 1307 static struct drm_framebuffer * 1308 radeon_user_framebuffer_create(struct drm_device *dev, 1309 struct drm_file *file_priv, 1310 const struct drm_mode_fb_cmd2 *mode_cmd) 1311 { 1312 struct drm_gem_object *obj; 1313 struct radeon_framebuffer *radeon_fb; 1314 int ret; 1315 1316 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); 1317 if (obj == NULL) { 1318 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 1319 "can't create framebuffer\n", mode_cmd->handles[0]); 1320 return ERR_PTR(-ENOENT); 1321 } 1322 1323 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); 1324 if (radeon_fb == NULL) { 1325 drm_gem_object_unreference_unlocked(obj); 1326 return ERR_PTR(-ENOMEM); 1327 } 1328 1329 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj); 1330 if (ret) { 1331 kfree(radeon_fb); 1332 drm_gem_object_unreference_unlocked(obj); 1333 return ERR_PTR(ret); 1334 } 1335 1336 return &radeon_fb->base; 1337 } 1338 1339 static void radeon_output_poll_changed(struct drm_device *dev) 1340 { 1341 struct radeon_device *rdev = dev->dev_private; 1342 radeon_fb_output_poll_changed(rdev); 1343 } 1344 1345 static const struct drm_mode_config_funcs radeon_mode_funcs = { 1346 .fb_create = radeon_user_framebuffer_create, 1347 .output_poll_changed = radeon_output_poll_changed 1348 }; 1349 1350 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = 1351 { { 0, "driver" }, 1352 { 1, "bios" }, 1353 }; 1354 1355 static struct drm_prop_enum_list radeon_tv_std_enum_list[] = 1356 { { TV_STD_NTSC, "ntsc" }, 1357 { TV_STD_PAL, "pal" }, 1358 { TV_STD_PAL_M, "pal-m" }, 1359 { TV_STD_PAL_60, "pal-60" }, 1360 { TV_STD_NTSC_J, "ntsc-j" }, 1361 { TV_STD_SCART_PAL, "scart-pal" }, 1362 { TV_STD_PAL_CN, "pal-cn" }, 1363 { TV_STD_SECAM, "secam" }, 1364 }; 1365 1366 static struct drm_prop_enum_list radeon_underscan_enum_list[] = 1367 { { UNDERSCAN_OFF, "off" }, 1368 { UNDERSCAN_ON, "on" }, 1369 { UNDERSCAN_AUTO, "auto" }, 1370 }; 1371 1372 static struct drm_prop_enum_list radeon_audio_enum_list[] = 1373 { { RADEON_AUDIO_DISABLE, "off" }, 1374 { RADEON_AUDIO_ENABLE, "on" }, 1375 { RADEON_AUDIO_AUTO, "auto" }, 1376 }; 1377 1378 /* XXX support different dither options? spatial, temporal, both, etc. */ 1379 static struct drm_prop_enum_list radeon_dither_enum_list[] = 1380 { { RADEON_FMT_DITHER_DISABLE, "off" }, 1381 { RADEON_FMT_DITHER_ENABLE, "on" }, 1382 }; 1383 1384 static int radeon_modeset_create_props(struct radeon_device *rdev) 1385 { 1386 int sz; 1387 1388 if (rdev->is_atom_bios) { 1389 rdev->mode_info.coherent_mode_property = 1390 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1); 1391 if (!rdev->mode_info.coherent_mode_property) 1392 return -ENOMEM; 1393 } 1394 1395 if (!ASIC_IS_AVIVO(rdev)) { 1396 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); 1397 rdev->mode_info.tmds_pll_property = 1398 drm_property_create_enum(rdev->ddev, 0, 1399 "tmds_pll", 1400 radeon_tmds_pll_enum_list, sz); 1401 } 1402 1403 rdev->mode_info.load_detect_property = 1404 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1); 1405 if (!rdev->mode_info.load_detect_property) 1406 return -ENOMEM; 1407 1408 drm_mode_create_scaling_mode_property(rdev->ddev); 1409 1410 sz = ARRAY_SIZE(radeon_tv_std_enum_list); 1411 rdev->mode_info.tv_std_property = 1412 drm_property_create_enum(rdev->ddev, 0, 1413 "tv standard", 1414 radeon_tv_std_enum_list, sz); 1415 1416 sz = ARRAY_SIZE(radeon_underscan_enum_list); 1417 rdev->mode_info.underscan_property = 1418 drm_property_create_enum(rdev->ddev, 0, 1419 "underscan", 1420 radeon_underscan_enum_list, sz); 1421 1422 rdev->mode_info.underscan_hborder_property = 1423 drm_property_create_range(rdev->ddev, 0, 1424 "underscan hborder", 0, 128); 1425 if (!rdev->mode_info.underscan_hborder_property) 1426 return -ENOMEM; 1427 1428 rdev->mode_info.underscan_vborder_property = 1429 drm_property_create_range(rdev->ddev, 0, 1430 "underscan vborder", 0, 128); 1431 if (!rdev->mode_info.underscan_vborder_property) 1432 return -ENOMEM; 1433 1434 sz = ARRAY_SIZE(radeon_audio_enum_list); 1435 rdev->mode_info.audio_property = 1436 drm_property_create_enum(rdev->ddev, 0, 1437 "audio", 1438 radeon_audio_enum_list, sz); 1439 1440 sz = ARRAY_SIZE(radeon_dither_enum_list); 1441 rdev->mode_info.dither_property = 1442 drm_property_create_enum(rdev->ddev, 0, 1443 "dither", 1444 radeon_dither_enum_list, sz); 1445 1446 return 0; 1447 } 1448 1449 void radeon_update_display_priority(struct radeon_device *rdev) 1450 { 1451 /* adjustment options for the display watermarks */ 1452 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { 1453 /* set display priority to high for r3xx, rv515 chips 1454 * this avoids flickering due to underflow to the 1455 * display controllers during heavy acceleration. 1456 * Don't force high on rs4xx igp chips as it seems to 1457 * affect the sound card. See kernel bug 15982. 1458 */ 1459 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && 1460 !(rdev->flags & RADEON_IS_IGP)) 1461 rdev->disp_priority = 2; 1462 else 1463 rdev->disp_priority = 0; 1464 } else 1465 rdev->disp_priority = radeon_disp_priority; 1466 1467 } 1468 1469 /* 1470 * Allocate hdmi structs and determine register offsets 1471 */ 1472 static void radeon_afmt_init(struct radeon_device *rdev) 1473 { 1474 int i; 1475 1476 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) 1477 rdev->mode_info.afmt[i] = NULL; 1478 1479 if (ASIC_IS_NODCE(rdev)) { 1480 /* nothing to do */ 1481 } else if (ASIC_IS_DCE4(rdev)) { 1482 static uint32_t eg_offsets[] = { 1483 EVERGREEN_CRTC0_REGISTER_OFFSET, 1484 EVERGREEN_CRTC1_REGISTER_OFFSET, 1485 EVERGREEN_CRTC2_REGISTER_OFFSET, 1486 EVERGREEN_CRTC3_REGISTER_OFFSET, 1487 EVERGREEN_CRTC4_REGISTER_OFFSET, 1488 EVERGREEN_CRTC5_REGISTER_OFFSET, 1489 0x13830 - 0x7030, 1490 }; 1491 int num_afmt; 1492 1493 /* DCE8 has 7 audio blocks tied to DIG encoders */ 1494 /* DCE6 has 6 audio blocks tied to DIG encoders */ 1495 /* DCE4/5 has 6 audio blocks tied to DIG encoders */ 1496 /* DCE4.1 has 2 audio blocks tied to DIG encoders */ 1497 if (ASIC_IS_DCE8(rdev)) 1498 num_afmt = 7; 1499 else if (ASIC_IS_DCE6(rdev)) 1500 num_afmt = 6; 1501 else if (ASIC_IS_DCE5(rdev)) 1502 num_afmt = 6; 1503 else if (ASIC_IS_DCE41(rdev)) 1504 num_afmt = 2; 1505 else /* DCE4 */ 1506 num_afmt = 6; 1507 1508 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets)); 1509 for (i = 0; i < num_afmt; i++) { 1510 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1511 if (rdev->mode_info.afmt[i]) { 1512 rdev->mode_info.afmt[i]->offset = eg_offsets[i]; 1513 rdev->mode_info.afmt[i]->id = i; 1514 } 1515 } 1516 } else if (ASIC_IS_DCE3(rdev)) { 1517 /* DCE3.x has 2 audio blocks tied to DIG encoders */ 1518 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1519 if (rdev->mode_info.afmt[0]) { 1520 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0; 1521 rdev->mode_info.afmt[0]->id = 0; 1522 } 1523 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1524 if (rdev->mode_info.afmt[1]) { 1525 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1; 1526 rdev->mode_info.afmt[1]->id = 1; 1527 } 1528 } else if (ASIC_IS_DCE2(rdev)) { 1529 /* DCE2 has at least 1 routable audio block */ 1530 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1531 if (rdev->mode_info.afmt[0]) { 1532 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0; 1533 rdev->mode_info.afmt[0]->id = 0; 1534 } 1535 /* r6xx has 2 routable audio blocks */ 1536 if (rdev->family >= CHIP_R600) { 1537 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1538 if (rdev->mode_info.afmt[1]) { 1539 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1; 1540 rdev->mode_info.afmt[1]->id = 1; 1541 } 1542 } 1543 } 1544 } 1545 1546 static void radeon_afmt_fini(struct radeon_device *rdev) 1547 { 1548 int i; 1549 1550 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) { 1551 kfree(rdev->mode_info.afmt[i]); 1552 rdev->mode_info.afmt[i] = NULL; 1553 } 1554 } 1555 1556 int radeon_modeset_init(struct radeon_device *rdev) 1557 { 1558 int i; 1559 int ret; 1560 1561 drm_mode_config_init(rdev->ddev); 1562 rdev->mode_info.mode_config_initialized = true; 1563 1564 rdev->ddev->mode_config.funcs = &radeon_mode_funcs; 1565 1566 if (ASIC_IS_DCE5(rdev)) { 1567 rdev->ddev->mode_config.max_width = 16384; 1568 rdev->ddev->mode_config.max_height = 16384; 1569 } else if (ASIC_IS_AVIVO(rdev)) { 1570 rdev->ddev->mode_config.max_width = 8192; 1571 rdev->ddev->mode_config.max_height = 8192; 1572 } else { 1573 rdev->ddev->mode_config.max_width = 4096; 1574 rdev->ddev->mode_config.max_height = 4096; 1575 } 1576 1577 rdev->ddev->mode_config.preferred_depth = 24; 1578 rdev->ddev->mode_config.prefer_shadow = 1; 1579 1580 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; 1581 1582 ret = radeon_modeset_create_props(rdev); 1583 if (ret) { 1584 return ret; 1585 } 1586 1587 /* init i2c buses */ 1588 radeon_i2c_init(rdev); 1589 1590 /* check combios for a valid hardcoded EDID - Sun servers */ 1591 if (!rdev->is_atom_bios) { 1592 /* check for hardcoded EDID in BIOS */ 1593 radeon_combios_check_hardcoded_edid(rdev); 1594 } 1595 1596 /* allocate crtcs */ 1597 for (i = 0; i < rdev->num_crtc; i++) { 1598 radeon_crtc_init(rdev->ddev, i); 1599 } 1600 1601 /* okay we should have all the bios connectors */ 1602 ret = radeon_setup_enc_conn(rdev->ddev); 1603 if (!ret) { 1604 return ret; 1605 } 1606 1607 /* init dig PHYs, disp eng pll */ 1608 if (rdev->is_atom_bios) { 1609 radeon_atom_encoder_init(rdev); 1610 radeon_atom_disp_eng_pll_init(rdev); 1611 } 1612 1613 /* initialize hpd */ 1614 radeon_hpd_init(rdev); 1615 1616 /* setup afmt */ 1617 radeon_afmt_init(rdev); 1618 1619 radeon_fbdev_init(rdev); 1620 drm_kms_helper_poll_init(rdev->ddev); 1621 1622 if (rdev->pm.dpm_enabled) { 1623 /* do dpm late init */ 1624 ret = radeon_pm_late_init(rdev); 1625 if (ret) { 1626 rdev->pm.dpm_enabled = false; 1627 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1628 } 1629 /* set the dpm state for PX since there won't be 1630 * a modeset to call this. 1631 */ 1632 radeon_pm_compute_clocks(rdev); 1633 } 1634 1635 return 0; 1636 } 1637 1638 void radeon_modeset_fini(struct radeon_device *rdev) 1639 { 1640 radeon_fbdev_fini(rdev); 1641 kfree(rdev->mode_info.bios_hardcoded_edid); 1642 1643 if (rdev->mode_info.mode_config_initialized) { 1644 radeon_afmt_fini(rdev); 1645 drm_kms_helper_poll_fini(rdev->ddev); 1646 radeon_hpd_fini(rdev); 1647 DRM_UNLOCK(rdev->ddev); /* Work around lock recursion. dumbbell@ */ 1648 drm_mode_config_cleanup(rdev->ddev); 1649 DRM_LOCK(rdev->ddev); 1650 rdev->mode_info.mode_config_initialized = false; 1651 } 1652 /* free i2c buses */ 1653 radeon_i2c_fini(rdev); 1654 } 1655 1656 static bool is_hdtv_mode(const struct drm_display_mode *mode) 1657 { 1658 /* try and guess if this is a tv or a monitor */ 1659 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 1660 (mode->vdisplay == 576) || /* 576p */ 1661 (mode->vdisplay == 720) || /* 720p */ 1662 (mode->vdisplay == 1080)) /* 1080p */ 1663 return true; 1664 else 1665 return false; 1666 } 1667 1668 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 1669 const struct drm_display_mode *mode, 1670 struct drm_display_mode *adjusted_mode) 1671 { 1672 struct drm_device *dev = crtc->dev; 1673 struct radeon_device *rdev = dev->dev_private; 1674 struct drm_encoder *encoder; 1675 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1676 struct radeon_encoder *radeon_encoder; 1677 struct drm_connector *connector; 1678 struct radeon_connector *radeon_connector; 1679 bool first = true; 1680 u32 src_v = 1, dst_v = 1; 1681 u32 src_h = 1, dst_h = 1; 1682 1683 radeon_crtc->h_border = 0; 1684 radeon_crtc->v_border = 0; 1685 1686 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1687 if (encoder->crtc != crtc) 1688 continue; 1689 radeon_encoder = to_radeon_encoder(encoder); 1690 connector = radeon_get_connector_for_encoder(encoder); 1691 radeon_connector = to_radeon_connector(connector); 1692 1693 if (first) { 1694 /* set scaling */ 1695 if (radeon_encoder->rmx_type == RMX_OFF) 1696 radeon_crtc->rmx_type = RMX_OFF; 1697 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || 1698 mode->vdisplay < radeon_encoder->native_mode.vdisplay) 1699 radeon_crtc->rmx_type = radeon_encoder->rmx_type; 1700 else 1701 radeon_crtc->rmx_type = RMX_OFF; 1702 /* copy native mode */ 1703 memcpy(&radeon_crtc->native_mode, 1704 &radeon_encoder->native_mode, 1705 sizeof(struct drm_display_mode)); 1706 src_v = crtc->mode.vdisplay; 1707 dst_v = radeon_crtc->native_mode.vdisplay; 1708 src_h = crtc->mode.hdisplay; 1709 dst_h = radeon_crtc->native_mode.hdisplay; 1710 1711 /* fix up for overscan on hdmi */ 1712 if (ASIC_IS_AVIVO(rdev) && 1713 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 1714 ((radeon_encoder->underscan_type == UNDERSCAN_ON) || 1715 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && 1716 drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 1717 is_hdtv_mode(mode)))) { 1718 if (radeon_encoder->underscan_hborder != 0) 1719 radeon_crtc->h_border = radeon_encoder->underscan_hborder; 1720 else 1721 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; 1722 if (radeon_encoder->underscan_vborder != 0) 1723 radeon_crtc->v_border = radeon_encoder->underscan_vborder; 1724 else 1725 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; 1726 radeon_crtc->rmx_type = RMX_FULL; 1727 src_v = crtc->mode.vdisplay; 1728 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); 1729 src_h = crtc->mode.hdisplay; 1730 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); 1731 } 1732 first = false; 1733 } else { 1734 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { 1735 /* WARNING: Right now this can't happen but 1736 * in the future we need to check that scaling 1737 * are consistent across different encoder 1738 * (ie all encoder can work with the same 1739 * scaling). 1740 */ 1741 DRM_ERROR("Scaling not consistent across encoder.\n"); 1742 return false; 1743 } 1744 } 1745 } 1746 if (radeon_crtc->rmx_type != RMX_OFF) { 1747 fixed20_12 a, b; 1748 a.full = dfixed_const(src_v); 1749 b.full = dfixed_const(dst_v); 1750 radeon_crtc->vsc.full = dfixed_div(a, b); 1751 a.full = dfixed_const(src_h); 1752 b.full = dfixed_const(dst_h); 1753 radeon_crtc->hsc.full = dfixed_div(a, b); 1754 } else { 1755 radeon_crtc->vsc.full = dfixed_const(1); 1756 radeon_crtc->hsc.full = dfixed_const(1); 1757 } 1758 return true; 1759 } 1760 1761 /* 1762 * Retrieve current video scanout position of crtc on a given gpu, and 1763 * an optional accurate timestamp of when query happened. 1764 * 1765 * \param dev Device to query. 1766 * \param crtc Crtc to query. 1767 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 1768 * \param *vpos Location where vertical scanout position should be stored. 1769 * \param *hpos Location where horizontal scanout position should go. 1770 * \param *stime Target location for timestamp taken immediately before 1771 * scanout position query. Can be NULL to skip timestamp. 1772 * \param *etime Target location for timestamp taken immediately after 1773 * scanout position query. Can be NULL to skip timestamp. 1774 * 1775 * Returns vpos as a positive number while in active scanout area. 1776 * Returns vpos as a negative number inside vblank, counting the number 1777 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 1778 * until start of active scanout / end of vblank." 1779 * 1780 * \return Flags, or'ed together as follows: 1781 * 1782 * DRM_SCANOUTPOS_VALID = Query successful. 1783 * DRM_SCANOUTPOS_INVBL = Inside vblank. 1784 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 1785 * this flag means that returned position may be offset by a constant but 1786 * unknown small number of scanlines wrt. real scanout position. 1787 * 1788 */ 1789 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags, 1790 int *vpos, int *hpos, ktime_t *stime, ktime_t *etime, 1791 const struct drm_display_mode *mode) 1792 { 1793 u32 stat_crtc = 0, vbl = 0, position = 0; 1794 int vbl_start, vbl_end, vtotal, ret = 0; 1795 bool in_vbl = true; 1796 1797 struct radeon_device *rdev = dev->dev_private; 1798 1799 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 1800 1801 /* Get optional system timestamp before query. */ 1802 if (stime) 1803 *stime = ktime_get(); 1804 1805 if (ASIC_IS_DCE4(rdev)) { 1806 if (crtc == 0) { 1807 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1808 EVERGREEN_CRTC0_REGISTER_OFFSET); 1809 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1810 EVERGREEN_CRTC0_REGISTER_OFFSET); 1811 ret |= DRM_SCANOUTPOS_VALID; 1812 } 1813 if (crtc == 1) { 1814 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1815 EVERGREEN_CRTC1_REGISTER_OFFSET); 1816 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1817 EVERGREEN_CRTC1_REGISTER_OFFSET); 1818 ret |= DRM_SCANOUTPOS_VALID; 1819 } 1820 if (crtc == 2) { 1821 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1822 EVERGREEN_CRTC2_REGISTER_OFFSET); 1823 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1824 EVERGREEN_CRTC2_REGISTER_OFFSET); 1825 ret |= DRM_SCANOUTPOS_VALID; 1826 } 1827 if (crtc == 3) { 1828 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1829 EVERGREEN_CRTC3_REGISTER_OFFSET); 1830 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1831 EVERGREEN_CRTC3_REGISTER_OFFSET); 1832 ret |= DRM_SCANOUTPOS_VALID; 1833 } 1834 if (crtc == 4) { 1835 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1836 EVERGREEN_CRTC4_REGISTER_OFFSET); 1837 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1838 EVERGREEN_CRTC4_REGISTER_OFFSET); 1839 ret |= DRM_SCANOUTPOS_VALID; 1840 } 1841 if (crtc == 5) { 1842 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1843 EVERGREEN_CRTC5_REGISTER_OFFSET); 1844 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1845 EVERGREEN_CRTC5_REGISTER_OFFSET); 1846 ret |= DRM_SCANOUTPOS_VALID; 1847 } 1848 } else if (ASIC_IS_AVIVO(rdev)) { 1849 if (crtc == 0) { 1850 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); 1851 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); 1852 ret |= DRM_SCANOUTPOS_VALID; 1853 } 1854 if (crtc == 1) { 1855 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); 1856 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); 1857 ret |= DRM_SCANOUTPOS_VALID; 1858 } 1859 } else { 1860 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ 1861 if (crtc == 0) { 1862 /* Assume vbl_end == 0, get vbl_start from 1863 * upper 16 bits. 1864 */ 1865 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & 1866 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1867 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ 1868 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1869 stat_crtc = RREG32(RADEON_CRTC_STATUS); 1870 if (!(stat_crtc & 1)) 1871 in_vbl = false; 1872 1873 ret |= DRM_SCANOUTPOS_VALID; 1874 } 1875 if (crtc == 1) { 1876 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & 1877 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1878 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1879 stat_crtc = RREG32(RADEON_CRTC2_STATUS); 1880 if (!(stat_crtc & 1)) 1881 in_vbl = false; 1882 1883 ret |= DRM_SCANOUTPOS_VALID; 1884 } 1885 } 1886 1887 /* Get optional system timestamp after query. */ 1888 if (etime) 1889 *etime = ktime_get(); 1890 1891 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 1892 1893 /* Decode into vertical and horizontal scanout position. */ 1894 *vpos = position & 0x1fff; 1895 *hpos = (position >> 16) & 0x1fff; 1896 1897 /* Valid vblank area boundaries from gpu retrieved? */ 1898 if (vbl > 0) { 1899 /* Yes: Decode. */ 1900 ret |= DRM_SCANOUTPOS_ACCURATE; 1901 vbl_start = vbl & 0x1fff; 1902 vbl_end = (vbl >> 16) & 0x1fff; 1903 } 1904 else { 1905 /* No: Fake something reasonable which gives at least ok results. */ 1906 vbl_start = mode->crtc_vdisplay; 1907 vbl_end = 0; 1908 } 1909 1910 /* Test scanout position against vblank region. */ 1911 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 1912 in_vbl = false; 1913 1914 /* Check if inside vblank area and apply corrective offsets: 1915 * vpos will then be >=0 in video scanout area, but negative 1916 * within vblank area, counting down the number of lines until 1917 * start of scanout. 1918 */ 1919 1920 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 1921 if (in_vbl && (*vpos >= vbl_start)) { 1922 vtotal = mode->crtc_vtotal; 1923 *vpos = *vpos - vtotal; 1924 } 1925 1926 /* Correct for shifted end of vbl at vbl_end. */ 1927 *vpos = *vpos - vbl_end; 1928 1929 /* In vblank? */ 1930 if (in_vbl) 1931 ret |= DRM_SCANOUTPOS_IN_VBLANK; 1932 1933 /* Is vpos outside nominal vblank area, but less than 1934 * 1/100 of a frame height away from start of vblank? 1935 * If so, assume this isn't a massively delayed vblank 1936 * interrupt, but a vblank interrupt that fired a few 1937 * microseconds before true start of vblank. Compensate 1938 * by adding a full frame duration to the final timestamp. 1939 * Happens, e.g., on ATI R500, R600. 1940 * 1941 * We only do this if DRM_CALLED_FROM_VBLIRQ. 1942 */ 1943 if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) { 1944 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay; 1945 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal; 1946 1947 if (vbl_start - *vpos < vtotal / 100) { 1948 *vpos -= vtotal; 1949 1950 /* Signal this correction as "applied". */ 1951 ret |= 0x8; 1952 } 1953 } 1954 1955 return ret; 1956 } 1957