1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * 26 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_display.c 254885 2013-08-25 19:37:15Z dumbbell $ 27 */ 28 29 #include <drm/drmP.h> 30 #include <uapi_drm/radeon_drm.h> 31 #include "radeon.h" 32 33 #include "atom.h" 34 35 #include <drm/drm_crtc_helper.h> 36 #include <drm/drm_edid.h> 37 38 static void avivo_crtc_load_lut(struct drm_crtc *crtc) 39 { 40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 41 struct drm_device *dev = crtc->dev; 42 struct radeon_device *rdev = dev->dev_private; 43 int i; 44 45 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 46 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); 47 48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 51 52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 55 56 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); 57 WREG32(AVIVO_DC_LUT_RW_MODE, 0); 58 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); 59 60 WREG8(AVIVO_DC_LUT_RW_INDEX, 0); 61 for (i = 0; i < 256; i++) { 62 WREG32(AVIVO_DC_LUT_30_COLOR, 63 (radeon_crtc->lut_r[i] << 20) | 64 (radeon_crtc->lut_g[i] << 10) | 65 (radeon_crtc->lut_b[i] << 0)); 66 } 67 68 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); 69 } 70 71 static void dce4_crtc_load_lut(struct drm_crtc *crtc) 72 { 73 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 74 struct drm_device *dev = crtc->dev; 75 struct radeon_device *rdev = dev->dev_private; 76 int i; 77 78 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 79 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 80 81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 82 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 84 85 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 86 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 88 89 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 90 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 91 92 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 93 for (i = 0; i < 256; i++) { 94 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 95 (radeon_crtc->lut_r[i] << 20) | 96 (radeon_crtc->lut_g[i] << 10) | 97 (radeon_crtc->lut_b[i] << 0)); 98 } 99 } 100 101 static void dce5_crtc_load_lut(struct drm_crtc *crtc) 102 { 103 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 104 struct drm_device *dev = crtc->dev; 105 struct radeon_device *rdev = dev->dev_private; 106 int i; 107 108 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 109 110 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 111 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | 112 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); 113 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, 114 NI_GRPH_PRESCALE_BYPASS); 115 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, 116 NI_OVL_PRESCALE_BYPASS); 117 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, 118 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | 119 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); 120 121 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 122 123 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 124 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 125 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 126 127 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 128 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 129 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 130 131 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 132 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 133 134 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 135 for (i = 0; i < 256; i++) { 136 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 137 (radeon_crtc->lut_r[i] << 20) | 138 (radeon_crtc->lut_g[i] << 10) | 139 (radeon_crtc->lut_b[i] << 0)); 140 } 141 142 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, 143 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 144 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 145 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 146 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); 147 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, 148 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | 149 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); 150 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, 151 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | 152 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); 153 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 154 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) | 155 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); 156 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 157 WREG32(0x6940 + radeon_crtc->crtc_offset, 0); 158 159 } 160 161 static void legacy_crtc_load_lut(struct drm_crtc *crtc) 162 { 163 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 164 struct drm_device *dev = crtc->dev; 165 struct radeon_device *rdev = dev->dev_private; 166 int i; 167 uint32_t dac2_cntl; 168 169 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 170 if (radeon_crtc->crtc_id == 0) 171 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; 172 else 173 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; 174 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 175 176 WREG8(RADEON_PALETTE_INDEX, 0); 177 for (i = 0; i < 256; i++) { 178 WREG32(RADEON_PALETTE_30_DATA, 179 (radeon_crtc->lut_r[i] << 20) | 180 (radeon_crtc->lut_g[i] << 10) | 181 (radeon_crtc->lut_b[i] << 0)); 182 } 183 } 184 185 void radeon_crtc_load_lut(struct drm_crtc *crtc) 186 { 187 struct drm_device *dev = crtc->dev; 188 struct radeon_device *rdev = dev->dev_private; 189 190 if (!crtc->enabled) 191 return; 192 193 if (ASIC_IS_DCE5(rdev)) 194 dce5_crtc_load_lut(crtc); 195 else if (ASIC_IS_DCE4(rdev)) 196 dce4_crtc_load_lut(crtc); 197 else if (ASIC_IS_AVIVO(rdev)) 198 avivo_crtc_load_lut(crtc); 199 else 200 legacy_crtc_load_lut(crtc); 201 } 202 203 /** Sets the color ramps on behalf of fbcon */ 204 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 205 u16 blue, int regno) 206 { 207 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 208 209 radeon_crtc->lut_r[regno] = red >> 6; 210 radeon_crtc->lut_g[regno] = green >> 6; 211 radeon_crtc->lut_b[regno] = blue >> 6; 212 } 213 214 /** Gets the color ramps on behalf of fbcon */ 215 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 216 u16 *blue, int regno) 217 { 218 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 219 220 *red = radeon_crtc->lut_r[regno] << 6; 221 *green = radeon_crtc->lut_g[regno] << 6; 222 *blue = radeon_crtc->lut_b[regno] << 6; 223 } 224 225 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 226 u16 *blue, uint32_t start, uint32_t size) 227 { 228 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 229 int end = (start + size > 256) ? 256 : start + size, i; 230 231 /* userspace palettes are always correct as is */ 232 for (i = start; i < end; i++) { 233 radeon_crtc->lut_r[i] = red[i] >> 6; 234 radeon_crtc->lut_g[i] = green[i] >> 6; 235 radeon_crtc->lut_b[i] = blue[i] >> 6; 236 } 237 radeon_crtc_load_lut(crtc); 238 } 239 240 static void radeon_crtc_destroy(struct drm_crtc *crtc) 241 { 242 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 243 244 drm_crtc_cleanup(crtc); 245 drm_free(radeon_crtc, DRM_MEM_DRIVER); 246 } 247 248 /* 249 * Handle unpin events outside the interrupt handler proper. 250 */ 251 static void radeon_unpin_work_func(void *arg, int pending) 252 { 253 struct radeon_unpin_work *work = arg; 254 int r; 255 256 /* unpin of the old buffer */ 257 r = radeon_bo_reserve(work->old_rbo, false); 258 if (likely(r == 0)) { 259 r = radeon_bo_unpin(work->old_rbo); 260 if (unlikely(r != 0)) { 261 DRM_ERROR("failed to unpin buffer after flip\n"); 262 } 263 radeon_bo_unreserve(work->old_rbo); 264 } else 265 DRM_ERROR("failed to reserve buffer after flip\n"); 266 267 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 268 drm_free(work, DRM_MEM_DRIVER); 269 } 270 271 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) 272 { 273 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 274 struct radeon_unpin_work *work; 275 struct drm_pending_vblank_event *e; 276 struct timeval now; 277 u32 update_pending; 278 int vpos, hpos; 279 280 lockmgr(&rdev->ddev->event_lock, LK_EXCLUSIVE); 281 work = radeon_crtc->unpin_work; 282 if (work == NULL || 283 (work->fence && !radeon_fence_signaled(work->fence))) { 284 lockmgr(&rdev->ddev->event_lock, LK_RELEASE); 285 return; 286 } 287 /* New pageflip, or just completion of a previous one? */ 288 if (!radeon_crtc->deferred_flip_completion) { 289 /* do the flip (mmio) */ 290 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base); 291 } else { 292 /* This is just a completion of a flip queued in crtc 293 * at last invocation. Make sure we go directly to 294 * completion routine. 295 */ 296 update_pending = 0; 297 radeon_crtc->deferred_flip_completion = 0; 298 } 299 300 /* Has the pageflip already completed in crtc, or is it certain 301 * to complete in this vblank? 302 */ 303 if (update_pending && 304 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 305 &vpos, &hpos)) && 306 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) || 307 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) { 308 /* crtc didn't flip in this target vblank interval, 309 * but flip is pending in crtc. Based on the current 310 * scanout position we know that the current frame is 311 * (nearly) complete and the flip will (likely) 312 * complete before the start of the next frame. 313 */ 314 update_pending = 0; 315 } 316 if (update_pending) { 317 /* crtc didn't flip in this target vblank interval, 318 * but flip is pending in crtc. It will complete it 319 * in next vblank interval, so complete the flip at 320 * next vblank irq. 321 */ 322 radeon_crtc->deferred_flip_completion = 1; 323 lockmgr(&rdev->ddev->event_lock, LK_RELEASE); 324 return; 325 } 326 327 /* Pageflip (will be) certainly completed in this vblank. Clean up. */ 328 radeon_crtc->unpin_work = NULL; 329 330 /* wakeup userspace */ 331 if (work->event) { 332 e = work->event; 333 e->event.sequence = drm_vblank_count_and_time(rdev->ddev, crtc_id, &now); 334 e->event.tv_sec = now.tv_sec; 335 e->event.tv_usec = now.tv_usec; 336 list_add_tail(&e->base.link, &e->base.file_priv->event_list); 337 #ifdef DUMBBELL_WIP 338 wake_up_interruptible(&e->base.file_priv->event_wait); 339 #endif /* DUMBBELL_WIP */ 340 } 341 lockmgr(&rdev->ddev->event_lock, LK_RELEASE); 342 343 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id); 344 radeon_fence_unref(&work->fence); 345 radeon_post_page_flip(work->rdev, work->crtc_id); 346 taskqueue_enqueue(rdev->tq, &work->work); 347 } 348 349 static int radeon_crtc_page_flip(struct drm_crtc *crtc, 350 struct drm_framebuffer *fb, 351 struct drm_pending_vblank_event *event) 352 { 353 struct drm_device *dev = crtc->dev; 354 struct radeon_device *rdev = dev->dev_private; 355 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 356 struct radeon_framebuffer *old_radeon_fb; 357 struct radeon_framebuffer *new_radeon_fb; 358 struct drm_gem_object *obj; 359 struct radeon_bo *rbo; 360 struct radeon_unpin_work *work; 361 u32 tiling_flags, pitch_pixels; 362 u64 base; 363 int r; 364 365 work = kmalloc(sizeof *work, DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 366 if (work == NULL) 367 return -ENOMEM; 368 369 work->event = event; 370 work->rdev = rdev; 371 work->crtc_id = radeon_crtc->crtc_id; 372 old_radeon_fb = to_radeon_framebuffer(crtc->fb); 373 new_radeon_fb = to_radeon_framebuffer(fb); 374 /* schedule unpin of the old buffer */ 375 obj = old_radeon_fb->obj; 376 /* take a reference to the old object */ 377 drm_gem_object_reference(obj); 378 rbo = gem_to_radeon_bo(obj); 379 work->old_rbo = rbo; 380 obj = new_radeon_fb->obj; 381 rbo = gem_to_radeon_bo(obj); 382 383 lockmgr(&rbo->tbo.bdev->fence_lock, LK_EXCLUSIVE); 384 if (rbo->tbo.sync_obj) 385 work->fence = radeon_fence_ref(rbo->tbo.sync_obj); 386 lockmgr(&rbo->tbo.bdev->fence_lock, LK_RELEASE); 387 388 TASK_INIT(&work->work, 0, radeon_unpin_work_func, work); 389 390 /* We borrow the event spin lock for protecting unpin_work */ 391 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 392 if (radeon_crtc->unpin_work) { 393 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 394 r = -EBUSY; 395 goto unlock_free; 396 } 397 radeon_crtc->unpin_work = work; 398 radeon_crtc->deferred_flip_completion = 0; 399 lockmgr(&dev->event_lock, LK_RELEASE); 400 401 /* pin the new buffer */ 402 DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n", 403 work->old_rbo, rbo); 404 405 r = radeon_bo_reserve(rbo, false); 406 if (unlikely(r != 0)) { 407 DRM_ERROR("failed to reserve new rbo buffer before flip\n"); 408 goto pflip_cleanup; 409 } 410 /* Only 27 bit offset for legacy CRTC */ 411 r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 412 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base); 413 if (unlikely(r != 0)) { 414 radeon_bo_unreserve(rbo); 415 r = -EINVAL; 416 DRM_ERROR("failed to pin new rbo buffer before flip\n"); 417 goto pflip_cleanup; 418 } 419 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 420 radeon_bo_unreserve(rbo); 421 422 if (!ASIC_IS_AVIVO(rdev)) { 423 /* crtc offset is from display base addr not FB location */ 424 base -= radeon_crtc->legacy_display_base_addr; 425 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8); 426 427 if (tiling_flags & RADEON_TILING_MACRO) { 428 if (ASIC_IS_R300(rdev)) { 429 base &= ~0x7ff; 430 } else { 431 int byteshift = fb->bits_per_pixel >> 4; 432 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11; 433 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8); 434 } 435 } else { 436 int offset = crtc->y * pitch_pixels + crtc->x; 437 switch (fb->bits_per_pixel) { 438 case 8: 439 default: 440 offset *= 1; 441 break; 442 case 15: 443 case 16: 444 offset *= 2; 445 break; 446 case 24: 447 offset *= 3; 448 break; 449 case 32: 450 offset *= 4; 451 break; 452 } 453 base += offset; 454 } 455 base &= ~7; 456 } 457 458 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 459 work->new_crtc_base = base; 460 lockmgr(&dev->event_lock, LK_RELEASE); 461 462 /* update crtc fb */ 463 crtc->fb = fb; 464 465 r = drm_vblank_get(dev, radeon_crtc->crtc_id); 466 if (r) { 467 DRM_ERROR("failed to get vblank before flip\n"); 468 goto pflip_cleanup1; 469 } 470 471 /* set the proper interrupt */ 472 radeon_pre_page_flip(rdev, radeon_crtc->crtc_id); 473 474 return 0; 475 476 pflip_cleanup1: 477 if (unlikely(radeon_bo_reserve(rbo, false) != 0)) { 478 DRM_ERROR("failed to reserve new rbo in error path\n"); 479 goto pflip_cleanup; 480 } 481 if (unlikely(radeon_bo_unpin(rbo) != 0)) { 482 DRM_ERROR("failed to unpin new rbo in error path\n"); 483 } 484 radeon_bo_unreserve(rbo); 485 486 pflip_cleanup: 487 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 488 radeon_crtc->unpin_work = NULL; 489 unlock_free: 490 lockmgr(&dev->event_lock, LK_RELEASE); 491 drm_gem_object_unreference_unlocked(old_radeon_fb->obj); 492 radeon_fence_unref(&work->fence); 493 drm_free(work, DRM_MEM_DRIVER); 494 495 return r; 496 } 497 498 static const struct drm_crtc_funcs radeon_crtc_funcs = { 499 .cursor_set = radeon_crtc_cursor_set, 500 .cursor_move = radeon_crtc_cursor_move, 501 .gamma_set = radeon_crtc_gamma_set, 502 .set_config = drm_crtc_helper_set_config, 503 .destroy = radeon_crtc_destroy, 504 .page_flip = radeon_crtc_page_flip, 505 }; 506 507 static void radeon_crtc_init(struct drm_device *dev, int index) 508 { 509 struct radeon_device *rdev = dev->dev_private; 510 struct radeon_crtc *radeon_crtc; 511 int i; 512 513 radeon_crtc = kmalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), 514 DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 515 if (radeon_crtc == NULL) 516 return; 517 518 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); 519 520 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); 521 radeon_crtc->crtc_id = index; 522 rdev->mode_info.crtcs[index] = radeon_crtc; 523 524 #if 0 525 radeon_crtc->mode_set.crtc = &radeon_crtc->base; 526 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); 527 radeon_crtc->mode_set.num_connectors = 0; 528 #endif 529 530 for (i = 0; i < 256; i++) { 531 radeon_crtc->lut_r[i] = i << 2; 532 radeon_crtc->lut_g[i] = i << 2; 533 radeon_crtc->lut_b[i] = i << 2; 534 } 535 536 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) 537 radeon_atombios_init_crtc(dev, radeon_crtc); 538 else 539 radeon_legacy_init_crtc(dev, radeon_crtc); 540 } 541 542 static const char *encoder_names[37] = { 543 "NONE", 544 "INTERNAL_LVDS", 545 "INTERNAL_TMDS1", 546 "INTERNAL_TMDS2", 547 "INTERNAL_DAC1", 548 "INTERNAL_DAC2", 549 "INTERNAL_SDVOA", 550 "INTERNAL_SDVOB", 551 "SI170B", 552 "CH7303", 553 "CH7301", 554 "INTERNAL_DVO1", 555 "EXTERNAL_SDVOA", 556 "EXTERNAL_SDVOB", 557 "TITFP513", 558 "INTERNAL_LVTM1", 559 "VT1623", 560 "HDMI_SI1930", 561 "HDMI_INTERNAL", 562 "INTERNAL_KLDSCP_TMDS1", 563 "INTERNAL_KLDSCP_DVO1", 564 "INTERNAL_KLDSCP_DAC1", 565 "INTERNAL_KLDSCP_DAC2", 566 "SI178", 567 "MVPU_FPGA", 568 "INTERNAL_DDI", 569 "VT1625", 570 "HDMI_SI1932", 571 "DP_AN9801", 572 "DP_DP501", 573 "INTERNAL_UNIPHY", 574 "INTERNAL_KLDSCP_LVTMA", 575 "INTERNAL_UNIPHY1", 576 "INTERNAL_UNIPHY2", 577 "NUTMEG", 578 "TRAVIS", 579 "INTERNAL_VCE" 580 }; 581 582 static const char *hpd_names[6] = { 583 "HPD1", 584 "HPD2", 585 "HPD3", 586 "HPD4", 587 "HPD5", 588 "HPD6", 589 }; 590 591 static void radeon_print_display_setup(struct drm_device *dev) 592 { 593 struct drm_connector *connector; 594 struct radeon_connector *radeon_connector; 595 struct drm_encoder *encoder; 596 struct radeon_encoder *radeon_encoder; 597 uint32_t devices; 598 int i = 0; 599 600 DRM_INFO("Radeon Display Connectors\n"); 601 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 602 radeon_connector = to_radeon_connector(connector); 603 DRM_INFO("Connector %d:\n", i); 604 DRM_INFO(" %s\n", drm_get_connector_name(connector)); 605 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 606 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); 607 if (radeon_connector->ddc_bus) { 608 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 609 radeon_connector->ddc_bus->rec.mask_clk_reg, 610 radeon_connector->ddc_bus->rec.mask_data_reg, 611 radeon_connector->ddc_bus->rec.a_clk_reg, 612 radeon_connector->ddc_bus->rec.a_data_reg, 613 radeon_connector->ddc_bus->rec.en_clk_reg, 614 radeon_connector->ddc_bus->rec.en_data_reg, 615 radeon_connector->ddc_bus->rec.y_clk_reg, 616 radeon_connector->ddc_bus->rec.y_data_reg); 617 if (radeon_connector->router.ddc_valid) 618 DRM_INFO(" DDC Router 0x%x/0x%x\n", 619 radeon_connector->router.ddc_mux_control_pin, 620 radeon_connector->router.ddc_mux_state); 621 if (radeon_connector->router.cd_valid) 622 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 623 radeon_connector->router.cd_mux_control_pin, 624 radeon_connector->router.cd_mux_state); 625 } else { 626 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 627 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 628 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 629 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 630 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 631 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 632 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 633 } 634 DRM_INFO(" Encoders:\n"); 635 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 636 radeon_encoder = to_radeon_encoder(encoder); 637 devices = radeon_encoder->devices & radeon_connector->devices; 638 if (devices) { 639 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 640 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); 641 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 642 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); 643 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 644 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); 645 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 646 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); 647 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 648 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); 649 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 650 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); 651 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 652 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); 653 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 654 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); 655 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 656 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); 657 if (devices & ATOM_DEVICE_TV1_SUPPORT) 658 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); 659 if (devices & ATOM_DEVICE_CV_SUPPORT) 660 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); 661 } 662 } 663 i++; 664 } 665 } 666 667 static bool radeon_setup_enc_conn(struct drm_device *dev) 668 { 669 struct radeon_device *rdev = dev->dev_private; 670 bool ret = false; 671 672 if (rdev->bios) { 673 if (rdev->is_atom_bios) { 674 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); 675 if (ret == false) 676 ret = radeon_get_atom_connector_info_from_object_table(dev); 677 } else { 678 ret = radeon_get_legacy_connector_info_from_bios(dev); 679 if (ret == false) 680 ret = radeon_get_legacy_connector_info_from_table(dev); 681 } 682 } else { 683 if (!ASIC_IS_AVIVO(rdev)) 684 ret = radeon_get_legacy_connector_info_from_table(dev); 685 } 686 if (ret) { 687 radeon_setup_encoder_clones(dev); 688 radeon_print_display_setup(dev); 689 } 690 691 return ret; 692 } 693 694 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) 695 { 696 struct drm_device *dev = radeon_connector->base.dev; 697 struct radeon_device *rdev = dev->dev_private; 698 int ret = 0; 699 700 /* on hw with routers, select right port */ 701 if (radeon_connector->router.ddc_valid) 702 radeon_router_select_ddc_port(radeon_connector); 703 704 if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) != 705 ENCODER_OBJECT_ID_NONE) { 706 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 707 708 if (dig->dp_i2c_bus) 709 radeon_connector->edid = drm_get_edid(&radeon_connector->base, 710 dig->dp_i2c_bus->adapter); 711 } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 712 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) { 713 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 714 715 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 716 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus) 717 radeon_connector->edid = drm_get_edid(&radeon_connector->base, 718 dig->dp_i2c_bus->adapter); 719 else if (radeon_connector->ddc_bus && !radeon_connector->edid) 720 radeon_connector->edid = drm_get_edid(&radeon_connector->base, 721 radeon_connector->ddc_bus->adapter); 722 } else { 723 if (radeon_connector->ddc_bus && !radeon_connector->edid) 724 radeon_connector->edid = drm_get_edid(&radeon_connector->base, 725 radeon_connector->ddc_bus->adapter); 726 } 727 728 if (!radeon_connector->edid) { 729 if (rdev->is_atom_bios) { 730 /* some laptops provide a hardcoded edid in rom for LCDs */ 731 if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) || 732 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP))) 733 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); 734 } else 735 /* some servers provide a hardcoded edid in rom for KVMs */ 736 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); 737 } 738 if (radeon_connector->edid) { 739 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); 740 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); 741 return ret; 742 } 743 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); 744 return 0; 745 } 746 747 /* avivo */ 748 static void avivo_get_fb_div(struct radeon_pll *pll, 749 u32 target_clock, 750 u32 post_div, 751 u32 ref_div, 752 u32 *fb_div, 753 u32 *frac_fb_div) 754 { 755 u32 tmp = post_div * ref_div; 756 757 tmp *= target_clock; 758 *fb_div = tmp / pll->reference_freq; 759 *frac_fb_div = tmp % pll->reference_freq; 760 761 if (*fb_div > pll->max_feedback_div) 762 *fb_div = pll->max_feedback_div; 763 else if (*fb_div < pll->min_feedback_div) 764 *fb_div = pll->min_feedback_div; 765 } 766 767 static u32 avivo_get_post_div(struct radeon_pll *pll, 768 u32 target_clock) 769 { 770 u32 vco, post_div, tmp; 771 772 if (pll->flags & RADEON_PLL_USE_POST_DIV) 773 return pll->post_div; 774 775 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) { 776 if (pll->flags & RADEON_PLL_IS_LCD) 777 vco = pll->lcd_pll_out_min; 778 else 779 vco = pll->pll_out_min; 780 } else { 781 if (pll->flags & RADEON_PLL_IS_LCD) 782 vco = pll->lcd_pll_out_max; 783 else 784 vco = pll->pll_out_max; 785 } 786 787 post_div = vco / target_clock; 788 tmp = vco % target_clock; 789 790 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) { 791 if (tmp) 792 post_div++; 793 } else { 794 if (!tmp) 795 post_div--; 796 } 797 798 if (post_div > pll->max_post_div) 799 post_div = pll->max_post_div; 800 else if (post_div < pll->min_post_div) 801 post_div = pll->min_post_div; 802 803 return post_div; 804 } 805 806 #define MAX_TOLERANCE 10 807 808 void radeon_compute_pll_avivo(struct radeon_pll *pll, 809 u32 freq, 810 u32 *dot_clock_p, 811 u32 *fb_div_p, 812 u32 *frac_fb_div_p, 813 u32 *ref_div_p, 814 u32 *post_div_p) 815 { 816 u32 target_clock = freq / 10; 817 u32 post_div = avivo_get_post_div(pll, target_clock); 818 u32 ref_div = pll->min_ref_div; 819 u32 fb_div = 0, frac_fb_div = 0, tmp; 820 821 if (pll->flags & RADEON_PLL_USE_REF_DIV) 822 ref_div = pll->reference_div; 823 824 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 825 avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div); 826 frac_fb_div = (100 * frac_fb_div) / pll->reference_freq; 827 if (frac_fb_div >= 5) { 828 frac_fb_div -= 5; 829 frac_fb_div = frac_fb_div / 10; 830 frac_fb_div++; 831 } 832 if (frac_fb_div >= 10) { 833 fb_div++; 834 frac_fb_div = 0; 835 } 836 } else { 837 while (ref_div <= pll->max_ref_div) { 838 avivo_get_fb_div(pll, target_clock, post_div, ref_div, 839 &fb_div, &frac_fb_div); 840 if (frac_fb_div >= (pll->reference_freq / 2)) 841 fb_div++; 842 frac_fb_div = 0; 843 tmp = (pll->reference_freq * fb_div) / (post_div * ref_div); 844 tmp = (tmp * 10000) / target_clock; 845 846 if (tmp > (10000 + MAX_TOLERANCE)) 847 ref_div++; 848 else if (tmp >= (10000 - MAX_TOLERANCE)) 849 break; 850 else 851 ref_div++; 852 } 853 } 854 855 *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) / 856 (ref_div * post_div * 10); 857 *fb_div_p = fb_div; 858 *frac_fb_div_p = frac_fb_div; 859 *ref_div_p = ref_div; 860 *post_div_p = post_div; 861 DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n", 862 *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div); 863 } 864 865 /* pre-avivo */ 866 static inline uint32_t radeon_div(uint64_t n, uint32_t d) 867 { 868 uint64_t mod; 869 870 n += d / 2; 871 872 mod = do_div(n, d); 873 return n; 874 } 875 876 void radeon_compute_pll_legacy(struct radeon_pll *pll, 877 uint64_t freq, 878 uint32_t *dot_clock_p, 879 uint32_t *fb_div_p, 880 uint32_t *frac_fb_div_p, 881 uint32_t *ref_div_p, 882 uint32_t *post_div_p) 883 { 884 uint32_t min_ref_div = pll->min_ref_div; 885 uint32_t max_ref_div = pll->max_ref_div; 886 uint32_t min_post_div = pll->min_post_div; 887 uint32_t max_post_div = pll->max_post_div; 888 uint32_t min_fractional_feed_div = 0; 889 uint32_t max_fractional_feed_div = 0; 890 uint32_t best_vco = pll->best_vco; 891 uint32_t best_post_div = 1; 892 uint32_t best_ref_div = 1; 893 uint32_t best_feedback_div = 1; 894 uint32_t best_frac_feedback_div = 0; 895 uint32_t best_freq = -1; 896 uint32_t best_error = 0xffffffff; 897 uint32_t best_vco_diff = 1; 898 uint32_t post_div; 899 u32 pll_out_min, pll_out_max; 900 901 DRM_DEBUG_KMS("PLL freq %ju %u %u\n", (uintmax_t)freq, pll->min_ref_div, pll->max_ref_div); 902 freq = freq * 1000; 903 904 if (pll->flags & RADEON_PLL_IS_LCD) { 905 pll_out_min = pll->lcd_pll_out_min; 906 pll_out_max = pll->lcd_pll_out_max; 907 } else { 908 pll_out_min = pll->pll_out_min; 909 pll_out_max = pll->pll_out_max; 910 } 911 912 if (pll_out_min > 64800) 913 pll_out_min = 64800; 914 915 if (pll->flags & RADEON_PLL_USE_REF_DIV) 916 min_ref_div = max_ref_div = pll->reference_div; 917 else { 918 while (min_ref_div < max_ref_div-1) { 919 uint32_t mid = (min_ref_div + max_ref_div) / 2; 920 uint32_t pll_in = pll->reference_freq / mid; 921 if (pll_in < pll->pll_in_min) 922 max_ref_div = mid; 923 else if (pll_in > pll->pll_in_max) 924 min_ref_div = mid; 925 else 926 break; 927 } 928 } 929 930 if (pll->flags & RADEON_PLL_USE_POST_DIV) 931 min_post_div = max_post_div = pll->post_div; 932 933 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 934 min_fractional_feed_div = pll->min_frac_feedback_div; 935 max_fractional_feed_div = pll->max_frac_feedback_div; 936 } 937 938 for (post_div = max_post_div; post_div >= min_post_div; --post_div) { 939 uint32_t ref_div; 940 941 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 942 continue; 943 944 /* legacy radeons only have a few post_divs */ 945 if (pll->flags & RADEON_PLL_LEGACY) { 946 if ((post_div == 5) || 947 (post_div == 7) || 948 (post_div == 9) || 949 (post_div == 10) || 950 (post_div == 11) || 951 (post_div == 13) || 952 (post_div == 14) || 953 (post_div == 15)) 954 continue; 955 } 956 957 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { 958 uint32_t feedback_div, current_freq = 0, error, vco_diff; 959 uint32_t pll_in = pll->reference_freq / ref_div; 960 uint32_t min_feed_div = pll->min_feedback_div; 961 uint32_t max_feed_div = pll->max_feedback_div + 1; 962 963 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) 964 continue; 965 966 while (min_feed_div < max_feed_div) { 967 uint32_t vco; 968 uint32_t min_frac_feed_div = min_fractional_feed_div; 969 uint32_t max_frac_feed_div = max_fractional_feed_div + 1; 970 uint32_t frac_feedback_div; 971 uint64_t tmp; 972 973 feedback_div = (min_feed_div + max_feed_div) / 2; 974 975 tmp = (uint64_t)pll->reference_freq * feedback_div; 976 vco = radeon_div(tmp, ref_div); 977 978 if (vco < pll_out_min) { 979 min_feed_div = feedback_div + 1; 980 continue; 981 } else if (vco > pll_out_max) { 982 max_feed_div = feedback_div; 983 continue; 984 } 985 986 while (min_frac_feed_div < max_frac_feed_div) { 987 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; 988 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; 989 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; 990 current_freq = radeon_div(tmp, ref_div * post_div); 991 992 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 993 if (freq < current_freq) 994 error = 0xffffffff; 995 else 996 error = freq - current_freq; 997 } else 998 error = abs(current_freq - freq); 999 vco_diff = abs(vco - best_vco); 1000 1001 if ((best_vco == 0 && error < best_error) || 1002 (best_vco != 0 && 1003 ((best_error > 100 && error < best_error - 100) || 1004 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { 1005 best_post_div = post_div; 1006 best_ref_div = ref_div; 1007 best_feedback_div = feedback_div; 1008 best_frac_feedback_div = frac_feedback_div; 1009 best_freq = current_freq; 1010 best_error = error; 1011 best_vco_diff = vco_diff; 1012 } else if (current_freq == freq) { 1013 if (best_freq == -1) { 1014 best_post_div = post_div; 1015 best_ref_div = ref_div; 1016 best_feedback_div = feedback_div; 1017 best_frac_feedback_div = frac_feedback_div; 1018 best_freq = current_freq; 1019 best_error = error; 1020 best_vco_diff = vco_diff; 1021 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 1022 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 1023 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 1024 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 1025 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 1026 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 1027 best_post_div = post_div; 1028 best_ref_div = ref_div; 1029 best_feedback_div = feedback_div; 1030 best_frac_feedback_div = frac_feedback_div; 1031 best_freq = current_freq; 1032 best_error = error; 1033 best_vco_diff = vco_diff; 1034 } 1035 } 1036 if (current_freq < freq) 1037 min_frac_feed_div = frac_feedback_div + 1; 1038 else 1039 max_frac_feed_div = frac_feedback_div; 1040 } 1041 if (current_freq < freq) 1042 min_feed_div = feedback_div + 1; 1043 else 1044 max_feed_div = feedback_div; 1045 } 1046 } 1047 } 1048 1049 *dot_clock_p = best_freq / 10000; 1050 *fb_div_p = best_feedback_div; 1051 *frac_fb_div_p = best_frac_feedback_div; 1052 *ref_div_p = best_ref_div; 1053 *post_div_p = best_post_div; 1054 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1055 (long long)freq, 1056 best_freq / 1000, best_feedback_div, best_frac_feedback_div, 1057 best_ref_div, best_post_div); 1058 1059 } 1060 1061 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) 1062 { 1063 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1064 1065 if (radeon_fb->obj) { 1066 drm_gem_object_unreference_unlocked(radeon_fb->obj); 1067 } 1068 drm_framebuffer_cleanup(fb); 1069 drm_free(radeon_fb, DRM_MEM_DRIVER); 1070 } 1071 1072 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, 1073 struct drm_file *file_priv, 1074 unsigned int *handle) 1075 { 1076 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1077 1078 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); 1079 } 1080 1081 static const struct drm_framebuffer_funcs radeon_fb_funcs = { 1082 .destroy = radeon_user_framebuffer_destroy, 1083 .create_handle = radeon_user_framebuffer_create_handle, 1084 }; 1085 1086 int 1087 radeon_framebuffer_init(struct drm_device *dev, 1088 struct radeon_framebuffer *rfb, 1089 struct drm_mode_fb_cmd2 *mode_cmd, 1090 struct drm_gem_object *obj) 1091 { 1092 int ret; 1093 rfb->obj = obj; 1094 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); 1095 if (ret) { 1096 rfb->obj = NULL; 1097 return ret; 1098 } 1099 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); 1100 return 0; 1101 } 1102 1103 static int 1104 radeon_user_framebuffer_create(struct drm_device *dev, 1105 struct drm_file *file_priv, 1106 struct drm_mode_fb_cmd2 *mode_cmd, 1107 struct drm_framebuffer **res) 1108 { 1109 struct drm_gem_object *obj; 1110 struct radeon_framebuffer *radeon_fb; 1111 int ret; 1112 1113 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]); 1114 if (obj == NULL) { 1115 dev_err(dev->device, "No GEM object associated to handle 0x%08X, " 1116 "can't create framebuffer\n", mode_cmd->handles[0]); 1117 return -ENOENT; 1118 } 1119 1120 radeon_fb = kmalloc(sizeof(*radeon_fb), DRM_MEM_DRIVER, 1121 M_WAITOK | M_ZERO); 1122 if (radeon_fb == NULL) { 1123 drm_gem_object_unreference_unlocked(obj); 1124 return (-ENOMEM); 1125 } 1126 1127 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj); 1128 if (ret) { 1129 drm_free(radeon_fb, DRM_MEM_DRIVER); 1130 drm_gem_object_unreference_unlocked(obj); 1131 return ret; 1132 } 1133 1134 *res = &radeon_fb->base; 1135 return 0; 1136 } 1137 1138 static void radeon_output_poll_changed(struct drm_device *dev) 1139 { 1140 struct radeon_device *rdev = dev->dev_private; 1141 radeon_fb_output_poll_changed(rdev); 1142 } 1143 1144 static const struct drm_mode_config_funcs radeon_mode_funcs = { 1145 .fb_create = radeon_user_framebuffer_create, 1146 .output_poll_changed = radeon_output_poll_changed 1147 }; 1148 1149 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = 1150 { { 0, "driver" }, 1151 { 1, "bios" }, 1152 }; 1153 1154 static struct drm_prop_enum_list radeon_tv_std_enum_list[] = 1155 { { TV_STD_NTSC, "ntsc" }, 1156 { TV_STD_PAL, "pal" }, 1157 { TV_STD_PAL_M, "pal-m" }, 1158 { TV_STD_PAL_60, "pal-60" }, 1159 { TV_STD_NTSC_J, "ntsc-j" }, 1160 { TV_STD_SCART_PAL, "scart-pal" }, 1161 { TV_STD_PAL_CN, "pal-cn" }, 1162 { TV_STD_SECAM, "secam" }, 1163 }; 1164 1165 static struct drm_prop_enum_list radeon_underscan_enum_list[] = 1166 { { UNDERSCAN_OFF, "off" }, 1167 { UNDERSCAN_ON, "on" }, 1168 { UNDERSCAN_AUTO, "auto" }, 1169 }; 1170 1171 static int radeon_modeset_create_props(struct radeon_device *rdev) 1172 { 1173 int sz; 1174 1175 if (rdev->is_atom_bios) { 1176 rdev->mode_info.coherent_mode_property = 1177 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1); 1178 if (!rdev->mode_info.coherent_mode_property) 1179 return -ENOMEM; 1180 } 1181 1182 if (!ASIC_IS_AVIVO(rdev)) { 1183 sz = DRM_ARRAY_SIZE(radeon_tmds_pll_enum_list); 1184 rdev->mode_info.tmds_pll_property = 1185 drm_property_create_enum(rdev->ddev, 0, 1186 "tmds_pll", 1187 radeon_tmds_pll_enum_list, sz); 1188 } 1189 1190 rdev->mode_info.load_detect_property = 1191 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1); 1192 if (!rdev->mode_info.load_detect_property) 1193 return -ENOMEM; 1194 1195 drm_mode_create_scaling_mode_property(rdev->ddev); 1196 1197 sz = DRM_ARRAY_SIZE(radeon_tv_std_enum_list); 1198 rdev->mode_info.tv_std_property = 1199 drm_property_create_enum(rdev->ddev, 0, 1200 "tv standard", 1201 radeon_tv_std_enum_list, sz); 1202 1203 sz = DRM_ARRAY_SIZE(radeon_underscan_enum_list); 1204 rdev->mode_info.underscan_property = 1205 drm_property_create_enum(rdev->ddev, 0, 1206 "underscan", 1207 radeon_underscan_enum_list, sz); 1208 1209 rdev->mode_info.underscan_hborder_property = 1210 drm_property_create_range(rdev->ddev, 0, 1211 "underscan hborder", 0, 128); 1212 if (!rdev->mode_info.underscan_hborder_property) 1213 return -ENOMEM; 1214 1215 rdev->mode_info.underscan_vborder_property = 1216 drm_property_create_range(rdev->ddev, 0, 1217 "underscan vborder", 0, 128); 1218 if (!rdev->mode_info.underscan_vborder_property) 1219 return -ENOMEM; 1220 1221 return 0; 1222 } 1223 1224 void radeon_update_display_priority(struct radeon_device *rdev) 1225 { 1226 /* adjustment options for the display watermarks */ 1227 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { 1228 /* set display priority to high for r3xx, rv515 chips 1229 * this avoids flickering due to underflow to the 1230 * display controllers during heavy acceleration. 1231 * Don't force high on rs4xx igp chips as it seems to 1232 * affect the sound card. See kernel bug 15982. 1233 */ 1234 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && 1235 !(rdev->flags & RADEON_IS_IGP)) 1236 rdev->disp_priority = 2; 1237 else 1238 rdev->disp_priority = 0; 1239 } else 1240 rdev->disp_priority = radeon_disp_priority; 1241 1242 } 1243 1244 /* 1245 * Allocate hdmi structs and determine register offsets 1246 */ 1247 static void radeon_afmt_init(struct radeon_device *rdev) 1248 { 1249 int i; 1250 1251 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) 1252 rdev->mode_info.afmt[i] = NULL; 1253 1254 if (ASIC_IS_DCE6(rdev)) { 1255 /* todo */ 1256 } else if (ASIC_IS_DCE4(rdev)) { 1257 /* DCE4/5 has 6 audio blocks tied to DIG encoders */ 1258 /* DCE4.1 has 2 audio blocks tied to DIG encoders */ 1259 rdev->mode_info.afmt[0] = kmalloc(sizeof(struct radeon_afmt), 1260 DRM_MEM_DRIVER, 1261 M_WAITOK | M_ZERO); 1262 if (rdev->mode_info.afmt[0]) { 1263 rdev->mode_info.afmt[0]->offset = EVERGREEN_CRTC0_REGISTER_OFFSET; 1264 rdev->mode_info.afmt[0]->id = 0; 1265 } 1266 rdev->mode_info.afmt[1] = kmalloc(sizeof(struct radeon_afmt), 1267 DRM_MEM_DRIVER, 1268 M_WAITOK | M_ZERO); 1269 if (rdev->mode_info.afmt[1]) { 1270 rdev->mode_info.afmt[1]->offset = EVERGREEN_CRTC1_REGISTER_OFFSET; 1271 rdev->mode_info.afmt[1]->id = 1; 1272 } 1273 if (!ASIC_IS_DCE41(rdev)) { 1274 rdev->mode_info.afmt[2] = kmalloc(sizeof(struct radeon_afmt), 1275 DRM_MEM_DRIVER, 1276 M_WAITOK | M_ZERO); 1277 if (rdev->mode_info.afmt[2]) { 1278 rdev->mode_info.afmt[2]->offset = EVERGREEN_CRTC2_REGISTER_OFFSET; 1279 rdev->mode_info.afmt[2]->id = 2; 1280 } 1281 rdev->mode_info.afmt[3] = kmalloc(sizeof(struct radeon_afmt), 1282 DRM_MEM_DRIVER, 1283 M_WAITOK | M_ZERO); 1284 if (rdev->mode_info.afmt[3]) { 1285 rdev->mode_info.afmt[3]->offset = EVERGREEN_CRTC3_REGISTER_OFFSET; 1286 rdev->mode_info.afmt[3]->id = 3; 1287 } 1288 rdev->mode_info.afmt[4] = kmalloc(sizeof(struct radeon_afmt), 1289 DRM_MEM_DRIVER, 1290 M_WAITOK | M_ZERO); 1291 if (rdev->mode_info.afmt[4]) { 1292 rdev->mode_info.afmt[4]->offset = EVERGREEN_CRTC4_REGISTER_OFFSET; 1293 rdev->mode_info.afmt[4]->id = 4; 1294 } 1295 rdev->mode_info.afmt[5] = kmalloc(sizeof(struct radeon_afmt), 1296 DRM_MEM_DRIVER, 1297 M_WAITOK | M_ZERO); 1298 if (rdev->mode_info.afmt[5]) { 1299 rdev->mode_info.afmt[5]->offset = EVERGREEN_CRTC5_REGISTER_OFFSET; 1300 rdev->mode_info.afmt[5]->id = 5; 1301 } 1302 } 1303 } else if (ASIC_IS_DCE3(rdev)) { 1304 /* DCE3.x has 2 audio blocks tied to DIG encoders */ 1305 rdev->mode_info.afmt[0] = kmalloc(sizeof(struct radeon_afmt), 1306 DRM_MEM_DRIVER, 1307 M_WAITOK | M_ZERO); 1308 if (rdev->mode_info.afmt[0]) { 1309 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0; 1310 rdev->mode_info.afmt[0]->id = 0; 1311 } 1312 rdev->mode_info.afmt[1] = kmalloc(sizeof(struct radeon_afmt), 1313 DRM_MEM_DRIVER, 1314 M_WAITOK | M_ZERO); 1315 if (rdev->mode_info.afmt[1]) { 1316 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1; 1317 rdev->mode_info.afmt[1]->id = 1; 1318 } 1319 } else if (ASIC_IS_DCE2(rdev)) { 1320 /* DCE2 has at least 1 routable audio block */ 1321 rdev->mode_info.afmt[0] = kmalloc(sizeof(struct radeon_afmt), 1322 DRM_MEM_DRIVER, 1323 M_WAITOK | M_ZERO); 1324 if (rdev->mode_info.afmt[0]) { 1325 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0; 1326 rdev->mode_info.afmt[0]->id = 0; 1327 } 1328 /* r6xx has 2 routable audio blocks */ 1329 if (rdev->family >= CHIP_R600) { 1330 rdev->mode_info.afmt[1] = kmalloc(sizeof(struct radeon_afmt), 1331 DRM_MEM_DRIVER, 1332 M_WAITOK | M_ZERO); 1333 if (rdev->mode_info.afmt[1]) { 1334 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1; 1335 rdev->mode_info.afmt[1]->id = 1; 1336 } 1337 } 1338 } 1339 } 1340 1341 static void radeon_afmt_fini(struct radeon_device *rdev) 1342 { 1343 int i; 1344 1345 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) { 1346 drm_free(rdev->mode_info.afmt[i], DRM_MEM_DRIVER); 1347 rdev->mode_info.afmt[i] = NULL; 1348 } 1349 } 1350 1351 int radeon_modeset_init(struct radeon_device *rdev) 1352 { 1353 int i; 1354 int ret; 1355 1356 drm_mode_config_init(rdev->ddev); 1357 rdev->mode_info.mode_config_initialized = true; 1358 1359 rdev->ddev->mode_config.funcs = &radeon_mode_funcs; 1360 1361 if (ASIC_IS_DCE5(rdev)) { 1362 rdev->ddev->mode_config.max_width = 16384; 1363 rdev->ddev->mode_config.max_height = 16384; 1364 } else if (ASIC_IS_AVIVO(rdev)) { 1365 rdev->ddev->mode_config.max_width = 8192; 1366 rdev->ddev->mode_config.max_height = 8192; 1367 } else { 1368 rdev->ddev->mode_config.max_width = 4096; 1369 rdev->ddev->mode_config.max_height = 4096; 1370 } 1371 1372 rdev->ddev->mode_config.preferred_depth = 24; 1373 rdev->ddev->mode_config.prefer_shadow = 1; 1374 1375 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; 1376 1377 ret = radeon_modeset_create_props(rdev); 1378 if (ret) { 1379 return ret; 1380 } 1381 1382 /* init i2c buses */ 1383 radeon_i2c_init(rdev); 1384 1385 /* check combios for a valid hardcoded EDID - Sun servers */ 1386 if (!rdev->is_atom_bios) { 1387 /* check for hardcoded EDID in BIOS */ 1388 radeon_combios_check_hardcoded_edid(rdev); 1389 } 1390 1391 /* allocate crtcs */ 1392 for (i = 0; i < rdev->num_crtc; i++) { 1393 radeon_crtc_init(rdev->ddev, i); 1394 } 1395 1396 /* okay we should have all the bios connectors */ 1397 ret = radeon_setup_enc_conn(rdev->ddev); 1398 if (!ret) { 1399 return ret; 1400 } 1401 1402 /* init dig PHYs, disp eng pll */ 1403 if (rdev->is_atom_bios) { 1404 radeon_atom_encoder_init(rdev); 1405 radeon_atom_disp_eng_pll_init(rdev); 1406 } 1407 1408 /* initialize hpd */ 1409 radeon_hpd_init(rdev); 1410 1411 /* setup afmt */ 1412 radeon_afmt_init(rdev); 1413 1414 /* Initialize power management */ 1415 radeon_pm_init(rdev); 1416 1417 radeon_fbdev_init(rdev); 1418 drm_kms_helper_poll_init(rdev->ddev); 1419 1420 return 0; 1421 } 1422 1423 void radeon_modeset_fini(struct radeon_device *rdev) 1424 { 1425 radeon_fbdev_fini(rdev); 1426 drm_free(rdev->mode_info.bios_hardcoded_edid, DRM_MEM_KMS); 1427 radeon_pm_fini(rdev); 1428 1429 if (rdev->mode_info.mode_config_initialized) { 1430 radeon_afmt_fini(rdev); 1431 drm_kms_helper_poll_fini(rdev->ddev); 1432 radeon_hpd_fini(rdev); 1433 DRM_UNLOCK(rdev->ddev); /* Work around lock recursion. dumbbell@ */ 1434 drm_mode_config_cleanup(rdev->ddev); 1435 DRM_LOCK(rdev->ddev); 1436 rdev->mode_info.mode_config_initialized = false; 1437 } 1438 /* free i2c buses */ 1439 radeon_i2c_fini(rdev); 1440 } 1441 1442 static bool is_hdtv_mode(const struct drm_display_mode *mode) 1443 { 1444 /* try and guess if this is a tv or a monitor */ 1445 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 1446 (mode->vdisplay == 576) || /* 576p */ 1447 (mode->vdisplay == 720) || /* 720p */ 1448 (mode->vdisplay == 1080)) /* 1080p */ 1449 return true; 1450 else 1451 return false; 1452 } 1453 1454 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 1455 const struct drm_display_mode *mode, 1456 struct drm_display_mode *adjusted_mode) 1457 { 1458 struct drm_device *dev = crtc->dev; 1459 struct radeon_device *rdev = dev->dev_private; 1460 struct drm_encoder *encoder; 1461 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1462 struct radeon_encoder *radeon_encoder; 1463 struct drm_connector *connector; 1464 struct radeon_connector *radeon_connector; 1465 bool first = true; 1466 u32 src_v = 1, dst_v = 1; 1467 u32 src_h = 1, dst_h = 1; 1468 1469 radeon_crtc->h_border = 0; 1470 radeon_crtc->v_border = 0; 1471 1472 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1473 if (encoder->crtc != crtc) 1474 continue; 1475 radeon_encoder = to_radeon_encoder(encoder); 1476 connector = radeon_get_connector_for_encoder(encoder); 1477 radeon_connector = to_radeon_connector(connector); 1478 1479 if (first) { 1480 /* set scaling */ 1481 if (radeon_encoder->rmx_type == RMX_OFF) 1482 radeon_crtc->rmx_type = RMX_OFF; 1483 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || 1484 mode->vdisplay < radeon_encoder->native_mode.vdisplay) 1485 radeon_crtc->rmx_type = radeon_encoder->rmx_type; 1486 else 1487 radeon_crtc->rmx_type = RMX_OFF; 1488 /* copy native mode */ 1489 memcpy(&radeon_crtc->native_mode, 1490 &radeon_encoder->native_mode, 1491 sizeof(struct drm_display_mode)); 1492 src_v = crtc->mode.vdisplay; 1493 dst_v = radeon_crtc->native_mode.vdisplay; 1494 src_h = crtc->mode.hdisplay; 1495 dst_h = radeon_crtc->native_mode.hdisplay; 1496 1497 /* fix up for overscan on hdmi */ 1498 if (ASIC_IS_AVIVO(rdev) && 1499 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 1500 ((radeon_encoder->underscan_type == UNDERSCAN_ON) || 1501 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && 1502 drm_detect_hdmi_monitor(radeon_connector->edid) && 1503 is_hdtv_mode(mode)))) { 1504 if (radeon_encoder->underscan_hborder != 0) 1505 radeon_crtc->h_border = radeon_encoder->underscan_hborder; 1506 else 1507 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; 1508 if (radeon_encoder->underscan_vborder != 0) 1509 radeon_crtc->v_border = radeon_encoder->underscan_vborder; 1510 else 1511 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; 1512 radeon_crtc->rmx_type = RMX_FULL; 1513 src_v = crtc->mode.vdisplay; 1514 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); 1515 src_h = crtc->mode.hdisplay; 1516 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); 1517 } 1518 first = false; 1519 } else { 1520 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { 1521 /* WARNING: Right now this can't happen but 1522 * in the future we need to check that scaling 1523 * are consistent across different encoder 1524 * (ie all encoder can work with the same 1525 * scaling). 1526 */ 1527 DRM_ERROR("Scaling not consistent across encoder.\n"); 1528 return false; 1529 } 1530 } 1531 } 1532 if (radeon_crtc->rmx_type != RMX_OFF) { 1533 fixed20_12 a, b; 1534 a.full = dfixed_const(src_v); 1535 b.full = dfixed_const(dst_v); 1536 radeon_crtc->vsc.full = dfixed_div(a, b); 1537 a.full = dfixed_const(src_h); 1538 b.full = dfixed_const(dst_h); 1539 radeon_crtc->hsc.full = dfixed_div(a, b); 1540 } else { 1541 radeon_crtc->vsc.full = dfixed_const(1); 1542 radeon_crtc->hsc.full = dfixed_const(1); 1543 } 1544 return true; 1545 } 1546 1547 /* 1548 * Retrieve current video scanout position of crtc on a given gpu. 1549 * 1550 * \param dev Device to query. 1551 * \param crtc Crtc to query. 1552 * \param *vpos Location where vertical scanout position should be stored. 1553 * \param *hpos Location where horizontal scanout position should go. 1554 * 1555 * Returns vpos as a positive number while in active scanout area. 1556 * Returns vpos as a negative number inside vblank, counting the number 1557 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 1558 * until start of active scanout / end of vblank." 1559 * 1560 * \return Flags, or'ed together as follows: 1561 * 1562 * DRM_SCANOUTPOS_VALID = Query successful. 1563 * DRM_SCANOUTPOS_INVBL = Inside vblank. 1564 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 1565 * this flag means that returned position may be offset by a constant but 1566 * unknown small number of scanlines wrt. real scanout position. 1567 * 1568 */ 1569 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos) 1570 { 1571 u32 stat_crtc = 0, vbl = 0, position = 0; 1572 int vbl_start, vbl_end, vtotal, ret = 0; 1573 bool in_vbl = true; 1574 1575 struct radeon_device *rdev = dev->dev_private; 1576 1577 if (ASIC_IS_DCE4(rdev)) { 1578 if (crtc == 0) { 1579 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1580 EVERGREEN_CRTC0_REGISTER_OFFSET); 1581 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1582 EVERGREEN_CRTC0_REGISTER_OFFSET); 1583 ret |= DRM_SCANOUTPOS_VALID; 1584 } 1585 if (crtc == 1) { 1586 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1587 EVERGREEN_CRTC1_REGISTER_OFFSET); 1588 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1589 EVERGREEN_CRTC1_REGISTER_OFFSET); 1590 ret |= DRM_SCANOUTPOS_VALID; 1591 } 1592 if (crtc == 2) { 1593 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1594 EVERGREEN_CRTC2_REGISTER_OFFSET); 1595 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1596 EVERGREEN_CRTC2_REGISTER_OFFSET); 1597 ret |= DRM_SCANOUTPOS_VALID; 1598 } 1599 if (crtc == 3) { 1600 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1601 EVERGREEN_CRTC3_REGISTER_OFFSET); 1602 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1603 EVERGREEN_CRTC3_REGISTER_OFFSET); 1604 ret |= DRM_SCANOUTPOS_VALID; 1605 } 1606 if (crtc == 4) { 1607 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1608 EVERGREEN_CRTC4_REGISTER_OFFSET); 1609 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1610 EVERGREEN_CRTC4_REGISTER_OFFSET); 1611 ret |= DRM_SCANOUTPOS_VALID; 1612 } 1613 if (crtc == 5) { 1614 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1615 EVERGREEN_CRTC5_REGISTER_OFFSET); 1616 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1617 EVERGREEN_CRTC5_REGISTER_OFFSET); 1618 ret |= DRM_SCANOUTPOS_VALID; 1619 } 1620 } else if (ASIC_IS_AVIVO(rdev)) { 1621 if (crtc == 0) { 1622 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); 1623 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); 1624 ret |= DRM_SCANOUTPOS_VALID; 1625 } 1626 if (crtc == 1) { 1627 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); 1628 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); 1629 ret |= DRM_SCANOUTPOS_VALID; 1630 } 1631 } else { 1632 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ 1633 if (crtc == 0) { 1634 /* Assume vbl_end == 0, get vbl_start from 1635 * upper 16 bits. 1636 */ 1637 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & 1638 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1639 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ 1640 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1641 stat_crtc = RREG32(RADEON_CRTC_STATUS); 1642 if (!(stat_crtc & 1)) 1643 in_vbl = false; 1644 1645 ret |= DRM_SCANOUTPOS_VALID; 1646 } 1647 if (crtc == 1) { 1648 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & 1649 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1650 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1651 stat_crtc = RREG32(RADEON_CRTC2_STATUS); 1652 if (!(stat_crtc & 1)) 1653 in_vbl = false; 1654 1655 ret |= DRM_SCANOUTPOS_VALID; 1656 } 1657 } 1658 1659 /* Decode into vertical and horizontal scanout position. */ 1660 *vpos = position & 0x1fff; 1661 *hpos = (position >> 16) & 0x1fff; 1662 1663 /* Valid vblank area boundaries from gpu retrieved? */ 1664 if (vbl > 0) { 1665 /* Yes: Decode. */ 1666 ret |= DRM_SCANOUTPOS_ACCURATE; 1667 vbl_start = vbl & 0x1fff; 1668 vbl_end = (vbl >> 16) & 0x1fff; 1669 } 1670 else { 1671 /* No: Fake something reasonable which gives at least ok results. */ 1672 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay; 1673 vbl_end = 0; 1674 } 1675 1676 /* Test scanout position against vblank region. */ 1677 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 1678 in_vbl = false; 1679 1680 /* Check if inside vblank area and apply corrective offsets: 1681 * vpos will then be >=0 in video scanout area, but negative 1682 * within vblank area, counting down the number of lines until 1683 * start of scanout. 1684 */ 1685 1686 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 1687 if (in_vbl && (*vpos >= vbl_start)) { 1688 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal; 1689 *vpos = *vpos - vtotal; 1690 } 1691 1692 /* Correct for shifted end of vbl at vbl_end. */ 1693 *vpos = *vpos - vbl_end; 1694 1695 /* In vblank? */ 1696 if (in_vbl) 1697 ret |= DRM_SCANOUTPOS_INVBL; 1698 1699 return ret; 1700 } 1701