1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/radeon_drm.h> 28 #include "radeon.h" 29 30 #include "atom.h" 31 #include <asm/div64.h> 32 33 #include <linux/pm_runtime.h> 34 #include <drm/drm_crtc_helper.h> 35 #include <drm/drm_plane_helper.h> 36 #include <drm/drm_edid.h> 37 38 #include <linux/gcd.h> 39 40 static void avivo_crtc_load_lut(struct drm_crtc *crtc) 41 { 42 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 43 struct drm_device *dev = crtc->dev; 44 struct radeon_device *rdev = dev->dev_private; 45 int i; 46 47 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 48 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); 49 50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 52 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 53 54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 56 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 57 58 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); 59 WREG32(AVIVO_DC_LUT_RW_MODE, 0); 60 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); 61 62 WREG8(AVIVO_DC_LUT_RW_INDEX, 0); 63 for (i = 0; i < 256; i++) { 64 WREG32(AVIVO_DC_LUT_30_COLOR, 65 (radeon_crtc->lut_r[i] << 20) | 66 (radeon_crtc->lut_g[i] << 10) | 67 (radeon_crtc->lut_b[i] << 0)); 68 } 69 70 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */ 71 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1); 72 } 73 74 static void dce4_crtc_load_lut(struct drm_crtc *crtc) 75 { 76 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 77 struct drm_device *dev = crtc->dev; 78 struct radeon_device *rdev = dev->dev_private; 79 int i; 80 81 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 82 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 83 84 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 85 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 86 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 87 88 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 89 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 90 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 91 92 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 93 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 94 95 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 96 for (i = 0; i < 256; i++) { 97 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 98 (radeon_crtc->lut_r[i] << 20) | 99 (radeon_crtc->lut_g[i] << 10) | 100 (radeon_crtc->lut_b[i] << 0)); 101 } 102 } 103 104 static void dce5_crtc_load_lut(struct drm_crtc *crtc) 105 { 106 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 107 struct drm_device *dev = crtc->dev; 108 struct radeon_device *rdev = dev->dev_private; 109 int i; 110 111 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 112 113 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 114 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | 115 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); 116 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, 117 NI_GRPH_PRESCALE_BYPASS); 118 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, 119 NI_OVL_PRESCALE_BYPASS); 120 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, 121 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | 122 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); 123 124 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 125 126 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 127 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 128 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 129 130 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 131 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 132 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 133 134 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 135 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 136 137 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 138 for (i = 0; i < 256; i++) { 139 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 140 (radeon_crtc->lut_r[i] << 20) | 141 (radeon_crtc->lut_g[i] << 10) | 142 (radeon_crtc->lut_b[i] << 0)); 143 } 144 145 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, 146 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 147 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 148 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 149 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); 150 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, 151 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | 152 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); 153 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, 154 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | 155 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); 156 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 157 (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) | 158 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); 159 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 160 WREG32(0x6940 + radeon_crtc->crtc_offset, 0); 161 if (ASIC_IS_DCE8(rdev)) { 162 /* XXX this only needs to be programmed once per crtc at startup, 163 * not sure where the best place for it is 164 */ 165 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset, 166 CIK_CURSOR_ALPHA_BLND_ENA); 167 } 168 } 169 170 static void legacy_crtc_load_lut(struct drm_crtc *crtc) 171 { 172 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 173 struct drm_device *dev = crtc->dev; 174 struct radeon_device *rdev = dev->dev_private; 175 int i; 176 uint32_t dac2_cntl; 177 178 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 179 if (radeon_crtc->crtc_id == 0) 180 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; 181 else 182 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; 183 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 184 185 WREG8(RADEON_PALETTE_INDEX, 0); 186 for (i = 0; i < 256; i++) { 187 WREG32(RADEON_PALETTE_30_DATA, 188 (radeon_crtc->lut_r[i] << 20) | 189 (radeon_crtc->lut_g[i] << 10) | 190 (radeon_crtc->lut_b[i] << 0)); 191 } 192 } 193 194 void radeon_crtc_load_lut(struct drm_crtc *crtc) 195 { 196 struct drm_device *dev = crtc->dev; 197 struct radeon_device *rdev = dev->dev_private; 198 199 if (!crtc->enabled) 200 return; 201 202 if (ASIC_IS_DCE5(rdev)) 203 dce5_crtc_load_lut(crtc); 204 else if (ASIC_IS_DCE4(rdev)) 205 dce4_crtc_load_lut(crtc); 206 else if (ASIC_IS_AVIVO(rdev)) 207 avivo_crtc_load_lut(crtc); 208 else 209 legacy_crtc_load_lut(crtc); 210 } 211 212 /** Sets the color ramps on behalf of fbcon */ 213 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 214 u16 blue, int regno) 215 { 216 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 217 218 radeon_crtc->lut_r[regno] = red >> 6; 219 radeon_crtc->lut_g[regno] = green >> 6; 220 radeon_crtc->lut_b[regno] = blue >> 6; 221 } 222 223 /** Gets the color ramps on behalf of fbcon */ 224 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 225 u16 *blue, int regno) 226 { 227 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 228 229 *red = radeon_crtc->lut_r[regno] << 6; 230 *green = radeon_crtc->lut_g[regno] << 6; 231 *blue = radeon_crtc->lut_b[regno] << 6; 232 } 233 234 static int radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 235 u16 *blue, uint32_t size, 236 struct drm_modeset_acquire_ctx *ctx) 237 { 238 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 239 int i; 240 241 /* userspace palettes are always correct as is */ 242 for (i = 0; i < size; i++) { 243 radeon_crtc->lut_r[i] = red[i] >> 6; 244 radeon_crtc->lut_g[i] = green[i] >> 6; 245 radeon_crtc->lut_b[i] = blue[i] >> 6; 246 } 247 radeon_crtc_load_lut(crtc); 248 249 return 0; 250 } 251 252 static void radeon_crtc_destroy(struct drm_crtc *crtc) 253 { 254 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 255 256 drm_crtc_cleanup(crtc); 257 destroy_workqueue(radeon_crtc->flip_queue); 258 kfree(radeon_crtc); 259 } 260 261 /** 262 * radeon_unpin_work_func - unpin old buffer object 263 * 264 * @__work - kernel work item 265 * 266 * Unpin the old frame buffer object outside of the interrupt handler 267 */ 268 static void radeon_unpin_work_func(struct work_struct *__work) 269 { 270 struct radeon_flip_work *work = 271 container_of(__work, struct radeon_flip_work, unpin_work); 272 int r; 273 274 /* unpin of the old buffer */ 275 r = radeon_bo_reserve(work->old_rbo, false); 276 if (likely(r == 0)) { 277 r = radeon_bo_unpin(work->old_rbo); 278 if (unlikely(r != 0)) { 279 DRM_ERROR("failed to unpin buffer after flip\n"); 280 } 281 radeon_bo_unreserve(work->old_rbo); 282 } else 283 DRM_ERROR("failed to reserve buffer after flip\n"); 284 285 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 286 kfree(work); 287 } 288 289 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id) 290 { 291 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 292 unsigned long flags; 293 u32 update_pending; 294 int vpos, hpos; 295 296 /* can happen during initialization */ 297 if (radeon_crtc == NULL) 298 return; 299 300 /* Skip the pageflip completion check below (based on polling) on 301 * asics which reliably support hw pageflip completion irqs. pflip 302 * irqs are a reliable and race-free method of handling pageflip 303 * completion detection. A use_pflipirq module parameter < 2 allows 304 * to override this in case of asics with faulty pflip irqs. 305 * A module parameter of 0 would only use this polling based path, 306 * a parameter of 1 would use pflip irq only as a backup to this 307 * path, as in Linux 3.16. 308 */ 309 if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev)) 310 return; 311 312 spin_lock_irqsave(&rdev->ddev->event_lock, flags); 313 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 314 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 315 "RADEON_FLIP_SUBMITTED(%d)\n", 316 radeon_crtc->flip_status, 317 RADEON_FLIP_SUBMITTED); 318 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 319 return; 320 } 321 322 update_pending = radeon_page_flip_pending(rdev, crtc_id); 323 324 /* Has the pageflip already completed in crtc, or is it certain 325 * to complete in this vblank? GET_DISTANCE_TO_VBLANKSTART provides 326 * distance to start of "fudged earlier" vblank in vpos, distance to 327 * start of real vblank in hpos. vpos >= 0 && hpos < 0 means we are in 328 * the last few scanlines before start of real vblank, where the vblank 329 * irq can fire, so we have sampled update_pending a bit too early and 330 * know the flip will complete at leading edge of the upcoming real 331 * vblank. On pre-AVIVO hardware, flips also complete inside the real 332 * vblank, not only at leading edge, so if update_pending for hpos >= 0 333 * == inside real vblank, the flip will complete almost immediately. 334 * Note that this method of completion handling is still not 100% race 335 * free, as we could execute before the radeon_flip_work_func managed 336 * to run and set the RADEON_FLIP_SUBMITTED status, thereby we no-op, 337 * but the flip still gets programmed into hw and completed during 338 * vblank, leading to a delayed emission of the flip completion event. 339 * This applies at least to pre-AVIVO hardware, where flips are always 340 * completing inside vblank, not only at leading edge of vblank. 341 */ 342 if (update_pending && 343 (DRM_SCANOUTPOS_VALID & 344 radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 345 GET_DISTANCE_TO_VBLANKSTART, 346 &vpos, &hpos, NULL, NULL, 347 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) && 348 ((vpos >= 0 && hpos < 0) || (hpos >= 0 && !ASIC_IS_AVIVO(rdev)))) { 349 /* crtc didn't flip in this target vblank interval, 350 * but flip is pending in crtc. Based on the current 351 * scanout position we know that the current frame is 352 * (nearly) complete and the flip will (likely) 353 * complete before the start of the next frame. 354 */ 355 update_pending = 0; 356 } 357 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 358 if (!update_pending) 359 radeon_crtc_handle_flip(rdev, crtc_id); 360 } 361 362 /** 363 * radeon_crtc_handle_flip - page flip completed 364 * 365 * @rdev: radeon device pointer 366 * @crtc_id: crtc number this event is for 367 * 368 * Called when we are sure that a page flip for this crtc is completed. 369 */ 370 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) 371 { 372 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 373 struct radeon_flip_work *work; 374 unsigned long flags; 375 376 /* this can happen at init */ 377 if (radeon_crtc == NULL) 378 return; 379 380 spin_lock_irqsave(&rdev->ddev->event_lock, flags); 381 work = radeon_crtc->flip_work; 382 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 383 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 384 "RADEON_FLIP_SUBMITTED(%d)\n", 385 radeon_crtc->flip_status, 386 RADEON_FLIP_SUBMITTED); 387 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 388 return; 389 } 390 391 /* Pageflip completed. Clean up. */ 392 radeon_crtc->flip_status = RADEON_FLIP_NONE; 393 radeon_crtc->flip_work = NULL; 394 395 /* wakeup userspace */ 396 if (work->event) 397 drm_crtc_send_vblank_event(&radeon_crtc->base, work->event); 398 399 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 400 401 drm_crtc_vblank_put(&radeon_crtc->base); 402 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id); 403 queue_work(radeon_crtc->flip_queue, &work->unpin_work); 404 } 405 406 /** 407 * radeon_flip_work_func - page flip framebuffer 408 * 409 * @work - kernel work item 410 * 411 * Wait for the buffer object to become idle and do the actual page flip 412 */ 413 static void radeon_flip_work_func(struct work_struct *__work) 414 { 415 struct radeon_flip_work *work = 416 container_of(__work, struct radeon_flip_work, flip_work); 417 struct radeon_device *rdev = work->rdev; 418 struct drm_device *dev = rdev->ddev; 419 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id]; 420 421 struct drm_crtc *crtc = &radeon_crtc->base; 422 unsigned long flags; 423 int r; 424 int vpos, hpos; 425 426 down_read(&rdev->exclusive_lock); 427 if (work->fence) { 428 struct radeon_fence *fence; 429 430 fence = to_radeon_fence(work->fence); 431 if (fence && fence->rdev == rdev) { 432 r = radeon_fence_wait(fence, false); 433 if (r == -EDEADLK) { 434 up_read(&rdev->exclusive_lock); 435 do { 436 r = radeon_gpu_reset(rdev); 437 } while (r == -EAGAIN); 438 down_read(&rdev->exclusive_lock); 439 } 440 } else 441 r = dma_fence_wait(work->fence, false); 442 443 if (r) 444 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r); 445 446 /* We continue with the page flip even if we failed to wait on 447 * the fence, otherwise the DRM core and userspace will be 448 * confused about which BO the CRTC is scanning out 449 */ 450 451 dma_fence_put(work->fence); 452 work->fence = NULL; 453 } 454 455 /* Wait until we're out of the vertical blank period before the one 456 * targeted by the flip. Always wait on pre DCE4 to avoid races with 457 * flip completion handling from vblank irq, as these old asics don't 458 * have reliable pageflip completion interrupts. 459 */ 460 while (radeon_crtc->enabled && 461 (radeon_get_crtc_scanoutpos(dev, work->crtc_id, 0, 462 &vpos, &hpos, NULL, NULL, 463 &crtc->hwmode) 464 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 465 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 466 (!ASIC_IS_AVIVO(rdev) || 467 ((int) (work->target_vblank - 468 dev->driver->get_vblank_counter(dev, work->crtc_id)) > 0))) 469 usleep_range(1000, 2000); 470 471 /* We borrow the event spin lock for protecting flip_status */ 472 spin_lock_irqsave(&crtc->dev->event_lock, flags); 473 474 /* set the proper interrupt */ 475 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id); 476 477 /* do the flip (mmio) */ 478 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async); 479 480 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED; 481 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 482 up_read(&rdev->exclusive_lock); 483 } 484 485 static int radeon_crtc_page_flip_target(struct drm_crtc *crtc, 486 struct drm_framebuffer *fb, 487 struct drm_pending_vblank_event *event, 488 uint32_t page_flip_flags, 489 uint32_t target, 490 struct drm_modeset_acquire_ctx *ctx) 491 { 492 struct drm_device *dev = crtc->dev; 493 struct radeon_device *rdev = dev->dev_private; 494 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 495 struct radeon_framebuffer *old_radeon_fb; 496 struct radeon_framebuffer *new_radeon_fb; 497 struct drm_gem_object *obj; 498 struct radeon_flip_work *work; 499 struct radeon_bo *new_rbo; 500 uint32_t tiling_flags, pitch_pixels; 501 uint64_t base; 502 unsigned long flags; 503 int r; 504 505 work = kzalloc(sizeof *work, GFP_KERNEL); 506 if (work == NULL) 507 return -ENOMEM; 508 509 INIT_WORK(&work->flip_work, radeon_flip_work_func); 510 INIT_WORK(&work->unpin_work, radeon_unpin_work_func); 511 512 work->rdev = rdev; 513 work->crtc_id = radeon_crtc->crtc_id; 514 work->event = event; 515 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 516 517 /* schedule unpin of the old buffer */ 518 old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb); 519 obj = old_radeon_fb->obj; 520 521 /* take a reference to the old object */ 522 drm_gem_object_reference(obj); 523 work->old_rbo = gem_to_radeon_bo(obj); 524 525 new_radeon_fb = to_radeon_framebuffer(fb); 526 obj = new_radeon_fb->obj; 527 new_rbo = gem_to_radeon_bo(obj); 528 529 /* pin the new buffer */ 530 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n", 531 work->old_rbo, new_rbo); 532 533 r = radeon_bo_reserve(new_rbo, false); 534 if (unlikely(r != 0)) { 535 DRM_ERROR("failed to reserve new rbo buffer before flip\n"); 536 goto cleanup; 537 } 538 /* Only 27 bit offset for legacy CRTC */ 539 r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM, 540 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, (u64 *)&base); 541 if (unlikely(r != 0)) { 542 radeon_bo_unreserve(new_rbo); 543 r = -EINVAL; 544 DRM_ERROR("failed to pin new rbo buffer before flip\n"); 545 goto cleanup; 546 } 547 work->fence = dma_fence_get(reservation_object_get_excl(new_rbo->tbo.resv)); 548 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); 549 radeon_bo_unreserve(new_rbo); 550 551 if (!ASIC_IS_AVIVO(rdev)) { 552 /* crtc offset is from display base addr not FB location */ 553 base -= radeon_crtc->legacy_display_base_addr; 554 pitch_pixels = fb->pitches[0] / fb->format->cpp[0]; 555 556 if (tiling_flags & RADEON_TILING_MACRO) { 557 if (ASIC_IS_R300(rdev)) { 558 base &= ~0x7ff; 559 } else { 560 int byteshift = fb->format->cpp[0] * 8 >> 4; 561 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11; 562 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8); 563 } 564 } else { 565 int offset = crtc->y * pitch_pixels + crtc->x; 566 switch (fb->format->cpp[0] * 8) { 567 case 8: 568 default: 569 offset *= 1; 570 break; 571 case 15: 572 case 16: 573 offset *= 2; 574 break; 575 case 24: 576 offset *= 3; 577 break; 578 case 32: 579 offset *= 4; 580 break; 581 } 582 base += offset; 583 } 584 base &= ~7; 585 } 586 work->base = base; 587 work->target_vblank = target - drm_crtc_vblank_count(crtc) + 588 dev->driver->get_vblank_counter(dev, work->crtc_id); 589 590 /* We borrow the event spin lock for protecting flip_work */ 591 spin_lock_irqsave(&crtc->dev->event_lock, flags); 592 593 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) { 594 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 595 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 596 r = -EBUSY; 597 goto pflip_cleanup; 598 } 599 radeon_crtc->flip_status = RADEON_FLIP_PENDING; 600 radeon_crtc->flip_work = work; 601 602 /* update crtc fb */ 603 crtc->primary->fb = fb; 604 605 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 606 607 queue_work(radeon_crtc->flip_queue, &work->flip_work); 608 return 0; 609 610 pflip_cleanup: 611 if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) { 612 DRM_ERROR("failed to reserve new rbo in error path\n"); 613 goto cleanup; 614 } 615 if (unlikely(radeon_bo_unpin(new_rbo) != 0)) { 616 DRM_ERROR("failed to unpin new rbo in error path\n"); 617 } 618 radeon_bo_unreserve(new_rbo); 619 620 cleanup: 621 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 622 dma_fence_put(work->fence); 623 kfree(work); 624 return r; 625 } 626 627 static int 628 radeon_crtc_set_config(struct drm_mode_set *set, 629 struct drm_modeset_acquire_ctx *ctx) 630 { 631 struct drm_device *dev; 632 struct radeon_device *rdev; 633 struct drm_crtc *crtc; 634 bool active = false; 635 int ret; 636 637 if (!set || !set->crtc) 638 return -EINVAL; 639 640 dev = set->crtc->dev; 641 642 ret = pm_runtime_get_sync(dev->dev); 643 if (ret < 0) 644 return ret; 645 646 ret = drm_crtc_helper_set_config(set, ctx); 647 648 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 649 if (crtc->enabled) 650 active = true; 651 652 pm_runtime_mark_last_busy(dev->dev); 653 654 rdev = dev->dev_private; 655 /* if we have active crtcs and we don't have a power ref, 656 take the current one */ 657 if (active && !rdev->have_disp_power_ref) { 658 rdev->have_disp_power_ref = true; 659 return ret; 660 } 661 /* if we have no active crtcs, then drop the power ref 662 we got before */ 663 if (!active && rdev->have_disp_power_ref) { 664 pm_runtime_put_autosuspend(dev->dev); 665 rdev->have_disp_power_ref = false; 666 } 667 668 /* drop the power reference we got coming in here */ 669 pm_runtime_put_autosuspend(dev->dev); 670 return ret; 671 } 672 673 static const struct drm_crtc_funcs radeon_crtc_funcs = { 674 .cursor_set2 = radeon_crtc_cursor_set2, 675 .cursor_move = radeon_crtc_cursor_move, 676 .gamma_set = radeon_crtc_gamma_set, 677 .set_config = radeon_crtc_set_config, 678 .destroy = radeon_crtc_destroy, 679 .page_flip_target = radeon_crtc_page_flip_target, 680 }; 681 682 static void radeon_crtc_init(struct drm_device *dev, int index) 683 { 684 struct radeon_device *rdev = dev->dev_private; 685 struct radeon_crtc *radeon_crtc; 686 int i; 687 688 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 689 if (radeon_crtc == NULL) 690 return; 691 692 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); 693 694 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); 695 radeon_crtc->crtc_id = index; 696 radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0); 697 rdev->mode_info.crtcs[index] = radeon_crtc; 698 699 if (rdev->family >= CHIP_BONAIRE) { 700 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH; 701 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT; 702 } else { 703 radeon_crtc->max_cursor_width = CURSOR_WIDTH; 704 radeon_crtc->max_cursor_height = CURSOR_HEIGHT; 705 } 706 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width; 707 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height; 708 709 #if 0 710 radeon_crtc->mode_set.crtc = &radeon_crtc->base; 711 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); 712 radeon_crtc->mode_set.num_connectors = 0; 713 #endif 714 715 for (i = 0; i < 256; i++) { 716 radeon_crtc->lut_r[i] = i << 2; 717 radeon_crtc->lut_g[i] = i << 2; 718 radeon_crtc->lut_b[i] = i << 2; 719 } 720 721 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) 722 radeon_atombios_init_crtc(dev, radeon_crtc); 723 else 724 radeon_legacy_init_crtc(dev, radeon_crtc); 725 } 726 727 static const char *encoder_names[38] = { 728 "NONE", 729 "INTERNAL_LVDS", 730 "INTERNAL_TMDS1", 731 "INTERNAL_TMDS2", 732 "INTERNAL_DAC1", 733 "INTERNAL_DAC2", 734 "INTERNAL_SDVOA", 735 "INTERNAL_SDVOB", 736 "SI170B", 737 "CH7303", 738 "CH7301", 739 "INTERNAL_DVO1", 740 "EXTERNAL_SDVOA", 741 "EXTERNAL_SDVOB", 742 "TITFP513", 743 "INTERNAL_LVTM1", 744 "VT1623", 745 "HDMI_SI1930", 746 "HDMI_INTERNAL", 747 "INTERNAL_KLDSCP_TMDS1", 748 "INTERNAL_KLDSCP_DVO1", 749 "INTERNAL_KLDSCP_DAC1", 750 "INTERNAL_KLDSCP_DAC2", 751 "SI178", 752 "MVPU_FPGA", 753 "INTERNAL_DDI", 754 "VT1625", 755 "HDMI_SI1932", 756 "DP_AN9801", 757 "DP_DP501", 758 "INTERNAL_UNIPHY", 759 "INTERNAL_KLDSCP_LVTMA", 760 "INTERNAL_UNIPHY1", 761 "INTERNAL_UNIPHY2", 762 "NUTMEG", 763 "TRAVIS", 764 "INTERNAL_VCE", 765 "INTERNAL_UNIPHY3", 766 }; 767 768 static const char *hpd_names[6] = { 769 "HPD1", 770 "HPD2", 771 "HPD3", 772 "HPD4", 773 "HPD5", 774 "HPD6", 775 }; 776 777 static void radeon_print_display_setup(struct drm_device *dev) 778 { 779 struct drm_connector *connector; 780 struct radeon_connector *radeon_connector; 781 struct drm_encoder *encoder; 782 struct radeon_encoder *radeon_encoder; 783 uint32_t devices; 784 int i = 0; 785 786 DRM_INFO("Radeon Display Connectors\n"); 787 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 788 radeon_connector = to_radeon_connector(connector); 789 DRM_INFO("Connector %d:\n", i); 790 DRM_INFO(" %s\n", connector->name); 791 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 792 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); 793 if (radeon_connector->ddc_bus) { 794 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 795 radeon_connector->ddc_bus->rec.mask_clk_reg, 796 radeon_connector->ddc_bus->rec.mask_data_reg, 797 radeon_connector->ddc_bus->rec.a_clk_reg, 798 radeon_connector->ddc_bus->rec.a_data_reg, 799 radeon_connector->ddc_bus->rec.en_clk_reg, 800 radeon_connector->ddc_bus->rec.en_data_reg, 801 radeon_connector->ddc_bus->rec.y_clk_reg, 802 radeon_connector->ddc_bus->rec.y_data_reg); 803 if (radeon_connector->router.ddc_valid) 804 DRM_INFO(" DDC Router 0x%x/0x%x\n", 805 radeon_connector->router.ddc_mux_control_pin, 806 radeon_connector->router.ddc_mux_state); 807 if (radeon_connector->router.cd_valid) 808 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 809 radeon_connector->router.cd_mux_control_pin, 810 radeon_connector->router.cd_mux_state); 811 } else { 812 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 813 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 814 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 815 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 816 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 817 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 818 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 819 } 820 DRM_INFO(" Encoders:\n"); 821 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 822 radeon_encoder = to_radeon_encoder(encoder); 823 devices = radeon_encoder->devices & radeon_connector->devices; 824 if (devices) { 825 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 826 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); 827 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 828 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); 829 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 830 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); 831 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 832 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); 833 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 834 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); 835 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 836 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); 837 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 838 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); 839 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 840 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); 841 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 842 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); 843 if (devices & ATOM_DEVICE_TV1_SUPPORT) 844 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); 845 if (devices & ATOM_DEVICE_CV_SUPPORT) 846 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); 847 } 848 } 849 i++; 850 } 851 } 852 853 static bool radeon_setup_enc_conn(struct drm_device *dev) 854 { 855 struct radeon_device *rdev = dev->dev_private; 856 bool ret = false; 857 858 if (rdev->bios) { 859 if (rdev->is_atom_bios) { 860 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); 861 if (ret == false) 862 ret = radeon_get_atom_connector_info_from_object_table(dev); 863 } else { 864 ret = radeon_get_legacy_connector_info_from_bios(dev); 865 if (ret == false) 866 ret = radeon_get_legacy_connector_info_from_table(dev); 867 } 868 } else { 869 if (!ASIC_IS_AVIVO(rdev)) 870 ret = radeon_get_legacy_connector_info_from_table(dev); 871 } 872 if (ret) { 873 radeon_setup_encoder_clones(dev); 874 radeon_print_display_setup(dev); 875 } 876 877 return ret; 878 } 879 880 /* avivo */ 881 882 /** 883 * avivo_reduce_ratio - fractional number reduction 884 * 885 * @nom: nominator 886 * @den: denominator 887 * @nom_min: minimum value for nominator 888 * @den_min: minimum value for denominator 889 * 890 * Find the greatest common divisor and apply it on both nominator and 891 * denominator, but make nominator and denominator are at least as large 892 * as their minimum values. 893 */ 894 static void avivo_reduce_ratio(unsigned *nom, unsigned *den, 895 unsigned nom_min, unsigned den_min) 896 { 897 unsigned tmp; 898 899 /* reduce the numbers to a simpler ratio */ 900 tmp = gcd(*nom, *den); 901 *nom /= tmp; 902 *den /= tmp; 903 904 /* make sure nominator is large enough */ 905 if (*nom < nom_min) { 906 tmp = DIV_ROUND_UP(nom_min, *nom); 907 *nom *= tmp; 908 *den *= tmp; 909 } 910 911 /* make sure the denominator is large enough */ 912 if (*den < den_min) { 913 tmp = DIV_ROUND_UP(den_min, *den); 914 *nom *= tmp; 915 *den *= tmp; 916 } 917 } 918 919 /** 920 * avivo_get_fb_ref_div - feedback and ref divider calculation 921 * 922 * @nom: nominator 923 * @den: denominator 924 * @post_div: post divider 925 * @fb_div_max: feedback divider maximum 926 * @ref_div_max: reference divider maximum 927 * @fb_div: resulting feedback divider 928 * @ref_div: resulting reference divider 929 * 930 * Calculate feedback and reference divider for a given post divider. Makes 931 * sure we stay within the limits. 932 */ 933 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, 934 unsigned fb_div_max, unsigned ref_div_max, 935 unsigned *fb_div, unsigned *ref_div) 936 { 937 /* limit reference * post divider to a maximum */ 938 ref_div_max = max(min(100 / post_div, ref_div_max), 1u); 939 940 /* get matching reference and feedback divider */ 941 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); 942 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); 943 944 /* limit fb divider to its maximum */ 945 if (*fb_div > fb_div_max) { 946 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); 947 *fb_div = fb_div_max; 948 } 949 } 950 951 /** 952 * radeon_compute_pll_avivo - compute PLL paramaters 953 * 954 * @pll: information about the PLL 955 * @dot_clock_p: resulting pixel clock 956 * fb_div_p: resulting feedback divider 957 * frac_fb_div_p: fractional part of the feedback divider 958 * ref_div_p: resulting reference divider 959 * post_div_p: resulting reference divider 960 * 961 * Try to calculate the PLL parameters to generate the given frequency: 962 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div) 963 */ 964 void radeon_compute_pll_avivo(struct radeon_pll *pll, 965 u32 freq, 966 u32 *dot_clock_p, 967 u32 *fb_div_p, 968 u32 *frac_fb_div_p, 969 u32 *ref_div_p, 970 u32 *post_div_p) 971 { 972 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? 973 freq : freq / 10; 974 975 unsigned fb_div_min, fb_div_max, fb_div; 976 unsigned post_div_min, post_div_max, post_div; 977 unsigned ref_div_min, ref_div_max, ref_div; 978 unsigned post_div_best, diff_best; 979 unsigned nom, den; 980 981 /* determine allowed feedback divider range */ 982 fb_div_min = pll->min_feedback_div; 983 fb_div_max = pll->max_feedback_div; 984 985 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 986 fb_div_min *= 10; 987 fb_div_max *= 10; 988 } 989 990 /* determine allowed ref divider range */ 991 if (pll->flags & RADEON_PLL_USE_REF_DIV) 992 ref_div_min = pll->reference_div; 993 else 994 ref_div_min = pll->min_ref_div; 995 996 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && 997 pll->flags & RADEON_PLL_USE_REF_DIV) 998 ref_div_max = pll->reference_div; 999 else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 1000 /* fix for problems on RS880 */ 1001 ref_div_max = min(pll->max_ref_div, 7u); 1002 else 1003 ref_div_max = pll->max_ref_div; 1004 1005 /* determine allowed post divider range */ 1006 if (pll->flags & RADEON_PLL_USE_POST_DIV) { 1007 post_div_min = pll->post_div; 1008 post_div_max = pll->post_div; 1009 } else { 1010 unsigned vco_min, vco_max; 1011 1012 if (pll->flags & RADEON_PLL_IS_LCD) { 1013 vco_min = pll->lcd_pll_out_min; 1014 vco_max = pll->lcd_pll_out_max; 1015 } else { 1016 vco_min = pll->pll_out_min; 1017 vco_max = pll->pll_out_max; 1018 } 1019 1020 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1021 vco_min *= 10; 1022 vco_max *= 10; 1023 } 1024 1025 post_div_min = vco_min / target_clock; 1026 if ((target_clock * post_div_min) < vco_min) 1027 ++post_div_min; 1028 if (post_div_min < pll->min_post_div) 1029 post_div_min = pll->min_post_div; 1030 1031 post_div_max = vco_max / target_clock; 1032 if ((target_clock * post_div_max) > vco_max) 1033 --post_div_max; 1034 if (post_div_max > pll->max_post_div) 1035 post_div_max = pll->max_post_div; 1036 } 1037 1038 /* represent the searched ratio as fractional number */ 1039 nom = target_clock; 1040 den = pll->reference_freq; 1041 1042 /* reduce the numbers to a simpler ratio */ 1043 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min); 1044 1045 /* now search for a post divider */ 1046 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 1047 post_div_best = post_div_min; 1048 else 1049 post_div_best = post_div_max; 1050 diff_best = ~0; 1051 1052 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { 1053 unsigned diff; 1054 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, 1055 ref_div_max, &fb_div, &ref_div); 1056 diff = abs(target_clock - (pll->reference_freq * fb_div) / 1057 (ref_div * post_div)); 1058 1059 if (diff < diff_best || (diff == diff_best && 1060 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) { 1061 1062 post_div_best = post_div; 1063 diff_best = diff; 1064 } 1065 } 1066 post_div = post_div_best; 1067 1068 /* get the feedback and reference divider for the optimal value */ 1069 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max, 1070 &fb_div, &ref_div); 1071 1072 /* reduce the numbers to a simpler ratio once more */ 1073 /* this also makes sure that the reference divider is large enough */ 1074 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); 1075 1076 /* avoid high jitter with small fractional dividers */ 1077 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { 1078 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50); 1079 if (fb_div < fb_div_min) { 1080 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div); 1081 fb_div *= tmp; 1082 ref_div *= tmp; 1083 } 1084 } 1085 1086 /* and finally save the result */ 1087 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1088 *fb_div_p = fb_div / 10; 1089 *frac_fb_div_p = fb_div % 10; 1090 } else { 1091 *fb_div_p = fb_div; 1092 *frac_fb_div_p = 0; 1093 } 1094 1095 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + 1096 (pll->reference_freq * *frac_fb_div_p)) / 1097 (ref_div * post_div * 10); 1098 *ref_div_p = ref_div; 1099 *post_div_p = post_div; 1100 1101 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1102 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, 1103 ref_div, post_div); 1104 } 1105 1106 /* pre-avivo */ 1107 static inline uint32_t radeon_div(uint64_t n, uint32_t d) 1108 { 1109 uint64_t mod; 1110 1111 n += d / 2; 1112 1113 mod = do_div(n, d); 1114 return n; 1115 } 1116 1117 void radeon_compute_pll_legacy(struct radeon_pll *pll, 1118 uint64_t freq, 1119 uint32_t *dot_clock_p, 1120 uint32_t *fb_div_p, 1121 uint32_t *frac_fb_div_p, 1122 uint32_t *ref_div_p, 1123 uint32_t *post_div_p) 1124 { 1125 uint32_t min_ref_div = pll->min_ref_div; 1126 uint32_t max_ref_div = pll->max_ref_div; 1127 uint32_t min_post_div = pll->min_post_div; 1128 uint32_t max_post_div = pll->max_post_div; 1129 uint32_t min_fractional_feed_div = 0; 1130 uint32_t max_fractional_feed_div = 0; 1131 uint32_t best_vco = pll->best_vco; 1132 uint32_t best_post_div = 1; 1133 uint32_t best_ref_div = 1; 1134 uint32_t best_feedback_div = 1; 1135 uint32_t best_frac_feedback_div = 0; 1136 uint32_t best_freq = -1; 1137 uint32_t best_error = 0xffffffff; 1138 uint32_t best_vco_diff = 1; 1139 uint32_t post_div; 1140 u32 pll_out_min, pll_out_max; 1141 1142 DRM_DEBUG_KMS("PLL freq %lu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); 1143 freq = freq * 1000; 1144 1145 if (pll->flags & RADEON_PLL_IS_LCD) { 1146 pll_out_min = pll->lcd_pll_out_min; 1147 pll_out_max = pll->lcd_pll_out_max; 1148 } else { 1149 pll_out_min = pll->pll_out_min; 1150 pll_out_max = pll->pll_out_max; 1151 } 1152 1153 if (pll_out_min > 64800) 1154 pll_out_min = 64800; 1155 1156 if (pll->flags & RADEON_PLL_USE_REF_DIV) 1157 min_ref_div = max_ref_div = pll->reference_div; 1158 else { 1159 while (min_ref_div < max_ref_div-1) { 1160 uint32_t mid = (min_ref_div + max_ref_div) / 2; 1161 uint32_t pll_in = pll->reference_freq / mid; 1162 if (pll_in < pll->pll_in_min) 1163 max_ref_div = mid; 1164 else if (pll_in > pll->pll_in_max) 1165 min_ref_div = mid; 1166 else 1167 break; 1168 } 1169 } 1170 1171 if (pll->flags & RADEON_PLL_USE_POST_DIV) 1172 min_post_div = max_post_div = pll->post_div; 1173 1174 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1175 min_fractional_feed_div = pll->min_frac_feedback_div; 1176 max_fractional_feed_div = pll->max_frac_feedback_div; 1177 } 1178 1179 for (post_div = max_post_div; post_div >= min_post_div; --post_div) { 1180 uint32_t ref_div; 1181 1182 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 1183 continue; 1184 1185 /* legacy radeons only have a few post_divs */ 1186 if (pll->flags & RADEON_PLL_LEGACY) { 1187 if ((post_div == 5) || 1188 (post_div == 7) || 1189 (post_div == 9) || 1190 (post_div == 10) || 1191 (post_div == 11) || 1192 (post_div == 13) || 1193 (post_div == 14) || 1194 (post_div == 15)) 1195 continue; 1196 } 1197 1198 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { 1199 uint32_t feedback_div, current_freq = 0, error, vco_diff; 1200 uint32_t pll_in = pll->reference_freq / ref_div; 1201 uint32_t min_feed_div = pll->min_feedback_div; 1202 uint32_t max_feed_div = pll->max_feedback_div + 1; 1203 1204 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) 1205 continue; 1206 1207 while (min_feed_div < max_feed_div) { 1208 uint32_t vco; 1209 uint32_t min_frac_feed_div = min_fractional_feed_div; 1210 uint32_t max_frac_feed_div = max_fractional_feed_div + 1; 1211 uint32_t frac_feedback_div; 1212 uint64_t tmp; 1213 1214 feedback_div = (min_feed_div + max_feed_div) / 2; 1215 1216 tmp = (uint64_t)pll->reference_freq * feedback_div; 1217 vco = radeon_div(tmp, ref_div); 1218 1219 if (vco < pll_out_min) { 1220 min_feed_div = feedback_div + 1; 1221 continue; 1222 } else if (vco > pll_out_max) { 1223 max_feed_div = feedback_div; 1224 continue; 1225 } 1226 1227 while (min_frac_feed_div < max_frac_feed_div) { 1228 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; 1229 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; 1230 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; 1231 current_freq = radeon_div(tmp, ref_div * post_div); 1232 1233 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 1234 if (freq < current_freq) 1235 error = 0xffffffff; 1236 else 1237 error = freq - current_freq; 1238 } else 1239 error = abs(current_freq - freq); 1240 vco_diff = abs(vco - best_vco); 1241 1242 if ((best_vco == 0 && error < best_error) || 1243 (best_vco != 0 && 1244 ((best_error > 100 && error < best_error - 100) || 1245 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { 1246 best_post_div = post_div; 1247 best_ref_div = ref_div; 1248 best_feedback_div = feedback_div; 1249 best_frac_feedback_div = frac_feedback_div; 1250 best_freq = current_freq; 1251 best_error = error; 1252 best_vco_diff = vco_diff; 1253 } else if (current_freq == freq) { 1254 if (best_freq == -1) { 1255 best_post_div = post_div; 1256 best_ref_div = ref_div; 1257 best_feedback_div = feedback_div; 1258 best_frac_feedback_div = frac_feedback_div; 1259 best_freq = current_freq; 1260 best_error = error; 1261 best_vco_diff = vco_diff; 1262 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 1263 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 1264 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 1265 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 1266 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 1267 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 1268 best_post_div = post_div; 1269 best_ref_div = ref_div; 1270 best_feedback_div = feedback_div; 1271 best_frac_feedback_div = frac_feedback_div; 1272 best_freq = current_freq; 1273 best_error = error; 1274 best_vco_diff = vco_diff; 1275 } 1276 } 1277 if (current_freq < freq) 1278 min_frac_feed_div = frac_feedback_div + 1; 1279 else 1280 max_frac_feed_div = frac_feedback_div; 1281 } 1282 if (current_freq < freq) 1283 min_feed_div = feedback_div + 1; 1284 else 1285 max_feed_div = feedback_div; 1286 } 1287 } 1288 } 1289 1290 *dot_clock_p = best_freq / 10000; 1291 *fb_div_p = best_feedback_div; 1292 *frac_fb_div_p = best_frac_feedback_div; 1293 *ref_div_p = best_ref_div; 1294 *post_div_p = best_post_div; 1295 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1296 (long long)freq, 1297 best_freq / 1000, best_feedback_div, best_frac_feedback_div, 1298 best_ref_div, best_post_div); 1299 1300 } 1301 1302 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) 1303 { 1304 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1305 1306 drm_gem_object_unreference_unlocked(radeon_fb->obj); 1307 drm_framebuffer_cleanup(fb); 1308 kfree(radeon_fb); 1309 } 1310 1311 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, 1312 struct drm_file *file_priv, 1313 unsigned int *handle) 1314 { 1315 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1316 1317 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); 1318 } 1319 1320 static const struct drm_framebuffer_funcs radeon_fb_funcs = { 1321 .destroy = radeon_user_framebuffer_destroy, 1322 .create_handle = radeon_user_framebuffer_create_handle, 1323 }; 1324 1325 int 1326 radeon_framebuffer_init(struct drm_device *dev, 1327 struct radeon_framebuffer *rfb, 1328 const struct drm_mode_fb_cmd2 *mode_cmd, 1329 struct drm_gem_object *obj) 1330 { 1331 int ret; 1332 rfb->obj = obj; 1333 drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); 1334 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); 1335 if (ret) { 1336 rfb->obj = NULL; 1337 return ret; 1338 } 1339 return 0; 1340 } 1341 1342 static struct drm_framebuffer * 1343 radeon_user_framebuffer_create(struct drm_device *dev, 1344 struct drm_file *file_priv, 1345 const struct drm_mode_fb_cmd2 *mode_cmd) 1346 { 1347 struct drm_gem_object *obj; 1348 struct radeon_framebuffer *radeon_fb; 1349 int ret; 1350 1351 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); 1352 if (obj == NULL) { 1353 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 1354 "can't create framebuffer\n", mode_cmd->handles[0]); 1355 return ERR_PTR(-ENOENT); 1356 } 1357 1358 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ 1359 if (obj->import_attach) { 1360 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n"); 1361 return ERR_PTR(-EINVAL); 1362 } 1363 1364 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); 1365 if (radeon_fb == NULL) { 1366 drm_gem_object_unreference_unlocked(obj); 1367 return ERR_PTR(-ENOMEM); 1368 } 1369 1370 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj); 1371 if (ret) { 1372 kfree(radeon_fb); 1373 drm_gem_object_unreference_unlocked(obj); 1374 return ERR_PTR(ret); 1375 } 1376 1377 return &radeon_fb->base; 1378 } 1379 1380 static void radeon_output_poll_changed(struct drm_device *dev) 1381 { 1382 struct radeon_device *rdev = dev->dev_private; 1383 radeon_fb_output_poll_changed(rdev); 1384 } 1385 1386 static const struct drm_mode_config_funcs radeon_mode_funcs = { 1387 .fb_create = radeon_user_framebuffer_create, 1388 .output_poll_changed = radeon_output_poll_changed 1389 }; 1390 1391 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = 1392 { { 0, "driver" }, 1393 { 1, "bios" }, 1394 }; 1395 1396 static struct drm_prop_enum_list radeon_tv_std_enum_list[] = 1397 { { TV_STD_NTSC, "ntsc" }, 1398 { TV_STD_PAL, "pal" }, 1399 { TV_STD_PAL_M, "pal-m" }, 1400 { TV_STD_PAL_60, "pal-60" }, 1401 { TV_STD_NTSC_J, "ntsc-j" }, 1402 { TV_STD_SCART_PAL, "scart-pal" }, 1403 { TV_STD_PAL_CN, "pal-cn" }, 1404 { TV_STD_SECAM, "secam" }, 1405 }; 1406 1407 static struct drm_prop_enum_list radeon_underscan_enum_list[] = 1408 { { UNDERSCAN_OFF, "off" }, 1409 { UNDERSCAN_ON, "on" }, 1410 { UNDERSCAN_AUTO, "auto" }, 1411 }; 1412 1413 static struct drm_prop_enum_list radeon_audio_enum_list[] = 1414 { { RADEON_AUDIO_DISABLE, "off" }, 1415 { RADEON_AUDIO_ENABLE, "on" }, 1416 { RADEON_AUDIO_AUTO, "auto" }, 1417 }; 1418 1419 /* XXX support different dither options? spatial, temporal, both, etc. */ 1420 static struct drm_prop_enum_list radeon_dither_enum_list[] = 1421 { { RADEON_FMT_DITHER_DISABLE, "off" }, 1422 { RADEON_FMT_DITHER_ENABLE, "on" }, 1423 }; 1424 1425 static struct drm_prop_enum_list radeon_output_csc_enum_list[] = 1426 { { RADEON_OUTPUT_CSC_BYPASS, "bypass" }, 1427 { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" }, 1428 { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" }, 1429 { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" }, 1430 }; 1431 1432 static int radeon_modeset_create_props(struct radeon_device *rdev) 1433 { 1434 int sz; 1435 1436 if (rdev->is_atom_bios) { 1437 rdev->mode_info.coherent_mode_property = 1438 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1); 1439 if (!rdev->mode_info.coherent_mode_property) 1440 return -ENOMEM; 1441 } 1442 1443 if (!ASIC_IS_AVIVO(rdev)) { 1444 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); 1445 rdev->mode_info.tmds_pll_property = 1446 drm_property_create_enum(rdev->ddev, 0, 1447 "tmds_pll", 1448 radeon_tmds_pll_enum_list, sz); 1449 } 1450 1451 rdev->mode_info.load_detect_property = 1452 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1); 1453 if (!rdev->mode_info.load_detect_property) 1454 return -ENOMEM; 1455 1456 drm_mode_create_scaling_mode_property(rdev->ddev); 1457 1458 sz = ARRAY_SIZE(radeon_tv_std_enum_list); 1459 rdev->mode_info.tv_std_property = 1460 drm_property_create_enum(rdev->ddev, 0, 1461 "tv standard", 1462 radeon_tv_std_enum_list, sz); 1463 1464 sz = ARRAY_SIZE(radeon_underscan_enum_list); 1465 rdev->mode_info.underscan_property = 1466 drm_property_create_enum(rdev->ddev, 0, 1467 "underscan", 1468 radeon_underscan_enum_list, sz); 1469 1470 rdev->mode_info.underscan_hborder_property = 1471 drm_property_create_range(rdev->ddev, 0, 1472 "underscan hborder", 0, 128); 1473 if (!rdev->mode_info.underscan_hborder_property) 1474 return -ENOMEM; 1475 1476 rdev->mode_info.underscan_vborder_property = 1477 drm_property_create_range(rdev->ddev, 0, 1478 "underscan vborder", 0, 128); 1479 if (!rdev->mode_info.underscan_vborder_property) 1480 return -ENOMEM; 1481 1482 sz = ARRAY_SIZE(radeon_audio_enum_list); 1483 rdev->mode_info.audio_property = 1484 drm_property_create_enum(rdev->ddev, 0, 1485 "audio", 1486 radeon_audio_enum_list, sz); 1487 1488 sz = ARRAY_SIZE(radeon_dither_enum_list); 1489 rdev->mode_info.dither_property = 1490 drm_property_create_enum(rdev->ddev, 0, 1491 "dither", 1492 radeon_dither_enum_list, sz); 1493 1494 sz = ARRAY_SIZE(radeon_output_csc_enum_list); 1495 rdev->mode_info.output_csc_property = 1496 drm_property_create_enum(rdev->ddev, 0, 1497 "output_csc", 1498 radeon_output_csc_enum_list, sz); 1499 1500 return 0; 1501 } 1502 1503 void radeon_update_display_priority(struct radeon_device *rdev) 1504 { 1505 /* adjustment options for the display watermarks */ 1506 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { 1507 /* set display priority to high for r3xx, rv515 chips 1508 * this avoids flickering due to underflow to the 1509 * display controllers during heavy acceleration. 1510 * Don't force high on rs4xx igp chips as it seems to 1511 * affect the sound card. See kernel bug 15982. 1512 */ 1513 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && 1514 !(rdev->flags & RADEON_IS_IGP)) 1515 rdev->disp_priority = 2; 1516 else 1517 rdev->disp_priority = 0; 1518 } else 1519 rdev->disp_priority = radeon_disp_priority; 1520 1521 } 1522 1523 /* 1524 * Allocate hdmi structs and determine register offsets 1525 */ 1526 static void radeon_afmt_init(struct radeon_device *rdev) 1527 { 1528 int i; 1529 1530 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) 1531 rdev->mode_info.afmt[i] = NULL; 1532 1533 if (ASIC_IS_NODCE(rdev)) { 1534 /* nothing to do */ 1535 } else if (ASIC_IS_DCE4(rdev)) { 1536 static uint32_t eg_offsets[] = { 1537 EVERGREEN_CRTC0_REGISTER_OFFSET, 1538 EVERGREEN_CRTC1_REGISTER_OFFSET, 1539 EVERGREEN_CRTC2_REGISTER_OFFSET, 1540 EVERGREEN_CRTC3_REGISTER_OFFSET, 1541 EVERGREEN_CRTC4_REGISTER_OFFSET, 1542 EVERGREEN_CRTC5_REGISTER_OFFSET, 1543 0x13830 - 0x7030, 1544 }; 1545 int num_afmt; 1546 1547 /* DCE8 has 7 audio blocks tied to DIG encoders */ 1548 /* DCE6 has 6 audio blocks tied to DIG encoders */ 1549 /* DCE4/5 has 6 audio blocks tied to DIG encoders */ 1550 /* DCE4.1 has 2 audio blocks tied to DIG encoders */ 1551 if (ASIC_IS_DCE8(rdev)) 1552 num_afmt = 7; 1553 else if (ASIC_IS_DCE6(rdev)) 1554 num_afmt = 6; 1555 else if (ASIC_IS_DCE5(rdev)) 1556 num_afmt = 6; 1557 else if (ASIC_IS_DCE41(rdev)) 1558 num_afmt = 2; 1559 else /* DCE4 */ 1560 num_afmt = 6; 1561 1562 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets)); 1563 for (i = 0; i < num_afmt; i++) { 1564 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1565 if (rdev->mode_info.afmt[i]) { 1566 rdev->mode_info.afmt[i]->offset = eg_offsets[i]; 1567 rdev->mode_info.afmt[i]->id = i; 1568 } 1569 } 1570 } else if (ASIC_IS_DCE3(rdev)) { 1571 /* DCE3.x has 2 audio blocks tied to DIG encoders */ 1572 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1573 if (rdev->mode_info.afmt[0]) { 1574 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0; 1575 rdev->mode_info.afmt[0]->id = 0; 1576 } 1577 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1578 if (rdev->mode_info.afmt[1]) { 1579 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1; 1580 rdev->mode_info.afmt[1]->id = 1; 1581 } 1582 } else if (ASIC_IS_DCE2(rdev)) { 1583 /* DCE2 has at least 1 routable audio block */ 1584 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1585 if (rdev->mode_info.afmt[0]) { 1586 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0; 1587 rdev->mode_info.afmt[0]->id = 0; 1588 } 1589 /* r6xx has 2 routable audio blocks */ 1590 if (rdev->family >= CHIP_R600) { 1591 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1592 if (rdev->mode_info.afmt[1]) { 1593 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1; 1594 rdev->mode_info.afmt[1]->id = 1; 1595 } 1596 } 1597 } 1598 } 1599 1600 static void radeon_afmt_fini(struct radeon_device *rdev) 1601 { 1602 int i; 1603 1604 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) { 1605 kfree(rdev->mode_info.afmt[i]); 1606 rdev->mode_info.afmt[i] = NULL; 1607 } 1608 } 1609 1610 int radeon_modeset_init(struct radeon_device *rdev) 1611 { 1612 int i; 1613 int ret; 1614 1615 drm_mode_config_init(rdev->ddev); 1616 rdev->mode_info.mode_config_initialized = true; 1617 1618 rdev->ddev->mode_config.funcs = &radeon_mode_funcs; 1619 1620 if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600) 1621 rdev->ddev->mode_config.async_page_flip = true; 1622 1623 if (ASIC_IS_DCE5(rdev)) { 1624 rdev->ddev->mode_config.max_width = 16384; 1625 rdev->ddev->mode_config.max_height = 16384; 1626 } else if (ASIC_IS_AVIVO(rdev)) { 1627 rdev->ddev->mode_config.max_width = 8192; 1628 rdev->ddev->mode_config.max_height = 8192; 1629 } else { 1630 rdev->ddev->mode_config.max_width = 4096; 1631 rdev->ddev->mode_config.max_height = 4096; 1632 } 1633 1634 rdev->ddev->mode_config.preferred_depth = 24; 1635 rdev->ddev->mode_config.prefer_shadow = 1; 1636 1637 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; 1638 1639 ret = radeon_modeset_create_props(rdev); 1640 if (ret) { 1641 return ret; 1642 } 1643 1644 /* init i2c buses */ 1645 radeon_i2c_init(rdev); 1646 1647 /* check combios for a valid hardcoded EDID - Sun servers */ 1648 if (!rdev->is_atom_bios) { 1649 /* check for hardcoded EDID in BIOS */ 1650 radeon_combios_check_hardcoded_edid(rdev); 1651 } 1652 1653 /* allocate crtcs */ 1654 for (i = 0; i < rdev->num_crtc; i++) { 1655 radeon_crtc_init(rdev->ddev, i); 1656 } 1657 1658 /* okay we should have all the bios connectors */ 1659 ret = radeon_setup_enc_conn(rdev->ddev); 1660 if (!ret) { 1661 return ret; 1662 } 1663 1664 /* init dig PHYs, disp eng pll */ 1665 if (rdev->is_atom_bios) { 1666 radeon_atom_encoder_init(rdev); 1667 radeon_atom_disp_eng_pll_init(rdev); 1668 } 1669 1670 /* initialize hpd */ 1671 radeon_hpd_init(rdev); 1672 1673 /* setup afmt */ 1674 radeon_afmt_init(rdev); 1675 1676 radeon_fbdev_init(rdev); 1677 drm_kms_helper_poll_init(rdev->ddev); 1678 1679 /* do pm late init */ 1680 ret = radeon_pm_late_init(rdev); 1681 1682 return 0; 1683 } 1684 1685 void radeon_modeset_fini(struct radeon_device *rdev) 1686 { 1687 if (rdev->mode_info.mode_config_initialized) { 1688 drm_kms_helper_poll_fini(rdev->ddev); 1689 radeon_hpd_fini(rdev); 1690 drm_crtc_force_disable_all(rdev->ddev); 1691 radeon_fbdev_fini(rdev); 1692 radeon_afmt_fini(rdev); 1693 drm_mode_config_cleanup(rdev->ddev); 1694 rdev->mode_info.mode_config_initialized = false; 1695 } 1696 1697 kfree(rdev->mode_info.bios_hardcoded_edid); 1698 1699 /* free i2c buses */ 1700 radeon_i2c_fini(rdev); 1701 } 1702 1703 static bool is_hdtv_mode(const struct drm_display_mode *mode) 1704 { 1705 /* try and guess if this is a tv or a monitor */ 1706 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 1707 (mode->vdisplay == 576) || /* 576p */ 1708 (mode->vdisplay == 720) || /* 720p */ 1709 (mode->vdisplay == 1080)) /* 1080p */ 1710 return true; 1711 else 1712 return false; 1713 } 1714 1715 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 1716 const struct drm_display_mode *mode, 1717 struct drm_display_mode *adjusted_mode) 1718 { 1719 struct drm_device *dev = crtc->dev; 1720 struct radeon_device *rdev = dev->dev_private; 1721 struct drm_encoder *encoder; 1722 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1723 struct radeon_encoder *radeon_encoder; 1724 struct drm_connector *connector; 1725 struct radeon_connector *radeon_connector; 1726 bool first = true; 1727 u32 src_v = 1, dst_v = 1; 1728 u32 src_h = 1, dst_h = 1; 1729 1730 radeon_crtc->h_border = 0; 1731 radeon_crtc->v_border = 0; 1732 1733 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1734 if (encoder->crtc != crtc) 1735 continue; 1736 radeon_encoder = to_radeon_encoder(encoder); 1737 connector = radeon_get_connector_for_encoder(encoder); 1738 radeon_connector = to_radeon_connector(connector); 1739 1740 if (first) { 1741 /* set scaling */ 1742 if (radeon_encoder->rmx_type == RMX_OFF) 1743 radeon_crtc->rmx_type = RMX_OFF; 1744 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || 1745 mode->vdisplay < radeon_encoder->native_mode.vdisplay) 1746 radeon_crtc->rmx_type = radeon_encoder->rmx_type; 1747 else 1748 radeon_crtc->rmx_type = RMX_OFF; 1749 /* copy native mode */ 1750 memcpy(&radeon_crtc->native_mode, 1751 &radeon_encoder->native_mode, 1752 sizeof(struct drm_display_mode)); 1753 src_v = crtc->mode.vdisplay; 1754 dst_v = radeon_crtc->native_mode.vdisplay; 1755 src_h = crtc->mode.hdisplay; 1756 dst_h = radeon_crtc->native_mode.hdisplay; 1757 1758 /* fix up for overscan on hdmi */ 1759 if (ASIC_IS_AVIVO(rdev) && 1760 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 1761 ((radeon_encoder->underscan_type == UNDERSCAN_ON) || 1762 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && 1763 drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 1764 is_hdtv_mode(mode)))) { 1765 if (radeon_encoder->underscan_hborder != 0) 1766 radeon_crtc->h_border = radeon_encoder->underscan_hborder; 1767 else 1768 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; 1769 if (radeon_encoder->underscan_vborder != 0) 1770 radeon_crtc->v_border = radeon_encoder->underscan_vborder; 1771 else 1772 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; 1773 radeon_crtc->rmx_type = RMX_FULL; 1774 src_v = crtc->mode.vdisplay; 1775 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); 1776 src_h = crtc->mode.hdisplay; 1777 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); 1778 } 1779 first = false; 1780 } else { 1781 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { 1782 /* WARNING: Right now this can't happen but 1783 * in the future we need to check that scaling 1784 * are consistent across different encoder 1785 * (ie all encoder can work with the same 1786 * scaling). 1787 */ 1788 DRM_ERROR("Scaling not consistent across encoder.\n"); 1789 return false; 1790 } 1791 } 1792 } 1793 if (radeon_crtc->rmx_type != RMX_OFF) { 1794 fixed20_12 a, b; 1795 a.full = dfixed_const(src_v); 1796 b.full = dfixed_const(dst_v); 1797 radeon_crtc->vsc.full = dfixed_div(a, b); 1798 a.full = dfixed_const(src_h); 1799 b.full = dfixed_const(dst_h); 1800 radeon_crtc->hsc.full = dfixed_div(a, b); 1801 } else { 1802 radeon_crtc->vsc.full = dfixed_const(1); 1803 radeon_crtc->hsc.full = dfixed_const(1); 1804 } 1805 return true; 1806 } 1807 1808 /* 1809 * Retrieve current video scanout position of crtc on a given gpu, and 1810 * an optional accurate timestamp of when query happened. 1811 * 1812 * \param dev Device to query. 1813 * \param crtc Crtc to query. 1814 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 1815 * For driver internal use only also supports these flags: 1816 * 1817 * USE_REAL_VBLANKSTART to use the real start of vblank instead 1818 * of a fudged earlier start of vblank. 1819 * 1820 * GET_DISTANCE_TO_VBLANKSTART to return distance to the 1821 * fudged earlier start of vblank in *vpos and the distance 1822 * to true start of vblank in *hpos. 1823 * 1824 * \param *vpos Location where vertical scanout position should be stored. 1825 * \param *hpos Location where horizontal scanout position should go. 1826 * \param *stime Target location for timestamp taken immediately before 1827 * scanout position query. Can be NULL to skip timestamp. 1828 * \param *etime Target location for timestamp taken immediately after 1829 * scanout position query. Can be NULL to skip timestamp. 1830 * 1831 * Returns vpos as a positive number while in active scanout area. 1832 * Returns vpos as a negative number inside vblank, counting the number 1833 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 1834 * until start of active scanout / end of vblank." 1835 * 1836 * \return Flags, or'ed together as follows: 1837 * 1838 * DRM_SCANOUTPOS_VALID = Query successful. 1839 * DRM_SCANOUTPOS_INVBL = Inside vblank. 1840 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 1841 * this flag means that returned position may be offset by a constant but 1842 * unknown small number of scanlines wrt. real scanout position. 1843 * 1844 */ 1845 int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 1846 unsigned int flags, int *vpos, int *hpos, 1847 ktime_t *stime, ktime_t *etime, 1848 const struct drm_display_mode *mode) 1849 { 1850 u32 stat_crtc = 0, vbl = 0, position = 0; 1851 int vbl_start, vbl_end, vtotal, ret = 0; 1852 bool in_vbl = true; 1853 1854 struct radeon_device *rdev = dev->dev_private; 1855 1856 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 1857 1858 /* Get optional system timestamp before query. */ 1859 if (stime) 1860 *stime = ktime_get(); 1861 1862 if (ASIC_IS_DCE4(rdev)) { 1863 if (pipe == 0) { 1864 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1865 EVERGREEN_CRTC0_REGISTER_OFFSET); 1866 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1867 EVERGREEN_CRTC0_REGISTER_OFFSET); 1868 ret |= DRM_SCANOUTPOS_VALID; 1869 } 1870 if (pipe == 1) { 1871 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1872 EVERGREEN_CRTC1_REGISTER_OFFSET); 1873 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1874 EVERGREEN_CRTC1_REGISTER_OFFSET); 1875 ret |= DRM_SCANOUTPOS_VALID; 1876 } 1877 if (pipe == 2) { 1878 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1879 EVERGREEN_CRTC2_REGISTER_OFFSET); 1880 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1881 EVERGREEN_CRTC2_REGISTER_OFFSET); 1882 ret |= DRM_SCANOUTPOS_VALID; 1883 } 1884 if (pipe == 3) { 1885 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1886 EVERGREEN_CRTC3_REGISTER_OFFSET); 1887 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1888 EVERGREEN_CRTC3_REGISTER_OFFSET); 1889 ret |= DRM_SCANOUTPOS_VALID; 1890 } 1891 if (pipe == 4) { 1892 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1893 EVERGREEN_CRTC4_REGISTER_OFFSET); 1894 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1895 EVERGREEN_CRTC4_REGISTER_OFFSET); 1896 ret |= DRM_SCANOUTPOS_VALID; 1897 } 1898 if (pipe == 5) { 1899 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1900 EVERGREEN_CRTC5_REGISTER_OFFSET); 1901 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1902 EVERGREEN_CRTC5_REGISTER_OFFSET); 1903 ret |= DRM_SCANOUTPOS_VALID; 1904 } 1905 } else if (ASIC_IS_AVIVO(rdev)) { 1906 if (pipe == 0) { 1907 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); 1908 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); 1909 ret |= DRM_SCANOUTPOS_VALID; 1910 } 1911 if (pipe == 1) { 1912 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); 1913 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); 1914 ret |= DRM_SCANOUTPOS_VALID; 1915 } 1916 } else { 1917 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ 1918 if (pipe == 0) { 1919 /* Assume vbl_end == 0, get vbl_start from 1920 * upper 16 bits. 1921 */ 1922 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & 1923 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1924 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ 1925 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1926 stat_crtc = RREG32(RADEON_CRTC_STATUS); 1927 if (!(stat_crtc & 1)) 1928 in_vbl = false; 1929 1930 ret |= DRM_SCANOUTPOS_VALID; 1931 } 1932 if (pipe == 1) { 1933 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & 1934 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1935 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1936 stat_crtc = RREG32(RADEON_CRTC2_STATUS); 1937 if (!(stat_crtc & 1)) 1938 in_vbl = false; 1939 1940 ret |= DRM_SCANOUTPOS_VALID; 1941 } 1942 } 1943 1944 /* Get optional system timestamp after query. */ 1945 if (etime) 1946 *etime = ktime_get(); 1947 1948 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 1949 1950 /* Decode into vertical and horizontal scanout position. */ 1951 *vpos = position & 0x1fff; 1952 *hpos = (position >> 16) & 0x1fff; 1953 1954 /* Valid vblank area boundaries from gpu retrieved? */ 1955 if (vbl > 0) { 1956 /* Yes: Decode. */ 1957 ret |= DRM_SCANOUTPOS_ACCURATE; 1958 vbl_start = vbl & 0x1fff; 1959 vbl_end = (vbl >> 16) & 0x1fff; 1960 } 1961 else { 1962 /* No: Fake something reasonable which gives at least ok results. */ 1963 vbl_start = mode->crtc_vdisplay; 1964 vbl_end = 0; 1965 } 1966 1967 /* Called from driver internal vblank counter query code? */ 1968 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1969 /* Caller wants distance from real vbl_start in *hpos */ 1970 *hpos = *vpos - vbl_start; 1971 } 1972 1973 /* Fudge vblank to start a few scanlines earlier to handle the 1974 * problem that vblank irqs fire a few scanlines before start 1975 * of vblank. Some driver internal callers need the true vblank 1976 * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 1977 * 1978 * The cause of the "early" vblank irq is that the irq is triggered 1979 * by the line buffer logic when the line buffer read position enters 1980 * the vblank, whereas our crtc scanout position naturally lags the 1981 * line buffer read position. 1982 */ 1983 if (!(flags & USE_REAL_VBLANKSTART)) 1984 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 1985 1986 /* Test scanout position against vblank region. */ 1987 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 1988 in_vbl = false; 1989 1990 /* In vblank? */ 1991 if (in_vbl) 1992 ret |= DRM_SCANOUTPOS_IN_VBLANK; 1993 1994 /* Called from driver internal vblank counter query code? */ 1995 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1996 /* Caller wants distance from fudged earlier vbl_start */ 1997 *vpos -= vbl_start; 1998 return ret; 1999 } 2000 2001 /* Check if inside vblank area and apply corrective offsets: 2002 * vpos will then be >=0 in video scanout area, but negative 2003 * within vblank area, counting down the number of lines until 2004 * start of scanout. 2005 */ 2006 2007 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 2008 if (in_vbl && (*vpos >= vbl_start)) { 2009 vtotal = mode->crtc_vtotal; 2010 *vpos = *vpos - vtotal; 2011 } 2012 2013 /* Correct for shifted end of vbl at vbl_end. */ 2014 *vpos = *vpos - vbl_end; 2015 2016 return ret; 2017 } 2018