1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/radeon_drm.h> 28 #include "radeon.h" 29 30 #include "atom.h" 31 32 #include <linux/pm_runtime.h> 33 #include <drm/drm_crtc_helper.h> 34 #include <drm/drm_plane_helper.h> 35 #include <drm/drm_edid.h> 36 37 #include <linux/gcd.h> 38 39 static void avivo_crtc_load_lut(struct drm_crtc *crtc) 40 { 41 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 42 struct drm_device *dev = crtc->dev; 43 struct radeon_device *rdev = dev->dev_private; 44 int i; 45 46 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 47 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); 48 49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 52 53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 56 57 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); 58 WREG32(AVIVO_DC_LUT_RW_MODE, 0); 59 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); 60 61 WREG8(AVIVO_DC_LUT_RW_INDEX, 0); 62 for (i = 0; i < 256; i++) { 63 WREG32(AVIVO_DC_LUT_30_COLOR, 64 (radeon_crtc->lut_r[i] << 20) | 65 (radeon_crtc->lut_g[i] << 10) | 66 (radeon_crtc->lut_b[i] << 0)); 67 } 68 69 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */ 70 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1); 71 } 72 73 static void dce4_crtc_load_lut(struct drm_crtc *crtc) 74 { 75 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 76 struct drm_device *dev = crtc->dev; 77 struct radeon_device *rdev = dev->dev_private; 78 int i; 79 80 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 81 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 82 83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 84 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 85 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 86 87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 88 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 89 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 90 91 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 92 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 93 94 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 95 for (i = 0; i < 256; i++) { 96 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 97 (radeon_crtc->lut_r[i] << 20) | 98 (radeon_crtc->lut_g[i] << 10) | 99 (radeon_crtc->lut_b[i] << 0)); 100 } 101 } 102 103 static void dce5_crtc_load_lut(struct drm_crtc *crtc) 104 { 105 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 106 struct drm_device *dev = crtc->dev; 107 struct radeon_device *rdev = dev->dev_private; 108 int i; 109 110 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 111 112 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 113 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | 114 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); 115 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, 116 NI_GRPH_PRESCALE_BYPASS); 117 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, 118 NI_OVL_PRESCALE_BYPASS); 119 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, 120 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | 121 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); 122 123 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 124 125 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 126 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 127 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 128 129 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 130 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 131 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 132 133 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 134 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 135 136 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 137 for (i = 0; i < 256; i++) { 138 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 139 (radeon_crtc->lut_r[i] << 20) | 140 (radeon_crtc->lut_g[i] << 10) | 141 (radeon_crtc->lut_b[i] << 0)); 142 } 143 144 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, 145 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 146 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 147 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 148 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); 149 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, 150 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | 151 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); 152 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, 153 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | 154 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); 155 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 156 (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) | 157 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); 158 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 159 WREG32(0x6940 + radeon_crtc->crtc_offset, 0); 160 if (ASIC_IS_DCE8(rdev)) { 161 /* XXX this only needs to be programmed once per crtc at startup, 162 * not sure where the best place for it is 163 */ 164 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset, 165 CIK_CURSOR_ALPHA_BLND_ENA); 166 } 167 } 168 169 static void legacy_crtc_load_lut(struct drm_crtc *crtc) 170 { 171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 172 struct drm_device *dev = crtc->dev; 173 struct radeon_device *rdev = dev->dev_private; 174 int i; 175 uint32_t dac2_cntl; 176 177 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 178 if (radeon_crtc->crtc_id == 0) 179 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; 180 else 181 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; 182 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 183 184 WREG8(RADEON_PALETTE_INDEX, 0); 185 for (i = 0; i < 256; i++) { 186 WREG32(RADEON_PALETTE_30_DATA, 187 (radeon_crtc->lut_r[i] << 20) | 188 (radeon_crtc->lut_g[i] << 10) | 189 (radeon_crtc->lut_b[i] << 0)); 190 } 191 } 192 193 void radeon_crtc_load_lut(struct drm_crtc *crtc) 194 { 195 struct drm_device *dev = crtc->dev; 196 struct radeon_device *rdev = dev->dev_private; 197 198 if (!crtc->enabled) 199 return; 200 201 if (ASIC_IS_DCE5(rdev)) 202 dce5_crtc_load_lut(crtc); 203 else if (ASIC_IS_DCE4(rdev)) 204 dce4_crtc_load_lut(crtc); 205 else if (ASIC_IS_AVIVO(rdev)) 206 avivo_crtc_load_lut(crtc); 207 else 208 legacy_crtc_load_lut(crtc); 209 } 210 211 /** Sets the color ramps on behalf of fbcon */ 212 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 213 u16 blue, int regno) 214 { 215 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 216 217 radeon_crtc->lut_r[regno] = red >> 6; 218 radeon_crtc->lut_g[regno] = green >> 6; 219 radeon_crtc->lut_b[regno] = blue >> 6; 220 } 221 222 /** Gets the color ramps on behalf of fbcon */ 223 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 224 u16 *blue, int regno) 225 { 226 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 227 228 *red = radeon_crtc->lut_r[regno] << 6; 229 *green = radeon_crtc->lut_g[regno] << 6; 230 *blue = radeon_crtc->lut_b[regno] << 6; 231 } 232 233 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 234 u16 *blue, uint32_t start, uint32_t size) 235 { 236 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 237 int end = (start + size > 256) ? 256 : start + size, i; 238 239 /* userspace palettes are always correct as is */ 240 for (i = start; i < end; i++) { 241 radeon_crtc->lut_r[i] = red[i] >> 6; 242 radeon_crtc->lut_g[i] = green[i] >> 6; 243 radeon_crtc->lut_b[i] = blue[i] >> 6; 244 } 245 radeon_crtc_load_lut(crtc); 246 } 247 248 static void radeon_crtc_destroy(struct drm_crtc *crtc) 249 { 250 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 251 252 drm_crtc_cleanup(crtc); 253 destroy_workqueue(radeon_crtc->flip_queue); 254 kfree(radeon_crtc); 255 } 256 257 /** 258 * radeon_unpin_work_func - unpin old buffer object 259 * 260 * @__work - kernel work item 261 * 262 * Unpin the old frame buffer object outside of the interrupt handler 263 */ 264 static void radeon_unpin_work_func(struct work_struct *__work) 265 { 266 struct radeon_flip_work *work = 267 container_of(__work, struct radeon_flip_work, unpin_work); 268 int r; 269 270 /* unpin of the old buffer */ 271 r = radeon_bo_reserve(work->old_rbo, false); 272 if (likely(r == 0)) { 273 r = radeon_bo_unpin(work->old_rbo); 274 if (unlikely(r != 0)) { 275 DRM_ERROR("failed to unpin buffer after flip\n"); 276 } 277 radeon_bo_unreserve(work->old_rbo); 278 } else 279 DRM_ERROR("failed to reserve buffer after flip\n"); 280 281 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 282 kfree(work); 283 } 284 285 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id) 286 { 287 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 288 unsigned long flags; 289 u32 update_pending; 290 int vpos, hpos; 291 292 /* can happen during initialization */ 293 if (radeon_crtc == NULL) 294 return; 295 296 /* Skip the pageflip completion check below (based on polling) on 297 * asics which reliably support hw pageflip completion irqs. pflip 298 * irqs are a reliable and race-free method of handling pageflip 299 * completion detection. A use_pflipirq module parameter < 2 allows 300 * to override this in case of asics with faulty pflip irqs. 301 * A module parameter of 0 would only use this polling based path, 302 * a parameter of 1 would use pflip irq only as a backup to this 303 * path, as in Linux 3.16. 304 */ 305 if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev)) 306 return; 307 308 spin_lock_irqsave(&rdev->ddev->event_lock, flags); 309 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 310 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 311 "RADEON_FLIP_SUBMITTED(%d)\n", 312 radeon_crtc->flip_status, 313 RADEON_FLIP_SUBMITTED); 314 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 315 return; 316 } 317 318 update_pending = radeon_page_flip_pending(rdev, crtc_id); 319 320 /* Has the pageflip already completed in crtc, or is it certain 321 * to complete in this vblank? 322 */ 323 if (update_pending && 324 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, 325 crtc_id, 326 USE_REAL_VBLANKSTART, 327 &vpos, &hpos, NULL, NULL, 328 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) && 329 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) || 330 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) { 331 /* crtc didn't flip in this target vblank interval, 332 * but flip is pending in crtc. Based on the current 333 * scanout position we know that the current frame is 334 * (nearly) complete and the flip will (likely) 335 * complete before the start of the next frame. 336 */ 337 update_pending = 0; 338 } 339 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 340 if (!update_pending) 341 radeon_crtc_handle_flip(rdev, crtc_id); 342 } 343 344 /** 345 * radeon_crtc_handle_flip - page flip completed 346 * 347 * @rdev: radeon device pointer 348 * @crtc_id: crtc number this event is for 349 * 350 * Called when we are sure that a page flip for this crtc is completed. 351 */ 352 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) 353 { 354 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 355 struct radeon_flip_work *work; 356 unsigned long flags; 357 358 /* this can happen at init */ 359 if (radeon_crtc == NULL) 360 return; 361 362 spin_lock_irqsave(&rdev->ddev->event_lock, flags); 363 work = radeon_crtc->flip_work; 364 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 365 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 366 "RADEON_FLIP_SUBMITTED(%d)\n", 367 radeon_crtc->flip_status, 368 RADEON_FLIP_SUBMITTED); 369 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 370 return; 371 } 372 373 /* Pageflip completed. Clean up. */ 374 radeon_crtc->flip_status = RADEON_FLIP_NONE; 375 radeon_crtc->flip_work = NULL; 376 377 /* wakeup userspace */ 378 if (work->event) 379 drm_send_vblank_event(rdev->ddev, crtc_id, work->event); 380 381 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 382 383 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id); 384 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id); 385 queue_work(radeon_crtc->flip_queue, &work->unpin_work); 386 } 387 388 /** 389 * radeon_flip_work_func - page flip framebuffer 390 * 391 * @work - kernel work item 392 * 393 * Wait for the buffer object to become idle and do the actual page flip 394 */ 395 static void radeon_flip_work_func(struct work_struct *__work) 396 { 397 struct radeon_flip_work *work = 398 container_of(__work, struct radeon_flip_work, flip_work); 399 struct radeon_device *rdev = work->rdev; 400 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id]; 401 402 struct drm_crtc *crtc = &radeon_crtc->base; 403 unsigned long flags; 404 int r; 405 int vpos, hpos, stat, min_udelay = 0; 406 unsigned repcnt = 4; 407 struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id]; 408 409 down_read(&rdev->exclusive_lock); 410 if (work->fence) { 411 struct radeon_fence *fence; 412 413 fence = to_radeon_fence(work->fence); 414 if (fence && fence->rdev == rdev) { 415 r = radeon_fence_wait(fence, false); 416 if (r == -EDEADLK) { 417 up_read(&rdev->exclusive_lock); 418 do { 419 r = radeon_gpu_reset(rdev); 420 } while (r == -EAGAIN); 421 down_read(&rdev->exclusive_lock); 422 } 423 } else 424 r = fence_wait(work->fence, false); 425 426 if (r) 427 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r); 428 429 /* We continue with the page flip even if we failed to wait on 430 * the fence, otherwise the DRM core and userspace will be 431 * confused about which BO the CRTC is scanning out 432 */ 433 434 fence_put(work->fence); 435 work->fence = NULL; 436 } 437 438 /* We borrow the event spin lock for protecting flip_status */ 439 spin_lock_irqsave(&crtc->dev->event_lock, flags); 440 441 /* set the proper interrupt */ 442 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id); 443 444 /* If this happens to execute within the "virtually extended" vblank 445 * interval before the start of the real vblank interval then it needs 446 * to delay programming the mmio flip until the real vblank is entered. 447 * This prevents completing a flip too early due to the way we fudge 448 * our vblank counter and vblank timestamps in order to work around the 449 * problem that the hw fires vblank interrupts before actual start of 450 * vblank (when line buffer refilling is done for a frame). It 451 * complements the fudging logic in radeon_get_crtc_scanoutpos() for 452 * timestamping and radeon_get_vblank_counter_kms() for vblank counts. 453 * 454 * In practice this won't execute very often unless on very fast 455 * machines because the time window for this to happen is very small. 456 */ 457 while (radeon_crtc->enabled && --repcnt) { 458 /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank 459 * start in hpos, and to the "fudged earlier" vblank start in 460 * vpos. 461 */ 462 stat = radeon_get_crtc_scanoutpos(rdev->ddev, work->crtc_id, 463 GET_DISTANCE_TO_VBLANKSTART, 464 &vpos, &hpos, NULL, NULL, 465 &crtc->hwmode); 466 467 if ((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 468 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE) || 469 !(vpos >= 0 && hpos <= 0)) 470 break; 471 472 /* Sleep at least until estimated real start of hw vblank */ 473 min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5); 474 if (min_udelay > vblank->framedur_ns / 2000) { 475 /* Don't wait ridiculously long - something is wrong */ 476 repcnt = 0; 477 break; 478 } 479 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 480 usleep_range(min_udelay, 2 * min_udelay); 481 spin_lock_irqsave(&crtc->dev->event_lock, flags); 482 }; 483 484 if (!repcnt) 485 DRM_DEBUG_DRIVER("Delay problem on crtc %d: min_udelay %d, " 486 "framedur %d, linedur %d, stat %d, vpos %d, " 487 "hpos %d\n", work->crtc_id, min_udelay, 488 vblank->framedur_ns / 1000, 489 vblank->linedur_ns / 1000, stat, vpos, hpos); 490 491 /* do the flip (mmio) */ 492 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base); 493 494 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED; 495 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 496 up_read(&rdev->exclusive_lock); 497 } 498 499 static int radeon_crtc_page_flip(struct drm_crtc *crtc, 500 struct drm_framebuffer *fb, 501 struct drm_pending_vblank_event *event, 502 uint32_t page_flip_flags) 503 { 504 struct drm_device *dev = crtc->dev; 505 struct radeon_device *rdev = dev->dev_private; 506 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 507 struct radeon_framebuffer *old_radeon_fb; 508 struct radeon_framebuffer *new_radeon_fb; 509 struct drm_gem_object *obj; 510 struct radeon_flip_work *work; 511 struct radeon_bo *new_rbo; 512 uint32_t tiling_flags, pitch_pixels; 513 uint64_t base; 514 unsigned long flags; 515 int r; 516 517 work = kzalloc(sizeof *work, GFP_KERNEL); 518 if (work == NULL) 519 return -ENOMEM; 520 521 INIT_WORK(&work->flip_work, radeon_flip_work_func); 522 INIT_WORK(&work->unpin_work, radeon_unpin_work_func); 523 524 work->rdev = rdev; 525 work->crtc_id = radeon_crtc->crtc_id; 526 work->event = event; 527 528 /* schedule unpin of the old buffer */ 529 old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb); 530 obj = old_radeon_fb->obj; 531 532 /* take a reference to the old object */ 533 drm_gem_object_reference(obj); 534 work->old_rbo = gem_to_radeon_bo(obj); 535 536 new_radeon_fb = to_radeon_framebuffer(fb); 537 obj = new_radeon_fb->obj; 538 new_rbo = gem_to_radeon_bo(obj); 539 540 /* pin the new buffer */ 541 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n", 542 work->old_rbo, new_rbo); 543 544 r = radeon_bo_reserve(new_rbo, false); 545 if (unlikely(r != 0)) { 546 DRM_ERROR("failed to reserve new rbo buffer before flip\n"); 547 goto cleanup; 548 } 549 /* Only 27 bit offset for legacy CRTC */ 550 r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM, 551 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, (u64 *)&base); 552 if (unlikely(r != 0)) { 553 radeon_bo_unreserve(new_rbo); 554 r = -EINVAL; 555 DRM_ERROR("failed to pin new rbo buffer before flip\n"); 556 goto cleanup; 557 } 558 work->fence = fence_get(reservation_object_get_excl(new_rbo->tbo.resv)); 559 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); 560 radeon_bo_unreserve(new_rbo); 561 562 if (!ASIC_IS_AVIVO(rdev)) { 563 /* crtc offset is from display base addr not FB location */ 564 base -= radeon_crtc->legacy_display_base_addr; 565 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8); 566 567 if (tiling_flags & RADEON_TILING_MACRO) { 568 if (ASIC_IS_R300(rdev)) { 569 base &= ~0x7ff; 570 } else { 571 int byteshift = fb->bits_per_pixel >> 4; 572 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11; 573 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8); 574 } 575 } else { 576 int offset = crtc->y * pitch_pixels + crtc->x; 577 switch (fb->bits_per_pixel) { 578 case 8: 579 default: 580 offset *= 1; 581 break; 582 case 15: 583 case 16: 584 offset *= 2; 585 break; 586 case 24: 587 offset *= 3; 588 break; 589 case 32: 590 offset *= 4; 591 break; 592 } 593 base += offset; 594 } 595 base &= ~7; 596 } 597 work->base = base; 598 599 r = drm_vblank_get(crtc->dev, radeon_crtc->crtc_id); 600 if (r) { 601 DRM_ERROR("failed to get vblank before flip\n"); 602 goto pflip_cleanup; 603 } 604 605 /* We borrow the event spin lock for protecting flip_work */ 606 spin_lock_irqsave(&crtc->dev->event_lock, flags); 607 608 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) { 609 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 610 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 611 r = -EBUSY; 612 goto vblank_cleanup; 613 } 614 radeon_crtc->flip_status = RADEON_FLIP_PENDING; 615 radeon_crtc->flip_work = work; 616 617 /* update crtc fb */ 618 crtc->primary->fb = fb; 619 620 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 621 622 queue_work(radeon_crtc->flip_queue, &work->flip_work); 623 return 0; 624 625 vblank_cleanup: 626 drm_vblank_put(crtc->dev, radeon_crtc->crtc_id); 627 628 pflip_cleanup: 629 if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) { 630 DRM_ERROR("failed to reserve new rbo in error path\n"); 631 goto cleanup; 632 } 633 if (unlikely(radeon_bo_unpin(new_rbo) != 0)) { 634 DRM_ERROR("failed to unpin new rbo in error path\n"); 635 } 636 radeon_bo_unreserve(new_rbo); 637 638 cleanup: 639 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 640 fence_put(work->fence); 641 kfree(work); 642 return r; 643 } 644 645 static int 646 radeon_crtc_set_config(struct drm_mode_set *set) 647 { 648 struct drm_device *dev; 649 struct radeon_device *rdev; 650 struct drm_crtc *crtc; 651 bool active = false; 652 int ret; 653 654 if (!set || !set->crtc) 655 return -EINVAL; 656 657 dev = set->crtc->dev; 658 659 #ifdef PM_TODO 660 ret = pm_runtime_get_sync(dev->dev); 661 if (ret < 0) 662 return ret; 663 #endif 664 665 ret = drm_crtc_helper_set_config(set); 666 667 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 668 if (crtc->enabled) 669 active = true; 670 671 #ifdef PM_TODO 672 pm_runtime_mark_last_busy(dev->dev); 673 #endif 674 675 rdev = dev->dev_private; 676 /* if we have active crtcs and we don't have a power ref, 677 take the current one */ 678 if (active && !rdev->have_disp_power_ref) { 679 rdev->have_disp_power_ref = true; 680 return ret; 681 } 682 /* if we have no active crtcs, then drop the power ref 683 we got before */ 684 if (!active && rdev->have_disp_power_ref) { 685 #ifdef PM_TODO 686 pm_runtime_put_autosuspend(dev->dev); 687 #endif 688 rdev->have_disp_power_ref = false; 689 } 690 691 /* drop the power reference we got coming in here */ 692 #ifdef PM_TODO 693 pm_runtime_put_autosuspend(dev->dev); 694 #endif 695 return ret; 696 } 697 static const struct drm_crtc_funcs radeon_crtc_funcs = { 698 .cursor_set2 = radeon_crtc_cursor_set2, 699 .cursor_move = radeon_crtc_cursor_move, 700 .gamma_set = radeon_crtc_gamma_set, 701 .set_config = radeon_crtc_set_config, 702 .destroy = radeon_crtc_destroy, 703 .page_flip = radeon_crtc_page_flip, 704 }; 705 706 static void radeon_crtc_init(struct drm_device *dev, int index) 707 { 708 struct radeon_device *rdev = dev->dev_private; 709 struct radeon_crtc *radeon_crtc; 710 int i; 711 712 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 713 if (radeon_crtc == NULL) 714 return; 715 716 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); 717 718 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); 719 radeon_crtc->crtc_id = index; 720 radeon_crtc->flip_queue = create_singlethread_workqueue("radeon-crtc"); 721 rdev->mode_info.crtcs[index] = radeon_crtc; 722 723 if (rdev->family >= CHIP_BONAIRE) { 724 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH; 725 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT; 726 } else { 727 radeon_crtc->max_cursor_width = CURSOR_WIDTH; 728 radeon_crtc->max_cursor_height = CURSOR_HEIGHT; 729 } 730 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width; 731 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height; 732 733 #if 0 734 radeon_crtc->mode_set.crtc = &radeon_crtc->base; 735 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); 736 radeon_crtc->mode_set.num_connectors = 0; 737 #endif 738 739 for (i = 0; i < 256; i++) { 740 radeon_crtc->lut_r[i] = i << 2; 741 radeon_crtc->lut_g[i] = i << 2; 742 radeon_crtc->lut_b[i] = i << 2; 743 } 744 745 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) 746 radeon_atombios_init_crtc(dev, radeon_crtc); 747 else 748 radeon_legacy_init_crtc(dev, radeon_crtc); 749 } 750 751 static const char *encoder_names[38] = { 752 "NONE", 753 "INTERNAL_LVDS", 754 "INTERNAL_TMDS1", 755 "INTERNAL_TMDS2", 756 "INTERNAL_DAC1", 757 "INTERNAL_DAC2", 758 "INTERNAL_SDVOA", 759 "INTERNAL_SDVOB", 760 "SI170B", 761 "CH7303", 762 "CH7301", 763 "INTERNAL_DVO1", 764 "EXTERNAL_SDVOA", 765 "EXTERNAL_SDVOB", 766 "TITFP513", 767 "INTERNAL_LVTM1", 768 "VT1623", 769 "HDMI_SI1930", 770 "HDMI_INTERNAL", 771 "INTERNAL_KLDSCP_TMDS1", 772 "INTERNAL_KLDSCP_DVO1", 773 "INTERNAL_KLDSCP_DAC1", 774 "INTERNAL_KLDSCP_DAC2", 775 "SI178", 776 "MVPU_FPGA", 777 "INTERNAL_DDI", 778 "VT1625", 779 "HDMI_SI1932", 780 "DP_AN9801", 781 "DP_DP501", 782 "INTERNAL_UNIPHY", 783 "INTERNAL_KLDSCP_LVTMA", 784 "INTERNAL_UNIPHY1", 785 "INTERNAL_UNIPHY2", 786 "NUTMEG", 787 "TRAVIS", 788 "INTERNAL_VCE", 789 "INTERNAL_UNIPHY3", 790 }; 791 792 static const char *hpd_names[6] = { 793 "HPD1", 794 "HPD2", 795 "HPD3", 796 "HPD4", 797 "HPD5", 798 "HPD6", 799 }; 800 801 static void radeon_print_display_setup(struct drm_device *dev) 802 { 803 struct drm_connector *connector; 804 struct radeon_connector *radeon_connector; 805 struct drm_encoder *encoder; 806 struct radeon_encoder *radeon_encoder; 807 uint32_t devices; 808 int i = 0; 809 810 DRM_INFO("Radeon Display Connectors\n"); 811 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 812 radeon_connector = to_radeon_connector(connector); 813 DRM_INFO("Connector %d:\n", i); 814 DRM_INFO(" %s\n", connector->name); 815 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 816 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); 817 if (radeon_connector->ddc_bus) { 818 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 819 radeon_connector->ddc_bus->rec.mask_clk_reg, 820 radeon_connector->ddc_bus->rec.mask_data_reg, 821 radeon_connector->ddc_bus->rec.a_clk_reg, 822 radeon_connector->ddc_bus->rec.a_data_reg, 823 radeon_connector->ddc_bus->rec.en_clk_reg, 824 radeon_connector->ddc_bus->rec.en_data_reg, 825 radeon_connector->ddc_bus->rec.y_clk_reg, 826 radeon_connector->ddc_bus->rec.y_data_reg); 827 if (radeon_connector->router.ddc_valid) 828 DRM_INFO(" DDC Router 0x%x/0x%x\n", 829 radeon_connector->router.ddc_mux_control_pin, 830 radeon_connector->router.ddc_mux_state); 831 if (radeon_connector->router.cd_valid) 832 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 833 radeon_connector->router.cd_mux_control_pin, 834 radeon_connector->router.cd_mux_state); 835 } else { 836 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 837 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 838 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 839 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 840 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 841 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 842 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 843 } 844 DRM_INFO(" Encoders:\n"); 845 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 846 radeon_encoder = to_radeon_encoder(encoder); 847 devices = radeon_encoder->devices & radeon_connector->devices; 848 if (devices) { 849 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 850 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); 851 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 852 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); 853 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 854 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); 855 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 856 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); 857 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 858 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); 859 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 860 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); 861 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 862 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); 863 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 864 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); 865 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 866 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); 867 if (devices & ATOM_DEVICE_TV1_SUPPORT) 868 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); 869 if (devices & ATOM_DEVICE_CV_SUPPORT) 870 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); 871 } 872 } 873 i++; 874 } 875 } 876 877 static bool radeon_setup_enc_conn(struct drm_device *dev) 878 { 879 struct radeon_device *rdev = dev->dev_private; 880 bool ret = false; 881 882 if (rdev->bios) { 883 if (rdev->is_atom_bios) { 884 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); 885 if (ret == false) 886 ret = radeon_get_atom_connector_info_from_object_table(dev); 887 } else { 888 ret = radeon_get_legacy_connector_info_from_bios(dev); 889 if (ret == false) 890 ret = radeon_get_legacy_connector_info_from_table(dev); 891 } 892 } else { 893 if (!ASIC_IS_AVIVO(rdev)) 894 ret = radeon_get_legacy_connector_info_from_table(dev); 895 } 896 if (ret) { 897 radeon_setup_encoder_clones(dev); 898 radeon_print_display_setup(dev); 899 } 900 901 return ret; 902 } 903 904 /* avivo */ 905 906 /** 907 * avivo_reduce_ratio - fractional number reduction 908 * 909 * @nom: nominator 910 * @den: denominator 911 * @nom_min: minimum value for nominator 912 * @den_min: minimum value for denominator 913 * 914 * Find the greatest common divisor and apply it on both nominator and 915 * denominator, but make nominator and denominator are at least as large 916 * as their minimum values. 917 */ 918 static void avivo_reduce_ratio(unsigned *nom, unsigned *den, 919 unsigned nom_min, unsigned den_min) 920 { 921 unsigned tmp; 922 923 /* reduce the numbers to a simpler ratio */ 924 tmp = gcd(*nom, *den); 925 *nom /= tmp; 926 *den /= tmp; 927 928 /* make sure nominator is large enough */ 929 if (*nom < nom_min) { 930 tmp = DIV_ROUND_UP(nom_min, *nom); 931 *nom *= tmp; 932 *den *= tmp; 933 } 934 935 /* make sure the denominator is large enough */ 936 if (*den < den_min) { 937 tmp = DIV_ROUND_UP(den_min, *den); 938 *nom *= tmp; 939 *den *= tmp; 940 } 941 } 942 943 /** 944 * avivo_get_fb_ref_div - feedback and ref divider calculation 945 * 946 * @nom: nominator 947 * @den: denominator 948 * @post_div: post divider 949 * @fb_div_max: feedback divider maximum 950 * @ref_div_max: reference divider maximum 951 * @fb_div: resulting feedback divider 952 * @ref_div: resulting reference divider 953 * 954 * Calculate feedback and reference divider for a given post divider. Makes 955 * sure we stay within the limits. 956 */ 957 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, 958 unsigned fb_div_max, unsigned ref_div_max, 959 unsigned *fb_div, unsigned *ref_div) 960 { 961 /* limit reference * post divider to a maximum */ 962 ref_div_max = max(min(100 / post_div, ref_div_max), 1u); 963 964 /* get matching reference and feedback divider */ 965 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); 966 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); 967 968 /* limit fb divider to its maximum */ 969 if (*fb_div > fb_div_max) { 970 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); 971 *fb_div = fb_div_max; 972 } 973 } 974 975 /** 976 * radeon_compute_pll_avivo - compute PLL paramaters 977 * 978 * @pll: information about the PLL 979 * @dot_clock_p: resulting pixel clock 980 * fb_div_p: resulting feedback divider 981 * frac_fb_div_p: fractional part of the feedback divider 982 * ref_div_p: resulting reference divider 983 * post_div_p: resulting reference divider 984 * 985 * Try to calculate the PLL parameters to generate the given frequency: 986 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div) 987 */ 988 void radeon_compute_pll_avivo(struct radeon_pll *pll, 989 u32 freq, 990 u32 *dot_clock_p, 991 u32 *fb_div_p, 992 u32 *frac_fb_div_p, 993 u32 *ref_div_p, 994 u32 *post_div_p) 995 { 996 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? 997 freq : freq / 10; 998 999 unsigned fb_div_min, fb_div_max, fb_div; 1000 unsigned post_div_min, post_div_max, post_div; 1001 unsigned ref_div_min, ref_div_max, ref_div; 1002 unsigned post_div_best, diff_best; 1003 unsigned nom, den; 1004 1005 /* determine allowed feedback divider range */ 1006 fb_div_min = pll->min_feedback_div; 1007 fb_div_max = pll->max_feedback_div; 1008 1009 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1010 fb_div_min *= 10; 1011 fb_div_max *= 10; 1012 } 1013 1014 /* determine allowed ref divider range */ 1015 if (pll->flags & RADEON_PLL_USE_REF_DIV) 1016 ref_div_min = pll->reference_div; 1017 else 1018 ref_div_min = pll->min_ref_div; 1019 1020 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && 1021 pll->flags & RADEON_PLL_USE_REF_DIV) 1022 ref_div_max = pll->reference_div; 1023 else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 1024 /* fix for problems on RS880 */ 1025 ref_div_max = min(pll->max_ref_div, 7u); 1026 else 1027 ref_div_max = pll->max_ref_div; 1028 1029 /* determine allowed post divider range */ 1030 if (pll->flags & RADEON_PLL_USE_POST_DIV) { 1031 post_div_min = pll->post_div; 1032 post_div_max = pll->post_div; 1033 } else { 1034 unsigned vco_min, vco_max; 1035 1036 if (pll->flags & RADEON_PLL_IS_LCD) { 1037 vco_min = pll->lcd_pll_out_min; 1038 vco_max = pll->lcd_pll_out_max; 1039 } else { 1040 vco_min = pll->pll_out_min; 1041 vco_max = pll->pll_out_max; 1042 } 1043 1044 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1045 vco_min *= 10; 1046 vco_max *= 10; 1047 } 1048 1049 post_div_min = vco_min / target_clock; 1050 if ((target_clock * post_div_min) < vco_min) 1051 ++post_div_min; 1052 if (post_div_min < pll->min_post_div) 1053 post_div_min = pll->min_post_div; 1054 1055 post_div_max = vco_max / target_clock; 1056 if ((target_clock * post_div_max) > vco_max) 1057 --post_div_max; 1058 if (post_div_max > pll->max_post_div) 1059 post_div_max = pll->max_post_div; 1060 } 1061 1062 /* represent the searched ratio as fractional number */ 1063 nom = target_clock; 1064 den = pll->reference_freq; 1065 1066 /* reduce the numbers to a simpler ratio */ 1067 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min); 1068 1069 /* now search for a post divider */ 1070 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 1071 post_div_best = post_div_min; 1072 else 1073 post_div_best = post_div_max; 1074 diff_best = ~0; 1075 1076 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { 1077 unsigned diff; 1078 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, 1079 ref_div_max, &fb_div, &ref_div); 1080 diff = abs(target_clock - (pll->reference_freq * fb_div) / 1081 (ref_div * post_div)); 1082 1083 if (diff < diff_best || (diff == diff_best && 1084 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) { 1085 1086 post_div_best = post_div; 1087 diff_best = diff; 1088 } 1089 } 1090 post_div = post_div_best; 1091 1092 /* get the feedback and reference divider for the optimal value */ 1093 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max, 1094 &fb_div, &ref_div); 1095 1096 /* reduce the numbers to a simpler ratio once more */ 1097 /* this also makes sure that the reference divider is large enough */ 1098 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); 1099 1100 /* avoid high jitter with small fractional dividers */ 1101 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { 1102 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50); 1103 if (fb_div < fb_div_min) { 1104 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div); 1105 fb_div *= tmp; 1106 ref_div *= tmp; 1107 } 1108 } 1109 1110 /* and finally save the result */ 1111 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1112 *fb_div_p = fb_div / 10; 1113 *frac_fb_div_p = fb_div % 10; 1114 } else { 1115 *fb_div_p = fb_div; 1116 *frac_fb_div_p = 0; 1117 } 1118 1119 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + 1120 (pll->reference_freq * *frac_fb_div_p)) / 1121 (ref_div * post_div * 10); 1122 *ref_div_p = ref_div; 1123 *post_div_p = post_div; 1124 1125 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1126 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, 1127 ref_div, post_div); 1128 } 1129 1130 /* pre-avivo */ 1131 static inline uint32_t radeon_div(uint64_t n, uint32_t d) 1132 { 1133 uint64_t mod; 1134 1135 n += d / 2; 1136 1137 mod = do_div(n, d); 1138 return n; 1139 } 1140 1141 void radeon_compute_pll_legacy(struct radeon_pll *pll, 1142 uint64_t freq, 1143 uint32_t *dot_clock_p, 1144 uint32_t *fb_div_p, 1145 uint32_t *frac_fb_div_p, 1146 uint32_t *ref_div_p, 1147 uint32_t *post_div_p) 1148 { 1149 uint32_t min_ref_div = pll->min_ref_div; 1150 uint32_t max_ref_div = pll->max_ref_div; 1151 uint32_t min_post_div = pll->min_post_div; 1152 uint32_t max_post_div = pll->max_post_div; 1153 uint32_t min_fractional_feed_div = 0; 1154 uint32_t max_fractional_feed_div = 0; 1155 uint32_t best_vco = pll->best_vco; 1156 uint32_t best_post_div = 1; 1157 uint32_t best_ref_div = 1; 1158 uint32_t best_feedback_div = 1; 1159 uint32_t best_frac_feedback_div = 0; 1160 uint32_t best_freq = -1; 1161 uint32_t best_error = 0xffffffff; 1162 uint32_t best_vco_diff = 1; 1163 uint32_t post_div; 1164 u32 pll_out_min, pll_out_max; 1165 1166 DRM_DEBUG_KMS("PLL freq %ju %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); 1167 freq = freq * 1000; 1168 1169 if (pll->flags & RADEON_PLL_IS_LCD) { 1170 pll_out_min = pll->lcd_pll_out_min; 1171 pll_out_max = pll->lcd_pll_out_max; 1172 } else { 1173 pll_out_min = pll->pll_out_min; 1174 pll_out_max = pll->pll_out_max; 1175 } 1176 1177 if (pll_out_min > 64800) 1178 pll_out_min = 64800; 1179 1180 if (pll->flags & RADEON_PLL_USE_REF_DIV) 1181 min_ref_div = max_ref_div = pll->reference_div; 1182 else { 1183 while (min_ref_div < max_ref_div-1) { 1184 uint32_t mid = (min_ref_div + max_ref_div) / 2; 1185 uint32_t pll_in = pll->reference_freq / mid; 1186 if (pll_in < pll->pll_in_min) 1187 max_ref_div = mid; 1188 else if (pll_in > pll->pll_in_max) 1189 min_ref_div = mid; 1190 else 1191 break; 1192 } 1193 } 1194 1195 if (pll->flags & RADEON_PLL_USE_POST_DIV) 1196 min_post_div = max_post_div = pll->post_div; 1197 1198 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1199 min_fractional_feed_div = pll->min_frac_feedback_div; 1200 max_fractional_feed_div = pll->max_frac_feedback_div; 1201 } 1202 1203 for (post_div = max_post_div; post_div >= min_post_div; --post_div) { 1204 uint32_t ref_div; 1205 1206 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 1207 continue; 1208 1209 /* legacy radeons only have a few post_divs */ 1210 if (pll->flags & RADEON_PLL_LEGACY) { 1211 if ((post_div == 5) || 1212 (post_div == 7) || 1213 (post_div == 9) || 1214 (post_div == 10) || 1215 (post_div == 11) || 1216 (post_div == 13) || 1217 (post_div == 14) || 1218 (post_div == 15)) 1219 continue; 1220 } 1221 1222 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { 1223 uint32_t feedback_div, current_freq = 0, error, vco_diff; 1224 uint32_t pll_in = pll->reference_freq / ref_div; 1225 uint32_t min_feed_div = pll->min_feedback_div; 1226 uint32_t max_feed_div = pll->max_feedback_div + 1; 1227 1228 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) 1229 continue; 1230 1231 while (min_feed_div < max_feed_div) { 1232 uint32_t vco; 1233 uint32_t min_frac_feed_div = min_fractional_feed_div; 1234 uint32_t max_frac_feed_div = max_fractional_feed_div + 1; 1235 uint32_t frac_feedback_div; 1236 uint64_t tmp; 1237 1238 feedback_div = (min_feed_div + max_feed_div) / 2; 1239 1240 tmp = (uint64_t)pll->reference_freq * feedback_div; 1241 vco = radeon_div(tmp, ref_div); 1242 1243 if (vco < pll_out_min) { 1244 min_feed_div = feedback_div + 1; 1245 continue; 1246 } else if (vco > pll_out_max) { 1247 max_feed_div = feedback_div; 1248 continue; 1249 } 1250 1251 while (min_frac_feed_div < max_frac_feed_div) { 1252 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; 1253 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; 1254 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; 1255 current_freq = radeon_div(tmp, ref_div * post_div); 1256 1257 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 1258 if (freq < current_freq) 1259 error = 0xffffffff; 1260 else 1261 error = freq - current_freq; 1262 } else 1263 error = abs(current_freq - freq); 1264 vco_diff = abs(vco - best_vco); 1265 1266 if ((best_vco == 0 && error < best_error) || 1267 (best_vco != 0 && 1268 ((best_error > 100 && error < best_error - 100) || 1269 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { 1270 best_post_div = post_div; 1271 best_ref_div = ref_div; 1272 best_feedback_div = feedback_div; 1273 best_frac_feedback_div = frac_feedback_div; 1274 best_freq = current_freq; 1275 best_error = error; 1276 best_vco_diff = vco_diff; 1277 } else if (current_freq == freq) { 1278 if (best_freq == -1) { 1279 best_post_div = post_div; 1280 best_ref_div = ref_div; 1281 best_feedback_div = feedback_div; 1282 best_frac_feedback_div = frac_feedback_div; 1283 best_freq = current_freq; 1284 best_error = error; 1285 best_vco_diff = vco_diff; 1286 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 1287 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 1288 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 1289 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 1290 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 1291 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 1292 best_post_div = post_div; 1293 best_ref_div = ref_div; 1294 best_feedback_div = feedback_div; 1295 best_frac_feedback_div = frac_feedback_div; 1296 best_freq = current_freq; 1297 best_error = error; 1298 best_vco_diff = vco_diff; 1299 } 1300 } 1301 if (current_freq < freq) 1302 min_frac_feed_div = frac_feedback_div + 1; 1303 else 1304 max_frac_feed_div = frac_feedback_div; 1305 } 1306 if (current_freq < freq) 1307 min_feed_div = feedback_div + 1; 1308 else 1309 max_feed_div = feedback_div; 1310 } 1311 } 1312 } 1313 1314 *dot_clock_p = best_freq / 10000; 1315 *fb_div_p = best_feedback_div; 1316 *frac_fb_div_p = best_frac_feedback_div; 1317 *ref_div_p = best_ref_div; 1318 *post_div_p = best_post_div; 1319 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1320 (long long)freq, 1321 best_freq / 1000, best_feedback_div, best_frac_feedback_div, 1322 best_ref_div, best_post_div); 1323 1324 } 1325 1326 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) 1327 { 1328 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1329 1330 if (radeon_fb->obj) { 1331 drm_gem_object_unreference_unlocked(radeon_fb->obj); 1332 } 1333 drm_framebuffer_cleanup(fb); 1334 kfree(radeon_fb); 1335 } 1336 1337 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, 1338 struct drm_file *file_priv, 1339 unsigned int *handle) 1340 { 1341 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1342 1343 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); 1344 } 1345 1346 static const struct drm_framebuffer_funcs radeon_fb_funcs = { 1347 .destroy = radeon_user_framebuffer_destroy, 1348 .create_handle = radeon_user_framebuffer_create_handle, 1349 }; 1350 1351 int 1352 radeon_framebuffer_init(struct drm_device *dev, 1353 struct radeon_framebuffer *rfb, 1354 const struct drm_mode_fb_cmd2 *mode_cmd, 1355 struct drm_gem_object *obj) 1356 { 1357 int ret; 1358 rfb->obj = obj; 1359 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); 1360 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); 1361 if (ret) { 1362 rfb->obj = NULL; 1363 return ret; 1364 } 1365 return 0; 1366 } 1367 1368 static struct drm_framebuffer * 1369 radeon_user_framebuffer_create(struct drm_device *dev, 1370 struct drm_file *file_priv, 1371 const struct drm_mode_fb_cmd2 *mode_cmd) 1372 { 1373 struct drm_gem_object *obj; 1374 struct radeon_framebuffer *radeon_fb; 1375 int ret; 1376 1377 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); 1378 if (obj == NULL) { 1379 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 1380 "can't create framebuffer\n", mode_cmd->handles[0]); 1381 return ERR_PTR(-ENOENT); 1382 } 1383 1384 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ 1385 if (obj->import_attach) { 1386 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n"); 1387 return ERR_PTR(-EINVAL); 1388 } 1389 1390 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); 1391 if (radeon_fb == NULL) { 1392 drm_gem_object_unreference_unlocked(obj); 1393 return ERR_PTR(-ENOMEM); 1394 } 1395 1396 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj); 1397 if (ret) { 1398 kfree(radeon_fb); 1399 drm_gem_object_unreference_unlocked(obj); 1400 return ERR_PTR(ret); 1401 } 1402 1403 return &radeon_fb->base; 1404 } 1405 1406 static void radeon_output_poll_changed(struct drm_device *dev) 1407 { 1408 struct radeon_device *rdev = dev->dev_private; 1409 radeon_fb_output_poll_changed(rdev); 1410 } 1411 1412 static const struct drm_mode_config_funcs radeon_mode_funcs = { 1413 .fb_create = radeon_user_framebuffer_create, 1414 .output_poll_changed = radeon_output_poll_changed 1415 }; 1416 1417 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = 1418 { { 0, "driver" }, 1419 { 1, "bios" }, 1420 }; 1421 1422 static struct drm_prop_enum_list radeon_tv_std_enum_list[] = 1423 { { TV_STD_NTSC, "ntsc" }, 1424 { TV_STD_PAL, "pal" }, 1425 { TV_STD_PAL_M, "pal-m" }, 1426 { TV_STD_PAL_60, "pal-60" }, 1427 { TV_STD_NTSC_J, "ntsc-j" }, 1428 { TV_STD_SCART_PAL, "scart-pal" }, 1429 { TV_STD_PAL_CN, "pal-cn" }, 1430 { TV_STD_SECAM, "secam" }, 1431 }; 1432 1433 static struct drm_prop_enum_list radeon_underscan_enum_list[] = 1434 { { UNDERSCAN_OFF, "off" }, 1435 { UNDERSCAN_ON, "on" }, 1436 { UNDERSCAN_AUTO, "auto" }, 1437 }; 1438 1439 static struct drm_prop_enum_list radeon_audio_enum_list[] = 1440 { { RADEON_AUDIO_DISABLE, "off" }, 1441 { RADEON_AUDIO_ENABLE, "on" }, 1442 { RADEON_AUDIO_AUTO, "auto" }, 1443 }; 1444 1445 /* XXX support different dither options? spatial, temporal, both, etc. */ 1446 static struct drm_prop_enum_list radeon_dither_enum_list[] = 1447 { { RADEON_FMT_DITHER_DISABLE, "off" }, 1448 { RADEON_FMT_DITHER_ENABLE, "on" }, 1449 }; 1450 1451 static struct drm_prop_enum_list radeon_output_csc_enum_list[] = 1452 { { RADEON_OUTPUT_CSC_BYPASS, "bypass" }, 1453 { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" }, 1454 { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" }, 1455 { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" }, 1456 }; 1457 1458 static int radeon_modeset_create_props(struct radeon_device *rdev) 1459 { 1460 int sz; 1461 1462 if (rdev->is_atom_bios) { 1463 rdev->mode_info.coherent_mode_property = 1464 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1); 1465 if (!rdev->mode_info.coherent_mode_property) 1466 return -ENOMEM; 1467 } 1468 1469 if (!ASIC_IS_AVIVO(rdev)) { 1470 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); 1471 rdev->mode_info.tmds_pll_property = 1472 drm_property_create_enum(rdev->ddev, 0, 1473 "tmds_pll", 1474 radeon_tmds_pll_enum_list, sz); 1475 } 1476 1477 rdev->mode_info.load_detect_property = 1478 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1); 1479 if (!rdev->mode_info.load_detect_property) 1480 return -ENOMEM; 1481 1482 drm_mode_create_scaling_mode_property(rdev->ddev); 1483 1484 sz = ARRAY_SIZE(radeon_tv_std_enum_list); 1485 rdev->mode_info.tv_std_property = 1486 drm_property_create_enum(rdev->ddev, 0, 1487 "tv standard", 1488 radeon_tv_std_enum_list, sz); 1489 1490 sz = ARRAY_SIZE(radeon_underscan_enum_list); 1491 rdev->mode_info.underscan_property = 1492 drm_property_create_enum(rdev->ddev, 0, 1493 "underscan", 1494 radeon_underscan_enum_list, sz); 1495 1496 rdev->mode_info.underscan_hborder_property = 1497 drm_property_create_range(rdev->ddev, 0, 1498 "underscan hborder", 0, 128); 1499 if (!rdev->mode_info.underscan_hborder_property) 1500 return -ENOMEM; 1501 1502 rdev->mode_info.underscan_vborder_property = 1503 drm_property_create_range(rdev->ddev, 0, 1504 "underscan vborder", 0, 128); 1505 if (!rdev->mode_info.underscan_vborder_property) 1506 return -ENOMEM; 1507 1508 sz = ARRAY_SIZE(radeon_audio_enum_list); 1509 rdev->mode_info.audio_property = 1510 drm_property_create_enum(rdev->ddev, 0, 1511 "audio", 1512 radeon_audio_enum_list, sz); 1513 1514 sz = ARRAY_SIZE(radeon_dither_enum_list); 1515 rdev->mode_info.dither_property = 1516 drm_property_create_enum(rdev->ddev, 0, 1517 "dither", 1518 radeon_dither_enum_list, sz); 1519 1520 sz = ARRAY_SIZE(radeon_output_csc_enum_list); 1521 rdev->mode_info.output_csc_property = 1522 drm_property_create_enum(rdev->ddev, 0, 1523 "output_csc", 1524 radeon_output_csc_enum_list, sz); 1525 1526 return 0; 1527 } 1528 1529 void radeon_update_display_priority(struct radeon_device *rdev) 1530 { 1531 /* adjustment options for the display watermarks */ 1532 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { 1533 /* set display priority to high for r3xx, rv515 chips 1534 * this avoids flickering due to underflow to the 1535 * display controllers during heavy acceleration. 1536 * Don't force high on rs4xx igp chips as it seems to 1537 * affect the sound card. See kernel bug 15982. 1538 */ 1539 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && 1540 !(rdev->flags & RADEON_IS_IGP)) 1541 rdev->disp_priority = 2; 1542 else 1543 rdev->disp_priority = 0; 1544 } else 1545 rdev->disp_priority = radeon_disp_priority; 1546 1547 } 1548 1549 /* 1550 * Allocate hdmi structs and determine register offsets 1551 */ 1552 static void radeon_afmt_init(struct radeon_device *rdev) 1553 { 1554 int i; 1555 1556 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) 1557 rdev->mode_info.afmt[i] = NULL; 1558 1559 if (ASIC_IS_NODCE(rdev)) { 1560 /* nothing to do */ 1561 } else if (ASIC_IS_DCE4(rdev)) { 1562 static uint32_t eg_offsets[] = { 1563 EVERGREEN_CRTC0_REGISTER_OFFSET, 1564 EVERGREEN_CRTC1_REGISTER_OFFSET, 1565 EVERGREEN_CRTC2_REGISTER_OFFSET, 1566 EVERGREEN_CRTC3_REGISTER_OFFSET, 1567 EVERGREEN_CRTC4_REGISTER_OFFSET, 1568 EVERGREEN_CRTC5_REGISTER_OFFSET, 1569 0x13830 - 0x7030, 1570 }; 1571 int num_afmt; 1572 1573 /* DCE8 has 7 audio blocks tied to DIG encoders */ 1574 /* DCE6 has 6 audio blocks tied to DIG encoders */ 1575 /* DCE4/5 has 6 audio blocks tied to DIG encoders */ 1576 /* DCE4.1 has 2 audio blocks tied to DIG encoders */ 1577 if (ASIC_IS_DCE8(rdev)) 1578 num_afmt = 7; 1579 else if (ASIC_IS_DCE6(rdev)) 1580 num_afmt = 6; 1581 else if (ASIC_IS_DCE5(rdev)) 1582 num_afmt = 6; 1583 else if (ASIC_IS_DCE41(rdev)) 1584 num_afmt = 2; 1585 else /* DCE4 */ 1586 num_afmt = 6; 1587 1588 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets)); 1589 for (i = 0; i < num_afmt; i++) { 1590 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1591 if (rdev->mode_info.afmt[i]) { 1592 rdev->mode_info.afmt[i]->offset = eg_offsets[i]; 1593 rdev->mode_info.afmt[i]->id = i; 1594 } 1595 } 1596 } else if (ASIC_IS_DCE3(rdev)) { 1597 /* DCE3.x has 2 audio blocks tied to DIG encoders */ 1598 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1599 if (rdev->mode_info.afmt[0]) { 1600 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0; 1601 rdev->mode_info.afmt[0]->id = 0; 1602 } 1603 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1604 if (rdev->mode_info.afmt[1]) { 1605 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1; 1606 rdev->mode_info.afmt[1]->id = 1; 1607 } 1608 } else if (ASIC_IS_DCE2(rdev)) { 1609 /* DCE2 has at least 1 routable audio block */ 1610 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1611 if (rdev->mode_info.afmt[0]) { 1612 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0; 1613 rdev->mode_info.afmt[0]->id = 0; 1614 } 1615 /* r6xx has 2 routable audio blocks */ 1616 if (rdev->family >= CHIP_R600) { 1617 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1618 if (rdev->mode_info.afmt[1]) { 1619 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1; 1620 rdev->mode_info.afmt[1]->id = 1; 1621 } 1622 } 1623 } 1624 } 1625 1626 static void radeon_afmt_fini(struct radeon_device *rdev) 1627 { 1628 int i; 1629 1630 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) { 1631 kfree(rdev->mode_info.afmt[i]); 1632 rdev->mode_info.afmt[i] = NULL; 1633 } 1634 } 1635 1636 int radeon_modeset_init(struct radeon_device *rdev) 1637 { 1638 int i; 1639 int ret; 1640 1641 drm_mode_config_init(rdev->ddev); 1642 rdev->mode_info.mode_config_initialized = true; 1643 1644 rdev->ddev->mode_config.funcs = &radeon_mode_funcs; 1645 1646 if (ASIC_IS_DCE5(rdev)) { 1647 rdev->ddev->mode_config.max_width = 16384; 1648 rdev->ddev->mode_config.max_height = 16384; 1649 } else if (ASIC_IS_AVIVO(rdev)) { 1650 rdev->ddev->mode_config.max_width = 8192; 1651 rdev->ddev->mode_config.max_height = 8192; 1652 } else { 1653 rdev->ddev->mode_config.max_width = 4096; 1654 rdev->ddev->mode_config.max_height = 4096; 1655 } 1656 1657 rdev->ddev->mode_config.preferred_depth = 24; 1658 rdev->ddev->mode_config.prefer_shadow = 1; 1659 1660 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; 1661 1662 ret = radeon_modeset_create_props(rdev); 1663 if (ret) { 1664 return ret; 1665 } 1666 1667 /* init i2c buses */ 1668 radeon_i2c_init(rdev); 1669 1670 /* check combios for a valid hardcoded EDID - Sun servers */ 1671 if (!rdev->is_atom_bios) { 1672 /* check for hardcoded EDID in BIOS */ 1673 radeon_combios_check_hardcoded_edid(rdev); 1674 } 1675 1676 /* allocate crtcs */ 1677 for (i = 0; i < rdev->num_crtc; i++) { 1678 radeon_crtc_init(rdev->ddev, i); 1679 } 1680 1681 /* okay we should have all the bios connectors */ 1682 ret = radeon_setup_enc_conn(rdev->ddev); 1683 if (!ret) { 1684 return ret; 1685 } 1686 1687 /* init dig PHYs, disp eng pll */ 1688 if (rdev->is_atom_bios) { 1689 radeon_atom_encoder_init(rdev); 1690 radeon_atom_disp_eng_pll_init(rdev); 1691 } 1692 1693 /* initialize hpd */ 1694 radeon_hpd_init(rdev); 1695 1696 /* setup afmt */ 1697 radeon_afmt_init(rdev); 1698 1699 radeon_fbdev_init(rdev); 1700 drm_kms_helper_poll_init(rdev->ddev); 1701 1702 /* do pm late init */ 1703 ret = radeon_pm_late_init(rdev); 1704 1705 return 0; 1706 } 1707 1708 void radeon_modeset_fini(struct radeon_device *rdev) 1709 { 1710 radeon_fbdev_fini(rdev); 1711 kfree(rdev->mode_info.bios_hardcoded_edid); 1712 1713 if (rdev->mode_info.mode_config_initialized) { 1714 radeon_afmt_fini(rdev); 1715 drm_kms_helper_poll_fini(rdev->ddev); 1716 radeon_hpd_fini(rdev); 1717 drm_mode_config_cleanup(rdev->ddev); 1718 rdev->mode_info.mode_config_initialized = false; 1719 } 1720 /* free i2c buses */ 1721 radeon_i2c_fini(rdev); 1722 } 1723 1724 static bool is_hdtv_mode(const struct drm_display_mode *mode) 1725 { 1726 /* try and guess if this is a tv or a monitor */ 1727 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 1728 (mode->vdisplay == 576) || /* 576p */ 1729 (mode->vdisplay == 720) || /* 720p */ 1730 (mode->vdisplay == 1080)) /* 1080p */ 1731 return true; 1732 else 1733 return false; 1734 } 1735 1736 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 1737 const struct drm_display_mode *mode, 1738 struct drm_display_mode *adjusted_mode) 1739 { 1740 struct drm_device *dev = crtc->dev; 1741 struct radeon_device *rdev = dev->dev_private; 1742 struct drm_encoder *encoder; 1743 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1744 struct radeon_encoder *radeon_encoder; 1745 struct drm_connector *connector; 1746 struct radeon_connector *radeon_connector; 1747 bool first = true; 1748 u32 src_v = 1, dst_v = 1; 1749 u32 src_h = 1, dst_h = 1; 1750 1751 radeon_crtc->h_border = 0; 1752 radeon_crtc->v_border = 0; 1753 1754 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1755 if (encoder->crtc != crtc) 1756 continue; 1757 radeon_encoder = to_radeon_encoder(encoder); 1758 connector = radeon_get_connector_for_encoder(encoder); 1759 radeon_connector = to_radeon_connector(connector); 1760 1761 if (first) { 1762 /* set scaling */ 1763 if (radeon_encoder->rmx_type == RMX_OFF) 1764 radeon_crtc->rmx_type = RMX_OFF; 1765 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || 1766 mode->vdisplay < radeon_encoder->native_mode.vdisplay) 1767 radeon_crtc->rmx_type = radeon_encoder->rmx_type; 1768 else 1769 radeon_crtc->rmx_type = RMX_OFF; 1770 /* copy native mode */ 1771 memcpy(&radeon_crtc->native_mode, 1772 &radeon_encoder->native_mode, 1773 sizeof(struct drm_display_mode)); 1774 src_v = crtc->mode.vdisplay; 1775 dst_v = radeon_crtc->native_mode.vdisplay; 1776 src_h = crtc->mode.hdisplay; 1777 dst_h = radeon_crtc->native_mode.hdisplay; 1778 1779 /* fix up for overscan on hdmi */ 1780 if (ASIC_IS_AVIVO(rdev) && 1781 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 1782 ((radeon_encoder->underscan_type == UNDERSCAN_ON) || 1783 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && 1784 drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 1785 is_hdtv_mode(mode)))) { 1786 if (radeon_encoder->underscan_hborder != 0) 1787 radeon_crtc->h_border = radeon_encoder->underscan_hborder; 1788 else 1789 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; 1790 if (radeon_encoder->underscan_vborder != 0) 1791 radeon_crtc->v_border = radeon_encoder->underscan_vborder; 1792 else 1793 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; 1794 radeon_crtc->rmx_type = RMX_FULL; 1795 src_v = crtc->mode.vdisplay; 1796 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); 1797 src_h = crtc->mode.hdisplay; 1798 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); 1799 } 1800 first = false; 1801 } else { 1802 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { 1803 /* WARNING: Right now this can't happen but 1804 * in the future we need to check that scaling 1805 * are consistent across different encoder 1806 * (ie all encoder can work with the same 1807 * scaling). 1808 */ 1809 DRM_ERROR("Scaling not consistent across encoder.\n"); 1810 return false; 1811 } 1812 } 1813 } 1814 if (radeon_crtc->rmx_type != RMX_OFF) { 1815 fixed20_12 a, b; 1816 a.full = dfixed_const(src_v); 1817 b.full = dfixed_const(dst_v); 1818 radeon_crtc->vsc.full = dfixed_div(a, b); 1819 a.full = dfixed_const(src_h); 1820 b.full = dfixed_const(dst_h); 1821 radeon_crtc->hsc.full = dfixed_div(a, b); 1822 } else { 1823 radeon_crtc->vsc.full = dfixed_const(1); 1824 radeon_crtc->hsc.full = dfixed_const(1); 1825 } 1826 return true; 1827 } 1828 1829 /* 1830 * Retrieve current video scanout position of crtc on a given gpu, and 1831 * an optional accurate timestamp of when query happened. 1832 * 1833 * \param dev Device to query. 1834 * \param crtc Crtc to query. 1835 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 1836 * For driver internal use only also supports these flags: 1837 * 1838 * USE_REAL_VBLANKSTART to use the real start of vblank instead 1839 * of a fudged earlier start of vblank. 1840 * 1841 * GET_DISTANCE_TO_VBLANKSTART to return distance to the 1842 * fudged earlier start of vblank in *vpos and the distance 1843 * to true start of vblank in *hpos. 1844 * 1845 * \param *vpos Location where vertical scanout position should be stored. 1846 * \param *hpos Location where horizontal scanout position should go. 1847 * \param *stime Target location for timestamp taken immediately before 1848 * scanout position query. Can be NULL to skip timestamp. 1849 * \param *etime Target location for timestamp taken immediately after 1850 * scanout position query. Can be NULL to skip timestamp. 1851 * 1852 * Returns vpos as a positive number while in active scanout area. 1853 * Returns vpos as a negative number inside vblank, counting the number 1854 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 1855 * until start of active scanout / end of vblank." 1856 * 1857 * \return Flags, or'ed together as follows: 1858 * 1859 * DRM_SCANOUTPOS_VALID = Query successful. 1860 * DRM_SCANOUTPOS_INVBL = Inside vblank. 1861 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 1862 * this flag means that returned position may be offset by a constant but 1863 * unknown small number of scanlines wrt. real scanout position. 1864 * 1865 */ 1866 int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 1867 unsigned int flags, int *vpos, int *hpos, 1868 ktime_t *stime, ktime_t *etime, 1869 const struct drm_display_mode *mode) 1870 { 1871 u32 stat_crtc = 0, vbl = 0, position = 0; 1872 int vbl_start, vbl_end, vtotal, ret = 0; 1873 bool in_vbl = true; 1874 1875 struct radeon_device *rdev = dev->dev_private; 1876 1877 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 1878 1879 /* Get optional system timestamp before query. */ 1880 if (stime) 1881 *stime = ktime_get(); 1882 1883 if (ASIC_IS_DCE4(rdev)) { 1884 if (pipe == 0) { 1885 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1886 EVERGREEN_CRTC0_REGISTER_OFFSET); 1887 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1888 EVERGREEN_CRTC0_REGISTER_OFFSET); 1889 ret |= DRM_SCANOUTPOS_VALID; 1890 } 1891 if (pipe == 1) { 1892 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1893 EVERGREEN_CRTC1_REGISTER_OFFSET); 1894 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1895 EVERGREEN_CRTC1_REGISTER_OFFSET); 1896 ret |= DRM_SCANOUTPOS_VALID; 1897 } 1898 if (pipe == 2) { 1899 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1900 EVERGREEN_CRTC2_REGISTER_OFFSET); 1901 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1902 EVERGREEN_CRTC2_REGISTER_OFFSET); 1903 ret |= DRM_SCANOUTPOS_VALID; 1904 } 1905 if (pipe == 3) { 1906 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1907 EVERGREEN_CRTC3_REGISTER_OFFSET); 1908 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1909 EVERGREEN_CRTC3_REGISTER_OFFSET); 1910 ret |= DRM_SCANOUTPOS_VALID; 1911 } 1912 if (pipe == 4) { 1913 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1914 EVERGREEN_CRTC4_REGISTER_OFFSET); 1915 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1916 EVERGREEN_CRTC4_REGISTER_OFFSET); 1917 ret |= DRM_SCANOUTPOS_VALID; 1918 } 1919 if (pipe == 5) { 1920 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1921 EVERGREEN_CRTC5_REGISTER_OFFSET); 1922 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1923 EVERGREEN_CRTC5_REGISTER_OFFSET); 1924 ret |= DRM_SCANOUTPOS_VALID; 1925 } 1926 } else if (ASIC_IS_AVIVO(rdev)) { 1927 if (pipe == 0) { 1928 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); 1929 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); 1930 ret |= DRM_SCANOUTPOS_VALID; 1931 } 1932 if (pipe == 1) { 1933 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); 1934 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); 1935 ret |= DRM_SCANOUTPOS_VALID; 1936 } 1937 } else { 1938 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ 1939 if (pipe == 0) { 1940 /* Assume vbl_end == 0, get vbl_start from 1941 * upper 16 bits. 1942 */ 1943 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & 1944 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1945 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ 1946 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1947 stat_crtc = RREG32(RADEON_CRTC_STATUS); 1948 if (!(stat_crtc & 1)) 1949 in_vbl = false; 1950 1951 ret |= DRM_SCANOUTPOS_VALID; 1952 } 1953 if (pipe == 1) { 1954 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & 1955 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1956 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1957 stat_crtc = RREG32(RADEON_CRTC2_STATUS); 1958 if (!(stat_crtc & 1)) 1959 in_vbl = false; 1960 1961 ret |= DRM_SCANOUTPOS_VALID; 1962 } 1963 } 1964 1965 /* Get optional system timestamp after query. */ 1966 if (etime) 1967 *etime = ktime_get(); 1968 1969 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 1970 1971 /* Decode into vertical and horizontal scanout position. */ 1972 *vpos = position & 0x1fff; 1973 *hpos = (position >> 16) & 0x1fff; 1974 1975 /* Valid vblank area boundaries from gpu retrieved? */ 1976 if (vbl > 0) { 1977 /* Yes: Decode. */ 1978 ret |= DRM_SCANOUTPOS_ACCURATE; 1979 vbl_start = vbl & 0x1fff; 1980 vbl_end = (vbl >> 16) & 0x1fff; 1981 } 1982 else { 1983 /* No: Fake something reasonable which gives at least ok results. */ 1984 vbl_start = mode->crtc_vdisplay; 1985 vbl_end = 0; 1986 } 1987 1988 /* Called from driver internal vblank counter query code? */ 1989 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1990 /* Caller wants distance from real vbl_start in *hpos */ 1991 *hpos = *vpos - vbl_start; 1992 } 1993 1994 /* Fudge vblank to start a few scanlines earlier to handle the 1995 * problem that vblank irqs fire a few scanlines before start 1996 * of vblank. Some driver internal callers need the true vblank 1997 * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 1998 * 1999 * The cause of the "early" vblank irq is that the irq is triggered 2000 * by the line buffer logic when the line buffer read position enters 2001 * the vblank, whereas our crtc scanout position naturally lags the 2002 * line buffer read position. 2003 */ 2004 if (!(flags & USE_REAL_VBLANKSTART)) 2005 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 2006 2007 /* Test scanout position against vblank region. */ 2008 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 2009 in_vbl = false; 2010 2011 /* In vblank? */ 2012 if (in_vbl) 2013 ret |= DRM_SCANOUTPOS_IN_VBLANK; 2014 2015 /* Called from driver internal vblank counter query code? */ 2016 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 2017 /* Caller wants distance from fudged earlier vbl_start */ 2018 *vpos -= vbl_start; 2019 return ret; 2020 } 2021 2022 /* Check if inside vblank area and apply corrective offsets: 2023 * vpos will then be >=0 in video scanout area, but negative 2024 * within vblank area, counting down the number of lines until 2025 * start of scanout. 2026 */ 2027 2028 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 2029 if (in_vbl && (*vpos >= vbl_start)) { 2030 vtotal = mode->crtc_vtotal; 2031 *vpos = *vpos - vtotal; 2032 } 2033 2034 /* Correct for shifted end of vbl at vbl_end. */ 2035 *vpos = *vpos - vbl_end; 2036 2037 return ret; 2038 } 2039