1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/radeon_drm.h> 28 #include "radeon.h" 29 30 #include "atom.h" 31 32 #include <linux/pm_runtime.h> 33 #include <drm/drm_crtc_helper.h> 34 #include <drm/drm_plane_helper.h> 35 #include <drm/drm_edid.h> 36 37 #include <linux/gcd.h> 38 39 static void avivo_crtc_load_lut(struct drm_crtc *crtc) 40 { 41 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 42 struct drm_device *dev = crtc->dev; 43 struct radeon_device *rdev = dev->dev_private; 44 int i; 45 46 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 47 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); 48 49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 52 53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 56 57 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); 58 WREG32(AVIVO_DC_LUT_RW_MODE, 0); 59 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); 60 61 WREG8(AVIVO_DC_LUT_RW_INDEX, 0); 62 for (i = 0; i < 256; i++) { 63 WREG32(AVIVO_DC_LUT_30_COLOR, 64 (radeon_crtc->lut_r[i] << 20) | 65 (radeon_crtc->lut_g[i] << 10) | 66 (radeon_crtc->lut_b[i] << 0)); 67 } 68 69 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */ 70 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1); 71 } 72 73 static void dce4_crtc_load_lut(struct drm_crtc *crtc) 74 { 75 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 76 struct drm_device *dev = crtc->dev; 77 struct radeon_device *rdev = dev->dev_private; 78 int i; 79 80 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 81 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 82 83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 84 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 85 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 86 87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 88 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 89 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 90 91 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 92 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 93 94 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 95 for (i = 0; i < 256; i++) { 96 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 97 (radeon_crtc->lut_r[i] << 20) | 98 (radeon_crtc->lut_g[i] << 10) | 99 (radeon_crtc->lut_b[i] << 0)); 100 } 101 } 102 103 static void dce5_crtc_load_lut(struct drm_crtc *crtc) 104 { 105 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 106 struct drm_device *dev = crtc->dev; 107 struct radeon_device *rdev = dev->dev_private; 108 int i; 109 110 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 111 112 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 113 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | 114 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); 115 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, 116 NI_GRPH_PRESCALE_BYPASS); 117 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, 118 NI_OVL_PRESCALE_BYPASS); 119 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, 120 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | 121 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); 122 123 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 124 125 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 126 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 127 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 128 129 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 130 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 131 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 132 133 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 134 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 135 136 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 137 for (i = 0; i < 256; i++) { 138 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 139 (radeon_crtc->lut_r[i] << 20) | 140 (radeon_crtc->lut_g[i] << 10) | 141 (radeon_crtc->lut_b[i] << 0)); 142 } 143 144 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, 145 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 146 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 147 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 148 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); 149 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, 150 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | 151 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); 152 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, 153 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | 154 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); 155 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 156 (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) | 157 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); 158 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 159 WREG32(0x6940 + radeon_crtc->crtc_offset, 0); 160 if (ASIC_IS_DCE8(rdev)) { 161 /* XXX this only needs to be programmed once per crtc at startup, 162 * not sure where the best place for it is 163 */ 164 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset, 165 CIK_CURSOR_ALPHA_BLND_ENA); 166 } 167 } 168 169 static void legacy_crtc_load_lut(struct drm_crtc *crtc) 170 { 171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 172 struct drm_device *dev = crtc->dev; 173 struct radeon_device *rdev = dev->dev_private; 174 int i; 175 uint32_t dac2_cntl; 176 177 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 178 if (radeon_crtc->crtc_id == 0) 179 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; 180 else 181 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; 182 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 183 184 WREG8(RADEON_PALETTE_INDEX, 0); 185 for (i = 0; i < 256; i++) { 186 WREG32(RADEON_PALETTE_30_DATA, 187 (radeon_crtc->lut_r[i] << 20) | 188 (radeon_crtc->lut_g[i] << 10) | 189 (radeon_crtc->lut_b[i] << 0)); 190 } 191 } 192 193 void radeon_crtc_load_lut(struct drm_crtc *crtc) 194 { 195 struct drm_device *dev = crtc->dev; 196 struct radeon_device *rdev = dev->dev_private; 197 198 if (!crtc->enabled) 199 return; 200 201 if (ASIC_IS_DCE5(rdev)) 202 dce5_crtc_load_lut(crtc); 203 else if (ASIC_IS_DCE4(rdev)) 204 dce4_crtc_load_lut(crtc); 205 else if (ASIC_IS_AVIVO(rdev)) 206 avivo_crtc_load_lut(crtc); 207 else 208 legacy_crtc_load_lut(crtc); 209 } 210 211 /** Sets the color ramps on behalf of fbcon */ 212 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 213 u16 blue, int regno) 214 { 215 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 216 217 radeon_crtc->lut_r[regno] = red >> 6; 218 radeon_crtc->lut_g[regno] = green >> 6; 219 radeon_crtc->lut_b[regno] = blue >> 6; 220 } 221 222 /** Gets the color ramps on behalf of fbcon */ 223 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 224 u16 *blue, int regno) 225 { 226 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 227 228 *red = radeon_crtc->lut_r[regno] << 6; 229 *green = radeon_crtc->lut_g[regno] << 6; 230 *blue = radeon_crtc->lut_b[regno] << 6; 231 } 232 233 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 234 u16 *blue, uint32_t start, uint32_t size) 235 { 236 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 237 int end = (start + size > 256) ? 256 : start + size, i; 238 239 /* userspace palettes are always correct as is */ 240 for (i = start; i < end; i++) { 241 radeon_crtc->lut_r[i] = red[i] >> 6; 242 radeon_crtc->lut_g[i] = green[i] >> 6; 243 radeon_crtc->lut_b[i] = blue[i] >> 6; 244 } 245 radeon_crtc_load_lut(crtc); 246 } 247 248 static void radeon_crtc_destroy(struct drm_crtc *crtc) 249 { 250 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 251 252 drm_crtc_cleanup(crtc); 253 destroy_workqueue(radeon_crtc->flip_queue); 254 kfree(radeon_crtc); 255 } 256 257 /** 258 * radeon_unpin_work_func - unpin old buffer object 259 * 260 * @__work - kernel work item 261 * 262 * Unpin the old frame buffer object outside of the interrupt handler 263 */ 264 static void radeon_unpin_work_func(struct work_struct *__work) 265 { 266 struct radeon_flip_work *work = 267 container_of(__work, struct radeon_flip_work, unpin_work); 268 int r; 269 270 /* unpin of the old buffer */ 271 r = radeon_bo_reserve(work->old_rbo, false); 272 if (likely(r == 0)) { 273 r = radeon_bo_unpin(work->old_rbo); 274 if (unlikely(r != 0)) { 275 DRM_ERROR("failed to unpin buffer after flip\n"); 276 } 277 radeon_bo_unreserve(work->old_rbo); 278 } else 279 DRM_ERROR("failed to reserve buffer after flip\n"); 280 281 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 282 kfree(work); 283 } 284 285 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id) 286 { 287 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 288 unsigned long flags; 289 u32 update_pending; 290 int vpos, hpos; 291 292 /* can happen during initialization */ 293 if (radeon_crtc == NULL) 294 return; 295 296 /* Skip the pageflip completion check below (based on polling) on 297 * asics which reliably support hw pageflip completion irqs. pflip 298 * irqs are a reliable and race-free method of handling pageflip 299 * completion detection. A use_pflipirq module parameter < 2 allows 300 * to override this in case of asics with faulty pflip irqs. 301 * A module parameter of 0 would only use this polling based path, 302 * a parameter of 1 would use pflip irq only as a backup to this 303 * path, as in Linux 3.16. 304 */ 305 if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev)) 306 return; 307 308 spin_lock_irqsave(&rdev->ddev->event_lock, flags); 309 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 310 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 311 "RADEON_FLIP_SUBMITTED(%d)\n", 312 radeon_crtc->flip_status, 313 RADEON_FLIP_SUBMITTED); 314 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 315 return; 316 } 317 318 update_pending = radeon_page_flip_pending(rdev, crtc_id); 319 320 /* Has the pageflip already completed in crtc, or is it certain 321 * to complete in this vblank? 322 */ 323 if (update_pending && 324 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, 325 crtc_id, 326 USE_REAL_VBLANKSTART, 327 &vpos, &hpos, NULL, NULL, 328 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) && 329 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) || 330 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) { 331 /* crtc didn't flip in this target vblank interval, 332 * but flip is pending in crtc. Based on the current 333 * scanout position we know that the current frame is 334 * (nearly) complete and the flip will (likely) 335 * complete before the start of the next frame. 336 */ 337 update_pending = 0; 338 } 339 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 340 if (!update_pending) 341 radeon_crtc_handle_flip(rdev, crtc_id); 342 } 343 344 /** 345 * radeon_crtc_handle_flip - page flip completed 346 * 347 * @rdev: radeon device pointer 348 * @crtc_id: crtc number this event is for 349 * 350 * Called when we are sure that a page flip for this crtc is completed. 351 */ 352 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) 353 { 354 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 355 struct radeon_flip_work *work; 356 unsigned long flags; 357 358 /* this can happen at init */ 359 if (radeon_crtc == NULL) 360 return; 361 362 spin_lock_irqsave(&rdev->ddev->event_lock, flags); 363 work = radeon_crtc->flip_work; 364 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 365 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 366 "RADEON_FLIP_SUBMITTED(%d)\n", 367 radeon_crtc->flip_status, 368 RADEON_FLIP_SUBMITTED); 369 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 370 return; 371 } 372 373 /* Pageflip completed. Clean up. */ 374 radeon_crtc->flip_status = RADEON_FLIP_NONE; 375 radeon_crtc->flip_work = NULL; 376 377 /* wakeup userspace */ 378 if (work->event) 379 drm_crtc_send_vblank_event(&radeon_crtc->base, work->event); 380 381 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 382 383 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id); 384 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id); 385 queue_work(radeon_crtc->flip_queue, &work->unpin_work); 386 } 387 388 /** 389 * radeon_flip_work_func - page flip framebuffer 390 * 391 * @work - kernel work item 392 * 393 * Wait for the buffer object to become idle and do the actual page flip 394 */ 395 static void radeon_flip_work_func(struct work_struct *__work) 396 { 397 struct radeon_flip_work *work = 398 container_of(__work, struct radeon_flip_work, flip_work); 399 struct radeon_device *rdev = work->rdev; 400 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id]; 401 402 struct drm_crtc *crtc = &radeon_crtc->base; 403 unsigned long flags; 404 int r; 405 int vpos, hpos, stat, min_udelay = 0; 406 unsigned repcnt = 4; 407 struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id]; 408 409 down_read(&rdev->exclusive_lock); 410 if (work->fence) { 411 struct radeon_fence *fence; 412 413 fence = to_radeon_fence(work->fence); 414 if (fence && fence->rdev == rdev) { 415 r = radeon_fence_wait(fence, false); 416 if (r == -EDEADLK) { 417 up_read(&rdev->exclusive_lock); 418 do { 419 r = radeon_gpu_reset(rdev); 420 } while (r == -EAGAIN); 421 down_read(&rdev->exclusive_lock); 422 } 423 } else 424 r = fence_wait(work->fence, false); 425 426 if (r) 427 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r); 428 429 /* We continue with the page flip even if we failed to wait on 430 * the fence, otherwise the DRM core and userspace will be 431 * confused about which BO the CRTC is scanning out 432 */ 433 434 fence_put(work->fence); 435 work->fence = NULL; 436 } 437 438 /* We borrow the event spin lock for protecting flip_status */ 439 spin_lock_irqsave(&crtc->dev->event_lock, flags); 440 441 /* set the proper interrupt */ 442 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id); 443 444 /* If this happens to execute within the "virtually extended" vblank 445 * interval before the start of the real vblank interval then it needs 446 * to delay programming the mmio flip until the real vblank is entered. 447 * This prevents completing a flip too early due to the way we fudge 448 * our vblank counter and vblank timestamps in order to work around the 449 * problem that the hw fires vblank interrupts before actual start of 450 * vblank (when line buffer refilling is done for a frame). It 451 * complements the fudging logic in radeon_get_crtc_scanoutpos() for 452 * timestamping and radeon_get_vblank_counter_kms() for vblank counts. 453 * 454 * In practice this won't execute very often unless on very fast 455 * machines because the time window for this to happen is very small. 456 */ 457 while (radeon_crtc->enabled && --repcnt) { 458 /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank 459 * start in hpos, and to the "fudged earlier" vblank start in 460 * vpos. 461 */ 462 stat = radeon_get_crtc_scanoutpos(rdev->ddev, work->crtc_id, 463 GET_DISTANCE_TO_VBLANKSTART, 464 &vpos, &hpos, NULL, NULL, 465 &crtc->hwmode); 466 467 if ((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 468 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE) || 469 !(vpos >= 0 && hpos <= 0)) 470 break; 471 472 /* Sleep at least until estimated real start of hw vblank */ 473 min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5); 474 if (min_udelay > vblank->framedur_ns / 2000) { 475 /* Don't wait ridiculously long - something is wrong */ 476 repcnt = 0; 477 break; 478 } 479 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 480 usleep_range(min_udelay, 2 * min_udelay); 481 spin_lock_irqsave(&crtc->dev->event_lock, flags); 482 }; 483 484 if (!repcnt) 485 DRM_DEBUG_DRIVER("Delay problem on crtc %d: min_udelay %d, " 486 "framedur %d, linedur %d, stat %d, vpos %d, " 487 "hpos %d\n", work->crtc_id, min_udelay, 488 vblank->framedur_ns / 1000, 489 vblank->linedur_ns / 1000, stat, vpos, hpos); 490 491 /* do the flip (mmio) */ 492 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async); 493 494 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED; 495 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 496 up_read(&rdev->exclusive_lock); 497 } 498 499 static int radeon_crtc_page_flip(struct drm_crtc *crtc, 500 struct drm_framebuffer *fb, 501 struct drm_pending_vblank_event *event, 502 uint32_t page_flip_flags) 503 { 504 struct drm_device *dev = crtc->dev; 505 struct radeon_device *rdev = dev->dev_private; 506 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 507 struct radeon_framebuffer *old_radeon_fb; 508 struct radeon_framebuffer *new_radeon_fb; 509 struct drm_gem_object *obj; 510 struct radeon_flip_work *work; 511 struct radeon_bo *new_rbo; 512 uint32_t tiling_flags, pitch_pixels; 513 uint64_t base; 514 unsigned long flags; 515 int r; 516 517 work = kzalloc(sizeof *work, GFP_KERNEL); 518 if (work == NULL) 519 return -ENOMEM; 520 521 INIT_WORK(&work->flip_work, radeon_flip_work_func); 522 INIT_WORK(&work->unpin_work, radeon_unpin_work_func); 523 524 work->rdev = rdev; 525 work->crtc_id = radeon_crtc->crtc_id; 526 work->event = event; 527 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 528 529 /* schedule unpin of the old buffer */ 530 old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb); 531 obj = old_radeon_fb->obj; 532 533 /* take a reference to the old object */ 534 drm_gem_object_reference(obj); 535 work->old_rbo = gem_to_radeon_bo(obj); 536 537 new_radeon_fb = to_radeon_framebuffer(fb); 538 obj = new_radeon_fb->obj; 539 new_rbo = gem_to_radeon_bo(obj); 540 541 /* pin the new buffer */ 542 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n", 543 work->old_rbo, new_rbo); 544 545 r = radeon_bo_reserve(new_rbo, false); 546 if (unlikely(r != 0)) { 547 DRM_ERROR("failed to reserve new rbo buffer before flip\n"); 548 goto cleanup; 549 } 550 /* Only 27 bit offset for legacy CRTC */ 551 r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM, 552 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, (u64 *)&base); 553 if (unlikely(r != 0)) { 554 radeon_bo_unreserve(new_rbo); 555 r = -EINVAL; 556 DRM_ERROR("failed to pin new rbo buffer before flip\n"); 557 goto cleanup; 558 } 559 work->fence = fence_get(reservation_object_get_excl(new_rbo->tbo.resv)); 560 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); 561 radeon_bo_unreserve(new_rbo); 562 563 if (!ASIC_IS_AVIVO(rdev)) { 564 /* crtc offset is from display base addr not FB location */ 565 base -= radeon_crtc->legacy_display_base_addr; 566 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8); 567 568 if (tiling_flags & RADEON_TILING_MACRO) { 569 if (ASIC_IS_R300(rdev)) { 570 base &= ~0x7ff; 571 } else { 572 int byteshift = fb->bits_per_pixel >> 4; 573 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11; 574 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8); 575 } 576 } else { 577 int offset = crtc->y * pitch_pixels + crtc->x; 578 switch (fb->bits_per_pixel) { 579 case 8: 580 default: 581 offset *= 1; 582 break; 583 case 15: 584 case 16: 585 offset *= 2; 586 break; 587 case 24: 588 offset *= 3; 589 break; 590 case 32: 591 offset *= 4; 592 break; 593 } 594 base += offset; 595 } 596 base &= ~7; 597 } 598 work->base = base; 599 600 r = drm_vblank_get(crtc->dev, radeon_crtc->crtc_id); 601 if (r) { 602 DRM_ERROR("failed to get vblank before flip\n"); 603 goto pflip_cleanup; 604 } 605 606 /* We borrow the event spin lock for protecting flip_work */ 607 spin_lock_irqsave(&crtc->dev->event_lock, flags); 608 609 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) { 610 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 611 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 612 r = -EBUSY; 613 goto vblank_cleanup; 614 } 615 radeon_crtc->flip_status = RADEON_FLIP_PENDING; 616 radeon_crtc->flip_work = work; 617 618 /* update crtc fb */ 619 crtc->primary->fb = fb; 620 621 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 622 623 queue_work(radeon_crtc->flip_queue, &work->flip_work); 624 return 0; 625 626 vblank_cleanup: 627 drm_vblank_put(crtc->dev, radeon_crtc->crtc_id); 628 629 pflip_cleanup: 630 if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) { 631 DRM_ERROR("failed to reserve new rbo in error path\n"); 632 goto cleanup; 633 } 634 if (unlikely(radeon_bo_unpin(new_rbo) != 0)) { 635 DRM_ERROR("failed to unpin new rbo in error path\n"); 636 } 637 radeon_bo_unreserve(new_rbo); 638 639 cleanup: 640 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 641 fence_put(work->fence); 642 kfree(work); 643 return r; 644 } 645 646 static int 647 radeon_crtc_set_config(struct drm_mode_set *set) 648 { 649 struct drm_device *dev; 650 struct radeon_device *rdev; 651 struct drm_crtc *crtc; 652 bool active = false; 653 int ret; 654 655 if (!set || !set->crtc) 656 return -EINVAL; 657 658 dev = set->crtc->dev; 659 660 #ifdef PM_TODO 661 ret = pm_runtime_get_sync(dev->dev); 662 if (ret < 0) 663 return ret; 664 #endif 665 666 ret = drm_crtc_helper_set_config(set); 667 668 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 669 if (crtc->enabled) 670 active = true; 671 672 #ifdef PM_TODO 673 pm_runtime_mark_last_busy(dev->dev); 674 #endif 675 676 rdev = dev->dev_private; 677 /* if we have active crtcs and we don't have a power ref, 678 take the current one */ 679 if (active && !rdev->have_disp_power_ref) { 680 rdev->have_disp_power_ref = true; 681 return ret; 682 } 683 /* if we have no active crtcs, then drop the power ref 684 we got before */ 685 if (!active && rdev->have_disp_power_ref) { 686 #ifdef PM_TODO 687 pm_runtime_put_autosuspend(dev->dev); 688 #endif 689 rdev->have_disp_power_ref = false; 690 } 691 692 /* drop the power reference we got coming in here */ 693 #ifdef PM_TODO 694 pm_runtime_put_autosuspend(dev->dev); 695 #endif 696 return ret; 697 } 698 static const struct drm_crtc_funcs radeon_crtc_funcs = { 699 .cursor_set2 = radeon_crtc_cursor_set2, 700 .cursor_move = radeon_crtc_cursor_move, 701 .gamma_set = radeon_crtc_gamma_set, 702 .set_config = radeon_crtc_set_config, 703 .destroy = radeon_crtc_destroy, 704 .page_flip = radeon_crtc_page_flip, 705 }; 706 707 static void radeon_crtc_init(struct drm_device *dev, int index) 708 { 709 struct radeon_device *rdev = dev->dev_private; 710 struct radeon_crtc *radeon_crtc; 711 int i; 712 713 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 714 if (radeon_crtc == NULL) 715 return; 716 717 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); 718 719 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); 720 radeon_crtc->crtc_id = index; 721 radeon_crtc->flip_queue = create_singlethread_workqueue("radeon-crtc"); 722 rdev->mode_info.crtcs[index] = radeon_crtc; 723 724 if (rdev->family >= CHIP_BONAIRE) { 725 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH; 726 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT; 727 } else { 728 radeon_crtc->max_cursor_width = CURSOR_WIDTH; 729 radeon_crtc->max_cursor_height = CURSOR_HEIGHT; 730 } 731 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width; 732 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height; 733 734 #if 0 735 radeon_crtc->mode_set.crtc = &radeon_crtc->base; 736 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); 737 radeon_crtc->mode_set.num_connectors = 0; 738 #endif 739 740 for (i = 0; i < 256; i++) { 741 radeon_crtc->lut_r[i] = i << 2; 742 radeon_crtc->lut_g[i] = i << 2; 743 radeon_crtc->lut_b[i] = i << 2; 744 } 745 746 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) 747 radeon_atombios_init_crtc(dev, radeon_crtc); 748 else 749 radeon_legacy_init_crtc(dev, radeon_crtc); 750 } 751 752 static const char *encoder_names[38] = { 753 "NONE", 754 "INTERNAL_LVDS", 755 "INTERNAL_TMDS1", 756 "INTERNAL_TMDS2", 757 "INTERNAL_DAC1", 758 "INTERNAL_DAC2", 759 "INTERNAL_SDVOA", 760 "INTERNAL_SDVOB", 761 "SI170B", 762 "CH7303", 763 "CH7301", 764 "INTERNAL_DVO1", 765 "EXTERNAL_SDVOA", 766 "EXTERNAL_SDVOB", 767 "TITFP513", 768 "INTERNAL_LVTM1", 769 "VT1623", 770 "HDMI_SI1930", 771 "HDMI_INTERNAL", 772 "INTERNAL_KLDSCP_TMDS1", 773 "INTERNAL_KLDSCP_DVO1", 774 "INTERNAL_KLDSCP_DAC1", 775 "INTERNAL_KLDSCP_DAC2", 776 "SI178", 777 "MVPU_FPGA", 778 "INTERNAL_DDI", 779 "VT1625", 780 "HDMI_SI1932", 781 "DP_AN9801", 782 "DP_DP501", 783 "INTERNAL_UNIPHY", 784 "INTERNAL_KLDSCP_LVTMA", 785 "INTERNAL_UNIPHY1", 786 "INTERNAL_UNIPHY2", 787 "NUTMEG", 788 "TRAVIS", 789 "INTERNAL_VCE", 790 "INTERNAL_UNIPHY3", 791 }; 792 793 static const char *hpd_names[6] = { 794 "HPD1", 795 "HPD2", 796 "HPD3", 797 "HPD4", 798 "HPD5", 799 "HPD6", 800 }; 801 802 static void radeon_print_display_setup(struct drm_device *dev) 803 { 804 struct drm_connector *connector; 805 struct radeon_connector *radeon_connector; 806 struct drm_encoder *encoder; 807 struct radeon_encoder *radeon_encoder; 808 uint32_t devices; 809 int i = 0; 810 811 DRM_INFO("Radeon Display Connectors\n"); 812 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 813 radeon_connector = to_radeon_connector(connector); 814 DRM_INFO("Connector %d:\n", i); 815 DRM_INFO(" %s\n", connector->name); 816 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 817 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); 818 if (radeon_connector->ddc_bus) { 819 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 820 radeon_connector->ddc_bus->rec.mask_clk_reg, 821 radeon_connector->ddc_bus->rec.mask_data_reg, 822 radeon_connector->ddc_bus->rec.a_clk_reg, 823 radeon_connector->ddc_bus->rec.a_data_reg, 824 radeon_connector->ddc_bus->rec.en_clk_reg, 825 radeon_connector->ddc_bus->rec.en_data_reg, 826 radeon_connector->ddc_bus->rec.y_clk_reg, 827 radeon_connector->ddc_bus->rec.y_data_reg); 828 if (radeon_connector->router.ddc_valid) 829 DRM_INFO(" DDC Router 0x%x/0x%x\n", 830 radeon_connector->router.ddc_mux_control_pin, 831 radeon_connector->router.ddc_mux_state); 832 if (radeon_connector->router.cd_valid) 833 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 834 radeon_connector->router.cd_mux_control_pin, 835 radeon_connector->router.cd_mux_state); 836 } else { 837 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 838 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 839 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 840 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 841 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 842 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 843 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 844 } 845 DRM_INFO(" Encoders:\n"); 846 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 847 radeon_encoder = to_radeon_encoder(encoder); 848 devices = radeon_encoder->devices & radeon_connector->devices; 849 if (devices) { 850 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 851 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); 852 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 853 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); 854 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 855 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); 856 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 857 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); 858 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 859 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); 860 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 861 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); 862 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 863 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); 864 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 865 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); 866 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 867 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); 868 if (devices & ATOM_DEVICE_TV1_SUPPORT) 869 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); 870 if (devices & ATOM_DEVICE_CV_SUPPORT) 871 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); 872 } 873 } 874 i++; 875 } 876 } 877 878 static bool radeon_setup_enc_conn(struct drm_device *dev) 879 { 880 struct radeon_device *rdev = dev->dev_private; 881 bool ret = false; 882 883 if (rdev->bios) { 884 if (rdev->is_atom_bios) { 885 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); 886 if (ret == false) 887 ret = radeon_get_atom_connector_info_from_object_table(dev); 888 } else { 889 ret = radeon_get_legacy_connector_info_from_bios(dev); 890 if (ret == false) 891 ret = radeon_get_legacy_connector_info_from_table(dev); 892 } 893 } else { 894 if (!ASIC_IS_AVIVO(rdev)) 895 ret = radeon_get_legacy_connector_info_from_table(dev); 896 } 897 if (ret) { 898 radeon_setup_encoder_clones(dev); 899 radeon_print_display_setup(dev); 900 } 901 902 return ret; 903 } 904 905 /* avivo */ 906 907 /** 908 * avivo_reduce_ratio - fractional number reduction 909 * 910 * @nom: nominator 911 * @den: denominator 912 * @nom_min: minimum value for nominator 913 * @den_min: minimum value for denominator 914 * 915 * Find the greatest common divisor and apply it on both nominator and 916 * denominator, but make nominator and denominator are at least as large 917 * as their minimum values. 918 */ 919 static void avivo_reduce_ratio(unsigned *nom, unsigned *den, 920 unsigned nom_min, unsigned den_min) 921 { 922 unsigned tmp; 923 924 /* reduce the numbers to a simpler ratio */ 925 tmp = gcd(*nom, *den); 926 *nom /= tmp; 927 *den /= tmp; 928 929 /* make sure nominator is large enough */ 930 if (*nom < nom_min) { 931 tmp = DIV_ROUND_UP(nom_min, *nom); 932 *nom *= tmp; 933 *den *= tmp; 934 } 935 936 /* make sure the denominator is large enough */ 937 if (*den < den_min) { 938 tmp = DIV_ROUND_UP(den_min, *den); 939 *nom *= tmp; 940 *den *= tmp; 941 } 942 } 943 944 /** 945 * avivo_get_fb_ref_div - feedback and ref divider calculation 946 * 947 * @nom: nominator 948 * @den: denominator 949 * @post_div: post divider 950 * @fb_div_max: feedback divider maximum 951 * @ref_div_max: reference divider maximum 952 * @fb_div: resulting feedback divider 953 * @ref_div: resulting reference divider 954 * 955 * Calculate feedback and reference divider for a given post divider. Makes 956 * sure we stay within the limits. 957 */ 958 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, 959 unsigned fb_div_max, unsigned ref_div_max, 960 unsigned *fb_div, unsigned *ref_div) 961 { 962 /* limit reference * post divider to a maximum */ 963 ref_div_max = max(min(100 / post_div, ref_div_max), 1u); 964 965 /* get matching reference and feedback divider */ 966 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); 967 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); 968 969 /* limit fb divider to its maximum */ 970 if (*fb_div > fb_div_max) { 971 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); 972 *fb_div = fb_div_max; 973 } 974 } 975 976 /** 977 * radeon_compute_pll_avivo - compute PLL paramaters 978 * 979 * @pll: information about the PLL 980 * @dot_clock_p: resulting pixel clock 981 * fb_div_p: resulting feedback divider 982 * frac_fb_div_p: fractional part of the feedback divider 983 * ref_div_p: resulting reference divider 984 * post_div_p: resulting reference divider 985 * 986 * Try to calculate the PLL parameters to generate the given frequency: 987 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div) 988 */ 989 void radeon_compute_pll_avivo(struct radeon_pll *pll, 990 u32 freq, 991 u32 *dot_clock_p, 992 u32 *fb_div_p, 993 u32 *frac_fb_div_p, 994 u32 *ref_div_p, 995 u32 *post_div_p) 996 { 997 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? 998 freq : freq / 10; 999 1000 unsigned fb_div_min, fb_div_max, fb_div; 1001 unsigned post_div_min, post_div_max, post_div; 1002 unsigned ref_div_min, ref_div_max, ref_div; 1003 unsigned post_div_best, diff_best; 1004 unsigned nom, den; 1005 1006 /* determine allowed feedback divider range */ 1007 fb_div_min = pll->min_feedback_div; 1008 fb_div_max = pll->max_feedback_div; 1009 1010 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1011 fb_div_min *= 10; 1012 fb_div_max *= 10; 1013 } 1014 1015 /* determine allowed ref divider range */ 1016 if (pll->flags & RADEON_PLL_USE_REF_DIV) 1017 ref_div_min = pll->reference_div; 1018 else 1019 ref_div_min = pll->min_ref_div; 1020 1021 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && 1022 pll->flags & RADEON_PLL_USE_REF_DIV) 1023 ref_div_max = pll->reference_div; 1024 else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 1025 /* fix for problems on RS880 */ 1026 ref_div_max = min(pll->max_ref_div, 7u); 1027 else 1028 ref_div_max = pll->max_ref_div; 1029 1030 /* determine allowed post divider range */ 1031 if (pll->flags & RADEON_PLL_USE_POST_DIV) { 1032 post_div_min = pll->post_div; 1033 post_div_max = pll->post_div; 1034 } else { 1035 unsigned vco_min, vco_max; 1036 1037 if (pll->flags & RADEON_PLL_IS_LCD) { 1038 vco_min = pll->lcd_pll_out_min; 1039 vco_max = pll->lcd_pll_out_max; 1040 } else { 1041 vco_min = pll->pll_out_min; 1042 vco_max = pll->pll_out_max; 1043 } 1044 1045 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1046 vco_min *= 10; 1047 vco_max *= 10; 1048 } 1049 1050 post_div_min = vco_min / target_clock; 1051 if ((target_clock * post_div_min) < vco_min) 1052 ++post_div_min; 1053 if (post_div_min < pll->min_post_div) 1054 post_div_min = pll->min_post_div; 1055 1056 post_div_max = vco_max / target_clock; 1057 if ((target_clock * post_div_max) > vco_max) 1058 --post_div_max; 1059 if (post_div_max > pll->max_post_div) 1060 post_div_max = pll->max_post_div; 1061 } 1062 1063 /* represent the searched ratio as fractional number */ 1064 nom = target_clock; 1065 den = pll->reference_freq; 1066 1067 /* reduce the numbers to a simpler ratio */ 1068 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min); 1069 1070 /* now search for a post divider */ 1071 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 1072 post_div_best = post_div_min; 1073 else 1074 post_div_best = post_div_max; 1075 diff_best = ~0; 1076 1077 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { 1078 unsigned diff; 1079 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, 1080 ref_div_max, &fb_div, &ref_div); 1081 diff = abs(target_clock - (pll->reference_freq * fb_div) / 1082 (ref_div * post_div)); 1083 1084 if (diff < diff_best || (diff == diff_best && 1085 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) { 1086 1087 post_div_best = post_div; 1088 diff_best = diff; 1089 } 1090 } 1091 post_div = post_div_best; 1092 1093 /* get the feedback and reference divider for the optimal value */ 1094 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max, 1095 &fb_div, &ref_div); 1096 1097 /* reduce the numbers to a simpler ratio once more */ 1098 /* this also makes sure that the reference divider is large enough */ 1099 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); 1100 1101 /* avoid high jitter with small fractional dividers */ 1102 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { 1103 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50); 1104 if (fb_div < fb_div_min) { 1105 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div); 1106 fb_div *= tmp; 1107 ref_div *= tmp; 1108 } 1109 } 1110 1111 /* and finally save the result */ 1112 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1113 *fb_div_p = fb_div / 10; 1114 *frac_fb_div_p = fb_div % 10; 1115 } else { 1116 *fb_div_p = fb_div; 1117 *frac_fb_div_p = 0; 1118 } 1119 1120 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + 1121 (pll->reference_freq * *frac_fb_div_p)) / 1122 (ref_div * post_div * 10); 1123 *ref_div_p = ref_div; 1124 *post_div_p = post_div; 1125 1126 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1127 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, 1128 ref_div, post_div); 1129 } 1130 1131 /* pre-avivo */ 1132 static inline uint32_t radeon_div(uint64_t n, uint32_t d) 1133 { 1134 uint64_t mod; 1135 1136 n += d / 2; 1137 1138 mod = do_div(n, d); 1139 return n; 1140 } 1141 1142 void radeon_compute_pll_legacy(struct radeon_pll *pll, 1143 uint64_t freq, 1144 uint32_t *dot_clock_p, 1145 uint32_t *fb_div_p, 1146 uint32_t *frac_fb_div_p, 1147 uint32_t *ref_div_p, 1148 uint32_t *post_div_p) 1149 { 1150 uint32_t min_ref_div = pll->min_ref_div; 1151 uint32_t max_ref_div = pll->max_ref_div; 1152 uint32_t min_post_div = pll->min_post_div; 1153 uint32_t max_post_div = pll->max_post_div; 1154 uint32_t min_fractional_feed_div = 0; 1155 uint32_t max_fractional_feed_div = 0; 1156 uint32_t best_vco = pll->best_vco; 1157 uint32_t best_post_div = 1; 1158 uint32_t best_ref_div = 1; 1159 uint32_t best_feedback_div = 1; 1160 uint32_t best_frac_feedback_div = 0; 1161 uint32_t best_freq = -1; 1162 uint32_t best_error = 0xffffffff; 1163 uint32_t best_vco_diff = 1; 1164 uint32_t post_div; 1165 u32 pll_out_min, pll_out_max; 1166 1167 DRM_DEBUG_KMS("PLL freq %ju %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); 1168 freq = freq * 1000; 1169 1170 if (pll->flags & RADEON_PLL_IS_LCD) { 1171 pll_out_min = pll->lcd_pll_out_min; 1172 pll_out_max = pll->lcd_pll_out_max; 1173 } else { 1174 pll_out_min = pll->pll_out_min; 1175 pll_out_max = pll->pll_out_max; 1176 } 1177 1178 if (pll_out_min > 64800) 1179 pll_out_min = 64800; 1180 1181 if (pll->flags & RADEON_PLL_USE_REF_DIV) 1182 min_ref_div = max_ref_div = pll->reference_div; 1183 else { 1184 while (min_ref_div < max_ref_div-1) { 1185 uint32_t mid = (min_ref_div + max_ref_div) / 2; 1186 uint32_t pll_in = pll->reference_freq / mid; 1187 if (pll_in < pll->pll_in_min) 1188 max_ref_div = mid; 1189 else if (pll_in > pll->pll_in_max) 1190 min_ref_div = mid; 1191 else 1192 break; 1193 } 1194 } 1195 1196 if (pll->flags & RADEON_PLL_USE_POST_DIV) 1197 min_post_div = max_post_div = pll->post_div; 1198 1199 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1200 min_fractional_feed_div = pll->min_frac_feedback_div; 1201 max_fractional_feed_div = pll->max_frac_feedback_div; 1202 } 1203 1204 for (post_div = max_post_div; post_div >= min_post_div; --post_div) { 1205 uint32_t ref_div; 1206 1207 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 1208 continue; 1209 1210 /* legacy radeons only have a few post_divs */ 1211 if (pll->flags & RADEON_PLL_LEGACY) { 1212 if ((post_div == 5) || 1213 (post_div == 7) || 1214 (post_div == 9) || 1215 (post_div == 10) || 1216 (post_div == 11) || 1217 (post_div == 13) || 1218 (post_div == 14) || 1219 (post_div == 15)) 1220 continue; 1221 } 1222 1223 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { 1224 uint32_t feedback_div, current_freq = 0, error, vco_diff; 1225 uint32_t pll_in = pll->reference_freq / ref_div; 1226 uint32_t min_feed_div = pll->min_feedback_div; 1227 uint32_t max_feed_div = pll->max_feedback_div + 1; 1228 1229 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) 1230 continue; 1231 1232 while (min_feed_div < max_feed_div) { 1233 uint32_t vco; 1234 uint32_t min_frac_feed_div = min_fractional_feed_div; 1235 uint32_t max_frac_feed_div = max_fractional_feed_div + 1; 1236 uint32_t frac_feedback_div; 1237 uint64_t tmp; 1238 1239 feedback_div = (min_feed_div + max_feed_div) / 2; 1240 1241 tmp = (uint64_t)pll->reference_freq * feedback_div; 1242 vco = radeon_div(tmp, ref_div); 1243 1244 if (vco < pll_out_min) { 1245 min_feed_div = feedback_div + 1; 1246 continue; 1247 } else if (vco > pll_out_max) { 1248 max_feed_div = feedback_div; 1249 continue; 1250 } 1251 1252 while (min_frac_feed_div < max_frac_feed_div) { 1253 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; 1254 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; 1255 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; 1256 current_freq = radeon_div(tmp, ref_div * post_div); 1257 1258 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 1259 if (freq < current_freq) 1260 error = 0xffffffff; 1261 else 1262 error = freq - current_freq; 1263 } else 1264 error = abs(current_freq - freq); 1265 vco_diff = abs(vco - best_vco); 1266 1267 if ((best_vco == 0 && error < best_error) || 1268 (best_vco != 0 && 1269 ((best_error > 100 && error < best_error - 100) || 1270 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { 1271 best_post_div = post_div; 1272 best_ref_div = ref_div; 1273 best_feedback_div = feedback_div; 1274 best_frac_feedback_div = frac_feedback_div; 1275 best_freq = current_freq; 1276 best_error = error; 1277 best_vco_diff = vco_diff; 1278 } else if (current_freq == freq) { 1279 if (best_freq == -1) { 1280 best_post_div = post_div; 1281 best_ref_div = ref_div; 1282 best_feedback_div = feedback_div; 1283 best_frac_feedback_div = frac_feedback_div; 1284 best_freq = current_freq; 1285 best_error = error; 1286 best_vco_diff = vco_diff; 1287 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 1288 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 1289 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 1290 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 1291 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 1292 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 1293 best_post_div = post_div; 1294 best_ref_div = ref_div; 1295 best_feedback_div = feedback_div; 1296 best_frac_feedback_div = frac_feedback_div; 1297 best_freq = current_freq; 1298 best_error = error; 1299 best_vco_diff = vco_diff; 1300 } 1301 } 1302 if (current_freq < freq) 1303 min_frac_feed_div = frac_feedback_div + 1; 1304 else 1305 max_frac_feed_div = frac_feedback_div; 1306 } 1307 if (current_freq < freq) 1308 min_feed_div = feedback_div + 1; 1309 else 1310 max_feed_div = feedback_div; 1311 } 1312 } 1313 } 1314 1315 *dot_clock_p = best_freq / 10000; 1316 *fb_div_p = best_feedback_div; 1317 *frac_fb_div_p = best_frac_feedback_div; 1318 *ref_div_p = best_ref_div; 1319 *post_div_p = best_post_div; 1320 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1321 (long long)freq, 1322 best_freq / 1000, best_feedback_div, best_frac_feedback_div, 1323 best_ref_div, best_post_div); 1324 1325 } 1326 1327 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) 1328 { 1329 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1330 1331 if (radeon_fb->obj) { 1332 drm_gem_object_unreference_unlocked(radeon_fb->obj); 1333 } 1334 drm_framebuffer_cleanup(fb); 1335 kfree(radeon_fb); 1336 } 1337 1338 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, 1339 struct drm_file *file_priv, 1340 unsigned int *handle) 1341 { 1342 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1343 1344 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); 1345 } 1346 1347 static const struct drm_framebuffer_funcs radeon_fb_funcs = { 1348 .destroy = radeon_user_framebuffer_destroy, 1349 .create_handle = radeon_user_framebuffer_create_handle, 1350 }; 1351 1352 int 1353 radeon_framebuffer_init(struct drm_device *dev, 1354 struct radeon_framebuffer *rfb, 1355 const struct drm_mode_fb_cmd2 *mode_cmd, 1356 struct drm_gem_object *obj) 1357 { 1358 int ret; 1359 rfb->obj = obj; 1360 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); 1361 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); 1362 if (ret) { 1363 rfb->obj = NULL; 1364 return ret; 1365 } 1366 return 0; 1367 } 1368 1369 static struct drm_framebuffer * 1370 radeon_user_framebuffer_create(struct drm_device *dev, 1371 struct drm_file *file_priv, 1372 const struct drm_mode_fb_cmd2 *mode_cmd) 1373 { 1374 struct drm_gem_object *obj; 1375 struct radeon_framebuffer *radeon_fb; 1376 int ret; 1377 1378 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); 1379 if (obj == NULL) { 1380 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 1381 "can't create framebuffer\n", mode_cmd->handles[0]); 1382 return ERR_PTR(-ENOENT); 1383 } 1384 1385 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ 1386 if (obj->import_attach) { 1387 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n"); 1388 return ERR_PTR(-EINVAL); 1389 } 1390 1391 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); 1392 if (radeon_fb == NULL) { 1393 drm_gem_object_unreference_unlocked(obj); 1394 return ERR_PTR(-ENOMEM); 1395 } 1396 1397 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj); 1398 if (ret) { 1399 kfree(radeon_fb); 1400 drm_gem_object_unreference_unlocked(obj); 1401 return ERR_PTR(ret); 1402 } 1403 1404 return &radeon_fb->base; 1405 } 1406 1407 static void radeon_output_poll_changed(struct drm_device *dev) 1408 { 1409 struct radeon_device *rdev = dev->dev_private; 1410 radeon_fb_output_poll_changed(rdev); 1411 } 1412 1413 static const struct drm_mode_config_funcs radeon_mode_funcs = { 1414 .fb_create = radeon_user_framebuffer_create, 1415 .output_poll_changed = radeon_output_poll_changed 1416 }; 1417 1418 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = 1419 { { 0, "driver" }, 1420 { 1, "bios" }, 1421 }; 1422 1423 static struct drm_prop_enum_list radeon_tv_std_enum_list[] = 1424 { { TV_STD_NTSC, "ntsc" }, 1425 { TV_STD_PAL, "pal" }, 1426 { TV_STD_PAL_M, "pal-m" }, 1427 { TV_STD_PAL_60, "pal-60" }, 1428 { TV_STD_NTSC_J, "ntsc-j" }, 1429 { TV_STD_SCART_PAL, "scart-pal" }, 1430 { TV_STD_PAL_CN, "pal-cn" }, 1431 { TV_STD_SECAM, "secam" }, 1432 }; 1433 1434 static struct drm_prop_enum_list radeon_underscan_enum_list[] = 1435 { { UNDERSCAN_OFF, "off" }, 1436 { UNDERSCAN_ON, "on" }, 1437 { UNDERSCAN_AUTO, "auto" }, 1438 }; 1439 1440 static struct drm_prop_enum_list radeon_audio_enum_list[] = 1441 { { RADEON_AUDIO_DISABLE, "off" }, 1442 { RADEON_AUDIO_ENABLE, "on" }, 1443 { RADEON_AUDIO_AUTO, "auto" }, 1444 }; 1445 1446 /* XXX support different dither options? spatial, temporal, both, etc. */ 1447 static struct drm_prop_enum_list radeon_dither_enum_list[] = 1448 { { RADEON_FMT_DITHER_DISABLE, "off" }, 1449 { RADEON_FMT_DITHER_ENABLE, "on" }, 1450 }; 1451 1452 static struct drm_prop_enum_list radeon_output_csc_enum_list[] = 1453 { { RADEON_OUTPUT_CSC_BYPASS, "bypass" }, 1454 { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" }, 1455 { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" }, 1456 { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" }, 1457 }; 1458 1459 static int radeon_modeset_create_props(struct radeon_device *rdev) 1460 { 1461 int sz; 1462 1463 if (rdev->is_atom_bios) { 1464 rdev->mode_info.coherent_mode_property = 1465 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1); 1466 if (!rdev->mode_info.coherent_mode_property) 1467 return -ENOMEM; 1468 } 1469 1470 if (!ASIC_IS_AVIVO(rdev)) { 1471 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); 1472 rdev->mode_info.tmds_pll_property = 1473 drm_property_create_enum(rdev->ddev, 0, 1474 "tmds_pll", 1475 radeon_tmds_pll_enum_list, sz); 1476 } 1477 1478 rdev->mode_info.load_detect_property = 1479 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1); 1480 if (!rdev->mode_info.load_detect_property) 1481 return -ENOMEM; 1482 1483 drm_mode_create_scaling_mode_property(rdev->ddev); 1484 1485 sz = ARRAY_SIZE(radeon_tv_std_enum_list); 1486 rdev->mode_info.tv_std_property = 1487 drm_property_create_enum(rdev->ddev, 0, 1488 "tv standard", 1489 radeon_tv_std_enum_list, sz); 1490 1491 sz = ARRAY_SIZE(radeon_underscan_enum_list); 1492 rdev->mode_info.underscan_property = 1493 drm_property_create_enum(rdev->ddev, 0, 1494 "underscan", 1495 radeon_underscan_enum_list, sz); 1496 1497 rdev->mode_info.underscan_hborder_property = 1498 drm_property_create_range(rdev->ddev, 0, 1499 "underscan hborder", 0, 128); 1500 if (!rdev->mode_info.underscan_hborder_property) 1501 return -ENOMEM; 1502 1503 rdev->mode_info.underscan_vborder_property = 1504 drm_property_create_range(rdev->ddev, 0, 1505 "underscan vborder", 0, 128); 1506 if (!rdev->mode_info.underscan_vborder_property) 1507 return -ENOMEM; 1508 1509 sz = ARRAY_SIZE(radeon_audio_enum_list); 1510 rdev->mode_info.audio_property = 1511 drm_property_create_enum(rdev->ddev, 0, 1512 "audio", 1513 radeon_audio_enum_list, sz); 1514 1515 sz = ARRAY_SIZE(radeon_dither_enum_list); 1516 rdev->mode_info.dither_property = 1517 drm_property_create_enum(rdev->ddev, 0, 1518 "dither", 1519 radeon_dither_enum_list, sz); 1520 1521 sz = ARRAY_SIZE(radeon_output_csc_enum_list); 1522 rdev->mode_info.output_csc_property = 1523 drm_property_create_enum(rdev->ddev, 0, 1524 "output_csc", 1525 radeon_output_csc_enum_list, sz); 1526 1527 return 0; 1528 } 1529 1530 void radeon_update_display_priority(struct radeon_device *rdev) 1531 { 1532 /* adjustment options for the display watermarks */ 1533 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { 1534 /* set display priority to high for r3xx, rv515 chips 1535 * this avoids flickering due to underflow to the 1536 * display controllers during heavy acceleration. 1537 * Don't force high on rs4xx igp chips as it seems to 1538 * affect the sound card. See kernel bug 15982. 1539 */ 1540 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && 1541 !(rdev->flags & RADEON_IS_IGP)) 1542 rdev->disp_priority = 2; 1543 else 1544 rdev->disp_priority = 0; 1545 } else 1546 rdev->disp_priority = radeon_disp_priority; 1547 1548 } 1549 1550 /* 1551 * Allocate hdmi structs and determine register offsets 1552 */ 1553 static void radeon_afmt_init(struct radeon_device *rdev) 1554 { 1555 int i; 1556 1557 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) 1558 rdev->mode_info.afmt[i] = NULL; 1559 1560 if (ASIC_IS_NODCE(rdev)) { 1561 /* nothing to do */ 1562 } else if (ASIC_IS_DCE4(rdev)) { 1563 static uint32_t eg_offsets[] = { 1564 EVERGREEN_CRTC0_REGISTER_OFFSET, 1565 EVERGREEN_CRTC1_REGISTER_OFFSET, 1566 EVERGREEN_CRTC2_REGISTER_OFFSET, 1567 EVERGREEN_CRTC3_REGISTER_OFFSET, 1568 EVERGREEN_CRTC4_REGISTER_OFFSET, 1569 EVERGREEN_CRTC5_REGISTER_OFFSET, 1570 0x13830 - 0x7030, 1571 }; 1572 int num_afmt; 1573 1574 /* DCE8 has 7 audio blocks tied to DIG encoders */ 1575 /* DCE6 has 6 audio blocks tied to DIG encoders */ 1576 /* DCE4/5 has 6 audio blocks tied to DIG encoders */ 1577 /* DCE4.1 has 2 audio blocks tied to DIG encoders */ 1578 if (ASIC_IS_DCE8(rdev)) 1579 num_afmt = 7; 1580 else if (ASIC_IS_DCE6(rdev)) 1581 num_afmt = 6; 1582 else if (ASIC_IS_DCE5(rdev)) 1583 num_afmt = 6; 1584 else if (ASIC_IS_DCE41(rdev)) 1585 num_afmt = 2; 1586 else /* DCE4 */ 1587 num_afmt = 6; 1588 1589 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets)); 1590 for (i = 0; i < num_afmt; i++) { 1591 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1592 if (rdev->mode_info.afmt[i]) { 1593 rdev->mode_info.afmt[i]->offset = eg_offsets[i]; 1594 rdev->mode_info.afmt[i]->id = i; 1595 } 1596 } 1597 } else if (ASIC_IS_DCE3(rdev)) { 1598 /* DCE3.x has 2 audio blocks tied to DIG encoders */ 1599 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1600 if (rdev->mode_info.afmt[0]) { 1601 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0; 1602 rdev->mode_info.afmt[0]->id = 0; 1603 } 1604 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1605 if (rdev->mode_info.afmt[1]) { 1606 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1; 1607 rdev->mode_info.afmt[1]->id = 1; 1608 } 1609 } else if (ASIC_IS_DCE2(rdev)) { 1610 /* DCE2 has at least 1 routable audio block */ 1611 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1612 if (rdev->mode_info.afmt[0]) { 1613 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0; 1614 rdev->mode_info.afmt[0]->id = 0; 1615 } 1616 /* r6xx has 2 routable audio blocks */ 1617 if (rdev->family >= CHIP_R600) { 1618 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1619 if (rdev->mode_info.afmt[1]) { 1620 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1; 1621 rdev->mode_info.afmt[1]->id = 1; 1622 } 1623 } 1624 } 1625 } 1626 1627 static void radeon_afmt_fini(struct radeon_device *rdev) 1628 { 1629 int i; 1630 1631 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) { 1632 kfree(rdev->mode_info.afmt[i]); 1633 rdev->mode_info.afmt[i] = NULL; 1634 } 1635 } 1636 1637 int radeon_modeset_init(struct radeon_device *rdev) 1638 { 1639 int i; 1640 int ret; 1641 1642 drm_mode_config_init(rdev->ddev); 1643 rdev->mode_info.mode_config_initialized = true; 1644 1645 rdev->ddev->mode_config.funcs = &radeon_mode_funcs; 1646 1647 if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600) 1648 rdev->ddev->mode_config.async_page_flip = true; 1649 1650 if (ASIC_IS_DCE5(rdev)) { 1651 rdev->ddev->mode_config.max_width = 16384; 1652 rdev->ddev->mode_config.max_height = 16384; 1653 } else if (ASIC_IS_AVIVO(rdev)) { 1654 rdev->ddev->mode_config.max_width = 8192; 1655 rdev->ddev->mode_config.max_height = 8192; 1656 } else { 1657 rdev->ddev->mode_config.max_width = 4096; 1658 rdev->ddev->mode_config.max_height = 4096; 1659 } 1660 1661 rdev->ddev->mode_config.preferred_depth = 24; 1662 rdev->ddev->mode_config.prefer_shadow = 1; 1663 1664 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; 1665 1666 ret = radeon_modeset_create_props(rdev); 1667 if (ret) { 1668 return ret; 1669 } 1670 1671 /* init i2c buses */ 1672 radeon_i2c_init(rdev); 1673 1674 /* check combios for a valid hardcoded EDID - Sun servers */ 1675 if (!rdev->is_atom_bios) { 1676 /* check for hardcoded EDID in BIOS */ 1677 radeon_combios_check_hardcoded_edid(rdev); 1678 } 1679 1680 /* allocate crtcs */ 1681 for (i = 0; i < rdev->num_crtc; i++) { 1682 radeon_crtc_init(rdev->ddev, i); 1683 } 1684 1685 /* okay we should have all the bios connectors */ 1686 ret = radeon_setup_enc_conn(rdev->ddev); 1687 if (!ret) { 1688 return ret; 1689 } 1690 1691 /* init dig PHYs, disp eng pll */ 1692 if (rdev->is_atom_bios) { 1693 radeon_atom_encoder_init(rdev); 1694 radeon_atom_disp_eng_pll_init(rdev); 1695 } 1696 1697 /* initialize hpd */ 1698 radeon_hpd_init(rdev); 1699 1700 /* setup afmt */ 1701 radeon_afmt_init(rdev); 1702 1703 radeon_fbdev_init(rdev); 1704 drm_kms_helper_poll_init(rdev->ddev); 1705 1706 /* do pm late init */ 1707 ret = radeon_pm_late_init(rdev); 1708 1709 return 0; 1710 } 1711 1712 void radeon_modeset_fini(struct radeon_device *rdev) 1713 { 1714 radeon_fbdev_fini(rdev); 1715 kfree(rdev->mode_info.bios_hardcoded_edid); 1716 1717 /* free i2c buses */ 1718 radeon_i2c_fini(rdev); 1719 1720 if (rdev->mode_info.mode_config_initialized) { 1721 radeon_afmt_fini(rdev); 1722 drm_kms_helper_poll_fini(rdev->ddev); 1723 radeon_hpd_fini(rdev); 1724 drm_mode_config_cleanup(rdev->ddev); 1725 rdev->mode_info.mode_config_initialized = false; 1726 } 1727 } 1728 1729 static bool is_hdtv_mode(const struct drm_display_mode *mode) 1730 { 1731 /* try and guess if this is a tv or a monitor */ 1732 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 1733 (mode->vdisplay == 576) || /* 576p */ 1734 (mode->vdisplay == 720) || /* 720p */ 1735 (mode->vdisplay == 1080)) /* 1080p */ 1736 return true; 1737 else 1738 return false; 1739 } 1740 1741 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 1742 const struct drm_display_mode *mode, 1743 struct drm_display_mode *adjusted_mode) 1744 { 1745 struct drm_device *dev = crtc->dev; 1746 struct radeon_device *rdev = dev->dev_private; 1747 struct drm_encoder *encoder; 1748 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1749 struct radeon_encoder *radeon_encoder; 1750 struct drm_connector *connector; 1751 struct radeon_connector *radeon_connector; 1752 bool first = true; 1753 u32 src_v = 1, dst_v = 1; 1754 u32 src_h = 1, dst_h = 1; 1755 1756 radeon_crtc->h_border = 0; 1757 radeon_crtc->v_border = 0; 1758 1759 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1760 if (encoder->crtc != crtc) 1761 continue; 1762 radeon_encoder = to_radeon_encoder(encoder); 1763 connector = radeon_get_connector_for_encoder(encoder); 1764 radeon_connector = to_radeon_connector(connector); 1765 1766 if (first) { 1767 /* set scaling */ 1768 if (radeon_encoder->rmx_type == RMX_OFF) 1769 radeon_crtc->rmx_type = RMX_OFF; 1770 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || 1771 mode->vdisplay < radeon_encoder->native_mode.vdisplay) 1772 radeon_crtc->rmx_type = radeon_encoder->rmx_type; 1773 else 1774 radeon_crtc->rmx_type = RMX_OFF; 1775 /* copy native mode */ 1776 memcpy(&radeon_crtc->native_mode, 1777 &radeon_encoder->native_mode, 1778 sizeof(struct drm_display_mode)); 1779 src_v = crtc->mode.vdisplay; 1780 dst_v = radeon_crtc->native_mode.vdisplay; 1781 src_h = crtc->mode.hdisplay; 1782 dst_h = radeon_crtc->native_mode.hdisplay; 1783 1784 /* fix up for overscan on hdmi */ 1785 if (ASIC_IS_AVIVO(rdev) && 1786 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 1787 ((radeon_encoder->underscan_type == UNDERSCAN_ON) || 1788 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && 1789 drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 1790 is_hdtv_mode(mode)))) { 1791 if (radeon_encoder->underscan_hborder != 0) 1792 radeon_crtc->h_border = radeon_encoder->underscan_hborder; 1793 else 1794 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; 1795 if (radeon_encoder->underscan_vborder != 0) 1796 radeon_crtc->v_border = radeon_encoder->underscan_vborder; 1797 else 1798 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; 1799 radeon_crtc->rmx_type = RMX_FULL; 1800 src_v = crtc->mode.vdisplay; 1801 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); 1802 src_h = crtc->mode.hdisplay; 1803 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); 1804 } 1805 first = false; 1806 } else { 1807 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { 1808 /* WARNING: Right now this can't happen but 1809 * in the future we need to check that scaling 1810 * are consistent across different encoder 1811 * (ie all encoder can work with the same 1812 * scaling). 1813 */ 1814 DRM_ERROR("Scaling not consistent across encoder.\n"); 1815 return false; 1816 } 1817 } 1818 } 1819 if (radeon_crtc->rmx_type != RMX_OFF) { 1820 fixed20_12 a, b; 1821 a.full = dfixed_const(src_v); 1822 b.full = dfixed_const(dst_v); 1823 radeon_crtc->vsc.full = dfixed_div(a, b); 1824 a.full = dfixed_const(src_h); 1825 b.full = dfixed_const(dst_h); 1826 radeon_crtc->hsc.full = dfixed_div(a, b); 1827 } else { 1828 radeon_crtc->vsc.full = dfixed_const(1); 1829 radeon_crtc->hsc.full = dfixed_const(1); 1830 } 1831 return true; 1832 } 1833 1834 /* 1835 * Retrieve current video scanout position of crtc on a given gpu, and 1836 * an optional accurate timestamp of when query happened. 1837 * 1838 * \param dev Device to query. 1839 * \param crtc Crtc to query. 1840 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 1841 * For driver internal use only also supports these flags: 1842 * 1843 * USE_REAL_VBLANKSTART to use the real start of vblank instead 1844 * of a fudged earlier start of vblank. 1845 * 1846 * GET_DISTANCE_TO_VBLANKSTART to return distance to the 1847 * fudged earlier start of vblank in *vpos and the distance 1848 * to true start of vblank in *hpos. 1849 * 1850 * \param *vpos Location where vertical scanout position should be stored. 1851 * \param *hpos Location where horizontal scanout position should go. 1852 * \param *stime Target location for timestamp taken immediately before 1853 * scanout position query. Can be NULL to skip timestamp. 1854 * \param *etime Target location for timestamp taken immediately after 1855 * scanout position query. Can be NULL to skip timestamp. 1856 * 1857 * Returns vpos as a positive number while in active scanout area. 1858 * Returns vpos as a negative number inside vblank, counting the number 1859 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 1860 * until start of active scanout / end of vblank." 1861 * 1862 * \return Flags, or'ed together as follows: 1863 * 1864 * DRM_SCANOUTPOS_VALID = Query successful. 1865 * DRM_SCANOUTPOS_INVBL = Inside vblank. 1866 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 1867 * this flag means that returned position may be offset by a constant but 1868 * unknown small number of scanlines wrt. real scanout position. 1869 * 1870 */ 1871 int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 1872 unsigned int flags, int *vpos, int *hpos, 1873 ktime_t *stime, ktime_t *etime, 1874 const struct drm_display_mode *mode) 1875 { 1876 u32 stat_crtc = 0, vbl = 0, position = 0; 1877 int vbl_start, vbl_end, vtotal, ret = 0; 1878 bool in_vbl = true; 1879 1880 struct radeon_device *rdev = dev->dev_private; 1881 1882 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 1883 1884 /* Get optional system timestamp before query. */ 1885 if (stime) 1886 *stime = ktime_get(); 1887 1888 if (ASIC_IS_DCE4(rdev)) { 1889 if (pipe == 0) { 1890 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1891 EVERGREEN_CRTC0_REGISTER_OFFSET); 1892 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1893 EVERGREEN_CRTC0_REGISTER_OFFSET); 1894 ret |= DRM_SCANOUTPOS_VALID; 1895 } 1896 if (pipe == 1) { 1897 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1898 EVERGREEN_CRTC1_REGISTER_OFFSET); 1899 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1900 EVERGREEN_CRTC1_REGISTER_OFFSET); 1901 ret |= DRM_SCANOUTPOS_VALID; 1902 } 1903 if (pipe == 2) { 1904 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1905 EVERGREEN_CRTC2_REGISTER_OFFSET); 1906 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1907 EVERGREEN_CRTC2_REGISTER_OFFSET); 1908 ret |= DRM_SCANOUTPOS_VALID; 1909 } 1910 if (pipe == 3) { 1911 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1912 EVERGREEN_CRTC3_REGISTER_OFFSET); 1913 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1914 EVERGREEN_CRTC3_REGISTER_OFFSET); 1915 ret |= DRM_SCANOUTPOS_VALID; 1916 } 1917 if (pipe == 4) { 1918 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1919 EVERGREEN_CRTC4_REGISTER_OFFSET); 1920 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1921 EVERGREEN_CRTC4_REGISTER_OFFSET); 1922 ret |= DRM_SCANOUTPOS_VALID; 1923 } 1924 if (pipe == 5) { 1925 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1926 EVERGREEN_CRTC5_REGISTER_OFFSET); 1927 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1928 EVERGREEN_CRTC5_REGISTER_OFFSET); 1929 ret |= DRM_SCANOUTPOS_VALID; 1930 } 1931 } else if (ASIC_IS_AVIVO(rdev)) { 1932 if (pipe == 0) { 1933 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); 1934 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); 1935 ret |= DRM_SCANOUTPOS_VALID; 1936 } 1937 if (pipe == 1) { 1938 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); 1939 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); 1940 ret |= DRM_SCANOUTPOS_VALID; 1941 } 1942 } else { 1943 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ 1944 if (pipe == 0) { 1945 /* Assume vbl_end == 0, get vbl_start from 1946 * upper 16 bits. 1947 */ 1948 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & 1949 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1950 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ 1951 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1952 stat_crtc = RREG32(RADEON_CRTC_STATUS); 1953 if (!(stat_crtc & 1)) 1954 in_vbl = false; 1955 1956 ret |= DRM_SCANOUTPOS_VALID; 1957 } 1958 if (pipe == 1) { 1959 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & 1960 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1961 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1962 stat_crtc = RREG32(RADEON_CRTC2_STATUS); 1963 if (!(stat_crtc & 1)) 1964 in_vbl = false; 1965 1966 ret |= DRM_SCANOUTPOS_VALID; 1967 } 1968 } 1969 1970 /* Get optional system timestamp after query. */ 1971 if (etime) 1972 *etime = ktime_get(); 1973 1974 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 1975 1976 /* Decode into vertical and horizontal scanout position. */ 1977 *vpos = position & 0x1fff; 1978 *hpos = (position >> 16) & 0x1fff; 1979 1980 /* Valid vblank area boundaries from gpu retrieved? */ 1981 if (vbl > 0) { 1982 /* Yes: Decode. */ 1983 ret |= DRM_SCANOUTPOS_ACCURATE; 1984 vbl_start = vbl & 0x1fff; 1985 vbl_end = (vbl >> 16) & 0x1fff; 1986 } 1987 else { 1988 /* No: Fake something reasonable which gives at least ok results. */ 1989 vbl_start = mode->crtc_vdisplay; 1990 vbl_end = 0; 1991 } 1992 1993 /* Called from driver internal vblank counter query code? */ 1994 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1995 /* Caller wants distance from real vbl_start in *hpos */ 1996 *hpos = *vpos - vbl_start; 1997 } 1998 1999 /* Fudge vblank to start a few scanlines earlier to handle the 2000 * problem that vblank irqs fire a few scanlines before start 2001 * of vblank. Some driver internal callers need the true vblank 2002 * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 2003 * 2004 * The cause of the "early" vblank irq is that the irq is triggered 2005 * by the line buffer logic when the line buffer read position enters 2006 * the vblank, whereas our crtc scanout position naturally lags the 2007 * line buffer read position. 2008 */ 2009 if (!(flags & USE_REAL_VBLANKSTART)) 2010 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 2011 2012 /* Test scanout position against vblank region. */ 2013 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 2014 in_vbl = false; 2015 2016 /* In vblank? */ 2017 if (in_vbl) 2018 ret |= DRM_SCANOUTPOS_IN_VBLANK; 2019 2020 /* Called from driver internal vblank counter query code? */ 2021 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 2022 /* Caller wants distance from fudged earlier vbl_start */ 2023 *vpos -= vbl_start; 2024 return ret; 2025 } 2026 2027 /* Check if inside vblank area and apply corrective offsets: 2028 * vpos will then be >=0 in video scanout area, but negative 2029 * within vblank area, counting down the number of lines until 2030 * start of scanout. 2031 */ 2032 2033 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 2034 if (in_vbl && (*vpos >= vbl_start)) { 2035 vtotal = mode->crtc_vtotal; 2036 *vpos = *vpos - vtotal; 2037 } 2038 2039 /* Correct for shifted end of vbl at vbl_end. */ 2040 *vpos = *vpos - vbl_end; 2041 2042 return ret; 2043 } 2044