1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/radeon_drm.h> 28 #include "radeon.h" 29 30 #include "atom.h" 31 32 #include <linux/pm_runtime.h> 33 #include <drm/drm_crtc_helper.h> 34 #include <drm/drm_plane_helper.h> 35 #include <drm/drm_edid.h> 36 37 #include <linux/gcd.h> 38 39 static void avivo_crtc_load_lut(struct drm_crtc *crtc) 40 { 41 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 42 struct drm_device *dev = crtc->dev; 43 struct radeon_device *rdev = dev->dev_private; 44 int i; 45 46 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 47 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); 48 49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 52 53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 56 57 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); 58 WREG32(AVIVO_DC_LUT_RW_MODE, 0); 59 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); 60 61 WREG8(AVIVO_DC_LUT_RW_INDEX, 0); 62 for (i = 0; i < 256; i++) { 63 WREG32(AVIVO_DC_LUT_30_COLOR, 64 (radeon_crtc->lut_r[i] << 20) | 65 (radeon_crtc->lut_g[i] << 10) | 66 (radeon_crtc->lut_b[i] << 0)); 67 } 68 69 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */ 70 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1); 71 } 72 73 static void dce4_crtc_load_lut(struct drm_crtc *crtc) 74 { 75 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 76 struct drm_device *dev = crtc->dev; 77 struct radeon_device *rdev = dev->dev_private; 78 int i; 79 80 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 81 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 82 83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 84 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 85 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 86 87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 88 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 89 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 90 91 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 92 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 93 94 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 95 for (i = 0; i < 256; i++) { 96 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 97 (radeon_crtc->lut_r[i] << 20) | 98 (radeon_crtc->lut_g[i] << 10) | 99 (radeon_crtc->lut_b[i] << 0)); 100 } 101 } 102 103 static void dce5_crtc_load_lut(struct drm_crtc *crtc) 104 { 105 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 106 struct drm_device *dev = crtc->dev; 107 struct radeon_device *rdev = dev->dev_private; 108 int i; 109 110 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 111 112 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 113 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | 114 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); 115 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, 116 NI_GRPH_PRESCALE_BYPASS); 117 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, 118 NI_OVL_PRESCALE_BYPASS); 119 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, 120 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | 121 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); 122 123 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 124 125 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 126 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 127 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 128 129 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 130 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 131 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 132 133 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 134 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 135 136 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 137 for (i = 0; i < 256; i++) { 138 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 139 (radeon_crtc->lut_r[i] << 20) | 140 (radeon_crtc->lut_g[i] << 10) | 141 (radeon_crtc->lut_b[i] << 0)); 142 } 143 144 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, 145 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 146 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 147 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 148 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); 149 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, 150 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | 151 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); 152 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, 153 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | 154 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); 155 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 156 (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) | 157 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); 158 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 159 WREG32(0x6940 + radeon_crtc->crtc_offset, 0); 160 if (ASIC_IS_DCE8(rdev)) { 161 /* XXX this only needs to be programmed once per crtc at startup, 162 * not sure where the best place for it is 163 */ 164 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset, 165 CIK_CURSOR_ALPHA_BLND_ENA); 166 } 167 } 168 169 static void legacy_crtc_load_lut(struct drm_crtc *crtc) 170 { 171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 172 struct drm_device *dev = crtc->dev; 173 struct radeon_device *rdev = dev->dev_private; 174 int i; 175 uint32_t dac2_cntl; 176 177 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 178 if (radeon_crtc->crtc_id == 0) 179 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; 180 else 181 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; 182 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 183 184 WREG8(RADEON_PALETTE_INDEX, 0); 185 for (i = 0; i < 256; i++) { 186 WREG32(RADEON_PALETTE_30_DATA, 187 (radeon_crtc->lut_r[i] << 20) | 188 (radeon_crtc->lut_g[i] << 10) | 189 (radeon_crtc->lut_b[i] << 0)); 190 } 191 } 192 193 void radeon_crtc_load_lut(struct drm_crtc *crtc) 194 { 195 struct drm_device *dev = crtc->dev; 196 struct radeon_device *rdev = dev->dev_private; 197 198 if (!crtc->enabled) 199 return; 200 201 if (ASIC_IS_DCE5(rdev)) 202 dce5_crtc_load_lut(crtc); 203 else if (ASIC_IS_DCE4(rdev)) 204 dce4_crtc_load_lut(crtc); 205 else if (ASIC_IS_AVIVO(rdev)) 206 avivo_crtc_load_lut(crtc); 207 else 208 legacy_crtc_load_lut(crtc); 209 } 210 211 /** Sets the color ramps on behalf of fbcon */ 212 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 213 u16 blue, int regno) 214 { 215 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 216 217 radeon_crtc->lut_r[regno] = red >> 6; 218 radeon_crtc->lut_g[regno] = green >> 6; 219 radeon_crtc->lut_b[regno] = blue >> 6; 220 } 221 222 /** Gets the color ramps on behalf of fbcon */ 223 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 224 u16 *blue, int regno) 225 { 226 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 227 228 *red = radeon_crtc->lut_r[regno] << 6; 229 *green = radeon_crtc->lut_g[regno] << 6; 230 *blue = radeon_crtc->lut_b[regno] << 6; 231 } 232 233 static int radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 234 u16 *blue, uint32_t size) 235 { 236 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 237 int i; 238 239 /* userspace palettes are always correct as is */ 240 for (i = 0; i < size; i++) { 241 radeon_crtc->lut_r[i] = red[i] >> 6; 242 radeon_crtc->lut_g[i] = green[i] >> 6; 243 radeon_crtc->lut_b[i] = blue[i] >> 6; 244 } 245 radeon_crtc_load_lut(crtc); 246 247 return 0; 248 } 249 250 static void radeon_crtc_destroy(struct drm_crtc *crtc) 251 { 252 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 253 254 drm_crtc_cleanup(crtc); 255 destroy_workqueue(radeon_crtc->flip_queue); 256 kfree(radeon_crtc); 257 } 258 259 /** 260 * radeon_unpin_work_func - unpin old buffer object 261 * 262 * @__work - kernel work item 263 * 264 * Unpin the old frame buffer object outside of the interrupt handler 265 */ 266 static void radeon_unpin_work_func(struct work_struct *__work) 267 { 268 struct radeon_flip_work *work = 269 container_of(__work, struct radeon_flip_work, unpin_work); 270 int r; 271 272 /* unpin of the old buffer */ 273 r = radeon_bo_reserve(work->old_rbo, false); 274 if (likely(r == 0)) { 275 r = radeon_bo_unpin(work->old_rbo); 276 if (unlikely(r != 0)) { 277 DRM_ERROR("failed to unpin buffer after flip\n"); 278 } 279 radeon_bo_unreserve(work->old_rbo); 280 } else 281 DRM_ERROR("failed to reserve buffer after flip\n"); 282 283 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 284 kfree(work); 285 } 286 287 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id) 288 { 289 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 290 unsigned long flags; 291 u32 update_pending; 292 int vpos, hpos; 293 294 /* can happen during initialization */ 295 if (radeon_crtc == NULL) 296 return; 297 298 /* Skip the pageflip completion check below (based on polling) on 299 * asics which reliably support hw pageflip completion irqs. pflip 300 * irqs are a reliable and race-free method of handling pageflip 301 * completion detection. A use_pflipirq module parameter < 2 allows 302 * to override this in case of asics with faulty pflip irqs. 303 * A module parameter of 0 would only use this polling based path, 304 * a parameter of 1 would use pflip irq only as a backup to this 305 * path, as in Linux 3.16. 306 */ 307 if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev)) 308 return; 309 310 spin_lock_irqsave(&rdev->ddev->event_lock, flags); 311 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 312 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 313 "RADEON_FLIP_SUBMITTED(%d)\n", 314 radeon_crtc->flip_status, 315 RADEON_FLIP_SUBMITTED); 316 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 317 return; 318 } 319 320 update_pending = radeon_page_flip_pending(rdev, crtc_id); 321 322 /* Has the pageflip already completed in crtc, or is it certain 323 * to complete in this vblank? GET_DISTANCE_TO_VBLANKSTART provides 324 * distance to start of "fudged earlier" vblank in vpos, distance to 325 * start of real vblank in hpos. vpos >= 0 && hpos < 0 means we are in 326 * the last few scanlines before start of real vblank, where the vblank 327 * irq can fire, so we have sampled update_pending a bit too early and 328 * know the flip will complete at leading edge of the upcoming real 329 * vblank. On pre-AVIVO hardware, flips also complete inside the real 330 * vblank, not only at leading edge, so if update_pending for hpos >= 0 331 * == inside real vblank, the flip will complete almost immediately. 332 * Note that this method of completion handling is still not 100% race 333 * free, as we could execute before the radeon_flip_work_func managed 334 * to run and set the RADEON_FLIP_SUBMITTED status, thereby we no-op, 335 * but the flip still gets programmed into hw and completed during 336 * vblank, leading to a delayed emission of the flip completion event. 337 * This applies at least to pre-AVIVO hardware, where flips are always 338 * completing inside vblank, not only at leading edge of vblank. 339 */ 340 if (update_pending && 341 (DRM_SCANOUTPOS_VALID & 342 radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 343 GET_DISTANCE_TO_VBLANKSTART, 344 &vpos, &hpos, NULL, NULL, 345 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) && 346 ((vpos >= 0 && hpos < 0) || (hpos >= 0 && !ASIC_IS_AVIVO(rdev)))) { 347 /* crtc didn't flip in this target vblank interval, 348 * but flip is pending in crtc. Based on the current 349 * scanout position we know that the current frame is 350 * (nearly) complete and the flip will (likely) 351 * complete before the start of the next frame. 352 */ 353 update_pending = 0; 354 } 355 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 356 if (!update_pending) 357 radeon_crtc_handle_flip(rdev, crtc_id); 358 } 359 360 /** 361 * radeon_crtc_handle_flip - page flip completed 362 * 363 * @rdev: radeon device pointer 364 * @crtc_id: crtc number this event is for 365 * 366 * Called when we are sure that a page flip for this crtc is completed. 367 */ 368 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) 369 { 370 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 371 struct radeon_flip_work *work; 372 unsigned long flags; 373 374 /* this can happen at init */ 375 if (radeon_crtc == NULL) 376 return; 377 378 spin_lock_irqsave(&rdev->ddev->event_lock, flags); 379 work = radeon_crtc->flip_work; 380 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 381 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 382 "RADEON_FLIP_SUBMITTED(%d)\n", 383 radeon_crtc->flip_status, 384 RADEON_FLIP_SUBMITTED); 385 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 386 return; 387 } 388 389 /* Pageflip completed. Clean up. */ 390 radeon_crtc->flip_status = RADEON_FLIP_NONE; 391 radeon_crtc->flip_work = NULL; 392 393 /* wakeup userspace */ 394 if (work->event) 395 drm_crtc_send_vblank_event(&radeon_crtc->base, work->event); 396 397 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 398 399 drm_crtc_vblank_put(&radeon_crtc->base); 400 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id); 401 queue_work(radeon_crtc->flip_queue, &work->unpin_work); 402 } 403 404 /** 405 * radeon_flip_work_func - page flip framebuffer 406 * 407 * @work - kernel work item 408 * 409 * Wait for the buffer object to become idle and do the actual page flip 410 */ 411 static void radeon_flip_work_func(struct work_struct *__work) 412 { 413 struct radeon_flip_work *work = 414 container_of(__work, struct radeon_flip_work, flip_work); 415 struct radeon_device *rdev = work->rdev; 416 struct drm_device *dev = rdev->ddev; 417 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id]; 418 419 struct drm_crtc *crtc = &radeon_crtc->base; 420 unsigned long flags; 421 int r; 422 int vpos, hpos; 423 424 down_read(&rdev->exclusive_lock); 425 if (work->fence) { 426 struct radeon_fence *fence; 427 428 fence = to_radeon_fence(work->fence); 429 if (fence && fence->rdev == rdev) { 430 r = radeon_fence_wait(fence, false); 431 if (r == -EDEADLK) { 432 up_read(&rdev->exclusive_lock); 433 do { 434 r = radeon_gpu_reset(rdev); 435 } while (r == -EAGAIN); 436 down_read(&rdev->exclusive_lock); 437 } 438 } else 439 r = dma_fence_wait(work->fence, false); 440 441 if (r) 442 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r); 443 444 /* We continue with the page flip even if we failed to wait on 445 * the fence, otherwise the DRM core and userspace will be 446 * confused about which BO the CRTC is scanning out 447 */ 448 449 dma_fence_put(work->fence); 450 work->fence = NULL; 451 } 452 453 /* Wait until we're out of the vertical blank period before the one 454 * targeted by the flip. Always wait on pre DCE4 to avoid races with 455 * flip completion handling from vblank irq, as these old asics don't 456 * have reliable pageflip completion interrupts. 457 */ 458 while (radeon_crtc->enabled && 459 (radeon_get_crtc_scanoutpos(dev, work->crtc_id, 0, 460 &vpos, &hpos, NULL, NULL, 461 &crtc->hwmode) 462 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 463 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 464 (!ASIC_IS_AVIVO(rdev) || 465 ((int) (work->target_vblank - 466 dev->driver->get_vblank_counter(dev, work->crtc_id)) > 0))) 467 usleep_range(1000, 2000); 468 469 /* We borrow the event spin lock for protecting flip_status */ 470 spin_lock_irqsave(&crtc->dev->event_lock, flags); 471 472 /* set the proper interrupt */ 473 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id); 474 475 /* do the flip (mmio) */ 476 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async); 477 478 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED; 479 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 480 up_read(&rdev->exclusive_lock); 481 } 482 483 static int radeon_crtc_page_flip_target(struct drm_crtc *crtc, 484 struct drm_framebuffer *fb, 485 struct drm_pending_vblank_event *event, 486 uint32_t page_flip_flags, 487 uint32_t target) 488 { 489 struct drm_device *dev = crtc->dev; 490 struct radeon_device *rdev = dev->dev_private; 491 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 492 struct radeon_framebuffer *old_radeon_fb; 493 struct radeon_framebuffer *new_radeon_fb; 494 struct drm_gem_object *obj; 495 struct radeon_flip_work *work; 496 struct radeon_bo *new_rbo; 497 uint32_t tiling_flags, pitch_pixels; 498 uint64_t base; 499 unsigned long flags; 500 int r; 501 502 work = kzalloc(sizeof *work, GFP_KERNEL); 503 if (work == NULL) 504 return -ENOMEM; 505 506 INIT_WORK(&work->flip_work, radeon_flip_work_func); 507 INIT_WORK(&work->unpin_work, radeon_unpin_work_func); 508 509 work->rdev = rdev; 510 work->crtc_id = radeon_crtc->crtc_id; 511 work->event = event; 512 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 513 514 /* schedule unpin of the old buffer */ 515 old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb); 516 obj = old_radeon_fb->obj; 517 518 /* take a reference to the old object */ 519 drm_gem_object_reference(obj); 520 work->old_rbo = gem_to_radeon_bo(obj); 521 522 new_radeon_fb = to_radeon_framebuffer(fb); 523 obj = new_radeon_fb->obj; 524 new_rbo = gem_to_radeon_bo(obj); 525 526 /* pin the new buffer */ 527 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n", 528 work->old_rbo, new_rbo); 529 530 r = radeon_bo_reserve(new_rbo, false); 531 if (unlikely(r != 0)) { 532 DRM_ERROR("failed to reserve new rbo buffer before flip\n"); 533 goto cleanup; 534 } 535 /* Only 27 bit offset for legacy CRTC */ 536 r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM, 537 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, (u64 *)&base); 538 if (unlikely(r != 0)) { 539 radeon_bo_unreserve(new_rbo); 540 r = -EINVAL; 541 DRM_ERROR("failed to pin new rbo buffer before flip\n"); 542 goto cleanup; 543 } 544 work->fence = dma_fence_get(reservation_object_get_excl(new_rbo->tbo.resv)); 545 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); 546 radeon_bo_unreserve(new_rbo); 547 548 if (!ASIC_IS_AVIVO(rdev)) { 549 /* crtc offset is from display base addr not FB location */ 550 base -= radeon_crtc->legacy_display_base_addr; 551 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8); 552 553 if (tiling_flags & RADEON_TILING_MACRO) { 554 if (ASIC_IS_R300(rdev)) { 555 base &= ~0x7ff; 556 } else { 557 int byteshift = fb->bits_per_pixel >> 4; 558 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11; 559 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8); 560 } 561 } else { 562 int offset = crtc->y * pitch_pixels + crtc->x; 563 switch (fb->bits_per_pixel) { 564 case 8: 565 default: 566 offset *= 1; 567 break; 568 case 15: 569 case 16: 570 offset *= 2; 571 break; 572 case 24: 573 offset *= 3; 574 break; 575 case 32: 576 offset *= 4; 577 break; 578 } 579 base += offset; 580 } 581 base &= ~7; 582 } 583 work->base = base; 584 work->target_vblank = target - drm_crtc_vblank_count(crtc) + 585 dev->driver->get_vblank_counter(dev, work->crtc_id); 586 587 /* We borrow the event spin lock for protecting flip_work */ 588 spin_lock_irqsave(&crtc->dev->event_lock, flags); 589 590 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) { 591 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 592 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 593 r = -EBUSY; 594 goto pflip_cleanup; 595 } 596 radeon_crtc->flip_status = RADEON_FLIP_PENDING; 597 radeon_crtc->flip_work = work; 598 599 /* update crtc fb */ 600 crtc->primary->fb = fb; 601 602 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 603 604 queue_work(radeon_crtc->flip_queue, &work->flip_work); 605 return 0; 606 607 pflip_cleanup: 608 if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) { 609 DRM_ERROR("failed to reserve new rbo in error path\n"); 610 goto cleanup; 611 } 612 if (unlikely(radeon_bo_unpin(new_rbo) != 0)) { 613 DRM_ERROR("failed to unpin new rbo in error path\n"); 614 } 615 radeon_bo_unreserve(new_rbo); 616 617 cleanup: 618 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 619 dma_fence_put(work->fence); 620 kfree(work); 621 return r; 622 } 623 624 static int 625 radeon_crtc_set_config(struct drm_mode_set *set) 626 { 627 struct drm_device *dev; 628 struct radeon_device *rdev; 629 struct drm_crtc *crtc; 630 bool active = false; 631 int ret; 632 633 if (!set || !set->crtc) 634 return -EINVAL; 635 636 dev = set->crtc->dev; 637 638 #ifdef PM_TODO 639 ret = pm_runtime_get_sync(dev->dev); 640 if (ret < 0) 641 return ret; 642 #endif 643 644 ret = drm_crtc_helper_set_config(set); 645 646 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 647 if (crtc->enabled) 648 active = true; 649 650 #ifdef PM_TODO 651 pm_runtime_mark_last_busy(dev->dev); 652 #endif 653 654 rdev = dev->dev_private; 655 /* if we have active crtcs and we don't have a power ref, 656 take the current one */ 657 if (active && !rdev->have_disp_power_ref) { 658 rdev->have_disp_power_ref = true; 659 return ret; 660 } 661 /* if we have no active crtcs, then drop the power ref 662 we got before */ 663 if (!active && rdev->have_disp_power_ref) { 664 #ifdef PM_TODO 665 pm_runtime_put_autosuspend(dev->dev); 666 #endif 667 rdev->have_disp_power_ref = false; 668 } 669 670 /* drop the power reference we got coming in here */ 671 #ifdef PM_TODO 672 pm_runtime_put_autosuspend(dev->dev); 673 #endif 674 return ret; 675 } 676 677 static const struct drm_crtc_funcs radeon_crtc_funcs = { 678 .cursor_set2 = radeon_crtc_cursor_set2, 679 .cursor_move = radeon_crtc_cursor_move, 680 .gamma_set = radeon_crtc_gamma_set, 681 .set_config = radeon_crtc_set_config, 682 .destroy = radeon_crtc_destroy, 683 .page_flip_target = radeon_crtc_page_flip_target, 684 }; 685 686 static void radeon_crtc_init(struct drm_device *dev, int index) 687 { 688 struct radeon_device *rdev = dev->dev_private; 689 struct radeon_crtc *radeon_crtc; 690 int i; 691 692 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 693 if (radeon_crtc == NULL) 694 return; 695 696 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); 697 698 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); 699 radeon_crtc->crtc_id = index; 700 radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0); 701 rdev->mode_info.crtcs[index] = radeon_crtc; 702 703 if (rdev->family >= CHIP_BONAIRE) { 704 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH; 705 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT; 706 } else { 707 radeon_crtc->max_cursor_width = CURSOR_WIDTH; 708 radeon_crtc->max_cursor_height = CURSOR_HEIGHT; 709 } 710 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width; 711 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height; 712 713 #if 0 714 radeon_crtc->mode_set.crtc = &radeon_crtc->base; 715 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); 716 radeon_crtc->mode_set.num_connectors = 0; 717 #endif 718 719 for (i = 0; i < 256; i++) { 720 radeon_crtc->lut_r[i] = i << 2; 721 radeon_crtc->lut_g[i] = i << 2; 722 radeon_crtc->lut_b[i] = i << 2; 723 } 724 725 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) 726 radeon_atombios_init_crtc(dev, radeon_crtc); 727 else 728 radeon_legacy_init_crtc(dev, radeon_crtc); 729 } 730 731 static const char *encoder_names[38] = { 732 "NONE", 733 "INTERNAL_LVDS", 734 "INTERNAL_TMDS1", 735 "INTERNAL_TMDS2", 736 "INTERNAL_DAC1", 737 "INTERNAL_DAC2", 738 "INTERNAL_SDVOA", 739 "INTERNAL_SDVOB", 740 "SI170B", 741 "CH7303", 742 "CH7301", 743 "INTERNAL_DVO1", 744 "EXTERNAL_SDVOA", 745 "EXTERNAL_SDVOB", 746 "TITFP513", 747 "INTERNAL_LVTM1", 748 "VT1623", 749 "HDMI_SI1930", 750 "HDMI_INTERNAL", 751 "INTERNAL_KLDSCP_TMDS1", 752 "INTERNAL_KLDSCP_DVO1", 753 "INTERNAL_KLDSCP_DAC1", 754 "INTERNAL_KLDSCP_DAC2", 755 "SI178", 756 "MVPU_FPGA", 757 "INTERNAL_DDI", 758 "VT1625", 759 "HDMI_SI1932", 760 "DP_AN9801", 761 "DP_DP501", 762 "INTERNAL_UNIPHY", 763 "INTERNAL_KLDSCP_LVTMA", 764 "INTERNAL_UNIPHY1", 765 "INTERNAL_UNIPHY2", 766 "NUTMEG", 767 "TRAVIS", 768 "INTERNAL_VCE", 769 "INTERNAL_UNIPHY3", 770 }; 771 772 static const char *hpd_names[6] = { 773 "HPD1", 774 "HPD2", 775 "HPD3", 776 "HPD4", 777 "HPD5", 778 "HPD6", 779 }; 780 781 static void radeon_print_display_setup(struct drm_device *dev) 782 { 783 struct drm_connector *connector; 784 struct radeon_connector *radeon_connector; 785 struct drm_encoder *encoder; 786 struct radeon_encoder *radeon_encoder; 787 uint32_t devices; 788 int i = 0; 789 790 DRM_INFO("Radeon Display Connectors\n"); 791 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 792 radeon_connector = to_radeon_connector(connector); 793 DRM_INFO("Connector %d:\n", i); 794 DRM_INFO(" %s\n", connector->name); 795 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 796 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); 797 if (radeon_connector->ddc_bus) { 798 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 799 radeon_connector->ddc_bus->rec.mask_clk_reg, 800 radeon_connector->ddc_bus->rec.mask_data_reg, 801 radeon_connector->ddc_bus->rec.a_clk_reg, 802 radeon_connector->ddc_bus->rec.a_data_reg, 803 radeon_connector->ddc_bus->rec.en_clk_reg, 804 radeon_connector->ddc_bus->rec.en_data_reg, 805 radeon_connector->ddc_bus->rec.y_clk_reg, 806 radeon_connector->ddc_bus->rec.y_data_reg); 807 if (radeon_connector->router.ddc_valid) 808 DRM_INFO(" DDC Router 0x%x/0x%x\n", 809 radeon_connector->router.ddc_mux_control_pin, 810 radeon_connector->router.ddc_mux_state); 811 if (radeon_connector->router.cd_valid) 812 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 813 radeon_connector->router.cd_mux_control_pin, 814 radeon_connector->router.cd_mux_state); 815 } else { 816 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 817 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 818 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 819 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 820 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 821 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 822 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 823 } 824 DRM_INFO(" Encoders:\n"); 825 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 826 radeon_encoder = to_radeon_encoder(encoder); 827 devices = radeon_encoder->devices & radeon_connector->devices; 828 if (devices) { 829 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 830 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); 831 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 832 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); 833 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 834 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); 835 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 836 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); 837 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 838 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); 839 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 840 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); 841 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 842 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); 843 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 844 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); 845 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 846 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); 847 if (devices & ATOM_DEVICE_TV1_SUPPORT) 848 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); 849 if (devices & ATOM_DEVICE_CV_SUPPORT) 850 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); 851 } 852 } 853 i++; 854 } 855 } 856 857 static bool radeon_setup_enc_conn(struct drm_device *dev) 858 { 859 struct radeon_device *rdev = dev->dev_private; 860 bool ret = false; 861 862 if (rdev->bios) { 863 if (rdev->is_atom_bios) { 864 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); 865 if (ret == false) 866 ret = radeon_get_atom_connector_info_from_object_table(dev); 867 } else { 868 ret = radeon_get_legacy_connector_info_from_bios(dev); 869 if (ret == false) 870 ret = radeon_get_legacy_connector_info_from_table(dev); 871 } 872 } else { 873 if (!ASIC_IS_AVIVO(rdev)) 874 ret = radeon_get_legacy_connector_info_from_table(dev); 875 } 876 if (ret) { 877 radeon_setup_encoder_clones(dev); 878 radeon_print_display_setup(dev); 879 } 880 881 return ret; 882 } 883 884 /* avivo */ 885 886 /** 887 * avivo_reduce_ratio - fractional number reduction 888 * 889 * @nom: nominator 890 * @den: denominator 891 * @nom_min: minimum value for nominator 892 * @den_min: minimum value for denominator 893 * 894 * Find the greatest common divisor and apply it on both nominator and 895 * denominator, but make nominator and denominator are at least as large 896 * as their minimum values. 897 */ 898 static void avivo_reduce_ratio(unsigned *nom, unsigned *den, 899 unsigned nom_min, unsigned den_min) 900 { 901 unsigned tmp; 902 903 /* reduce the numbers to a simpler ratio */ 904 tmp = gcd(*nom, *den); 905 *nom /= tmp; 906 *den /= tmp; 907 908 /* make sure nominator is large enough */ 909 if (*nom < nom_min) { 910 tmp = DIV_ROUND_UP(nom_min, *nom); 911 *nom *= tmp; 912 *den *= tmp; 913 } 914 915 /* make sure the denominator is large enough */ 916 if (*den < den_min) { 917 tmp = DIV_ROUND_UP(den_min, *den); 918 *nom *= tmp; 919 *den *= tmp; 920 } 921 } 922 923 /** 924 * avivo_get_fb_ref_div - feedback and ref divider calculation 925 * 926 * @nom: nominator 927 * @den: denominator 928 * @post_div: post divider 929 * @fb_div_max: feedback divider maximum 930 * @ref_div_max: reference divider maximum 931 * @fb_div: resulting feedback divider 932 * @ref_div: resulting reference divider 933 * 934 * Calculate feedback and reference divider for a given post divider. Makes 935 * sure we stay within the limits. 936 */ 937 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, 938 unsigned fb_div_max, unsigned ref_div_max, 939 unsigned *fb_div, unsigned *ref_div) 940 { 941 /* limit reference * post divider to a maximum */ 942 ref_div_max = max(min(100 / post_div, ref_div_max), 1u); 943 944 /* get matching reference and feedback divider */ 945 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); 946 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); 947 948 /* limit fb divider to its maximum */ 949 if (*fb_div > fb_div_max) { 950 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); 951 *fb_div = fb_div_max; 952 } 953 } 954 955 /** 956 * radeon_compute_pll_avivo - compute PLL paramaters 957 * 958 * @pll: information about the PLL 959 * @dot_clock_p: resulting pixel clock 960 * fb_div_p: resulting feedback divider 961 * frac_fb_div_p: fractional part of the feedback divider 962 * ref_div_p: resulting reference divider 963 * post_div_p: resulting reference divider 964 * 965 * Try to calculate the PLL parameters to generate the given frequency: 966 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div) 967 */ 968 void radeon_compute_pll_avivo(struct radeon_pll *pll, 969 u32 freq, 970 u32 *dot_clock_p, 971 u32 *fb_div_p, 972 u32 *frac_fb_div_p, 973 u32 *ref_div_p, 974 u32 *post_div_p) 975 { 976 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? 977 freq : freq / 10; 978 979 unsigned fb_div_min, fb_div_max, fb_div; 980 unsigned post_div_min, post_div_max, post_div; 981 unsigned ref_div_min, ref_div_max, ref_div; 982 unsigned post_div_best, diff_best; 983 unsigned nom, den; 984 985 /* determine allowed feedback divider range */ 986 fb_div_min = pll->min_feedback_div; 987 fb_div_max = pll->max_feedback_div; 988 989 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 990 fb_div_min *= 10; 991 fb_div_max *= 10; 992 } 993 994 /* determine allowed ref divider range */ 995 if (pll->flags & RADEON_PLL_USE_REF_DIV) 996 ref_div_min = pll->reference_div; 997 else 998 ref_div_min = pll->min_ref_div; 999 1000 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && 1001 pll->flags & RADEON_PLL_USE_REF_DIV) 1002 ref_div_max = pll->reference_div; 1003 else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 1004 /* fix for problems on RS880 */ 1005 ref_div_max = min(pll->max_ref_div, 7u); 1006 else 1007 ref_div_max = pll->max_ref_div; 1008 1009 /* determine allowed post divider range */ 1010 if (pll->flags & RADEON_PLL_USE_POST_DIV) { 1011 post_div_min = pll->post_div; 1012 post_div_max = pll->post_div; 1013 } else { 1014 unsigned vco_min, vco_max; 1015 1016 if (pll->flags & RADEON_PLL_IS_LCD) { 1017 vco_min = pll->lcd_pll_out_min; 1018 vco_max = pll->lcd_pll_out_max; 1019 } else { 1020 vco_min = pll->pll_out_min; 1021 vco_max = pll->pll_out_max; 1022 } 1023 1024 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1025 vco_min *= 10; 1026 vco_max *= 10; 1027 } 1028 1029 post_div_min = vco_min / target_clock; 1030 if ((target_clock * post_div_min) < vco_min) 1031 ++post_div_min; 1032 if (post_div_min < pll->min_post_div) 1033 post_div_min = pll->min_post_div; 1034 1035 post_div_max = vco_max / target_clock; 1036 if ((target_clock * post_div_max) > vco_max) 1037 --post_div_max; 1038 if (post_div_max > pll->max_post_div) 1039 post_div_max = pll->max_post_div; 1040 } 1041 1042 /* represent the searched ratio as fractional number */ 1043 nom = target_clock; 1044 den = pll->reference_freq; 1045 1046 /* reduce the numbers to a simpler ratio */ 1047 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min); 1048 1049 /* now search for a post divider */ 1050 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 1051 post_div_best = post_div_min; 1052 else 1053 post_div_best = post_div_max; 1054 diff_best = ~0; 1055 1056 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { 1057 unsigned diff; 1058 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, 1059 ref_div_max, &fb_div, &ref_div); 1060 diff = abs(target_clock - (pll->reference_freq * fb_div) / 1061 (ref_div * post_div)); 1062 1063 if (diff < diff_best || (diff == diff_best && 1064 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) { 1065 1066 post_div_best = post_div; 1067 diff_best = diff; 1068 } 1069 } 1070 post_div = post_div_best; 1071 1072 /* get the feedback and reference divider for the optimal value */ 1073 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max, 1074 &fb_div, &ref_div); 1075 1076 /* reduce the numbers to a simpler ratio once more */ 1077 /* this also makes sure that the reference divider is large enough */ 1078 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); 1079 1080 /* avoid high jitter with small fractional dividers */ 1081 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { 1082 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50); 1083 if (fb_div < fb_div_min) { 1084 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div); 1085 fb_div *= tmp; 1086 ref_div *= tmp; 1087 } 1088 } 1089 1090 /* and finally save the result */ 1091 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1092 *fb_div_p = fb_div / 10; 1093 *frac_fb_div_p = fb_div % 10; 1094 } else { 1095 *fb_div_p = fb_div; 1096 *frac_fb_div_p = 0; 1097 } 1098 1099 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + 1100 (pll->reference_freq * *frac_fb_div_p)) / 1101 (ref_div * post_div * 10); 1102 *ref_div_p = ref_div; 1103 *post_div_p = post_div; 1104 1105 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1106 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, 1107 ref_div, post_div); 1108 } 1109 1110 /* pre-avivo */ 1111 static inline uint32_t radeon_div(uint64_t n, uint32_t d) 1112 { 1113 uint64_t mod; 1114 1115 n += d / 2; 1116 1117 mod = do_div(n, d); 1118 return n; 1119 } 1120 1121 void radeon_compute_pll_legacy(struct radeon_pll *pll, 1122 uint64_t freq, 1123 uint32_t *dot_clock_p, 1124 uint32_t *fb_div_p, 1125 uint32_t *frac_fb_div_p, 1126 uint32_t *ref_div_p, 1127 uint32_t *post_div_p) 1128 { 1129 uint32_t min_ref_div = pll->min_ref_div; 1130 uint32_t max_ref_div = pll->max_ref_div; 1131 uint32_t min_post_div = pll->min_post_div; 1132 uint32_t max_post_div = pll->max_post_div; 1133 uint32_t min_fractional_feed_div = 0; 1134 uint32_t max_fractional_feed_div = 0; 1135 uint32_t best_vco = pll->best_vco; 1136 uint32_t best_post_div = 1; 1137 uint32_t best_ref_div = 1; 1138 uint32_t best_feedback_div = 1; 1139 uint32_t best_frac_feedback_div = 0; 1140 uint32_t best_freq = -1; 1141 uint32_t best_error = 0xffffffff; 1142 uint32_t best_vco_diff = 1; 1143 uint32_t post_div; 1144 u32 pll_out_min, pll_out_max; 1145 1146 DRM_DEBUG_KMS("PLL freq %ju %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); 1147 freq = freq * 1000; 1148 1149 if (pll->flags & RADEON_PLL_IS_LCD) { 1150 pll_out_min = pll->lcd_pll_out_min; 1151 pll_out_max = pll->lcd_pll_out_max; 1152 } else { 1153 pll_out_min = pll->pll_out_min; 1154 pll_out_max = pll->pll_out_max; 1155 } 1156 1157 if (pll_out_min > 64800) 1158 pll_out_min = 64800; 1159 1160 if (pll->flags & RADEON_PLL_USE_REF_DIV) 1161 min_ref_div = max_ref_div = pll->reference_div; 1162 else { 1163 while (min_ref_div < max_ref_div-1) { 1164 uint32_t mid = (min_ref_div + max_ref_div) / 2; 1165 uint32_t pll_in = pll->reference_freq / mid; 1166 if (pll_in < pll->pll_in_min) 1167 max_ref_div = mid; 1168 else if (pll_in > pll->pll_in_max) 1169 min_ref_div = mid; 1170 else 1171 break; 1172 } 1173 } 1174 1175 if (pll->flags & RADEON_PLL_USE_POST_DIV) 1176 min_post_div = max_post_div = pll->post_div; 1177 1178 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1179 min_fractional_feed_div = pll->min_frac_feedback_div; 1180 max_fractional_feed_div = pll->max_frac_feedback_div; 1181 } 1182 1183 for (post_div = max_post_div; post_div >= min_post_div; --post_div) { 1184 uint32_t ref_div; 1185 1186 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 1187 continue; 1188 1189 /* legacy radeons only have a few post_divs */ 1190 if (pll->flags & RADEON_PLL_LEGACY) { 1191 if ((post_div == 5) || 1192 (post_div == 7) || 1193 (post_div == 9) || 1194 (post_div == 10) || 1195 (post_div == 11) || 1196 (post_div == 13) || 1197 (post_div == 14) || 1198 (post_div == 15)) 1199 continue; 1200 } 1201 1202 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { 1203 uint32_t feedback_div, current_freq = 0, error, vco_diff; 1204 uint32_t pll_in = pll->reference_freq / ref_div; 1205 uint32_t min_feed_div = pll->min_feedback_div; 1206 uint32_t max_feed_div = pll->max_feedback_div + 1; 1207 1208 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) 1209 continue; 1210 1211 while (min_feed_div < max_feed_div) { 1212 uint32_t vco; 1213 uint32_t min_frac_feed_div = min_fractional_feed_div; 1214 uint32_t max_frac_feed_div = max_fractional_feed_div + 1; 1215 uint32_t frac_feedback_div; 1216 uint64_t tmp; 1217 1218 feedback_div = (min_feed_div + max_feed_div) / 2; 1219 1220 tmp = (uint64_t)pll->reference_freq * feedback_div; 1221 vco = radeon_div(tmp, ref_div); 1222 1223 if (vco < pll_out_min) { 1224 min_feed_div = feedback_div + 1; 1225 continue; 1226 } else if (vco > pll_out_max) { 1227 max_feed_div = feedback_div; 1228 continue; 1229 } 1230 1231 while (min_frac_feed_div < max_frac_feed_div) { 1232 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; 1233 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; 1234 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; 1235 current_freq = radeon_div(tmp, ref_div * post_div); 1236 1237 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 1238 if (freq < current_freq) 1239 error = 0xffffffff; 1240 else 1241 error = freq - current_freq; 1242 } else 1243 error = abs(current_freq - freq); 1244 vco_diff = abs(vco - best_vco); 1245 1246 if ((best_vco == 0 && error < best_error) || 1247 (best_vco != 0 && 1248 ((best_error > 100 && error < best_error - 100) || 1249 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { 1250 best_post_div = post_div; 1251 best_ref_div = ref_div; 1252 best_feedback_div = feedback_div; 1253 best_frac_feedback_div = frac_feedback_div; 1254 best_freq = current_freq; 1255 best_error = error; 1256 best_vco_diff = vco_diff; 1257 } else if (current_freq == freq) { 1258 if (best_freq == -1) { 1259 best_post_div = post_div; 1260 best_ref_div = ref_div; 1261 best_feedback_div = feedback_div; 1262 best_frac_feedback_div = frac_feedback_div; 1263 best_freq = current_freq; 1264 best_error = error; 1265 best_vco_diff = vco_diff; 1266 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 1267 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 1268 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 1269 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 1270 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 1271 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 1272 best_post_div = post_div; 1273 best_ref_div = ref_div; 1274 best_feedback_div = feedback_div; 1275 best_frac_feedback_div = frac_feedback_div; 1276 best_freq = current_freq; 1277 best_error = error; 1278 best_vco_diff = vco_diff; 1279 } 1280 } 1281 if (current_freq < freq) 1282 min_frac_feed_div = frac_feedback_div + 1; 1283 else 1284 max_frac_feed_div = frac_feedback_div; 1285 } 1286 if (current_freq < freq) 1287 min_feed_div = feedback_div + 1; 1288 else 1289 max_feed_div = feedback_div; 1290 } 1291 } 1292 } 1293 1294 *dot_clock_p = best_freq / 10000; 1295 *fb_div_p = best_feedback_div; 1296 *frac_fb_div_p = best_frac_feedback_div; 1297 *ref_div_p = best_ref_div; 1298 *post_div_p = best_post_div; 1299 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1300 (long long)freq, 1301 best_freq / 1000, best_feedback_div, best_frac_feedback_div, 1302 best_ref_div, best_post_div); 1303 1304 } 1305 1306 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) 1307 { 1308 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1309 1310 drm_gem_object_unreference_unlocked(radeon_fb->obj); 1311 drm_framebuffer_cleanup(fb); 1312 kfree(radeon_fb); 1313 } 1314 1315 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, 1316 struct drm_file *file_priv, 1317 unsigned int *handle) 1318 { 1319 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1320 1321 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); 1322 } 1323 1324 static const struct drm_framebuffer_funcs radeon_fb_funcs = { 1325 .destroy = radeon_user_framebuffer_destroy, 1326 .create_handle = radeon_user_framebuffer_create_handle, 1327 }; 1328 1329 int 1330 radeon_framebuffer_init(struct drm_device *dev, 1331 struct radeon_framebuffer *rfb, 1332 const struct drm_mode_fb_cmd2 *mode_cmd, 1333 struct drm_gem_object *obj) 1334 { 1335 int ret; 1336 rfb->obj = obj; 1337 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); 1338 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); 1339 if (ret) { 1340 rfb->obj = NULL; 1341 return ret; 1342 } 1343 return 0; 1344 } 1345 1346 static struct drm_framebuffer * 1347 radeon_user_framebuffer_create(struct drm_device *dev, 1348 struct drm_file *file_priv, 1349 const struct drm_mode_fb_cmd2 *mode_cmd) 1350 { 1351 struct drm_gem_object *obj; 1352 struct radeon_framebuffer *radeon_fb; 1353 int ret; 1354 1355 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); 1356 if (obj == NULL) { 1357 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 1358 "can't create framebuffer\n", mode_cmd->handles[0]); 1359 return ERR_PTR(-ENOENT); 1360 } 1361 1362 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ 1363 if (obj->import_attach) { 1364 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n"); 1365 return ERR_PTR(-EINVAL); 1366 } 1367 1368 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); 1369 if (radeon_fb == NULL) { 1370 drm_gem_object_unreference_unlocked(obj); 1371 return ERR_PTR(-ENOMEM); 1372 } 1373 1374 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj); 1375 if (ret) { 1376 kfree(radeon_fb); 1377 drm_gem_object_unreference_unlocked(obj); 1378 return ERR_PTR(ret); 1379 } 1380 1381 return &radeon_fb->base; 1382 } 1383 1384 static void radeon_output_poll_changed(struct drm_device *dev) 1385 { 1386 struct radeon_device *rdev = dev->dev_private; 1387 radeon_fb_output_poll_changed(rdev); 1388 } 1389 1390 static const struct drm_mode_config_funcs radeon_mode_funcs = { 1391 .fb_create = radeon_user_framebuffer_create, 1392 .output_poll_changed = radeon_output_poll_changed 1393 }; 1394 1395 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = 1396 { { 0, "driver" }, 1397 { 1, "bios" }, 1398 }; 1399 1400 static struct drm_prop_enum_list radeon_tv_std_enum_list[] = 1401 { { TV_STD_NTSC, "ntsc" }, 1402 { TV_STD_PAL, "pal" }, 1403 { TV_STD_PAL_M, "pal-m" }, 1404 { TV_STD_PAL_60, "pal-60" }, 1405 { TV_STD_NTSC_J, "ntsc-j" }, 1406 { TV_STD_SCART_PAL, "scart-pal" }, 1407 { TV_STD_PAL_CN, "pal-cn" }, 1408 { TV_STD_SECAM, "secam" }, 1409 }; 1410 1411 static struct drm_prop_enum_list radeon_underscan_enum_list[] = 1412 { { UNDERSCAN_OFF, "off" }, 1413 { UNDERSCAN_ON, "on" }, 1414 { UNDERSCAN_AUTO, "auto" }, 1415 }; 1416 1417 static struct drm_prop_enum_list radeon_audio_enum_list[] = 1418 { { RADEON_AUDIO_DISABLE, "off" }, 1419 { RADEON_AUDIO_ENABLE, "on" }, 1420 { RADEON_AUDIO_AUTO, "auto" }, 1421 }; 1422 1423 /* XXX support different dither options? spatial, temporal, both, etc. */ 1424 static struct drm_prop_enum_list radeon_dither_enum_list[] = 1425 { { RADEON_FMT_DITHER_DISABLE, "off" }, 1426 { RADEON_FMT_DITHER_ENABLE, "on" }, 1427 }; 1428 1429 static struct drm_prop_enum_list radeon_output_csc_enum_list[] = 1430 { { RADEON_OUTPUT_CSC_BYPASS, "bypass" }, 1431 { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" }, 1432 { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" }, 1433 { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" }, 1434 }; 1435 1436 static int radeon_modeset_create_props(struct radeon_device *rdev) 1437 { 1438 int sz; 1439 1440 if (rdev->is_atom_bios) { 1441 rdev->mode_info.coherent_mode_property = 1442 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1); 1443 if (!rdev->mode_info.coherent_mode_property) 1444 return -ENOMEM; 1445 } 1446 1447 if (!ASIC_IS_AVIVO(rdev)) { 1448 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); 1449 rdev->mode_info.tmds_pll_property = 1450 drm_property_create_enum(rdev->ddev, 0, 1451 "tmds_pll", 1452 radeon_tmds_pll_enum_list, sz); 1453 } 1454 1455 rdev->mode_info.load_detect_property = 1456 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1); 1457 if (!rdev->mode_info.load_detect_property) 1458 return -ENOMEM; 1459 1460 drm_mode_create_scaling_mode_property(rdev->ddev); 1461 1462 sz = ARRAY_SIZE(radeon_tv_std_enum_list); 1463 rdev->mode_info.tv_std_property = 1464 drm_property_create_enum(rdev->ddev, 0, 1465 "tv standard", 1466 radeon_tv_std_enum_list, sz); 1467 1468 sz = ARRAY_SIZE(radeon_underscan_enum_list); 1469 rdev->mode_info.underscan_property = 1470 drm_property_create_enum(rdev->ddev, 0, 1471 "underscan", 1472 radeon_underscan_enum_list, sz); 1473 1474 rdev->mode_info.underscan_hborder_property = 1475 drm_property_create_range(rdev->ddev, 0, 1476 "underscan hborder", 0, 128); 1477 if (!rdev->mode_info.underscan_hborder_property) 1478 return -ENOMEM; 1479 1480 rdev->mode_info.underscan_vborder_property = 1481 drm_property_create_range(rdev->ddev, 0, 1482 "underscan vborder", 0, 128); 1483 if (!rdev->mode_info.underscan_vborder_property) 1484 return -ENOMEM; 1485 1486 sz = ARRAY_SIZE(radeon_audio_enum_list); 1487 rdev->mode_info.audio_property = 1488 drm_property_create_enum(rdev->ddev, 0, 1489 "audio", 1490 radeon_audio_enum_list, sz); 1491 1492 sz = ARRAY_SIZE(radeon_dither_enum_list); 1493 rdev->mode_info.dither_property = 1494 drm_property_create_enum(rdev->ddev, 0, 1495 "dither", 1496 radeon_dither_enum_list, sz); 1497 1498 sz = ARRAY_SIZE(radeon_output_csc_enum_list); 1499 rdev->mode_info.output_csc_property = 1500 drm_property_create_enum(rdev->ddev, 0, 1501 "output_csc", 1502 radeon_output_csc_enum_list, sz); 1503 1504 return 0; 1505 } 1506 1507 void radeon_update_display_priority(struct radeon_device *rdev) 1508 { 1509 /* adjustment options for the display watermarks */ 1510 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { 1511 /* set display priority to high for r3xx, rv515 chips 1512 * this avoids flickering due to underflow to the 1513 * display controllers during heavy acceleration. 1514 * Don't force high on rs4xx igp chips as it seems to 1515 * affect the sound card. See kernel bug 15982. 1516 */ 1517 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && 1518 !(rdev->flags & RADEON_IS_IGP)) 1519 rdev->disp_priority = 2; 1520 else 1521 rdev->disp_priority = 0; 1522 } else 1523 rdev->disp_priority = radeon_disp_priority; 1524 1525 } 1526 1527 /* 1528 * Allocate hdmi structs and determine register offsets 1529 */ 1530 static void radeon_afmt_init(struct radeon_device *rdev) 1531 { 1532 int i; 1533 1534 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) 1535 rdev->mode_info.afmt[i] = NULL; 1536 1537 if (ASIC_IS_NODCE(rdev)) { 1538 /* nothing to do */ 1539 } else if (ASIC_IS_DCE4(rdev)) { 1540 static uint32_t eg_offsets[] = { 1541 EVERGREEN_CRTC0_REGISTER_OFFSET, 1542 EVERGREEN_CRTC1_REGISTER_OFFSET, 1543 EVERGREEN_CRTC2_REGISTER_OFFSET, 1544 EVERGREEN_CRTC3_REGISTER_OFFSET, 1545 EVERGREEN_CRTC4_REGISTER_OFFSET, 1546 EVERGREEN_CRTC5_REGISTER_OFFSET, 1547 0x13830 - 0x7030, 1548 }; 1549 int num_afmt; 1550 1551 /* DCE8 has 7 audio blocks tied to DIG encoders */ 1552 /* DCE6 has 6 audio blocks tied to DIG encoders */ 1553 /* DCE4/5 has 6 audio blocks tied to DIG encoders */ 1554 /* DCE4.1 has 2 audio blocks tied to DIG encoders */ 1555 if (ASIC_IS_DCE8(rdev)) 1556 num_afmt = 7; 1557 else if (ASIC_IS_DCE6(rdev)) 1558 num_afmt = 6; 1559 else if (ASIC_IS_DCE5(rdev)) 1560 num_afmt = 6; 1561 else if (ASIC_IS_DCE41(rdev)) 1562 num_afmt = 2; 1563 else /* DCE4 */ 1564 num_afmt = 6; 1565 1566 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets)); 1567 for (i = 0; i < num_afmt; i++) { 1568 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1569 if (rdev->mode_info.afmt[i]) { 1570 rdev->mode_info.afmt[i]->offset = eg_offsets[i]; 1571 rdev->mode_info.afmt[i]->id = i; 1572 } 1573 } 1574 } else if (ASIC_IS_DCE3(rdev)) { 1575 /* DCE3.x has 2 audio blocks tied to DIG encoders */ 1576 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1577 if (rdev->mode_info.afmt[0]) { 1578 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0; 1579 rdev->mode_info.afmt[0]->id = 0; 1580 } 1581 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1582 if (rdev->mode_info.afmt[1]) { 1583 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1; 1584 rdev->mode_info.afmt[1]->id = 1; 1585 } 1586 } else if (ASIC_IS_DCE2(rdev)) { 1587 /* DCE2 has at least 1 routable audio block */ 1588 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1589 if (rdev->mode_info.afmt[0]) { 1590 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0; 1591 rdev->mode_info.afmt[0]->id = 0; 1592 } 1593 /* r6xx has 2 routable audio blocks */ 1594 if (rdev->family >= CHIP_R600) { 1595 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1596 if (rdev->mode_info.afmt[1]) { 1597 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1; 1598 rdev->mode_info.afmt[1]->id = 1; 1599 } 1600 } 1601 } 1602 } 1603 1604 static void radeon_afmt_fini(struct radeon_device *rdev) 1605 { 1606 int i; 1607 1608 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) { 1609 kfree(rdev->mode_info.afmt[i]); 1610 rdev->mode_info.afmt[i] = NULL; 1611 } 1612 } 1613 1614 int radeon_modeset_init(struct radeon_device *rdev) 1615 { 1616 int i; 1617 int ret; 1618 1619 drm_mode_config_init(rdev->ddev); 1620 rdev->mode_info.mode_config_initialized = true; 1621 1622 rdev->ddev->mode_config.funcs = &radeon_mode_funcs; 1623 1624 if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600) 1625 rdev->ddev->mode_config.async_page_flip = true; 1626 1627 if (ASIC_IS_DCE5(rdev)) { 1628 rdev->ddev->mode_config.max_width = 16384; 1629 rdev->ddev->mode_config.max_height = 16384; 1630 } else if (ASIC_IS_AVIVO(rdev)) { 1631 rdev->ddev->mode_config.max_width = 8192; 1632 rdev->ddev->mode_config.max_height = 8192; 1633 } else { 1634 rdev->ddev->mode_config.max_width = 4096; 1635 rdev->ddev->mode_config.max_height = 4096; 1636 } 1637 1638 rdev->ddev->mode_config.preferred_depth = 24; 1639 rdev->ddev->mode_config.prefer_shadow = 1; 1640 1641 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; 1642 1643 ret = radeon_modeset_create_props(rdev); 1644 if (ret) { 1645 return ret; 1646 } 1647 1648 /* init i2c buses */ 1649 radeon_i2c_init(rdev); 1650 1651 /* check combios for a valid hardcoded EDID - Sun servers */ 1652 if (!rdev->is_atom_bios) { 1653 /* check for hardcoded EDID in BIOS */ 1654 radeon_combios_check_hardcoded_edid(rdev); 1655 } 1656 1657 /* allocate crtcs */ 1658 for (i = 0; i < rdev->num_crtc; i++) { 1659 radeon_crtc_init(rdev->ddev, i); 1660 } 1661 1662 /* okay we should have all the bios connectors */ 1663 ret = radeon_setup_enc_conn(rdev->ddev); 1664 if (!ret) { 1665 return ret; 1666 } 1667 1668 /* init dig PHYs, disp eng pll */ 1669 if (rdev->is_atom_bios) { 1670 radeon_atom_encoder_init(rdev); 1671 radeon_atom_disp_eng_pll_init(rdev); 1672 } 1673 1674 /* initialize hpd */ 1675 radeon_hpd_init(rdev); 1676 1677 /* setup afmt */ 1678 radeon_afmt_init(rdev); 1679 1680 radeon_fbdev_init(rdev); 1681 drm_kms_helper_poll_init(rdev->ddev); 1682 1683 /* do pm late init */ 1684 ret = radeon_pm_late_init(rdev); 1685 1686 return 0; 1687 } 1688 1689 void radeon_modeset_fini(struct radeon_device *rdev) 1690 { 1691 if (rdev->mode_info.mode_config_initialized) { 1692 drm_kms_helper_poll_fini(rdev->ddev); 1693 radeon_hpd_fini(rdev); 1694 drm_crtc_force_disable_all(rdev->ddev); 1695 radeon_fbdev_fini(rdev); 1696 radeon_afmt_fini(rdev); 1697 drm_mode_config_cleanup(rdev->ddev); 1698 rdev->mode_info.mode_config_initialized = false; 1699 } 1700 1701 kfree(rdev->mode_info.bios_hardcoded_edid); 1702 1703 /* free i2c buses */ 1704 radeon_i2c_fini(rdev); 1705 } 1706 1707 static bool is_hdtv_mode(const struct drm_display_mode *mode) 1708 { 1709 /* try and guess if this is a tv or a monitor */ 1710 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 1711 (mode->vdisplay == 576) || /* 576p */ 1712 (mode->vdisplay == 720) || /* 720p */ 1713 (mode->vdisplay == 1080)) /* 1080p */ 1714 return true; 1715 else 1716 return false; 1717 } 1718 1719 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 1720 const struct drm_display_mode *mode, 1721 struct drm_display_mode *adjusted_mode) 1722 { 1723 struct drm_device *dev = crtc->dev; 1724 struct radeon_device *rdev = dev->dev_private; 1725 struct drm_encoder *encoder; 1726 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1727 struct radeon_encoder *radeon_encoder; 1728 struct drm_connector *connector; 1729 struct radeon_connector *radeon_connector; 1730 bool first = true; 1731 u32 src_v = 1, dst_v = 1; 1732 u32 src_h = 1, dst_h = 1; 1733 1734 radeon_crtc->h_border = 0; 1735 radeon_crtc->v_border = 0; 1736 1737 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1738 if (encoder->crtc != crtc) 1739 continue; 1740 radeon_encoder = to_radeon_encoder(encoder); 1741 connector = radeon_get_connector_for_encoder(encoder); 1742 radeon_connector = to_radeon_connector(connector); 1743 1744 if (first) { 1745 /* set scaling */ 1746 if (radeon_encoder->rmx_type == RMX_OFF) 1747 radeon_crtc->rmx_type = RMX_OFF; 1748 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || 1749 mode->vdisplay < radeon_encoder->native_mode.vdisplay) 1750 radeon_crtc->rmx_type = radeon_encoder->rmx_type; 1751 else 1752 radeon_crtc->rmx_type = RMX_OFF; 1753 /* copy native mode */ 1754 memcpy(&radeon_crtc->native_mode, 1755 &radeon_encoder->native_mode, 1756 sizeof(struct drm_display_mode)); 1757 src_v = crtc->mode.vdisplay; 1758 dst_v = radeon_crtc->native_mode.vdisplay; 1759 src_h = crtc->mode.hdisplay; 1760 dst_h = radeon_crtc->native_mode.hdisplay; 1761 1762 /* fix up for overscan on hdmi */ 1763 if (ASIC_IS_AVIVO(rdev) && 1764 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 1765 ((radeon_encoder->underscan_type == UNDERSCAN_ON) || 1766 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && 1767 drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 1768 is_hdtv_mode(mode)))) { 1769 if (radeon_encoder->underscan_hborder != 0) 1770 radeon_crtc->h_border = radeon_encoder->underscan_hborder; 1771 else 1772 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; 1773 if (radeon_encoder->underscan_vborder != 0) 1774 radeon_crtc->v_border = radeon_encoder->underscan_vborder; 1775 else 1776 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; 1777 radeon_crtc->rmx_type = RMX_FULL; 1778 src_v = crtc->mode.vdisplay; 1779 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); 1780 src_h = crtc->mode.hdisplay; 1781 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); 1782 } 1783 first = false; 1784 } else { 1785 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { 1786 /* WARNING: Right now this can't happen but 1787 * in the future we need to check that scaling 1788 * are consistent across different encoder 1789 * (ie all encoder can work with the same 1790 * scaling). 1791 */ 1792 DRM_ERROR("Scaling not consistent across encoder.\n"); 1793 return false; 1794 } 1795 } 1796 } 1797 if (radeon_crtc->rmx_type != RMX_OFF) { 1798 fixed20_12 a, b; 1799 a.full = dfixed_const(src_v); 1800 b.full = dfixed_const(dst_v); 1801 radeon_crtc->vsc.full = dfixed_div(a, b); 1802 a.full = dfixed_const(src_h); 1803 b.full = dfixed_const(dst_h); 1804 radeon_crtc->hsc.full = dfixed_div(a, b); 1805 } else { 1806 radeon_crtc->vsc.full = dfixed_const(1); 1807 radeon_crtc->hsc.full = dfixed_const(1); 1808 } 1809 return true; 1810 } 1811 1812 /* 1813 * Retrieve current video scanout position of crtc on a given gpu, and 1814 * an optional accurate timestamp of when query happened. 1815 * 1816 * \param dev Device to query. 1817 * \param crtc Crtc to query. 1818 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 1819 * For driver internal use only also supports these flags: 1820 * 1821 * USE_REAL_VBLANKSTART to use the real start of vblank instead 1822 * of a fudged earlier start of vblank. 1823 * 1824 * GET_DISTANCE_TO_VBLANKSTART to return distance to the 1825 * fudged earlier start of vblank in *vpos and the distance 1826 * to true start of vblank in *hpos. 1827 * 1828 * \param *vpos Location where vertical scanout position should be stored. 1829 * \param *hpos Location where horizontal scanout position should go. 1830 * \param *stime Target location for timestamp taken immediately before 1831 * scanout position query. Can be NULL to skip timestamp. 1832 * \param *etime Target location for timestamp taken immediately after 1833 * scanout position query. Can be NULL to skip timestamp. 1834 * 1835 * Returns vpos as a positive number while in active scanout area. 1836 * Returns vpos as a negative number inside vblank, counting the number 1837 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 1838 * until start of active scanout / end of vblank." 1839 * 1840 * \return Flags, or'ed together as follows: 1841 * 1842 * DRM_SCANOUTPOS_VALID = Query successful. 1843 * DRM_SCANOUTPOS_INVBL = Inside vblank. 1844 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 1845 * this flag means that returned position may be offset by a constant but 1846 * unknown small number of scanlines wrt. real scanout position. 1847 * 1848 */ 1849 int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 1850 unsigned int flags, int *vpos, int *hpos, 1851 ktime_t *stime, ktime_t *etime, 1852 const struct drm_display_mode *mode) 1853 { 1854 u32 stat_crtc = 0, vbl = 0, position = 0; 1855 int vbl_start, vbl_end, vtotal, ret = 0; 1856 bool in_vbl = true; 1857 1858 struct radeon_device *rdev = dev->dev_private; 1859 1860 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 1861 1862 /* Get optional system timestamp before query. */ 1863 if (stime) 1864 *stime = ktime_get(); 1865 1866 if (ASIC_IS_DCE4(rdev)) { 1867 if (pipe == 0) { 1868 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1869 EVERGREEN_CRTC0_REGISTER_OFFSET); 1870 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1871 EVERGREEN_CRTC0_REGISTER_OFFSET); 1872 ret |= DRM_SCANOUTPOS_VALID; 1873 } 1874 if (pipe == 1) { 1875 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1876 EVERGREEN_CRTC1_REGISTER_OFFSET); 1877 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1878 EVERGREEN_CRTC1_REGISTER_OFFSET); 1879 ret |= DRM_SCANOUTPOS_VALID; 1880 } 1881 if (pipe == 2) { 1882 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1883 EVERGREEN_CRTC2_REGISTER_OFFSET); 1884 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1885 EVERGREEN_CRTC2_REGISTER_OFFSET); 1886 ret |= DRM_SCANOUTPOS_VALID; 1887 } 1888 if (pipe == 3) { 1889 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1890 EVERGREEN_CRTC3_REGISTER_OFFSET); 1891 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1892 EVERGREEN_CRTC3_REGISTER_OFFSET); 1893 ret |= DRM_SCANOUTPOS_VALID; 1894 } 1895 if (pipe == 4) { 1896 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1897 EVERGREEN_CRTC4_REGISTER_OFFSET); 1898 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1899 EVERGREEN_CRTC4_REGISTER_OFFSET); 1900 ret |= DRM_SCANOUTPOS_VALID; 1901 } 1902 if (pipe == 5) { 1903 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1904 EVERGREEN_CRTC5_REGISTER_OFFSET); 1905 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1906 EVERGREEN_CRTC5_REGISTER_OFFSET); 1907 ret |= DRM_SCANOUTPOS_VALID; 1908 } 1909 } else if (ASIC_IS_AVIVO(rdev)) { 1910 if (pipe == 0) { 1911 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); 1912 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); 1913 ret |= DRM_SCANOUTPOS_VALID; 1914 } 1915 if (pipe == 1) { 1916 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); 1917 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); 1918 ret |= DRM_SCANOUTPOS_VALID; 1919 } 1920 } else { 1921 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ 1922 if (pipe == 0) { 1923 /* Assume vbl_end == 0, get vbl_start from 1924 * upper 16 bits. 1925 */ 1926 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & 1927 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1928 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ 1929 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1930 stat_crtc = RREG32(RADEON_CRTC_STATUS); 1931 if (!(stat_crtc & 1)) 1932 in_vbl = false; 1933 1934 ret |= DRM_SCANOUTPOS_VALID; 1935 } 1936 if (pipe == 1) { 1937 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & 1938 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1939 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1940 stat_crtc = RREG32(RADEON_CRTC2_STATUS); 1941 if (!(stat_crtc & 1)) 1942 in_vbl = false; 1943 1944 ret |= DRM_SCANOUTPOS_VALID; 1945 } 1946 } 1947 1948 /* Get optional system timestamp after query. */ 1949 if (etime) 1950 *etime = ktime_get(); 1951 1952 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 1953 1954 /* Decode into vertical and horizontal scanout position. */ 1955 *vpos = position & 0x1fff; 1956 *hpos = (position >> 16) & 0x1fff; 1957 1958 /* Valid vblank area boundaries from gpu retrieved? */ 1959 if (vbl > 0) { 1960 /* Yes: Decode. */ 1961 ret |= DRM_SCANOUTPOS_ACCURATE; 1962 vbl_start = vbl & 0x1fff; 1963 vbl_end = (vbl >> 16) & 0x1fff; 1964 } 1965 else { 1966 /* No: Fake something reasonable which gives at least ok results. */ 1967 vbl_start = mode->crtc_vdisplay; 1968 vbl_end = 0; 1969 } 1970 1971 /* Called from driver internal vblank counter query code? */ 1972 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1973 /* Caller wants distance from real vbl_start in *hpos */ 1974 *hpos = *vpos - vbl_start; 1975 } 1976 1977 /* Fudge vblank to start a few scanlines earlier to handle the 1978 * problem that vblank irqs fire a few scanlines before start 1979 * of vblank. Some driver internal callers need the true vblank 1980 * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 1981 * 1982 * The cause of the "early" vblank irq is that the irq is triggered 1983 * by the line buffer logic when the line buffer read position enters 1984 * the vblank, whereas our crtc scanout position naturally lags the 1985 * line buffer read position. 1986 */ 1987 if (!(flags & USE_REAL_VBLANKSTART)) 1988 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 1989 1990 /* Test scanout position against vblank region. */ 1991 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 1992 in_vbl = false; 1993 1994 /* In vblank? */ 1995 if (in_vbl) 1996 ret |= DRM_SCANOUTPOS_IN_VBLANK; 1997 1998 /* Called from driver internal vblank counter query code? */ 1999 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 2000 /* Caller wants distance from fudged earlier vbl_start */ 2001 *vpos -= vbl_start; 2002 return ret; 2003 } 2004 2005 /* Check if inside vblank area and apply corrective offsets: 2006 * vpos will then be >=0 in video scanout area, but negative 2007 * within vblank area, counting down the number of lines until 2008 * start of scanout. 2009 */ 2010 2011 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 2012 if (in_vbl && (*vpos >= vbl_start)) { 2013 vtotal = mode->crtc_vtotal; 2014 *vpos = *vpos - vtotal; 2015 } 2016 2017 /* Correct for shifted end of vbl at vbl_end. */ 2018 *vpos = *vpos - vbl_end; 2019 2020 return ret; 2021 } 2022